SCC2692AE1N40 [NXP]
Dual asynchronous receiver/transmitter DUART; 双重异步接收器/发送器DUART
| 型号： | SCC2692AE1N40 |
| 厂家： | 
NXP |
| 描述： | Dual asynchronous receiver/transmitter DUART |
| 文件： | 总30页 (文件大小：212K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
SCC2692
Dual asynchronous receiver/transmitter
(DUART)
Product specification
1998 Sep 04
Supersedes data of 1998 Feb 19
IC19 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCC2692
– Non-standard user-defined rate derived from programmable
counter/timer
DESCRIPTION
The Philips Semiconductors SCC2692 Dual Universal
Asynchronous Receiver/Transmitter (DUART) which is compatible
with the SCN2681. It is a single-chip CMOS-LSI communications
device that provides two full-duplex asynchronous
receiver/transmitter channels in a single package. It interfaces
directly with microprocessors and may be used in a polled or
interrupt driven system.
– External 1X or 16X clock
• Parity, framing, and overrun error detection
• False start bit detection
• Line break detection and generation
• Programmable channel mode
– Normal (full-duplex)
The operating mode and data format of each channel can be
programmed independently. Additionally, each receiver and
transmitter can select its operating speed as one of eighteen fixed
baud rates, a 16X clock derived from a programmable counter/timer,
or an external 1X or 16X clock. The baud rate generator and
counter/timer can operate directly from a crystal or from external
clock inputs. The ability to independently program the operating
speed of the receiver and transmitter make the DUART particularly
attractive for dual-speed channel applications such as clustered
terminal systems.
– Automatic echo
– Local loopback
– Remote loopback
– Multidrop mode (also called ‘wake-up’ or ‘9-bit’)
• Multi-function 7-bit input port
– Can serve as clock or control inputs
– Change of state detection on four inputs
– Inputs have typically >100k pull-up resistors
Each receiver is quadruply buffered to minimize the potential of
receiver over-run or to reduce interrupt overhead in interrupt driven
systems. In addition, a flow control capability is provided to disable a
remote DUART transmitter when the receiver buffer is full.
• Multi-function 8-bit output port
– Individual bit set/reset capability
– Outputs can be programmed to be status/interrupt signals
Also provided on the SCC2692 are a multipurpose 7-bit input port
and a multipurpose 8-bit output port. These can be used as general
purpose I/O ports or can be assigned specific functions (such as
clock inputs or status/interrupt outputs) under program control.
• Versatile interrupt system
– Single interrupt output with eight maskable interrupting
conditions
– Output port can be configured to provide a total of up to six
separate wire-ORable interrupt outputs
FEATURES
• Maximum data transfer rates: 1X – 1MB/sec, 16X – 125kB/sec
• Automatic wake-up mode for multidrop applications
• Start-end break interrupt/status
• Dual full-duplex asynchronous receiver/transmitters
• Quadruple buffered receiver data register
• Programmable data format
– 5 to 8 data bits plus parity
• Detects break which originates in the middle of a character
• On-chip crystal oscillator
– Odd, even, no parity or force parity
– 1, 1.5 or 2 stop bits programmable in 1/16-bit increments
• Power down mode
• 16-bit programmable Counter/Timer
• Receiver timeout mode
• Programmable baud rate for each receiver and transmitter
selectable from:
• Commercial and industrial temperature range versions
• TTL compatible
– 22 fixed rates: 50 to 115.2k baud
– Non-standard rates to 115.2Kb
• Single +5V power supply
ORDERING INFORMATION
COMMERCIAL
INDUSTRIAL
V = +5V +10%,
CC
DESCRIPTION
DWG #
V
CC
= +5V +10%,
T
A
= 0 to +70°C
T = -40 to +85°C
A
1
40-Pin Plastic Dual In-Line Package (DIP)
SCC2692AC1N40
SCC2692AC1N28
SCC2692AC1A44
SCC2692AC1B44
SCC2692AE1N40
SCC2692AE1N28
SCC2692AE1A44
SCC2692AE1B44
SOT129-1
SOT117-1
SOT187-2
SOT307–2
1
28-Pin Plastic Dual In-Line Package (DIP)
44-Pin Plastic Leaded Chip Carrier (PLCC) Package
44–Pin Plastic Quad Flat Pack (PQFP)
NOTE:
1. For availability, please contact factory.
2
1998 Sep 04
853–0895 19971
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCC2692
INDEX
CORNER
A0
IP3
A1
1
2
3
4
5
40
V
CC
6
40
1
39 IP4
38 IP5
37 IP6
36 IP2
44
34
7
39
1
33
A0
A1
1
2
3
4
5
28 V
CC
IP1
A2
27 IP2
PLCC
PQFP
CEN
A2
26
A3
IP0
6
7
8
9
35 CEN
34 RESET
33 X2
A3
25 RESET
24 X2
11
23
22
29
17
WRN
12
WRN
RDN
18
28
TOP VIEW
RDN
RxDB
TxDB
OP1
6
7
8
9
23 X1/CLK
22 RxDA
21 TxDA
20 OP0
19 D0
32 X1/CLK
31 RxDA
30 TxDA
29 OP0
TOP VIEW
RxDB 10
TxDB 11
OP1 12
DIP
DIP
PIN/FUNCTION
PIN/FUNCTION
PIN/FUNCTION
PIN/FUNCTION
1
2
NC
A0
IP3
A1
IP1
A2
A3
IP0
WRN
23 NC
24 INTRN
25 D6
26 D4
27 D2
1
2
A3
IP0
23 N/C
24 OP6
25 OP4
26 OP2
27 OP0
28 TxDA
29 RxDA
30 X1/CLK
31 X2
3
4
5
6
7
8
9
3
4
5
6
7
8
9
WRN
RDN
RxDB
TxDB
OP1
OP3
OP5
D1 10
D3 11
D5 12
OP3 13
OP5 14
OP7 15
D1 16
28 OP2
27 OP4
26 OP6
25 D0
18 D2
28 D0
29 OP6
30 OP4
31 OP2
32 OP0
33 TXDA
34 NC
17 D4
D7 13
GND 14
16 D6
10 RDN
11 RXDB
12 NC
10 OP7
11 N/C
12 D1
32 RESET
33 CEN
34 IP2
15 INTRN
D3 17
24 D2
13 TXDB
14 OP1
15 OP3
16 OP5
17 OP7
18 D1
19 D3
20 D5
21 D7
22 GND
35 RXDA
36 X1/CLK
37 X2
38 RESET
39 CEN
40 IP2
41 IP6
42 IP5
43 IP4
13 D3
14 D5
15 D7
16 GND
17 GND
18 INTRN
19 D6
20 D4
21 D2
35 IP6
36 IP5
37 IP4
D5 18
23 D4
38
39
V
V
D7 19
22 D6
CC
CC
40 A0
41 IP3
42 A1
43 IP1
44 A2
GND 20
21 INTRN
44 V
22 D0
CC
SD00131
Figure 1. Pin Configurations
1
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
Note 4
UNIT
°C
2
T
A
Operating ambient temperature range
T
Storage temperature range
-65 to +150
-0.5 to +7.0
°C
STG
3
V
Voltage from V to GND
V
CC
CC
3
V
Voltage from any pin to GND
Package power dissipation
Package power dissipation
Package power dissipation
Package power dissipation
Derating factor above 25°C
Derating factor above 25°C
Derating factor above 25°C
Derating factor above 25°C
-0.5 to V +0.5
V
S
CC
DIP28
DIP40
1.22
2.97
2.66
2.08
19
W
W
P
D
PLCC44
PQFP44
DIP28
W
W
mW/°C
mW/°C
mW/°C
mW/°C
DIP40
24
PLCC44
PQFP44
21
17
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not
implied.
2. For operating at elevated temperatures, the device must be derated.
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Parameters are valid over specified temperature range.
3
1998 Sep 04
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCC2692
BLOCK DIAGRAM
8
CHANNEL A
D0–D7
BUS BUFFER
TRANSMIT
TxDA
RxDA
HOLDING REG
TRANSMIT
SHIFT REGISTER
OPERATION CONTROL
RDN
RECEIVE
HOLDING REG (3)
WRN
CEN
ADDRESS
DECODE
4
RECEIVE
SHIFT REGISTER
A0–A3
RESET
R/W CONTROL
MRA1, 2
CRA
SRA
INTERRUPT CONTROL
TxDB
RxDB
INTRN
IMR
ISR
CHANNEL B
(AS ABOVE)
INPUT PORT
CHANGE OF
STATE
DETECTORS (4)
TIMING
7
IP0-IP6
BAUD RATE
GENERATOR
IPCR
ACR
CLOCK
SELECTORS
COUNTER/
TIMER
OUTPUT PORT
FUNCTION
SELECT LOGIC
8
OP0-OP7
X1/CLK
X2
XTAL OSC
OPCR
OPR
CSRA
CSRB
ACR
U
CTLR
CTLR
V
CC
GND
SD00132
Figure 2. Block Diagram
4
1998 Sep 04
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCC2692
PIN DESCRIPTION
APPLICABLE
SYMBOL
TYPE
NAME AND FUNCTION
40,44
28
D0-D7
X
X
I/O
Data Bus: Bidirectional 3-State data bus used to transfer commands, data and status between the
DUART and the CPU. D0 is the least significant bit.
CEN
X
X
I
Chip Enable: Active-Low input signal. When Low, data transfers between the CPU and the DUART
are enabled on D0-D7 as controlled by the WRN, RDN and A0-A3 inputs. When High, places the
D0-D7 lines in the 3-State condition.
WRN
RDN
X
X
X
X
I
I
Write Strobe: When Low and CEN is also Low, the contents of the data bus are loaded into the
addressed register. The transfer occurs on the rising edge of the signal.
Read Strobe: When Low and CEN is also Low, causes the contents of the addressed register to be
presented on the data bus. The read cycle begins on the falling edge of RDN.
A0-A3
X
X
X
X
I
I
Address Inputs: Select the DUART internal registers and ports for read/write operations.
RESET
Reset: A High level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OP0-OP7 in
the High state, stops the counter/timer, and puts Channels A and B in the inactive state, with the TxDA
and TxDB outputs in the mark (High) state. Resets Test modes, MR pointer set to MR1.
INTRN
X1/CLK
X2
X
X
X
X
X
X
X
X
X
X
X
X
O
I
Interrupt Request: Active-Low, open-drain, output which signals the CPU that one or more of the
eight maskable interrupting conditions are true.
Crystal 1: Crystal connection or an external clock input. A crystal of a clock the appropriate frequency
(nominally 3.6864 MHz) must be supplied at all times. For crystal connections see Figure 7, Clock Timing.
Crystal 2: Crystal connection. See Figure 7. If a crystal is not used it is best to keep this pin not
connected although it is permissible to ground it.
Channel A Receiver Serial Data Input: The least significant bit is received first. “Mark” is High,
“space” is Low.
Channel B Receiver Serial Data Input: The least significant bit is received first. “Mark” is High,
“space” is Low.
Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is
held in the “mark” condition when the transmitter is disabled, idle or when operating in local loopback
mode. “Mark” is High, “space” is Low.
I
RxDA
RxDB
TxDA
I
I
O
TxDB
X
X
O
Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This output
is held in the ‘mark’ condition when the transmitter is disabled, idle, or when operating in local
loopback mode. ‘Mark’ is High, ‘space’ is Low.
OP0
OP1
OP2
OP3
X
X
X
X
X
X
O
O
O
O
Output 0: General purpose output or Channel A request to send (RTSAN, active-Low). Can be
deactivated automatically on receive or transmit.
Output 1: General purpose output or Channel B request to send (RTSBN, active-Low). Can be
deactivated automatically on receive or transmit.
Output 2: General purpose output, or Channel A transmitter 1X or 16X clock output, or Channel A
receiver 1X clock output.
Output 3: General purpose output or open-drain, active-Low counter/timer output or Channel B
transmitter 1X clock output, or Channel B receiver 1X clock output.
OP4
OP5
OP6
OP7
IP0
X
X
X
X
X
O
O
O
O
I
Output 4: General purpose output or Channel A open-drain, active-Low, RxRDYAN/FFULLAN output.
Output 5: General purpose output or Channel B open-drain, active-Low, RxRDYBN/FFULLBN output.
Output 6: General purpose output or Channel A open-drain, active-Low, TxRDYAN output.
Output 7: General purpose output, or Channel B open-drain, active-Low, TxRDYBN output.
Input 0: General purpose input or Channel A clear to send active-Low input (CTSAN). Pin has an
internal V pull-up device supplying 1 to 4 mA of current.
CC
IP1
IP2
IP3
X
X
X
I
I
I
Input 1: General purpose input or Channel B clear to send active-Low input (CTSBN). Pin has an
internal V pull-up device supplying 1 to 4 mA of current.
CC
X
Input 2: General purpose input or counter/timer external clock input. Pin has an internal V pull-up
CC
device supplying 1 to 4 mA of current.
Input 3: General purpose input or Channel A transmitter external clock input (TxCA). When the
external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the
clock. Pin has an internal V pull-up device supplying 1 to 4 mA of current.
CC
IP4
IP5
IP6
X
X
X
I
I
I
Input 4: General purpose input or Channel A receiver external clock input (RxCA). When the external
clock is used by the receiver, the received data is sampled on the rising edge of the clock. Pin has an
internal V pull-up device supplying 1 to 4 mA of current.
CC
Input 5: General purpose input or Channel B transmitter external clock input (TxCB). When the
external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the
clock. Pin has an internal V pull-up device supplying 1 to 4 mA of current.
CC
Input 6: General purpose input or Channel B receiver external clock input (RxCB). When the external
clock is used by the receiver, the received data is sampled on the rising edge of the clock. Pin has an
internal V pull-up device supplying 1 to 4 mA of current.
CC
V
X
X
X
X
I
I
Power Supply: +5V supply input.
CC
GND
Ground
5
1998 Sep 04
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCC2692
1, 2, 3
DC ELECTRICAL CHARACTERISTICS
LIMITS
Typ
SYM-
BOL
PARAMETER
TEST CONDITIONS
UNIT
Max
Min
V
V
V
V
Input low voltage
0.8
V
V
V
V
IL
6
Input high voltage (except X1/CLK)
Input high voltage (except X1/CLK)
Input high voltage (X1/CLK)
2.0
2.5
IH
IH
IH
7
0.8 V
CC
V
V
Output low voltage
0.4
V
V
I
= 2.4mA
OL
OL
4
Output high voltage (except OD outputs)
V
CC
-0.5
I
= -400µA
OH
OH
I
X1/CLK input current - power down
X1/CLK input low current - operating
X1/CLK input high current - operating
-10
+10
0
75
µA
µA
µA
V
= 0 to V
IX1PD
IN
CC
I
I
V
IN
= 0
-75
0
ILX1
V
= V
IHX1
IN
CC
I
I
I
I
X2 output high current - operating
0
+75
-1
0
µA
mA
µA
V
V
= V , X1 = 0
CC
OHX2
OUT
X2 output high short circuit current - operating
X2 output low current - operating
X2 output low short circuit current - operating and power down
V
= 0, X1 = 0
-10
-75
1
OHX2S
OLX2
OUT
= 0, X1 = V
OUT
CC
V
OUT
= V , X1 = V
CC
10
mA
OLX2S
CC
Input leakage current:
All except input port pins
Input port pins
I
V
V
= 0 to V
= 0 to V
-10
-20
+10
+10
µA
µA
I
IN
IN
V
CC
CC
I
I
Output off current high, 3-state data bus
Output off current low, 3-state data bus
= V
CC
10
µA
µA
OZH
IN
V
IN
= 0V
-10
-10
OZL
I
I
Open-drain output low current in off-state
Open-drain output high current in off-state
V
IN
= 0
µA
µA
ODL
V
= V
CC
10
ODH
IN
5
Power supply current
I
Operating mode
Power down mode
CMOS input levels
CMOS input levels
10
10
mA
CC
8
2
mA
NOTES:
1. Parameters are valid over specified temperature range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 2.4V with a transition time of 5ns
maximum. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of 0.8V and 2.0V and
output voltages of 0.8V and 2.0V, as appropriate.
3. Typical values are at +25°C, typical supply voltages, and typical processing parameters.
4. Test conditions for outputs: C = 150pF, except interrupt outputs. Test conditions for interrupt outputs: C = 50pF, R = 2.7KΩ to V
.
L
L
L
CC
5. All outputs are disconnected. Inputs are switching between CMOS levels of V -0.2V and V + 0.2V.
CC
SS
6. T > 0°C
A
7. T < 0°C
A
8. See UART application note for 5µA.
1, 2, 4
AC CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
UNIT
3
Min
Typ
Max
Reset Timing (See Figure 3)
t
RESET pulse width
200
ns
RES
5
Bus Timing (See Figure 4)
t
t
t
t
t
t
t
t
t
t
t
t
A0-A3 setup time to RDN, WRN Low
A0-A3 hold time from RDN, WRN Low
CEN setup time to RDN, WRN Low
CEN hold time from RDN, WRN High
WRN, RDN pulse width
10
100
0
0
225
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AS
AH
CS
CH
RW
DD
DA
DF
DI
Data valid after RDN Low
RDN Low to data bus active
175
125
7
15
Data bus floating after RDN High
7
RDN High to data bus invalid
20
100
20
Data setup time before WRN High
Data hold time after WRN High
High time between reads and/or writes
DS
DH
RWD
5, 6
200
6
1998 Sep 04
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCC2692
1, 2, 4
AC CHARACTERISTICS (Continued)
LIMITS
SYMBOL
Port Timing (See Figure 5)
PARAMETER
UNIT
Max
3
Min
Typ
5
Port input setup time before RDN Low
Port input hold time after RDN High
OP output valid from WRN High
0
0
ns
ns
ns
t
t
t
PS
PH
PD
400
n
Interrupt Timing (See Figure 6)
INTRN (or OP3-OP7 when used as interrupts) negated from:
Read RHR (RxRDY/FFULL interrupt)
Write THR (TxRDY interrupt)
Reset command (break change interrupt)
Stop C/T command (counter interrupt)
Read IPCR (input port change interrupt)
Write IMR (clear of interrupt mask bit)
300
300
300
300
300
300
ns
ns
ns
ns
ns
ns
9
t
IR
Clock Timing (See Figure 7)
t
100
ns
X1/CLK High or Low time
CLK
CLK
10
f
t
f
t
f
X1/CLK frequency
0
100
0
220
0
0
220
0
3.6864
4
4
MHz
ns
MHz
ns
MHz
MHz
ns
MHz
MHz
CTCLK (IP2) High or Low time
CTCLK (IP2) frequency
RxC High or Low time
CTC
CTC
RX
8
8
RxC frequency
(16X)
(1X)
2
1
RX
t
f
TxC High or Low time
TxC frequency
TX
8
(16X)
(1X)
1
1
TX
0
Transmitter Timing (See Figure 8)
t
t
TxD output delay from TxC external clock input on IP pin
Output delay from TxC low at OP pin to TxD data output
350
150
ns
ns
TXD
0
TCS
Receiver Timing (See Figure 9)
t
t
RxD data setup time before RxC high at external clock input on IP pin
RxD data hold time after RxC high at external clock input on IP pin
240
200
ns
ns
RXS
RXH
NOTES:
1. Parameters are valid over specified temperature range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 2.4V with a transition time of 5ns
maximum. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of 0.8V and 2.0V and
output voltages of 0.8V and 2.0V, as appropriate.
3. Typical values are at +25°C, typical supply voltages, and typical processing parameters.
4. Test conditions for outputs: C = 150pF, except interrupt outputs. Test conditions for interrupt outputs: C = 50pF, R = 2.7KΩ to V .
L
L
L
CC
5. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the ‘strobing’ input. CEN
and RDN (also CEN and WRN) are ORed internally. As a consequence, the signal asserted last initiates the cycle and the signal negated
first terminates the cycle.
6. If CEN is used as the ‘strobing’ input, the parameter defines the minimum High times between one CEN and the next. The RDN signal must
be negated for t
to guarantee that any status register changes are valid.
RWD
7. Guaranteed by characterization of sample units.
8. Minimum frequencies are not tested but are guaranteed by design.
9. 325ns maximum for T > 70°C.
A
10.Operation to 0MHz is assured by design. Minimum test frequency is 2.0MHz. Crystal frequencies 2 to 4 MHz.
7
1998 Sep 04
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCC2692
BLOCK DIAGRAM
• In the timer mode it generates a square wave.
• In the counter mode it generates a time delay.
The SCC2692 DUART consists of the following eight major sections:
data bus buffer, operation control, interrupt control, timing,
communications Channels A and B, input port and output port. Refer
to the Block Diagram.
• In the time out mode it monitors the receiver data flow and signals
data flow has paused. In the time out mode the receiver controls
the starting/stopping of the C/T.
Data Bus Buffer
The data bus buffer provides the interface between the external and
internal data buses. It is controlled by the operation control block to
allow read and write operations to take place between the controlling
CPU and the DUART.
The counter operates as a down counter and sets its output bit in
the ISR (Interrupt Status Register) each time it passes through 0.
The output of the counter/timer may be seen on one of the OP pins
or as an Rx or Tx clock.
The Timer/Counter is controlled with six (6) “commands”; Start C/T,
Stop C/T, write C/T, preset registers, read C/T value, set or reset
time out mode.
Operation Control
The operation control logic receives operation commands from the
CPU and generates appropriate signals to internal sections to
control device operation. It contains address decoding and read and
write circuits to permit communications with the microprocessor via
the data bus buffer.
Please see the detail of the commands under the Counter/Timer
register descriptions.
Communications Channels A and B
Interrupt Control
Each communications channel of the SCC2692 comprises a
full-duplex asynchronous receiver/transmitter (UART). The operating
frequency for each receiver and transmitter can be selected
independently from the baud rate generator, the counter/timer, or
from an external input.
A single active-Low interrupt output (INTRN) is provided which is
activated upon the occurrence of any of eight internal events.
Associated with the interrupt system are the Interrupt Mask Register
(IMR) and the Interrupt Status Register (ISR). The IMR can be
programmed to select only certain conditions to cause INTRN to be
asserted. The ISR can be read by the CPU to determine all currently
active interrupting conditions.
The transmitter accepts parallel data from the CPU, converts it to a
serial bit stream, inserts the appropriate start, stop, and optional
parity bits and outputs a composite serial stream of data on the TxD
output pin. The receiver accepts serial data on the RxD pin,
converts this serial input to parallel format, checks for start bit, stop
bit, parity bit (if any), or break condition and sends an assembled
character to the CPU.
Outputs OP3-OP7 can be programmed to provide discrete interrupt
outputs for the transmitter, receivers, and counter/timer.
TIMING CIRCUITS
Input Port
Crystal Clock
The inputs to this unlatched 7-bit port can be read by the CPU by
performing a read operation at address H’D’. A High input results in
a logic 1 while a Low input results in a logic 0. D7 will always read
as a logic 1. The pins of this port can also serve as auxiliary inputs
to certain portions of the DUART logic.
The timing block consists of a crystal oscillator, a baud rate
generator, a programmable 16-bit counter/timer, and four clock
selectors. The crystal oscillator operates directly from a crystal
connected across the X1/CLK and X2 inputs. If an external clock of
the appropriate frequency is available, it may be connected to
X1/CLK. The clock serves as the basic timing reference for the Baud
Rate Generator (BRG), the counter/timer, and other internal circuits.
A clock signal within the limits specified in the specifications section
of this data sheet must always be supplied to the DUART.
Four change-of-state detectors are provided which are associated
with inputs IP3, IP2, IP1 and IP0. A High-to-Low or Low-to-High
transition of these inputs, lasting longer than 25 - 50µs, will set the
corresponding bit in the input port change register. The bits are
cleared when the register is read by the CPU. Any change-of-state
can also be programmed to generate an interrupt to the CPU.
If an external clock is used instead of a crystal, X1 should be driven
using a configuration similar to the one in Figure 7.
The input port pulse detection circuitry uses a 38.4KHz sampling
clock derived from one of the baud rate generator taps. This results
in a sampling period of slightly more than 25µs (this assumes that
the clock input is 3.6864MHz). The detection circuitry, in order to
guarantee that a true change in level has occurred, requires two
successive samples at the new logic level be observed. As a
consequence, the minimum duration of the signal change is 25µs if
the transition occurs “coincident with the first sample pulse”. The
50µs time refers to the situation in which the change-of-state is “just
missed” and the first change-of-state is not detected until 25µs later.
All the IP pins have a small pull-up device that will source 1 to 4 mA
BRG
The baud rate generator operates from the oscillator or external
clock input and is capable of generating 23 commonly used data
communications baud rates ranging from 50 to 130.4K baud. A
3.6864MHz crystal or external clock must be used to get the
standard baud rate. The clock outputs from the BRG are at 16X the
actual baud rate. The counter/timer can be used as a timer to
produce a 16X clock for any other baud rate by counting down the
crystal clock or an external clock. The four clock selectors allow the
independent selection, for each receiver and transmitter, of any of
these baud rates or external timing signal.
of current from V . These pins do not require pull-up devices or
CC
V
CC
connections if they are not used.
Counter/Timer (C/T)
Output Port
The counter timer is a 16 bit programmable divider that operates
one of three modes: Counter, Timer or Time Out mode. In all three
modes it uses the 16-bit value loaded to the CTUR and CTLR
registers. (Counter timer upper and lower preset registers).
The output port pins may be controlled by the OPR, OPCR, MR and
CR registers. Via appropriate programming they may be just another
parallel port to external circuits, or they may represent many internal
8
1998 Sep 04
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCC2692
conditions of the UART. When this 8-bit port is used as a general
purpose output, the pins so defined will assume the compliment of
the associated bit in the Output Port Register (OPR). OPR(n) = 1
results in OP(n) = Low and vice versa. Bits of the OPR can be
individually set and reset. A bit is set by performing a write operation
at address H’E’ with the accompanying data specifying the bits to be
reset (1 = set, 0 = no change). Likewise, a bit is reset by a write at
address H’F’ with the accompanying data specifying the bits to be
reset (1 = reset, 0 = no change).
(if any) are completely transmitted, if the transmitter has been
disabled.
Receiver
The SCC2692 is conditioned to receive data when enabled through
the command register. The receiver looks for a High-to-Low
(mark-to-space) transition of the start bit on the RxD input pin. If a
transition is detected, the state of the RxD pin is sampled each 16X
clock for 7-1/2 clocks (16X clock mode) or at the next rising edge of
the bit time clock (1X clock mode). If RxD is sampled High, the start
bit is invalid and the search for a valid start bit begins again. If RxD
is still Low, a valid start bit is assumed and the receiver continues to
sample the input at one bit time intervals at the theoretical center of
the bit, until the proper number of data bits and parity bit (if any)
have been assembled, and one stop bit has been detected. The
least significant bit is received first. The data is then transferred to
the Receive Holding Register (RHR) and the RxRDY bit in the SR is
set to a 1. This condition can be programmed to generate an
interrupt at OP4 or OP5 and INTRN. If the character length is less
than 8 bits, the most significant unused bits in the RHR are set to
zero.
Outputs can be also individually assigned specific functions by
appropriate programming of the Channel A mode registers (MR1A,
MR2A), the Channel B mode registers (MR1B, MR2B), and the
Output Port Configuration Register (OPCR).
Output ports are driven high on hardware reset. Please note that
these pins drive both high and low. HOWEVER when they are
programmed to represent interrupt type functions (such as receiver
ready, transmitter ready or counter/timer ready) they will be switched
to an open drain configuration in which case an external pull-up
device would be required.
After the stop bit is detected, the receiver will immediately look for
the next start bit. However, if a non-zero character was received
without a stop bit (framing error) and RxD remains Low for one half
of the bit period after the stop bit was sampled, then the receiver
operates as if a new start bit transition had been detected at that
point (one-half bit time after the stop bit was sampled).
OPERATION
Transmitter
The SCC2692 is conditioned to transmit data when the transmitter is
enabled through the command register. The SCC2692 indicates to
the CPU that it is ready to accept a character by setting the TxRDY
bit in the status register. This condition can be programmed to
generate an interrupt request at OP6 or OP7 and INTRN. When a
character is loaded into the Transmit Holding Register (THR), the
above conditions are negated. Data is transferred from the holding
register to transmit shift register when it is idle or has completed
transmission of the previous character. The TxRDY conditions are
then asserted again which means one full character time of buffering
is provided. Characters cannot be loaded into the THR while the
transmitter is disabled.
The parity error, framing error, and overrun error (if any) are strobed
into the SR at the received character boundary, before the RxRDY
status bit is set. If a break condition is detected (RxD is Low for the
entire character including the stop bit), a character consisting of all
zeros will be loaded into the RHR and the received break bit in the
SR is set to 1. The RxD input must return to high for two (2) clock
edges of the X1 crystal clock for the receiver to recognize the end of
the break condition and begin the search for a start bit. This will
usually require a high time of one X1 clock period or 3 X1
edges since the clock of the controller is not synchronous to
the X1 clock.
The transmitter converts the parallel data from the CPU to a serial
bit stream on the TxD output pin. It automatically sends a start bit
followed by the programmed number of data bits, an optional parity
bit, and the programmed number of stop bits. The least significant
bit is sent first. Following the transmission of the stop bits, if a new
character is not available in the THR, the TxD output remains High
and the TxEMT bit in the Status Register (SR) will be set to 1.
Transmission resumes and the TxEMT bit is cleared when the CPU
loads a new character into the THR.
Receiver FIFO
The RHR consists of a First-In-First-Out (FIFO) stack with a
capacity of three characters. Data is loaded from the receive shift
register into the topmost empty position of the FIFO. The RxRDY bit
in the status register is set whenever one or more characters are
available to be read, and a FFULL status bit is set if all three stack
positions are filled with data. Either of these bits can be selected to
cause an interrupt. A read of the RHR outputs the data at the top of
the FIFO. After the read cycle, the data FIFO and its associated
status bits (see below) are ‘popped’ thus emptying a FIFO position
for new data.
If the transmitter is disabled, it continues operating until the
character currently being transmitted is completely sent out. The
transmitter can be forced to send a continuous Low condition by
issuing a send break command.
The transmitter can be reset through a software command. If it is
reset, operation ceases immediately and the transmitter must be
enabled through the command register before resuming operation.
If CTS operation is enable, the CTSN input must be Low in order for
the character to be transmitted. If it goes High in the middle of a
transmission, the character in the shift register is transmitted and
TxDA then remains in the marking state until CTSN goes Low. The
transmitter can also control the deactivation of the RTSN output.
If programmed, the RTSN output will be reset one bit time after the
character in the transmit shift register and transmit holding register
Receiver Status Bits
In addition to the data word, three status bits (parity error, framing
error, and received break) are also appended to each data character
in the FIFO (overrun is not). Status can be provided in two ways, as
programmed by the error mode control bit in the mode register. In
the ‘character’ mode, status is provided on a character-by-character
basis; the status applies only to the character at the top of the FIFO.
In the ‘block’ mode, the status provided in the SR for these three bits
is the logical-OR of the status for all characters coming to the top of
the FIFO since the last ‘reset error’ command was issued. In either
9
1998 Sep 04
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCC2692
mode reading the SR does not affect the FIFO. The FIFO is
‘popped’ only when the RHR is read. Therefore the status register
should be read prior to reading the FIFO.
Counter commands and puts the C/T into counter mode under the
control of the received data stream. Each time a received character
is transferred from the shift register to the RHR, the C/T is stopped
after 1 C/T clock, reloaded with the value in CTU and CTL and then
restarted on the next C/T clock. If the C/T is allowed to end the
count before a new character has been received, the counter ready
bit, ISR[3], will be set. If IMR[3] is set, this will generate an interrupt.
Since receiving a character after the C/T has timed out will clear the
counter ready bit, ISR[3], and the interrupt. Invoking the ‘Set
Timeout Mode On’ command, CRx = ‘Ax’, will also clear the counter
ready bit and stop the counter until the next character is received.
If the FIFO is full when a new character is received, that character is
held in the receive shift register until a FIFO position is available. If
an additional character is received while this state exits, the
contents of the FIFO are not affected; the character previously in the
shift register is lost and the overrun error status bit (SR[4] will be
set-upon receipt of the start bit of the new (overrunning) character.
The receiver can control the deactivation of RTS. If programmed to
operate in this mode, the RTSN output will be negated when a valid
start bit was received and the FIFO is full. When a FIFO position
becomes available, the RTSN output will be re-asserted
automatically. This feature can be used to prevent an overrun, in the
receiver, by connecting the RTSN output to the CTSN input of the
transmitting device.
This mode is reset by the “Disable Time-out Mode” command (CR
x’C0) must be used.
Time Out Mode Caution
When operating in the special time out mode, it is possible to
generate what appears to be a “false interrupt”, i.e., an interrupt
without a cause. This may result when a time-out interrupt occurs
and then, BEFORE the interrupt is serviced, another character is
received, i.e., the data stream has started again. (The interrupt
latency is longer than the pause in the data strea.) In this case,
when a new character has been receiver, the counter/timer will be
restarted by the receiver, thereby withdrawing its interrupt. If, at this
time, the interrupt service begins for the previously seen interrupt, a
read of the ISR will show the “Counter Ready” bit not set. If nothing
else is interrupting, this read of the ISR will return a x’00 character.
Receiver Reset and Disable
Receiver disable stops the receiver immediately – data being
assembled if the receiver shift register is lost. Data and status in the
FIFO is preserved and may be read. A re-enable of the receiver
after a disable will cause the receiver to begin assembling
characters at the next start bit detected. A receiver reset will discard
the present shift register data, reset the receiver ready bit (RxRDY),
clear the status of the byte at the top of the FIFO and re-align the
FIFO read/write pointers. This has the appearance of “clearing or
flushing” the receiver FIFO. In fact, the FIFO is NEVER cleared!
The data in the FIFO remains valid until overwritten by another
received character. Because of this, erroneous reading or extra
reads of the receiver FIFO will miss-align the FIFO pointers and
result in the reading of previously read data. A receiver reset will
re-align the pointers.
Multidrop Mode
The DUART is equipped with a receiver wake-up mode for multidrop
applications. This mode is selected by programming bits MR1A[4:3]
or MR1B[4:3] to ‘11’ for Channels A and B, respectively. In this mode
of operation, a ‘master’ station transmits an address character
followed by data characters for the addressed ‘slave’ station. The
slave stations, with receivers that are normally disabled, examine
the received data stream and ‘wake-up’ the CPU (by setting
RxRDY) only upon receipt of an address character. The CPU
compares the received address to its station address and enables
the receiver if it wishes to receive the subsequent data characters.
Upon receipt of another address character, the CPU may disable the
receiver to initiate the process again.
Receiver Timeout Mode
The timeout mode uses the received data stream to control the
counter/timer. Each time a received character is transferred from the
shift register to the RHR, the counter is restarted. If a new character
is not received before the counter reaches zero count, the counter
ready bit is set, and an interrupt can be generated. This mode can
be used to indicate when data has been left in the Rx FIFO for more
than the programmed time limit. Otherwise, if the receiver has been
programmed to interrupt the CPU when the receive FIFO is full, and
the message ends before the FIFO is full, the CPU may not know
there is data left in the FIFO. The CTU and CTL value would be
programmed for just over one character time, so that the CPU would
be interrupted as soon as it has stopped receiving continuous data.
This mode can also be used to indicate when the serial line has
been marking for longer than the programmed time limit. In this
case, the CPU has read all of the characters from the FIFO, but the
last character received has started the count. If there is no new data
during the programmed time interval, the counter ready bit will get
set, and an interrupt can be generated.
A transmitted character consists of a start bit, the programmed
number of data bits, and Address/Data (A/D) bit, and the
programmed number of stop bits. The polarity of the transmitted A/D
bit is selected by the CPU by programming bit MR1A[2]/MR1B[2].
MR1A[2]/MR1B[2] = 0 transmits a zero in the A/D bit position, which
identifies the corresponding data bits as data while
MR1A[2]/MR1B[2] = 1 transmits a one in the A/D bit position, which
identifies the corresponding data bits as an address. The CPU
should program the mode register prior to loading the corresponding
data bits into the THR.
In this mode, the receiver continuously looks at the received data
stream, whether it is enabled or disabled. If disabled, it sets the
RxRDY status bit and loads the character into the RHR FIFO if the
received A/D bit is a one (address tag), but discards the received
character if the received A/D bit is a zero (data tag). If enabled, all
received characters are transferred to the CPU via the RHR. In
either case, the data bits are loaded into the data FIFO while the
A/D bit is loaded into the status FIFO position normally used for
parity error (SRA[5] or SRB[5]). Framing error, overrun error, and
break detect operate normally whether or not the receive is enabled.
The timeout mode is enabled by writing the appropriate command to
the command register. Writing an ‘Ax’ to CRA or CRB will invoke the
timeout mode for that channel. Writing a ‘Cx’ to CRA or CRB will
disable the timeout mode. The timeout mode should only be used by
one channel at once, since it uses the C/T. CTU and CTL must be
loaded with a value greater than the normal receive character
period. The timeout mode disables the regular START/STOP
10
1998 Sep 04
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCC2692
Table 1. SCC2692 Register Addressing
A3
A2
A1
A0
READ (RDN = 0)
WRITE (WRN = 0)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Mode Register A (MR1A, MR2A)
Status Register A (SRA)
BRG Test
Mode Register A (MR1A, MR2A)
Clock Select Register A (CSRA)
Command Register A (CRA)
Tx Holding Register A (THRA)
Aux. Control Register (ACR)
Interrupt Mask Register (IMR)
C/T Upper Preset Value (CRUR)
C/T Lower Preset Value (CTLR)
Mode Register B (MR1B, MR2B)
Clock Select Register B (CSRB)
Command Register B (CRB)
Tx Holding Register B (THRB)
Reserved
Rx Holding Register A (RHRA)
Input Port Change Register (IPCR)
Interrupt Status Register (ISR)
Counter/Timer Upper Value (CTU)
Counter/Timer Lower Value (CTL)
Mode Register B (MR1B, MR2B)
Status Register B (SRB)
1X/16X Test
Rx Holding Register B (RHRB)
Reserved
Input Ports IP0 to IP6
Start Counter Command
Stop Counter Command
Output Port Conf. Register (OPCR)
Set Output Port Bits Command
Reset Output Port Bits Command
* See Table 6 for BRG Test frequencies in this data sheet, and “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692,
SCC68681 and SCC2698B” in application notes elsewhere in this publication
Table 2. Register Bit Formats
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RxRTS
CONTROL
RxINT
SELECT
ERROR
MODE*
PARITY
TYPE
BITS PER
CHARACTER
PARITY MODE
MR1A
MR1B
00 = With Parity
01 = Force Parity
10 = No Parity
00 = 5
01 = 6
10 = 7
11 = 8
0 = No
1 = Yes
0 = RxRDY
1 = FFULL
0 = Char
1 = Block
0 = Even
1 = Odd
11 = Multidrop Mode
NOTE:
*In block error mode, block error conditions must be cleared by using the error reset command (command 4x) or a receiver reset.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TxRTS
CONTROL
CTS
ENABLE Tx
CHANNEL MODE
STOP BIT LENGTH*
MR2A
MR2B
00 = Normal
0 = 0.563
1 = 0.625
2 = 0.688
3 = 0.750
4 = 0.813
5 = 0.875
6 = 0.938
7 = 1.000
8 = 1.563
9 = 1.625
A = 1.688
B = 1.750
C = 1.813
D = 1.875
E = 1.938
F = 2.000
01 = Auto-Echo
10 = Local loop
11 = Remote loop
0 = No
1 = Yes
0 = No
1 = Yes
NOTE: *Add 0.5 to values shown for 0 – 7 if channel is programmed for 5 bits/char.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CSRA
CSRB
RECEIVER CLOCK SELECT
TRANSMITTER CLOCK SELECT
See Text
See Text
* See Table 6 for BRG Test frequencies in this data sheet, and “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692,
SCC68681 and SCC2698B” in application notes elsewhere in this publication
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CRA
CRB
MISCELLANEOUS COMMANDS
DISABLE Tx
ENABLE Tx
DISABLE Rx
ENABLE Rx
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
See Text and Timing Requirement
NOTE: Access to the miscellaneous commands should be separated by 3 X1 clock edges. A disabled transmitter cannot be loaded.
11
1998 Sep 04
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCC2692
Table 2. Register Bit Formats (Continued)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RECEIVED
BREAK*
FRAMING
ERROR*
PARITY
ERROR*
OVERRUN
ERROR
SRA
SRB
TxEMT
TxRDY
FFULL
RxRDY
0 = No
0 = No
0 = No
0 = No
0 = No
0 = No
0 = No
0 = No
1 = Yes
1 = Yes
1 = Yes
1 = Yes
1 = Yes
1 = Yes
1 = Yes
1 = Yes
NOTE: *These status bits are appended to the corresponding data character in the receive FIFO. A read of the status provides these bits
(7:5) from the top of the FIFO together with bits (4:0). These bits are cleared by a “reset error status” command. In character mode they are
discarded when the corresponding data character is read from the FIFO. In block error mode, block error conditions must be cleared by using
the error reset command (command 4x) or a receiver reset.
BIT 7
OP7
BIT 6
OP6
BIT 5
OP5
BIT 4
OP4
BIT 3
BIT 2
BIT 1
BIT 0
OP3
00 = OPR[3]
01 = C/T OUTPUT
10 = TxCB(1X)
11 = RxCB(1X)
OP2
0 = OPR[7]
1 = TxRDYB 1 = TxRDYA 1 = RxRDY/
FFULLB
0 = OPR[6]
0 = OPR[5]
0 = OPR[4]
1 = RxRDY/
FFULLA
00 = OPR[2]
OPCR
01 = TxCA(16X)
10 = TxCA(1X)
11 = RxCA(1X)
OPR
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
OPR bit
OP pin
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
NOTE:
The level at the OP pin is the inverse of the bit in the OPR register.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BRG SET
SELECT
COUNTER/TIMER
MODE AND SOURCE
DELTA
IP 3 INT
DELTA
IP 2 INT
DELTA
IP 1 INT
DELTA
IP 0 INT
ACR
0 = set 1
1 = set 2
0 = Off
1 = On
0 = Off
1 = On
0 = Off
1 = On
0 = Off
1 = On
See Table 4
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
IP 3
BIT 2
IP 2
BIT 1
IP 1
BIT 0
IP 0
DELTA
IP 3
DELTA
IP 2
DELTA
IP 1
DELTA
IP 0
IPCR
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = Low
1 = High
0 = Low
1 = High
0 = Low
1 = High
0 = Low
1 = High
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
INPUT
PORT
CHANGE
DELTA
BREAK B
RxRDY/
FFULLB
COUNTER
READY
DELTA
BREAK A
RxRDY/
FFULLA
TxRDYB
TxRDYA
ISR
IMR
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
IN. PORT
CHANGE
INT
DELTA
BREAK B
INT
RxRDY/
FFULLB
INT
COUNTER
READY
INT
DELTA
BREAK A
INT
RxRDY/
FFULLA
INT
TxRDYB
INT
TxRDYA
INT
0 = Off
1 = On
0 = Off
1 = On
0 = Off
1 = On
0 = Off
1 = On
0 = Off
1 = On
0 = Off
1 = On
0 = Off
1 = On
0 = Off
1 = On
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CTUR
CTLR
C/T[15]
C/T[14]
C/T[13]
C/T[12]
C/T[11]
C/T[10]
C/T[9]
C/T[8]
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
C/T[7]
C/T[6]
C/T[5]
C/T[4]
C/T[3]
C/T[2]
C/T[1]
C/T[0]
12
1998 Sep 04
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCC2692
MR1A[4:3| – Channel A Parity Mode Select
PROGRAMMING
If ‘with parity’ or ‘force parity’ is selected a parity bit is added to the
transmitted character and the receiver performs a parity check on
incoming data MR1A[4:3] = 11 selects Channel A to operate in the
special multidrop mode described in the Operation section.
The operation of the DUART is programmed by writing control words
into the appropriate registers. Operational feedback is provided via
status registers which can be read by the CPU. The addressing of
the registers is described in Table 1.
The contents of certain control registers are initialized to zero on
RESET. Care should be exercised if the contents of a register are
changed during operation, since certain changes may cause
operational problems.
MR1A[2] – Channel A Parity Type Select
This bit selects the parity type (odd or even) if the ‘with parity’ mode
is programmed by MR1A[4:3], and the polarity of the forced parity bit
if the ‘force parity’ mode is programmed. It has no effect if the ‘no
parity’ mode is programmed. In the special multidrop mode it selects
the polarity of the A/D bit.
For example, changing the number of bits per character while the
transmitter is active may cause the transmission of an incorrect
character. In general, the contents of the MR, the CSR, and the
OPCR should only be changed while the receiver(s) and
transmitter(s) are not enabled, and certain changes to the ACR
should only be made while the C/T is stopped.
MR1A[1:0] – Channel A Bits Per Character Select
This field selects the number of data bits per character to be
transmitted and received. The character length does not include the
start, parity, and stop bits.
Mode registers 1 and 2 of each channel are accessed via
independent auxiliary pointers. The pointer is set to MR1X by
RESET or by issuing a ‘reset pointer’ command via the
corresponding command register. Any read or write of the mode
register while the pointer is at MR1X, switches the pointer to MR2X.
The pointer then remains at MR2X, so that subsequent accesses
are always to MR2X unless the pointer is reset to MR1X as
described above.
MR2A – Channel A Mode Register 2
MR2A is accessed when the Channel A MR pointer points to MR2,
which occurs after any access to MR1A. Accesses to MR2A do not
change the pointer.
MR2A[7:6] – Channel A Mode Select
Each channel of the DUART can operate in one of four modes.
MR2A[7:6] = 00 is the normal mode, with the transmitter and
receiver operating independently. MR2A[7:6] = 01 places the
channel in the automatic echo mode, which automatically
re-transmits the received data. The following conditions are true
while in automatic echo mode:
Mode, command, clock select, and status registers are duplicated
for each channel to provide total independent operation and control.
Refer to Table 2 for register bit descriptions. The reserved registers
at addresses H‘02’ and H‘OA’ should never be read during normal
operation since they are reserved for internal diagnostics.
1. Received data is re-clocked and retransmitted on the TxDA out-
put.
MR1A – Channel A Mode Register 1
MR1A is accessed when the Channel A MR pointer points to MR1.
The pointer is set to MR1 by RESET or by a ‘set pointer’ command
applied via CRA. After reading or writing MR1A, the pointer will point
to MR2A.
2. The receive clock is used for the transmitter.
3. The receiver must be enabled, but the transmitter need not be
enabled.
4. The Channel A TxRDY and TxEMT status bits are inactive.
5. The received parity is checked, but is not regenerated for trans-
mission, i.e., transmitted parity bit is as received.
MR1A[7] – Channel A Receiver Request-to-Send Control
This bit controls the deactivation of the RTSAN output (OP0) by the
receiver. This output is normally asserted by setting OPR[0] and
negated by resetting OPR[0]. MR1A[7] = 1 causes RTSAN to be
negated upon receipt of a valid start bit if the Channel A FIFO is full.
However, OPR[0] is not reset and RTSAN will be asserted again
when an empty FIFO position is available. This feature can be used
for flow control to prevent overrun in the receiver by using the
RTSAN output signal to control the CTSN input of the transmitting
device.
6. Character framing is checked, but the stop bits are retransmitted
as received.
7. A received break is echoed as received until the next valid start
bit is detected.
8. CPU to receiver communication continues normally, but the CPU
to transmitter link is disabled.
Two diagnostic modes can also be configured. MR2A[7:6] = 10
selects local loopback mode. In this mode:
1. The transmitter output is internally connected to the receiver
input.
MR1A[6] – Channel A Receiver Interrupt Select
This bit selects either the Channel A receiver ready status (RxRDY)
or the Channel A FIFO full status (FFULL) to be used for CPU
interrupts. It also causes the selected bit to be output on OP4 if it is
programmed as an interrupt output via the OPCR.
2. The transmit clock is used for the receiver.
3. The TxDA output is held High.
4. The RxDA input is ignored.
MR1A[5] – Channel A Error Mode Select
This bit selects the operating mode of the three FIFOed status bits
(FE, PE, received break) for Channel A. In the ‘character’ mode,
status is provided on a character-by-character basis; the status
applies only to the character at the top of the FIFO. In the ‘block’
mode, the status provided in the SR for these bits is the
accumulation (logical-OR) of the status for all characters coming to
the top of the FIFO since the last ‘reset error’ command for Channel
A was issued.
5. The transmitter must be enabled, but the receiver need not be
enabled.
6. CPU to transmitter and receiver communications continue nor-
mally.
The second diagnostic mode is the remote loopback mode, selected
by MR2A[7:6] = 11. In this mode:
13
1998 Sep 04
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCC2692
1. Received data is re-clocked and retransmitted on the TxDA out-
put.
1. Program the auto-reset mode: MR2[5]=1
2. Enable transmitter, if not already enabled
3. Assert RTSN via command
4. Send message
5. After the last character of the message is loaded to the THR,
disable the transmitter. (If the transmitter is underrun, a special
case exists. See note below.)
2. The receive clock is used for the transmitter.
3. Received data is not sent to the local CPU, and the error status
conditions are inactive.
4. The received parity is not checked and is not regenerated for
transmission, i.e., transmitted parity is as received.
6. The last character will be transmitted and the RTSN will be reset
one bit time after the last stop bit is sent.
5. The receiver must be enabled.
NOTE: The transmitter is in an underrun condition when both the
TxRDY and the TxEMT bits are set. This condition also exists
immediately after the transmitter is enabled from the disabled or
reset state. When using the above procedure with the transmitter in
the underrun condition, the issuing of the transmitter disable must be
delayed from the loading of a single, or last, character until the
TxRDY becomes active again after the character is loaded.
6. Character framing is not checked, and the stop bits are retrans-
mitted as received.
7. A received break is echoed as received until the next valid start
bit is detected.
The user must exercise care when switching into and out of the
various modes. The selected mode will be activated immediately
upon mode selection, even if this occurs in the middle of a received
or transmitted character. Likewise, if a mode is deselected the
device will switch out of the mode immediately. An exception to this
is switching out of autoecho or remote loopback modes: if the
de-selection occurs just after the receiver has sampled the stop bit
(indicated in autoecho by assertion of RxRDY), and the transmitter
is enabled, the transmitter will remain in autoecho mode until the
entire stop has been re-transmitted.
MR2A[4] – Channel A Clear-to-Send Control
If this bit is 0, CTSAN has no effect on the transmitter. If this bit is a
1, the transmitter checks the state of CTSAN (IPO) each time it is
ready to send a character. If IPO is asserted (Low), the character is
transmitted. If it is negated (High), the TxDA output remains in the
marking state and the transmission is delayed until CTSAN goes
low. Changes in CTSAN while a character is being transmitted do
not affect the transmission of that character..
MR2A[5] – Channel A Transmitter Request-to-Send Control
CAUTION: When the transmitter controls the OP pin (usually used
for the RTSN signal) the meaning of the pin is not RTSN at all!
Rather, it signals that the transmitter has finished the transmission
(i.e., end of block).
MR2A[3:0] – Channel A Stop Bit Length Select
This field programs the length of the stop bit appended to the
transmitted character. Stop bit lengths of 9/16 to 1 and 1-9/16 to 2
bits, in increments of 1/16 bit, can be programmed for character
lengths of 6, 7, and 8 bits. For a character lengths of 5 bits, 1-1/16 to
2 stop bits can be programmed in increments of 1/16 bit. In all
cases, the receiver only checks for a ‘mark’ condition at the center
of the first stop bit position (one bit time after the last data bit, or
after the parity bit is enabled).
This bit allows deactivation of the RTSN output by the transmitter.
This output is manually asserted and negated by the appropriate
commands issued via the command register. MR2[5] set to 1
caused the RTSN to be reset automatically one bit time after the
character(s) in the transmit shift register and in the THR (if any) are
completely transmitted (including the programmed number of stop
bits) if a previously issued transmitter disable is pending. This
feature can be used to automatically terminate the transmission as
follows:
If an external 1X clock is used for the transmitter, MR2A[3] = 0
selects one stop bit and MR2A[3] = 1 selects two stop bits to be
transmitted.
14
1998 Sep 04
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCC2692
CSRB[3:0] – Channel B Transmitter Clock Select
This field selects the baud rate clock for the Channel B transmitter.
The field definition is as shown in Table 3, except as follows:
MR1B – Channel B Mode Register 1
MR1B is accessed when the Channel B MR pointer points to MR1.
The pointer is set to MR1 by RESET or by a ‘set pointer’ command
applied via CRB. After reading or writing MR1B, the pointer will point
to MR2B.
CSRB[3:0]
ACR[7] = 0
ACR[7] = 1
1110
1111
IP5-16X
IP5-1X
IP5-16X
IP5-1X
The bit definitions for this register are identical to MR1A, except that
all control actions apply to the Channel B receiver and transmitter
and the corresponding inputs and outputs.
The transmitter clock is always a 16X clock except for CSRB[3:0] =
1111.
MR2B – Channel B Mode Register 2
MR2B is accessed when the Channel B MR pointer points to MR2,
which occurs after any access to MR1B. Accesses to MR2B do not
change the pointer.
CRA – Channel A Command Register
CRA is a register used to supply commands to Channel A. Multiple
commands can be specified in a single write to CRA as long as the
commands are non-conflicting, e.g., the ‘enable transmitter’ and
‘reset transmitter’ commands cannot be specified in a single
command word.
The bit definitions for mode register are identical to the bit
definitions for MR2A, except that all control actions apply to the
Channel B receiver and transmitter and the corresponding inputs
and outputs.
CRA[7:4] – Miscellaneous Commands
Sequential writes to CR(7:4) should be separated by three edges of
the X1 clock.
CSRA – Channel A Clock Select Register
CSRA[7:4] – Channel A Receiver Clock Select
This field selects the baud rate clock for the Channel A transmitter.
The field definition is shown in Table 3.
The encoded value of this field may be used to specify a single
command as follows:
0000 No command.
0001 Reset MR pointer. Causes the Channel A MR pointer to point
to MR1.
0010 Reset receiver. Resets the Channel A receiver as if a hard-
ware reset had been applied. The receiver is disabled and the
FIFO is flushed.
0011 Reset transmitter. Resets the Channel A transmitter as if a
hardware reset had been applied.
CSRA[3:0] – Channel A Transmitter Clock Select
This field selects the baud rate clock for the Channel A transmitter.
The field definition is as shown in Table 3, except as follows:
CSRA[3:0]
ACR[7] = 0
ACR[7] = 1
1110
1111
IP3-16X
IP3-1X
IP3-16X
IP3-1X
The transmitter clock is always a 16X clock except for CSRA[3:0] =
1111.
0100 Reset error status. Clears the Channel A Received Break,
Parity Error, and Overrun Error bits in the status register
(SRA[7:4]). Used in character mode to clear OE status (al-
though RB, PE and FE bits will also be cleared) and in block
mode to clear all error status after a block of data has been
received.
0101 Reset Channel A break change interrupt. Causes the Chan-
nel A break detect change bit in the interrupt status register
(ISR[2]) to be cleared to zero.
0110 Start break. Forces the TxDA output Low (spacing). If the
transmitter is empty the start of the break condition will be
delayed up to two bit times. If the transmitter is active the
break begins when transmission of the character is com-
pleted. If a character is in the THR, the start of the break will
be delayed until that character, or any other loaded subse-
quently are transmitted. The transmitter must be enabled for
this command to be accepted.
0111 Stop break. The TxDA line will go High (marking) within two
bit times. TxDA will remain High for one bit time before the
next character, if any, is transmitted.
1000 Assert RTSN. Causes the RTSN output to be asserted (Low).
1001 Negate RTSN. Causes the RTSN output to be negated
(High).
1010 Set Timeout Mode On. The receiver in this channel will restart
the C/T as each receive character is transferred from the shift
register to the RHR. The C/T is placed in the counter mode,
the START/STOP counter commands are disabled, the
counter is stopped, and the Counter Ready Bit, ISR[3], is
reset. The counter will not start until the first character is re-
ceived after the command is issued.
Table 3. Baud Rate
CSRA[7:4]
ACR[7] = 0
ACR[7] = 1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
50
110
134.5
200
300
600
1,200
1,050
2,400
4,800
75
110
134.5
150
300
600
1,200
2,000
2,400
4,800
1010
1011
1100
1101
1110
1111
7,200
9,600
38.4K
Timer
IP4-16X
1,800
9,600
19.2K
Timer
IP4-16X
IP4-1X
IP4-1X
NOTE: The receiver clock is always a 16X clock except for CSRA[7:4]
= 1111. Also, see Table 6 for baud rates available in BRG Test.
CSRB – Channel B Clock Select Register
CSRB[7:4] – Channel B Receiver Clock Select
This field selects the baud rate clock for the Channel B receiver.
The field definition is as shown in Table 3, except as follows:
1011 Not used.
CSRB[7:4]
ACR[7] = 0
ACR[7] = 1
1100 Disable Timeout Mode. This command returns control of the
C/T to the regular START/STOP counter commands. It does
not stop the counter, or clear any pending interrupts. After
disabling the timeout mode, a ‘Stop Counter’ command
should be issued to reset the ISR(3) bit.
1110
1111
IP6-16X
IP6-1X
IP6-16X
IP6-1X
The receiver clock is always a 16X clock except for CSRB[7:4] = 1111.
1998 Sep 04
1101 Not used.
15
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCC2692
1110 Power Down Mode On. In this mode, the DUART oscillator is
stopped and all functions requiring this clock are suspended.
The execution of commands other than disable power down
mode (1111) requires a X1/CLK. While in the power down
mode, do not issue any commands to the CR except the
disable power down mode command. The contents of all
registers will be saved while in this mode. It is recommended
that the transmitter and receiver be disabled prior to placing
the DUART into power down mode. This command is in CRA
only.
SRA[6] – Channel A Framing Error
This bit, when set, indicates that a stop bit was not detected when
the corresponding data character in the FIFO was received. The
stop bit check is made in the middle of the first stop bit position.
SRA[5] – Channel A Parity Error
This bit is set when the ‘with parity’ or ‘force parity’ mode is
programmed and the corresponding character in the FIFO was
received with incorrect parity.
In the special multidrop mode the parity error bit stores the receive
A/D bit.
1111 Disable Power Down Mode. This command restarts the oscil-
lator. After invoking this command, wait for the oscillator to
start up before writing further commands to the CR. This
command is in CRA only.
SRA[4] – Channel A Overrun Error
This bit, when set, indicates that one or more characters in the
received data stream have been lost. It is set upon receipt of a new
character when the FIFO is full and a character is already in the
receive shift register waiting for an empty FIFO position. When this
occurs, the character in the receive shift register (and its break
detect, parity error and framing error status, if any) is lost.
CRA[3] – Disable Channel A Transmitter
This command terminates transmitter operation and resets the
TxDRY and TxEMT status bits. However, if a character is being
transmitted or if a character is in the THR when the transmitter is
disabled, the transmission of the character(s) is completed before
assuming the inactive state.
This bit is cleared by a ‘reset error status’ command.
CRA[2] – Enable Channel A Transmitter
Enables operation of the Channel A transmitter. The TxRDY status
bit will be asserted.
SRA[3] – Channel A Transmitter Empty (TxEMTA)
This bit will be set when the transmitter underruns, i.e., both the
TxEMT and TxRDY bits are set. This bit and TxRDY are set when
the transmitter is first enabled and at any time it is re-enabled after
either (a) reset, or (b) the transmitter has assumed the disabled
state. It is always set after transmission of the last stop bit of a
character if no character is in the THR awaiting transmission.
CRA[1] – Disable Channel A Receiver
This command terminates operation of the receiver immediately – a
character being received will be lost. The command has no effect on
the receiver status bits or any other control registers. If the special
multidrop mode is programmed, the receiver operates even if it is
disabled. See Operation section.
It is reset when the THR is loaded by the CPU, a pending
transmitter disable is executed, the transmitter is reset, or the
transmitter is disabled while in the underrun condition.
CRA[0] – Enable Channel A Receiver
Enables operation of the Channel A receiver. If not in the special
wake-up mode, this also forces the receiver into the search for start
bit state.
SRA[2] – Channel A Transmitter Ready (TxRDYA)
This bit, when set, indicates that the THR is empty and ready to be
loaded with a character. This bit is cleared when the THR is loaded
by the CPU and is set when the character is transferred to the
transmit shift register. TxRDY is reset when the transmitter is
disabled and is set when the transmitter is first enabled, e.g.,
characters loaded into the THR while the transmitter is disabled will
not be transmitted.
CRB – Channel B Command Register
CRB is a register used to supply commands to Channel B. Multiple
commands can be specified in a single write to CRB as long as the
commands are non-conflicting, e.g., the ‘enable transmitter’ and
‘reset transmitter’ commands cannot be specified in a single
command word.
SRA[1] – Channel A FIFO Full (FFULLA)
The bit definitions for this register are identical to the bit definitions
for CRA, with the exception of commands “Ex” and “Fx” which are
used for power downmode. These two commands are not used in
CRB. All other control actions that apply to CRA also apply to CRB.
This bit is set when a character is transferred from the receive shift
register to the receive FIFO and the transfer causes the FIFO to
become full, i.e., all three FIFO positions are occupied. It is reset
when the CPU reads the RHR. If a character is waiting in the
receive shift register because the FIFO is full, FFULL will not be
reset when the CPU reads the RHR.
SRA – Channel A Status Register
SRA[7] – Channel A Received Break
SRA[0] – Channel A Receiver Ready (RxRDYA)
This bit indicates that a character has been received and is waiting
in the FIFO to be read by the CPU. It is set when the character is
transferred from the receive shift to the FIFO and reset when the
CPU reads the RHR, if after this read there are not more characters
still in the FIFO.
This bit indicates that an all zero character of the programmed
length has been received without a stop bit. Only a single FIFO
position is occupied when a break is received: further entries to the
FIFO are inhibited until the RxDA line returns to the marking state
for at least one-half a bit time two successive edges of the internal
or external 1X clock. This will usually require a high time of one
X1 clock period or 3 X1 edges since the clock of the controller
is not synchronous to the X1 clock.
SRB – Channel B Status Register
The bit definitions for this register are identical to the bit definitions
for SRA, except that all status applies to the Channel B receiver and
transmitter and the corresponding inputs and outputs.
When this bit is set, the Channel A ‘change in break’ bit in the ISR
(ISR[2]) is set. ISR[2] is also set when the end of the break
condition, as defined above, is detected.
The break detect circuitry can detect breaks that originate in the
middle of a received character. However, if a break begins in the
middle of a character, it must persist until at least the end of the next
character time in order for it to be detected.
16
1998 Sep 04
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCC2692
10 The 1X clock for the Channel A transmitter, which is the clock
that shifts the transmitted data. If data is not being transmitted, a
free running 1X clock is output.
11 The 1X clock for the Channel A receiver, which is the clock that
samples the received data. If data is not being received, a free
running 1X clock is output.
OPCR – Output Port Configuration Register
OPCR[7] – OP7 Output Select
This bit programs the OP7 output to provide one of the following:
0 The complement of OPR[7].
1 The Channel B transmitter interrupt output which is the
complement of TxRDYB. When in this mode OP7 acts as an
open- drain output. Note that this output is not masked by the
contents of the IMR.
ACR – Auxiliary Control Register
ACR[7] – Baud Rate Generator Set Select
This bit selects one of two sets of baud rates to be generated by the
BRG:
OPCR[6] – OP6 Output Select
This bit programs the OP6 output to provide one of the following:
0 The complement of OPR[6].
1 The Channel A transmitter interrupt output which is the
complement of TxRDYA. When in this mode OP6 acts as an
open- drain output. Note that this output is not masked by the
contents of the IMR.
Set 1:
50, 110, 134.5, 200, 300, 600, 1.05K, 1.2K, 2.4K, 4.8K,
7.2K, 9.6K, and 38.4K baud.
Set 2:
75, 110, 134.5, 150, 300, 600, 1.2K, 1.8K, 2.0K, 2.4K,
4.8K, 9.6K, and 19.2K baud.
Table 4. Bit Rate Generator Characteristics
Crystal or Clock = 3.6864MHz
OPCR[5] – OP5 Output Select
BAUD RATE
ACTUAL 16X CLOCK (kHz)
ERROR (%)
This bit programs the OP5 output to provide one of the following:
0 The complement of OPR[5].
1 The Channel B transmitter interrupt output which is the
complement of ISR[5]. When in this mode OP5 acts as an
open-drain output. Note that this output is not masked by the
contents of the IMR.
50
75
110
134.5
150
200
0.8
1.2
1.759
2.153
2.4
0
0
-0.069
0.059
0
0
3.2
300
600
4.8
9.6
16.756
19.2
28.8
32.056
38.4
76.8
115.2
153.6
230.4
307.2
460.8
614.4
921.2
1,843.2
0
0
OPCR[4] – OP4 Output Select
This field programs the OP4 output to provide one of the following:
0 The complement of OPR[4].
1 The Channel A receiver interrupt output which is the complement
of ISR[1]. When in this mode OP4 acts as an open-drain output.
Note that this output is not masked by the contents of the IMR.
1050
1200
1800
2000
2400
4800
7200
9600
14.4K
19.2K
28.8K
38.4K
57.6K
115.2K
-0.260
0
0
0.175
0
0
0
0
0
0
0
0
0
0
OPCR[3:2] – OP3 Output Select
This bit programs the OP3 output to provide one of the following:
00 The complement of OPR[3].
01 The counter/timer output, in which case OP3 acts as an
open-drain output. In the timer mode, this output is a square
wave at the programmed frequency. In the counter mode, the
output remains High until terminal count is reached, at which
time it goes Low. The output returns to the High state when the
counter is stopped by a stop counter command. Note that this
output is not masked by the contents of the IMR.
10 The 1X clock for the Channel B transmitter, which is the clock
that shifts the transmitted data. If data is not being transmitted, a
free running 1X clock is output.
NOTE: Duty cycle of 16X clock is 50% ±1%.
The selected set of rates is available for use by the Channel A and
B receivers and transmitters as described in CSRA and CSRB.
Baud rate generator characteristics are given in Table 4.
ACR[6:4] – Counter/Timer Mode And Clock Source Select
This field selects the operating mode of the counter/timer and its
clock source as shown in Table 5.
11 The 1X clock for the Channel B receiver, which is the clock that
samples the received data. If data is not being received, a free
running 1X clock is output.
ACR[3:0] – IP3, IP2, IP1, IP0 Change-of-State Interrupt Enable
This field selects which bits of the input port change register (IPCR)
cause the input change bit in the interrupt status register (ISR[7]) to
be set. If a bit is in the ‘on’ state the setting of the corresponding bit
in the IPCR will also result in the setting of ISR[7], which results in
the generation of an interrupt output if IMR[7] = 1. If a bit is in the
‘off’ state, the setting of that bit in the IPCR has no effect on ISR[7].
OPCR[1:0] – OP2 Output Select
This field programs the OP2 output to provide one of the following:
00 The complement of OPR[2].
01 The 16X clock for the Channel A transmitter. This is the clock
selected by CSRA[3:0], and will be a 1X clock if CSRA[3:0] =
1111.
17
1998 Sep 04
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCC2692
a character is transferred from the receive holding register to the
receive FIFO and the transfer caused the Channel B FIFO to
become full; i.e., all three FIFO positions are occupied. It is reset
when the CPU reads the RHR. If a character is waiting in the
receive shift register because the FIFO is full, the bit will be set
again when the waiting character is loaded into the FIFO.
Table 5. ACR 6:4 Field Definition
ACR
6:4
MODE
CLOCK SOURCE
000
Counter
Counter
External (IP2)
TxCA – 1X clock of Channel A
transmitter
001
010
011
ISR[4] – Channel B Transmitter Ready
This bit is a duplicate of TxRDYB (SRB[2]).
TxCB – 1X clock of Channel B
transmitter
Counter
Counter
Crystal or external (X1/CLK)
divided by 16
ISR[3] – Counter Ready.
In the counter mode, this bit is set when the counter reaches
terminal count and is reset when the counter is stopped by a stop
counter command.
100
101
Timer (square wave)
Timer (square wave)
External (IP2)
External (IP2) divided by 16
Crystal or external clock
(X1/CLK)
110
111
Timer (square wave)
Timer (square wave)
In the timer mode, this bit is set once each cycle of the generated
square wave (every other time that the counter/timer reaches zero
count). The bit is reset by a stop counter command. The command,
however, does not stop the counter/timer.
Crystal or IP2 clock (X1/CLK)
divided by 16
NOTE: Timer mode generates a squarewave.
In the time-out mode, the “Disable Time-out Mode” command (CR
x’C0) must be used.
IPCR – Input Port Change Register
IPCR[7:4] – IP3, IP2, IP1, IP0 Change-of-State
ISR[2] – Channel A Change in Break
These bits are set when a change-of-state, as defined in the input
port section of this data sheet, occurs at the respective input pins.
They are cleared when the IPCR is read by the CPU. A read of the
IPCR also clears ISR[7], the input change bit in the interrupt status
register. The setting of these bits can be programmed to generate
an interrupt to the CPU.
This bit, when set, indicates that the Channel A receiver has
detected the beginning or the end of a received break. It is reset
when the CPU issues a Channel A ‘reset break change interrupt’
command.
ISR[1] – Channel A Receiver Ready Or FIFO Full
The function of this bit is programmed by MR1A[6]. If programmed
as receiver ready, it indicates that a character has been received in
Channel A and is waiting in the FIFO to be read by the CPU. It is set
when the character is transferred from the receive shift register to
the FIFO and reset when the CPU reads the RHR. If after this read
there are more characters still in the FIFO the bit will be set again
after the FIFO is ‘popped’. If programmed as FIFO full, it is set
when a character is transferred from the receive holding register to
the receive FIFO and the transfer caused the Channel A FIFO to
become full; i.e., all three FIFO positions are occupied. It is reset
when the CPU reads the RHR. If a character is waiting in the
receive shift register because the FIFO is full, the bit will be set
again when the ISR[0] and IMR waiting character is loaded into the
FIFO.
IPCR[3:0] – IP3, IP2, IP1, IP0 Change-of-State
These bits provide the current state of the respective inputs. The
information is unlatched and reflects the state of the input pins at the
time the IPCR is read.
ISR – Interrupt Status Register
This register provides the status of all potential interrupt sources.
The contents of this register are masked by the Interrupt Mask
Register (IMR). If a bit in the ISR is a ‘1’ and the corresponding bit in
the IMR is also a ‘1’, the INTRN output will be asserted (Low). If the
corresponding bit in the IMR is a zero, the state of the bit in the ISR
has no effect on the INTRN output. Note that the IMR does not mask
the reading of the ISR – the true status will be provided regardless
of the contents of the IMR. The contents of this register are
ISR[0] – Channel A Transmitter Ready
This bit is a duplicate of TxRDYA (SRA[2]).
initialized to 00 when the DUART is reset.
16
ISR[7] – Input Port Change Status
IMR – Interrupt Mask Register
This bit is a ‘1’ when a change-of-state has occurred at the IP0, IP1,
IP2, or IP3 inputs and that event has been selected to cause an
interrupt by the programming of ACR[3:0]. The bit is cleared when
the CPU reads the IPCR.
The programming of this register selects which bits in the ISR
causes an interrupt output. If a bit in the ISR is a ‘1’ and the
corresponding bit in the IMR is also a ‘1’ the INTRN output will be
asserted. If the corresponding bit in the IMR is a zero, the state of
the bit in the ISR has no effect on the INTRN output. Note that the
IMR does not mask the programmable interrupt outputs OP3-OP7 or
the reading of the ISR.
ISR[6] – Channel B Change In Break
This bit, when set, indicates that the Channel B receiver has
detected the beginning or the end of a received break. It is reset
when the CPU issues a Channel B ‘reset break change interrupt’
command.
CTUR and CTLR – Counter/Timer Registers
The CTUR and CTLR hold the eight MSBs and eight LSBs,
respectively, of the value to be used by the counter/timer in either
the counter or timer modes of operation. The minimum value which
may be loaded into the CTUR/CTLR registers is H‘0002’. Note that
these registers are write-only and cannot be read by the CPU.
ISR[5] – Channel B Receiver Ready or FIFO Full
The function of this bit is programmed by MR1B[6]. If programmed
as receiver ready, it indicates that a character has been received in
Channel B and is waiting in the FIFO to be read by the CPU. It is set
when the character is transferred from the receive shift register to
the FIFO and reset when the CPU reads the RHR. If after this read
there are more characters still in the FIFO the bit will be set again
after the FIFO is ‘popped’. If programmed as FIFO full, it is set when
In the timer (programmable divider) mode, the C/T generates a
square wave with a period of twice the value (in clock periods) of the
CTUR and CTLR. The waveform so generated is often used for a
18
1998 Sep 04
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCC2692
data clock. The formula for calculating the divisor n to load to the
CTUR and CTLR for a particular 1X data clock is shown below:
In the counter mode, the C/T counts down the number of pulses
loaded into CTUR and CTLR by the CPU. Counting begins upon
receipt of a start counter command. Upon reaching terminal count
H‘0000’, the counter ready interrupt bit (ISR[3]) is set. The counter
continues counting past the terminal count until stopped by the CPU.
If OP3 is programmed to be the output of the C/T, the output
remains High until terminal count is reached, at which time it goes
Low. The output returns to the High state and ISR[3] is cleared when
the counter is stopped by a stop counter command. The CPU may
change the values of CTUR and CTLR at any time, but the new
count becomes effective only on the next start counter commands. If
new values have not been loaded, the previous count values are
preserved and used for the next count cycle
counter clock frequency
n +
16 x 2 x baud rate desired
Often this division will result in a non-integer number; 26.3, for
example. One can only program integer numbers in a digital divider.
Therefore, 26 would be chosen. This gives a baud rate error of
0.3/26.3 which is 1.14%; well within the ability asynchronous mode
of operation.
If the value in CTUR and CTLR is changed, the current half-period
will not be affected, but subsequent half periods will be. The C/T will
not be running until it receives an initial ‘Start Counter’ command
(read at address A3-A0 = 1110). After this, while in timer mode, the
C/T will run continuously. Receipt of a start counter command (read
with A3-A0 = 1110) causes the counter to terminate the current
timing cycle and to begin a new cycle using the values in CTUR and
CTLR.
In the counter mode, the current value of the upper and lower 8 bits
of the counter (CTU, CTL) may be read by the CPU. It is
recommended that the counter be stopped when reading to prevent
potential problems which may occur if a carry from the lower 8 bits
to the upper 8 bits occurs between the times that both halves of the
counter are read. However, note that a subsequent start counter
command will cause the counter to begin a new count cycle using
the values in CTUR and CTLR.
The counter ready status bit (ISR[3]) is set once each cycle of the
square wave. The bit is reset by a stop counter command (read with
A3-A0 = H‘F’). The command however, does not stop the C/T. The
generated square wave is output on OP3 if it is programmed to be
the C/T output.
RESETN
t
RES
SD00133
Figure 3. Reset Timing
19
1998 Sep 04
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCC2692
A0–A3
t
AS
t
AH
CEN
t
t
CH
CS
t
t
RWD
RW
RDN
t
t
DF
DD
NOT
VALID
D0–D7
(READ)
FLOAT
VALID
FLOAT
t
RWD
t
DA
WDN
t
DS
t
DH
D0–D7
(WRITE)
VALID
SD00134
Figure 4. Bus Timing
RDN
t
t
PS
PH
IP0–IP6
(a) INPUT PINS
WRN
t
PD
OP0–OP7
OLD DATA
NEW DATA
(b) OUTPUT PINS
SD00135
Figure 5. Port Timing
20
1998 Sep 04
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCC2692
V
M
WRN
t
IR
1
INTERRUPT
V
+0.5V
OL
OUTPUT
V
OL
V
M
RDN
t
IR
1
INTERRUPT
V
+0.5V
OL
OUTPUT
V
OL
NOTES:
1. INTRN or OP3-OP7 when used as interrupt outputs.
2. The test for open-drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from the midpoint of the switching
signal, V , to a point 0.5V above V . This point represents noise margin that assures true switching has occurred. Beyond this level, the effects of external circuitry and
M
OL
test environment are pronounced and can greatly affect the resultant measurement.
SD00136
Figure 6. Interrupt Timing
t
t
CLK
CTC
+5V
t
Rx
Tx
t
R1
1K
X1/CLK
CTCLK
RxC
X1
X2
U1
TxC
RESISTOR REQUIRED
WHEN U1 IS A TTL DEVICE
t
t
CLK
CTC
NC
t
Rx
t
Tx
SCC2698B
3pF
C1 = C2 = 24pF FOR C = 20PF
L
X1
X2
50 TO
150 KΩ
TO INTERNAL CLOCK DRIVERS
3.6864MHz
4pF
NOTE:
C1 AND C2 SHOULD BE BASED ON MANUFACTURER’S SPECIFICATION. PARASITIC CAPACITANCE SHOULD
BE INCLUDED WITH C1 AND C2. R1 IS ONLY REQUIRED IF U1 WILL NOT DRIVE TO X1 INPUT LEVELS
TYPICAL CRYSTAL SPECIFICATION
FREQUENCY:
LOAD CAPACITANCE (C ):
2 – 4MHZ
12 – 32pF
L
TYPE OF OPERATION:
PARALLEL RESONANT, FUNDAMENTAL MODE
SD00137
Figure 7. Clock Timing
21
1998 Sep 04
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCC2692
1 BIT TIME
(1 OR 16 CLOCKS)
TxC
(INPUT)
t
TXD
TxD
t
TCS
TxC
(1X OUTPUT)
SD00138
Figure 8. Transmitter External
RxC
(1X INPUT)
t
t
RXH
RXS
RxD
SD00139
Figure 9. Receive External Clock
TxD
D1
D2
D3
BREAK
D4
D6
TRANSMITTER
ENABLED
TxRDY
(SR2)
WRN
D1
D2
D3
START
BREAK
D4
STOP
BREAK
D5 WILL
NOT BE
D6
TRANSMITTED
1
CTSN
(IP0)
2
RTSN
(OP0)
OPR(0) = 1
OPR(0) = 1
NOTES:
1. Timing shown for MR2(4) = 1.
2. Timing shown for MR2(5) = 1.
SD00140
Figure 10. Transmitter Timing
22
1998 Sep 04
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCC2692
D1
D2
D3
D4
D5
D6
D7
D8
RxD
D6, D7, D8 WILL BE LOST
RECEIVER
ENABLED
RxRDY
(SR0)
FFULL
(SR1)
RxRDY/
FFULL
2
(OP5)
RDN
STATUS DATA
STATUS DATA STATUS DATA STATUS DATA
D5 WILL
BE LOST
D1
D2
D3
D4
OVERRUN
(SR4)
RESET BY COMMAND
1
RTS
(OP0)
OPR(0) = 1
NOTES:
1. Timing shown for MR1(7) = 1.
2. Shown for OPCR(4) = 1 and MR(6) = 0.
SD00141
Figure 11. Receiver Timing
MASTER STATION
TxD
BIT 9
BIT 9
BIT 9
1
ADD#1
1
D0
0
ADD#2
TRANSMITTER
ENABLED
TxRDY
(SR2)
WRN
MR1(4–3) = 11
MR1(2) = 1
ADD#1 MR1(2) = 0 D0
MR1(2) = 1 ADD#2
PERIPHERAL STATION
BIT 9
BIT 9
1
BIT 9
0
BIT 9
BIT 9
0
0
ADD#1
D0
ADD#2 1
RxD
RECEIVER
ENABLED
RxRDY
(SR0)
RDN/WRN
MR1(4–3) = 11
ADD#1
STATUS DATA
STATUS DATA
ADD#2
D0
SD00142
Figure 12. Wake-Up Mode
23
1998 Sep 04
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCC2692
RTS can also be controlled by the commands 1000 and 1001 in the
command register. RTS is expressed at the OP0 or OP1 pin which
is still an output port. Therefore, the state of OP0 or OP1 should be
set low (either by commands of the CR register or by writing to the
Set Output Ports Register) for the receiver to generate the proper
RTS signal. The logic at the output is basically a NAND of the OPR
register and the RTS signal as generated by the receiver. When the
RTS flow control is selected via the MR(7) bit state of the OPR
register is not changed. Terminating the use of “Flow Control” (via
the MR registers) will return the OP0 or OP1 pins to the control of
the OPR register.
2.7K
+5V
INTRN
50pF
750Ω
D0–D7
TxDA/B
OP0–OP7
2.15V
150pF
SD00143
Figure 13. Test Conditions on Outputs
Transmitter Disable Note
Output Port Notes
The sequence of instructions enable transmitter — load transmit
holding register — disable transmitter will result in nothing being
sent if the time between the end of loading the transmit holding
register and the disable command is less that 3/16 bit time in the
16x mode or one bit time in the 1x mode. Also, if the transmitter,
while in the enabled state and underrun condition, is immediately
disabled after a single character is loaded to the transmit holding
register, that character will not be sent.
The output ports are controlled from four places: the OPCR register,
the OPR register, the MR registers and the command register. The
OPCR register controls the source of the data for the output ports
OP2 through OP7. The data source for output ports OP0 and OP1 is
controlled by the MR and CR registers. When the OPR is the source
of the data for the output ports, the data at the ports is inverted from
that in the OPR register. The content of the OPR register is
controlled by the “Set Output Port Bits Command” and the “Reset
Output Bits Command”. These commands are at E and F,
respectively. When these commands are used, action takes place
only at the bit locations where ones exist. For example, a one in bit
location 5 of the data word used with the “Set Output Port Bits”
command will result in OPR5 being set to one. The OP5 would then
In general, when it is desired to disable the transmitter before the
last character is sent AND the TxEMT bit is set in the status register
(TxEMT is always set if the transmitter has underrun or has just
been enabled), be sure the TxRDY bit is active immediately before
issuing the transmitter disable instruction. TxRDY sets at the end of
the “start bit” time. It is during the start bit that the data in the
transmit holding register is transferred to the transmit shift register.
be set to zero (V ). Similarly, a one in bit position 5 of the data
SS
word associated with the “Reset Output Ports Bits” command would
set OPR5 to zero and, hence, the pin OP5 to a one (V ).
DD
Table 6. Baud Rates Extended
Normal BRG
BRG Test
The CTS, RTS, CTS Enable Tx signals
CTS (Clear To Send) is usually meant to be a signal to the
transmitter meaning that it may transmit data to the receiver. The
CTS input is on pin IP0 for TxA and on IP1 for TxB. The CTS signal
is active low; thus, it is called CTSAN for TxA and CTSBN for TxB.
CSR[7:4] ACR[7] = 0 ACR[7] = 1 ACR[7] = 0 ACR[7] = 1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
50
75
4,800
880
7,200
880
110
110
134.5
200
134.5
150
1,076
19.2K
28.8K
57.6K
115.2K
1,050
57.6K
4,800
57.6K
9,600
38.4K
Timer
1,076
14.4K
28.8K
57.6K
115.2K
2,000
57.6K
4,800
14.4K
9,600
19.2K
Timer
RTS is usually meant to be a signal from the receiver indicating that
the receiver is ready to receive data. It is also active low and is,
thus, called RTSAN for RxA and RTSBN for RxB. RTSAN is on pin
OP0 and RTSBN is on OP1. A receiver’s RTS output will usually be
connected to the CTS input of the associated transmitter. Therefore,
one could say that RTS and CTS are different ends of the same
wire!
300
300
600
600
1,200
1,050
2,400
4,800
7,200
9,600
38.4K
Timer
1,200
2,000
2,400
4,800
1,800
9,600
19.2K
Timer
MR2(4) is the bit that allows the transmitter to be controlled by the
CTS pin (IP0 or IP1). When this bit is set to one AND the CTS input
is driven high, the transmitter will stop sending data at the end of the
present character being serialized. It is usually the RTS output of the
receiver that will be connected to the transmitter’s CTS input. The
receiver will set RTS high when the receiver FIFO is full AND the
start bit of the fourth character is sensed. Transmission then stops
with four valid characters in the receiver. When MR2(4) is set to one,
CTSN must be at zero for the transmitter to operate. If MR2(4) is set
to zero, the IP pin will have no effect on the operation of the
transmitter.
I/O2 – 16X I/O2 – 16X I/O2 – 16X I/O2 – 16X
I/O2 – 1X I/O2 – 1X I/O2 – 1X I/O2 – 1X
NOTE:
Each read on address H‘2’ will toggle the baud rate test mode.
When in the BRG test mode, the baud rates change as shown to the
left. This change affects all receivers and transmitters on the DUART.
See “Extended baud rates for SCN2681, SCN68681, SCC2691,
SCC2692, SCC68681 and SCC2698B” in application notes
elsewhere in this publication
MR1(7) is the bit that allows the receiver to control OP0. When OP0
(or OP1) is controlled by the receiver, the meaning of that pin will be
RTS. However, a point of confusion arises in that OP0 (or OP1) may
also be controlled by the transmitter. When the transmitter is
controlling this pin, its meaning is not RTS at all. It is, rather, that the
transmitter has finished sending its last data byte. Programming the
OP0 or OP1 pin to be controlled by the receiver and the transmitter
at the same time is allowed, but would usually be incompatible.
The test mode at address H‘A’ changes all transmitters and
receivers to the 1x mode and connects the output ports to some
internal nodes.
24
1998 Sep 04
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCC2692
A condition that occurs infrequently has been observed where the receiver will ignore all data. It is caused by a corruption of the start bit
generally due to noise. When this occurs the receiver will appear to be asleep or locked up. The receiver must be reset for the UART to
continue to function properly.
Reset in the Normal Mode (Receiver Enabled)
Recovery can be accomplished easily by issuing a receiver software reset followed by a receiver enable. All receiver data, status and
programming will be preserved and available before reset. The reset will NOT affect the programming.
Reset in the Wake-Up Mode (MR1[4:3] = 11)
Recovery can also be accomplished easily by first exiting the wake-up mode (MR1[4:3] = 00 or 01 or 10), then issuing a receiver software
reset followed by a wake-up re-entry (MR1[4:3] = 11). All receiver data, status and programming will be preserved and available before
reset. The reset will NOT affect the programming.
The receiver has a digital filter designed to reject “noisy” data transitions and the receiver state machine was designed to reject noisy start
bits or noise that might be considered a start bit. In spite of these precautions, corruption of the start bit can occur in 15ns window
–5
approximately 100ns prior to the rising edge of the data clock. The probability of this occurring is less than 10 at 9600 baud.
A corrupted start bit may have some deleterious effects in ASYNC operation if it occurs within a normal data block. The receiver will tend
to align its data clock to the next ‘0’ bit in the data stream, thus potentially corrupting the remainder of the data block. A good design
practice, in environments where start bit corruption is possible, is to monitor data quality (framing error, parity error, break change and
received break) and “data stopped” time out periods. Time out periods can be enabled using the counter/timer in the SCC2691, SCC2692,
SCC2698B and SC68692 products. This monitoring can indicate a potential start bit corruption problem.
SD00097
25
1998 Sep 04
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCC2692
DIP40: plastic dual in-line package; 40 leads (600 mil)
SOT129-1
26
1998 Sep 04
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCC2692
DIP28: plastic dual in-line package; 28 leads (600 mil)
SOT117-1
27
1998 Sep 04
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCC2692
PLCC44: plastic leaded chip carrier; 44 leads
SOT187-2
28
1998 Sep 04
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCC2692
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
29
1998 Sep 04
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCC2692
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 09-98
Document order number:
9397 750 04359
Philips
Semiconductors
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