SCM63P733ATQ133R [NXP]
IC,SYNC SRAM,128KX32,CMOS,QFP,100PIN,PLASTIC;
| 型号： | SCM63P733ATQ133R |
| 厂家： | 
NXP |
| 描述： | IC,SYNC SRAM,128KX32,CMOS,QFP,100PIN,PLASTIC 静态存储器 内存集成电路 |
| 文件： | 总17页 (文件大小：380K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
MOTOROLA
Order this document
by MCM63P733A/D
MCM63P733A
SCM63P733A
128K x 32 Bit Pipelined
BurstRAM Synchronous
Fast Static RAM
The MCM63P733A and SCM63P733A are 4M–bit synchronous fast static
RAMs designed to provide a burstable, high performance, secondary cache.
The MCM63P733A and SCM63P733A (organized as 128K words by 32 bits)
are fabricated in Motorola’s high performance silicon gate CMOS technology.
These devices integrate input registers, an output register, a 2–bit address
counter, and high speed SRAM onto a single monolithic circuit for reduced
parts count in cache data RAM applications. Synchronous design allows
precise cycle control with the use of an external clock (K). CMOS circuitry re-
duces the overall power consumption of the integrated functions for greater
reliability.
TQ PACKAGE
TQFP
CASE 983A–01
Addresses (SA), data inputs (DQx), and all control signals except output
enable (G) and Linear Burst Order (LBO) are clock (K) controlled through
positive–edge–triggered noninverting registers.
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst
addresses can be generated internally by the MCM63P733A and SCM63P733A
(burstsequenceoperatesinlinearorinterleavedmodedependentuponthestate
of LBO) and controlled by the burst address advance (ADV) input pin.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
Synchronous byte write (SBx), synchronous global write (SGW), and synchro-
nous write enable (SW) are provided to allow writes to either individual bytes or
to all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa controls
DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte
writes SBx are asserted with SW. All bytes are written if either SGW is asserted
or if all SBx and SW are asserted.
For read cycles, pipelined SRAMs output data is temporarily stored by an
edge–triggeredoutput register and then released to the output buffers at the next
rising edge of clock (K).
TheMCM63P733AandSCM63P733Aoperatefroma3.3Vcorepowersupply
and all outputs operate on a 2.5 V or 3.3 V power supply. All inputs and outputs
are JEDEC standard JESD8–5 compatible.
•
MCM63P733A–150 = 3.8 ns Access/6.7 ns Cycle (150 MHz)
MCM63P733A/SCM63P733A–133 = 4 ns Access/7.5 ns Cycle (133 MHz)
MCM63P733A–117 = 4.2 ns Access/8.5 ns Cycle (117 MHz)
MCM63P733A–100 = 4.5 ns Access/10 ns Cycle (100 MHz)
MCM63P733A–90 = 5 ns Access/11 ns Cycle (90 MHz)
3.3 V +10%,–5% Core, Power Supply, 2.5 V or 3.3 V I/O Supply
ADSP, ADSC, and ADV Burst Control Pins
Selectable Burst Sequencing Order (Linear/Interleaved)
Internally Self–Timed Write Cycle
Byte Write and Global Write Control
Single–Cycle Deselect
Sleep Mode (ZZ)
–40° to 85°C Extended Operating Temperatures (SCM63P733A only)
100–Pin TQFP Package
•
•
•
•
•
•
•
•
•
REV 5
9/21/99
Motorola, Inc. 1999
For More Information On This Product,
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Freescale Semiconductor, Inc.
FUNCTIONAL BLOCK DIAGRAM
LBO
ADV
K
BURST
2
17
COUNTER
ADSC
ADSP
128K x 32 ARRAY
K2
CLR
2
SA
SA1
SA0
17
15
ADDRESS
REGISTER
SGW
SW
WRITE
REGISTER
a
32
32
SBa
WRITE
REISTER
b
SBb
SBc
SBd
4
DATA–IN
REGISTER
DATA–OUT
REGISTER
WRITE
REGISTER
c
K
WRITE
REGISTER
d
K2
K
SE1
SE2
SE3
ENABLE
REGISTER
ENABLE
REGISTER
G
DQa – DQd
MCM63P733A•SCM63P733A
2
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PIN ASSIGNMENT
10099 9897 9695 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
DQc
DQc
DDQ
1
2
3
4
5
6
7
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
DQb
DQb
V
V
DDQ
SS
V
SS
V
DQc
DQc
DQc
DQc
DQb
DQb
DQb
DQb
8
9
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SS
V
V
DQb
DQb
SS
DDQ
V
DDQ
DQc
DQc
NC
V
SS
V
DD
NC
V
NC
DD
V
DQd
DQd
SS
ZZ
DQa
DQa
V
V
DDQ
V
V
DDQ
SS
V
SS
DQd
DQd
DQd
DQd
DQa
DQa
DQa
DQa
V
V
SS
SS
V
DDQ
DQd
DQd
NC
DDQ
DQa
DQa
NC
31 3233 343536 3738 3940 414243 444546 4748 49 50
MCM63P733A•SCM63P733A
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PIN DESCRIPTIONS
Pin Locations
Symbol
Type
Description
85
ADSC
Input
Synchronous Address Status Controller: Active low, interrupts any
ongoing burst and latches a new external address. Used to initiate a
READ, WRITE, or chip deselect.
84
ADSP
Input
Synchronous Address Status Processor: Active low, interrupts any
ongoing burst and latches a new external address. Used to initiate a
new READ, WRITE, or chip deselect (exception — chip deselect
does not occur when ADSP is asserted and SE1 is high).
83
ADV
DQx
Input
I/O
Synchronous Address Advance: Increments address count in
accordance with counter type selected (linear/interleaved).
(a) 52, 53, 56, 57, 58, 59, 62, 63
(b) 68, 69, 72, 73, 74, 75, 78, 79
(c) 2, 3, 6, 7, 8, 9, 12, 13
Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b, c, d).
(d) 18, 19, 22, 23, 24, 25, 28, 29
86
89
G
K
Input
Input
Asynchronous Output Enable Input.
Clock: This signal reisters the address, data in, and all control
signals except , LBO, and ZZ.
31
LBO
Input
Linear Brst Order Input: This pin may be left floating; it will default
as interleaved.
Low — linear burst counter.
High — interleaved burst counter.
32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50,
81, 82, 99, 100
SA
Input
Input
Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
36, 37
SA1, SA0
Synchronous Address Inputs: These pins must be wired to the two
LSBs of the address bus for proper burst operation. These inputs
are registered and must meet setup and hold times.
93, 94, 95, 96
(a) (b) (c) (d)
SBx
SE1
Input
Input
Synchronous Byte Write Inputs: “x” refers to the byte being written
(byte a, b, c, d). SGW overrides SBx.
98
Synchronous Chip Enable: Active low to enable chip.
Negated high — blocks ADSP or deselects chip when ADSC is
asserted.
97
92
88
SE2
SE3
Input
Input
Input
Synchronous Chip Enable: Active high for depth expansion.
Synchronous Chip Enable: Active low for depth expansion.
SGW
Synchronous Global Write: This signal writes all bytes regardless of
the status of the SBx and SW signals. If only byte write signals SBx
are being used, tie this pin high.
87
64
SW
ZZ
Input
Input
Synchronous Write: This signal writes only those bytes that have
been selected using the byte write SBx pins. If only byte write
signals SBx are being used, tie this pin low.
Sleep Mode: This active high asynchronous signal places the RAM
into the lowest power mode. The ZZ pin disables the RAMs internal
clock when placed in this mode. When ZZ is negated, the RAM
remains in low power mode until it is commanded to READ or
WRITE. Data integrity is maintained upon returning to normal
operation.
15, 41, 65, 91
V
Supply
Supply
Supply
Core Power Supply.
I/O Power Supply.
Ground.
DD
4, 11, 20, 27, 54, 61, 70, 77
V
DDQ
5, 10, 17, 21, 26, 40, 55, 60, 67,
71, 76, 90
V
SS
1, 14, 16, 30, 38, 39, 42, 43, 51, 66, 80
NC
—
No Connection: There is no connection to the chip.
MCM63P733A•SCM63P733A
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TRUTH TABLE (See Notes 1 through 5)
Address
Used
3
2, 4
Next Cycle
Deselect
SE1
1
SE2
X
X
0
SE3
X
1
ADSP
ADSC
ADV
X
X
X
X
X
X
X
0
G
DQx
High–Z
High–Z
High–Z
High–Z
High–Z
High–Z
High–Z
High–Z
DQ
Write
None
None
X
0
0
1
1
0
1
1
1
X
X
1
1
X
X
1
1
X
1
X
0
X
X
0
0
X
0
1
1
1
1
1
1
1
1
0
1
1
1
1
X
X
X
X
X
X
X
Deselect
0
X
X
X
X
X
X
1
Deselect
None
0
X
1
Deselect
None
X
X
0
X
0
Deselect
None
X
0
Begin Read
Begin Read
Continue Read
Continue Read
Continue Read
Continue Read
Suspend Read
Suspend Read
Suspend Read
Suspend Read
Begin Write
External
External
Next
1
0
1
0
READ
X
X
1
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
0
READ
READ
READ
READ
READ
READ
READ
READ
WRITE
WRITE
WRITE
WRITE
WRITE
Next
0
Next
0
1
High–Z
DQ
Next
1
0
0
Current
Current
Current
Current
External
Next
X
X
1
1
1
High–Z
DQ
1
0
1
1
High–Z
DQ
1
1
0
0
X
0
X
X
X
X
X
High–Z
High–Z
High–Z
High–Z
High–Z
Continue Write
Continue Write
Suspend Write
Suspend Write
NOTES:
X
1
X
X
X
X
X
X
X
X
Next
0
Current
Current
X
1
1
1
1. X = Don’t Care. 1 = logic high. 0 = logic low.
2. Write is defined as either 1) any SBx and SW low, or 2) SGW is low.
3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (t
) following G going low.
GLQX
4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times.
G must also remain negated at the completion of the write cycle to ensure proper write data hold times.
ASYNCHRONOUS TRUTH TABLE
Operation
Read
ZZ
L
G
L
I/O Status
Data Out (DQx)
High–Z
Read
L
H
X
X
X
Write
L
High–Z
Deselected
Selected
L
High–Z
H
High–Z
LINEAR BURST ADDRESS TABLE (LBO = V
)
SS
1st Address (External)
X . . . X00
2nd Address (Internal)
X . . . X01
3rd Address (Internal)
X . . . X10
4th Address (Internal)
X . . . X11
X . . . X01
X . . . X10
X . . . X11
X . . . X00
X . . . X10
X . . . X11
X . . . X00
X . . . X01
X . . . X11
X . . . X00
X . . . X01
X . . . X10
MCM63P733A•SCM63P733A
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INTERLEAVED BURST ADDRESS TABLE (LBO = V
)
DD
1st Address (External)
X . . . X00
2nd Address (Internal)
3rd Address (Internal)
X . . . X10
4th Address (Internal)
X . . . X11
X . . . X01
X . . . X00
X . . . X11
X . . . X10
X . . . X01
X . . . X11
X . . . X10
X . . . X10
X . . . X00
X . . . X01
X . . . X11
X . . . X01
X . . . X00
WRITE TRUTH TABLE
Cycle Type
SGW
H
SW
H
L
SBa
X
SBb
X
SBc
X
SBd
X
Read
Read
H
H
H
H
H
Write Byte a
Write Byte b
Write Byte c
Write Byte d
Write All Bytes
Write All Bytes
H
L
L
H
H
H
H
L
H
L
H
H
H
L
H
H
L
H
H
L
H
H
H
L
H
L
L
L
L
L
L
X
X
X
X
X
ABSOLUTE MAXIMUM RATINGS (See Note 1)
This device contains circuitry to protect the
Rating
Power Supply Voltage
I/O Supply Voltage
Symbol
Value
Unit
V
Notes
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high–impedance
circuit.
V
DD
–0.5 to 4.6
V
DDQ
V
– 0.5 to V
V
SS
DD
Input Voltage Relative to V
Any Pin Except V
DD
for
V , V
in out
–0.5 to V
+ 0.5
V
SS
DD
Input Voltage (Three–State I/O)
Output Current (per I/O)
Package Power Dissipation
Temperature Under Bias
Storage Temperature
NOTES:
V
–0.5 to V
+ 0.5
V
mA
W
IT
DDQ
I
±20
1.2
out
P
2
D
T
bias
–10 to 85
°C
°C
T
stg
–55 to 125
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposuretohigherthanrecommendedvoltagesforextended
periods of time could affect device reliability.
2. Power dissipation capability is dependent upon package characteristics and use
environment. See Package Thermal Characteristics.
PACKAGE THERMAL CHARACTERISTICS
Rating
Symbol
Max
Unit
Notes
Junction to Ambient (@ 200 lfm)
Single–Layer Board
Four–Layer Board
R
40
25
°C/W
1, 2
θJA
Junction to Board (Bottom)
Junction to Case (Top)
NOTES:
R
R
17
9
°C/W
°C/W
3
4
θJB
θJC
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, board population, and board thermal resistance.
2. Per SEMI G38–87.
3. Indicates the average thermal resistance between the die and the printed circuit board.
4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883
Method 1012.1).
MCM63P733A•SCM63P733A
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DC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 3.3 V +10%, –5%, T = 0° to 70°C for MCM63P733A,
DD
T = –40° to 85°C for SCM63P733A, Unless Otherwise Noted)
A
A
RECOMMENDED OPERATING CONDITIONS: 2.5 V I/O Supply (Voltages Referenced to V
SS
= 0 V)
Typ
Parameter
Symbol
Min
3.135
2.375
–0.3
1.7
Max
3.6
2.9
0.7
Unit
V
Supply Voltage
V
DD
3.3
2.5
—
I/O Supply Voltage
Input Low Voltage
V
DDQ
V
V
IL
V
Input High Voltage
Input High Voltage (I/O Pins)
V
IH
—
V
DD
+ 0.3
V
V
IH2
1.7
—
V
DDQ
+ 0.3
V
Output Low Voltage (I
= 2 mA)
V
OL
—
—
0.7
V
OL
Output High Voltage (I
= –2 mA)
V
OH
1.7
—
—
V
OH
RECOMMENDED OPERATING CONDITIONS: 3.3 V I/O Supply (Voltages Referenced to V
SS
= 0 V)
Parameter
Symbol
Min
3.135
3.135
–0.5
2
Typ
3.3
3.3
—
Max
Unit
V
Supply Voltage
V
DD
3.6
I/O Supply Voltage
Input Low Voltage
V
DDQ
V
DD
V
V
IL
0.8
V
Input High Voltage
Input High Voltage (I/O Pins)
V
IH
—
V
+ 0.5
V
DD
V
IH2
2
—
V
DDQ
+ 0.5
V
Output Low Voltage (I
= 8 mA)
V
OL
—
—
0.4
V
OL
Output High Voltage (I
= –4 mA)
V
OH
2.4
—
—
V
OH
V
IH
V
SS
V
– 1.0 V
SS
20% t
(MIN)
KHKH
Figure 1. Undershoot Voltage
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SUPPLY CURRENTS
Parameter
Symbol
Min
—
Typ
—
Max
±1
Unit
µA
Notes
Input Leakage Current (0 V ≤ V ≤ V
)
I
1, 2
in DD
lkg(I)
Output Leakage Current (0 V ≤ V ≤ V
)
I
lkg(O)
—
—
±1
µA
in
DDQ
AC Supply Current (Device
MCM63P733A–150
I
—
—
470
440
415
390
375
mA
3, 4, 5
DDA
Selected, All Outputs
Open, Freq = Max)
MCM63P733A/SCM63P733A–133
MCM63P733A–117
Includes V
DD
Only
MCM63P733A–100
MCM63P733A–90
CMOS Standby Supply Current (Device Deselected, Freq = 0,
= Max, All Inputs Static at CMOS Levels)
I
—
—
—
—
5
mA
mA
6, 8
SB2
V
DD
Sleep Mode Supply Current (Sleep Mode, Freq = Max,
= Max, All Other Inputs Static at CMOS Levels,
I
5
2, 7, 8
ZZ
V
DD
ZZ ≥ V
– 0.2 V)
DD
TTL Standby Supply Current (Device Deselected, Freq = 0,
= Max, All Inputs Static at TTL Levels)
I
—
—
—
—
25
mA
mA
6, 9
SB3
V
DD
Clock Running (Device
Deselected, Freq = Max, MCM63P733A/SCM63P733A–133
MCM63P733A–150
I
160
150
140
130
120
3, 4,
5, 6, 8
SB4
V
= Max, All Inputs
MCM63P733A–117
MCM63P733A–100
MCM63P733A–90
DD
Toggling at CMOS Levels)
Static Clock Running (Device
Deselected, Freq = Max, MCM63P733A/SCM63P733A–133
MCM63P733A–150
I
—
—
60
50
45
40
40
mA
6, 9
SB5
V
= Max, All Inputs
MCM63P733A–117
MCM63P733A–100
MCM63P733A–90
DD
Static at TTL Levels)
NOTES:
1. LBO pin has an internal pull–up and ill exhibit leakage currents of ±5 µA.
2. ZZ pin has an internal pull–down and will exhibit leakage currents of ±5 µA.
3. Reference AC Operating Conditions and Characteristics for input and timing.
4. All addresses transitiosimultaneously low (LSB) then high (MSB).
5. Data states are all zero.
6. Device is deselected as defined by the Truth Table.
7. Device in Sleep Mode as defined by the Asynchronous Truth Table.
8. CMOS levels for I/Os are V ≤ V
+ 0.2 V or ≥ V
– 0.2 V. CMOS levels for other inputs are V ≤ V
+ 0.2 V or ≥ V
– 0.2 V.
IT SS
DDQ
in SS
DD
9. TTL levels for I/Os are V ≤ V or ≥ V
. TTL levels for other inputs are V ≤ V or ≥ V .
in IL IH
IT IL IH2
CAPACITANCE (f = 1.0 MHz, T = 0° to 70°C, Periodically Sampled Rather Than 100% Tested)
A
Parameter
Symbol
Min
—
Typ
Max
5
Unit
pF
Input Capacitance
C
4
7
in
Input/Output Capacitance
C
—
8
pF
I/O
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AC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 3.3 V +10%, –5%, T = 0° to 70°C for MCM63P733A,
DD
T = –40° to 85°C for SCM63P733A, Unless Otherwise Noted)
A
A
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . 1.0 V/ns (20% to 80%)
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . See Figure 2 Unless Otherwise Noted
READ/WRITE CYCLE TIMING (See Notes 1 through 4)
MCMxxx–133
SCMxxx–133
MCMxxx–150
MCMxxx–117
MCMxxx–100
MCMxxx–90
Parameter
Cycle Time
Symbol
Unit Notes
Min
6.7
2.6
Max
—
Min
7.5
3
Max
—
Min
8.5
3.4
Max
—
Min
10
4
Max
—
Min
11
Max
—
t
ns
ns
KHKH
Clock High Pulse
Width
t
—
—
—
—
4.4
—
KHKL
KLKH
KHQV
Clock Low Pulse
Width
t
2.6
—
3
—
3.4
—
4
—
4.4
—
ns
Clock Access Time
t
—
—
3.8
3.8
—
—
4
—
—
4.2
3.8
—
—
4.5
4.5
—
—
5
5
ns
ns
Output Enable to
Output Valid
t
3.8
GLQV
Clock High to Output
Active
t
t
0
—
—
0
1.5
0
—
—
0
1.5
0
—
—
0
1.5
0
—
—
0
1.5
0
—
—
—
5
ns
ns
ns
ns
ns
ns
5, 6
6
KHQX1
KHQX2
Clock High to Output
Change
1.5
0
Output Enable to
Output Active
t
—
—
—
—
5, 6
5, 6
5, 6
GLQX
GHQZ
Output Disable to Q
High–Z
t
—
3.8
6.7
—
—
1.5
2
3.8
7.5
—
—
1.5
2
3.8
8.5
—
—
1.5
2
4.5
10
—
—
1.5
2
Clock High to Q
High–Z
t
1.5
1.5
11
—
KHQZ
Setup Times:
Address
ADSP, ADSC, ADV
Data In
t
ADKH
t
ADSKH
t
DVKH
Write
Chip Enable
t
WVKH
t
EVKH
Hold Times:
Address
ADSP, ADSC, ADV
Data In
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
ns
t
KHAX
t
KHADSX
t
KHDX
Write
Chip Enable
t
KHWX
t
KHEX
Sleep Mode Standby
t
—
2 x
—
2 x
—
2 x
—
2 x
—
2 x
ns
ns
ns
ZZS
t
t
t
t
t
KHKH
—
KHKH
—
KHKH
—
KHKH
—
KHKH
—
Sleep Mode
Recovery
t
2 x
2 x
2 x
2 x
2 x
ZZREC
t
t
t
t
t
KHKH
—
KHKH
—
KHKH
—
KHKH
—
KHKH
—
Sleep Mode High to
Q High–Z
t
15
15
15
15
15
ZZQZ
NOTES:
1. Write is defined as either any SBx and SW low or SGW is low. Chip Enable is defined as SE1 low, SE2 high, and SE3 low whenever ADSP
or ADSC is asserted.
2. All read and write cycle timings are referenced from K or G.
3. G is a don’t care after write cycle begins. To prevent bus contention, G should be negated prior to start of write cycle.
4. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between
data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at V
/2. In some
DDQ
designexercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is given
in the AC Test Conditions section of the data sheet as 1 V/ns, one can easily interpolate timing values to other reference levels.
5. This parameter is sampled and not 100% tested.
6. Measured at ±200 mV from steady state.
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OUTPUT
Z
= 50 Ω
R
= 50 Ω
0
L
1.5 V
Figure 2. AC Test Load
2400
2200
2000
1800
1600
1400
OUTPUT
1200
1000
C
L
800
600
400
200
0
0
20
40
60
80
100
LUMPED CAPACITANCE, C (pF)
L
Figure 3. Lumped Capacitive Load and Typical Derating Curve
MCM63P733A•SCM63P733A
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2.9
2.5
PULL–UP
I (mA) MIN
2.3
VOLTAGE (V)
I (mA) MAX
–0.5
0
–38
–38
–38
–30
–105
–105
–105
0.8
1.25
1.25
0.8
–83
1.5
2.3
2.7
2.9
–27
0
–75
–40
–15
0
0
0
0
0
–40
CURRENT (mA)
–105
(a) Pull–Up for V
= 2.5 V
DDQ
3.6
3.135
2.8
PULL–UP
VOLTAGE (V)
I (mA) MIN
I (mA) MAX
–120
–120
–120
– 08
–0.5
0
–40
–40
–40
–37
–28
0
1.65
1.4
1.4
1.65
2.0
–81
3.135
3.6
–20
0
0
0
0
–40
CURRENT (mA)
–80
–120
(b) Pull–Up: V
= 3.3 V
DDQ
V
DD
PULL–DOWN
VOLTAGE (V)
I (mA) MIN
I (mA) MAX
–0.5
0
0
0
1.6
0
0
0.4
0.8
1.25
1.6
2.8
10
20
31
40
40
20
40
63
80
80
1.25
0.3
0
3.2
3.4
40
40
80
80
0
40
80
CURRENT (mA)
(c) Pull–Down
Figure 4. Typical Output Buffer Characteristics
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12
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APPLICATION INFORMATION
SLEEP MODE
may continue to run without impacting the RAMs sleep cur-
rent (I ). All inputs are allowed to toggle — the RAM will not
be selected and perform any reads or writes. However, if
ZZ
A sleep mode feature, the ZZ pin, has been implemented
on the MCM63P733A and SCM63P733A. It allows the sys-
tem designer to place the RAM in the lowest possible power
condition by asserting ZZ. The Sleep Mode Timing diagram
shows the different modes of operation: Normal Operation,
No READ/WRITE Allowed, and Sleep Mode. Each mode has
its own set of constraints and conditions that are allowed.
Normal Operation: All inputs must meet setup and hold
inputs toggle, the I (max) specification will not be met.
ZZ
NON–BURST SYNCHRONOUS OPERATION
Although this BurstRAM has been designed for high–end
MPU–based systems, these SRAMs can be used in other
high speed memory applications that do not require the burst
address feature. Most L2 caches designed with a synchro-
nous interface can make use of the MCM63P733A and
SCM63P733A. The burst counter feature of the BurstRAM
can be disabled, and the SRAM can be configured to act
upon a continuous stream of addresses. See Figure 5.
timespriortosleepandt
nanosecondsafterrecovering
ZZREC
from sleep. Clock (K) must also meet cycle high and low
times during these periods. Two cycles prior to sleep, initi-
ation of either a read or write operation is not allowed.
No READ/WRITE: During the period of time just prior to
sleep and during recovery from sleep, the assertion of either
ADSC, ADSP, or any write signal is not allowed. If a write
operation occurs during these periods, the memory array
may be corrupted. Validity of data out from the RAM can not
be guaranteed immediately after ZZ is asserted (prior to
being in sleep).
CONTROL PIN TIE VALUES EXAMPLE (H ≥ V , L ≤ V
)
IH IL
Non–Burst
ADSP ADSC ADV SE1 SE2 LBO
Sync Non–Burst,
Pipelined SRAM
H
L
H
L
H
X
Sleep Mode: The RAM automatically deselects itself. The
RAM disconnects its internal clock buffer. The external clock
NOTE: Although X is specified in the table as a don’t care, the pin
must be tied either high or low.
K
ADDR
SE3
W
A
B
C
D
E
F
G
H
G
DQ
Q(A)
Q(B)
Q(C)
Q(D)
D(E)
D(F)
D(G)
D(H)
READS
WRITES
Figure 5. Example Configuration as Non–Burst Synchronous SRAM
MCM63P733A•SCM63P733A
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ORDERING INFORMATION
(Order by Full Part Number)
SCM
MCM
63P733A XX
X
X
Blank = Trays, R = Tape and Reel
Motorola Memory Prefix
Part Number
Speed (150 = 150 MHz, 133 = 133 MHz,
117 = 117 MHz, 100 = 100 MHz, 90 = 90 MHz)
Package (TQ = TQFP)
Full Part Numbers — MCM63P733ATQ150 MCM63P733ATQ150R
MCM63P733ATQ133 MCM63P733ATQ133R
MCM63P733ATQ117 MCM63P733ATQ117R
MCM63P733ATQ100 MCM63P733ATQ100R
MCM63P733ATQ90
MCM63P733ATQ90R
SCM63P733ATQ133 SCM63P733ATQ133R
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PACKAGE DIMENSIONS
TQ PACKAGE
100–PIN TQFP
CASE 983A–01
4X
80
e
0.20 (0.008)
H
A–B
D
2X 30 TIPS
0.20 (0.008)
e/2
C
A–B
D
–D–
51
50
81
B
B
–X–
E/2
X=A, B, OR D
–A–
–B–
VIEW Y
E1
E
BASE
META
PLATING
E1/2
b1
31
100
c1
c
1
30
b
D1/2
D/2
D1
D
M
S
S
0.13 (0.005)
C
A–B
D
SECTION B–B
2X 20 TIPS
0.20 (0.008)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
C
A–B
D
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –A–, –B– AND –D– TO BE DETERMINED
AT DATUM PLANE –H–.
A
q2
0.10 (0.004)
C
–H–
5. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE –C–.
–C–
SEATING
PLANE
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE PROTRUSION
IS 0.25 (0.010) PER SIDE. DIMENSIONS D1 AND
B1 DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –H–.
7. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE b DIMENSION TO EXCEED 0.45
(0.018).
q3
VIEW AB
S
0.05 (0.002)
S
q1
R2
MILLIMETERS
INCHES
MIN
0.25 (0.010)
DIM
A
A1
A2
b
MIN
–––
MAX
1.60
0.15
1.45
0.38
0.33
0.20
0.16
MAX
0.063
0.006
0.057
0.015
0.013
0.008
0.006
GAGE PLANE
–––
0.002
0.053
0.009
0.009
0.004
0.004
A2
0.05
1.35
0.22
0.22
0.09
0.09
b1
c
L2
L
R1
A1
c1
D
q
22.00 BSC
0.866 BSC
D1
E
E1
e
20.00 BSC
16.00 BSC
14.00 BSC
0.65 BSC
0.787 BSC
0.630 BSC
0.551 BSC
0.026 BSC
L1
VIEW AB
L
0.45
1.00 REF
0.50 REF
0.75
0.018
0.039 REF
0.020 REF
0.030
L1
L2
S
R1
R2
q
0.20
–––
–––
0.20
7
–––
13
0.008
–––
–––
0.008
7
0.08
0.08
0
0.003
0.003
0
_
_
_
_
q
q
q
1
2
3
0
11
11
0
11
11
–––
13
_
_
_
_
_
_
_
_
13
13
_
_
MCM63P733A•SCM63P733A
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
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