SCM6946TS8 [NXP]
512KX8 STANDARD SRAM, 8ns, PDSO44, TSOP2-44;
| 型号： | SCM6946TS8 |
| 厂家： | 
NXP |
| 描述： | 512KX8 STANDARD SRAM, 8ns, PDSO44, TSOP2-44 信息通信管理 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总9页 (文件大小：318K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MCM6946/D
MCM6946
SCM6946
512K x 8 Bit Static Random
Access Memory
The MCM6946/SCM6946 is a 4,194,304–bit static random access memory or-
ganizedas 524,288 words of 8 bits. Static design eliminates the need for external
clocks or timing strobes.
The MCM6946/SCM6946 is equipped with chip enable (E) and output enable
(G) pins, allowing for greater system flexibility and eliminating bus contention
problems. Either input, when high, will force the outputs into high impedance.
TheMCM6946isavailableina400mil, 36–leadsurface–mountSOJpackage.
YJ PACKAGE
400 MIL SOJ
CASE 893–02
•
•
•
•
•
•
•
Single 3.3 V – 5%, + 10% Power Supply
Fast Access Time: 8/10/12/15 ns
Equal Address and Chip Enable Access Time
All Inputs and Outputs are TTL Compatible
Three–State Outputs
TS PACKAGE
44–LEAD
TSOP TYPE II
CASE 924A–02
Power Operation: 195/185/180/175 mA Maximum, Active AC
Available in TSOP or SOJ Packages
PIN NAMES
A0 – A18 . . . . . . . . . . . . . . . Address Inputs
W . . . . . . . . . . . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . . . . . . . . . Output Enable
E . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable
DQ . . . . . . . . . . . . . . . . . Data Input/Output
NC . . . . . . . . . . . . . . . . . . . . No Connection
BLOCK DIAGRAM
A
A
A
A
A
A
A
A
A
A
V
DD
V
SS
. . . . . . . . . . . . . + 3.3 V Power Supply
. . . . . . . . . . . . . . . . . . . . . . . . . Ground
ROW
MEMORY MATRIX
DECODER
DQ
COLUMN I/O
COLUMN DECODER
INPUT
DATA
CONTROL
DQ
A
A
A
A
A
A
A
A
A
DQ
DQ
E
W
G
REV 8
1/29/99
Motorola, Inc. 1999
For More Information On This Product,
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Freescale Semiconductor, Inc.
PIN ASSIGNMENTS
400 MIL SOJ
TSOP TYPE II
NC
NC
A
1
2
3
4
44
43
42
41
NC
NC
NC
A
A
A
1
2
3
4
5
6
7
8
9
10
36 NC
35
34
33
32
31
A
A
A
A
G
A
A
A
A
A
5
6
7
8
9
40
39
38
37
36
A
A
A
A
A
E
E
G
DQ
DQ
30 DQ
29 DQ
DQ
DQ
DQ
10
11
12
13
14
35
34
33
32
31
DQ
V
28
27
V
V
DD
SS
V
V
V
DD
SS
V
V
SS
DD
SS
DD
DQ
DQ
DQ
DQ
DQ
11
12
13
14
15
16
17
18
26 DQ
25 DQ
DQ
W
A
W
A
15
30
29
28
27
26
25
24
23
A
24
23
22
21
20
A
A
A
A
A
16
17
18
19
A
A
A
A
A
A
A
A
A
A
20
21
22
NC
NC
NC
A
NC
NC
A
19 NC
TRUTH TABLE (X = Don’t Care)
E
H
L
G
X
H
L
W
X
H
H
L
Mode
Not Selected
Output Disabled
Read
I/O Pin
Cycle
—
Current
I , I
SB1 SB2
High–Z
High–Z
—
I
I
I
DDA
DDA
DDA
L
D
Read
Write
out
L
X
Write
High–Z
ABSOLUTE MAXIMUM RATINGS (See Note)
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to these high–impedance
circuits.
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board and
transverse air flow of at least 500 linear feet per
minute is maintained.
Rating
Symbol
Value
– 0.5 to 5.0
– 0.5 to V + 0.5
Unit
Power Supply Voltage Relative to V
V
DD
V
V
SS
Voltage Relative to V
for Any Pin
V , V
in out
SS
DD
Except V
DD
Output Current (per I/O)
I
mA
± 20
1.0
out
Power Dissipation
P
D
W
°C
°C
°C
Temperature Under Bias
Operating Temperature
T
bias
– 10 to 85
0 to 70
T
A
Storage Temperature — Plastic
T
stg
– 55 to 150
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
SCM6946•MCM6946
2
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DC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 3.3 V – 5%, + 10%, T = 0 to 70°C, Unless Otherwise Noted)
DD
A
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
3.135
2.2
Typ
3.3
—
Max
Unit
V
Supply Voltage (Operating Voltage Range)
Input High Voltage
V
DD
3.6
V
IH
V
+ 0.3**
V
DD
Input Low Voltage
V
IL
—
0.8
V
– 0.5*
*V (min) = – 0.5 V dc; V (min) = – 2.0 V ac (pulse width ≤ 2.0 ns).
IL IL
**V (max) = V
+ 0.3 V dc; V (max) = V
+ 2.0 V ac (pulse width ≤ 2.0 ns).
IH IH
DD
DD
DC CHARACTERISTICS
Parameter
Symbol
Min
—
Max
± 1.0
± 1.0
0.4
Unit
µA
µA
V
Input Leakage Current (All Inputs, V = 0 to V
)
I
lkg(I)
in
DD
Output Leakage Current (E = V , V
= 0 to V
)
I
lkg(O)
—
IH out
DD
Output Low Voltage (I
= + 8.0 mA)
V
OL
—
OL
Output High Voltage (I
= – 4.0 mA)
V
OH
2.4
—
V
OH
POWER SUPPLY CURRENTS
Parameter
Symbol
0 to 70°C
Unit
AC Active Supply Current
SCM6946–8: t
= 8 ns
I
195
185
180
175
mA
AVAV
DD
(I
out
= 0 mA, V
= Max)
MCM6946–10: t
MCM6946–12: t
MCM6946–15: t
= 10 ns
= 12 ns
= 15 ns
DD
AVAV
AVAV
AVAV
AC Standby Current (V
DD
= Max, E = V
,
SCM6946–8: t
AVAV
= 8 ns
I
55
50
50
45
mA
mA
IH
No Other Restrictions on Other Inputs)
SB1
MCM6946–10: t
MCM6946–12: t
MCM6946–15: t
= 10 ns
= 12 ns
= 15 ns
AVAV
AVAV
AVAV
CMOS Standby Current (E ≥ V
– 0.2 V, V ≤ V
in
+ 0.2 V or ≥ V – 0.2 V)
DD
I
20
DD
SS
SB2
(V
DD
= Max, f = 0 MHz)
CAPACITANCE (f = 1.0 MHz, dV = 3.3 V, T = 25°C, Periodically Sampled Rather Than 100% Tested)
A
Parameter
Symbol
Typ
Max
Unit
Input Capacitance
All Inputs Except Clocks and DQs
E, G, W
C
4
5
6
8
pF
in
C
ck
Input/Output Capacitance
DQ
C
5
8
pF
I/O
MCM6946•SCM6946
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3
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AC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 3.3 V – 5%, + 10%, T = 0 to 70°C, Unless Otherwise Noted)
DD
A
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
READ CYCLE TIMING (See Notes 1 and 2)
SCM6946–8
MCM6946–10 MCM6946–12 MCM6946–15
Parameter
Read Cycle Time
Symbol
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Min
8
Max
—
8
Min
10
—
—
—
2
Max
—
10
10
5
Min
12
—
—
—
2
Max
—
12
12
6
Min
15
—
—
—
2
Max
—
15
15
7
t
3
AVAV
Address Access Time
t
—
—
—
2
AVQV
Enable Access Time
t
8
4
ELQV
GLQV
AXQX
Output Enable Access Time
Output Hold from Address Change
Enable Low to Output Active
Output Enable Low to Output Active
Enable High to Output High–Z
Output Enable High to Output High–Z
t
t
4
—
—
—
4
—
—
—
5
—
—
—
6
—
—
—
7
t
3
3
3
5, 6, 7
5, 6, 7
5, 6, 7
5, 6, 7
ELQX
GLQX
EHQZ
GHQZ
t
t
0
0
0
0
0
0
0
0
t
0
4
0
5
0
6
0
7
NOTES:
1. W is high for read cycle.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All read cycle timings are referenced from the last valid address to the first transitioning address.
4. Addresses valid prior to or coincident witE going low.
5. At any given voltage and temperature, t
to device.
max
t
min, and t
max
t min, both for a given device and from device
GLQX
EHQZ
ELQX
GHQZ
6. Transition is measured ± 200 mV from steady–state voltage.
7. This parameter is samled and not 100% tested.
8. Device is continuously selected (E ≤ V , G ≤ V ).
IL IL
TIMING LIMITS
The table of timing values shows either a minimum
or a maximum limit for each parameter. Input require-
ments are specified from the external system point of
view. Thus, address setup time is shown as a mini-
mum since the system must supply at least that much
time. On the other hand, responses from the memory
are specified from the device point of view. Thus, the
access time is shown as a maximum since the device
never provides data later than that time.
R
= 50 Ω
L
OUTPUT
Z
= 50 Ω
0
V
= 1.5 V
L
Figure 1. AC Test Load
SCM6946•MCM6946
4
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READ CYCLE 1 (See Note 8)
t
AVAV
A (ADDRESS)
Q (DATA OUT)
t
AXQX
PREVIOUS DATA VALID
DATA VALID
t
AVQV
READ CYCLE 2 (See Note 4)
t
AVAV
A (ADDRESS)
t
ELQV
E (CHIP ENABLE)
t
t
t
t
EHQZ
ELQX
G (OUTPUT ENABLE)
Q (DATA OUT)
t
GLQV
GHQZ
t
GLQX
HIGH–Z
DATA VALID
AVQV
I
DD
SUPPLY CURRENT
I
SB
MCM6946•SCM6946
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WRITE CYCLE 1 (W Controlled; See Notes 1, 2, and 3)
SCM6946–8
MCM6946–10 MCM6946–12 MCM6946–15
Parameter
Write Cycle Time
Symbol
Unit
ns
Notes
Min
8
Max
—
Min
10
0.5
9
Max
—
Min
12
0.5
10
9
Max
—
Min
15
Max
—
t
4
AVAV
Address Setup Time
t
0.5
8
—
—
—
0.5
12
—
ns
AVWL
Address Valid to End of Write
Address Valid to End of Write (G High)
Write Pulse Width
t
—
—
—
—
ns
AVWH
AVWH
t
7
—
8
—
—
10
—
ns
t
t
8
—
9
—
10
—
12
—
ns
WLWH
WLEH
t
Write Pulse Width (G High)
7
—
8
—
9
—
10
—
ns
WLWH
t
WLEH
DVWH
WHDX
Data Valid to End of Write
Data Hold Time
t
t
6
0
0
3
0
—
—
4
6
0
0
3
0
—
—
5
6
0
0
3
0
—
—
6
7
0
0
3
0
—
—
7
ns
ns
ns
ns
ns
Write Low to Data High–Z
Write High to Output Active
Write Recovery Time
NOTES:
t
5, 6, 7
5, 6, 7
WLQZ
t
—
—
—
—
—
—
—
—
WHQX
t
WHAX
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state.
4. All write cycle timings are referenced from the lasvalid address to the first transitioning address.
5. Transition is measured ± 200 mV from steady–state voltage.
6. This parameter is sampled and not 100% tested.
7. At any given voltage and temperaturt
max < t
min, both for a given device and from device to device.
WHQX
WLQZ
WRITE CYCLE 1 (W Controlled; See Notes 1, 2, and 3)
t
AVAV
A (ADDRESS)
t
t
WHAX
AVWH
E (CHIP ENABLE)
t
WLWH
t
WLEH
W (WRITE ENABLE)
D (DATA IN)
t
t
t
WHDX
AVWL
DVWH
DATA VALID
t
t
WLQZ
WHQX
HIGH–Z
HIGH–Z
Q (DATA OUT)
SCM6946•MCM6946
6
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WRITE CYCLE 2 (E Controlled; See Notes 1, 2, and 3)
SCM6946–8
MCM6946–10 MCM6946–12 MCM6946–15
Parameter
Write Cycle Time
Symbol
Unit
ns
Notes
Min
8
Max
—
Min
10
0
Max
—
Min
12
0
Max
—
Min
15
0
Max
—
t
4
AVAV
Address Setup Time
t
0
—
—
—
—
ns
AVEL
Address Valid to End of Write
Address Valid to End of Write (G High)
Enable Pulse Width
t
t
8
—
9
—
10
9
—
12
10
12
—
ns
AVEH
7
—
8
—
—
—
ns
AVEH
t
t
8
—
9
—
10
—
—
ns
5, 6
5, 6
ELEH,
ELWH
Enable Pulse Width (G High)
t
t
7
—
8
—
9
—
10
—
ns
ELEH,
ELWH
Data Valid to End of Write
Data Hold Time
t
t
6
0
0
—
—
—
6
0
0
—
—
—
6
0
0
—
—
—
7
0
0
—
—
—
ns
ns
ns
DVEH
EHDX
Write Recovery Time
NOTES:
t
EHAX
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state.
4. All write cycle timing is referenced from the last valid address to the first transitioning address.
5. If E goes low coincident with or after W goes low, the output will remain in a high–impedance condition.
6. If E goes high coincident with or before W goes high, the output will remain in a high–impedance condition.
WRITE CYCLE 2 (E Controlled; See Notes 1, 2, and 3)
t
AVAV
A (ADDRESS)
t
AVEH
t
ELEH
E (CHIP ENABLE)
t
t
t
EHAX
AVEL
ELWH
W (WRITE ENABLE)
t
DVEH
D (DATA IN)
DATA VALID
t
EHDX
HIGH–Z
Q (DATA OUT)
ORDERING INFORMATION
(Order by Full Part Number)
XCM 6946 XX XX XX
Motorola Memory Prefix
Part Number
Shipping Method (R = Tape and Reel, Blank = Rails)
Speed (8 = 8 ns, 10 = 10 ns, 12 = 12 ns,
15 = 15 ns)
Package (YJ = 400 mil SOJ, TS = 44–Lead
TSOP Type II)
Full Commercial Part Numbers — SCM6946YJ8
SCM6946TS8
MCM6946YJ10
MCM6946YJ10R MCM6946YJ12R MCM6946YJ15R
MCM6946TS10 MCM6946TS12 MCM6946TS15
MCM6946TS10R MCM6946TS12R MCM6946TS15R
MCM6946YJ12
MCM6946YJ15
MCM6946•SCM6946
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PACKAGE DIMENSIONS
YJ PACKAGE
400 MIL SOJ
CASE 893–02
0.015 (0.381)
T
Y
2 ZONES 18 PLACES
NOTE 3
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
0.007 (0.17)
T
Y
X
2. CONTROLLING DIMENSION: INCH.
3. TO BE DETERMINED AT PLANE –T–.
4. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION. MOLD PROTRUSION SHALL NOT
EXCEED 0.006 (0.15) PER SIDE.
C
E
36
19
5. DIMENSION A AND B INCLUDE MOLD MISMATCH
AND ARE DETERMINED AT THE PARTING LINE.
–Y–
INCHES
MILLIMETERS
P
B
R
DIM
A
C
D
E
F
G
K
MIN
MAX
0.930
0.405
0.148
0.020
–––
MIN
23.37
10.03
3.25
0.38
2.08
MAX
23.62
10.29
3.76
0.51
–––
0.920
0.395
0.128
0.015
0.082
0.026
R/2
1
18
0.032
0.66
0.81
36X R R1
0.050 BSC
1.27 BSC
0.035
0.55
0.90
1.40
36X F
L
N
P
0.025 BSC
0.64 BSC
0.035
0.435
0.045
0.445
0.90
1.14
11.05
11.30
R
R1
0.370 BSC
9.40 BSC
–X–
0.030
0.040
0.76
1.02
36X N
A
K
0.004 (0.1)
T
SEATING
PLANE
–T–
36X D
0.007 (0.17)
2X
L
M
S
S
T
Y
X
VIEW A
NOTE 3
34X
G
VIEW A
SCM6946•MCM6946
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TS PACKAGE
44–LEAD
TSOP TYPE II
CASE 924A–02
VIEW A
B
44
23
E1
A
A
1
22
A2
A
A
D
22X E
M
0.2
C B
44X
0.004 (0.1)
C
NOTES:
1. DIMENSIONINS AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETER.
SEATING
PLANE
3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE MOLD PROTRUSION
IS 0.15 PER SIDE.
4. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSIONS. DAMBAR PROTRUSION SHALL
NOT CAUSE THE LEAD WIDTH TO EXCEED 0.58.
4X e /2
C
42X
e
MILLIMETERS
DIM
A
A1
A2
b
MIN
–––
MAX
1.20
0.15
1.05
0.45
0.21
18.54
0.05
0.95
0.30
0.12
18.28
c
c
D
A1
b
e
E
E1
L
0.80 BSC
M
0.2
C B
L
11.56
10.03
0.40
0
11.96
10.29
0.60
5
SECTION A–A
VIEW A
40 PLACES
ROTATED 90 CLOCKWISE
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
Opportunity/Affirmative Action Employer.
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Mfax is a trademark of Motorola, Inc.
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;
P.O. Box 5405, Denver, Colorado, 80217. 1-303-675-2140 or 1-800-441-2447 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan. 81-3-5487-8488
Mfax : RMFAX0@email.sps.mot.com – TOUCHTONE 1-602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre,
– US & Canada ONLY 1-800-774-1848 2 Dai King Street, Tai Po Industrial Estate, Tao Po, N.T., Hong Kong.
JAPAN: Motorola Japan Ltd.; SPD, Strategic Planning Office, 141,
Motorola Fax Back System
– http://sps.motorola.com/mfax/
852-26629298
HOME PAGE: http://motorola.com/sps/
CUSTOMER FOCUS CENTER: 1-800-521-6274
MCM6946/D
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