SCN68661 [NXP]
Enhanced programmable communications interface EPCI; 增强的可编程通信接口EPCI
| 型号： | SCN68661 |
| 厂家： | 
NXP |
| 描述： | Enhanced programmable communications interface EPCI |
| 文件： | 总19页 (文件大小：131K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
Enhanced programmable communications
interface (EPCI)
SCN2661/SCN68661
DESCRIPTION
PIN CONFIGURATIONS
The Philips Semiconductors SCN2661 EPCI is a universal
synchronous/asynchronous data communications controller chip
that is an enhanced version of the SCN2651. It interfaces easily to
all 8-bit and 16-bit microprocessors and may be used in a polled or
interrupt driven system environment. The SCN2661 accepts
programmed instructions from the microprocessor while supporting
many serial data communications disciplines —synchronous and
asynchronous — in the full- or half-duplex mode. Special support
for BISYNC is provided.
D2
D3
D1
D0
V
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RxD
GND
D4
3
CC
RxC/BKDET
DTR
4
5
D5
RTS
6
The EPCI serializes parallel data characters received from the
microprocessor for transmission. Simultaneously, it can receive
serial data and convert it into parallel data characters for input to the
microcomputer.
D6
DSR
7
DIP
D7
RESET
BRCLK
TxD
8
TxC/XSYNC
9
A1
CE
A0
10
11
12
13
14
The SCN2661 contains a baud rate generator which can be
programmed to either accept an external clock or to generate
internal transmit or receive clocks. Sixteen different baud rates can
be selected under program control when operating in the internal
clock mode. Each version of the EPCI (A, B, C) has a different set
of baud rates.
TxEMT/DSCHG
CTS
R/W
DCD
RxRDY
TxRDY
FEATURES
• Synchronous operation
INDEX
CORNER
4
1
26
– 5- to 8-bit characters plus parity
5
25
– Single or double SYN operation
– Internal or external character synchronization
– Transparent or non-transparent mode
– Transparent mode DLE stuffing (Tx) and detection (Rx)
PLCC
11
19
– Automatic SYN or DLE-SYN insertion SYN, DLE and DLESYN
stripping
12
18
TOP VIEW
– Odd, even, or no parity
NOTE:
– Local or remote maintenance loopback mode
– Baud rate: DC to 1Mbps (1X clock)
Pin Functions the same as 28-pin DIP.
SD00077
• Asynchronous operation
– 5- to 8-bit characters plus parity
– 1, 1-1/2 or 2 stop bits transmitted
– Odd, even, or no parity
• Dynamic character length switching
• Full- or half-duplex operation
• TTL compatible inputs and outputs
– Parity, overrun and framing error detection
– Line break detection and generation
– False start bit detection
• RxC and TxC pins are short-circuit protected
• Single +5V power supply
• No system clock required
– Automatic serial echo mode (echoplex)
– Local or remote maintenance loopback mode
– Baud rate: DC to 1Mbps
(1X clock)
APPLICATIONS
DC to 62.5kbps (16X clock)
DC to 15.625kbps
(64X clock)
• Intelligent terminals
• Network processors
• Front-end processors
• Remote data concentrators
OTHER FEATURES
• Computer-to-computer links
• Serial peripherals
• Internal or external baud rate clock
• 3 baud rate sets
• BISYNC adaptors
• 16 internal rates for each set
• Double-buffered transmitter and receiver
1
1994 Apr 27
853-1070 12793
Philips Semiconductors
Product specification
Enhanced programmable communications
interface (EPCI)
SCN2661/SCN68661
ORDERING CODE
V
CC
= +5V +5%
PACKAGES
DWG #
Commercial
Industrial
0°C to +70°C
-40°C to +85°C
SCN2661BC1F28
SCN2661CC1F28
SCN2661BA1F28
SCN2661CA1F28
28-Pin Ceramic Dual In-Line Package (cerdip) 0.6” Wide
28-Pin Plastic Dual In-Line Package (DIP) 0.6” Wide
0589B
SCN2661AC1N28
SCN2661BC1N28
SCN2661CC1N28
Contact Factory
Contact Factory
SOT117-2
SCN2661AC1A28
SCN2661BC1A28
SCN2661CC1A28
28-Pin Plastic Lead Chip Carrier (PLCC)
SOT261-3
BLOCK DIAGRAM
SNE/DLE CONTROL
DATA BUS
D0–D7
DATA BUS
BUFFER
SYN 1 REGISTER
SYN 2 REGISTER
DLE REGISTER
RESET
OPERATION CONTROL
MODE REGISTER 1
MODE REGISTER 2
COMMAND REGISTER
STATUS REGISTER
A
A
0
1
TRANSMITTER
TxRDY*
R/W
CE
TRANSMIT DATA
HOLDING REGISTER
TRANSMIT
SHIFT REGISTER
TxD
BRCLK
BAUD RATE
GENERATOR
AND
TxC/SYNC
CLOCK CONTROL
RECEIVER
RxRDY*
RxC/BKDET
RECEIVE DATA
HOLDING REGISTER
RECEIVE
SHIFT REGISTER
RxD
DSR
DCD
CTS
MODEM
CONTROL
RTS
DTR
TxEMT/*
DSCHG
NOTES:
Open–drain output pin.
*
SD00078
1
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
2
T
Operating ambient temperature
Note 4
°C
°C
A
T
Storage temperature
-65 to +150
-0.5 to +6.0
STG
3
All voltages with respect to ground
V
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or at any other condition above those indicated in the operation section of this specification is not
implied.
2. For operating at elevated temperatures, the device must be derated based on +150°C maximum function temperature.
3. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effect of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Over recommended free-air operating temperature range and supply voltage range unless otherwise specified. For conditions shown as MIN
or MAX, use the appropriate value specified under recommended operating conditions.
2
1994 Apr 27
Philips Semiconductors
Product specification
Enhanced programmable communications
interface (EPCI)
SCN2661/SCN68661
1, 2, 3
DC ELECTRICAL CHARACTERISTICS
LIMITS
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
Min
Typ
Max
Input voltage
V
V
Low
High
V
V
IL
IH
0.8
2.0
Output voltage
V
V
Low
High
I
= 2.2mA
= -400µA
V
V
OL
OH
OL
0.4
10
4
I
2.4
OH
I
IL
Input leakage current
V
IN
= 0 to 5.5V
µA
3-State output leakage current
10
10
I
LH
I
LL
Data bus high
Data bus low
V
= 4.0V
= 0.45V
µA
µA
O
V
O
I
Power supply current
150
mA
CC
NOTES:
1. Over recommended free-air operating temperature range and supply voltage range unless otherwise specified. For conditions shown as MIN
or MAX, use the appropriate value specified under recommended operating conditions.
2. All voltages measurements are referenced to ground. All time measurements are at the 50% level for inputs (except t
0.8V and 2.0V for outputs. Input levels swing between 0.4V and 2.4V, with a transition time of ≤ 20ns maximum.
3. Typical values are at +25°C, typical supply voltages and typical processing parameters.
4. INTR, TxRDY, RxRDY and TxEMT/DSCHG outputs are open-drain.
and t
) and at
BRH
BRL
CAPACITANCE T = 25°C, V = 0V
A
CC
LIMITS
Typ
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
Min
Max
Capacitance
C
C
C
Input
Output
Input/Output
20
20
20
pF
pF
pF
IN
OUT
I/O
f
= 1MHz
C
Unmeasured pins tied to ground
3
1994 Apr 27
Philips Semiconductors
Product specification
Enhanced programmable communications
interface (EPCI)
SCN2661/SCN68661
1, 2, 3
AC ELECTRICAL CHARACTERISTICS
LIMITS
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
Min
Typ
Max
Pulse width
t
t
Reset
Chip enable
1000
250
ns
ns
RES
CE
Setup and hold time
t
t
t
t
t
t
t
t
Address setup
Address hold
R/W control setup
R/W control hold
Data setup for write
Data hold for write
RX data setup
10
10
10
10
150
10
300
350
ns
ns
ns
ns
ns
ns
ns
ns
AS
AH
CS
CH
DS
DH
RXS
RXH
RX data hold
C
C
= 150pF
= 150pF
t
t
t
Data delay time for read
Data bus floating time for read
CE to CE delay
200
100
ns
ns
ns
L
L
DD
7
DF
600
CED
Input clock frequency
f
f
f
Baud rate generator (2661A, B)
Baud rate generator (2661C)
TxC or RxC
1.0
1.0
dc
4.9152
5.0688
4.9202
5.0738
1.0
MHz
MHz
MHz
BRG
BRG
6
R/T
Clock width
5
5
5
5
t
t
t
t
t
t
Baud rate High (2661A, B)
Baud rate High (2661C)
Baud rate Low (2661A, B)
Baud rate Low (2661C)
TxC or RxC High
75
70
75
70
480
ns
ns
ns
ns
ns
ns
BRH
BRH
BRL
BRL
R/TH
6
TxC or RxC Low
480
R/TL
t
t
TxD delay from falling edge of TxC
C
C
= 150pF
= 150pF
TXD
TCS
650
ns
ns
L
L
0
Skew between TxD changing and falling edge
4
of TxC output
NOTES:
1. Over recommended free-air operating temperature range and supply voltage range unless otherwise specified. For conditions shown as MIN
or MAX, use the appropriate value specified under recommended operating conditions.
2. All voltages measurements are referenced to ground. All time measurements are at the 50% level for inputs (except t
0.8V and 2.0V for outputs. Input levels swing between 0.4V and 2.4V, with a transition time of ≤ 20ns maximum.
3. Typical values are at +25°C, typical supply voltages and typical processing parameters.
4. Parameter applies when internal transmitter clock is used.
and t
) and at
BRH
BRL
5. Under test conditions of 5.0688MHz f
(68661) and 4.9152MHz f
(68661A, B), t
and t
measured at V and V , respectively.
BRG
BRG
BRH
BRL
IH
IL
6. In asynchronous local loopback mode, using 1X clock, the following parameters apply: f
7. See AC load conditions.
= 0.83MHz max and t
= 700ns min.
R/T
R/TL
BLOCK DIAGRAM
Timing
The EPCI consists of six major sections. These are the transmitter,
receiver, timing, operation control, modern control and SYN/DLE
control. These sections communicate with each other via an
internal data bus and an internal control bus. The internal data bus
interfaces to the microprocessor data bus via a data bus buffer.
The EPCI contains a Baud Rate Generator (BRG) which is
programmable to accept external transmit or receive clocks or to
divide an external clock to perform data communications. The unit
can generate 16 commonly used baud rates, any one of which can
be selected for full-duplex operation. See Table 1.
Operation Control
Receiver
This functional block stores configuration and operation commands
from the CPU and generates appropriate signals to various internal
sections to control the overall device operation. It contains read and
write circuits to permit communications with the microprocessor via
the data bus and contains mode registers 1 and 2, the command
register, and the status register. Details of register addressing and
protocol are presented in the EPCI programming section of this data
sheet.
The receiver accepts serial data on the RxD pin, converts this serial
input to parallel format, checks for bits or characters that are unique
to the communication technique and sends an “assembled”
character to the CPU.
Transmitter
The transmitter accepts parallel data from the CPU, converts it to a
serial bit stream, inserts the appropriate characters or bits (based on
4
1994 Apr 27
Philips Semiconductors
Product specification
Enhanced programmable communications
interface (EPCI)
SCN2661/SCN68661
the communication technique) and outputs a composite serial
stream of data on the TxD output pin.
SYN/DLE Control
This section contains control circuitry and three 8-bit registers
storing the SYN1, SYN2, and DLE characters provided by the CPU.
These registers are used in the synchronous mode of operation to
provide the characters required for synchronization, idle fill and data
transparency.
Modem Control
The modern control section provides interfacing for three input
signals and three output signals used for “handshaking” and status
indication between the CPU and a modem.
Table 1.
Baud Rate Generator Characteristics
68661A (BRCLK = 4.9152MHz)
MR23–20
ACTUAL FREQUENCY
PERCENT
ERROR
BAUD RATE
DIVISOR
16X CLOCK
0.8kHz
1.2
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
50
75
—
—
6144
4096
2793
2284
2048
1536
1024
512
292
256
171
154
128
64
110
1.7598
2.152
2.4
–0.01
—
134.5
150
—
200
3.2
—
300
4.8
—
600
9.6
—
1050
1200
1800
2000
2400
4800
9600
19200
16.8329
19.2
0.196
—
28.7438
31.9168
38.4
–0.19
–0.26
—
76.8
—
153.6
307.2
—
32
—
16
68661B (BRCLK = 4.9152MHz)
MR23–20
ACTUAL FREQUENCY
16X CLOCK
PERCENT
ERROR
BAUD RATE
DIVISOR
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
45.5
50
0.7279kHz
0.8
0.005
—
6752
6144
4096
2793
2284
2048
1024
512
256
171
154
128
64
75
1.2
—
110
1.7598
2.152
2.4
–0.01
—
134.5
150
—
300
4.8
—
600
9.6
—
1200
1800
2000
2400
4800
9600
19200
38400
19.2
—
28.7438
31.9168
38.4
–0.19
–0.26
—
76.8
—
153.6
307.2
614.4
—
32
—
16
—
8
5
1994 Apr 27
Philips Semiconductors
Product specification
Enhanced programmable communications
interface (EPCI)
SCN2661/SCN68661
68661C (BRCLK = 5.0688MHz)
MR23–20
0000
0001
0010
0011
0100
0101
0110
0111
BAUD RATE
50
ACTUAL FREQUENCY 16X CLOCK
PERCENT ERROR
DIVISOR
6336
4224
2880
2355
2112
1056
528
0.8kHz
1.2
—
—
75
110
1.76
2.1523
2.4
—
134.5
150
0.016
—
300
4.8
—
600
9.6
—
1200
1800
2000
2400
3600
4800
7200
9600
19200
19.2
28.8
32.081
38.4
57.6
76.8
115.2
153.6
316.8
—
264
1000
1001
1010
1011
1100
1101
1110
—
176
0.253
—
158
132
—
88
—
66
—
44
—
33
1111
3.125
16
NOTE: 16X clock is used in asynchronous mode. In synchronous mode, clock multiplier is 1X and BRG can be used only for TxC.
Pin 25 can be programmed to be a break detect output by
OPERATION
appropriate setting of MR27-MR24. If so, a detected break will
cause that pin to go High. When RxD returns to mark for one RxC
time, pin 25 will go low. Refer to the Break Detection Timing
Diagram.
The functional operation of the 68661 is programmed by a set of
control words supplied by the CPU. These control words specify
items such as synchronous or asynchronous mode, baud rate,
number of bits per character, etc. The programming procedure is
described in the EPCI programming section of the data sheet.
When the EPCI is initialized into the synchronous mode, the
receiver first enters the hunt mode on a 0 to 1 transition of RxEN
(CR2). In this mode, as data are shifted into the receiver shift
register a bit at a time, the contents of the register are compared to
the contents of the SYN1 register. If the two are not equal, the next
bit is shifted in and the comparison is repeated. When the two
registers match, the hunt mode is terminated and character
assembly mode begins. If single SYN operation is programmed, the
SYN DETECT status bit is set. If double SYN operation is
programmed, the first character assembled after SYN1 must be
SYN2 in order for the SYN DETECT bit to be set. Otherwise, the
EPCI returns to the hunt mode. (Note that the sequence
SYN1-SYN1-SYN2 will not achieve synchronization.) When
synchronization has been achieved, the EPCI continues to
assemble characters and transfer then to the holding register,
setting the RxRDY status bit and asserting the RxRDY output each
time a character is transferred. The PE and OE status bits are set
as appropriate. Further receipt of the appropriate SYN sequence
sets the SYN DETECT status bit. If the SYN stripping mode is
commanded, SYN characters are not transferred to the holding
register. Note that the SYN characters used to establish initial
synchronization are not transferred to the holding register in any
case.
After programming, the EPCI is ready to perform the desired
communications functions. The receiver performs serial to parallel
conversion of data received from a modem or equivalent device.
The transmitter converts parallel data received from the CPU to a
serial bit stream. These actions are accomplished within the
framework specified by the control words.
Receiver
The 68661 is conditioned to receiver data when the DCD input is
Low and the RxEN bit in the commands register is true. In the
asynchronous mode, the receiver looks for High-to-Low (mark to
space) transition of the start bit on the RxD input line. If a transition
is detected, the state of the RxD line is sampled again after a delay
of one-half of a bit-time. If RxD is now high, the search for a valid
start bit is begun again. If RxD is still Low, a valid start bit is
assumed and the receiver continues to sample the input line at one
bit time intervals until the proper number of data bits, the parity bit,
and one stop bit have been assembled. The data are then
transferred to the receive data holding register, the RxRDY bit in the
status register is set, and the RxRDY output is asserted. If the
character length is less than 8 bits, the High order unused bits in the
holding register are set to zero. The parity error, framing error, and
overrun error status bits are strobed into the status register on the
positive going edge of RxC corresponding to the received character
boundary. If the stop bit is present, the receiver will immediately
begin its search for the next start bit. If the stop bit is absent
(framing error), the receiver will interpret a space as a start bit if it
persists into the next bit timer interval. If a break condition is
detected (RxD is Low for the entire character as well as the stop bit),
only one character consisting of all zeros (with the FE status bit SR5
set) will be transferred to the holding register. The RxD input must
return to a High condition before a search for the next start bit
begins.
External jam synchronization can be achieved via pin 9 by
appropriate setting of MR27-MR24. When pin 9 is an XSYNC input,
the internal SYN1, SYN1–SYN2, and DLE–SYN1 detection is
disabled. Each positive going signal on XSYNC will cause the
receiver to establish synchronization on the rising edge of the next
RxC pulse. Character assembly will start with the RxD input at this
edge. XSYNC may be lowered on the next rising edge of RxD. This
external synchronization will cause the SYN DETECT status bit to
be set until the status register is read. Refer to XSYNC timing
diagram.
6
1994 Apr 27
Philips Semiconductors
Product specification
Enhanced programmable communications
interface (EPCI)
SCN2661/SCN68661
Table 2.
PIN NAME
RESET
CPU-Related Signals
INPUT/
PIN NO.
FUNCTION
OUTPUT
21
I
A High on this input performs a master reset on the 68661. This signal asynchronously
terminates any device activity and clears the mode, command and status registers. The
device assumes the idle state and remains there until initialized with the appropriate control
words.
A0, A1
R/W
CE
12,10
13
I
I
I
Address lines used to select internal EPCI registers.
Read command when Low, write command when High.
11
Chip enable command. When Low, indicates that control and data lines to the EPCI are
valid and that the operation specified by the RW, A1 and A0 inputs should be performed.
When High, places the D0–D7 lines in the 3-State condition.
D0–D7
TxRDY
27,28,1,2,5–8
15
I/O
O
8-bit, 3-State data bus used to transfer commands, data and status between EPCI and the
CPU. D0 is the least significant bit, D7 the most significant bit.
This output is the complement of status register bit SR0. When Low, it indicates that the
transmit data holding register (THR) is ready to accept a data character from the CPU. It
goes High when the data character is loaded. This output is valid only when the transmitter
is enabled. It is an open-drain output which can be used as an interrupt to the CPU.
RxRDY
14
18
O
O
This output is the complement of status register bit SR1. When Low, it indicates that the
receive data holding register (RHR) has a character ready for input to the CPU. It goes
High when the RHR is read by the CPU, and also when the receiver is disabled. It is an
open-drain output which can be used as an interrupt to the CPU.
TxEMT/DS
CHG
This output is the complement of status register bit SR2. When Low, it indicates that the
transmitter has completed serialization of the last character loaded by the CPU, or that a
change of state of the DSR or DCD inputs has occurred. This output goes High when the
status register is ready by the CPU, if the TxEMT condition does not exist. Otherwise, the
THR must be loaded by the CPU for this line to go high. It is an open-drain output which
can be used as an interrupt to the CPU. See Status Register (SR2) for details.
Table 3.
PIN NAME
BRCLK
Device-Related Signals
INPUT/
PIN NO.
FUNCTION
OUTPUT
20
25
I
Clock input to the internal baud rate generator (see Table 1). Not required if external
receiver and transmitter clocks are used.
RxC/BKDET
I/O
Receiver clock. If external receiver clock is programmed, this input controls the rate at
which the character is to be received. Its frequency is 1X, 16X or 64X the baud rate, as
programmed by mode register 1. Data are sampled on the rising edge of the clock. If
internal receiver clock is programmed, this pin can be a 1X/16X clock or a break detect
output pin.
TxC/XSYNC
9
I/O
Transmitter clock. If external transmitter clock is programmed, this input controls the rate at
which the character is transmitted. Its frequency is 1X, 16X or 64X the baud rate, as
programmed by mode register 1. The transmitted data changes on the falling edge of the
clock. If internal transmitter clock is programmed, this pin can be a 1X/16X clock output or
an external jam synchronization input.
RxD
TxD
3
I
Serial data input to the receiver. “Mark” is High, “space” is Low.
19
O
Serial data output from the transmitter. “Mark” is High, “Space” is Low. Held in mark
condition when the transmitter is disabled.
DSR
DCD
22
16
I
I
General purpose input which can be used for data set ready or ring indicator condition. Its
complement appears as status register bit SR7. Causes a Low output on TxEMT/DSCHG
when its state changes if CR2 or CR0 = 1.
Data carrier detect input. Must be Low in order for the receiver to operate. Its complement
appears as status register bit SR6. Causes a Low output on TxEMT/DSCHG when its
state changes if CR2 or CR0 = 1. If DCD goes High while receiving, the RxC is internally
inhibited.
CTS
17
I
Clear to send input. Must be Low in order for the transmitter to operate. If it goes High
during transmission, the character in the transmit shift register will be transmitted before
termination.
DTR
RTS
24
23
O
O
General purpose output which is the complement of command register bit CR1. Normally
used to indicate data terminal ready.
General purpose output which is the complement of command register bit CR5. Normally
used to indicate request to send. See Command Register (CR5) for details.
7
1994 Apr 27
Philips Semiconductors
Product specification
Enhanced programmable communications
interface (EPCI)
SCN2661/SCN68661
1, and a subsequent operation addresses mode register 2. If more
than the required number of accesses are made, the internal
sequencer recycles to point at the first register. The pointers are
reset to SYN1 register and mode register 1 by a RESET input or by
performing a read command register operation, but are unaffected
by any other read or write operation.
Transmitter
The EPCI is conditioned to transmit data when the CTS input is Low
and the TxEN command register bit is set. The 68661 indicates to
the CPU that it can accept a character for transmission by setting
the TxRDY status bit and asserting the TxRDY output. When the
CPU writes a character into the transmit data holding register, these
conditions are negated. Data are transferred from the holding
register to the transmit shift register when it is idle or has completed
transmission of the previous character. The TxRDY conditions are
then asserted again. Thus, one full character time of buffering is
provided.
The 68661 register formats are summarized in Tables 5, 6, 7 and 8.
Mode registers 1 and 2 define the general operational
characteristics of the EPCI, while the command register controls the
operation within this basic framework. The EPCI indicates its status
in the status register. These registers are cleared when a RESET
input is applied.
In the asynchronous mode, the transmitter automatically sends a
start bit followed by the programmed number of data bits, the least
significant bit being sent first. It then appends an optional odd or
even parity bit and the programmed number of stop bits. If,
following transmission of the data bits, a new character is not
available in the transmit holding register, the TxD output remains in
the marking (High) condition and the TxEMT/DSCHG output and its
corresponding status bit are asserted. Transmission resumes when
the CPU loads a new character into the holding register. The
transmitter can be forced to output a continuous Low (BREAK)
condition by setting the send break command bit (CR3) High.
Mode Register 1 (MR1)
Table 5 illustrates mode register 1. Bits MR11 and MR10 select the
communication format and baud rate multiplier. 00 specifies
synchronous format. However, the multiplier in asynchronous
format applies only if the external clock input option is selected by
MR24 or MR25.
MR13 and MR12 select a character length of 5, 6, 7 or 8 bits. The
character length does not include the parity bit, if programmed, and
does not include the start and stop bits in asynchronous mode.
In the synchronous mode, when the 68661 is initially conditioned to
transmit, the TxD output remains High and the TxRDY condition is
asserted until the first character to be transmitted (usually a SYN
character) is loaded by the CPU. Subsequent to this, a continuous
stream of characters is transmitted. No extra bits (other than parity,
if commanded) are generated by the EPCI unless the CPU fails to
send a new character to the EPCI by the time the transmitter has
completed sending the previous character. Since synchronous
communication does not allow gaps between characters, the EPCI
asserts TxEMT and automatically “fills” the gap by transmitting
SYN1s, SYN1–SYN2 doublets, or DLE–SYN1 doubles, depending
on the state of MR16 and MR17. Normal transmission of the
message resumes when a new character is available in the transmit
data holding register. If the send DLE bit in the commands register
is true, the DLE character is automatically transmitted prior to
transmission of the message character in the THR.
MR14 controls parity generation. If enabled, a parity bit is added to
the transmitted character and the receiver performs a parity check
on incoming data. MR15 selects odd or even parity when parity is
enabled by MR14. In asynchronous mode, MR17 and MR16 select
character framing of 1, 1.5, or 2 stop bits. (If 2X baud rate is
programmed, 1.5 stop bits defaults to 1 stop bits on transmit.) In
synchronous mode, MR17 controls the number of SYN characters
used to establish synchronization and for character fill when the
transmitter is idle. SYN1 alone is used if MR17 = 1, and
SYN1–SYN2 is used when MR17 = 0. If the transparent mode is
specified by MR16, DLE–SYN1 is used for character fill and SYN
detect, but the normal synchronization sequence is used to establish
character sync. When transmitting, a DLE character in the transmit
holding register will cause a second DLE character to be
transmitted. This DLE stuffing eliminates the software DLE compare
and stuff on each transparent mode data character. If the send DLE
command (CR3) is active when a DLE is loaded into THR, only one
additional DLE will be transmitted. Also, DLE stripping and DLE
detect (with MR14 = 0) are enabled.
EPCI PROGRAMMING
Prior to initiating data communications, the 68661 operational mode
must be programmed by performing write operations to the mode
and command registers. In addition, if synchronous operation is
programmed, the appropriate SYN/DLE registers must be loaded.
The EPCI can be reconfigured at any time during program
execution. A flowchart of the initialization process appears in
Figure 1.
The bits in the mode register affecting character assembly and
disassembly (MR12–MR16) can be changed dynamically (during
active receive/transmit operation). The character mode register
affects both the transmitter and receiver; therefore in synchronous
mode, changes should be made only in half-duplex mode (RxEN = 1
or TxEN = 1, but not both simultaneously = 1). In asynchronous
mode, character changes should be made when RxEN and TxEN =
0 or when TxEN = 1 and the transmitter is marking in half-duplex
mode (RxEN = 0).
The internal registers of the EPCI are accessed by applying specific
signals to the CE, R/W, A1 and A0 inputs. The conditions
necessary to address each register are shown in Table 4.
To effect assembly/disassembly of the next received/transmitted
character, MR12 – 15 must be changed within n bit times of the
active going state of RxRDY/TxRDY. Transparent and
non-transparent mode changes (MR16) must occur within n-1 bit
times of the character to be affected when the receiver or transmitter
is active. (n – smaller of the new and old character lengths.)
The SYN1, SYN2, and DLE registers are accessed by performing
write operations with the conditions A1 = 0, A0 = 1, and R/W = 1.
The first operation loads the SYN1 register. The next loads the DLE
register. Reading or loading the mode registers is done in a similar
manner. The first write (or read) operation addresses mode register
8
1994 Apr 27
Philips Semiconductors
Product specification
Enhanced programmable communications
interface (EPCI)
SCN2661/SCN68661
Table 4. 68661 Register Addressing
CE
A
A
R/W
FUNCTION
1
0
1
0
0
0
0
0
0
0
0
X
X
X
0
1
0
1
0
1
0
1
3-State data bus
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
Read receive holding register
Write transmit holding register
Read status register
Write SYN1/SYN2/DLE registers
Read mode register 1/2
Write mode register 1/2
Read command register
Write command register
INITIAL RESET
LOAD
MODE REGISTER 1
NOTE:
LOAD
MODE REGISTER 2
Mode Register 1 must be written
before 2 can be written. Mode Register 2
need not be programmed if external
clocks are used.
N
SYNCHRONOUS?
Y
LOAD
SYN 1 REGISTER
NOTE:
SYN1 Register must be written
before SYN2 can be written, and
SYN2 before DLE can be written.
N
DOUBLE
SYNC?
Y
Y
TRANSPARENT
MODE?
LOAD
SYN 2 REGISTER
N
N
TRANSPARENT
MODE?
Y
LOAD
DLE REGISTER
LOAD
COMMAND REGISTER
OPERATE
N
RECONFIGURE?
Y
DISABLE
RCVR AND XMTR
SD00079
Figure 1. 68661 Initialization Flowchart
9
1994 Apr 27
Philips Semiconductors
Product specification
Enhanced programmable communications
interface (EPCI)
SCN2661/SCN68661
Table 5. Mode Register 1 (MR1)
MR17
MR16
MR15
MR14
MR13
MR12
MR11
MR10
Sync/Async
Parity Type
Parity Control
Character Length
Mode and Baud Rate Factor
Async: Stop bit length
00 = invalid
0 = Odd
1 = Even
0 = Disabled
1 = Enabled
00 = 5 bits
01 = 6 bits
10 = 7 bits
11 = 8 bits
00 = Synchronous 1X rate
01 = Asynchronous 1X rate
10 = Asynchronous 16X rate
11 = Asynchronous 64X rate
01 = 1 stop bit
10 = 1 1/2 stop bits
11 = 2 stop bits
Sync:
Number of
SYN char
Sync:
Transparency
control
0 = Double SYN 0 = Normal
1 = Single SYN 1 = Transparent
NOTE: Baud rate factor in asynchronous applies only if external clock is selected. Factor is 16X if internal clock is selected. Mode must be
selected (MR11, MR10) in any case.
Table 6. Mode Register 2 (MR2)
MR27 – MR24
MR23 – MR20
Baud Rate
Selection
TxC
RxC
Pin 9
Pin 25
TxC
RxC
Pin 9
Pin 25
Mode
0000
0001
0010
0011
0100
0101
0110
0111
E
E
I
E
I
E
I
E
I
TxC
TxC
1X
RxC
1X
RxC
1X
RxC
16X
RxC
16X
1000
1001
1010
1011
1100
1101
1110
1111
E
E
I
E
I
E
I
E
I
XSYNC* RXC/TxC
sync
async
sync
async
sync
async
sync
async
TxC
XSYNC*
1X
BKDET
RxC
BKDET
I
1X
I
See baud rates
in Table 1.
E
E
I
TxC
TxC
16X
16X
E
E
I
XSYNC* RxC/TxC
TXC
XSYNC*
16X
BKDET
RxC
BKDET
E
I
E
I
I
I
NOTES:
*
When pin 9 is programmed as XSYNC input, SYN1, SYN1–SYN2, and DLE–SYN1 detection is disabled.
E
I
= External clock
= Internal clock (BRG)
1X and 16X are clock outputs.
Table 7. Command Register (CR)
CR7
CR6
CR5
CR4
CR3
CR2
CR1
CR0
Receive
Control
(RxEN)
Transmit
Control
(TxEN)
Request
to Send
Data Terminal
Ready
Operating Mode
Reset Error
Sync/Async
00 = Normal operation
01 = Async:
0 = Force RTS
0 = Normal
Async:
0 = Disable
1 = Enable
0 = Force DTR 0 = Disable
output High 1 = Enable
1 = Force DTR
Output High 1 = Reset error
one clock
time after
Force Break
0 = Normal
1 = Force
Automatic
Echo mode
flags in
status reg.
output Low
Sync: SYN and/or DLE
stripping mode
10 = Local loopback
11 = Remote loopback
TxSR
(FE,OE,PE/ break
DLE detect.)
serialization
1 = Force RTS
output Low
Not applicable
in
Sync
Send DLE
0 = Normal
1 = Send DLE
10
1994 Apr 27
Philips Semiconductors
Product specification
Enhanced programmable communications
interface (EPCI)
SCN2661/SCN68661
Table 8. Status Register (SR)
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
Data Set
Ready
Data Carrier
Detect
FE/SYN
Detect
PE/DLE
Detect
TxEMT
DSCHG
Overrun
RxRDY
TxRDY
0 = DSR input
is High
1 = DSR input
is Low
0 = DCD input
is High
1 = DCD input
is Low
Async:
0 = Normal
1 = Overrun
error
Async:
0 = Normal
1 = Parity error
0 = Normal
1 = Change in
DSR or
0 = Receive
holding
register
empty
1 = Receive
0 = Transmit
holding
register
busy
1 = Transmit
0 = Normal
1 = Framing
error
DCD, or
transmit
shift
Sync:
Sync:
holding
holding
0 = Normal
1 = SYN
detected
0 = Normal
1 = Parity error
or DLE
register is
empty
register
has data
register
empty
received
(active) until both the THR and the transmit shift register are empty
and then go High (inactive) one TxC time later.
Mode Register 2 (MR2)
Table 6 illustrates mode register 2. MR23, MR22, MR21 and MR20
control the frequency of the internal baud rate generator (BRG).
Sixteen rates are selectable for each EPCI version (–1,–2,–3).
Versions 1 and 2 specify a 4.9152MHz TTL input at BRCLK (pin 20);
version 3 specifies a 5.0688MHz input which is identical to the
Philips Semiconductors 2651. MR23 – 20 are don’t cares if external
clocks are selected (MR25 – MR24 = 0). The individual rates are
given in Table 1.
The EPCI can operate in one of four submodes within each major
mode (synchronous or asynchronous). The operational sub-mode is
determined by CR7 and CR6. CR7 – CR6 = 00 is the normal mode,
with the transmitter and receive operating independently in
accordance with the mode and status register instructions.
In asynchronous mode, CR7 – CR6 = 01 places the EPCI in the
automatic echo mode. Clocked, regenerated received data are
automatically directed to the TxD line while normal receiver
operation continues. The receiver must be enabled (CR2 = 1), but
the transmitter need not be enabled. CPU to receiver
MR24 – MR27 select the receive and transmit clock source (either
the BRG or an external input) and the function at pins 9 and 25.
Refer to Table 6.
communication continues normally, but the CPU to transmitter link is
disabled. Only the first character of a break condition is echoed.
Command Register (CR)
Table 7 illustrates the command register. Bits CR0 (TxEN) and CR2
(RxEN) enable or disable the transmitter and receiver respectively.
A 0– to–1 transition of CR2 forces start bit search (async mode) or
hunt mode (sync mode) on the second RxC rising edge. Disabling
the receiver causes RxRDY to go High (inactive). If the transmitter
is disabled, it will complete the transmission of the character in the
transmit shift register (if any) prior to terminating operation. The TxD
output will then remain in the marking state (High) while TxRDY and
TxEMT will go High (inactive). If the receiver is disabled, it will
terminate operation immediately. Any character being assembled
will be neglected. A 0–to–1 transition of CR2 will initiate start bit
search (async) or hunt mode (sync).
The TxD output will go High until the next valid start is detected.
The following conditions are true while in automatic echo mode:
1. Data assembled by the receiver are automatically placed in the
transmit holding register and retransmitted by the transmitter on
the TxD output.
2. The transmitter is clocked by the receive clock.
3. TxRDY output = 1.
4. The TxEMT/DSCHG pin will reflect only the data set change
condition.
5. The TxEN command (CR0) is ignored.
Bits CR1 (DTR) and CR5 (RTS) control the DTR and RTS outputs.
Data at the outputs are the logical complement of the register data.
In synchronous mode, CR7 – CR6 = 01 places the EPCI in the
automatic SYN/DLE stripping mode. The exact action taken
depends on the setting of bits MR17 and MR16:
1. In the non-transparent, single SYN mode (MR17 – MR16 = 10),
characters in the data stream matching SYN1 are not transferred
to the Receive Data Holding register (RHR).
In asynchronous mode, setting CR3 will force and hold the TxD
output Low (spacing condition) at the end of the current transmitted
character. Normal operation resumes when CR3 is cleared. The
TxD line will go High for at least one bit time before beginning
transmission of the next character in the transmit data holding
register. In synchronous mode, setting CR3 causes the
transmission of the DLE register contents prior to sending the
character in the transmit data holding register. Since this is a one
time command, CR3 does not have to be reset by software. CR3
should be set when entering and exiting transparent mode and for
all DLE-non-DLE character sequences.
2. In the non-transparent, double SYN mode (MR17 – MR16 = 00),
character in the data stream matching SYN1, or SYN2 if immedi-
ately preceded by SYN1, are not transferred the RHR.
3. In transparent mode (MR16 = 1), character in the data stream
matching DLE, or SYN1 if immediately preceded by DLE, are not
transferred to the RHR. However, only the first DLE of a DLE–
DLE pair is stripped.
Setting CR4 causes the error flags in the status register (SR3, SR4,
and SR5) to be cleared; this is a one time command. There is no
internal latch for this bit.
Note that automatic stripping mode does not affect the setting of the
DLE detect and SYN detect status bits (SR3 and SR5).
When CR5 (RTS) is set, the RTS pin is forced Low. A 1–to–0
transition of CR5 will cause RTS to go High (inactive) one TxC time
after the last serial bit has been transmitted. If a 1–to–0 transition
of CR5 occurs while data is being transmitted, RTS will remain Low
Two diagnostic sub-modes can also be configured. In local
loopback mode (CR7 – CR6 = 10), the following loops are
connected internally:
11
1994 Apr 27
Philips Semiconductors
Product specification
Enhanced programmable communications
interface (EPCI)
SCN2661/SCN68661
1. The transmitter output is connected to the receiver input.
2. DTR is connected to DCD and RTS is connected to CTS.
3. The receiver is clocked by the transmit clock.
there is no new character in the holding register. This bit is cleared
when the CPU reads the receive data holding register or when the
receiver is disabled by CR2. When set, the RxRDY output is Low.
The TxEMT/DSCHG bit, SR2, when set, indicates either a change of
state of the DSR or DCD inputs (when CR2 or CR0 = 1) or that the
transmit shift register has completed transmission of a character and
no new character has been loaded into the transmit data holding
register. Note that in synchronous mode this bit will be set even
though the appropriate “fill” character is transmitted. TxEMT will not
go active until at least one character has been transmitted. It is
cleared by loading the transmit data holding register. The DSCHG
conditions is enabled when TxEN = 1 or RxEN = 1. It is cleared
when the status register is read by the CPU. If the status register is
read twice and SR2 – 1 while SR6 and SR7 remain unchanged,
then a TxEMT condition exists. When SR2 is set, the
4. The DTR, RTS and TxD outputs are held High.
5. The CTS, DCD, DSR and RxD inputs are ignored.
Additional requirements to operate in the local loopback mode are
that CR0 (TxEN), CR1 (DTR) and CR5 (RTS) must be set to 1.
CR2 (RxEN) is ignored by the EPCI.
The second diagnostic mode is the remote loopback mode (CR7 –
CR6 = 11). In this mode:
1. Data assembled by the receiver are automatically placed in the
transmit holding register and retransmitted by the transmitter on
the TxD output.
TxEMT/DSCHG output is Low.
2. The transmitter is clocked by the receiver clock.
SR3, when set, indicates a received parity error when parity is
enabled by MR14. In synchronous transparent mode (MR16 = 1),
with parity disabled, it indicates that a character matching DLE
register was received and the present character is neither SYN2 or
DLE. This bit is cleared when the next character following the
above sequence is loaded into RHR, when the receiver is disabled,
or by a reset error command, CR4.
3. No data are sent to the local CPU, but he error status conditions
(PE, FE) are set.
4. The RxRDY, TxRDY, and TxEMT/DSCHG outputs are held High.
5. CR0 (TxEN) is ignored.
6. All other signals operate normally.
The overrun error status bit, SR4, indicates that the previous
character loaded into the receive holding register was not ready the
CPU at the time of new received character was transferred into it.
This bit is cleared when the receiver is disabled or by the reset error
command, CR4.
Status Register
The data contained in the status register (as shown in Table 8)
indicates receiver and transmitter conditions and modem/data set
status.
In asynchronous mode, bit SR5 signifies that the received character
was not framed by a stop bit; i.e., only the first stop bit is checked. If
RHR = 0 when SR5 = 1, a break condition is present. In
SR0 is the transmitter ready (TxRDY) status bit. It, and its
corresponding output, are valid only when the transmitter is enabled.
If equal to 0–, it indicates that the transmit data holding register has
been loaded by the CPU and the data has not been transferred to
the transmit register. If set equal to 1, it indicates that the holding
register is ready to accept data from the CPU. This bit is initially set
when the transmitter is enabled by CR0, unless a character has
previously been loaded into the holding register. It is not set when
the automatic echo or remote loopback modes are programmed.
When this bit is set, the TxRDY output pin is Low. In the automatic
echo and remote loopback modes, the output is held High.
synchronous non-transparent mode (MR16 = 0), it indicates receipt
of the SYN1 character in single SYN mode or the SYN1 – SYN2 pair
in double SYN mode. In synchronous transparent mode (MR16 =
1), this bit is set upon detection of the initial synchronizing
characters (SYN or SYN1 – SYN2) and, after synchronization has
been achieved, when a DLE–SYN1 pair is received. The bit is reset
when the receiver is disabled, when the reset error command is
given in asynchronous mode, or when the status register is read by
the CPU in the synchronous mode.
SR1, the receiver ready (RxRDY) status bit, indicates the condition
of the receive data holding register. If set, it indicates that a
character has been loaded into the holding register from the receive
shift register and is ready to be read by the CPU. If equal to zero,
SR6 and SR7 reflect the conditions of the DCD and DSR inputs,
respectively. A Low input sets its corresponding status bit, and a
High input clears it.
12
1994 Apr 27
Philips Semiconductors
Product specification
Enhanced programmable communications
interface (EPCI)
SCN2661/SCN68661
Table 9.
68661 EPCI vs 2651 PCI
FEATURE
EPCI
PCI
1. MR2 BIT 6, 7
Control pins 9, 25
SR3 = 0 for DLE–DLE, DLE – SYN1
Not used
SR3 = 1 for DLE–DLE, DLE – SYN1
2. DLE detect – SR3
3. Reset of SR3, DLE detect
Second character after DLE, or receiver Receiver disable, or CR4 = 1
disable, or CR4 = 1
4. Send DLE – CR3
One time command
Reset via CR3 on next TxRDY
None
5. DLE stuffing in transparent mode
Automatic DLE stuffing when DLE is loaded
except if CR3 = 1
6. SYN1
stripping
in
double
sync All SYN1
First SYN1 of pair
One
non-transparent mode
7. Baud rate versions
Three
8. Terminate ASYNC transmission (drop
RTS)
Reset CR5 in response to TxEMT changing
from 1 to 0
Reset CR0 when TxEMT goes from 1 to 0.
Then reset CR5 when TxEMT goes from
1 to 0
*
9. Break detect
Pin 25
FE and null character
10. Stop bit searched
11. External jam sync
12. Data bus timing
13. Data bus drivers
One
Two
No
—
**
Pin 9
Improved over 2651
Sink 2.2mA
Source 400µA
Sink 1.6mA
Source 100µA
NOTES:
*
Internal BRG used for RxC.
** Internal BRG used for TxC.
AC LOAD CONDITIONS
2.2V
+5V
750Ω
2kΩ
OUTPUT
OUTPUT
C
= 150pF
C = 50pF
L
L
NOTES:
Open-drain outputs.
C
= Load capacitance includes JIG and probe capacitance.
SD00080
L
13
1994 Apr 27
Philips Semiconductors
Product specification
Enhanced programmable communications
interface (EPCI)
SCN2661/SCN68661
TIMING DIAGRAMS
CLOCK
t
t
t
BRH
R/TH
BRL
RESET
t
R/TL
BRCLK,
TxC, RxC
RESET
1/f
1/f
t
BRG
R/T
RES
TRANSMIT
1 BIT TIME
(1, 16, OR 64 CLOCK PERIODS)
RECEIVE
TxC
(INPUT)
RxD
TxD
t
t
RXS
RXH
t
t
TxD
TxD
RxC (IX)
t
TCS
TxC
(OUTPUT)
READ AND WRITE
CE
t
t
CED
CE
A
A
1
,
0
t
t
t
t
AS
AH
R/W
CS
CH
D
–D
0
7
(WRITE)
t
t
DS
DH
BUS
FLOATING
NOT
VALID
BUS
FLOATING
D
–D
7
0
DATA VALID
(READ)
t
t
DF
DD
SD00052
14
1994 Apr 27
Philips Semiconductors
Product specification
Enhanced programmable communications
interface (EPCI)
SCN2661/SCN68661
TIMING DIAGRAMS (Continued)
TxRDY, TxEMT (Shown for 5-bit characters, no parity, 2 stop bits [in asynchronous mode])
TxC (1X)
TxD
1
2
3
4
5
1
2
3
4
5
1
2
3
4
5
1
2
3
4
5
1
2
3
4
5
DATA 1
DATA 2
DATA 3
SYN 1
DATA 4
TxEN
TxRDY
TxEMT
CE FOR
WRITE
OF THR
DATA 1
D
DATA 2
DATA 3
DATA 4
A
1
2
3
4
5
B
C
A
1
2
3
4
5
B
C
A
1
2
3
4
5
B
C
D
A
1
2
TxD
DATA 1
DATA 2
DATA 3
DATA 4
TxEN
TxRDY
TxEMT
CE FOR
WRITE
OF THR
DATA 1
DATA 2
DATA 3
DATA 4
NOTES:
A = Start bit
B = Stop bit 1
C = Stop bit 2
D = TxD marking condition
TxEMT goes low at the beginning of the last data bit, or, if parity is enabled, at the beginning of the parity bit.
SD00053
15
1994 Apr 27
Philips Semiconductors
Product specification
Enhanced programmable communications
interface (EPCI)
SCN2661/SCN68661
TIMING DIAGRAMS (Continued)
EXTERNAL SYNCHRONIZATION WITH XSYNC
1X RxC
t
es
t
t
= XSYNC SETUP TIME = 300ns
es
H
= XSYNC HOLD TIME = ONE RxC
XSYNC
t
H
RxD
X
0
1
2
3
4
CHARACTER ASSEMBLY
BREAK DETECTION TIMING
Rx CHARACTER = 5 BITS, NO PARITY
RxC + 16 OR 64
LOOK FOR START BIT = LOW (IF RxD IS HIGH, LOOK FOR HIGH TO LOW TRANSITION)
FALSE START BIT CHECK MADE (RxD LOW)
RxD
MISSING STOP BIT
DETECTED SET FE BIT*
1st DATA BIT
SAMPLED
MISSING STOP BIT DETECTED, SET FE BIT.
0 → RHR, ACTIVATE RxRDY. SET BKDET PIN
RxD → INPUT RxSR UNTIL A MARK TO SPACE
TRANSITION OCCURS.
NOTE:
* If the stop bit is present, the start bit search will commence immediately.
SD00081
16
1994 Apr 27
Philips Semiconductors
Product specification
Enhanced programmable communications
interface (EPCI)
SCN2661/SCN68661
TIMING DIAGRAMS (Continued)
RxRDY (Shown for 5-bit characters, no parity, 2 stop bits [in asynchronous mode])
RxC
1
2
3
4
5
1
2
3
4
5
1
2
3
4
5
1
2
3
4
5
1
2
3
4
5
1
2
3
4
5
RxD
SYN 1
DATA 1
DATA 2
DATA 3
DATA 4
DATA 5
IGNORED
RxEN
SYNDET
STATUS BIT
RxRDY
CE FOR
READ
READ
STATUS
READ
STATUS
READ RHR
(DATA 1)
READ RHR
(DATA 2)
READ RHR
(DATA 3)
READ RHR
(DATA 3)
D
_
_
A
A
1
2
3
4
5
B
C
A
1
2
3
4
5
B
C
D
1
2
3
4
5
B
C
A
1
2
3
RxD
DATA 1
DATA 2
DATA 3
DATA 4
RxEN
RxRDY
OVERRUN
STATUS BIT
CE FOR
READ
READ RHR
(DATA 1)
READ RHR
(DATA 3)
NOTES:
A = Start bit
B = Stop bit 1
C = Stop bit 2
D = TxD marking condition
SD00054
17
1994 Apr 27
Philips Semiconductors
Product specification
Enhanced programmable communications
interface (EPCI)
SCN2661/SCN68661
TYPICAL APPLICATIONS
ASYNCHRONOUS INTERFACE TO CRT TERMINAL
ADDRESS BUS
CONTROL BUS
DATA BUS
8
RxD
TxD
EIA TO TTL
CONVERT
(OPT)
SCN2661/68661
BAUD RATE CLOCK
OSCILLATOR
CRT
TERMINAL
BRCLK
ASYNCHRONOUS INTERFACE TO TELEPHONE LINES
ADDRESS BUS
CONTROL BUS
DATA BUS
8
RxD
TxD
DSR
DTR
PHONE
LINE
INTERFACE
ASYNC
MODEM
SCN2661/68661
CTS
RTS
DCD
BRCLK
BAUD RATE CLOCK
OSCILLATOR
TELEPHONE
LINE
SD00082
18
1994 Apr 27
Philips Semiconductors
Product specification
Enhanced programmable communications
interface (EPCI)
SCN2661/SCN68661
TYPICAL APPLICATIONS (Continued)
SYNCHRONOUS INTERFACE TO TERMINAL OR PERIPHERAL DEVICE
ADDRESS BUS
CONTROL BUS
DATA BUS
RxD
TxD
RxC
SYNCHRONOUS
TERMINAL OR
PERIPHERAL
DEVICE
SCN2661/68661
TxC
SYNCHRONOUS INTERFACE TO TELEPHONE LINES
ADDRESS BUS
CONTROL BUS
DATA BUS
RxD
TxD
PHONE
LINE
INTERFACE
RxC
TxC
SYNC
MODEM
SCN2661/68661
DCD
CTS
RTS
DSR
DTR
TELEPHONE
LINE
SD00083
19
1994 Apr 27
相关型号：
SCN68661AC1N28
IC 1 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDIP28, 0.600 INCH, PLASTIC, DIP-28, Serial IO/Communication Controller
NXP
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