SCP2207VMU [NXP]
32-bit MPU, Image Cognition Processor, Automotive Qualified, MAPBGA 236;
| 型号： | SCP2207VMU |
| 厂家： | 
NXP |
| 描述： | 32-bit MPU, Image Cognition Processor, Automotive Qualified, MAPBGA 236 |
| 文件： | 总186页 (文件大小：1701K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor
Data Sheet: Product Preview
Document Number: SCP220x
Rev. 2.1, 06/2015
SCP220x
SCP220x ICP Family
Data Sheet
1
2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1
Introduction
1.1
1.2
The SCP220x function blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
SCP220x Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
The SCP220x is a family of highly-programmable Image
Cognition Processors (ICP) enabling imaging and video
applications for automotive smart cameras, video
surveillance cameras and consumer devices such as
personal media players. The ICPs of the SCP220x family
are programmable system-on-chip (SoC) featuring
CogniVue’s patented APEX™ technology providing high
computing performance at low power in a small package
size.
SCP220x Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2.1
2.2
2.3
2.4
Voltage islands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Buses and DMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3
4
System Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Core and I/O Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
PLL and Timing Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
External Memory Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Boot-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Low Power Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Interconnect and Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
NAND Flash Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Sensor Interface (SIF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Display Sub-System (DSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
USB 2.0 HIGH SPEED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Audio Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Media Storage MMC and MMCPlus blocks (compatible SD/SDHC) .42
I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
The SCP220x family comprises:
•
SCP2201 – Equipped with 128 Mbit (16 MB) of
stacked Mobile DDR SDRAM in package
•
SCP2207 – Equipped with 512 Mbit (64 MB) of
stacked Mobile DDR SDRAM in package
4.10 Pulse Width Modulated Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
4.11 KeyPad Scan Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
4.12 GPIOs and Alternate Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
4.13 Production Test and System Signals . . . . . . . . . . . . . . . . . . . . . . . . .61
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Clock Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
PAD and I/O registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Reset and Clock Gating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
NAND Interface Registers Description. . . . . . . . . . . . . . . . . . . . . . . .95
UART Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
SPI Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
5.10 Audio Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
5.11 MMC/SD Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
5.12 MMCPlus Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
5.13 I2C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
5.14 PWM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
5.15 KeyScan Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
5.16 GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
6
7
6.1
6.2
6.3
SCP2201 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
SCP2207 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
SCP220x Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
7.1
7.2
7.3
7.4
Absolute Maximum Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
Recommended Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . .180
Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
8
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
© Freescale Semiconductor, Inc., 2015
Introduction
1.1
The SCP220x function blocks
SCP220x
APEX Core
USB 2.0
OTG
Camera
Sensor
Interface
APU (96 CU + 96 CMEM)
...
CU ...CU
CU CU CU CU CU CU CU CU CU CU CU CU CU CU CU CU CU
NAND or
MoviNAND
Interface
Array Controller Processor
Display
Interface
Multi
Channel
DMA
Sequencer
RISC
Stream DMA
MicroSD/
SDHC
TV Out
Main Processor - ARM9
Memory Controller
Mobile DDR SDRAM
(stacked)
2
KeyPad
I S / AC’97
Power Manager
SPI
Master/
Slave
2
I C
UART
PWM
GPIO
Figure 1. SCP220x Image Cognition Processors
1.2
SCP220x Features
1.2.1
SCP220x General Features
CogniVue APEX Processor – programmable 34Billion-Operations per second Vision Processor with patented
massively parallel Array Processor Unit (APU) with 96 Computing Units (CUs) with dedicated memory, discreet
RISC processor, H/W acceleration blocks, wide-bandwidth stream DMAs and internal 64-bit data buses
ARM926EJ-S™ RISC processor with 16 KB of instruction cache (I-cache) and 16 KB of data cache (D-cache)
Multiple power domains for different peripheral IOs
1.2.2
Interconnect and Communication
Video Processing
1.2.2.1
Fully-programmable Array Processor (APEX) for running video/image processing algorithms
Video codecs support diverse resolutions at 30 fps with 4 Mbps maximum bitrate
Supported video decoding standards:
MPEG-4 Simple Profile and Advanced Simple Profile supports 720x480 at 30 fps
For other standards consult factory
Supported video encoding standard is MPEG-4 Simple Profile, 720x480 at 30 fps
SCP220x ICP Family, Rev.2.1
2
Freescale Semiconductor
Introduction
1.2.2.2
Audio Processing
Directly connects to I2S or AC97 compliant audio device
1.2.2.3
Graphics
True-color (24 bits per pixel) processing
2D graphics functions including: Bitblt, overlay, pixel-based alpha-blending, rotation, scaling, color space conversion,
color depth expansion and reduction
1.2.2.4
Image Sensor Interface
Sensor Interface (SIF) supports 10-bit input, 8-bit YUV datapath up to 10 M-pixel resolution
Integrated YUV image enhancement functions such as scale-down
1.2.2.5
Display Sub-System
Independent dual output, one digital, one analog
Digital:
•
•
LCD interface supports both TFT and buffered (CPU) LCDs
Supports up to four CPU-like devices (for example dual 8/9/16/18bit LCD modules and two other devices
with CPU-like interfaces) or supports up to WVGA TFT LCD up to 24 bits/pixel
•
ITU-R 601/656 compatible digital video output
Analog: Integrated 10-bit DAC for analog composite video output to TV (PAL or NTSC)
1.2.2.6
USB 2.0 High Speed Controller
USB 2.0 HIGH SPEED compliant
USB 2.0 PHY integrated on-chip
USB 2.0 On-The-Go
1.2.2.7
Audio Interface
I2S and AC97 compliant Audio Interface
1.2.2.8
Media Storage Interface
Supports SD/SDHC removable memory cards
Compatible MMC Plus Interface
Supports 8-bit NAND flash devices
Supports FAT-16 and FAT-32 file system with long name support and international characters
1.2.2.9
Serial Interfaces
Two UART (1x 4-pin, 1x 2-pin) interfaces and two SPIs
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
3
SCP220x Architecture Overview
1.2.2.10 Other Interfaces
General purpose I/O (GPIO) – selectable as alternative functions for various interface pins
Two PWM (Pulse width modulated) outputs with programmable frequency and duty cycle
JTAG test and debugging interface for the ARM926EJ-S processor
1.2.3
Reference Input Clock
Input clocks:
•
•
Clocks supplied by either a crystal or oscillator
10-30 MHz (13 MHz, 19.5 MHz, 24 MHz or 27 MHz suggested).
5 on-chip PLLs generate clocks for system, array processor, display interface, other interfaces and memory
Programmable internal clock frequencies
1.2.4
Boot-Up Options
Boot from either serial SPI or NAND Flash
1.2.5
Integrated Memory
SCP2201 has 128 Mbit DDR SDRAM integrated in package
SCP2207 has 512 Mbit DDR SDRAM integrated in package
1.2.6
Package
SCP2201 and SCP2207 are both used in the 236 MAPBGA package (9 x 9 x 1.24 mm).
1.2.7
POWER Supply
1.0V core and 3.0V I/O power (1.8V or 3.0V Sensor I/O power)
1.8V memory power supply
3.0V PLL power supply
3.3V supplies for USB and internal DAC
Multiple power domain within the core for power management
1.2.8
Ambient Operating Temperature
SCP2201 and SCP2207 chips operate between -40°C to +105°C, Automotive Qualified
2
SCP220x Architecture Overview
The SCP220x are system-on-chip offering a large selection of computation and communication blocks in a single
small form factor chip. The internal relationship between blocks within the chips can be represented by the following
figure:
SCP220x ICP Family, Rev.2.1
4
Freescale Semiconductor
SCP220x Architecture Overview
AHB 1 (32-bit)
Low Power
.....................
St ck
Audio/Video
Voltage Domain
S
M/S
M
M/S
a
e
d
Memory
Controller
Bridges
S
D
R
A
M
.....................
S
Multi-DMA
IC Core
Voltage Domain
JTAG
Controller
M
S
S
S
USB
SIF
M
S
Master
Slave
M/S Master/Slave
S
Reset
..... SCP2201/07 specific
M
DSS
S
M
M
S
ARM9
APU
96 CU+CMEM
M/S
S
M/S
Codec HW
Accerators
Bridges
S
S
S
Interrupt
Controller
M
RISC
Boot
Loader
AHB 2 (32-bit)
APEX
NAND
Crypto
S
S
Smart
Card
Key
Pad
GPIO
PWI
PWM
MP2TS
S
APB
Bridge
APB (32-bit)
S
SPI
RTC
Audio
I2C
UART
S
S
MMC
MMC plus
Figure 2. SCP220x Internal Architecture
2.1
Voltage islands
There are two voltage islands offering capabilities to lower power consumption when intensive computation is not
required. The chip can boot in one or the other mode, through external configuration (see 3.6.2, Boot-up
configuration), or can be switched by software. It is also possible to turn some blocks off for further power reduction
(see 3.7, Low Power Configurations).
2.2
Blocks
APEX
2.2.1
APEX is a programmable Vision Processor capable of 34 Billion-Operations per second.
APEX is composed of:
•
with patented massively parallel Array Processor Unit (APU) itself made of 96 Computing Units (CUs) with
dedicated memory, wide-bandwidth stream DMAs and internal 64-bit data buses
•
•
discreet RISC processor
H/W acceleration blocks
APEX is a Single Instruction Multiple Data (SIMD) type of parallel processor. It is normally programmed in a
proprietary SIMD Engine Language (SEL) to generate APU kernels. Custom APU kernels can be written with the
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
5
SCP220x Architecture Overview
additional APEX toolkit. Standard and custom kernels can be combined with the automated APEX usage
optimization tool ACF (APEX Core Framework).
APEX is then only used through supplied SDK, and no direct register accesses are required.
For advanced optimization needs, contact factory.
2.2.2
ARM926EJ-S RISC processor
The chip uses an ARM9 series as its main processor. It is a ARM926EJ-S™ RISC processor with 16 KB of
instruction cache (I-cache) and 16 KB of data cache (D-cache).
All the software runs on this processor and it sets up all the other blocks including the APEX.
Operating Systems supported:
•
Nucleus, embedded Real Time Operating System.
2.2.3
Reserved Use Blocks
We reserve the use of several blocks in the chip: Crypto, MP2TS.
2.2.4
Interconnect and Communication Blocks
Detailed description of the blocks can be found in 4, Interconnect and Communication.
2.3
Buses and DMA
There are four main buses in the chip:
•
•
•
AXI Fabric (64-bit)
AHB 1 and AHB 2 (both 32-bit)
APB (32-bit)
2.3.1
AXI Fabric
The AXI fabric (Advanced eXtensible Interface) provides high performance data transfers. It is linked to the use of
the APEX and so it is not recommended to access it directly. AXI provides an isolation from secondary data transfers
from peripherals and offers maximized performance on the main data movements from and to memory, image input
and output.
For your information, AXI provides a partial connectivity between the connected masters and slaves. The following
table illustrates what slaves each master can access. An “x” indicates connectivity between the master and slave.
Table 1. AXI Master/Slave Connectivity
Memory
Controller
AHB1
(data)
APEX
CMEM
apb3
APEX
SIF
S1
x
S2
x
S3
S4
S5
x
S6
AHB 1 (primary data)
USB
M1
M2
M3
M4
x
x
AHB 1 (instructions)
[reserved]
x
x
x
x
x
SCP220x ICP Family, Rev.2.1
6
Freescale Semiconductor
SCP220x Architecture Overview
Table 1. AXI Master/Slave Connectivity
[reserved]
DSS Bitblt
M5
M6
M7
M8
x
x
x
x
x
x
x
x
x
x
DSS Bitblt_mini
AHB 1 (secondary data)
x
2.3.2
AHB
There are two AHB (Advanced High-performance Bus) in the Chip. The first is the link between all the blocks. The
second is a dedicated bus for video codec operations.
2.3.3
APB
APB (Advanced Peripheral Bus) provides connectivity to a large number of relatively slow peripheral interfaces
blocs.
2.3.4
DMAs
There is an extensive number of DMAs (Direct Memory Access) in the chip. They play an important role in reaching
high computing performance in video/image processing.
In general, the DMAs are handled directly through the SDK.
2.4
Pin Configuration
The SCP220x are designed to be small chip and so have constrains on the number of pins available. To offer
maximum flexibility, the pins can have multiple functions selectable via software.
At most, a pin has a default function, a gpio use and an alternate function.
Also, the pin can have an internal Pull-Up (PU) or Pull-Down (PD) capability that could be activated by default.
Furthermore, the pin may have a direction and a configurable strength.
To illustrate, here is an example for the pin named audio_fsr.
4.12.1, GPIO and Alternate Function List tells us:
•
•
•
•
•
•
the main function is audio_fsr (its name)
if using as gpio it is the line 18
the alternate function is pwm2_out
the pin can have an internal Pull-Down
the PAD type is A
the power domain AUVDD
GPIO
Pin
Alternate
Power
PAD Type
A
PAD Resistor/Default
PD/none
gpio18
audio_fsr_p
pwm2_out
AUVDD
6.3, SCP220x Pinout tells us:
Freescale Semiconductor
SCP220x ICP Family, Rev.2.1
7
System Design Considerations
•
•
•
•
•
the pin belongs to the AUDIO power domain
the pin is capable of being an input or and output (bi-directional)
the pad strength can be configured for 2 mA or for 4 mA
the pin does NOT have its Pull-Down activated
the pin is at position M9 on SCP2201 and SCP2207
Pin Name
audio_fsr
Power Domain
AUDIO
PAD Type
Default PU/PD
none
SCP2201/0
7 Ball
Bi-dir. 2 mA / 4 mA
M9
A pin is configured as gpio when the corresponding gpio enable bit is active.
A pin is configured as the alternate function when the gpio enable bit is inactive and that the alternate enable bit is
active.
So a pin is configured as the primary function when the gpio enable bit is inactive and that the alternate enable bit
is also inactive.
See 4.12.1, GPIO and Alternate Function List for details.
Note: most pins will be in tri-state during and after reset. The pins will start their primary function during the boot.
3
System Design Considerations
3.1
Core and I/O Power
The SCP220x are low power system-on-chip with a power consumption generally under <250 mW (active image
processing with APEX).
They offer advanced power consumption reduction options see 3.7, Low Power Configurations.
In any case, all power need to be present at all times even if the chip is in power saving mode, undefined behavior
may happen if some powers are not present.
The IO supply allows (3.0 V DC 10%).
The Sensor Interface (SIF) allows for 3.0VDC 10%, or 1.8VDC -5%, +10%.
The table below provides the SCP220x pin information for core and I/O power.
Table 2. SCP220x Power Supply
Power Supply
Pin Names
Pin Description
1.0 V
VDD_CORE
VDD_LP
Power supply for IC core
Power supply for low power audio/video circuitry
Analog supply voltage for PLL
3.0 V
*
VDDA_PLL
VSSA_PLL
VDD_SDRAM
VDD_USB
VDDA_DAC
PLL power return (DO NOT CONNECT TO GROUND)
SDRAM core power
1.8 V
3.3 V
Power supply for USB
Analog supply voltage for internal DAC
SCP220x ICP Family, Rev.2.1
8
Freescale Semiconductor
System Design Considerations
Table 2. SCP220x Power Supply
IO supply for Sensor Interface block and I2C
3.0 V or 1.8V
3.0 V
VDD_SENSOR
VDD_OSC
VDD_SCCARD
VDD_GPIO
VDD_DIP
Power supply for crystal pad
IO supply for Smart Card Interface
IO supply for GPIOs and KeyScan
IO supply for DIP block
VDD_MISCIF
VDD_SDMMC
VDD_AUDIO
VDD_NAND
VSS
IO supply for MP2TS, UART, SPI, and JTAG interfaces.
IO supply for SD/SDHC/MMC Interface
IO supply for Audio Interface block
IO supply for NAND Interface block
Common ground
GND
VSSA_DAC
VSS_USB
Ground for internal analog DAC
Ground for USB
VSS_OSC
Ground for crystal pad
* See Figure 4 for VSSA_PLL connectivity
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
9
System Design Considerations
Figure 3. Powering the SCP220x
3.2
PLL and Timing Generation
The timing generation block provides and manages the clocks required by the internal logic and IP blocks. The
clocks are produced from internal PLLs. An external crystal oscillator or clock provides the input clock to the PLLs.
The following figure shows the connection between a crystal oscillator and the SCP220x. If the clock source is an
oscillator, the clock output signals (VDDA_PLL, VSSA_PLL) are not connected.
SCP220x ICP Family, Rev.2.1
10
Freescale Semiconductor
System Design Considerations
xtal
10 - 30 MHz
1M ohm
SCP220x
15 pf
clkin
clkout
15 pf
3.0 V
SYS_PLL
AP_PLL
DIP_PLL
IF_PLL
100 ohm
100 µF
VDDA_PLL
100 nf
VSSA_PLL
(PLL return)
MEM_PLL
Figure 4. Crystal Connected to SCP220x
The input clock drives the five internal PLLs:
•
•
•
•
•
SYS_PLL: System
AP_PLL: Array Processor Unit
DIP_PLL: Display Interface Port
IF_PLL: Interfaces
MEM_PLL: Memory
See 3.3, Clock Configuration for more details about the PLLs.
The SCP220x has different level of clock controls depending on the input oscillator or clock frequency:
•
•
•
•
Input is 24 MHz: this is the default, all the clocks are set automatically, no external clock setting
Input is 13 MHz, 19.2 MHz or 27 MHz: this is a pre-set, all clocks are set automatically through
an external clock setting, see 3.6.2, Boot-up configuration
Input is between 10 MHz and 30 MHz: this is a custom clock setting and so an external clock setting should
be chosen and then all the PLLs and clock configuration need to be managed, see 3.3, Clock Configuration
and then 5.2, Clock Configuration Registers.
t2
Clkin
t3
t4
Figure 5. Input Clock Timing
Table 3. Input Clock Timing
Parameter
Symbol
Min.
Typ.
Max.
Unit
Input clock period
Input clock rise time
Input clock fall time
Input clock duty cycle
t2
t3
t4
10
30
4
MHz
ns
4
ns
40
50
60
%
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
11
System Design Considerations
3.3
Clock Configuration
3.3.1
PLL configuration
The SCP220x has five internal PLLs as clock sources; all have the input reference clock as input:
•
•
•
•
•
SYS_PLL: System
AP_PLL: Array Processor Unit
DIP_PLL: Display Interface Port
IF_PLL: Interfaces
MEM_PLL: Memory
These five configurable internal clock sources have three configurable aspects:
•
•
•
PLL output frequency
PLL clock source for divider
Divider value
REF
IN
/NR
/NF
VCO
/2NO
RESET
PLL
/2
PLLOUT
RESET
Figure 6. PLL Programming Parameters
Each PLL can be configured to a wide range of output frequencies based on its NF, NR and NO settings, where:
•
•
•
NF (8-bit) ranges from 0 to 255
NR (5-bit) ranges from 0 to 31
NO (3-bit) ranges from 0 to 7; 2NO values: 1, 2, 4, 8, 16, 32, 64, 128
The PLL output frequency is derived from the following equation:
fOUT = (2 * fIN * (NF+1)) / (2NO * (NR+1))
where fIN is the input clock frequency. The following constraints must be met when deriving fPLLOUT.
•
•
•
•
fIN = input frequency must meet 10 Mhz < fIN < 30 Mhz
fREF = comparison frequency = fIN / (NR+1) must meet 10 Mhz < fREF < 30 Mhz
fVCO = VCO frequency = (2 * fIN * (NF+1)) / (NR+1) must meet 1000 Mhz < fVCO < 2000 Mhz
fOUT = output frequency must meet 20 Mhz < fOUT < 1000 Mhz
3.3.2
Configuring the clocks
There are two classes of clocks:
•
The system clocks (cmem_clk, ac_clk, arm_clk, sys_clk, mem_clk2x, mem_clk) that have extra hardware
controls so that changes are managed and they take default value from boot-up configuration; see 3.3.2.1,
System Clocks
•
The peripherals clocks are unmanaged. See 3.3.2.2, Peripheral Clocks
The PLL power-up default settings are controlled by either the recommended boot-up configuration (see 3.6.2,
Boot-up configuration) or software programmable registers (advanced use only).
SCP220x ICP Family, Rev.2.1
12
Freescale Semiconductor
System Design Considerations
The SYS_PLL and AP_PLL settings are applied to the PLL when the appropriate configuration bit is set in the clock
update register. The PLL has a “lock” time after the settings are applied. During this lock time, the timing_gen block
will glitchlessly switch the ARM926EJ-S processor and system clocks. The “lock” time is approximately 520 input
clock periods. It should be noted that if only the “NO” setting is changed the lock period is much shorter (9-10 input
clock periods).
The IF_PLL, DIP_PLL and MEM_PLL do not have any hardware ensuring clean transition. The appropriate software
clock gating must be activated before updating these PLLs.
The configuration of the ARM926EJ-S processor and system clocks is controlled by hardware mechanisms that are
initiated by a software “kick”, whereas, the AP and peripheral clock configurations do not have any hardware control
mechanisms. Software must manage all aspects of the clock configuration for the AP and peripherals.
The registers are described at 5.2, Clock Configuration Registers.
3.3.2.1
System Clocks
Three aspects of the ARM926EJ-S processor and system clocking can be individually updated:
•
•
•
The PLL configuration.
The output divider for the PLL.
The PLL to be used for the clock generation.
This allows a lot of flexibility during the overall clock configuration such as:
•
Using the other PLL while one PLL is locking. This prevents a switch over to the external reference clock
while the PLL is locking and may be required for performance reasons in some applications.
•
Using a common PLL for both the system and AP so that one of the PLLs can be powered down for current
savings.
Care should be taken in the order of the configurations such that an invalid frequency is not generated for the clock
domain.
The figure below shows the system clocks diagram:
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
13
System Design Considerations
1
ap_ref_clk_sel
timing_gen
4
1
pll_divide
SYS_PLL
AP_PLL
ap_clk_gate
/
cmem_clk
ac_clk
IF_PLL
CG
1-64
DIP_PLL
MEM_PLL
2
arm_clk_div
/2
/12, /10, /8,
/6, /4, /2
arm_clk
sys_clk
2
sys_clk_div
2
2
pll_sel
arm_clk2_div
/4, /3, /2, /1
SYS_PLL
AP_PLL
/12, /10, /8,
/6, /4, /2
arm2_clk
2
arm2_clk_en_div
3
mem_clk_div
sys2_clk6
/4, /3, /2, /1
/12, /10, /8,
/6, /4, /2
mem_clk2x
mem_clk
/2
/2
1
mem_ref_clk_sel
1
5
pll_divide
Interface PLL Select Register
2
1
SYS_PLL
AP_PLL
System Clock Configuration Register
AP Clock Configuration Register
AP PLL divide Register
MEM PLL divide Register
sys2_clk should match sys_clk
State after Reset
mem_clk_gate
3
/
4
5
IF_PLL
CG
1-64
DIP_PLL
MEM_PLL
6
.......
Figure 7. System Clocks
After reset, the system clocks are 96 MHz if the boot-up configuration matches the oscillator or crystal base
frequency. DS-10163-00-08 32/234
NOTE
The software bootloader can change the clocks settings but it is important to know that the System initialization
(Operating System and hardware subsystems) resets the clock setting as well.
There are three types of clock dividers:
•
The integer divider where is clock is divided by a integer value from 1 to 64. Shown as „/1-64. blocks in
diagram
•
•
Fixed divider by 2, shown as ‘/2’. block in diagram
Multiple choice dividers where clock is divider by one of the choice offered. The diagram shows these blocks
by their list of choices such as: ‘/4, /3, /2, /1’.
To modify the value of SYS_PLL, AP_PLL, corresponding multiplexer and divider, it is required to use the Clock
Update register to ensure proper transition, see.
NOTE
For advanced power saving mode, it is possible to gate clocks via the CG blocks. However, because of the reserved
multiplexer (memory used with synchronized clock to the ARM926EJ-S processor or from independent clock), the
mem_clk_gate should not be used.
3.3.2.2
Peripheral Clocks
There are five peripheral reference clocks:
if_ref_clock: interfaces reference clock
•
SCP220x ICP Family, Rev.2.1
14
Freescale Semiconductor
System Design Considerations
•
•
•
•
xga_ref_clock: digital display reference clock
sif_ref_clock: sensor interface reference clock
usb_ref_clock: USB (Universal Serial Bus) reference clock
tvout_ref_clock: analog display reference clock
*_ref_clk_sel1
pll_divide2
*_clk_gate1
SYS_PLL
AP_PLL
IF_PLL
/
.......
*_ref_clk
CG
1-64
DIP_PLL
MEM_PLL
1 Interface PLL Select Register
2 * PLL Divide Register
.......
State after Reset
* TVOUT, USB, SIF, XGA, IF
Figure 8. Peripherals Clocks
This if_ref_clk is used as a clock source for the following interfaces so that their external timing is unchanged when
the system clock frequency is adjusted.
•
mmc. This PLL clock is used to drive the MMC clock generator. The MMC clock generator has its own
configurable software divider. The target frequency for the MMC clock has a maximum of 20-25 Mhz so the
PLL should be programmed for twice that frequency as a minimum.
•
•
•
uart. The PLL clock is used in the baud rate generator and front end serializer/de-serializer.
spi. This PLL is used to drive the SPI clock generator and the SPI frontend interface.
Audio. This PLL clock is the clock source for the NCO in the audio block. The NCO is used to generate the
audio master clock. The audio master clock or a clock source connected to the master clock input is used
to derive the audio bit clocks and frame clocks. The NCO operates best at higher frequencies, so a 96 Mhz
setting is best for this application.
•
OS timer. This PLL clock is the clock source for the timer down counter. The timer has its own configurable
divider so the PLL clock frequency for this application is very flexible. RTC. This PLL clock is the clock source
for the NCO in the RTC timer. The NCO operates best at higher frequencies, so a 96 Mhz setting is best for
this application.
RTC. This PLL clock is the clock source for the NCO in the RTC timer. The NCO operates best at higher frequencies,
so a 96 Mhz setting is best for this application.
3.3.2.3
Clock Restrictions
System Clocking Restrictions:
•
•
Maximum ARM926EJ-S processor clock is 347.5 Mhz.
Maximum system clock is 120 Mhz.
AP Clocking Restrictions:
•
Maximum AP clock is 360 Mhz/180 Mhz (cmem_clk/ac_clk)
Other Clocking Restrictions:
•
•
•
•
Maximum SYS_PLL frequency is 719 Mhz
Maximum AP_PLL frequency is 632 Mhz
Maximum MEM_PLL frequency is 704 Mhz
Maximum DIP_MEM, IF_PLL frequency is 724 Mhz
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
15
System Design Considerations
•
If_ref_clk, xga_ref_clk, sif_ref_clk, usb_ref_clk and tvout_ref_clk maximum frequency is 133 Mhz
3.4
External Memory Interface
Memory Controller
3.4.1
The following diagram illustrates the system level architecture for the memory controller implementation.
Memory Controller
mem_clk
dqs_in
dqs_out
clk_out
apb
axi
DLL delay
APB Bridge
AXI Fabric
sdram_dqs
sdram_clkn
sdram_clk
Memory
Controller
data
sdram_data
sdram_ctrl
PAD
Muxing
control
pkg_opt
aclk
sys_clk
mclk_2xn
mclk_2x
mclk_n
mclk
mem_clk_2x
mem_clk
fb_clk
Figure 9. Memory Controller Architecture
The memory controller is configured such that the external memory interface is asynchronous to the system bus.
This allows the system to run at a faster speed than the external memory and also allows for dynamic system
frequency changes. By default, mem_clk is derived from mem_ref_clk. Dynamically changing this clock frequency
likely means that the memory controller cannot be used for the following reasons:
•
For DDR applications, the DDL delay line has a lock time whenever the “mclk” frequency is changed. Proper
read operation is not guaranteed during this lock time.
•
The memory controller timing registers can only be updated when the memory controller is put into a
configuration state. During this configuration state, external memory accesses are not allowed.
Registers are described in 5.6, Memory Controller.
3.5
Reset
A SCP220x chip becomes operational after a hardware reset through its reset pin (resetN). This pin, when asserted,
keeps the entire chip in a reset state. After the power supply voltages have stabilized, the external reset must remain
asserted for at least 1 sec. Then the chip waits for the PLLs lock for 500 input reference clock periods.
Figure 10: Reset Timing below illustrates the time line of events that occur within the chip when the external reset
is de-asserted.
SCP220x ICP Family, Rev.2.1
16
Freescale Semiconductor
System Design Considerations
Power Supply
External Reset
PLL Locked
1 µsec
500 input reference clocks
Delayed Reset
Figure 10. Reset Timing
As explained above, the internal reset architecture is controlled by an external reset pin but also by software initiated
reset requests from boot loader, system registers and watchdog [see the Figure below].
delayed reset
Arm held in reset
software block reset
Watchdog expired
Timing
external reset
Generation
Bootloading
enabled
Boot
Loader
Reset Block
ARM register
write
System
Registers
Watchdog
Figure 11. Internal Reset Architecture
NOTE
Most pins are in tri-state during and after reset so no damage could happen.
It is possible to reset the chip or a block through the system registers (See 5.4, Reset and Clock Gating).
3.6
Boot-up
3.6.1
Hardware Boot-up Configuration
The SCP220x chips need some pins to be set appropriately to boot and function properly.
•
•
hw_deep_secure = 0 (low)*
bootmode = 1 (high)*
*Suggestion: a 100 KOhms ( 5%, 1/16 W) can be use as pull-up or pull-down resistor.
3.6.2
Boot-up configuration
The SCP220x chips have a configurable boot mechanism. They offer options depending of the connected hardware
and boot configuration.
To configure the boot-up configurable parameters, a subset of the Display Interface Port Data bus pins (dip_data)
are sampled when reset is de-asserted. The dip_data pins are tri-stated by default; this allows the pull-up and
pull-down values to be sampled. The SCP220x have internal a pull-up and pull-down configuration so a default
behavior is available on some pin without requiring external pull-up or pull-down resistors.
The following table describes the configurable options.
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
17
System Design Considerations
Configurable Feature
Table 4. SCP220x Boot-up Configurable Options
dip_data Pins
(internal PU/PD)
Operation
Enables full-on power domain usage
by default
dip_data[7]
PD
0 = DISABLED*
1 = ENABLED
Enable ECC checking for NAND flash
booting
dip_data[6]
PD
0 = DISABLED*
1 = ENABLED
Boot Loader Mode
NEED external resistor!
See also section 3.6.4
dip_data[5-3]
PD PU PD
000 = DRAM (debug only)
001 = SPI port generic flash
010 = Reserved*
011 = SPI port ATMEL Dataflash
100 = NAND flash
Reserved
dip_data[2]
Reserved
PLL configuration so that the internal
clocks are 96 Mhz
dip_data[1-0]
PU PD
00 – input clk = 13 Mhz
01 – input clk = 19.2 Mhz
10 – input clk = 24 Mhz*
11 – input clk = 27 Mhz
See Section 3.3
* chip default
PU / PD : Pull-Up / Pull-Down
dip_data: Display Interface Port Data bus pins
To set a level externally on the dip_data pins, you can use a 4.7 KOhm ( 5%, 1/16 W) resistor as pull-up or pull-down.
3.6.3
Boot-up Timeline
The following timeline illustrates events that occur during a successful boot sequence. The internal configuration and
software binary image must be resident in the SPI device or NAND flash prior to initiating the boot-up sequence.
PLL lock time
time
Figure 12. Boot-up Sequence Timeline
It is possible to skip some steps in the boot-up sequence. For instance, if the software image was previously
downloaded and the DRAM was put into self refresh mode, then the DRAM initialization and code download steps
would not be necessary.
There are several possible ways to load the code into the SCP220x, they are presented in 3.6.4, Hardware Boot
Load Modes.
SCP220x ICP Family, Rev.2.1
18
Freescale Semiconductor
System Design Considerations
For all cases, the format of the downloaded data contains both the configuration information as well as the software
image. The data format is as follows:
4 bytes indicates the number of registers to configure. A value of “0”
# of cfg registers
will effectively bypass the configuration aspect.
cfg register address
4 bytes indicates register address. There is a special case. When this
field is “0”, it means that the register data should be treated as a delay.
cfg register data
cfg register address
cfg register data
4 bytes of data to write to the register or to use as a delay count.
cfg register address
cfg register data
4 bytes indicating the number of bytes of image data to follow.
4 bytes indicating the start address for this image “chunk”.
# of image bytes
image start address
image
“x” bytes (multiple of 4 bytes) of image data.
# of image bytes
image start address
image
A byte count of “0” indicates the end of the boot loading process. The
ARM is then taken out of reset.
# of image bytes
Figure 13. Hardware Boot Loader Load Description
3.6.4
Hardware Boot Load Modes
The hardware boot loader block facilitates code loading from different external interfaces.The external interface gets
data from an external device and the boot loader block moves the data from the receive FIFO to DRAM memory
While the Hardware Boot Loader is operating, the ARM926EJ-S processor is held in reset so that it does not start
executing code until the complete program store is in place. When the byte counter expires, indicating all code has
been copied, the boot loader indicates to the reset block that the ARM926EJ-S processor can be removed from
reset.
Possible boot loader configurations, as specified by the downloaded configuration information, are identified in the
table below.
Table 5. Configuring Boot Load Using dip_data[5:3] Pins
dip_data[5:3]
Description
b000
This setting will not invoke the boot loader and the ARM926EJ-S processor will be removed from
reset immediately. This is a debug mode of operation. Code must be written to memory through some
other means (ie. JTAG Port).
b011
Code is resident in a serial NAND flash connected to the SPI port. The serial Flash Memory is an
ATMEL DataFlash memory that supports the “continuous array read” command (0xe8).
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
19
System Design Considerations
Table 5. Configuring Boot Load Using dip_data[5:3] Pins
b001
Code is resident in a serial NAND flash connected to the SPI port. The serial Flash Memory is an
industry standard memory that supports the “read data bytes” command (0x03).
[b010]
b100
[RESERVED]
Code is resident in NAND flash. The NAND flash block read sequence is:
After reset is de-asserted, the bootloader will issue a “reset” command (“ff”) followed by a 25 µsec
delay.
The boot loader then issues the page read command (“00”) and 5 bytes of address (all “0”). This is
followed by a read confirm command (“30”).
Before proceeding further, a 50 µsec delay occurs.
A 2 Kbyte page is then read. If ECC is enabled four 512 byte page reads are issued.
If booting from NAND Flash, there is an optional ECC checking mode that may be enabled via a software register.
If ECC checking is enabled, the boot_loader checks for errors after a block is read from the device. Upon error
detection, the boot loader keeps the ARM926EJ-S processor in reset.
For NAND Flash, the data must be organized in the 2K Flash sector as follows.
7 spare bytes
512 bytes chuck
512 bytes chuck
512 bytes chuck
512 bytes chuck
9 ECC bytes
4x 512 bytes chucks = 2048 bytes image
Figure 14. NAND Flash Data Organization
3.7
Low Power Configurations
The SCP220x chips offer three power consumption reduction features described below: voltage islands, clock gating
and processor standby. They can be implemented independently for maximum control.
3.7.1
Voltage Islands
The SCP220x provides two voltage islands: Low Power Audio/Video domain and the IC Core domain (see Figure 2.,
SCP220x Internal Architecture).
The Low Power Audio/Video domain is powered through the VDD_LP pin. This domain allows for processing at
reduced power consumption. The ARM926EJ-S processor runs along with some of the blocks offering some
processing, audio and display capability (digital out only, see Figure 30., Display Sub-System (DSS) Internal
Architecture). Apex is not running and there is no input of images.
The IC Core domain is powered through the VDD_CORE pin. This domain contains the high performance blocks
such as the APEX, SIF and USB.
Low power consumption mode is achieved by removing power to the IC Core (VDD_CORE) by an external device
(i.e. power MOSFET) optionally controlled via a SCP220x GPIO pin. CogniVue Reference Design Kit (RDK) has this
low power option implemented. NOTE: it is recommended that all the other power lines be connected at all times
even if the corresponding blocks are not active.
SCP220x ICP Family, Rev.2.1
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Interconnect and Communication
3.7.2
Clock gating
It is possible to idle some blocks by gating their clocks. Clock gating is achieved through registers, see 5.4, Reset
and Clock Gating. Note that this functionality is provided by the SDK, direct register setting is recommended only for
custom bootloader code as SDK is not available at this stage.
3.7.3
Processor Standby
Another way to save power is to place the ARM926EJ-S processor in standby when no processing is required before
an event.
4
Interconnect and Communication
4.1
NAND Flash Interface
The SCP2201 and SCP2207 products have a NAND flash interface for connectivity to an external NAND flash
device. The following list details specific NAND flash features:
•
•
•
•
•
•
•
•
8-bit datapath
Software configurable external control signal timing
Incoming and outgoing datapath implemented using FIFOs
Software controlled command and page address
Read/Write datapath that bypasses the FIFO and allows direct access
Configurable page size
NAND flash read and write algorithms are software driven
Optional hardware ECC support; a simple ECC (1bit correct, 2 bit detect) as well as a Reed Solomon ECC
algorithm (4 bit correct)
•
Supports up to 4 external chip selects
4.1.1
NAND Flash connection
The following figure shows the connection between the SCP2201 or SCP2207 and a typical external NAND flash
device. It should be noted that the „ry_by. signal is not a dedicated pin on the SCP2201 or SCP2207. Instead this
connection, required for command status, is made to a GPIO. Alternatively, a software managed polling routing may
be used to determine when various commands are completed.
SCP2201
or
SCP2207
data[7:0]
data
nand_cle
nand_ale
oen
nand_D[7:0]
nand_cle
nand_ale
nand_ren
nand_wen
NAND Flash
wen
csn
nand_cen[3:0]
ry_by
GPIO
Figure 15. NAND Flash Connectivity
The following table describes the NAND Flash Interface pinout for the SCP220x
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
21
Interconnect and Communication
Table 6. NAND Flash Interface
Pin Direction
Signal
Alternate Function
gpio[81:74] or
Pin Description
nand_D[7:0]
Bi-dir.
NAND data bus or alternate function
mmcplus_data[7:0]
nand_cle
nand_ale
gpio[11]
Bi-dir.
Bi-dir.
Bi-dir.
Bi-dir.
Bi-dir.
Bi-dir.
Bi-dir.
Bi-dir.
Command latch enable or alternate function
Address latch enable or alternate function
Chip select or alternate function
Chip select or alternate function
Chip select or alternate function
Chip select or alternate function
Read enable or alternate function
Write enable or alternate function
gpio[10]
nand_cen[0]
nand_cen[1]
nand_cen[2]
nand_cen[3]
nand_ren
gpio[12] or mmcplus_clk
gpio[70] or mmcplus_cmd
gpio[71] or spi_Rxd1
gpio[72] or spi_Rxd2
gpio[14]
nand_wen
gpio[13]
4.1.2
NAND Flash Hardware Description
The hardware implementation for the NAND Flash block is as shown in the following diagram.
NAND Flash Block
AHB
sys_clk domain if_ref_clk domain
Registers
TX
FIFO
DMA
nand control
nand data
RX
FIFO
Interrupt
Generation
Interrupt
Figure 16. NAND Flash Hardware Architecture
The NAND Flash front-end contains a state machine that drives the external interface based on the configuration
settings from the software interface.
The front-end block issues commands, address and data as directed by the particular software configuration. The
transmit and receive fifos provide buffer space such that the internal bus-bandwidth required to move data is
minimized because AMBA AHB bursts can efficiently move data minimizing overall bus bandwidth usage.
The following diagrams illustrate what the external waveforms look like and also illustrate any software configurable
parameters that control the external signals.
SCP220x ICP Family, Rev.2.1
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Freescale Semiconductor
Interconnect and Communication
nand_csn
nand_cle
nand_ale
nand_we
nand_re
ry_by
t1
t3
t7
t7
t2 t4
t5 t6
cmd
a1 a2 a3
d1 d2 d3 d4 d5
data
Figure 17. NAND Flash Page Read Cycle
nand_csn
nand_cle
nand_ale
nand_we
ry_by
t1
t3
t7
t7
t2 t4
cmd
a1 a2 a3
d1 d2 d3 d4 d5
cmd
data
Figure 18. NAND Flash Page Write Cycle
It should be noted that ry_by is not a dedicated pin. Instead it has to be connected to a GPIO or else software must
poll the NAND Flash device to determine when various commands are completed.
NAND Flash has a page and block structure as illustrated in the following diagram.
IO width
A page is composed of the data and spare
Page
area. It represents the granularity that can
be read or written.
A block is composed of multiple pages and
represents the granularity that can be
erased.
The spare area is the location where
information such as ECC and bad blocks is
stored.
data spare
Figure 19. NAND Flash Page and Block Structure
The software configurable parameters in the NAND configuration register allow for a lot of flexibility when
programming and reading NAND Flash. There are two fields, page_size and spare size. As an example: lets say
that the data space in the NAND is 512 bytes and the spare space is 16 bytes (this is the case Toshiba 128Mx8
device).
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
23
Interconnect and Communication
Case 1 - ECC parity is enabled and only a single page is going to be written. In that case set page_size=512,
ecc_ena = 1, spare_size=0. The interface will write the page of data as it fills into the FIFO, generate parity during
this process and append the 6 bytes of ECC to the end of the data stream before interrupting indicating completion.
If it was a read, the interface would have read 512 bytes of data and placed them in the FIFO re-generating a new
ECC during this process. The interface would have then read the 6 bytes of ECC from the NAND and made the parity
check available to software before interrupting indicating completion.
Case 2 - ECC parity is enabled and multiple pages are read. In this case set page_size=512, ecc_ena = 1,
spare_size=10. Operation will proceed as described above except after the ECC has been read, 10 dummy bytes
are read effectively setting the address pointer to the beginning of the next block of data. The Flash will indicate it is
ready for the next block via it.s RY/BY pin at which time another "kick" will initiate another read process. The
"command" and "address" aspect of the cycle do not need to be repeated.
Case 3 - ECC parity is not required and a single page is going to be written. In this case set page_size=512, ecc_ena
= 0, spare_size=0. The interface will only write the page of data to NAND prior to interrupting.
The description of the control registers for the NAND Flash interface can be found at 5.7, NAND Interface Registers
Description.
4.2
UART
The SCP220x has two UARTs, referred to as UART and UART1, used for incoming or outgoing data paths. Note
that uart1_Rx and uart1_Tx signals of UART1 are available via shared I/Os and this UART does not support
CTS/RTS modem signals.
•
•
•
•
•
•
The UARTs have the following features:
Asynchronous interface
Programmable baud rate
Parity and framing error detection with indication via interrupts
Echo, local loopback and remote loopback diagnostic modes
Single start bit, 8-bit character length, programmable stop bits (1 or 2), programmable parity (even, odd or
none)
•
•
Independent receive and transmit FIFOs
The primary UART supports CTS/RTS modem signals for hardware flow control.
The following table lists the SCP220x pin information for the UART Interface.
Table 7. UART Interface
Alternate
Function
Signal
Pin Direction
Pin Description
uart_Rx
uart_Tx
uart_cts
gpio[23]
gpio[22]
Bi-dir.
Bi-dir.
Bi-dir.
UART serial receive data or alternate function
UART serial transmit data or alternate function
gpio[82] or spi_CS1
Clear to send modem signal or alternate
function
uart_rts
gpio[83] or spi_CS2
Bi-dir.
Request to send modem signal or alternate
function
UART1 signals are accessible only as alternate functions. These signals are listed in 4.12.1, GPIO and Alternate
Function List.
SCP220x ICP Family, Rev.2.1
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Interconnect and Communication
4.2.1
UART Hardware Description
The following diagrams illustrate the various loopback modes that are supported.
RX
FIFO
RX
FIFO
RX
FIFO
RX
TX
RX
TX
RX
TX
TX
FIFO
TX
FIFO
TX
FIFO
Echo
Local Loopback
Remote Loopback
Figure 20. Uart Diagnostic Loopbacks
The following UART protocol is supported with configurability for the stop and parity bits.
Start
d7
d6
d5
d4
d3
d2
d1
d0 Parity Stop Start
d7
Figure 21. Uart Protocol
The hardware implementation for the UART block is as shown in the following diagram.
UART Block
sys_clk domain if_ref_clk domain
Baud Rate
Generator
AHB
DMA
Registers
RTS
CTS
TX
TX
FIFO
RX
FIFO
Interrupt
Generation
Interrupt
RX
Figure 22. Uart Hardware Architecture
The Baud rate generator uses the software configurable baud rate register as a divider to generate the receive and
transmit clock enables.
The FIFOs are identical async fifos. The frontend block reads 8 bit wide data out of the transmit fifo, serializes it,
adds start,stop and parity bits and transmits it at the programmed baud rate. Similarily the frontend block receives
serial data and forms an 8 bit word. Start,stop and parity bits are stripped off. Parity errors and frame errors are
checked and generate interrupts.
The modem signals, when enabled, provide flow control to the hardware. The Clear To Send (CTS) input modem
signal indicates to the transmit state machine whether or not to send out a character. The receive state machine
generates the ready to send output when there is an appropriate amount of space available in the fifo.
The description of the control registers for the UART interface can be found at 5.8, UART Control Registers.
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
25
Interconnect and Communication
4.3
SPI
The Serial Peripheral Interface (SPI) provides an alternate data path to and from the SCP220x. The SCP220x device
has two SPI blocks on board referred as SPI and SPI1. The SPI blocks in the SCP2201 and SCP2207 devices each
have four chip selects (spi_CS, spi_CS1, spi_CS2, spi_CS3), four serial receive data signals (spi_Rx, spi_Rx1,
spi_Rx2, spi_Rx3) and a serial transmit data signal (spi_Tx). (Note that three of the chip selects and three receive
signals of SPI are accessible via shared I/Os). For more details, refer to 4.12.1, GPIO and Alternate Function List.
SPI1 has a dedicated clock, a chip select, and transmit and receive I/Os as shown below in Table 8.
This interface is compatible with the Motorola SPI specification and provides the following features:
•
Four wire synchronous full duplex interface using a clock, chip select, serialized receive data and serialized
transmit data
•
Configurable as master or slave. The master sources the clock and chip select and the slave sinks these
pins.
•
•
•
•
•
128-byte transmit FIFO and 128-byte receive FIFO
Programmable clock rate (master mode only)
Programmable frame size
Supports “continuous” mode of operation
Programmable clock phase (SPH) and polarity (SPO)
The following table lists the SCP220x pin information for the SPI.
Table 8. SPI Signals
Alternate
Function
Signal
Pin Type
Pin Description
spi_Clk
spi_CS
spi_Tx
gpio[29]
gpio[28]
Bi-dir.
Bi-dir.
Bi-dir.
Bi-dir.
Bi-dir.
Bi-dir.
Bi-dir.
Bi-dir.
SPI serial clock or alternate function
SPI slave select or alternate function
gpio[26]
SPI serial transmit data or alternate function
SPI serial receive data or alternate function
SPI1 serial clock or alternate function
spi_Rx
gpio[27]
spi1_Clk
spi1_CS
spi1_Tx
spi1_Rx
mp2ts1_clk
mp2ts1_sync
mp2ts1_valid
mp2ts1_data
SPI1 slave select or alternate function
SPI1 serial transmit data or alternate function
SPI1 serial receive data or alternate function
The clock phase and clock polarity configurability allow for four modes of operation. The clock phase controls which
edge of the clock that the transmitter transitions data and the receiver samples data. Transmission and reception of
data operate on opposite edges of the clock. The polarity controls whether or not the clock is high or low during the
inactive period. The following four diagrams illustrate the operation for these four modes for a byte length transaction.
When SPH=0, data is transmitted on the falling edge and sampled on the rising edge. When SPH=1, data is
transmitted on the rising edge and sampled on the falling edge.
When SPO=0, the clock is low during inactivity (ie. chip select de-asserted). When SPO=1, the clock is high during
inactivity.
SCP220x ICP Family, Rev.2.1
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Freescale Semiconductor
Interconnect and Communication
1
2
3
4
5
6
7
8
spi_sck
spi_ssn
d7
d6
d5
d4
d3
d2
d1
d0
spi_txd/rxd
Figure 23. SPI Clock Phase/Polarity - SPH=0, SPO=0
1
2
3
4
5
6
7
8
spi_sck
spi_ssn
d7
d6
d5
d4
d3
d2
d1
d0
spi_txd/rxd
Figure 24. SPI Clock Phase/Polarity - SPH=1, SPO=0
1
2
3
4
5
6
7
8
spi_sck
spi_ssn
d7
d6
d5
d4
d3
d2
d1
d0
spi_txd/rxd
Figure 25. SPI Clock Phase/Polarity - SPH=0, SPO=1
1
2
3
4
5
6
7
8
spi_sck
spi_ssn
d7
d6
d5
d4
d3
d2
d1
d0
spi_txd/rxd
Figure 26. SPI Clock Phase/Polarity - SPH=1, SPO=1
4.3.1
SPI Hardware Description
The hardware implementation for the SPI block is as shown in the following diagram.
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
27
Interconnect and Communication
SPI Block
sys_clk domain
if_ref_clk domain
spi_clk domain
spi_clk
Master Clock
Generator
master/
slave
AHB
DMA
Registers
spi_csn[3:0]
TX
FIFO
TX
RX
RX
FIFO
Interrupt
Generation
Interrupt
Figure 27. SPI Hardware Architecture
The frontend sub-block is operating in the spi_clk domain whether or not the SPI interface is configured as a master
or slave. The clock is tapped off the external pad so that the internal timing
requirements within the frontend are identical for master and slave operation. The frontend block is primarily a
serialization and de-serialization engine that pops and pushes data from/to the fifos. When the frontend gets a clock
edge when selected, its starts serializing transmit data and de-serializing the receive data. When a “word” has gone
through the serialization process, the frontend pushes the word into the receive fifo and pops the transmit fifo. The
process then repeats until the chip select is de-asserted.
The master clock generator is only used when the SPI block is configured as a master. The clock generator creates
an external SPI clock that is a programmable divider of the interface PLL clock. The clock generator must also create
the master chip select since it gets asserted before the external SPI clock starts wiggling. The chip select and
external SPI clock start a transaction when a data event has occurred in the FIFOs. This most likely is the event of
the transmit FIFO containing data. A FIFO not empty signal traverses clock domains and is used to kick activity within
the clock generator. Similarily, when the transmit fifo becomes empty (and the last data has been transmit/received),
the clock generator de-activates the external clock and chip select.
The receive and transmit FIFOs are asynchronous with one side in the internal system clock domain and the other
side in the interface reference clock domain. The read and write pointers cross clock domains through the technique
of converting the pointer to a gray code, double sampling and converting back to a pointer. The limitation that this
imposes is that the databus size must not be dynamic. The databus size is software configurable but cannot
dynamically change while the fifo is in use.
The description of the control registers for the SPI interface can be found at 5.9, SPI Registers.
4.3.2
SPI Port Timing
t13
spi_clk
inputs
t14 t16
t15
outputs
Figure 28. SPI Port Timing
SCP220x ICP Family, Rev.2.1
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Interconnect and Communication
Table 9. SPI Port Timing
Symbol
Parameter
Min.
Typ.
Max.
Unit
SPI port clock frequency (master)
SPI port input setup time (master)
SPI port input hold time (master)
SPI port output delay time (master)
t13
50
MHz
ns
t14 (3.0 V)
t16 (3.0 V)
t15 (3.0 V)
4.3
0.25
ns
10.3
ns
4.4
Sensor Interface (SIF)
The Sensor Interface receives data from one of two sources – the external sensor or from memory. Supported
format(s) of input data from the sensor:
•
YUV422 stream
NOTE
The Sensor Interface block may be programmed to accept YUV422 data in UYVY,
YUYV, VYUY and YVYU formats. Input image sizes up to 10M-pixels are supported
at clock frequencies up to 160 MHz.
Output image formats supported by the Sensor Interface block are:
•
•
YUV422 Stream
YUV420 Planar
The Sensor Interface also provides the following functionality:
•
•
•
•
•
•
•
•
scale down:
average mode scaling by: 1, 1/2, 1/4 and 1/8
decimation mode scaling by : horizontal and vertical decimation
adaptive luminance using histogram table build or gamma correction
image effects: grey scale, sepia, negative, emboss, sketch
edge enhancement
image smoothing using a LPF with 9 taps for luminance and 5 taps for chrominance coefficients
WOI (window of interest) used for cropping the input images
The SIF is controlled via the SDK under the Sensor Device Interface (SDI).
The following table lists the SCP220x external pinout of the Sensor Interface (SIF).
Table 10. Sensor Interface (SIF) External Pinout
Signal
Alternate Function
Pin Direction
Pin Description
sensor_D[9:0]
sensor_pclk
sensor_rclk
sensor_fclk
sensor_clkout
sensor_fodd
-
Input
Input
Input
Input
Bi-dir.
Bi-dir.
Sensor data
-
Sensor pixel clock
-
Sensor horizontal sync signal
Sensor vertical sync signal
-
gpio[1]
gpio[52]
Sensor source clock or alternate function
Field (odd, even) or alternate function
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
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Interconnect and Communication
Table 10. Sensor Interface (SIF) External Pinout
gpio[53] Bi-dir. Sensor GPIO or alternate function
sensor_gpio
t5
sensor_pclk
t6
t7
inputs
Figure 29. Sensor Interface Timing
Table 11. Sensor Interface Timing
Parameter
Symbol
Min.
Typ.
Max.
Unit
Sensor pixel clock frequency
Sensor input setup time
t5
160
MHz
nsec
nsec
nsec
nsec
t6(3.0V)
t6(1.8V)
t7(3.0V)
t7(1.8V)
3.2
3.2
Sensor input hold time
0.75
0.75
4.5
Display Sub-System (DSS)
The Display Sub-System (DSS) has two types of outputs through the Display Interface Port:
•
•
Digital, for LCD (1x) or CPU-like (x4) interfaces
Analog, generates NTSC/PAL composite signal
To minimize the load on the processor and APEX, there are two advanced resize/format blocks Bitblt and Bitblt mini.
The DSS has mixed voltage islands; the figure below gives more precision about the correspondence:
AHB 1 (32-bit)
Low Power
M
M
S
S
S
Audio/Video
Voltage Domain
Bitblt
Bitblt mini
Full Power
Voltage Domain
DIP
M - Master
S - Slave
M/S - Master/Slave
Internal
DAC
Figure 30. Display Sub-System (DSS) Internal Architecture
SCP220x ICP Family, Rev.2.1
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Freescale Semiconductor
Interconnect and Communication
4.5.1
Display Interface Port (DIP) and TV Output
The Display Interface Port (DIP) interfaces the SCP2201 or SCP2207 to an external video/display device such as
an LCD or a television.
The external display controller in the SCP2201 and SCP2207 devices may be a TFT LCD or four CPU-like interface
devices
The DIP has the following features:
•
Color format resizing (RGB24 -> RGB666/RGB565; RGB666->RGB24/RGB565;
RGB565->RGB24/RGB666, YUV422->YUV444)
•
Display Bus Interface (DBI): Drives an LCD, LCD Controller or CPU-type interface. Four chip selects are
available to support up to four devices including any combination of LCD Controllers and/or other devices
with CPU-type interfaces.
•
•
Timing Interface: Drives an external video device (RBG LCD) with hsync/vsync/blank signals; when this
mode is enabled, only TFT LCD devices may be used. This interface supports up to WVGA resolution.
TV Interface: This analog interface derives timing information from an internal NTSC/PAL video encoder to
drive video data at correct intervals. Maximum resolution supported is 640x480 (VGA).
The following figure shows a configuration with single TFT-RGB LCD and a TV connection to the DIP. In this case,
the internal SCP220x video encoder and DAC are used to derive the analog TV signal.
Figure 31. TFT-RGB LCD and TV Connected to DIP (Using Internal DAC)
SCP220x ICP Family, Rev.2.1
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Interconnect and Communication
Figure 32. RGB-type Display Waveform Diagram
The following figure shows a configuration with dual LCDs and a TV connection to the DIP. In this case, the internal
SCP220x video encoder and DAC are used to derive the analog TV signal.
data
cs
Second LCD
SCP220x
data
cs
dip_D
dip_CSn0
dip_CSn1
dip_CSn2
dip_CSn3
LCD
oe
rs
we
oe
rs
dip_OEn
dip_RS
we
dip_Wrn
3.3V
DAC_AVDD
DAC_AVSS
0.1 µF
DAC_vref_in
DAC_rset
10 µF
1.02 KOhm
(+/- 1%)
DAC_vref_out
TV
DAC_comp
DAC_io
0.01 µF
video_in
75 Ohm
Figure 33. CPU-Type LCD and TV Connected to DIP (Using Internal DAC)
The figure below illustrates timing for DBI connectivity to a CPU-type interface.
SCP220x ICP Family, Rev.2.1
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Interconnect and Communication
dip_RS
dip_CSn
dip_OEn
dip_Wrn
dip_D
xxxxxx
valid read data
valid write data
t0
t1
t2
t3
t4
t1
Timing parameters depend on CPU clock and modifying the CPU clock frequency
will alter the duration of the data transfer.
t0 - Width of the overall read cycle + 1
t1 - Time between transactions + 1
t2 - Time up to start of Wrn pulse and start of write data + 1
t3 - Width of Wrn pulse + 1
t4 - Extend write data after Wrn pulse + 1
Figure 34. DBI to CPU-type Display Waveform Diagram
The following table lists the SCP2201 and SCP2207 pin information for the DIP. The DAC signals correspond to the
TV Output feature available for all SCP220x products.
Table 12. Display Interface Pins
SCP2201, SCP2207
Signal
Alternate
Function
Pin Direction
Pin Description
dip_data[23]
dip_data[22]
gpio[51] or
uart1_txd
Bi-dir.
Digital video data or alternate function
gpio[50] or
uart1_rxd
Bi-dir.
Digital video data or alternate function
dip_data[21]
dip_data[20]
dip_data[19]
dip_data[18]
dip_data[17]
gpio[49]
gpio[48]
gpio[47]
gpio[46]
Bi-dir.
Bi-dir.
Bi-dir.
Bi-dir.
Bi-dir.
Digital video data or alternate function
Digital video data or alternate function
Digital video data or alternate function
Digital video data or alternate function
Digital video data or alternate function
gpio[3] or
scl_sec
dip_data[16]
gpio[4] or
sda_sec
Bi-dir.
Digital video data or alternate function
dip_data[15:0]
dip_pclk
-
Bi-dir.
Bi-dir.
Bi-dir.
Digital video data bus
gpio[5]
Digital video pixel clock or alternate function
Digital video output enable or alternate function
dip_OEn
gpio[15] or
dip_blank
dip_RS
dip_Wrn
dip_CSn0
dip_hsync
dip_vsync
-
Output
Output
Output
Digital video register select or alternate function
Digital video write enable or alternate function
Digital video chip select 0
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
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Interconnect and Communication
Table 12. Display Interface Pins
dip_CSn1
-
Output
Bi-dir.
Bi-dir.
Bi-dir.
Digital video chip select 1
dip_CSn2
dip_CSn3
gpio[24]
gpio[25]
gpio[54]
-
Digital video chip select 2 or alternate function
Digital video chip select 3 or alternate function
External synchronization frame pulse or alternate function
dip_cpu_vsync
DAC_comp
Analog
Output
Analog output of the DAC; signal can drive 1.0 Vpp on 75
ohm load
DAC_vref_out
DAC_rset
-
-
Analog
Output
Voltage reference output. This output delivers 1.140 V
reference voltage from cell. It is normally connected to the
VREFIN pin.
Analog In/Out An external resistor Rset connecting DAC_rset pin to AVSS
adjusts the magnitude of the DAC full-scale output current.
Recommended setting is 1.02 KOhm with 1% tolerance.
DAC_vref_in
DAC_io
-
-
Analog Input
Reference voltage input. It is suggested to place 0.1 µF
ceramic capacitor between this pin and AVSS pin externally.
Analog
Output
Analog output pin (with drive strength) to which a resistor
and capacitor is attached to ground to set the output current
of the DAC
Figure 35. DIP (TFT-RGB-type) Port Timing
Table 13. DIP (TFT-RGB-type) Port Timing
Parameter
Symbol
Min.
Typ.
Max.
Unit
DIP port pixel clock frequency
DIP port output delay time
t10
70
MHz
ns
t11 (3.0 V)
5.5
NOTE
DIP’s CPU-type protocol does not have a reference clock to determine setup/hold
time for dip_data[17:0] (For CPU Read transaction). Timing, as shown in Figure 35,
is dependent on individual CPU-type LCD, configurable within DIP.
SCP220x ICP Family, Rev.2.1
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Interconnect and Communication
4.5.2
Bitblt and Bitblt mini
Bitblt and Bitblt mini are supported through the SDK under the Graphic Display Interface (GDI).
4.6
USB 2.0 HIGH SPEED
The USB Interface has the following features:
•
•
•
•
•
USB 2.0 HIGH SPEED compliant
SCP2201 and SCP2207 devices support USB OTG
USB 2.0 PHY is integrated on chip
Supports high-speed (480 MHz), full speed (12 MHz), and low speed (1.5 MHz) operation
Supports seven physical endpoints - one control and six endpoints configurable as IN or OUT. The IN/OUT
endpoints are software configurable as bulk, isochronous, interrupt or control
The following table lists the SCP220x pin information for the USB Interface.
Table 14. USB Interface
Alternate
Function
Signal
Pin Direction
Pin Description
Indicates A or B cable
usb_phy_id
-
-
Analog USB pad
Analog USB pad
usb_phy_vbus
Vbus power monitor input. This is a 5 V
signal (+/-10%) with a max value of 5.5 V .
usb_phy_Plus
usb_phy_Minus
usb_phy_res
-
-
-
Analog USB pad
Analog USB pad
Analog USB pad
USB data plus
USB data minus
External resistor of 8.2 K 1% should be
connected from here to ground
utmiotg_drvvbus
gpio[73]
Bi-dir.
Externally controls power source for USB
VBUS voltage or alternate function;
The usb_phy_vbus signal monitors the 5.0 V VBus signals for USB 2.0 HIGH SPEED. The following figure illustrates
USB interface connectivity with the host.
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
35
Interconnect and Communication
SCP220x
usb_phy_id
usb_phy_Plus
usb_phy_Minus
usb_phy_rext
Host
8.2KOhm
(+/- 1%)
VBUS
usb_phy_vbus
utmiotg_drvvbus
out
in
Charge
Pump
Figure 36. USB/Host Connectivity
4.7
Audio Interface
The Audio Interface provides a direct connection to either voice quality or high-quality audio ADC/DAC. The Audio
Interface has the following features:
•
•
•
•
Supports I2S or AC97 interface protocol
Supports full duplex data path
Separate receive and transmit FIFOs
Software configurable hardware interface to support a variety of I2S and AC97 applications
Figure 35 shows the SCP2201/SCP2207 audio interface connections to an audio DAC.
SCP2201/
SCP2207
clkr
clkx
dr
audio_clkr
audio_clkx
audio_dx
audio_dr
audio_fsr
audio_fsx
mclk
Audio
DAC
dx
fsr
fsx
clk
Figure 37. Audio Interface
The following lists the SCP2201 and SCP2207 pin information for the Audio Interface.
Table 15. Audio Interface Pins
Alternate
Function
Signal
Pin Direction
Pin Description
audio_clkr
audio_clkx
gpio[16]
gpio[19]
Bi-dir.
Bi-dir.
Audio receive bit clock or alternate function
Audio transmit bit clock or alternate function
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Interconnect and Communication
Table 15. Audio Interface Pins
audio_dr
audio_dx
audio_fsr
gpio[17]
gpio[20]
Bi-dir.
Bi-dir.
Bi-dir.
Audio receive data or alternate function
Audio transmit data or alternate function
gpio[18] or
pwm2_out
Audio receive frame clock or alternate function
audio_fsx
mclk
gpio[21]
-
Bi-dir.
Bi-dir.
Audio transmit frame clock or alternate function
Audio clock source from external audio DAC.
There is a large degree of flexibility within this interface that allows support for the following applications:
•
•
•
AC97 controller sourcing the bit clock
AC97 controller sinking the bit clock
I2S controller with a common clock and sync for both receive and transmit. Clock and sync are configurable
as source or sink.
•
I2S controller with a separate clock and sync for the receive and transmit. Clocks and syncs are configurable
as source or sink.
The following sample waveforms illustrate the configurability available within this interface. The waveforms also
identify what timing aspects are software configurable.
frame_period
frame_width
clk
fs
txd/rxd
delay
word_length
Figure 38. I2S Stereo Transmission
frame_period
frame_width
clk
fs
txd/rxd
delay
word_length
Figure 39. I2S Mono Transmission
SCP220x ICP Family, Rev.2.1
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37
Interconnect and Communication
frame_period (48kHz)
frame_width (1 channel)
clk
fs
txd/rxd
ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch8 ch9 ch10 ch11 ch12 ch0
16-bits 20-bits
Figure 40. AC97 Mode of Operation
4.7.1
Audio Interface Hardware Description
The hardware implementation for the Audio block is as shown in the following diagram.
NCO
mclk
fsx
fsr
clkx
clkr
Clock
Generator
APB interface
DMA sideband
Registers
TX1
FIFO
Frontend
RX1
FIFO
txd
rxd
Interrupt
Generation
Interrupt
Audio Block
Figure 41. Audio Hardware Architecture
The clock generator block takes the software configuration from the registers block and divides the master clock
down appropriately to produce the bit clocks for the transmit and receive. Software configuration also controls the
PAD enables at the top level. If the ASIC sources the bit clocks, the PADs are enabled otherwise the bit clocks are
inputs and are driven by an external source. Irregardless of the bit clock source, the bit clocks re-enter the audio
block and are used as clocks in the frontend block. Software configuration select either the positive edge or negative
of the clock and also select whether the receive section has it.s own unique bit clock or uses the same bit clock as
the transmit section.
The frontend block primarily serializes and de-serializes the data form the receive and transmit fifos. The frame/sync
pulses are also generated through a software configured divide of the bit clocks.
The transmit and receive fifos are asynchronous fifos with the internal side residing in the system clock domain and
the external side residing in the bit clock domains. This is the mechanism for crossing between the two clock
domains.
The frontend operates quite differently when running in the I2S mode than when running in the AC97 mode. The I2S
mode operates in stereo or mono. The difference between the two is that the fifos are accessed twice for the stereo
mode of operation and only once for mono mode. The stereo mode sends left/right channel data on one edge of the
frame signal and sends right/left channel data on the other edge of the frame signal. The frame sync will typically be
configured with a 50% duty cycle. Mono mode only sends data on the assertion of the frame signal. In this case the
frame signal is typically a pulse that occurs at the beginning of the frame. Data is always sent MSB first. The fifo can
SCP220x ICP Family, Rev.2.1
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Interconnect and Communication
only be accessed with width increments of 8,16 or 32 bits. If the actual word length is not on these boundaries, a
larger data width is used with zeros padded in the extra bits (the data is right justified). The data organization in the
fifo is dependant on the word length. Also, for stereo applications, the left and right channel data alternate. The
following diagram illustrates some examples of fifo data organization.
32-bit
32-bit
32-bit
R
R
R
L
L
L
R
R
R
L
L
L
L
2
4
6
1
3
5
R
L
Stereo mode - 8-bit words Stereo mode - 20-bit words Mono mode - 16-bit words
Figure 42. I2S FIFO Data Organization
AC97 is comprised of 13 channels of which the first channel is 16 bits and the rest are 20 bits in length. The frame
period is 48 Khz. The following diagram illustrates the channel organization.
0
1
2
3
4
5
6
7
8
9
10
11
12
slot #
sync
CMD
ADDR
CMD
DATA
PCM L PCM R LINE 1
PCM
PCM L PCM R
PCM
LFE
LINE 2
DAC
HSET
DAC
TAG
TAG
IOCTRL
sdata_out
sdata_in
FRONT FRONT
DAC
CENTER SURR SURR
PCM L
(n+1)
PCM L PCM R PCM R PCM L PCM R PCM C
(n+1)
(n+1)
(n+1)
(n+1)
(n+1)
(n+1)
STATUS STATUS
ADDR DATA
LINE 1
ADC
PCM
MIC
LINE 2
ADC
HSET STATUS
ADC IOCTRL
PCM L PCM R
RSVRD RSVRD RSVRD
Figure 43. AC97 AC Link Frame Organization
The AC-link output slots are described below. Data for channels 3-12 come from the transmit fifo. If multiple channels
are enabled it is assumed that the data is organized in the fifo in the order that the channel gets transmitted.
Channels 0, 1, 2 and 12 are driven by software register configurations and accesses.
Slot
Name
Description
0
1
SDATA_OUT TAG
Control CMD ADDR write port
Control DATA write port
PCM L&R DAC playback
Modem line 1 DAC
MSBs indicate which slots contain valid data. LSBs convey codec ID.
Read/Write command bit plus 7 bit codec register address.
16 bit command register write data.
2
3,4
5
16,18,20 bit PCM data for left and right channels.
16 bit modem data for modem line 1 output.
6,7,8,9
10
PCM center, surround L&R, LFE
Modem Line 2 DAC
16,18,20 bit PCM data for center, surround L&R, LFE channels.
16 bit modem data for modem line 2 output.
11
Modem handset DAC
Modem IO control
16 bit modem data for modem handset output.
GPIO write port for modem control.
12
10,11
SPDIF Out
Optional AC-link bandwidth for SPDIF output.
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
39
Interconnect and Communication
6-12
Double rate audio
Optional AC-link bandwidth for 88.2 or 96khz on L, C, R channels.
The AC-link input slots are described below. Data from slots 3-11 (if valid) is written into the receive fifo in the order
that the channel arrives. Valid data from channel 1,2 and 12 is presented in a software register. An interrupt/status
indicator informs software that the register contains new data.
Slot
Name
Description
0
1
SDATA_IN TAG
STATUS ADDR read port
STATUS DATA read port
PCM L&R ADC record
Modem line 1 ADC
MSBs indicate which slots contain valid data.
MSBs echo register address. LSBs indicate which slots request data.
16 bit command register read data.
2
3,4
5
16,18,20 bit PCM data from left and right channels.
16 bit modem data for modem line 1 input.
6
Dedicated Microphone ADC
Vendor reserved
16,18,20 bit PCM data from optional 3rd ADC input.
Vendor specific (enhanced input for docking, array mic, etc.
16 bit modem data for modem line 2 input.
7,8,9
10
11
12
Modem Line 2 ADC
Modem handset ADC
Modem IO status
16 bit modem data for modem handset input.
GPIO read port for modem status.
Channel 1&2 are used to read and write registers within the codec. The mechanism to utilize these channels is not
through the fifo datapath. Instead software registers exist for the codec address, write data and read data.
Configuration of these registers will enable channel 1&2 in the next audio frame. An interrupt/status indicator
provides feedback on the completion of register writes or on the availability of register read data. More details of this
operation is described in the register definitions. In a similar fashion, the modem IO control and status (channel 12)
are also controlled by software registers.
AC97 codecs have a reset input. It is assumed that this is a GPIO and under software control. Whether or not the
codec sinks or sources the bit clock is determined by the conditions when the reset is removed. If the codec detects
a bit clock present (minimum 5 clocks) while reset is asserted it will be configured to sink the bit clock, otherwise it
will source the bit clock. Depending on the application (ASIC sinking or sourcing the bit clock) software must
appropriately configure and enable the bit clock generation prior to releasing the codec reset if the application
requires the ASIC to source the bit clock. This sequence of events must occur everytime the codec is reset.
There are 3 types of codec resets. The external pin reset (as described above) is a “cold” reset. When a cold reset
occurs all codec registers are reset and bit clock sourcing is re-determined. A “warm” reset will re-activate the
AC-link without resetting the codec registers. A “warm” reset is indicated by a 1 µsec pulse on the sync line. Software
can initiate this process through register configuration. The third reset mechanism is a register bit in the codec.
Software has access to this mechanism through the regular codec register configuration process.
The codec can also be placed in “power-down” mode. This is achieved by writing to a particular register in the codec.
Since this mechanism requires the hardware to enter a particular state after channel 2 has been sent, in addition to
the codec register configuration process, a software indicator bit must be set. To exit from this state a “warm” reset
must be issued.
The AC-link provides 12 channels (@ 20 bits) with a frame rate of 48 Khz. The interface also supports a mechanism
that allows for sampling rates other than 48 Khz. Data rates of 44.1 Khz, 88.2 Khz and 96 Khz are also supported.
The double-rate audio (88.2 Khz or 96 Khz) is supported by combining two slots per DAC channel. This would utilize
the optional alternate channel source for channels 6-12.
Up-sampling is not required to support the 44.1 Khz or 88.2 Khz data rates. Channel 0 (in both the incoming and
outgoing data stream) contains valid channel flags. This provides the mechanism to send valid data in a sub-set of
SCP220x ICP Family, Rev.2.1
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the frames being sent. A 44.1 Khz data rate needs valid data in only 441 frames for every 480 frames transferred at
48 Khz. The codec determines when data is sent by setting the channel request bits in the incoming TAG
information in channel 0. These are examined by hardware, and the appropriate channels are tagged as
valid and filled with data. Since it is assumed that the fifo is filled with the appropriate sequence of data
depending on which channels are enabled, the hardware must wait until all channel requests (for channels
that are enabled) are requesting since it is not possible to send a channel data in a different sequence
than that present in the fifo. Similarily it is assumed that the receive data remains in order (ie. All channels
are valid or not valid) and the data is written to the fifo as it is received.
A detailed view of the physical AC-link protocol is illustrated in the following diagrams.
sync
bit_clk
Valid
Frame
sdata_out
slot 1
slot 12
Time Slot “valid” bits
End of previous audio frame
0
ID1
ID0
19
0
19
0
19
0
Codec ID
slot 1
slot 2
slot 12
Figure 44. AC97 AC-link Output Frame
sync
bit_clk
codec
ready
sdata_in
slot 1
Time Slot “valid” bits
End of previous audio frame
slot 12
0
0
0
19
0
19
0
19
0
Codec ID
slot 1
slot 2
slot 12
Figure 45. Figure 44 AC97 AC-link Input Frame
Control registers are described at 5.10, Audio Registers.
SCP220x ICP Family, Rev.2.1
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Interconnect and Communication
4.7.2
Audio Port Timing
audio_fs
t22
audio_clk
audio_dr
t23
t24
audio_dx
t25
Figure 46. Audio Port Timing
Table 16. Audio Port Timing
Parameter
audio_clk frequency
Symbol
Min.
Typ.
Max.
Unit
t22
50
MHz
ns
Input data (audio_fs, audio_dr) setup time to the
rising edge of audio_clk
t23(3.0 V)
2.9
0.1
Input data (audio_fs, audio_dr) hold time from the
rising edge of audio_clk
t24(3.0 V)
t25(3.0 V)
ns
ns
Output data (audio_fs, audio_dx) delay time from
the rising edge of audio_clk
13.25
4.8
Media Storage MMC and MMCPlus blocks (compatible SD/SDHC)
The SCP220x has two MMC blocks both having identical characteristics except that MMCPlus is capable of 8-bit
parallel data path:
•
•
MMC: 1 or 4-bit data width
MMCPlus: 1 or 4 or 8-bit data width
Secure Digital and MMC are supported on both blocks; MMCPlus only on the MMCPlus block.
The Media Storage Interfaces are compatible with the SD and SDHC memory card specifications. SDHC cards are
supported up to 32 GB capacity, but only at SD card interface rates (i.e. clock is 25 MHz and not 50 MHz as SDHC
allows).
The Media Storage Interfaces have the following features:
•
•
•
•
Software programmable external clock
Support of a 48-bit command through a software accessible command buffer
Support of both a 48 or 136-bit response through a response buffer
Support of CRC generation and checking
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Interconnect and Communication
•
•
Software configurable data width of 1 (MMC mode) or 4 bits (SD/SDHC mode) [or 8 bits (MMCPlus) for the
MMCPlus block]
Incoming and outgoing datapath (implemented using FIFOs) driven by a DMA engine
The interface does not manage the media card power supply. Figure 45 shows the connectivity between the
SCP220x and an SD memory card.
SCP220x
clk
cmd
data
sd_clk
SD
sd_cmd
sd_data[3:0]
Figure 47. Media Storage Interface to SD Card
The following table lists the SCP220x pin information for the Media Storage Interfaces. Note that the MMCPlus is
only accessible from alternate functions.
Table 17. Media Storage Interfaces Pins
Pin
Type
Signal
Alternate Function
Pin Description
sd_clk
gpio[35]
gpio[34]
Bi-dir.
Bi-dir.
SD/SDHC clock or alternate function
sd_cmd
SD/SDHC serial command/response or
alternate function
sd_D[3:0]
gpio[33:30]
Bi-dir.
SD/SDHC serial data or alternate function
nand_cen_p[0]
nand_cen_p[1]
nand_data_p[7:0]
gpio[12] / mmcplus_clk
Gpio[70] / mmcplus_cmd
Bi-dir
Bi-dir
Bi-dir
Clock
Command
Data
gpio[81:74] /
mmcplus_data[7:0]
4.8.1
Media Storage Interfaces Hardware Description
The hardware implementation for the MMC and MMCPlus block are as shown in the following diagram.
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Interconnect and Communication
Media Storage Block
sys_clk domain mmc_clk / mmcp_clk domain
Clock
Generator
mmc_clk/
mmcp_clk
AHB
DMA
Registers
TX
FIFO
cmd/rsp
data
RX
FIFO
Interrupt
Generation
Interrupt
Figure 48. Media Storage MMC/MMCPlus Hardware Architecture
The hardware architecture of the MMC/MMCPlus blocks are similar to the other serial interface blocks. A register
section contains the software interface and is read and written from the AMBA bus.
The clock generator block, when enabled, divides the system clock down to create the external serial clock. To
simplify timing constraints, the clock is brought back into the block from the outgoing PAD and is used as a clock for
the front end interface block as well as the external side of the FIFOs.
The RX/TX FIFOs are asynchronous FIFOs with the internal side driven by sys_clk and the external side driven by
mmc_clk/mmcp_clk.
The front-end block is a large state machine that deals with the commands initiated in the register block and
generates the appropriate protocol on the external interface.
MMC Control registers are described at 5.11, MMC/SD Control Registers
MMCPlus Control registers are described at 5.12, MMCPlus Control Registers
4.8.2
Programming Model
This section illustrates a number of example software flow diagrams to help illustrate how the interface is used from
a software driver perspective. These flows are examples and by no means indicate that this is the only driver flow.
Depending on the physical device attached variants of the basic examples shown may very well be required.
The SD interface is based on a command and response architecture. The ASIC will issue the command written by
software into the command buffer. The media device will generate a response and this will be capture in the
response buffer for software viewing. Data is then read or written on a 4096bit block basis. Single or multiple data
blocks can be accessed. Hardware strips off the start stop, transmitter and CRC fields prior to dumping the response
or read data in the buffer space. The reverse process happens for the commands and write data blocks.
The following steps illustrate an example media card data read.
1. Initialize the interface pertinent for the media card installed. This would involve configuration of the clock rate
and configuration register.
2. Configure the datapath parameters in the data control register.
3. Issue a command by writing the appropriate command and argument to the command and argument
registers. The argument register should be written first since the act of writing to the command registers
initiates the operation on the interface.
4. If applicable, monitor for a response from the command and verify the response information.
5. Drain the fifo as it fills up. This can be done directly by reading the fifo or a dma channel can be setup to
drain the fifo.
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6. Continue the draining operation until the “sd_data_complete” interrupt occurs.
7. Check whether or not any errors have occurred.
The following steps illustrate an example media card data write:
•
Initialize the interface pertinent for the media card installed. This would involve configuration of the clock rate
and configuration register.
•
•
Configure the datapath parameters in the data control register.
Issue a command by writing the appropriate command and argument to the command and argument
registers.
•
•
•
If applicable, monitor for a response from the command and verify the response information.
Fill the fifo. This can be done directly by writing to the fifo or a dma channel can be setup to fill the fifo.
Continue the filling operation until the “sd_data_complete” interrupt occurs.
Check whether or not any errors have occurred.
4.8.3
MMC/MMCPlus Port Timing
t27
sd_clk
t28 t29
inputs
t30
outputs
Figure 49. MMC/MMCPlus Port Timing
Table 18. MMC/MMCPlus Port Timing
Parameter
Symbol
Min.
Typ.
Max.
Unit
MMC port clock frequency
MMC port input setup time
MMC port input hold time
MMC port output delay time
t27
25
MHz
ns
t28 (3.0 V)
t29 (3.0 V)
t30 (3.0 V)
2.5
5.0
ns
12.5
ns
4.9
I2C Interface
The I2C controller is a peripheral interface intended for configuring external devices such as sensors and audio
DACs. The interface consists of the following signals:
•
serial clock – This is a clock to sample an incoming serial data stream or to indicate when an outgoing serial
stream has valid data. This serial clock pin will “float” high and “drive” low much like an open collector and
requires an external pull-up resistor.
•
serial data – This is a bi-directional IO that can be driven by either the SCP220x or the peripheral being
configured. The serial data pin will “float” high and “drive” low much like an open collector and requires an
external pull-up resistor.
The SCP220x has two I2C interfaces on chip. One of these interfaces has primary functionality on dedicated I/Os.
The other I2C interface has its serial clock and serial data accessible as alternate functions via shared I/Os as shown
in the table below.
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Interconnect and Communication
Table 19. I2C Interface
Pin Direction
Alternate
Function
Signal
Pin Description
scl
gpio[36]
gpio[37]
Bi-dir.
Bi-dir.
Bi-dir.
Bi-dir.
Serial configuration clock
Serial configuration data
Serial configuration clock
Serial configuration data
sda
dip_data[17]
dip_data[16]
gpio[3] / scl_sec
gpio[4] / sda_sec
Transactions on the serial interface follow a particular protocol.
•
•
•
•
•
Transmission Start
Peripheral Slave Address
Peripheral Internal Address
Data transfer
Transmission Stop
Transmission start and stop are indicated by sequencing the serial clock and data as illustrated in the following
diagram. Transmission start occurs when serial data falls while serial clock is high and transmission stop occurs
when serial data rises while serial clock is high.
serial_clk
T
T
susto
hdsta
serial_data
T
buf
Stop
Start
Figure 50. Transmission Stop and Start Conditions
As illustrated there are a few timing parameters that must be satisfied for proper operation. Software configurable
counters are used to generate these time intervals since the system clock rate is not fixed.
There is also a software configurable delay parameter as illustrated below:
Typical Write Sequence
Tdelay
Tdelay
Tdelay
R
S1
SLAVE ID
A
ADDRESS
ADDRESS
A
A
WRITE DATA
A
S2
W
Typical Read Sequence
Tdelay
Tdelay
Tdelay
Tdelay
R
R
S1
SLAVE ID
A
S1
SLAVE ID
A
W
READ DATA
A
S2
W
S1 Start
R
Indicates whether the data transaction is a Read (“1”) or a Write (“0”)
Acknowledge
W
A
S2 Stop
Figure 51. I2C Configurable Delay
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The following diagram illustrates the address and data phases of the transaction cycle.
Typical Write Sequence
- - - -
R
- - - - -
- - - - -
2
S1
7
6
2
1
0
A
7
6
2
1
0
A
7
6
1
0
A S2
W
Phase 1
Phase 2
Phase 3
S1 Start
R
Indicates whether the data transaction is a Read (“1”) or a Write (“0”)
Acknowledge
W
A
S2 Stop
Figure 52. Serial Configuration Transaction Protocol
A basic element of a transaction is called a phase. A transaction can contain either 2-phases or 3- phases depending
on the peripheral. Usually a write transaction is a 3-phase transaction specifying the slave address, internal address
and data. A read transaction is usually a 2-phase transaction comprised of a peripheral slave address phase and a
data phase. The read transaction likely was preceded by a 2-phase write transaction that included a peripheral slave
address phase and a peripheral internal address phase.
A phase consists of sequential data transmission of 8-bits that followed by an acknowledge bit. The source of the
acknowledge bit is the recipient of the previous 8 bits of data. The external peripheral will source the acknowledge
bit for slave and internal address phases as well as write data phases. The controller sources the acknowledge for
data read phases.
The peripheral Slave address phase contains a 7 bit slave ID as well as a R/W bit. The R/W bit indicates to the
peripheral whether or not the following phases are read or write transactions. R/W=1 indicates a read transaction
and R/W=0 indicates a write transaction.
The I2C Controller supports both the master arbitration protocol as well as the Slave stall protocol.
The master arbitration protocol is utilized in systems that have multiple master controllers. The master controller
monitors the input SDA line during the SCL high period to see if the data it sent is present on the external SDA line.
The SDA line is open-collector, so if another master is driving the SDA line low the input SDA will not match the
output SDA for a master that is floating SDA high. This master is deemed to have lost arbitration and will remove
itself from the transaction. Master arbitration only occurs during the slave address phase and the write data phases
(this is when the master drives the SDA line).
The slave peripheral has a mechanism to stall any part of the I2C transaction. This is done by pulling the
SCL line low. The master monitors the SCL input to see if it is held low after the master has driven SCL
high. If it is still low, it knows that a slave is stalling the operation and the master pauses until the SCL line
floats high (i.e. the slave releases SCL when it is ready for the next part of the transaction.
4.9.1
I2C Hardware Description
The hardware implementation for the serial controller block is fairly simple and only has a few internal blocks as
shown in the following diagram.
SCP220x ICP Family, Rev.2.1
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Interconnect and Communication
2
I C Block
sys_clk domain
Interrupt
Generation
Interrupt
AHB
State
Machine
scl
Registers
De-
serializer
Serializer
sda
Figure 53. I2C Hardware Architecture
The serial controller is mostly a single state machine that gets initiated by software “kicks”. The various phases of
the transaction are initiated by a software register access. The state machine initiates the appropriate hardware
protocol at the interface as dictated by the register access.
4.9.2
Programming Model
The serial controller will be used for two very common operations. Either the controller will be used to write to a
peripheral to configure the setup of the peripheral or it may be used to read from a register within the peripheral. The
following sections provide programming guidelines for these two scenarios.
4.9.2.1
Peripheral Write – Manual Mode
The following steps suggest an algorithm for programming a peripheral configuration.
•
•
•
•
•
•
•
•
Initialize the three configuration registers.
Write the slave ID to the slave address register along with read_write=0.
Write the peripheral address to the target address register.
Write the peripheral data to the target data register.
Set the start bit in the control register.
Wait until the acknowledge interrupt occurs.
Set the stop bit in the control register.
Wait until the stop interrupt occurs.
4.9.2.2
Peripheral Write – Automatic Mode
The following steps suggest an algorithm for programming a peripheral configuration. This mode of operation is
enabled by setting the auto_mode_ena bit in the config1 register
•
•
•
•
•
•
Initialize the three configuration registers.
Write the slave ID to the slave address register along with read_write=0.
Write the peripheral address to the target address register.
Write the peripheral data to the target data register.
Set the start bit in the control register.
Wait until the stop interrupt occurs.
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4.9.2.3
Peripheral Read – Manual Mode
The following steps suggest an algorithm for programming a peripheral configuration.
•
•
•
•
•
•
•
•
•
•
•
Initialize the three configuration registers.
Write the slave ID to the slave address register along with read_write=0.
Write the peripheral address to the target address register.
Set the start bit in the control register.
Wait until the acknowledge interrupt occurs.
Write the slave ID to the slave address register along with read_write=1.
Set the start bit in the control register.
Wait until the acknowledge interrupt occurs.
Set the stop bit in the control register.
Wait until the stop interrupt occurs.
Read the configuration data from the slave data register.
4.9.2.4
Peripheral Read – Auto Mode
The following steps suggest an algorithm for programming a peripheral configuration. This mode of operation is
enabled by setting the auto_mode_ena bit in the config1 register
•
•
•
•
•
•
Initialize the three configuration registers.
Write the slave ID to the slave address register along with read_write=1.
Write the peripheral address to the target address register.
Set the start bit in the control register.
Wait until the stop interrupt occurs.
Read the configuration data from the slave data register.
I2C Control registers are described at 5.13, I2C Registers.
4.9.3
I2C Port Timing
t34
scl
sda (in)
t35 t36
t37
sda (out)
Figure 54. I2C Port Timing
Table 20. I2C Port Timing
Parameter
Symbol
Min.
Typ.
Max.
Unit
I2C port clock frequency (fSCL
)
t34
t35
t36
400
kHz
ns
I2C port input setup time (tSU;DAT
I2C port input hold time (tHD;DAT
)
1001
0
)
ns
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Interconnect and Communication
Table 20. I2C Port Timing
I2C port output delay time (tVD;DAT
)
t37
9001
ns
1
The I2C Controller design transitions signals at ¼ period intervals of the scl_clk, additionally the I/O pads are designed for
operating at >100 Mhz switching frequency, ensuring that the timing specifications of the I2C specification (NXP
Semiconductors Document UM10204, I2C-bus specification and user manual, Rev 5 – 9 October 2012) are met.
Example: fSCL = 400 kHZ , scl_clk period = 2500ns;
t35 = ¼ scl_clk period = 625ns ;
t37 = ¼ scl_clk period = 625ns
4.10 Pulse Width Modulated Outputs
Two pulse width modulated (PWM) outputs are available as alternate pin functions. As shown in the following table
Table 21. PWM Function Pinout
Signal
Alternate Function
Pin Direction
Pin Description
audio_fsr
gpio[18] or pwm2
Bi-dir.
Audio receive frame clock, GPIO or PWM
signal as alternate function;
sc_fcb
gpio[57] or pwm1
Bi-dir.
Smart card, GPIO or PWM signal as alternate
function;
4.10.1 PWM Hardware Description
The Pulse Width Modulation block allows for generating digital signal with variable pulse width with the following
features:
•
Control of working frequency from system clock (sys_clk) to system clock divided by 4096 (8- bit divider
followed by 1, 1/2, 1/4, 1/8 or 1/16)
•
•
•
•
Control of period and pulse width through 16-bit registers (from 1 to 65536)
One shot or free running with posted value updates
Out signal inverter
Out signal dead-zone generator through 8-bit register
The following diagram illustrates the architecture of the Pulse Width Modulation (PWM).
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Interconnect and Communication
PWM Block
t0_com_buffer
t0_count_buffer
t0_update
sys_clk
prescaler + 1
t0_start
/n
t0_auto_reload
/1
/2
t0 _clk_sel
t0 _inverter
dead_zone_en
Control
Logic 0
tout0
/4
Dead-zone
/8
dead_zone_length
t1 _inverter
/16
t1 _clk_sel
Control
Logic 1
tout1
t1_com_buffer
t1_count_buffer
t1_update
Legend:
Signal
t1_start
t1_auto_reload
Register
Figure 55. PWM Hardware Architecture
The Tout0 frequency is determined by the following formula:
For Tout1, just replace the t0 by t1.
PWM Control registers are described at 5.14, PWM Registers.
4.10.2 PWM Programming Notes
4.10.2.1 Example
The following section provides some details on appropriate programming of the PWM using an example. The
following diagram illustrates a timeline for a particular PWM configuration.
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Interconnect and Communication
start bit =1
timer started
count=com
auto-reload
count=com
timer is stopped
com_buffer
1
0
count_buffer
3
3
2
1
0
2
1
0
0
auto reload=0
count=3
cmp=1
count=2
cmp=0
manual update = 1 manual update = 0
interrupt request interrupt request
auto reload = 1
auto reload = 1
TOUTn
1
2
3
4
TOUTn
30
30
20
40
10
50
60
60
60
5
6
Interrupt
The following events refer to the numbering in the above diagram
1. count=60, cmp=30, update=1, auto_reload=1, update=0. The update must be toggled from “1” to “0”. The
value of the next count and cmp can be set at step 3. In the case where these values have been set prior to
step 1, the update should be disabled. If the next value is set in the enable state, this next value goes into
the first value of count and cmp at the “start”.
2. start=1.
3. cmp=20. This can be set as soon as the start was issued in step 2. In the case where auto_reload is
enabled, the count is updated when the interrupt occurs so count and cmp must be set prior to the interrupt
event. If the cmp value is enough until the next reflection, it can be set after the interrupt.
4. cmp=10.
5. auto_reload=0.
6. start=0.
4.10.2.2 PWM as general timer
Another use of the PWM is as a general timer. For this scenario, the cmp value is deducted from the PWM timer.
The rest of the settings are identical to the PWM usage. For example to get an interrupt every 10msec (100hz) for
a 24 Mhz clock source, the following settings are required.
•
•
•
24 Mhz / 100hz = 240,000
240,000 = (prescaler + 1) x (1/Tn_clk_sel) x (count + 1)
Prescaler=99, 1/Tn_clk_sel=16, count=149
4.10.2.3 PWM dead zones
Another PWM usage is to have dead zones. A dead-zone delays the low to high transition point. The following
diagram illustrates the concept.
SCP220x ICP Family, Rev.2.1
52
Freescale Semiconductor
Interconnect and Communication
TOUT0
TOUT0_DZ
4.11 KeyPad Scan Interface
The SCP220x has an optional keyscan capability. The keyscan processor has four output scan ports and four input
scan ports to allow recognition of up to 16 keys.
The Keyscan Interface provides the following features:
•
•
•
•
•
Programmable key scan and sense polarity
Programmable scan time
Programmable scan matrix
Auto clearing of the sense value after it has been read
Supports typing mode and gaming mode
Figure 54 shows the keyscan system implementation.
scanout1
scanout2
scanout3
scanout4
pull-up
sensein1
sensein2
sensein3
sensein4
scanout1
scanout2
scanout3
Tscan Tscan Tscan
sense value catch
Figure 56. Keyscan Interface
Table 22 lists the SCP220x pin information for the Keyscan Interface. To enable the keyscan interface, the Alternate
Function register must be programmed accordingly.
Table 22. Keyscan Interface
Signal
Keyscan Function
Pin Direction
Pin Description
reserved_14
gpio[45] or keyscan_out3
Bi-dir.
GPIO or alternate function
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
53
Interconnect and Communication
Table 22. Keyscan Interface
reserved_13
reserved_12
reserved_11
reserved_10
reserved_9
reserved_8
reserved_7
gpio[44] or keyscan_out2
gpio[43] or keyscan_out1
Bi-dir.
GPIO or alternate function
GPIO or alternate function
GPIO or alternate function
GPIO or alternate function
GPIO or alternate function
GPIO or alternate function
GPIO or alternate function
Bi-dir.
Bi-dir.
Bi-dir.
Bi-dir.
Bi-dir.
Bi-dir.
gpio[42] or keyscan_out0
gpio[41] or keyscan_in3
gpio[40] or keyscan_in2
gpio[39] or keyscan_in1
gpio[38] or keyscan_in0
Keyscan control registers are described at 5.15, KeyScan Registers.
4.12 GPIOs and Alternate Functions
A number of external pins have additional GPIO functionality and possibly an alternate function as shown in GPIO
and Alternate Function List.
The “gpio enable” register controls whether the pin functions as a GPIO. For the pins that have also an alternate
function, the “alternate function enable” register selects the alternate function if the GPIO enable bit for that pin is
disabled.
NOTE
External pins labeled ‘reserved_#’ should only be used as GPIOs or as the
alternate function as the primary functionality is reserved and not intended for use
during normal operation. The SDK generates a firmware that handles the pin
function already.
The primary function, GPIO, alternate function is listed in 4.12.1, GPIO and Alternate Function List below.
The pinout is listed in Table 88 (SCP220x Pinout)
The GPIO control registers are described at 5.16, GPIO Registers
The PAD and I/O control registers are described at 5.3, PAD and I/O registers
The GPIO enable bits are listed in ,
The Alternate function enable bits are listed in Table 40., Alternate Function Enable Register
The PAD strength enable bits are listed in Table ,
The PAD Types are described below 4.12.2, PAD Type description
4.12.1 GPIO and Alternate Function List
Table 23. GPIOs and Alternate Functions Shared with External Pins
GPIO
PIN - MAIN
ALTERNATE
POWER
PAD TYPE
PAD Resistor/Default
-
-
-
-
dip_rs_p
dip_wen_p
spi1_sck_p
spi1_rxd_p
dip_hsync
dip_vsync
mp2ts1_clk
mp2ts1_d
LVDD
LVDD
JVDD
JVDD
B
B
A
A
PD/none
PD/none
PD/none
PD/none
SCP220x ICP Family, Rev.2.1
54
Freescale Semiconductor
Interconnect and Communication
Table 23. GPIOs and Alternate Functions Shared with External Pins
-
spi1_ssn_p
spi1_txd_p
mp2ts1_sync
mp2ts1_valid
sdram_clk_fb
JVDD
JVDD
C
A
B
A
B
A
B
B
B
A
A
A
A
A
A
C
A
A
B
A
A
A
A
A
A
A
A
D
D
A
A
C
PU/PU
PD/none
-
-
-
sdram_clkn_p
Reserved_1
sif_clkout_p
Reserved_2
dip_data_p[17]
dip_data_p[16]
dip_pclk_p
RVDD
MVDD
SVDD
MVDD
LVDD
gpio00
gpio01
gpio02
gpio03
gpio04
gpio05
gpio06
gpio07
gpio08
gpio09
gpio10
gpio11
gpio12
gpio13
gpio14
gpio15
gpio16
gpio17
gpio18
gpio19
gpio20
gpio21
gpio22
gpio23
gpio24
gpio25
gpio26
gpio27
gpio28
PD/none
PD/none
PD/PD
scl_sec
PD/none
PD/none
PD/none
PD/none
PD/none
PD/none
PD/none
PD/none
PD/none
PU/PU
sda_sec
LVDD
LVDD
Reserved_3
Reserved_4
Reserved_5
Reserved_6
nand_ale_p
nand_cle_p
nand_cen_p[0]
nand_wen_p
nand_ren_p
dip_oen_p
pwi_clk
MVDD
MVDD
MVDD
MVDD
NVDD
NVDD
NVDD
NVDD
NVDD
LVDD
pwi_data
mmcplus_clk
dip_blank
PD/none
PD/none
PD/none
PD/none
PD/none
PD/none
PD/none
PD/none
PD/none
PD/none
PD/none
PU/PU
audio_clkr_p
audio_dr_p
audio_fsr_p
audio_clkx_p
audio_dx_p
audio_fsx_p
uart_txd_p
AUVDD
AUVDD
AUVDD
AUVDD
AUVDD
AUVDD
JVDD
pwm2_out
uart_rxd_p
JVDD
dip_csn2_p
dip_csn3_p
spi_txd_p
LVDD
LVDD
PU/PU
JVDD
PD/none
PD/none
PU/PU
spi_rxd_p
JVDD
spi_ssn_p
JVDD
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
55
Interconnect and Communication
Table 23. GPIOs and Alternate Functions Shared with External Pins
gpio29
gpio30
gpio31
gpio32
gpio33
gpio34
gpio35
gpio36
gpio37
gpio38
gpio39
gpio40
gpio41
gpio42
gpio43
gpio44
gpio45
gpio46
gpio47
gpio48
gpio49
gpio50
gpio51
gpio52
gpio53
gpio54
gpio55
gpio56
gpio57
gpio58
gpio59
gpio60
spi_sck_p
mmc_data_p[0]
mmc_data_p[1]
mmc_data_p[2]
mmc_data_p[3]
mmc_cmd_p
mmc_clk_p
JVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SVDD
A
B
B
B
B
B
D
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
D
B
B
B
B
B
PD/none
PD/none
PD/none
PD/none
PD/none
PD/none
PU/PU
scl_p
PD/none
PD/none
PD/none
PD/none
PD/none
PD/none
PD/none
PD/none
PD/none
PD/none
PD/none
PD/none
PD/none
PD/none
PD/none
PD/none
PD/none
PD/none
PD/none
PU/PU
sda_p
SVDD
Reserved_7
Reserved_8
Reserved_9
Reserved_10
Reserved_11
Reserved_12
Reserved_13
Reserved_14
dip_data_p[18]
dip_data_p[19]
dip_data_p[20]
dip_data_p[21]
dip_data_p[22]
dip_data_p[23]
fodd_p
keyscan_in0
keyscan_in1
keyscan_in2
keyscan_in3
keyscan_out0
keyscan_out1
keyscan_out2
keyscan_out3
MVDD
MVDD
MVDD
MVDD
MVDD
MVDD
MVDD
MVDD
LVDD
LVDD
LVDD
LVDD
uart1_rxd
uart1_txd
LVDD
LVDD
SVDD
sif_gpio_p
SVDD
dip_cpu_vsync_p
sc_clk_p
LVDD
SMVDD
SMVDD
SMVDD
SMVDD
SMVDD
SMVDD
sc_rst_p
PD/none
PD/none
PD/none
PD/none
PD/none
sc_fcb_p
pwm1_out
sc_io_p
sc_card_detect_p
sc_power_on_p
SCP220x ICP Family, Rev.2.1
56
Freescale Semiconductor
Interconnect and Communication
Table 23. GPIOs and Alternate Functions Shared with External Pins
gpio61
gpio62
gpio63
gpio64
gpio65
gpio66
gpio67
gpio68
gpio69
gpio70
gpio71
gpio72
gpio73
gpio74
gpio75
gpio76
gpio77
gpio78
gpio79
gpio80
gpio81
gpio82
gpio83
gpio84
gpio85
gpio86
gpio87
gpio88
gpio89
gpio90
gpio91
gpio92
sc_card_voltage_p
-
spi_rxd3
SMVDD
-
B
-
PD/none
-/-
-
-
-
-/-
-
-
-
-/-
-
-
-
-/-
-
-
-
-/-
-
-
-
-/-
-
-
-
-/-
-
-
-
-/-
nand_cen_p[1]
nand_cen_p[2]
nand_cen_p[3]
utmiotg_drvvbus_p
nand_data_p[0]
nand_data_p[1]
nand_data_p[2]
nand_data_p[3]
nand_data_p[4]
nand_data_p[5]
nand_data_p[6]
nand_data_p[7]
uart_cts_p
uart_rts_p
Reserved_15
sdram_rdy_p
dip_csn0_p
dip_csn1_p
mp2ts_d_p
mp2ts_clk_p
mp2ts_valid_p
mp2ts_sync_p
-
mmcplus_cmd
spi_rxd1
NVDD
NVDD
NVDD
AUVDD
NVDD
NVDD
NVDD
NVDD
NVDD
NVDD
NVDD
NVDD
JVDD
JVDD
MVDD
RVDD
LVDD
LVDD
JVDD
JVDD
JVDD
JVDD
-
C
C
C
D
A
A
A
A
A
A
A
A
A
A
A
B
D
D
A
-
PU/PU
PU/PU
PU/PU
PU/PU
PD/none
PD/none
PD/none
PD/none
PD/none
PD/none
PD/none
PD/none
PD/none
PD/none
PD/none
PD/none
PU/PU
PU/PU
PD/n.a.
PD/n.a.
PD/n.a.
PD/n.a.
-/-
spi_rxd2
mmcplus_data[0]
mmcplus_data[1]
mmcplus_data[2]
mmcplus_data[3]
mmcplus_data[4]
mmcplus_data[5]
mmcplus_data[6]
mmcplus_data[7]
spi_ssn1
spi_ssn2
spi_ssn3
A
A
-
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
57
Interconnect and Communication
Table 23. GPIOs and Alternate Functions Shared with External Pins
gpio93
gpio94
gpio95
-
-
-
-
-
-
-
-
-
-/-
-/-
-/-
4.12.2 PAD Type description
There are four types of hardware PAD for the GPIOs: A, B, C, D. The correspondence with the pin is listed in the
table above.
Following are each GPIO PAD type specifications at 50% transition and the corresponding measurement illustration
diagram.
4.12.2.1 GPIO pad type A specifications
Table 24. GPIO PAD type A specifications
Pad Type
Drive Strength
Parameter
Load (pF)
Min
Typ
Max
Unit
A
Low-drive
tpLH
10
25
2
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
200
10
10
18
2
19
35
5
tpHL
tpLH
tpHL
25
4
8
100
200
10
11
20
1
23
42
3
High-drive
25
2
4
100
200
10
5
10
16
3
8
1
25
2
5
100
200
6
12
22
11
SCP220x ICP Family, Rev.2.1
58
Freescale Semiconductor
Interconnect and Communication
4.12.2.2
GPIO PAD type B specifications
Table 25. GPIO PAD type B specifications
Pad Type
Drive Strength
Parameter
Load (pF)
Min
Typ
Max
Unit
B
Low-drive
tpLH
10
25
2
3
5
9
2
3
6
11
2
2
4
7
2
2
5
8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
200
10
11
18
5
tpHL
tpLH
tpHL
25
6
100
200
10
14
24
4
High-drive
25
5
100
200
10
8
13
4
25
5
100
200
10
16
4.12.2.3 GPIO PAD type C specifications
Table 26. GPIO pad type C specificatiopns
Pad Type
Drive Strength
Parameter
Load (pF)
Min
Typ
Max
Unit
C
Low-drive
tpLH
10
25
2
3
-
-
-
-
-
-
-
-
-
5
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
200
10
10
18
2
19
35
5
tpHL
25
4
8
100
200
10
11
20
1
23
42
3
High-drive
tpLH
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
59
Interconnect and Communication
Table 26. GPIO pad type C specificatiopns
25
2
5
-
-
-
-
-
-
-
4
10
16
3
ns
ns
ns
ns
ns
ns
ns
100
200
8
tpHL
10
25
1
2
5
100
200
6
12
22
11
4.12.2.4 GPIO PAD type D specifications
Table 27. GPIO pad type D specificatiopns
Pad Type
Drive Strength
Parameter
Load (pF)
Min
Typ
Max
Unit
D
Low-drive
tpLH
10
25
2
3
5
9
2
3
6
11
2
2
4
7
2
2
5
8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
200
10
11
18
5
tpHL
tpLH
tpHL
25
6
100
200
10
14
24
4
High-drive
25
5
100
200
10
8
13
4
25
5
100
200
10
16
SCP220x ICP Family, Rev.2.1
60
Freescale Semiconductor
Registers
4.12.2.5
GPIO PAD Propagation Schematic
V
/2
DD
tpLH
tpHL
Pad Output
V
/2
DD
Propagation delays Low to High and High to Low
Figure 57. GPIO PAD Propagation Schematic
4.13 Production Test and System Signals
The following table lists the SCP220x pin information for system and test signals.
Table 28. Production Test and System Singlas
Pad
Resistor
Pin
Direction
Signal
Pin Description
Clkin
-
-
Input
Clock input to SCP220x from crystal, oscillator or
baseband processor
Clkout
Output
Output for crystal connection or ground if Clkin is
driven by oscillator
resetN
hw_deep_secure
bootmode
-
-
-
Input
Input
Input
Chip reset
set to ‘0’, reserved
Selects how the part will startup after reset. Must
be set to ‘1’.
testmode
tck
PD
PU
-
Input
Input
Enable testmode (manufacture test only)
JTAG test clock
rtck
Output
Input
JTAG return clock
tdi
PU
-
JTAG test data input
JTAG test data output
JTAG test reset
tdo
Output
Input
Ntrst
tms
PD
PU
Input
JTAG test mode
5
Registers
In general, an application should use the SDK to use the blocks available on the chips. Most of the low level inter-
facing that requires register access is already available ready to use.
In case it is required to act directly on the registers here is the list of the main register groups. It is recommended to
use macro functions in the SDK to modify the values of the registers and in most cases the access is done through
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
61
Registers
the register/bit name rather than directly with the register value.
When writing boot loader code however it is necessary to access the register directly.
5.1
Memory Map
The following table describes the address map.
Table 29. Memory Map
Start Address
End Address
Peripheral
ARM1 HSEL
0x0000_0000
0x0000_0000
0x2000_0000
0x3000_0000
0x4000_0000
0x4400_0000
0x4800_0000
0x5000_0000
0x5400_0000
0x5800_0000
0x5c00_0000
0x6000_0000
0x0000_003f
0x1fff_ffff
0x2fff_ffff
0x3fff_ffff
0x43ff_ffff
0x47ff_ffff
0x4fff_ffff
0x53ff_ffff
0x57ff_ffff
0x5Bff_ffff
0x5fff_ffff
0x67ff_ffff
Reserved
External Memory
Section 5.6, Memory Controller
Reserved
Reserved
21
21
Reserved
DIP Port
4
BitBlt
23
24
BitBlt_mini
USB OTG
5
Reserved
Reserved
Reserved
Reserved
7
Reserved
Reserved
Section 5.7, NAND Interface
Registers Description
0x6800_0000
0x6c00_0000
0x6Bff_ffff
0x6fff_ffff
Section 5.11, MMC/SD Control
Registers
8
Section 5.12, MMCPlus Control
Registers
28
0x7000_0000
0x7400_0000
0x7800_0000
0x8000_0000
0x8800_0000
0x9000_0000
0x9400_0000
0x9800_0000
0xA000_0000
0xA400_0000
0xA800_0000
0x73ff_ffff
0x77ff_ffff
0x7fff_ffff
0x87fff_ffff
0x8fff_ffff
0x9fff_ffff
0x97ff_ffff
0x9fff_ffff
0xA3ff_ffff
0xA7ff_ffff
0xAfff_ffff
Multi-channel DMA
SPI1
9
30
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
14
Reserved
Reserved
Reserved
Reserved
Reserved
Section 5.9, SPI Registers
Reserved
Reserved
Reserved
Reserved
SCP220x ICP Family, Rev.2.1
62
Freescale Semiconductor
Registers
Table 29. Memory Map
0xBfff_ffff
0xB000_0000
0xC000_0000
0xC400_0000
0xc800_0000
0xcc00_0000
0xd000_0000
0xe000_0000
0xf000_0000
0xffff_f000
Sensor Interface
Reserved
Reserved
Reserved
Reserved
APB bridge
Reserved
Reserved
Reserved
16
0xC3ff_ffff
0xC7ff_ffff
0xcbff_ffff
0xcfff_ffff
0xdfff_ffff
0xefff_ffff
0xffff_efff
0xffff_ffff
Reserved
Reserved
Reserved
Reserved
19
Reserved
Reserved
Reserved
The following table decribes the memory mapping through the APB bridge containing most of the peripherals
interfaces.
Table 30. Sub-peripherals Memory Map
Start Address
End Address
Sub-peripherals
0xd000_0000
0xd001_0000
0xd002_0000
0xd003_0000
0xd004_0000
0xd005_0000
0xd006_0000
0xd007_0000
0xd008_0000
0xd009_0000
0xd00a_0000
0xd00b_0000
0xd00c_0000
0xd00d_0000
0xd00e_0000
0xd00f_0000
0xd000_ffff
0xd001_ffff
0xd002_ffff
0xd003_ffff
0xd004_ffff
0xd005_ffff
0xd006_ffff
0xd007_ffff
0xd008_ffff
0xd009_ffff
0xd00a_ffff
0xd00b_ffff
0xd00c_ffff
0xd00d_ffff
0xd00e_ffff
0xd00f_ffff
Section 5.10, Audio Registers
Section 5.8, UART Control Registers
Section 5.15, KeyScan Registers
System Registers
Section 5.13, I2C Registers
OS Timer 1
OS Timer 2
OS Timer 3
RTC Timer
Section 5.14, PWM Registers
Section 5.16, GPIO Registers
Smart Card
Reserved
OS Timer 4
Uart2
Reserved
The system register map is summarized below and described in the following sections.
System registers are located from address: 0xd003_0000.
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
63
Registers
Table 31. System Registers
Register
Address Offset
Mode
Section 5.2.1, System Clock Configuration Register
Section 5.2.2, AP Clock Configuration Register
Section 5.2.3, Clock Update Register
Section 5.4.3, System Reset Register
Section 5.4.1, System Power Down
Section 5.5.1, Chip ID Register
Section 5.3.1, Alternate Function Enable Register
Section 5.3.2, Drive Strength Register
Drive strength2
0x00
0x04
0x08
0x18
0x1c
RW
RW
RW
RW
RW
RO
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0x28
0x30
0x80
0x84
0x88
0x8C
0x90
0x94
0x98
0xCC
0xd0
0xF8
0xFC
0x100
0x104
0x108
0x10C
0x110
0x114
Drive strength3
Section 5.3.3, PAD Resistor Enable
PAD resistor enable2
PAD resistor enable3
PAD resistor enable4
Section 5.4.2, System power down1
Section 5.4.4, System Reset1 Register
Section 5.2.7, Interface PLL Select Register
IF PLL divide
XGA PLL divide
SIF PLL divide
MEM PLL divide
AP PLL divide
USB PLL divide
TVOUT PLL divide
5.2
Clock Configuration Registers
If necessary, it is possible to change the clocks configuration, exercise caution doing so especially when modifying
the system clocks. It is recommended in any case to change clocks configuration via the SDK.
Here is the list of registers, please refer to 3.3, Clock Configuration for details:
•
•
•
System Clock Configuration Register
AP Clock Configuration Register
Clock Update Register
SCP220x ICP Family, Rev.2.1
64
Freescale Semiconductor
Registers
•
•
•
•
•
Interface Clock Configuration Register
DIP Clock Configuration Register
Memory Clock Configuration Register
Interface PLL Select Register
PLL Divide Register
5.2.1
System Clock Configuration Register
Table 32. System Clock Configuration Register
System Clock Configuration
Address: 0x00
Reset = 0xcc0_0000
Function
Type: RW
Name
Bit
Reset
arm2_clk_en_div
31-30
Both ARMs have a clock enable that effectively tells the ARM926EJ-S
processor the frequency of the system bus. The primary ARM926EJ-S
processor is able to get the appropriate divide value from the sys_clk_div
field but the secondary ARM926EJ-S processor needs a separate field to
define this value since it can operate at a different frequency than the
primary ARM926EJ-S processor . This field is similar to the sys_clk_div
field and must be programmed based on the difference between the ARM2
clock and the system clock frequencies. Note: this field does not set the
frequency of the system clock.
0
11 : sys_clk = arm2_clk/4
10 : sys_clk = arm2_clk/3
01 : sys_clk = arm2_clk/2
00 : sys_clk = arm2_clk
tcm_clk_sel
29
The primary ARM926EJ-S processor TCM can be used as either TCM
memory or system memory (connected to the bus). The clocking source
and physical interface change for each application. This bit selects the
application. The sys_clk_config makes the switch over occur.
0 = system memory
1 = tcm memory
arm_clk2_div
28-26
This divide value is applied to the PLL output clock to generate the
secondary ARM926EJ-S processor clock.
0,7 : arm_clk = FPLLOUT /12
3
6 : arm_clk = FPLLOUT /10
5 : arm_clk = FPLLOUT /8
4 : arm_clk = FPLLOUT /6
3 : arm_clk = FPLLOUT /4
2 : arm_clk = FPLLOUT /3
1 : arm_clk = FPLLOUT /2
pll_sel
25
This field selects the PLL source for the system clock generation.
0
0 = sys pll
1 = ap pll
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
65
Registers
Table 32. System Clock Configuration Register
arm_clk_div
24-22
This divide value is applied to the PLL output clock to generate the primary
ARM926EJ-S processor clock.
0,7 : arm_clk = FPLLOUT /12
3
6 : arm_clk = FPLLOUT /10
5 : arm_clk = FPLLOUT /8
4 : arm_clk = FPLLOUT /6
3 : arm_clk = FPLLOUT /4
2 : arm_clk = FPLLOUT /3
1 : arm_clk = FPLLOUT /2
sys_clk_div
21-20
This divide value is applied to the ARM926EJ-S processor clock to
generate the system clock. The system clock runs all internal logic except
the ARM926EJ-S processor and array processor.
11 : sys_clk = arm_clk/4
0
10 : sys_clk = arm_clk/3
01 : sys_clk = arm_clk/2
00 : sys_clk = arm_clk
19
Range
18-16
This field must be set according the configured post reference divide
frequency.
0
0=bypass, 1=10-16 Mhz, 2=16-26 Mhz, 3=26-42 Mhz, 4=42-65 Mhz,
5=65-104 Mhz, 6=104-166 Mhz, 7=166 Mhz+
NO
NR
15-13
12-8
PLL Output Divider value.
0
0
PLL Input Divider value. Power-up default of this field is controlled by
configuration settings on the EBI address bus.
NF
7-0
PLL Feedback divider value.
0
5.2.2
AP Clock Configuration Register
Table 33. AP Clock Configuration Register
AP Clock Configuration
Address: 0x04
Reset = 0x2000_0000
Function
Type: RW
Name
Bit
Reset
SCP220x ICP Family, Rev.2.1
66
Freescale Semiconductor
Registers
Table 33. AP Clock Configuration Register
mem_clk_div
31-29
This divide value is applied to the PLL output clock to generate the
memory 2x clock. The “sys_clk_config” kicker applies the divide value.
This is only pertinent if the power-up config of the memory clock source is
the “sync” mode, otherwise the divide value defaults to /2 of the memory
PLL. An additional /2 is also applied so that both a clk and clk_2x are
generated. The clk frequency (not the clk_2x) must match the system
clock frequency.
1
0,7 : arm_clk = FPLLOUT /12
6 : arm_clk = FPLLOUT /10
5 : arm_clk = FPLLOUT /8
4 : arm_clk = FPLLOUT /6
3 : arm_clk = FPLLOUT /4
2 : arm_clk = FPLLOUT /3
1 : arm_clk = FPLLOUT /2
28-23
22
ap_clock_disable
Range
1 = The AP PLL is powered down and put in bypass mode
0 = The AP PLL is enabled
0
0
21-19
18-16
This field must be set according the configured post reference divide
frequency.
0=bypass, 1=10-16 Mhz, 2=16-26 Mhz, 3=26-42 Mhz, 4=42-65 Mhz,
5=65-104 Mhz, 6=104-166 Mhz, 7=166 Mhz+
NO
NR
15-13
12-8
PLL Output Divider value.
0
0
PLL Input Divider value. Power-up default of this field is controlled by
configuration settings on the EBI address bus.
NF
7-0
PLL Feedback divider value.
0
5.2.3
Clock Update Register
Table 34. Clock Update Register
Clock Update
Address: 0x08
Reset = 0x30
Type: RW
Name
Bit
Function
Reset
31-7
6
sys_pll_select_cfg
ap_pll_lock_status
When a ’1’ is written to this bit, the PLL selection is applied to the system
PLL. This bit is self clearing after the pll selection has been applied. When
switching to a new PLL source, the new PLL must already be properly
configured and locked.
0x0
5
This bit is a read only bit and reflects the "locking" status of the AP PLL. 0
= no lock, 1 = lock.
0x1
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
67
Registers
Table 34. Clock Update Register
sys_pll_lock_status
4
This bit is a read only bit and reflects the "locking" status of the system PLL.
0 = no lock, 1 = lock.
0x1
0x0
3
2
sys_clk_config
ap_pll_config
sys_pll_config
When a ’1’ is written to this bit, the clock divide settings for the system,
ARM926EJ-S processor and mem_clk_div are applied as well as the
tcm_clk_sel setting. This bit is self clearing after the clock divide has been
applied
1
0
When a ’1’ is written to this bit, the AP PLL configuration process is initiated
and the AP PLL is re-configured with the divider values programmed into
the AP Clock configuration register. This bit is self clearing after the AP PLL
has locked.
0x0
0x0
When a ’1’ is written to this bit, the system PLL configuration process is
initiated and the system PLL is re-configured with the divider values
programmed into the system Clock configuration register. This bit is self
clearing after the system PLL has locked.
5.2.4
Interface Clock Configuration Register
Table 35. Interface Clock Configuration Register
Interface Clock Configuration
Address: 0x3C
Name
Reserved
Reset = 0x10_0000
Function
Type: RW
Bit
Reset
31-21
20
Reserved
pll_lock_status
clock_disable
Range
This bit is a read only bit and reflects the “locking” status of the PLL. 0 =
no lock, 1 = lock.
0
0
0
19
1 = The PLL is powered down and put in bypass mode
0 = The PLL is enabled
18-16
This field must be set according the configured post reference divide
frequency.
0=bypass, 1=10-16 Mhz, 2=16-26 Mhz, 3=26-42 Mhz, 4=42-65 Mhz,
5=65-104 Mhz, 6=104-166 Mhz, 7=166 Mhz+
NO
NR
NF
15-13
12-8
7-0
PLL Output Divider value.
PLL Input Divider value.
PLL Feedback divider value.
0
0
0
SCP220x ICP Family, Rev.2.1
68
Freescale Semiconductor
Registers
5.2.5
DIP Clock Configuration Register
Table 36. DIP Clock Configuration Register
DIP Clock Configuration
Address: 0x38
Name
Reserved
Reset = 0xa8147
Function
Type: RW
Bit
Reset
31-22
20
Reserved
pll_lock_status
clock_disable
Range
This bit is a read only bit and reflects the “locking” status of the PLL. 0 =
no lock, 1 = lock.
0
1
19
1 = The PLL is powered down and put in bypass mode
0 = The PLL is enabled
18-16
This field must be set according the configured post reference divide
frequency.
d2
0=bypass, 1=10-16 Mhz, 2=16-26 Mhz, 3=26-42 Mhz, 4=42-65 Mhz,
5=65-104 Mhz, 6=104-166 Mhz, 7=166 Mhz+
NO
NR
NF
15-13
12-8
7-0
PLL Output Divider value.
PLL Input Divider value.
PLL Feedback divider value.
d4
d1
d71
5.2.6
Memory Clock Configuration Register
Table 37. Memory Clock Configuration Register
Memory Clock Configuration
Address: 0x4C
Name
Reset = 0x10_0000
Function
Type: RW
Bit
Reset
31-22
21
ddr_dll_disable
Some applications may not require the DDR DLLs. This bit will put the
DLLs in the powered down state.
0
1 = The DLLs are powered down
0 = The DLLs are enabled
pll_lock_status
clock_disable
Range
20
19
This bit is a read only bit and reflects the “locking” status of the PLL. 0 =
no lock, 1 = lock.
1
0
0
1 = The PLL is powered down and put in bypass mode
0 = The PLL is enabled
18-16
This field must be set according the configured post reference divide
frequency.
0=bypass, 1=10-16 Mhz, 2=16-26 Mhz, 3=26-42 Mhz, 4=42-65 Mhz,
5=65-104 Mhz, 6=104-166 Mhz, 7=166 Mhz+
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
69
Registers
Table 37. Memory Clock Configuration Register
NO
NR
NF
15-13
PLL Output Divider value.
PLL Input Divider value.
PLL Feedback divider value.
0
0
0
12-8
7-0
5.2.7
Interface PLL Select Register
Table 38. Interface PLL Select Register
Interface PLL Select
Address: 0xF8
Reset = 0x1800
Type: RW
Name
Bit
Function
Reset
31-28
27
tvout_clk_gate
This field controls the clock gating cell between the PLL clock source and the
clock divide circuitry. If the PLL or ref_clk_sel is being updated, the clock
gating cell must be activated first.
0x0
0 = normal operation. Clock output is not gated.
1 = Clock output is gated.
usb_clk_gate
ap_clk_gate
mem_clk_gate
sif_clk_gate
26
25
24
23
22
This field controls the clock gating cell between the PLL clock source and the
clock divide circuitry. If the PLL or ref_clk_sel is being updated, the clock
gating cell must be activated first.
0 = normal operation. Clock output is not gated.
1 = Clock output is gated.
0x0
0x0
0x0
0x0
0x0
This field controls the clock gating cell between the PLL clock source and the
clock divide circuitry. If the PLL or ref_clk_sel is being updated, the clock
gating cell must be activated first.
0 = normal operation. Clock output is not gated.
1 = Clock output is gated.
This field controls the clock gating cell between the PLL clock source and the
clock divide circuitry. If the PLL or ref_clk_sel is being updated, the clock
gating cell must be activated first.
0 = normal operation. Clock output is not gated.
1 = Clock output is gated.
This field controls the clock gating cell between the PLL clock source and the
clock divide circuitry. If the PLL or ref_clk_sel is being updated, the clock
gating cell must be activated first.
0 = normal operation. Clock output is not gated.
1 = Clock output is gated.
xga_clk_gate
This field controls the clock gating cell between the PLL clock source and the
clock divide circuitry. If the PLL or ref_clk_sel is being updated, the clock
gating cell must be activated first.
0 = normal operation. Clock output is not gated.
1 = Clock output is gated.
SCP220x ICP Family, Rev.2.1
70
Freescale Semiconductor
Registers
Table 38. Interface PLL Select Register
if_clk_gate
21
This field controls the clock gating cell between the PLL clock source and the
clock divide circuitry. If the PLL or ref_clk_sel is being updated, the clock
gating cell must be activated first.
0x0
0 = normal operation. Clock output is not gated.
1 = Clock output is gated.
tvout_ref_clk_sel
usb_ref_clk_sel
ap_ref_clk_sel
mem_ref_clk_sel
sif_ref_clk_sel
xga_ref_clk_sel
if_ref_clk_sel
20-18
17-15
14-12
11-9
8-6
This field selects the PLL clock source.
0 = IF PLL, 1 = AP PLL, 2 = SYS PLL, 3=DIP PLL, 4=MEM PLL
0x0
0x0
0x1
0x4
0x0
0x0
0x0
This field selects the PLL clock source.
0 = IF PLL, 1 = AP PLL, 2 = SYS PLL, 3=DIP PLL, 4=MEM PLL
This field selects the PLL clock source.
0 = IF PLL, 1 = AP PLL, 2 = SYS PLL, 3= DIP PLL, 4=MEM PLL
This field selects the PLL clock source.
0 = IF PLL, 1 = AP PLL, 2 = SYS PLL, 3= DIP PLL, 4=MEM PLL
This field selects the PLL clock source.
0 = IF PLL, 1 = AP PLL, 2 = SYS PLL, 3= DIP PLL, 4=MEM PLL
5-3
This field selects the PLL clock source.
0 = IF PLL, 1 = AP PLL, 2 = SYS PLL, 3= DIP PLL, 4=MEM PLL
2-0
This field selects the PLL clock source.
0 = IF PLL, 1 = AP PLL, 2 = SYS PLL, 3= DIP PLL, 4=MEM PLL
5.2.8
PLL Divide Register
Table 39. PLL Divide Register
PLL Divide
Address: 0xFC-114
Reset = 0x0
Type: RW
Name
Bit
Function
Reset
Reserved
31-9
8
Reserved
divide_status
This is a read only field that provides an indicator as to when the programmed
divide value has been applied. The divide value is applied when the “counter”
passes through a “0” value so that the resultant output clock remains clean.
Depending on the current count value and the previous clock frequency, there
may be a delay before the new divide value gets applied to the output clock.
This bit gets set when this register is written and slef clears after the new
divide value has been applied.
0x0
Reserved
7-6
Reserved
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
71
Registers
Table 39. PLL Divide Register
pll_divide
5-0
This field contains an integer divide that is applied to the selected ref_clk to
0x0
produce the appropriate peripheral clock.
0 = div1
1 = div2
2 = div3
…
63 = div64
5.3
PAD and I/O registers
5.3.1
Alternate Function Enable Register
Table 40. Alternate Function Enable Register
Alternate Function Enable
Address: 0xd003_0030
Reset = 0
Type: RW
Name
Bit
Function
Reset
reserved
31-29
28
reserved
gps_ena5
0 = main function selected (mp2ts_clk)
1 = alternate function selected (gps_clk)
mp2ts_clk = gps_clk
0
0
0
0
0
0
gps_ena4
gps_ena3
gps_ena2
gps_ena1
second_uart
27
26
25
24
23
0 = main function selected (uart_rts)
1 = alternate function selected (gps_m2)
uart_rts = gps_m2
0 = main function selected (mp2ts_sync)
1 = alternate function selected (gps_m1)
mp2ts_sync = gps_m1
0 = main function selected (mp2ts_valid)
1 = alternate function selected (gps_m0)
mp2ts_valid = gps_m0
0 = main function selected (mp2ts_d)
1 = alternate function selected (gps_s)
mp2ts_d = gps_s
0 = main function selected (dip_data[23:22])
1 = alternate function selected (second uart)
dip_data22 = uart1_rxd
dip_data23 = uart1_txd
spi_mp2ts
22
0 = main function selected (2nd spi interface)
1 = alternate function selected (2nd mp2ts interface)
spi1_sck = mp2ts_clk
0
spi1_ssn = mp2ts_sync
spi1_txd = mp2ts_valid
spi1_rxd = mp2ts_d
SCP220x ICP Family, Rev.2.1
72
Freescale Semiconductor
Registers
Table 40. Alternate Function Enable Register
pwi interface
spi_device3
21
20
19
18
17
0 = main function selected (bb_audio_fsx,bb_audio_clkx)
1 = alternate function selected (pwi_clk,pwi_data)
reserved_3 = pwi_clk
0
reserved_4 = pwi_data
0 = main function selected (nand)
1 = alternate function selected (spi_device3)
reserved_15 = spi_ssn3
0
0
0
0
sc_card_voltage = spi_rxd3
spi_device2
0 = main function selected (nand)
1 = alternate function selected (spi_device2)
uart_rts = spi_ssn2
nand_cen3 = spi_rxd2
spi_device1
0 = main function selected (nand)
1 = alternate function selected (spi_device1)
uart_cts = spi_ssn1
nand_cen2 = spi_rxd1
nand_or_mmc_plus
0 = main function selected (nand)
1 = alternate function selected (mmc_plus)
mmc_plus _data[7:0] = nand_data[7:0]
mmc_plus _clk = nand_cen0
mmc_plus _cmd = nand_cen1
uart_txd
spi_sck
16
15
14
13
12
11
10
9
0 = main function selected (uart_txd)
1 = alternate function selected (dip_ref_clk)
0
0
0
0
0
0
0
0
0
0
0
0 = main function selected (mmc_data3)
1 = alternate function selected (ac_clk)
spi_ssn
0 = main function selected (mmc_data2)
1 = alternate function selected (sys_clk)
spi_rxd
0 = main function selected (mmc_data1)
1 = alternate function selected (mem_ref_clk)
spi_txd
0 = main function selected (mmc_data0)
1 = alternate function selected (if_ref_clk)
reserved_14
reserved_13
reserved_12
reserved_11
reserved_10
reserved_9
0 = main function selected (reserved_14)
1 = alternate function selected (keyscan3_out)
0 = main function selected (reserved_13)
1 = alternate function selected (keyscan2_out)
0 = main function selected reserved_12)
1 = alternate function selected (keyscan1_out)
8
0 = main function selected (reserved_11)
1 = alternate function selected (keyscan0_out)
7
0 = main function selected (reserved_10)
1 = alternate function selected (keyscan3_in)
6
0 = main function selected (reserved_9)
1 = alternate function selected (keyscan2_in)
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
73
Registers
Table 40. Alternate Function Enable Register
reserved_8
5
4
3
2
1
0
0 = main function selected (reserved_8)
1 = alternate function selected (keyscan1_in)
0
0
0
0
0
0
reserved_7
dip_data17
dip_data16
audio_fsr
sc_fcb
0 = main function selected (reserved_7)
1 = alternate function selected (keyscan0_in)
0 = main function selected (dip_data17)
1 = alternate function selected (scl_sec)
0 = main function selected (dip_data16)
1 = alternate function selected (sda_sec)
0 = main function selected (audio_fsr)
1 = alternate function selected (pwm_output2)
0 = main function selected (sc_fcb)
1 = alternate function selected (pwm_output1)
5.3.2
Drive Strength Register
Table 41. Drive Strength Register
Drive Strength 1
Address: 0xd003_0080
Reset = 0
Type: RW
Name
drive_strength[31-0]
Bit
Function
Reset
31-0
A number of the external PADs have configurable drive strength. This register
allows software to configure the drive strength as low or as high. The
following table maps the drive_strength bits to the corresponding PAD that
they control.
0
0 = low drive strength
1 = high drive strength
Drive Strength 2
Address: 0xd003_0084
Reset = 0
Type: RW
Name
Bit
Function
Reset
drive_strength[63-32]
31-0
A number of the external PADs have configurable drive strength. This register
allows software to configure the drive strength as low or as high. The
following table maps the drive_strength bits to the corresponding PAD that
they control.
0
0 = low drive strength
1 = high drive strength
Drive Strength 3
Address: 0xd003_0088
Name Bit
Reset = 0
Type: RW
Function
Reset
SCP220x ICP Family, Rev.2.1
74
Freescale Semiconductor
Registers
Table 41. Drive Strength Register
drive_strength[95-64]
31-0
A number of the external PADs have configurable drive strength. This register
allows software to configure the drive strength as low or as high. The
following table maps the drive_strength bits to the corresponding PAD that
they control.
0
0 = low drive strength
1 = high drive strength
The table below gives the correspondence Drive Strength register bit to pin.
Table 42. Drive Strength register bit to pin correspondence
Bit
Pin
scl_p
Bit
Pin
Bit
Pin
Bit
Pin
0
1
24
25
mclk_p
48
49
spi_sck_p
spi_ssn_p
72
73
sc_fcb_p
sc_io_p
sda_p
audio_clkr
_p
2
3
sif_clkout_
p
26
27
28
29
30
31
32
33
34
audio_fsr_
p
50
51
52
53
54
55
56
57
58
spi_txd_p
fodd_p
74
75
76
77
78
79
80
81
82
sc_card_d
etect_p
audio_clkx
_p
sc_power_
on_p
4
audio_dr_p
sif_gpio_p
sc_card_v
oltage_p
5
audio_dx_
p
nand_ren_
p
nand_cen_
p1
6
audio_fsx_
p
nand_wen
_p
nand_cen_
p2
7
reserved_1
reserved_7
reserved_3
reserved_4
reserved_5
reserved_6
nand_ale_
p
nand_cen_
p3
8
nand_cle_
p
9
dip_data_p
23
10
dip_data_p
22
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
75
Registers
Table 42. Drive Strength register bit to pin correspondence
Bit
Pin
Bit
Pin
Bit
Pin
Bit
Pin
11
reserved_8
35
dip_data_p
[15:0]
59
dip_data_p
21
83
12
Reserved_
9
36
dip_csn0_
p
60
dip_data_p
20
84
dip_csn1_
p
dip_wen_p
dip_rs_p
13
14
15
16
17
18
19
20
21
22
23
reserved_1
0
37
38
39
40
41
42
43
44
45
46
47
mmc_clk_p
61
62
63
64
65
66
67
68
69
70
71
dip_data_p
19
85
86
87
88
89
90
91
92
93
94
95
reserved_1
1
mmc_cmd
_p
dip_data_p
18
reserved_1
2
mmc_data
_p3
dip_data_p
17
reserved_1
3
mmc_data
_p2
dip_data_p
16
Utmiotg_dr
vvbus_p
reserved_1
4
mmc_data
_p1
dip_csn2_
p
spi1_rxd_p
spi1_sck_p
spi1_ssn_p
spi1_txd_p
uart_cts_p
uart_cts_p
mmc_data
_p0
dip_csn3_
p
reserved_2
nand_cen_
p0
dip_oen_p
sdram
control
nand_data
_p[7:0]
dip_pclk_p
sdram_clk
_p
uart_rxd_p
uart_txd_p
spi_rxd_p
dip_cpu_vs
ync_p
ebi_addr_p
[12:0]
sc_clk_p
ebi_data_p
31:0
sc_rst_p
reserved_1
5
5.3.3
PAD Resistor Enable
Table 43. PAD Resistor Enable
PAD Resistor Enable 1
Address: 0xd003_008C
Name Bit
Reset = 0x0801_003c
Function
Type: RW
Reset
SCP220x ICP Family, Rev.2.1
76
Freescale Semiconductor
Registers
Table 43. PAD Resistor Enable
pad_resistor_ena
[31-0]
31-0
A number of the external PADs have configurable pull-up/pull-down
resistors in the PAD. This register allows software to enable the
resistor. The following table maps these register bits to the
corresponding PADs that they control.
0x0801_003c
0 = PAD resistor disabled
1 = PAD resistor enabled
PAD Resistor Enable 2
Address: 0xd003_0090
Reset = 0x0008_4f02
Function
Type: RW
Name
Bit
Reset
pad_resistor_ena
[63-32]
31-0
A number of the external PADs have configurable pull-up/pull-down
resistors in the PAD. This register allows software to enable the
resistor. The following table maps these register bits to the
corresponding PADs that they control.
0x0008_4f02
0 = PAD resistor disabled
1 = PAD resistor enabled
PAD Resistor Enable 3
Address: 0xd003_0094
Reset = 0x01e7_f0d0
Function
Type: RW
Name
Bit
Reset
pad_resistor_ena
[95-64]
31-0
A number of the external PADs have configurable pull-up/pull-down
resistors in the PAD. This register allows software to enable the
resistor. The following table maps these register bits to the
corresponding PADs that they control.
0x01e7_f0d0
0 = PAD resistor disabled
1 = PAD resistor enabled
PAD Resistor Enable 4
Address: 0xd003_0098
Reset = 0x0000_00bf
Function
Type: RW
Name
Bit
Reset
pad_resistor_ena
[117-96]
31-0
A number of the external PADs have configurable pull-up/pull-down
resistors in the PAD. This register allows software to enable the
resistor. The following table maps these register bits to the
corresponding PADs that they control.
0x0000_00bf
0 = PAD resistor disabled
1 = PAD resistor enabled
The table indicates whether the PAD has a pull-up or pull-down with the PU/PD nomenclature in the bit location field.
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
77
Registers
Bit
Table 44. PAD has a pull-up or pull-down
Pin
Bit
Pin
Bit
Pin
Bit
Pin
Bit
Pin
0-PD sda_p
24
reserved
48-P fodd_p
D
72
reserved
97-P dip_data_p
U
4
1-PD sif_clkout_
p
25
26
reserved
reserved
49-P mclk_p
D
73
74
reserved
reserved
98-P dip_data_p
D
3
2
reserved
50-P sif_gpio_p
D
99-P dip_data_p
D
2
3
reserved
27-P mmc_clk_p
U
51-P fclk_p
75-P scl_p
D
100- dip_data_p
PU
D
rclk_p
1
pclk_p
sensor_dat
a_p
4-PU utmiotg_dr
vvbus_p
28-P mmc_cmd
52
reserved
76-P ntrst_p
D
101- dip_data_p
PD
D
_p
0
5
reserved
29-P mmc_data
53-P nand_data[
7:0]
77-P tck_p
U
102- dip_cpu_vs
PD ync_p
D
_p3
D
6-PD sdram_rdy
_p
30-P mmc_data
54-P dip_data_p
23
78-P tdi_p
U
103- sc_clk_p
PU
D
_p2
D
7
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
31-P mmc_data
55-P dip_data_p
22
79-P tms_p
U
104- sc_rst_p
PD
D
_p1
D
8
32-P mmc_data
56-P dip_data_p
21
80-P dip_data_p
105- sc_fcb_p
PD
D
_p0
D
D
6
9
33-P nand_cen_
57-P dip_data_p
20
81-P dip_data_p
106- sc_io_p
PD
U
p0
D
D
7
10
11
12
13
14
15
16
34-P nand_ren_
58-P dip_data_p
19
82-P dip_data_p
107- sc_card_d
D
p
D
D
8
PD
etect_p
35-P nand_wen
_p
59-P dip_data_p
18
83-P dip_data_p
108- sc_power_
PD on_p
D
D
D
9
36-P nand_ale_
60-P dip_data_p
17
84-P dip_data_p
10
109- sc_card_v
PD oltage_p
D
p
D
D
37-P nand_cle_
61-P dip_data_p
16
85-P nand_cen_
p3
110- dip_data_p
D
p
D
U
PD
11
38-P uart_rxd_p
D
62-P dip_data_p
[15:12]
86-P nand_cen_
p2
111
reserved
D
U
39-P uart_txd_p
D
63-P dip_oen_p
D
87-P nand_cen_
p1
U
40-P dip_csn0_
64-P dip_pclk_p
D
88-P spi1_ssn_p
U
U
p
SCP220x ICP Family, Rev.2.1
78
Freescale Semiconductor
Registers
Table 44. PAD has a pull-up or pull-down
41-P dip_csn1_ 65-P mp2ts_clk_ 89-P spi1_txd_p
17-P audio_clkr
_p
D
U
p
D
p
D
mp2ts_d_p
mp2ts_vali
d_p
mp2ts_syn
c_p
18-P audio_fsr_
42-P dip_csn2_
66
67
68
69
70
71
reserved
reserved
reserved
reserved
reserved
reserved
90-P spi1_rxd_p
D
D
p
U
p
19-P audio_clkx
_p
43-P dip_csn3_
91-P spi1_sck_p
D
D
U
p
20-P audio_dr_p
D
44-P spi_rxd_p
D
92-P uart_cts_p
D
21-P audio_dx_
45-P spi_sck_p
D
93-P uart_rts_p
D
D
p
22-P audio_fsx_
46-P spi_ssn_p
U
94
reserved
D
p
23
reserved
47-P spi_txd_p
D
95
reserved
5.4
Reset and Clock Gating
The system reset bits are spread out into two registers: System Reset and System Reset1.
The system power down bits are spread out into two registers: System Power Down and System Power Down1.
5.4.1
System Power Down
This timing generation block has clock gating logic for most of the internal blocks. This register provides software
with a mechanism to gate the clock of any block that is not required for the application at hand. This will reduce power
for certain applications. When a block has its clock gated the block is “disabled” and unusable.
Table 45. System Power Down
System Power Down
Address: 0x d003_001c
Reset = 0xffed_d5ff
Function
Type: RW
Name
Bit
Reset
Reserved
mp2ts1_pdown
spi1_pdown
31
30
29
28
27
Reserved
1
1
1
1
1
When this bit is written “1” the peripheral has its clock gated.
When this bit is written “1” the peripheral has its clock gated.
When this bit is written “1” the peripheral has its clock gated.
When this bit is written “1” the peripheral has its clock gated.
Pwi_pdown
Mmcplus_pdown
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
79
Registers
Table 45. System Power Down
sequencer_pdown
26
When this bit is written “1” the peripheral has its clock gated. This powers
down the GOC buffers and decoding” circuitry (VLD).
1
crypto_pdown
Smart_card_pdown
Rotator_pdown
H264_loop_pdown
bitblt_mini_pdown
ebi_pdown
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
When this bit is written “1” the peripheral has its clock gated.
When this bit is written “1” the peripheral has its clock gated.
When this bit is written “1” the peripheral has its clock gated.
When this bit is written “1” the peripheral has its clock gated.
When this bit is written “1” the peripheral has its clock gated.
When this bit is written “1” the peripheral has its clock gated.
When this bit is written “1” the peripheral has its clock gated.
When this bit is written “1” the peripheral has its clock gated.
When this bit is written “1” the peripheral has its clock gated.
When this bit is written “1” the high speed cmem clock is gated.
When this bit is written “1” the peripheral has its clock gated.
When this bit is written “1” the peripheral has its clock gated.
When this bit is written “1” the peripheral has its clock gated.
When this bit is written “1” the peripheral has its clock gated.
When this bit is written “1” the peripheral has its clock gated.
When this bit is written “1” the peripheral has its clock gated.
When this bit is written “1” the peripheral has its clock gated.
When this bit is written “1” the peripheral has its clock gated.
When this bit is written “1” the peripheral has its clock gated.
1
1
1
1
1
0
1
1
0
1
1
1
0
1
0
1
0
1
1
1
bitblt_pdown
vld_pdown
cmem_if_pdown
ac_pdown
mmc_pdown
dip_pdown
hpi_pdown
usb_pdown
nand_pdown
sif_pdown
spi_pdown
cmem_dma_pdown
entropy_pdown1
bm_pdown
8
7
6
When this bit is written “1” the peripheral has its clock gated. This powers
down everything but the “decoding” circuitry (VLD).
be_pdown
multi_dma_pdown
Mpeg2_ts_pdown
uart_pdown
5
4
3
2
1
0
When this bit is written “1” the peripheral has its clock gated.
When this bit is written “1” the peripheral has its clock gated.
When this bit is written “1” the peripheral has its clock gated.
When this bit is written “1” the peripheral has its clock gated.
When this bit is written “1” the peripheral has its clock gated.
When this bit is written “1” the peripheral has its clock gated.
1
1
1
1
1
1
audio_pdown
i2c_pdown
SCP220x ICP Family, Rev.2.1
80
Freescale Semiconductor
Registers
5.4.2
System power down1
Table 46. System Power Down1
System Power Down1
Address: 0xd003_00cc
Reset = 0xffff_ff3e
Function
Type: RW
Name
Bit
Reset
Reserved
31:8
7
Reserved
When this bit is written “1” the low speed cmem clock is gated.
0xffff_ff
Sys_cmem_if_pdown
system_pdown
0
0
6
When this bit is written “1” some of the system related blocks get their clock
gated – boot_loader, keypad, pwm, gpio
entropy_pdown2
tcm_pdown
5
4
3
2
1
0
When this bit is written “1” the peripheral has its clock gated.
When this bit is written “1” the peripheral has its clock gated.
Reserved
1
1
1
1
1
0
Reserved
sbist_pdown
uart1_pdown
arm2_pdown
When this bit is written “1” the peripheral has its clock gated.
When this bit is written “1” the peripheral has its clock gated.
When this bit is written “1” the peripheral has its clock gated.
5.4.3
System Reset Register
This register provides a mechanism for software to reset any or all of the internal hardware components. Software
controls the assertion and de-assertion of the reset for all peripherals except the ARM926EJ-S processor and the EBI
block.
Table 47. System Reset Register
System Reset
Address: 0xd003_0018
Reset = 0
Type: RW
Name
Bit
Function
Reset
suicide
31
Writing a “1” to this bit will pulse the internal global reset. The entire chip will
be reset as if the external reset signal was asserted. The bit is self resetting
and always returns “0” when read.
0
mp2ts1_rst
spi1_rst
30
29
28
27
When this bit is written “1” the peripheral in held in reset until this bit is written
“0”.
0
0
0
0
When this bit is written “1” the peripheral in held in reset until this bit is written
“0”.
pwi_rst
When this bit is written “1” the peripheral in held in reset until this bit is written
“0”.
mmcplus_rst
When this bit is written “1” the peripheral in held in reset until this bit is written
“0”.
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
81
Registers
Table 47. System Reset Register
sequencer_rst
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
When this bit is written “1” the peripheral in held in reset until this bit is written
“0”.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
crypto_rst
Smart_card_rst
Rotator_rst
H264_loop_rst
bitblt_mini_rst
ebi_rst
When this bit is written “1” the peripheral in held in reset until this bit is written
“0”.
When this bit is written “1” the peripheral in held in reset until this bit is written
“0”.
When this bit is written “1” the peripheral in held in reset until this bit is written
“0”.
When this bit is written “1” the peripheral in held in reset until this bit is written
“0”.
When this bit is written “1” the peripheral in held in reset until this bit is written
“0”.
Writing a “1” to this bit will pulse the EBI block reset. The bit is self resetting
and always returns “0” when read.
bitblt_rst
When this bit is written “1” the peripheral in held in reset until this bit is written
“0”.
vld_rst
When this bit is written “1” the peripheral in held in reset until this bit is written
“0”.
cmem_if_rst
ac_rst
When this bit is written “1” the peripheral in held in reset until this bit is written
“0”.
When this bit is written “1” the peripheral in held in reset until this bit is written
“0”.
mmc_rst
When this bit is written “1” the peripheral in held in reset until this bit is written
“0”.
dip_rst
When this bit is written “1” the peripheral in held in reset until this bit is written
“0”.
hpi_rst
When this bit is written “1” the peripheral in held in reset until this bit is written
“0”.
usb_rst
When this bit is written “1” the peripheral in held in reset until this bit is written
“0”.
nand_rst
When this bit is written “1” the peripheral in held in reset until this bit is written
“0”.
sif_rst
When this bit is written “1” the peripheral in held in reset until this bit is written
“0”.
spi_rst
When this bit is written “1” the peripheral in held in reset until this bit is written
“0”.
cmem_dma_rst
entropy_rst
8
When this bit is written “1” the peripheral in held in reset until this bit is written
“0”.
7
When this bit is written “1” the peripheral in held in reset until this bit is written
“0”.
SCP220x ICP Family, Rev.2.1
82
Freescale Semiconductor
Registers
Table 47. System Reset Register
bm_rst
be_rst
6
5
4
3
2
1
0
When this bit is written “1” the peripheral in held in reset until this bit is written
“0”.
0
0
0
0
0
0
0
When this bit is written “1” the peripheral in held in reset until this bit is written
“0”.
multi_dma_rst
Mpeg2_ts_rst
uart_rst
When this bit is written “1” the peripheral in held in reset until this bit is written
“0”.
When this bit is written “1” the peripheral in held in reset until this bit is written
“0”.
When this bit is written “1” the peripheral in held in reset until this bit is written
“0”.
audio_rst
i2c_rst
When this bit is written “1” the peripheral in held in reset until this bit is written
“0”.
When this bit is written “1” the peripheral in held in reset until this bit is written
“0”.
5.4.4
System Reset1 Register
Table 48. System Reset1 Register
System Reset1
Address: 0xd003_00d0
Reset = 0
Type: RW
Name
Bit
Function
Reset
Reserved
31-4
Reserved
axi_fabric_rst
sbist_rst
3
2
1
0
When this bit is written “1” the peripheral is held in reset.
When this bit is written “1” the peripheral is held in reset.
When this bit is written “1” the peripheral is held in reset.
When this bit is written “1” the peripheral is held in reset.
0
0
0
0
uart1_rst
arm2_rst
5.5
Miscellaneous
5.5.1
Chip ID Register
Table 49. Chip ID Register
Reset = 0
chip ID
Address: 0xd003_0028
Type: RO
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
83
Registers
Table 49. Chip ID Register
Function
Name
Bit
Reset
Reserved
chip_id
31-7
6-4
Reserved
This field reflects the bond-out option for the jtag_sel_p PADs. It can be used
by software to differentiate different chips for marketing purposes.
0
0
chip_rev_num
3-0
This field reflects the silicon revision of the chip.
Table 50.
5.6
Memory Controller
5.6.1
Memory Controller Register Description
Register
Address Offset
0x000
Mode
memc_status
memc_cmd
direct_cmd
memory_cfg
refresh_prd
cas_latency
Tdqss
RO
WO
WO
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
0x040
0x044
0x048
0x04C
0x050
0x054-0xFF
Tmrd
Tras
Trc
Trcd
Trfc
Trp
Trrd
Twr
Twtr
Txp
Txsr
Tesr
memory_cfg2
memory_cfg3
reserved
SCP220x ICP Family, Rev.2.1
84
Freescale Semiconductor
Registers
id_0_cfg
0x100
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
id_1_cfg
0x104
id_2_cfg
0x108
id_3_cfg
0x10C
0x110
id_4_cfg
id_5_cfg
0x114
id_6_cfg
0x118
id_7_cfg
0x11C
0x120
id_8_cfg
id_9_cfg
0x124
id_10_cfg
id_11_cfg
id_12_cfg
id_13_cfg
id_14_cfg
id_15_cfg
reserved
0x128
0x12C
0x130
0x134
0x138
0x13C
0x140-0x1FF
0x200
chip_0_cfg
reserved
0x204-0xFDF
0xFE0
0xFE4
0xFE8
0xFEC
0xFF0
0xFF4
0xFF8
0xFFC
Periph_id_0
Periph_id_1
Periph_id_2
Periph_id_3
Pcell_id_0
Pcell_id_1
Pcell_id_2
Pcell_id_3
5.6.2
memc_status register
This register provides information on the configuration of the memory controller and also on the state of the memory
controller.
memc_status
Address: 0x000
Reset = 0xe34
Type: RO
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
85
Registers
Name
Bit
Function
Reset
Reserved
31-13
12
Reserved
See bit 9.
Memory_banks1
Exclusive_monitors
d1
d3
11-10
Returns the number of exclusive access monitor resources implemented in
the controller.
00=0 monitor, 01=1 monitor, 10=2 monitors , 11=4 monitors
Memory_banks0
9
This returns the maximum number of banks that the controller supports.
d1
00 = 2 banks
01 = 4 banks
10,11 = reserved
Memory_chips
Memory_ddr
8-7
6-4
This returns the number of chip selects that the controller supports.
00=1 chip, 01=2 chips, 10=3 chips, 11=4 chips
d0
This returns the type of memory controller.
d11
000=SDR sdram, 001=DDR sdram, 011=mobile DDR sdram
If mobile DDR sdram or SDR sdram is supported, the cas_half_cycle bit at
address offset 0x14 is ignored.
Memory_width
Memc_status
3-2
1-0
This returns the width of the external memory.
00=16bit, 01=32bit, 10=64bit
d1
This returns the state of the memory controller.
00=config, 01=ready, 10=paused, 11=low power
5.6.3
memc_cmd register
This registers controls the state of the FSM within the controller. By writing to this register the FSM can be traversed.
If a new command is received to change state and a previous command has not be completed, the APB3 pready
signal is held LOW (bus cycle is waited) until the new command can be carried out.
Memc_cmd
Address: 0x004
Reset = 0x0
Type: WO
Name
Bit
Function
Reset
Reserved
31-3
2-0
Reserved
Changes the state of the memory controller.
Memc_cmd
d0
000=go, 001=sleep, 010=wakeup, 011=pause, 100=configure, 111=active
pause
Active_pause puts the controller into a paused state without draining the arbiter
queue. This enables you to enter low-power mode to change configuration
settings such as memory frequency or timing register values without requiring
co-ordination between masters in a multi-master system.
If the controller is put into low-power mode after using the active_pause
command, you may not remove power from the controller because this results in
data loss and violation of the AXI protocol.
The controller does not issue refreshes while in the config state. It is, therefore,
recommended that you use the low-power mode to make register updates
because this ensures that the memory is put into self-refresh rather than entering
the config state when the memory contains valid data.
SCP220x ICP Family, Rev.2.1
86
Freescale Semiconductor
Registers
5.6.4
direct_cmd register
This register passes commands to the external memory. The configuration of this register enables you to write to
any type of mode register supported by the external memory device and also to generate NOP, prechargeall and
auto refresh commands. This register therefore enables any initialization sequence that an external memory device
might require. The only timing information associated with this register are the command delays defined in the timing
registers. Therefore, if an initialization sequence requires additional delays between commands, they must be timed
by the master driving the initialization sequence. The register can only be written to in the config or low-power state.
Direct_cmd
Address: 0x08
Name
Reset = 0c0
Type: WO
Bit
Function
Reset
Reserved
ext_memory_cmd
Chip_number
Memory_cmd
31-23
22
Reserved
See bit 19-18.
d0
d0
d0
21-20
19-18
Bits mapped to external memory chip address bits.
Determines the command required.
000=prechargeall, 001=auto-refresh, 010=modereg or extended modereg
access, 011=NOP,100=deep power down
Bank_addr
17-16
Bits mapped to external memory bank address bits when command is
modereg access.
d0
d0
Reserved
15-14
13-0
Reserved
Addr_13_to_0
Bits mapped to external memory address bits [13:0] when command is
modereg access.
5.6.5
memory_cfg register
This register configures the memory. It can only be read/written in the config or low-power state.
Memory_cfg
Address: 0x0C
Name
Reset = 0x10020
Type: RW
Bit
Function
Reset
sr_enable
fp_time
31
30-24
23
Auto self refersh entry.
d0
d0
d0
d0
Force precharge timeout count.
Force precharge enable.
fp_enable
Active_chips
22-21
Enables the refresh command generation for the number of memory
chips. It is only possible to generate commands up to and including the
number of chips in the configuration that the memc_status register
defines.
00=1 chip, 01=2 chips, 10=3 chips, 11=4 chips
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
87
Registers
Qos_master_bits
20-18
17-15
Encodes the 4 bits of the 8 bit AXI ARID that select one of the 16 QOS
values.
000=ARID[3:0], 001=ARID[4:1], 010=ARID[5:2], 011=ARID[6:3],
100=ARID[7:4]
d0
d3
Memory_burst
Encodes the number of data accesses that are performed to the SDRAM
for each read or write command.
000=burst1, 001=burst2, 010=burst4, 011=burst8, 100=burst16
The value must also be programmed into the SDRAM mode register
using the direct_cmd register at offset 0x8 and must match it.
Stop_mem_clk
14
13
When enabled, the memory clock is dynamically stopped when not
performing an access to the SDRAM.
d0
d0
Auto_power_down
When this is set, the memory interface automatically places the SDRAM
into the power-down state by de-asserting CKE when the command FIFO
has been empty for the PowerDownPrd memory clock cycles.
Power_down_prd
Ap_bit
12-7
6
Number of memory clock cycles for auto power-down of the SDRAM.
d0
d2
Encodes the position of the auto-precharge bit in the memory address.
0=addr10, 1=addr8
Row_bits
5-3
Encodes the number of the AXI address that comprise the row address.
000=11bits, 001=12bits, 010=13bits, 011=14bits, 100=15bits,
101=16bits
d0
The combination of row size, column size, BRC/RBC and memory width
must ensure that neither the MSB of the row address nor the MSB of the
bank address exceed address range [27:0].
Column_bits
2-0
Encodes the number of the AXI address that comprise the column
address.
d0
000=8bits, 001=9bits, 010=10bits, 011=11bits, 100=12bits
5.6.6
refresh_prd register
This sets the memory refresh period. It can only be read/written to in the config or low-power state.
Refresh_prd
Address: 0x10
Name
Reset = 0xa60
Type: RW
Bit
Function
Reset
Reserved
31-15
14-0
Reserved
Refresh_prd
Memory refresh period in memory clock cycles.
0xa60
5.6.7
cas_latency register
This sets the cas_latency in memory clock cycles. It can only be read/written to in the config or low-power state.
Cas_latency
Address: 0x14
Reset = 0x6
Type: RW
SCP220x ICP Family, Rev.2.1
88
Freescale Semiconductor
Registers
Reset
Name
Bit
Function
Reserved
Cas_latency
Cas_half_cycle
31-4
3-1
0
Reserved
CAS latency in memory clock cycles.
d3
d0
Encodes whether the CAS latency is half a memory clock cycle more than
the value given in bite[3:1].
0=zero cycle offset (is forced in MDDR and SDR mode)
1=half cycle offset to value in [3:1]
5.6.8
Tdqss register
It can only be read/written to in the config or low-power state.
Tdqss
Address: 0x18
Name
Reset = 0x1
Type: RW
Bit
Function
Reset
Reserved
Tdqss
31-2
1-0
Reserved
Write to DQS in memory clock cycles.
0x1
5.6.9
Tmrd register
It can only be read/written to in the config or low-power state.
Tmrd
Address: 0x1C
Name
Reset = 0x2
Type: RW
Bit
Function
Reset
Reserved
Tmrd
31-7
6-0
Reserved
Sets mode register command time in memory clock cycles.
0x2
5.6.10 Tras Register
It can only be read/written to in the config or low-power state.
Tras
Address: 0x20
Name
Reset = 0x7
Type: RW
Bit
Function
Reset
Reserved
Tras
31-4
3-0
Reserved
Sets RAS to precharge delay in memory clock cycles.
0x7
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
89
Registers
5.6.11 Trc Register
It can only be read/written to in the config or low-power state.
Tdqss
Address: 0x24
Name
Reset = 0xB
Type: RW
Bit
Function
Reset
Reserved
Trc
31-4
3-0
Reserved
Sets active bank x to active bank x delay in memory clock cycles.
0xB
5.6.12 Trcd Register
It can only be read/written to in the config or low-power state.
Trcd
Address: 0x28
Name
Reset = 0x1D
Type: RW
Bit
Function
Reset
Reserved
Schedule_Trcd
Trcd
31-6
5-3
Reserved
Sets the RAS to CAS minimum delay in aclk cycles – 3.
0x5
0x5
2-0
Sets the RAS to CAS minimum delay in memory clock cycles.
5.6.13 Trfc Register
It can only be read/written to in the config or low-power state.
Trfc
Address: 0x2C
Name
Reset = 0x212
Type: RW
Bit
Function
Reset
Reserved
Schedule_Trfc
Trfc
31-10
9-5
Reserved
Sets the auto-refresh command time in aclk cycles - 3.
0x10
0x12
4-0
Sets the auto-refresh command time in memory clock cycles.
5.6.14 Trp Register
It can only be read/written to in the config or low-power state.
Trp
Address: 0x30
Name
Reset = 0x1d
Type: RW
Bit
Function
Reset
SCP220x ICP Family, Rev.2.1
90
Freescale Semiconductor
Registers
Reserved
Schedule_Trp
Trp
31-6
5-3
Reserved
Sets the precharge to RAS delay in aclk cycles - 3.
Sets the precharge to RAS delay in memory clock cycles.
0x5
0x5
2-0
5.6.15 Trrd Register
It can only be read/written to in the config or low-power state.
Trrd
Address: 0x34
Name
Reset = 0x2
Type: RW
Bit
Function
Reset
Reserved
Trrd
31-4
3-0
Reserved
Sets active bank x to active bank y delay in memory clock cycles.
0x2
5.6.16 Twr Register
It can only be read/written to in the config or low-power state.
Twr
Address: 0x38
Name
Reset = 0x3
Type: RW
Bit
Function
Reset
Reserved
Twr
31-3
2-0
Reserved
Sets the write to precharge delay in memory clock cycles.
0x3
5.6.17 Twtr Register
It can only be read/written to in the config or low-power state.
Twtr
Address: 0x3C
Name
Reset = 0x2
Type: RW
Bit
Function
Reset
Reserved
Twtr
31-3
2-0
Reserved
Sets the write to read delay in memory clock cycles.
0x2
5.6.18 TxP Register
It can only be read/written to in the config or low-power state.
Txp
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
91
Registers
Address: 0x40
Name
Reset = 0x1
Type: RW
Bit
Function
Reset
Reserved
Txp
31-8
7-0
Reserved
Sets the exit power-down command time in memory clock cycles.
0x1
5.6.19 Txsr Register
It can only be read/written to in the config or low-power state.
Txsr
Address: 0x44
Name
Reset = 0xa
Type: RW
Bit
Function
Reset
Reserved
Txsr
31-8
7-0
Reserved
Sets the exit self-refresh command time in memory clock cycles.
0xa
5.6.20 Tesr Register
It can only be read/written to in the config or low-power state.
Tesr
Address: 0x48
Name
Reset = 0x14
Type: RW
Bit
Function
Reset
Reserved
Tesr
31-8
7-0
Reserved
Sets the self-refresh command time in memory clock cycles.
0x14
5.6.21 Memory_cfg2 Register
It can only be read/written to in the config or low-power state.
Memory_cfg2
Address: 0x4c
Name
Reset = 0x0
Type: RW
Bit
Function
Reset
Reserved
31-11
10-9
Reserved
Read_delay
Sets the latency in clocks cycles of the PAD interface.
0x0
SCP220x ICP Family, Rev.2.1
92
Freescale Semiconductor
Registers
memory_type
memory width
8-6
5-4
Sets the memory type.
000 = SDR
001 = DDR
010 = eDRAM
011 = LPDDR
0x0
Sets the width of the external memory.
00 = 16 bit
0x0
01 = 32 bit
10 = 64 bit
11 = reserved
cke_init
dqm_init
3
2
1
Sets the level of the cke output after reset.
Sets the level of the dqm outputs after reset.
0x0
0x0
0x0
a_gt_m_sync
Required to be set high when aclk and mclk are running synchronous but
when aclk running faster than mclk.
sync
0
Set high when aclk and mclk are synchronous.
0x0
5.6.22 Memory_cfg3 Register
It can only be read/written to in the config or low-power state.
Memory_cfg3
Address: 0x50
Name
Reset = 0x0
Type: RW
Bit
Function
Reset
Reserved
prescale
31-12
11-3
2-0
Reserved
Prescaler counter value.
Maximum number of outstanding refresh commands.
0x0
0x0
max_outs_refs
5.6.23 ld_x_cfg Registers
It can only be read/written to in the config or low-power state. For reference, the Ids for the masters are as follows:
Id = 0x00 – bridge from primary AHB control bus
Id = 0x20 – bridge from USB master
Id = 0x40 – bridge from ARM926EJ-S processor instruction bus
Id = 0x60 – MC-dma
Id = 0x80 – rotator
Id = 0xa0 – bitblt
Id = 0xc0 – bitblt_mini
Id = 0xe0 – bridge from secondary AHB control bus
Id_x_cfg
Address: 0x100-0x13c
Reset = 0x0
Type: RW
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
93
Registers
Name
Bit
Function
Reset
Reserved
Qos_max
Qos_min
31-10
9-2
1
Reserved
Sets a maximum QoS.
Sets a minimum Qos.
0x0
0x0
0x0
Qos_enable
0
Enables a QoS value to be applied to memory reads from address IS x.
5.6.24 chip_0_cfg Register
It can only be read/written to in the config or low-power state.
Chip_0_cfg
Address: 0x200
Name
Reset = 0xff00
Type: RW
Reset
0x0
Bit
Function
Reserved
Brc_n_rbc
31-17
16
Reserved
Selects the memory organization as decoded from the AXI address.
0=row,bank,column organization
1= bank,row,column organization
Address_match
Address_mask
15-8
7-0
Comparison value for AXI address bits [31:24] to determine the chip that
is selected.
0xFF
0x0
The mask for the AXI address bite [31:24] to determine the chip that is
selected.
1=corresponding address bit is to be used for comparison.
5.6.25 Peripheral Identification 0-3 registers
Peripheral_id0
Address: 0xfe0
Name
Reset = 0x40
Type: RO
Bit
Function
Reset
Reserved
31-8
7-0
Reserved
Part_number
Primecell part number.
0x40
Peripheral_id1
Address: 0xfe4
Name
Reset = 0x13
Type: RO
Bit
Function
Reset
Reserved
designer
31-8
7-4
Reserved
Primecell designer.
0x1
SCP220x ICP Family, Rev.2.1
94
Freescale Semiconductor
Registers
Part_number
3-0
Primecell part number.
0x3
Peripheral_id2
Address: 0xfe8
Name
Reset = 0x14
Type: RO
Type: RO
Type: RO
Bit
Function
Reset
Reserved
revision
31-8
7-4
Reserved
Primecell revision number.
Primecell designer.
0x1
0x4
designer
3-0
Peripheral_id3
Address: 0xfec
Name
Reset = 0x0
Bit
Function
Reset
Reserved
31-4
3-0
Reserved
Customer_mod
Customer Modified number.
0x0
5.6.26 Primecell Identification 0-3 registers
Pcell_id0
Address: 0xff0
Name
Reset = 0xD
Bit
Function
Reset
Reserved
31-8
7-0
Reserved
Id_number
Id_number
0xD
Pcell_id1
Address: 0xff4
Name
Reset = 0xF0
Type: RO
Bit
Function
Reset
Reserved
31-8
7-0
Reserved
Id_number
Id_number
0xF0
Pcell_id2
Address: 0xff8
Reset = 0x5
Type: RO
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
95
Registers
Name
Bit
Function
Reset
Reserved
31-8
7-0
Reserved
Id_number
Id_number
0x5
Pcell_id3
Address: 0xffc
Name
Reset = 0xB1
Type: RO
Bit
Function
Reset
Reserved
31-8
7-0
Reserved
Id_number
Id_number
0xB1
5.7
NAND Interface Registers Description
NAND Register Map
5.7.1
The register map is summarized below and described in the following sections.
Table 51. NAND Register Map
Register
Interrupt Source
Address Offset
0x00
Mode
RO
RW
WO
RW
RW
RW
RW
RW
RW
RO
WO
RO
RO
RO
Interrupt Mask
0x04
Interrupt Clear
0x08
Interface Timing
0x0C
0x10
NAND Configuration
NAND Action
0x14
NAND Command
NAND Address
0x18
0x1C
0x20
NAND Address (extended)
NAND Read
0x24
NAND Write
0x28
NAND Status
0x2C
0x30-0x3C
0x40-0x5C
0x60
NAND Simple ECC result
NAND Generated Simple ECC
FIFO status
RO/WO
RW
FIFO flag Configuration
0x64
SCP220x ICP Family, Rev.2.1
96
Freescale Semiconductor
Registers
Table 51. NAND Register Map
RS ECC config
0x68
RW
RW
RW
RW
RO
RO
RO
RO
RS ECC Read Parity1
RS ECC Read Parity2
RS ECC Read Parity3
RS ECC Write Parity1
RS ECC Write Parity2
RS ECC Write Parity3
RS ECC Status
0x6C
0x70
0x74
0x78
0x7C
0x80
0x84
reserved
0x88-0xfff
0x1000-0x1fff
0x2000-0x2fff
transmit FIFO
WO
RO
receive FIFO
5.7.2
Interrupt Source Register
The interrupt source register contains the raw unmasked interrupts and can be used for polling purposes (instead
of the external interrupt pin) or for determining which interrupt(s) have caused the external interrupt pin to assert.
Table 52. Interrupt Source Register
Interrupt Source Register
Address: 0x00
Name
Reset = 0x0
Type: RO
Bit
Function
Reset
Reserved
31-15
14
Reserved
corrected_data_done
This interrupt is asserted (if using the Reed Solomon ECC) when the
corrected data for a 512 byte block has been write to the input FIFO.
0x0
0x0
read_ecc_complete
write_par_complete
13
12
Indicates that the Reed Solomon ECC engine has finished checking the
last read 512 byte block. The RS ECC status register will now contain the
ECC results for that read block.
Indicates that the Reed Solomon ECC engine has generated the write
parity and it is available in the write parity registers.
0x0
nand_block_write
nand_block_read
tx_pop_error
11
10
9
Indicates that a NAND block write operation is completed
Indicates that a NAND block read operation is completed
0x0
0x0
0x0
asserted when the transmit FIFO experiences an overrun condition or
misaligned access. This error is from the perspective of the external
interface.
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
97
Registers
Table 52. Interrupt Source Register
rx_push_error
8
7
6
asserted when the receive FIFO experiences an underrun condition or
misaligned access. This error is from the perspective of the external
interface.
0x0
0x0
0x0
dma_pop_error
dma_push_error
asserted when the receive FIFO experiences an underrun condition or
misaligned access. This error is from the perspective of the internal APB
bus.
asserted when the transmit FIFO experiences an overrun condition or
misaligned access. A misaligned access can occur if the width of the write
has changed from a previous access. For example, if byte writes have
previously been used, the number of writes may be non-multiples of 32 bits.
If a 32 bit write now occurs, this is a misaligned access because the byte
pointers in the FIFO are not pointing to byte ’0’. This error is from the
perspective of the internal APB bus.
rx_ff
5
4
asserted when the receive FIFO has become full
0x0
0x0
rx_hf
asserted when the receive FIFO level (amount of bytes in the FIFO) is
above the software configured “half” empty level.
rx_fe
tx_ff
3
2
1
asserted when the receive FIFO has become NOT empty
asserted when the transmit FIFO has become NOT full
0x0
0x0
0x0
tx_hf
asserted when the transmit FIFO level (amount of space available) is above
the software configured “half” full level.
tx_fe
0
asserted when the transmit FIFO has become empty
0x0
5.7.3
Interrupt Mask Register
The interrupt mask register provides a mechanism to individually mask one or more of the interrupt sources.
Table 53. Interrupt Mask Register
Interrupt Mask Register
Address: 0x04
Name
Reset = 0xFFFF_FFFF
Function
Type: RW
Bit
Reset
Reserved
31-15
14
Reserved
corrected_data_done
read_ecc_complete
write_par_complete
nand_block_write
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
0x1
0x1
0x1
0x1
13
12
11
SCP220x ICP Family, Rev.2.1
98
Freescale Semiconductor
Registers
Table 53. Interrupt Mask Register
nand_block_read
tx_pop_error
rx_push_error
dma_pop_error
dma_push_error
rx_ff
10
9
8
7
6
5
4
3
2
1
0
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
rx_hf
rx_fe
tx_ff
tx_hf
tx_fe
5.7.4
Interrupt Clear Register
The interrupt clear register provides the mechanism for clearing the raw interrupt sources. Writing a „1. to the
interrupt bit location will clear the interrupt.
Table 54. Interrupt Clear Register
Interrupt Clear Register
Address: 0x08
Name
Reset = 0x0
Type: WO
Bit
Function
Reset
Reserved
corrected_data_done
read_ecc_complete
write_par_complete
nand_block_write
nand_block_read
tx_pop_error
31-15
14
13
12
11
10
9
Reserved
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
rx_push_error
dma_pop_error
dma_push_error
rx_ff
8
7
6
5
rx_hf
4
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
99
Registers
Table 54. Interrupt Clear Register
rx_fe
tx_ff
3
2
1
0
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
0x0
0x0
0x0
0x0
tx_hf
tx_fe
5.7.5
Interface Timing
All timing parameters refer to increments of the internal reference clock and a value of .0. means 1x refclk, a value
of .1. means 2x refclk, etc.
Table 55. Interface Timing
Interface Timing
Address: 0x0C
Reset = 0x01001000
Function
Type: RW
Name
Chip_select_sel
Bit
Reset
31-28
The nand interface supports 4 external chip selects (of which only one can
be active at any one time). This “one-hot” field indicates which external chip
select is active. The chip select that is active is turned on and off by the
controlling bits in the NAND Action register.
0001 – chip select 0 selected
0x0
0010 – chip select 1 selected
0100 – chip select 2 selected
1000 – chip select 3 selected
Any other value will disabled all chip selects.
t7
27-24
Indicates the number of system clocks from NAND_CLE/NAND_ALE
inactive to NAND_ALE/ NAND_CLE active. Also indicates the number of
system clocks from NAND_ALE inactive to NAND_WE/NAND_RE active. A
value of ‘0’ is invalid for this field.
0x1
t6
t5
t4
23-20
19-16
15-12
Indicates the number of system clocks for the NAND_RE inactive pulse width
Indicates the number of system clocks for the NAND_RE active pulse width
0x0
0x0
0x1
Indicates the number of system clocks for the NAND_WE inactive pulse
width. A value of ‘0’ is invalid for this field.
t3
11-8
Indicates the number of system clocks from NAND_WE inactive to
NAND_CLE inactive
0x0
t2
t1
7-4
3-0
Indicates the number of system clocks for the NAND_WE active pulse width
0x0
0x0
Indicates the number of system clocks from NAND_CLE active to NAND_WE
active
SCP220x ICP Family, Rev.2.1
100
Freescale Semiconductor
Registers
5.7.6
NAND configuration
Table 56. NAND Configuration
NAND Configuration
Address: 0x10
Reset = 0x0
Type: RW
Name
Bit
Function
Reset
nand_read_ena
31
The “NAND Read” register initiates an external access when the register is
read. There may be circumstances where this is undesirable (i.e. debug).
This bit will disable the operation of that register. When operation is disabled
a read of the “NAND Read” register will complete but the data will be invalid.
0 = “NAND Read” register accesses do not initiate external NAND cycles.
1 = Normal operation for “NAND Read” register accesses.
0x0
nand_if_ena
ecc_ena
30
Enables the internal state machine as well as the external PADs for the
control signals.
0 = interface disabled
1 = interface enabled
0x0
0x0
29
28
Enables the writing (for block writes) and checking (for block reads) of ECC.
Refer to the hardware description for a more detailed explanation of ECC
generation and checking. This enable bit is only pertinent to the “simple” ECC
method.
addr_size
27-24
23-16
Indicates how many bytes are associated with an address transaction.
0x0
0x0
spare_size
Indicates the number of bytes in the spare or redundant area of the NAND
Flash.
page_size
15-0
Indicates the number of bytes in the page of data associated with the NAND
flash.
0x0
5.7.7
NAND Action
Table 57. NAND Action
NAND Action
Address: 0x14
Reset = 0x0
Type: RW
Name
Bit
Function
Reset
Reserved
write_kick
31-4
3
Reserved
Initiates a block write transaction. The NAND hardware interface will do a
series of writes that totals the "page_size" + "ecc_size" + "spare_size". Once
completed, the NAND_page_write interrupt is asserted. This action will
commence after this bit is set and data is present in the transmit FIFO. The
bit is self resetting and always returns 0 when read.
0x0
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
101
Registers
Table 57. NAND Action
read_kick
2
Initiates a block read transaction. The NAND hardware interface will do a
series of reads that totals the "page_size" + "ecc_size" + "spare_size". Once
completed, the NAND_page_read interrupt is asserted. This action will
commence immediately after this bit is set. Software must ensure that the
NAND device is available for a page read operation prior to issuing the "kick".
The bit is self resetting and always returns 0 when read.
0x0
ce_dis
1
0
Setting this bit to ’1’ de-asserts the NAND Flash chip enable. This operation
must be done after NAND accesses are completed and the NAND Flash is
effectively idle. The bit is self resetting and always returns 0 when read.
0x0
0x0
ce_ena
Setting this bit to ’1’ asserts the NAND Flash chip enable. This operation
must be done before any NAND Flash reading or writing is initiated. The bit
is self resetting and always returns 0 when read.
5.7.8
NAND command
Table 58. NAND command
NAND Command
Address: 0x18
Reset = 0x0
Function
Type: RW
Name
Bit
Reset
Reserved
command
31-8
7-0
Reserved
This register contains and initiates a command cycle to the NAND Flash.
Writing a command to the register initiates an external command access.
Reading the register will provide the value of the previous command that was
issued.
0x0
SCP220x ICP Family, Rev.2.1
102
Freescale Semiconductor
Registers
5.7.9
NAND address
This register contains and initiates a series of address cycles to the NAND Flash. The number of address cycles
initiated is controlled by the "addr_size" field in the NAND configuration register. If the number of address bytes is
greater than 4, writing to this register does not initiate any external cycles. Instead the write to the extended NAND
address register initiates the external address cycles. Reading the register will provide the value of the previous
address that was issued.
Table 59. NAND Address
NAND Address
Address: 0x1C
Reset = 0x0
Type: RW
Type: RW
Type: RO
Name
Bit
Function
Reset
addr3
addr2
addr1
addr0
31-24
23-16
15-8
7-0
4th address byte
rd address byte
0x0
0x0
0x0
0x0
3
2nd address byte
1st address byte
5.7.10 NAND address (extended)
Table 60. NAND address (extended)
NAND Address (extended)
Address: 0x20
Reset = 0x0
Function
Name
Bit
Reset
addr7
addr6
addr5
addr4
31-24
23-16
15-8
7-0
8th address byte
th address byte
0x0
0x0
0x0
0x0
7
6th address byte
5th address byte
5.7.11 NAND Read
Table 61. NAND Read
NAND Read
Address: 0x24
Reset = 0x0
Name
Bit
Function
Reset
31-16
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
103
Registers
Table 61. NAND Read
read_data
15-0
This register, when read will initiate a read cycle to the NAND Flash. It is
intended as a status polling mechanism and must be used in conjunction with
appropriate command and address sequencing. The MSB is only applicable
if 16 bit NAND Flash is enabled.
0x0
5.7.12 NAND Write
Table 62. NAND Write
NAND Write
Address: 0x28
Reset = 0x0
Type: WO
Name
Bit
Function
Reset
31-16
15-0
write_data
This register, when written will initiate a write cycle to the NAND Flash. It is
intended as an alternative to a datapath driven by the FIFO. This register is
probably only pertinent to debug or NAND maintenance operations. The
MSB is only applicable if 16 bit NAND Flash is enabled.
0x0
5.7.13 NAND Status
This register contains status information associated with NAND read activity. ECC generation and checking is done
on 256 byte blocks. Error results are stored for each 256 byte block (for instance if the NAND page size is 2048 bytes
then there are 8 result fields and error bits that are pertinent to this activity).
Table 63. NAND Status
NAND Status
Address: 0x2C
Name
Reset = 0x0
Type: RO
Bit
Function
Reset
Reserved
31-19
18
Reserved
Write_pending
When ’1’, this bit indicates that a single write cycle is still in progress and
is not yet completed. If back to back writes need to be issued this bit should
be polled and the second write not written until the bit indicates a
completion.
0x0
address_pending
17
When ’1’, this bit indicates that an address cycle is still in progress and is
not yet completed. If back to back addresses need to be issued this bit
should be polled and the second address not written until the bit indicates
a completion.
0x0
SCP220x ICP Family, Rev.2.1
104
Freescale Semiconductor
Registers
Table 63. NAND Status
command_pending
16
When ’1’, this bit indicates that a command is still in progress and is not
yet completed. If back to back commands need to be issued this bit should
be polled and the second command not written until the bit indicates a
completion.
0x0
ecc_error
data_error
15-8
7-0
Indicates that there is an un-correctable error and the data is incorrect.
There is one bit per 256 byte block read from memory. This is only
pertinent to the “simple” ECC method.
0x0
0x0
Indicates that there is a correctable data error. The ecc_result field
registers provide enough information to correct the error. There is one bit
per 256 byte block read from memory. This is only pertinent to the “simple”
ECC method.
5.7.14
NAND Simple ECC result
These registers contain the result fields from the NAND ECC checking. These fields are only applicable when ECC
is enabled and a block read has taken place. There is a valid result field for every 256 byte block written to the NAND
page.
Table 64. NAND Simple ECC result
NAND Simple ECC result
Address: 0x30-3C
Reset = 0x0
Type: RO
Name
Bit
Function
Reset
31-27
26-16
ecc_result2
ecc_result4
ecc_result6
ecc_result8
ecc result field for additional 256 byte blocks
0x0
15-11
10-0
ecc_result1
ecc_result3
ecc_result5
ecc_result7
The result field is pertinent when a correctable error has been detected. The
NAND status register indicates whether an error has occurred and whether
the error is correctable. When the error is correctable (a single bit error in the
256 byte block) the result provides enough information so that it can be
corrected. eccx_result[7:0] contains the byte address (within the 256 byte
block) that has the bit error. eccx_result[10:8] indicates which bit within the
byte is incorrect. To fix the error, software must invert the bit indicated by this
result field.
0x0
5.7.15 NAND Generated Simple ECC
These registers contain the generated ECC resulting from a block write or a block read. The registers contain
generated ECC whether or not ECC has been enabled. The intent of these registers are to provide flexibility to
software. If ECC is enabled, the contents of these registers are automatically written to flash (for a block write)
immediately following the block of data. If the application requires the ECC to be in a location other than the first set
of bytes in the redundant block, ECC should be disabled so that hardware does not automatically write the ECC.
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
105
Registers
Software can then read the generated ECC from these registers and write it to a different location in the redundant
block. For a block read, the generated ECC and the stored ECC can be applied to the same validation algorithm that
the hardware employs to determine how to correct bit errors.
Table 65. NAND Generated Simple ECC
NAND Generated Simple ECC
Address: 0x40-5C
Reset = 0x0
Type: RO
Name
Bit
Function
Reset
Reserved
31-24
23-0
Reserved
ecc_generated1
ecc_generated2
ecc_generated3
ecc_generated4
ecc_generated5
ecc_generated6
ecc_generated7
ecc_generated8
The result field contains the generated ECC for the appropriate 256 byte
block. This is only pertinent to the “simple” ECC method.
0x0
5.7.16 FIFO Status
Table 66. FIFO Status
FIFO status
Address: 0x60
Reset = 0x80
Type: RO/WO
Name
Bit
Function
Reset
rx_flush
31
When this bit is written ‘1’, the receive FIFO is flushed.
This bit is a write only bit.
0x0
tx_flush
30
When this bit is written ‘1’, the transmit FIFO is flushed.
This bit is a write only bit.
0x0
Reserved
29-14
15-8
Reserved
rx_byte_count
Indicates how many bytes of data is present in the receive FIFO. This is a read
only field.
0x0
tx_byte_count
7-0
Indicates how many bytes of free space is available in the transmit FIFO. This
is a read only field.
0x80
5.7.17 FIFO Flag Configuration
Table 67. FIFO Flag Configuration
FIFO flag Configuration
SCP220x ICP Family, Rev.2.1
106
Freescale Semiconductor
Registers
Table 67. FIFO Flag Configuration
Reset = 0x28_4040
Address: 0x64
Name
Type: RW
Bit
Function
Reset
Reserved
31-22
21:20
Reserved
rx_FIFO_size
Although the asynchronous FIFO supports reads of varying sizes (8,16,32 or
0x10
64) the size must be configured prior to using the FIFO. This size refers to the
side of the FIFO that the internal bus or dma engine reads from. If this field
is being updated, the FIFO must be flushed to ensure that the internal
pointers are properly aligned.
00 = 8 bit
01 = 16 bit
10 = 32 bit
11 = 64 bit
tx_FIFO_size
19-18
Although the asynchronous FIFO supports writes of varying sizes (8,16,32 or
0x10
64) the size must be configured prior to using the FIFO. This size refers to the
side of the FIFO that the internal bus or dma engine writes to. If this field is
being updated, the FIFO must be flushed to ensure that the internal pointers
are properly aligned.
00 = 8 bit
01 = 16 bit
10 = 32 bit
11 = 64 bit
Reserved
17-16
15-8
Reserved
rx_half_empty
Sets the FIFO level (in bytes) that asserts the receive “half” empty flag. The
level setting is associated with how much data is in the FIFO. i.e. if the setting
is 0x20, then when the FIFO fills above 0x20 bytes of data available in the
FIFO, the interrupt will be asserted.
0x40
0x40
tx_half_full
7-0
Sets the FIFO level (in bytes) that asserts the transmit “half” full flag. The
level setting is associated with how much space is available in the FIFO. i.e.
if the setting is 0x20, then when the FIFO drains such that the amount of
space available becomes 0x20 bytes, the interrupt will be asserted.
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
107
Registers
5.7.18 RS ECC config
Table 68. RS ECC config
Reset = 0x0
RS ECC config
Address: 0x68
Type: RW
Name
Bit
Function
Reset
Reserved
31-3
2
Reserved
rs_ecc_writepar_go
Some applications require the write parity before the write block is sent to
the nand flash. This “kicking” signal allows the write block to pass through
the RS ECC block to generate the write ECC bytes without sending the 512
byte block to nand flash. This bit is self clearing, and when it is written the
hardware will read 512 bytes from the transmit FIFO and pass it through the
RS ECC block, After this process is complete, the 9 bytes of write ECC can
be then be read from the “RS ECC write parity” registers and written to
nand flash before the actual 512 byte block is written. After the parity is
written, a block write can be configured and the 512 bytes of data can be
written to the transmit FIFO again. This time the block will be written to the
nand flash.
0x0
rs_ecc_correct_go
rs_ecc_enable
1
0
This is a self clearing bit that is used if the RS ECC engine indicates that
correctable read errors have been detected. When this bit is written, the
input FIFO is loaded up with the corrected data of the 512 byte block.
0x0
0x0
This bit is set before any data operation occurs, if RS ECC operation is
required.
0 = RS ECC operation disabled.
1 = RS ECC checking and generation is enabled.
5.7.19 RS ECC read parity
These registers are programmed with the 9 bytes of ECC for the next 512 byte block read. They must be
programmed prior to initiating the block read.
RS ECC read parity1
Address: 0x6C
Reset = 0x0
Type: RW
Name
Read_parity
Bit
Function
Reset
31-0
Bits 31:0 of the read parity
0x0
RS ECC read parity2
Address: 0x70
Reset = 0x0
Type: RW
Name
Bit
Function
Reset
SCP220x ICP Family, Rev.2.1
108
Freescale Semiconductor
Registers
Read_parity
31-0
Bits [63:32] of the read parity
Table 69. RS ECC read parity
0x0
RS ECC read parity3
Address: 0x74
Reset = 0x0
Type: RW
Name
Bit
Function
Reset
Reserved
31-8
7-0
Reserved
Bits [71:64] of the read parity
Read_parity
0x0
5.7.20 RS ECC write parity
These registers contain the 9 bytes of generated parity that are generated by the RS ECC engine after a 512 bytes
block is written to NAND flash. The 9 bytes can be read and then written to nand flash.
RS ECC write parity1
Address: 0x78
Name
Write_parity
Reset = 0x0
Type: RO
Bit
Function
Reset
31-0
Bits 31:0 of the write parity
0x0
RS ECC write parity2
Address: 0x7C
Reset = 0x0
Type: RO
Name
Bit
Function
Reset
Write_parity
31-0
Bits [63:32] of the write parity
0x0
Table 70. RS ECC write parity
RS ECC write parity3
Address: 0x80
Reset = 0x0
Function
Type: RO
Name
Bit
Reset
Reserved
31-8
7-0
Reserved
Bits [71:64] of the write parity
Write_parity
0x0
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
109
Registers
5.7.21 RS ECC Status
Table 71. RS ECC Status
Reset = 0x0
RS ECC Status
Address: 0x84
Type: RO
Name
Bit
Function
Reset
Reserved
31-2
1-0
Reserved
After the 512 byte read operation is completed and the
rs_ecc_read_status
0x0
“read_ecc_complete” interrupt is asserted, this field indicates the status of
the block read.
00 = no errors
01 = correctable errors
1x = uncorrectable errors
5.7.22 Transmit FIFO
The Transmit FIFO operates as a FIFO even though it has a range of addresses. The wider range allows bus bursting
to fill the FIFO.
Table 72. Transmit FIFO
Transmit FIFO
Address: 0x1000-0x1fff
Reset = 0x0
Type: WO
Name
Bit
Function
Reset
data
31-0
This field contains the data to be written to the FIFO. This register supports
8,16 or 32 bit writes and pushes the appropriate amount of data into the
FIFO.
0x0
5.7.23 Receive FIFO
The Receive FIFO operates as a FIFO even though it has a range of addresses. The wider range allows bus bursting
to drain the FIFO.
Table 73. Receive FIFO
Receive FIFO
Address: 0x2000-0x2fff
Reset = 0x0
Type: WO
Name
Bit
Function
Reset
data
31-0
This field contains the data to be read from the FIFO. This register supports
8,16 or 32 bit reads and pops the appropriate amount of data from the FIFO.
0x0
SCP220x ICP Family, Rev.2.1
110
Freescale Semiconductor
Registers
5.8
UART Control Registers
UART Register Description
5.8.1
Table 74. UART Register Map
Register Address Offset
Interrupt Source 0x00
Mode
RO
RW
WO
RW
RW
Interrupt Mask
Interrupt Clear
baud rate control
Configuration
fifo status
0x04
0x08
0x0C
0x10
0x14
RO/WO
RW
fifo flag Configuration
reserved
0x18
0x1C-0xfff
0x1000-0x1fff
0x2000-0x2fff
WO
transmit fifo
WO
receive fifo
RO
The register map is summarized below and described in the following sections.
5.8.2
Interrupt Source Register
Table 75. Interrupt Source Register
Interrupt Source Register
Address: 0x00
Name
Reset = 0x0
Type: RO
Bit
Function
Reset
Reserved
RTS_raw
CTS_raw
31-13
12
Reserved
This bit reflects the state of the RTS modem signal.
This bit reflects the state of the CTS modem signal.
0x0
0x0
0x0
11
rx_push_error
10
asserted when the receive fifo experiences an overrun condition or
mis-aligned access.This error is from the perspective of the external
interface.
parity_error
frame_error
9
8
asserted when the receive block detects a parity error
0x0
0x0
asserted when the receive block has detected a frame error (missing stop
bit(s))
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
111
Registers
Table 75. Interrupt Source Register
bus_pop_error
7
6
asserted when the transmit fifo experiences an underrun condition or
mis-aligned access.This error is from the perspective of the internal APB
bus.
0x0
0x0
bus_push_error
asserted when the receive fifo experiences an overrun condition or
mis-aligned access. A mis-aligned access can occur if the width of the write
has changed from a previous access. For example, if byte writes have
previously been used, the number of writes may be non-multiples of 32 bits.
If a 32 bit write now occurs, this is a misaligned access because the byte
pointers in the fifo are not pointing to byte ’0’. This error is from the
perspective of the internal APB bus.
rx_ff
5
4
asserted when the receive fifo has become full
0x0
0x0
rx_hf
asserted when the receive fifo level (amount of bytes in the fifo) has risen
above the software configured “half” empty level.
rx_fe
tx_ff
3
2
1
asserted when the receive fifo has become NOT empty
asserted when the transmit fifo has become NOT full
0x0
0x0
0x0
tx_hf
asserted when the transmit fifo level (amount of space available) has risen
above the software configured “half” full level.
tx_fe
0
asserted when the transmit fifo has become empty
0x0
The interrupt source register contains the raw unmasked interrupts and can be used for polling purposes (instead
of the external interrupt pin) or for determining which interrupt(s) have caused the external interrupt pin to assert.
5.8.3
Interrupt Mask Register
The interrupt mask register provides a mechanism to individually mask one or more of the interrupt sources.
Table 76. Interrupt Mask Register
Interrupt Mask Register
Address: 0x04
Name
Reset = 0x1FFF
Function
Type: RW
Bit
Reset
Reserved
RTS_raw
31-13
12
11
10
9
Reserved
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
0x1
0x1
0x1
0x1
0x1
0x1
0x1
CTS_raw
rx_push_error
parity_error
frame_error
bus_pop_error
bus_push_error
8
7
6
SCP220x ICP Family, Rev.2.1
112
Freescale Semiconductor
Registers
Table 76. Interrupt Mask Register
rx_ff
rx_hf
rx_fe
tx_ff
5
4
3
2
1
0
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
0x1
0x1
0x1
0x1
0x1
0x1
tx_hf
tx_fe
5.8.4
Interrupt clear Register
Table 77. Interrupt Clear Register
• Interrupt Clear Register
•
•
• Address: 0x08
• Name
• Reset = 0x0
• Type: WO
• Bit
• Function
Reserved
• Reset
Reserved
RTS_raw
CTS_raw
rx_push_error
parity_error
frame_error
bus_pop_error
bus_push_error
rx_ff
31-13
12
11
10
9
This interrupt can’t be cleared. It just reflects the state of the modem signal.
This interrupt can’t be cleared. It just reflects the state of the modem signal.
Clears the interrupt when written ‘1’.
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Clears the interrupt when written ‘1’.
8
Clears the interrupt when written ‘1’.
7
Clears the interrupt when written ‘1’.
6
Clears the interrupt when written ‘1’.
5
Clears the interrupt when written ‘1’.
rx_hf
4
Clears the interrupt when written ‘1’.
rx_fe
3
Clears the interrupt when written ‘1’.
tx_ff
2
Clears the interrupt when written ‘1’.
tx_hf
1
Clears the interrupt when written ‘1’.
tx_fe
0
Clears the interrupt when written ‘1’.
The interrupt clear register provides the mechanism for clearing the raw interrupt sources. Writing a „1. to the
interrupt bit location will clear the interrupt.
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
113
Registers
5.8.5
Baud Rate Control
Table 78. Baud Rate Control
Baud Rate Control
Address: 0x0C
Reset = 0x0
Function
Type: RW
Name
Bit
Reset
rx_baud_rate_div
tx_baud_rate_div
31-16
The interface reference clock is divided by this value to produce the baud rate
for the receive data. Minimum value is d16.
0x0
15-0
The interface reference clock is divided by this value to produce the baud rate
for the transmit data. Minimum value is d16. For IR mode, the
tx_baud_rate_div must be the same as the rx_baud_rate_div.
0x0
5.8.6
Configuration
Table 79. UART Configuration
Configuration
Address: 0x10
Reset = 0x14_0000
Function
Type: RW
Name
rts_fifo_level
Bit
Reset
31-24
This field sets the FIFO threshold as to when to de-assert the RTS modem
signal. It represents the amount of empty space in the fifo in bytes. If the fifo
goes below this amount of empty space, the RTS modem signal is
de-asserted.
0x0
Reserved
23
22
Reserved
enable_CTS
This field enables the use of the CTS signal. When enabled, the transmitter
will only send characters when this signal is asserted.
0 = modem signal not enable
0x0
0x0
1 = modem signal enabled
enable_RTS
rx_fifo_size
21
This field enables the use of the RTS signal. When enabled, the receiver will
assert/de-assert the signal depending on how much space is available in the
fifo. If the modem signal is not enabled it will remain de-asserted.
0 = modem signal not enable
1 = modem signal enabled
20-19
The receive fifo is an async fifo that supports 8,16,32 or 64 bit wide reads.
0x10
The fifo access size must be set prior to using the fifo. If the fifo size is
changed, the fifo must be flushed.
00 = 8 bits
01 = 16 bits
10 = 32 bits
11 = 64 bits
SCP220x ICP Family, Rev.2.1
114
Freescale Semiconductor
Registers
Table 79. UART Configuration
tx_fifo_size
18-17
The transmit fifo is an async fifo that supports 8,16,32 or 64 bit wide writes.
0x10
The fifo access size must be set prior to using the fifo. If the fifo size is
changed, the fifo must be flushed.
00 = 8 bits
01 = 16 bits
10 = 32 bits
11 = 64 bits
external_pad_ena
rx_sampling_pos
16
This bit enables the external transmit data pad. It must be enabled before
0x0
0x0
sending any data.
0 = pad disabled
1 = pad enabled
15-12
The rx_sampling_pos is internal sampling position in a bit and is usually set
to 7 when normal mode and 0 when IR mode.
Dn-1
Dn
Dn+1
15
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
0
1
RXGRIP_CNT = 7
ir_tx_polarity
ir_rx_polarity
ir_mode
10
9
IR TX polarity in IR mode
0 : Active High
1 : Active Low
0x0
0x0
0x0
IR RX polarity in IR mode
0 : Active High
1 : Active Low
8
When the ir_mode is enabled, signal format is followed by IR mode timing
diagram.
0 = normal mode
1 = IR mode
Bit
Pulse width = 3/16 Bit Time
Time
IR Tx
0
1
1
0
0
0
1
0
0
0/1
1
1
Parity
(Option)
Stop2
(Option)
Start D0
D1
D2
D3
D4
D5
D6
D7
Stop
IR mode TX timing diagram
IR Rx
IR_RxINV = 1
IR_RxINV = 0
0
1
1
0
0
0
1
0
0
0/1
1
1
Parity Stop2
Stop
Start D0
D1
D2
D3
D4
D5
D6
D7
(Option)
(Option)
IR mode RX timing diagram
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
115
Registers
Table 79. UART Configuration
echo
7
6
5
4
When the echo is enabled, the incoming receive data is received internally
but it is also looped back to the external transmit path.
0 = loopback disabled
0x0
0x0
0x0
0x0
1 = loopback enabled
remote_loop
local_loop
rx_endian
When a remote loopback is enabled, the incoming receive data is loopback
to the outgoing transmit data. The internal receive path is disabled.
0 = loopback disabled
1 = loopback enabled
When a local loopback is enabled, the transmit data is looped back to the
receive data. The transmit data is still transmitted externally.
0 = loopback disabled
1 = loopback enabled
This bit is used to modify the endianess of the data while it passes through
the receive fifo. Data is written to the fifo a byte at a time. If data is read from
the fifo 32 bits at a time, then an endianess swap can occur. LE data can be
changed to BE data on 32 bit boundaries.
0 = maintain endianess
1 = change LE data to BE data
tx_endian
3
This bit is used to modify the endianess of the data while it passes through
the transmit fifo. Data is read from the fifo a byte at a time. If data is written
to the fifo 32 bits at a time, then an endianess swap can occur. LE data can
be changed to BE data on 32 bit boundaries.
0x0
0 = maintain endianess
1 = change LE data to BE data
parity
2:1
This field indicates the parity type.
00 = even parity
01 = odd parity
10 = no parity
11 = reserved
0x0
0x0
stop_bits
0
This field indicates the number of stop bits.
0 = 1 stop bit
1 = 2 stop bits
5.8.7
FIFO Status
Table 80. FIFO Status
FIFO status
Address: 0x14
Reset = 0x40
Type: RO/WO
Name
Bit
Function
Reset
rx_flush
tx_flush
31
30
When this bit is written ‘1’, the receive fifo is flushed. This bit is a write only bit.
0x0
0x0
When this bit is written ‘1’, the transmit fifo is flushed. This bit is a write only
bit.
SCP220x ICP Family, Rev.2.1
116
Freescale Semiconductor
Registers
Table 80. FIFO Status
Reserved
29-16
15-8
Reserved
rx_byte_count
Indicates how many bytes of data is present in the receive fifo. This is a read
only field.
0x0
tx_byte_count
7-0
Indicates how many bytes of free space is available in the transmit fifo. This
is a read only field.
0x40
5.8.8
FIFO flag configuration
Table 81. FIFO Flag Configuration
FIFO flag Configuration
Address: 0x18
Reset = 0x4040
Function
Type: RW
Name
Bit
Reset
Reserved
31-16
15-8
Reserved
rx_half_empty
Sets the FIFO level (in bytes) that asserts the receive “half” empty flag. The
level setting is associated with how much data is in the FIFO. i.e if the setting
is 0x20, then when there is 0x20 bytes (or more) of data available in the FIFO,
the interrupt will be asserted.
0x40
tx_half_full
7-0
Sets the FIFO level (in bytes) that asserts the transmit “half” full flag. The
level setting is associated with how much space is available in the FIFO. i.e
if the setting is 0x20, then when there is 0x20 bytes (or more) of space
available in the FIFO, the interrupt will be asserted.
0x40
5.8.9
Transmit FIFO
The Transmit FIFO operates as a fifo even though it has a range of addresses. The wider range allows bus bursting
to fill the fifo.
Table 82. Transmit FIFO
Transmit FIFO
Address: 0x1000-0x1fff
Reset = 0x0
Type: WO
Name
Bit
Function
Reset
data
31-0
This field contains the data to be written to the fifo. This register supports 8,16
or 32 bit writes and pushes the appropriate amount of data into the fifo.
0x0
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
117
Registers
5.8.10 Receive FIFO
The Receive FIFO operates as a fifo even though it has a range of addresses. The wider range allows bus bursting
to drain the fifo.
Table 83. Receive FIFO
Receive FIFO
Address: 0x2000-0x2fff
Reset = 0x0
Type: WO
Name
Bit
Function
Reset
data
31-0
0x0
This field contains the data to be read from the fifo. This register
supports 8,16 or 32 bit reads and pops the appropriate amount of data
from the fifo.
5.9
SPI Registers
The register map is summarized below and described in the following sections.
Register Address Offset
Interrupt Source
Mode
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
RO
RW
WO
RW
RW
RW
RO
Interrupt Mask
Interrupt Clear
clock rate control
Configuration1
Configuration2
read_status
fifo status
RO/WO
RW
fifo flag Configuration
GPS Configuration
GPS Counter 1
GPS Counter 2
reserved
RW
RW
RO
0x30-0xfff
WO
WO
RO
transmit fifo
0x1000-0x1fff
0x2000-0x2fff
receive fifo
5.9.1
Interrupt Source Register
The interrupt source register contains the raw unmasked interrupts and can be used for polling purposes (instead
of the external interrupt pin) or for determining which interrupt(s) have caused the external interrupt pin to assert.
SCP220x ICP Family, Rev.2.1
118
Freescale Semiconductor
Registers
Interrupt Source Register
Address: 0x00
Name
Reset = 0x0
Type: RO
Bit
Function
Reset
Reserved
rxdata_fall
31-11
10
Reserved
This interrupt source is specific to a SPI application involving MMC cards.
When reading or writing blocks of data from an MMC card, there is a period
of time after the command has been issued before the card is ready to
issue or accept data. During this period the MMC card must be polled to
determine when it is ready for the block transaction. It will issue “FF” until
its ready and then it issues “FE”. This interrupt eases the software
overhead when looking for the “FE”. Software can let the FIFO fill and
instead of reading all the data out looking for the “FE” it can continue to
flush the fifo until this interrupt occurs.
0x0
tx_pop_error
rx_push_error
dma_pop_error
dma_push_error
9
8
7
6
asserted when the receive fifo experiences an overrun condition or
mis-aligned access.This error is from the perspective of the external
interface.
0x0
0x0
0x0
0x0
asserted when the transmit fifo experiences an underrun condition or
mis-aligned access.This error is from the perspective of the external
interface.
asserted when the transmit fifo experiences an underrun condition or
mis-aligned access.This error is from the perspective of the internal APB
bus.
asserted when the receive fifo experiences an overrun condition or
mis-aligned access. A mis-aligned access can occur if the width of the write
has changed from a previous access. For example, if byte writes have
previously been used, the number of writes may be non-multiples of 32 bits.
If a 32 bit write now occurs, this is a misaligned access because the byte
pointers in the fifo are not pointing to byte ’0’. This error is from the
perspective of the internal APB bus.
rx_ff
5
4
asserted when the receive fifo has become full
0x0
0x0
rx_hf
asserted when the receive fifo level is above the software configured “half”
empty level.
rx_fe
tx_ff
3
2
1
asserted when the receive fifo has become NOT empty
asserted when the transmit fifo has become NOT full
0x0
0x0
0x0
tx_hf
asserted when the transmit fifo level is below the software configured “half”
full level.
tx_fe
0
asserted when the transmit fifo has become empty
0x0
5.9.2
Interrupt Mask Register
The interrupt mask register provides a mechanism to individually mask one or more of the interrupt sources.
Interrupt Mask Register
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
119
Registers
Address: 0x04
Reset = 0x7FF
Type: RW
Name
Bit
Function
Reset
Reserved
rxdata_fall
tx_pop_error
rx_push_error
dma_pop_error
dma_push_error
rx_ff
31-11
Reserved
10
9
8
7
6
5
4
3
2
1
0
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
rx_hf
rx_fe
tx_ff
tx_hf
tx_fe
5.9.3
Interrupt Clear Register
The interrupt clear register provides the mechanism for clearing the raw interrupt sources. Writing a „1. to the
interrupt bit location will clear the interrupt.
Interrupt Clear Register
Address: 0x08
Name
Reset = 0x0
Type: WO
Bit
Function
Reset
Reserved
rxdata_fall
tx_pop_error
rx_push_error
dma_pop_error
dma_push_error
rx_ff
31-11
Reserved
10
9
8
7
6
5
4
3
2
1
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
rx_hf
rx_fe
tx_ff
tx_hf
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Freescale Semiconductor
Registers
tx_fe
0
Clears the interrupt when written ‘1’.
0x0
5.9.4
Clock Rate Control
Clock Rate Control
Address: 0x0C
Reset = 0x2
Type: RW
Name
Bit
31-0
Function
Reset
clock_div
The interface PLL clock is divided by this value to produce the clock rate for
the external SPI clock. This register is only applicable for master mode of
operation. Values of “0” or “1” are invalid.
0x2
5.9.5
Configuration1
Configuration1
Address: 0x10
Reset = 0x108100
Type: RW
Name
Bit
Function
Reset
Reserved
31
Reserved
device_select
30-29
When the SPI interface is configured as a master it can support up to four
0x0
slave devices. Only one slave device at a time can be accessed, but muxing
control allows communication with four different devices (there are 4 chip
selects and 4 receive data, the clock and transmit data is common for all 4
devices). This field controls the muxing logic.
0 = device 0
1 = device 1
2 = device 2
3 = device 3
spi_clkgen_disable
transaction_cnt
28
This field disables the SPI clock generator. Slave applications do not require
the clock generator so it is recommended that this be disabled to minimize
power.
0 = SPI clock generator enabled
1 = SPI clock generator disabled
0x0
0x1
27-20
This field dictates the number of transactions that occur during a chip select
assertion for fixed length transactions. The transactions are of a length
defined by the "length" field. This field is intended to allow for continuous
streams of data. Operation does not begin until the data is in the fifo. Care
should be taken in how the fifo is filled. The fifo should be filled with
increments (8,16 or 32) that is equal or greater than the “length” field for the
SPI transaction.
This field is only applicable to master mode of operation. Continuos mode is
also supported in slave mode but the chip select duration is controlled
externally.
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
121
Registers
var_length_start
19
This field is used in conjunction with the var_length_ena field. When “1”, the
SPI serial stream will begin once data is in the fifo. The fifo should be filled
with increments (8,16 or 32) that is equal or greater than the “length” field for
the SPI transaction. The stream will continue as long as data is in the fifo and
as long as this bit is asserted.
0x0
Writing a “0” to this field will de-activate the chip select and stop the serial
stream. The fifo should be empty when this mode is stopped.
var_length_ena
length
18
When “1”, the variable length continuos stream mode is enabled. This is very
similar to the mode enabled by the transaction_cnt field except the start and
end are controlled by the toggling the var_length_start field.
0x0
0x8
17-12
This field dictates the number of bits that are transmitted per transaction on
the SPI interface. Valid values range from d3-d32.
If the length is not 8,16 or 32 the following characteristics apply.
When the de-serialized data is pushed into the fifo it is padded with “0” to
align with 8,16 or 32 bits.
When data is being serialized and transmitted, data is popped out of the fifo
as an 8,16 or 32 bit word and the extra bits up to the 8,16 or 32 bit boundary
are dropped.
Reserved
tx_dis
11-9
8
Reserved
transmit datapath disable. Since the SPI interface transmits data coincidently
with the reception of data, this bit provides some flexibility to software. If the
application is only reading and transmit data is non-exisitant, the receive path
can be disabled. This will prevent the transmit fifo from underrunning.
0=transmit datapath enable
0x1
0x0
0x0
1=transmit datapath disable.
rx_endian
tx_endian
7
6
This bit is used to modify the endianess of the data while it passes through
the receive fifo. Data is written to the fifo a byte at a time. If data is read from
the fifo 32 bits at a time, then an endianess swap can occur. LE data can be
changed to BE data on 32 bit boundaries.
0 = maintain endianess
1 = change LE data to BE data
This bit is used to modify the endianess of the data while it passes through
the transmit fifo. Data is read from the fifo a byte at a time. If data is written
to the fifo 32 bits at a time, then an endianess swap can occur. LE data can
be changed to BE data on 32 bit boundaries.
0 = maintain endianess
1 = change LE data to BE data
LSB_first
loopback
5
4
Depending on the setting, the LSB or MSB of the transaction will be
transmitted or received first.
0=MSB first
0x0
0x0
1=LSB first
When loopback is enabled, the transmit data is looped back into the receive
data path.
0=no loopback
1=loopback
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Freescale Semiconductor
Registers
rx_dis
3
Receive datapath disable. Since the SPI interface receives data coincidently
with the transmission of data, this bit provides some flexibility to software. If
the application is only writing and receive data is non-exisitant, the receive
path can be disabled. This will prevent the receive fifo from filling up with
garbage. Alternatively, the receive path can remain enabled and the receive
fifo can be flushed.
0x0
0=receive datapath enable
1=receive datapath disable
ms
2
1
master/slave select. This bit configures the interface as a slave or a master.
0=slave mode
1=master mode
0x0
0x0
spo
This field sets the inactive clock polarity. Inactivity is associated with the chip
select being de-asserted.
0 = clock low during inactivity
1 = clock high during inactivity
sph
0
This field sets the SPI clock phase.
0x0
0 = transmit on falling edge, receive on rising edge
1 = transmit on rising edge, receive on falling edge
5.9.6
Configuration2
This register is used to enable a burst of "reads" on the SPI interface. It is only applicable to the master mode of
operation.
Configuration2
Address: 0x14
Reset = 0x0
Type: RW
Name
Bit
Function
Reset
ena
31
This bit acts as a kickoff. When written ’1’ the SPI will perform the number of
transactions specified in the read_length field and write the received data to
the receive fifo. This bit is self clearing.
0x0
Reserved
30-16
15-0
Reserved
read_length
These bits dictate the number of transactions that will occur. The transaction
width is dictated by the length field in Configuration1.
0x0
5.9.7
Read Status
Read Status
Address: 0x18
Reset = 0x0
Type: RO
Name
Bit
Function
Reset
Reserved
31-16
Reserved
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
123
Registers
read_length
15-0
This field is pertinent only if burst read transactions have been configured
and enabled via the Configuration2 register.
0x0
When this field is read, it will reflect the current decremented value of the
read transaction counter.
5.9.8
FIFO Status
FIFO status
Address: 0x1C
Reset = 0x80
Type: RO/WO
Name
Bit
Function
Reset
rx_flush
31
When this bit is written ‘1’, the receive fifo is flushed.
This bit is a write only bit.
0x0
tx_flush
30
When this bit is written ‘1’, the transmit fifo is flushed.
This bit is a write only bit.
0x0
Reserved
29-16
15-8
Reserved
rx_byte_count
Indicates how many bytes of data is present in the receive fifo.
This is a read only field.
0x0
tx_byte_count
7-0
Indicates how many bytes of free space is available in the transmit fifo.
This is a read only field.
0x80
5.9.9
FIFO Flag Configuration
FIFO flag Configuration
Address: 0x20
Reset = 0x28_4040
Type: RW
Name
Bit
Function
Reset
Reserved
31-22
21-20
Reserved
rx_fifo_size
tx_fifo_size
Reserved
The receive fifo is an async fifo that supports 8,16,32 or 64 bit wide reads.
The fifo access size must be set prior to using the fifo. If the fifo size is
changed, the fifo must be flushed.
00 = 8 bits
01 = 16 bits
0x10
10 = 32 bits
11 = 64 bits
19-18
17-16
The transmit fifo is an async fifo that supports 8,16,32 or 64 bit wide writes.
The fifo access size must be set prior to using the fifo. If the fifo size is
changed, the fifo must be flushed.
00 = 8 bits
01 = 16 bits
0x10
10 = 32 bits
11 = 64 bits
Reserved
SCP220x ICP Family, Rev.2.1
124
Freescale Semiconductor
Registers
rx_half_empty
tx_half_full
15-8
7-0
Sets the FIFO level (in bytes) that asserts the receive “half” empty flag. The
level setting is associated with how much data is in the FIFO. i.e if the setting
is 0x20, then when there is 0x20 bytes of data available in the FIFO, the
interrupt will be asserted.
0x40
Sets the FIFO level (in bytes) that asserts the transmit “half” full flag. The
level setting is associated with how much space is available in the FIFO. i.e
if the setting is 0x20, then when there is 0x20 bytes of space available in the
FIFO, the interrupt will be asserted.
0x40
5.9.10 GPS Configuration and Control
The SPI block has an embedded alternate GPS function that stores data from a GPS source into the receive fifo.
When this mode is enabled the SPI function can no longer use the receive fifo (the transmit fifo is still available for
SPI transmit functions). The GPS interface is a very simple serial interface as shown below:
Error! Objects cannot be created from editing field codes.
The Data format stored in the FIFO is software configurable and can be one of the following:
Error! Objects cannot be created from editing field codes.
GPS Configuration
Address: 0x24
Name
Reset = 0x0
Type: RW
Bit
Function
Reset
Reserved
31-6
5
Reserved
enter_track_mode
During tracking mode, continuous data acquisition is not required. Instead,
just the number of samples needs to be stored.
0 – normal acquisition mode (all data is sent to the fifo)
1 – tracking mode (data is no longer stored but a sample counter is
incremented).
0x0
invert_clk
mode
4
3
This field will invert the clock before it is used by the internal hardware.
0 – no inversion
1 – gps_clk is inverted
0x0
0x0
0x0
Indicates how many magnitude bits are associated with the interface.
0 – 1 magnitude bit
1 – 3 magnitude bits
format
2-1
Sets the serialization format as illustrated above.
00 – unpacked
01 – packed
10 – super packed
11 - reserved
enable_gps
0
As soon as this mode is enabled, any activity on the GPS interface is
0x0
de-serialized and pushed into the receive fifo.
0 – disabled
1 - enabled
GPS Counter 1
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
125
Registers
Address: 0x28
Reset = 0x0
Type: RW
Name
Bit
Function
Reset
switch_over_cnt
31-0
This register is used to set the start value of a count down register. The count
down register is used when switching from acquisition mode to tracking
mode. It’s count is used to synchronize when the switch over from storing
data to just counting samples (data is thrown away) occurs. Usually it will
lineup with a completed DMA transaction.
0x0
If enter_track_mode is set, and the count down register is “0” data will no
longer be stored in the fifo. Instead the sample_cnt will be incremented.
When enter_track_mode is cleared, the data is once again stored in the fifo
and the down counter starts decrementing from its programmed start value.
GPS Counter 2
Address: 0x2C
Reset = 0x0
Type: RO
Name
Bit
Function
Reset
sample_cnt
31-0
This field contains the current sample count when the GPS is in the tracking
mode of operation.
0x0
It is cleared when the following event occurs – the enter_track_mode is set
and the count down register is “0”.
When enter_track_mode becomes “0”, the sample_cnt holds its current
value.
The following sequence is a typical use of the GPS registers.
•
Initially the acquisition mode is entered. The GPS interface is enabled and the data is moved by the mc-dma
to a storage buffer. The switch_over_cnt is programmed with a sample number that matches the chunk size
that the mc-dma is programmed with.
•
After acquisition, the tracking mode is entered. During this mode, most of the data is not required but the
number of samples that have been received needs to be saved. To enter this mode, the “enter_track_mode”
field is asserted. When this is asserted, the hardware will wait until the down counter expires (so that a
known amount of data is received) and then just counts the number of samples that occur. The incoming
data is discarded.
•
When additional data samples are required, the “enter_track_mode” field is de-asserted. This will re-enable
the data path to the fifo and hold the sample count until the next time the tracking mode is entered.
5.9.11 Transmit FIFO
The Transmit FIFO operates as a fifo even though it has a range of addresses. The wider range allows bus bursting
to fill the fifo.
Transmit FIFO
Address: 0x1000-0x1fff
Name
Reset = 0x0
Type: WO
Bit
Function
Reset
SCP220x ICP Family, Rev.2.1
126
Freescale Semiconductor
Registers
data
31-0
This field contains the data to be written to the fifo. This register supports 8,16
or 32 bit writes and pushes the appropriate amount of data into the fifo. The
size of the access must match the size that is programmed into the
tx_fifo_size field in the Configuration1 register.
0x0
5.9.12 Receive FIFO
The Receive FIFO operates as a fifo even though it has a range of addresses. The wider range allows bus bursting
to drain the fifo.
Receive FIFO
Address: 0x2000-0x2fff
Name
Reset = 0x0
Type: WO
Bit
31-0
Function
Reset
data
This field contains the data to be read from the fifo. This register supports
8,16 or 32 bit reads and pops the appropriate amount of data from the fifo.
The size of the access must match the size that is programmed into the
rx_fifo_size field in the Configuration1 register.
0x0
5.10 Audio Registers
The Audio register map is summarized below and described in the following sections. All register support 32 bit
accesses only. The FIFOs are the exception and they support 8,16 or 32 bit accesses.
Register
Address Offset
0x00
Mode
Interrupt Source
Interrupt Mask
Interrupt Clear
RO
RW
WO
RW
RW
RW
RW
RW
RW
RO
RW
RO
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
0x38
0x3c-0xfff
Interface Configuration
Bit Clock Configuration
Receive Frame Clock Configuration
Transmit Frame Clock Configuration
AC97 Configuration
AC97 Command
AC97 Status
AC97 Modem Control
AC97 Modem Status
fifo status
RO/WO
RW
fifo flag Configuration
NCO Configuration
reserved
RW
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
127
Registers
tx fifo
rx fifo
0x1000-0x1fff
0x2000-0x2fff
WO
RO
5.10.1 Interrupt Source Register
The interrupt source register contains the raw unmasked interrupts and can be used for polling purposes (instead
of the external interrupt pin) or for determining which interrupt(s) have caused the external interrupt pin to assert.
Interrupt Source Register
Address: 0x00
Name
Reset = 0x2
Type: RO
Bit
Function
Reset
Reserved
31-14
13
Reserved
modem_status
This interrupt is only applicable for the AC97 mode of operation. It is
asserted after the modem status field is valid.
0x0
0x0
cmd_read_complete
12
This interrupt is only applicable for the AC97 mode of operation. It is
asserted after a requested read command (slot 1 & 2) has completed and
valid data is now available in the AC97 status register.
cmd_write_complete
codec_ready
11
10
This interrupt is only applicable for the AC97 mode of operation. It is
asserted after a requested write command (slot 1 & 2) has completed.
0x0
0x0
This interrupt is only applicable for the AC97 mode of operation. It is
asserted when the “codec ready” bit in the incoming TAG channel has
transitioned from “0” to “1” indicating that the codec is now ready for
operation.
tx_pop_error
rx_push_error
bus_pop_error
bus_push_error
9
8
7
6
asserted when the receive fifo experiences an overrun condition or
mis-aligned access.This error is from the perspective of the external
interface.
0x0
0x0
0x0
0x0
asserted when the transmit fifo experiences an underrun condition or
mis-aligned access.This error is from the perspective of the external
interface.
asserted when the receive fifo experiences an underrun condition or
mis-aligned access.This error is from the perspective of the internal APB
bus.
asserted when the transmit fifo experiences an overrun condition or
mis-aligned access. A mis-aligned access can occur if the width of the
write has changed from a previous access. For example, if byte writes
have previously been used, the number of writes may be non-multiples of
32 bits. If a 32 bit write now occurs, this is a misaligned access because
the byte pointers in the fifo are not pointing to byte ’0’. This error is from
the perspective of the internal APB bus.
rx_ff
5
4
asserted when the receive fifo has become full
0x0
0x0
rx_hf
asserted when the receive fifo level has risen above the software
configured “half” empty level.
rx_fe
3
asserted when the receive fifo has become NOT empty
0x0
SCP220x ICP Family, Rev.2.1
128
Freescale Semiconductor
Registers
tx_ff
2
1
asserted when the transmit fifo has become NOT full
0x0
0x0
tx_hf
asserted when the transmit fifo level has dropped below the software
configured “half” full level.
tx_fe
0
asserted when the transmit fifo has become empty
0x0
5.10.2 Interrupt Mask Register
The interrupt mask register provides a mechanism to individually mask one or more of the interrupt sources.
Interrupt Mask Register
Address: 0x04
Name
Reset = 0xFFFF_FFFF
Type: RW
Bit
Function
Reset
Reserved
modem_status
cmd_read_complete
cmd_write_complete
codec_ready
tx_pop_error
rx_push_error
bus_pop_error
bus_push_error
rx_ff
31-14
13
12
11
10
9
Reserved
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
8
7
6
5
rx_hf
4
rx_fe
3
tx_ff
2
tx_hf
1
tx_fe
0
5.10.3 Interrupt Clear Register
The interrupt clear register provides the mechanism for clearing the raw interrupt sources. Writing a „1. to the
interrupt bit location will clear the interrupt.
Interrupt Clear Register
Address: 0x08
Name
Reset = 0x0
Type: WO
Bit
Function
Reset
31-14
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
129
Registers
modem_status
13
12
11
10
9
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
cmd_read_complete
cmd_write_complete
codec_ready
tx_pop_error
rx_push_error
bus_pop_error
bus_push_error
rx_ff
8
7
6
5
rx_hf
4
rx_fe
3
tx_ff
2
tx_hf
1
tx_fe
0
5.10.4 Interface Configuration
Interface Configuration
Address: 0x0C
Reset = 0x8080_0000
Type: RW
Name
Bit
Function
Reset
tx_fifo_size
31-30
The transmit fifo is an async fifo that supports 8,16,32 or 64 bit wide writes.
0x2
The fifo access size must be set prior to using the fifo. If the fifo size is
changed, the fifo must first be flushed.
00 = 8 bits
01 = 16 bits
10 = 32 bits
11 = 64 bits
rxd_word_length
rx_fifo_size
29-24
23-22
Number of bits de-serialized in each active channel on the receive interface.
Maximum value is 32 for the I2S mode of operation and 20 bits for the AC97
mode of operation. If this field has been changed after the fifos have been
used, the fifo must be flushed for proper operation.
0x0
0x2
The receive fifo is an async fifo that supports 8,16,32 or 64 bit wide reads.
The fifo access size must be set prior to using the fifo. If the fifo size is
changed, the fifo must first be flushed.
00 = 8 bits
01 = 16 bits
10 = 32 bits
11 = 64 bits
SCP220x ICP Family, Rev.2.1
130
Freescale Semiconductor
Registers
txd_word_length
rx_stereo
21-16
15
Number of bits serialized in each active channel on the transmit interface.
Maximum value is 32 for the I2S mode of operation and 20 bits for the AC97
mode of operation. If this field has been changed after the fifos have been
used, the fifo must be flushed for proper operation.
0x0
This field enables whether or not the stereo mode is enabled for the receive
path. When the stereo mode is enabled the frame is organized as a left and
right channel where one channel is transmitted during the first half of frame
period and the second channel is transmitted during the second half of the
frame period. This setting is only applicable when the interface operates in
the I2S mode.
0x0
0 = mono operation (single channel)
1 = stereo operation (two channels)
loop_back
14
13
When “1” the transmit data is looped back to the receive data.
0x0
0x0
common_sync
The audio interface can utilize a common frame synchronization signal for
both the transmit and receive datapath or can use separate synchronization
signals. If a common synchronization signal is selected, then the bit clocks
must also be configured as common. The transmit frame signal (fsx) is used
if common_sync is enabled
1 = receive frame sync is shared with the transmit.
0 = receive frame sync is separate and unique from the transmit.
rx_bitclk_src
fsx_polarity
12
11
The receive interface can operate with its own bit clock or it can share the
transmit bit clock. For applications that have a single bit clock, the receive bit
clock must be shared with the transmit bit clock. When the receive and
transmit share a bit clock, that bit clock is the transmit bit clock.
0 = receive bit clock is shared with the transmit.
0x0
0x0
1 = receive bit clock is separate and unique from the transmit.
This bit sets the polarity of the transmit frame clock. If the external device
sources the frame sync, this bit should be set such that the asic receives an
active high frame sync.
0 = internally generated frame sync is active high or external frame sync is
NOT inverted.
1 = internally generated frame sync is active low or external frame sync is
inverted.
fsr_polarity
10
This bit sets the polarity of the receive frame clock. . If the external device
sources the frame sync, this bit should be set such that the asic receives an
active high frame sync.
0x0
0 = internally generated frame sync is active high or external frame sync is
NOT inverted.
1 = internally generated frame sync is active low or external frame sync is
inverted.
clkx_polarity
clkr_polarity
9
8
This bit is used to determine which edge of the bit clock is used to transition
the transmit data and frame signal.
0 = transmit signaling transitions on the rising edge of the bit clock.
1 = transmit signaling transitions on the falling edge of the bit clock.
0x0
0x0
This bit is used to determine which edge of the bit clock is used to transition
the frame signal and sample the receive data.
0 = receive signaling transitions/sampled on the rising edge of the bit clock.
1 = receive signaling transitions/sampled on the falling edge of the bit clock.
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
131
Registers
fsx_src
7
6
5
4
3
This bit reflects whether or not the asic sources the frame synchronization or
whether the codec is the source.
0 = pad is disabled and an external device sources the frame sync.
1 = pad is enabled and the asic sources the frame sync. Prior to enabling the
frame sync timing must be properly setup.
0x0
0x0
0x0
fsr_src
clkx_src
This bit reflects whether or not the asic sources the frame synchronization or
whether the codec is the source.
0 = pad is disabled and an external device sources the frame sync.
1 = pad is enabled and the asic sources the frame sync. Prior to enabling the
frame sync timing must be properly setup.
This bit reflects whether or not the asic sources the bit clock or whether the
codec is the source.
0 = pad is disabled and an external device sources the bit clock
1 = pad is enabled and the asic sources the bit clock. Prior to enabling the bit
clock timing must be properly setup.
clkr_src
This bit reflects whether or not the asic sources the bit clock or whether the
codec is the source.
0 = pad is disabled and an external device sources the bit clock
1 = pad is enabled and the asic sources the bit clock. Prior to enabling the bit
clock timing must be properly setup.
ena_transmit
This bit enables the datapath for the transmit direction. This allows the sync
and bit clocks to be setup and enabled prior to having a datapath enabled in
the transmit direction. The transmit data will be tri-stated until this bit is set
and then data will be popped from the fifo and serialized.
0 = transmit datapath is disabled
0x0
0x0
0x0
1 = transmit datapath is enabled
ena_receive
tx_stereo
2
1
This bit enables the datapath for the receive direction. This allows the sync
and bit clocks to be setup and enabled prior to having a datapath enabled in
the receive direction. The receive data is ignored until this bit is set and then
data will be de-serialized and pushed into the fifo.
0 = receive datapath is disabled
1 = receive datapath is enabled
This field enables whether or not the stereo mode is enabled for the transmit
path. When the stereo mode is enabled the frame is organized as a left and
right channel where one channel is transmitted during the first half of frame
period and the second channel is transmitted during the second half of the
frame period. This setting is only applicable when the interface operates in
the I2S mode.
0 = mono operation (single channel)
1 = stereo operation (two channels)
mode
0
This field indicates to the hardware which mode of operation the interface will
0x0
operate.
0 = I2S mode of operation
1 = AC97 mode of operation
The interface configuration register allows pretty much any possible configuration of external signals and sources of
these signals. The following table provides some typical example settings.
Mode of
operation
mclk
fsx
clkx
fsr
clkr
SCP220x ICP Family, Rev.2.1
132
Freescale Semiconductor
Registers
I2S master
I2S slave
18.432 Mhz
Not used
ASIC sourced
Codec sourced
ASIC sourced
ASIC sourced
ASIC sourced
Codec sourced
ASIC sourced
Codec sourced
optional
optional
Not used
Not used
optional
optional
Not used
Not used
AC97 master
AC97 slave
24.576 Mhz
Not used
5.10.5 Bit clock Configuration
Bit Clock Configuration
Address: 0x10
Reset = 0x0
Type: RW
Name
Bit
Function
Reset
rx_clk_div
31-16
This field contains the divider value applied to the master audio clock (mclk)
to produce the receive bit clock (clkr). Values of 2 or greater are valid. This
field is only applicable when the receive clock source is the asic as
0x0
configured in the interface configuration register. The resultant clock will have
a 50% duty cycle for even divides and a non-50% duty cycle for odd divides.
tx_clk_div
15-0
This field contains the divider value applied to the master audio clock (mclk)
to produce the transmit bit clock (clkx). Values of 2 or greater are valid. This
field is only applicable when the transmit clock source is the asic as
configured in the interface configuration register. The resultant clock will have
a 50% duty cycle for even divides and a non-50% duty cycle for odd divides.
0x0
5.10.6 Receive Frame Clock Configuration
Receive Frame Clock Configuration
Address: 0x14
Name
Reset = 0x0
Type: RW
Bit
Function
Reset
Reserved
rx_dly
31
Reserved
0x0
0x0
30-24
This field provides the capability to delay the first bit period of valid data from
the assertion of the receive frame clock. This field contains the number of
receive bit clocks from the active edge of the frame clock to the first valid bit
of received data.
rx_frame_width
rx_frame_period
23-16
15-0
This field controls the active width of the receive frame clock. The field
represents the number of receive bit clocks and has a minimum value of 1.
0x0
0x0
This field contains the divider value applied to the receive bit clock to produce
the receive frame clock. Values of 2 or greater are valid.
5.10.7 Transmit Frame Clock Configuration
Transmit Frame Clock Configuration
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
133
Registers
Address: 0x18
Reset = 0x0
Type: RW
Name
Bit
Function
Reset
Reserved
tx_dly
31
Reserved
0x0
0x0
30-24
This field provides the capability to delay the first bit period of valid data from
the assertion of the transmit frame clock. This field contains the number of
transmit bit clocks from the active edge of the frame clock to the first valid bit
of transmitted data.
tx_frame_width
tx_frame_period
23-16
15-0
This field controls the active width of the transmit frame clock. The field
represents the number of transmit bit clocks and has a minimum value of 1.
0x0
0x0
This field contains the divider value applied to the transmit bit clock to produce
the transmit frame clock. Values of 2 or greater are valid.
5.10.8 C97 Configuration
AC97 Configuration
Address: 0x1C
Name
Reset = 0x0
Type: RW
Bit
Function
Reset
Reserved
codec_id
31-16
15-14
Reserved
0x0
0x0
This field contains the codec ID that will be transmitted during slot 0. Multiple
codecs are not supported so the ID will probably always be ‘0’ for a primary
codec. The field has been made configurable just in case the flexibility is
required.
warm_reset
13
Writing a ‘1’ to this bit will initiate a “warm” reset on the AC-link interface. This
should only be initiated if the codec is in the power-down mode. This bit will
cause the hardware to assert the sync signal for 1µsec initiating a warm reset
within the codec. The bit is self resetting after the reset activity is complete.
Prior to writing to this bit initiate a warm reset, the codec_pdown bit must be
cleared in the AC97 command register.
0x0
0 = no action
1 = hardware initiates a warm reset
tx_slot_ena
Reserved
12 -3
2-1
Enables the transmit channel for slots 3 to 12. If variable sampling rates are
enabled, this bit is ignored and the slot enable information is obtained from
the received TAG slot information.
0 = disable slot
1 = enable slot
0x0
0x0
Reserved
SCP220x ICP Family, Rev.2.1
134
Freescale Semiconductor
Registers
variable_rate_ena
0
An AC97 frame is based on a 48 Khz period. If the application is using a 48
Khz sampling rate, this bit should remain disabled and the enabled channels
will be transmitted/received in every frame. If the application is utilizing a
non-48 Khz period and the codec supports variable sampling rates, then this
bit should be set. When this bit is set, the hardware looks at the channel
request bits in the received TAG channel. When the channel request bits
match the enabled slots as configured in tx_slot_ena, the channels that are
requesting data are sent data. The hardware assumes that the data in the fifo
matches the channel requests (i.e. the hardware assumes that the requests
will maintain their channel order). Data is not sent until all channels are
requesting so that the channel order within the frame is maintained.
0x0
5.10.9 AC97 Command
This register provides the mechanism for read and writing the command registers in the codec. This operation
occurs in slot 1 and 2 during the AC97 frame. If a command write or status read are initiated, they will occur during
the next AC97 frame. Status and interrupt information is provided to indicate the completion of the command write
or the availability of the status information.
AC97 Command
Address: 0x20
Name
Reset = 0x0
Type: RW
Bit
Function
Reset
Reserved
31-26
25
Reserved
0x0
0x0
codec_pdown
The Codec can be placed in a power down state by writing to its power down
register. This operation is accomplished the same as any other register write
but the hardware needs to know that this register is being written to power
down the codec. If this is the case, all outputs are zeroed after slot 2 has been
transmitted. The codec is removed from this state by issuing a warm reset.
This bit must be cleared prior to requesting a warm reset.
0 = no action
1 = interface activity ends after valid slot 2 data has been sent.
control_reg_ena
24
To enable activity in slot 1 and 2, this bit must be set. Once the bit is set, when
the next frame occurs address and write data (if applicable) is serialized out in
the next frame. This bit is self resetting once this action occurs. The address
and write data must be valid when this bit is set.
0x0
0 = no action
1 = enable slot 1 or 2 (iff applicable) during the next frame.
write_data
read_write
23-8
7
This field contains the write data if the register access is a write. This field is
serialized out during slot 2 (command data port) if read_write=0.
0x0
0x0
This is the read/write bit that is serialized out in the read/write command bit
field of slot 1 (command address port).
0 = write
1 = read
control_reg_index
6-0
When enabled, this field will be serialized out in the address field of slot 1
(command address port). It is the address within the codec of the register
being written or read.
0x0
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
135
Registers
5.10.10 AC97 Status
AC97 Status
Address: 0x24
Reset = 0x0
Type: RO
Name
Bit
Function
Reset
Reserved
31-25
24
Reserved
0x0
0x0
codec_ready
This bit reflects the status of the “Codec Ready” bit in the slot 0 TAG
information for the most recently received frame. The codec is not ready for
operation until this bit gets set. The condition is normal following the
de-assertion of power on reset.
read_data_valid
23
This bit is asserted if the read_data is valid. The bit is self clearing when a
new codec register read is requested (as configured in the AC97 command
register). It is re-asserted once the codec has returned valid data.
0 = read_data is invalid
0x0
1 = read_data is valid
echoed_index
read_data
22-16
15-0
This is the register index that has been echoed back by the codec and
reflects the register address that was read.
0x0
0x0
This field contains the last valid read data from a register access. Data is valid
as long as the read_data_valid flag is set.
5.10.11 AC97 Modem Control
This register provides the mechanism for writing to slot 12 when the slot operates as the Modem GPIO control
channel.
AC97 Modem Control
Address: 0x28
Name
Reset = 0x0
Type: RW
Bit
Function
Reset
Reserved
31-21
20
Reserved
0x0
0x0
modem_ena
To enable activity in slot 12 (for modem control purposes), this bit must be
set. Once the bit is set, when the next frame occurs the modem_control field
is serialized out in the next frame. This bit is self resetting once this action
occurs. . The modem control data must be valid when this bit is set.
0 = no action
1 = enable slot 12 during the next frame.
modem_control
19-0
When enabled, this field will be serialized out in slot 12.
0x0
5.10.12 AC97 Modem Status
AC97 Modem Status
Address: 0x2C
Reset = 0x0
Type: RO
SCP220x ICP Family, Rev.2.1
136
Freescale Semiconductor
Registers
Reset
Name
Bit
Function
Reserved
31-20
19-0
Reserved
0x0
0x0
modem_control
This field contains the last valid modem GPIO status from slot 12. An
interrupt is raised when the data has been updated.
5.10.13 FIFO Status
FIFO status1
Address: 0x30
Reset = 0x80
Type: RO/WO
Name
Bit
Function
Reset
rx_flush
31
When this bit is written ‘1’, the receive fifo is flushed. This bit is a write only
self clearing bit.
0x0
tx_flush
30
When this bit is written ‘1’, the transmit fifo is flushed. This bit is a write only
self clearing bit.
0x0
Reserved
29-16
15-8
Reserved
0x0
0x0
rx_byte_count
Indicates how many bytes of data is present in the receive fifo. This is a read
only field.
tx_byte_count
7-0
Indicates how many bytes of free space is available in the transmit fifo. This
is a read only field.
0x80
5.10.14 FIFO Flag Configuration
FIFO flag Configuration
Address: 0x34
Name
Reset = 0x4040
Type: RW
Bit
Function
Reset
Reserved
31-16
15-8
Reserved
rx_half_empty
Sets the FIFO level (in bytes) that asserts the receive “half” empty flag. The
level setting is associated with how much data is in the FIFO. i.e if the setting
is 0x20, then when there is 0x20 bytes of data available in the FIFO, the
interrupt will be asserted.
0x40
tx_half_full
7-0
Sets the FIFO level (in bytes) that asserts the transmit “half” full flag. The
level setting is associated with how much data is in the FIFO. i.e if the setting
is 0x20, then when there is 0x20 bytes of data available in the FIFO, the
interrupt will be asserted.
0x40
5.10.15 NCO Configuration
NCO Configuration
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
137
Registers
Address: 0x38
Reset = 0x0
Type: RW
Name
Bit
Function
Reset
audio_nco_enable
31
Enables the NCO as the source of MCLK. Also enables the MCLK PAD to
drive out the NCO derived clock.
0x0
Reserved
30-20
19-0
Reserved
audio_nco_value
NCO value.
0x0
NCO value = round ((2^21 x mclk_freq) / SYS_freq)
5.11 MMC/SD Control Registers
The register map is summarized below and described in the following sections.
Register
Interrupt Source
Address Offset
0x00
Mode
RO
RW
WO
RW
RW
RW
RW
RW
RO
RO
Interrupt Mask
0x04
Interrupt Clear
0x08
MMC/SD clock rate
MMC/SD Configuration
MMC/SD Data Control
MMC/SD argument
MMC/SD command
MMC/SD command response
MMC/SD response
fifo status
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24-0x30
0x34
RO/WO
RW
fifo flag Configuration
reserved
0x38
0x3C-0xfff
0x1000-0x1fff
0x2000-0x2fff
transmit fifo
WO
RO
receive fifo
5.11.1 Interrupt Source Register
The interrupt source register contains the raw unmasked interrupts and can be used for polling purposes (instead
of the external interrupt pin) or for determining which interrupt(s) have caused the external interrupt pin to assert.
Interrupt Source Register
Address: 0x00
Name
Reset = 0x0
Type: RO
Bit
Function
Reset
SCP220x ICP Family, Rev.2.1
138
Freescale Semiconductor
Registers
Reserved
dat3
31-20
19
Reserved
This is not an interrupt but reflects the current state of the mmc_data3 signal.
0x0
0x0
sdio_interrupt
18
SDIO cards have a card interrupt mechanism. This bit is the indicator for that
interrupt and is only applicable to SDIO cards. This interrupt source can be
masked but not cleared by the interrupt clear register. It must be cleared
within the SDIO card itself.
data_complete
data_crc
17
16
15
Indicates that an MMC/SD data operation (read or write) is complete.
Indicates that for an MMC/SD data operation, the CRC check failed.
0x0
0x0
0x0
response
Indicates that for MMC/SD operation, an MMC/SD response is available in
the response buffer.
response_crc
dat3_low
14
13
Indicates that the received MMC/SD response has a CRC check failure.
0x0
0x0
This interrupt is asserted when the data state machine is idle and the
mmc_data3 is low.
dat3_high
12
This interrupt is asserted when the data state machine is idle and the
mmc_data3 is high.
0x0
cmd_complete
busy
11
10
Indicates that the current MMC/SD command has been sent.
0x0
0x0
Indicates that an MMC/SD card "busy" condition is no longer present. i.e. the
card is no longer busy.
tx_pop_error
rx_push_error
dma_pop_error
dma_push_error
9
8
7
6
asserted when the transmit fifo experiences an overrun condition or
misaligned access. This error is from the perspective of the external
interface.
0x0
0x0
0x0
0x0
asserted when the receive fifo experiences an underrun condition or
misaligned access. This error is from the perspective of the external
interface.
asserted when the receive fifo experiences an underrun condition or
misaligned access. This error is from the perspective of the internal APB
bus.
asserted when the transmit fifo experiences an overrun condition or
misaligned access. A misaligned access can occur if the width of the write
has changed from a previous access. For example, if byte writes have
previously been used, the number of writes may be non-multiples of 32 bits.
If a 32 bit write now occurs, this is a misaligned access because the byte
pointers in the fifo are not pointing to byte ’0’. This error is from the
perspective of the internal APB bus.
rx_ff
5
4
asserted when the receive fifo has become full
0x0
0x0
rx_hf
asserted when the receive fifo level (amount of bytes in the fifo) is above the
software configured “half” empty level.
rx_fe
tx_ff
3
2
1
asserted when the receive fifo has become NOT empty
asserted when the transmit fifo has become NOT full
0x0
0x0
0x0
tx_hf
asserted when the transmit fifo level (amount of space available) is above the
software configured “half” full level.
tx_fe
0
asserted when the transmit fifo has become empty
0x0
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
139
Registers
5.11.2 Interrupt Mask Register
The interrupt mask register provides a mechanism to individually mask one or more of the interrupt sources.
Interrupt Mask Register
Address: 0x04
Name
Reset = 0x7_FFFF
Type: RW
Bit
Function
Reset
31-19
18
17
16
15
14
13
12
11
10
9
sdio_interrupt
data_complete
data_crc
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
response
response_crc
dat3_low
dat3_high
cmd_complete
busy
tx_pop_error
rx_push_error
dma_pop_error
dma_push_error
rx_ff
8
7
6
5
rx_hf
4
rx_fe
3
tx_ff
2
tx_hf
1
tx_fe
0
5.11.3 Interrupt Clear Register
The interrupt clear register provides the mechanism for clearing the raw interrupt sources. Writing a „1. to the
interrupt bit location will clear the interrupt.
Interrupt Clear Register
Address: 0x08
Name
Reset = 0x0
Type: WO
Bit
Function
Reset
SCP220x ICP Family, Rev.2.1
140
Freescale Semiconductor
Registers
31-18
17
16
15
14
13
12
11
10
9
data_complete
data_crc
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
response
response_crc
dat3_low
dat3_high
cmd_complete
busy
tx_pop_error
rx_push_error
dma_pop_error
dma_push_error
rx_ff
8
7
6
5
rx_hf
4
rx_fe
3
tx_ff
2
tx_hf
1
tx_fe
0
5.11.4 MMC/SD Clock Rate
MMC/SD clock rate
Address: 0x0C
Reset = 0x80000000
Type: RW
Name
Bit
Function
Reset
disable
31
This bit provides a lower power standby condition when the SD interface is in
use. Setting this bit will halt the clock such that the external serial clock is low.
Power-up default is a disabled clock. Software must ensure that the proper
divide is programmed prior to enabling the clock. Also, it is recommended to
disable the clock whenever a clock_rate_divider change is required so that
spurious clock pulses do not occur.
0x1
Reserved
30-16
15-0
Reserved
clock_divider
The interface PLL clock is divided by the contents of this field to produce the
serial clock. A divider of 2 or greater is valid.
0x0
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
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Registers
5.11.5 MMC/SD configuration
MMC/SD Configuration
Address: 0x10
Name
Reset = 0x0
Type: RW
Bit
Function
Reset
Reserved
31-10
13:12
Reserved
data_width
Configures the width of the external data bus.
00 = 1-bit data
0x0
01 = 4-bit data
10,11 = reserved
Reserved
11-10
9-8
Reserved
tx_fifo_size
Although the asynchronous fifo supports writes of varying sizes (8,16,32 or
0x0
64) the size must be configured prior to using the fifo. This size refers to the
side of the fifo that the internal bus or dma engine writes to. If this field is being
updated, the fifo must be flushed to ensure that the internal pointers are
properly aligned.
00 = 8 bit
01 = 16 bit
10 = 32 bit
11 = 64 bit
rx_fifo_size
7-6
Although the asynchronous fifo supports reads of varying sizes (8,16,32 or 64)
0x0
the size must be configured prior to using the fifo. This size refers to the side
of the fifo that the internal bus or dma engine reads from. If this field is being
updated, the fifo must be flushed to ensure that the internal pointers are
properly aligned.
00 = 8 bit
01 = 16 bit
10 = 32 bit
11 = 64 bit
enable
5
This allows the media interface to function or holds it in an in-operative state.
0=disable
1=enable.
0x0
0x0
Reserved
block_size
4
Reserved
3-0
This field indicates how many bytes are associated with a block for any read
or write transaction. The hardware uses this field to break larger data lengths
into block size chunks. The block size is defined as 2block_size
.
0=reserved, 1=2bytes, 2=4bytes, 3=8bytes, 4=16bytes, 5=32bytes,
6=64bytes, 7=128bytes, 8=256bytes, 9=512bytes, 10=1Kbytes, 11=2Kbytes,
12=4Kbytes, 13=8Kbytes, 14=16Kbytes, 15=32Kbytes
5.11.6 MMC/SD Data Control
This register is used to indicate to hardware the data path activity associated with a particular command. This
register must be configured prior to writing to the command register.
MMC/SD Data Control
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Freescale Semiconductor
Registers
Address: 0x14
Reset = 0x0
Type: RW
Name
Bit
Function
Reset
data_size
31-16
This field indicates how many bytes are transferred before signaling a
completion interrupt. This field must be an integer multiple of the configured
block size. When this register is read, the data_size field will reflect how many
bytes of data remain to be transferred.
0x0
Reserved
data_ena
15-2
1
Reserved
Data path operation will not commence until this bit is enabled.
0=disable
1=enable.
0x0
0x0
data_direction
0
0=read
1=write.
5.11.7 MMC/SD Argument
MMC/SD Argument
Address: 0x18
Reset = 0x0
Type: RW
Name
Bit
Function
Reset
cmd_argument
31-0
This contains the argument for the command to be sent to the SD card. A read
of the register will provide the previous command argument that was written
0x0
5.11.8 MMC/SD Argument
MMC/SD Command
Address: 0x1C
Name
Reset = 0x0
Type: RW
Bit
Function
Reset
Reserved
31-11
10-8
Reserved
response_type
This field indicates to the hardware the type of response that is expected for
the particular command issued.
000=response type R1 or R6
0x0
001=rsponse type R1b
010=response type R2
011=response type R3 or R4
100=no response.
Reserved
7
Reserved
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
143
Registers
data_command
6
This bit is only applicable to SDIO cards that make use of the interrupt feature
on mmc_data1. Also it is only applicable when the interface is configured for
the 4 bit mode of operation which will use mmc_data1 as a data line. Under
this scenario the SDIO interrupt has a window of opportunity that it is valid. For
hardware to understand that window of opportunity it must know whether the
command that is being issued is associated with data or not.
0x0
1 = command is a data related command (read or write operation)
0 = command is not data related.
command_index
5-0
This is the command index to be sent to the SD card. The action of writing to
this register initiates the command transfer process. A read of the register will
provide the previous command index that was written.
0x0
5.11.9 MMC/SD Command Response
MMC/SD command response
Address: 0x20
Name
Reset = 0x0
Type: RO
Bit
Function
Reset
Reserved
31-6
5-0
Reserved
command_index
Contains the command index field of the last received response. If the
response is type R2 or R3 the field will be ’111111’.
0x0
5.11.10 MMC/SD Response
MMC/SD response
Address: 0x24
Name
Reset = 0x0
Type: RO
Bit
Function
Reset
card_status
CID/CSD[39:8]
31-0
These registers are used to store the current SD response. If the response is
type R1, R1b or R6 only the first 32 bits of the response field are valid
Contains the card status field of the response or contains either the CID fields
or CSD fields if a command is issued that queries this information.
0x0
MMC/SD response
Address: 0x28
Reset = 0x0
Type: RO
Name
Bit
31-0
Function
Reset
CID/CSD[71:40]
Contains either the CID fields or CSD fields if a command is issued that
queries this information.
0x0
MMC/SD response
SCP220x ICP Family, Rev.2.1
144
Freescale Semiconductor
Registers
Address: 0x2C
Reset = 0x0
Type: RO
Name
Bit
Function
Reset
CID/CSD[103:72]
31-0
Contains either the CID fields or CSD fields if a command is issued that
queries this information.
0x0
MMC/SD response
Address: 0x30
Name
Reset = 0x0
Type: RO
Bit
Function
Reset
Reserved
31-24
23-0
Reserved
CID/CSD[127:104]
Contains either the CID fields or CSD fields if a command is issued that
queries this information.
0x0
5.11.11 FIFO Status
FIFO status
Address: 0x34
Reset = 0x80
Type: RO/WO
Name
Bit
Function
Reset
rx_flush
31
When this bit is written ‘1’, the receive fifo is flushed.
This bit is a write only bit.
0x0
tx_flush
30
When this bit is written ‘1’, the transmit fifo is flushed.
This bit is a write only bit.
0x0
29-16
15-8
rx_byte_count
tx_byte_count
Indicates how many bytes of data is present in the receive fifo.
This is a read only field.
0x0
7-0
Indicates how many bytes of free space is available in the transmit fifo.
This is a read only field.
0x80
5.11.12 FIFO Flag Configuration
FIFO flag Configuration
Address: 0x38
Reset = 0x4040
Type: RW
Name
Bit
Function
Reset
Reserved
31-16
Reserved
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
145
Registers
rx_half_empty
15-8
7-0
Sets the FIFO level (in bytes) that asserts the receive “half” empty flag. The
level setting is associated with how much data is in the FIFO. i.e if the setting
is 0x20, then when there is 0x20 bytes of data available in the FIFO, the
interrupt will be asserted.
0x40
0x40
tx_half_full
Sets the FIFO level (in bytes) that asserts the transmit “half” full flag. The level
setting is associated with how much data is in the FIFO. i.e if the setting is
0x20, then when there is 0x20 bytes of data available in the FIFO, the interrupt
will be asserted.
5.11.13 Transmit FIFO
The Transmit FIFO operates as a fifo even though it has a range of addresses. The wider range allows bus bursting
to fill the fifo.
Transmit FIFO
Address: 0x1000-0x1fff
Name
Reset = 0x0
Type: WO
Bit
31-0
Function
Reset
data
This field contains the data to be written to the fifo. This register supports 8,16
or 32 bit writes and pushes the appropriate amount of data into the fifo. The
size of the access must match the size that is programmed into the tx_fifo_size
field in the Configuration1 register.
0x0
5.11.14 Receive FIFO
The Receive FIFO operates as a fifo even though it has a range of addresses. The wider range allows bus bursting
to drain the fifo.
Receive FIFO
Address: 0x2000-0x2fff
Name
Reset = 0x0
Type: WO
Bit
31-0
Function
Reset
data
This field contains the data to be read from the fifo. This register supports
8,16 or 32 bit reads and pops the appropriate amount of data from the fifo.
The size of the access must match the size that is programmed into the
rx_fifo_size field in the Configuration1 register.
0x0
5.12 MMCPlus Control Registers
The MMCPLUS register map is summarized below and described in the following sections.
Register
Interrupt Source
Address Offset
0x00
Mode
RO
RW
WO
Interrupt Mask
Interrupt Clear
0x04
0x08
SCP220x ICP Family, Rev.2.1
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Freescale Semiconductor
Registers
MMCPLUS clock rate
MMCPLUS Configuration
MMCPLUS Data Control
MMCPLUS argument
MMCPLUS command
MMCPLUS command response
MMCPLUS response
fifo status
0x0C
RW
RW
0x10
0x14
RW
0x18
RW
0x1C
RW
0x20
RO
0x24-0x30
0x34
RO
RO/WO
RW
fifo flag Configuration
reserved
0x38
0x3C-0xfff
0x1000-0x1fff
0x2000-0x2fff
transmit fifo
WO
RO
receive fifo
5.12.1 Interrupt Source Register
The interrupt source register contains the raw unmasked interrupts and can be used for polling purposes (instead
of the external interrupt pin) or for determining which interrupt(s) have caused the external interrupt pin to assert.
Interrupt Source Register
Address: 0x00
Name
Reset = 0x0
Type: RO
Bit
Function
Reset
Reserved
dat3
31-20
19
Reserved
This is not an interrupt but reflects the current state of the mmc_data3 signal.
0x0
0x0
sdio_interrupt
18
SDIO cards have a card interrupt mechanism. This bit is the indicator for that
interrupt and is only applicable to SDIO cards. This interrupt source can be
masked but not cleared by the interrupt clear register. It must be cleared
within the SDIO card itself.
data_complete
data_crc
17
16
15
Indicates that an MMCPLUS data operation (read or write) is complete.
Indicates that for an MMCPLUS data operation, the CRC check failed.
0x0
0x0
0x0
response
Indicates that for MMCPLUS operation, an MMCPLUS response is available
in the response buffer.
response_crc
dat3_low
14
13
Indicates that the received MMCPLUS response has a CRC check failure.
0x0
0x0
This interrupt is asserted when the data state machine is idle and the
mmc_data3 is low.
dat3_high
12
11
This interrupt is asserted when the data state machine is idle and the
mmc_data3 is high.
0x0
0x0
cmd_complete
Indicates that the current MMCPLUS command has been sent.
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
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Registers
busy
10
9
Indicates that an MMCPLUS card "busy" condition is no longer present. i.e.
the card is no longer busy.
0x0
0x0
tx_pop_error
rx_push_error
dma_pop_error
dma_push_error
asserted when the transmit fifo experiences an overrun condition or
misaligned access. This error is from the perspective of the external
interface.
8
7
6
asserted when the receive fifo experiences an underrun condition or
misaligned access. This error is from the perspective of the external
interface.
0x0
0x0
0x0
asserted when the receive fifo experiences an underrun condition or
misaligned access. This error is from the perspective of the internal APB
bus.
asserted when the transmit fifo experiences an overrun condition or
misaligned access. A misaligned access can occur if the width of the write
has changed from a previous access. For example, if byte writes have
previously been used, the number of writes may be non-multiples of 32 bits.
If a 32 bit write now occurs, this is a misaligned access because the byte
pointers in the fifo are not pointing to byte ’0’. This error is from the
perspective of the internal APB bus.
rx_ff
5
4
asserted when the receive fifo has become full
0x0
0x0
rx_hf
asserted when the receive fifo level (amount of bytes in the fifo) has risen
above the software configured “half” empty level.
rx_fe
tx_ff
3
2
1
asserted when the receive fifo has become NOT empty
asserted when the transmit fifo has become NOT full
0x0
0x0
0x0
tx_hf
asserted when the transmit fifo level (amount of space available) has risen
above the software configured “half” full level.
tx_fe
0
asserted when the transmit fifo has become empty
0x0
5.12.2 Interrupt Mask Register
The interrupt mask register provides a mechanism to individually mask one or more of the interrupt sources.
Interrupt Mask Register
Address: 0x04
Name
Reset = 0x7FFFF
Type: RW
Bit
Function
Reset
Reserved
sdio_interrupt
data_complete
data_crc
31-19
18
Reserved
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
0x1
0x1
0x1
0x1
0x1
0x1
17
16
response
15
response_crc
dat3_low
14
13
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Freescale Semiconductor
Registers
dat3_high
cmd_complete
busy
12
11
10
9
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
tx_pop_error
rx_push_error
dma_pop_error
dma_push_error
rx_ff
8
7
6
5
rx_hf
4
rx_fe
3
tx_ff
2
tx_hf
1
tx_fe
0
5.12.3 Interrupt Clear Register
The interrupt clear register provides the mechanism for clearing the raw interrupt sources. Writing a „1. to the
interrupt bit location will clear the interrupt.
Interrupt Clear Register
Address: 0x08
Name
Reset = 0x0
Type: WO
Bit
Function
Reset
31-18
17
16
15
14
13
12
11
10
9
data_complete
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
data_crc
response
response_crc
dat3_low
dat3_high
cmd_complete
busy
tx_pop_error
rx_push_error
dma_pop_error
dma_push_error
8
7
6
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
149
Registers
rx_ff
5
4
3
2
1
0
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
0x0
0x0
0x0
0x0
0x0
0x0
rx_hf
rx_fe
tx_ff
tx_hf
tx_fe
5.12.4 MMC PLUS Clock Rate
MMCPLUS clock rate
Address: 0x0C
Reset = 0x80000000
Type: RW
Name
Bit
Function
Reset
disable
31
This bit provides a lower power standby condition when the SD interface is in
use. Setting this bit will halt the clock such that the external serial clock is low.
Power-up default is a disabled clock. Software must ensure that the proper
divide is programmed prior to enabling the clock. Also, it is recommended to
disable the clock whenever a clock_rate_divider change is required so that
spurious clock pulses do not occur.
0x1
30-20
19-16
reserved
ext_clock_delay
mmcplus external clock delay
mmc_clock_out is delayed in proportion to this value.
0x0
0x0
clock_divider
15-0
The interface PLL clock is divided by the contents of this field to produce the
serial clock. A divider of 2 or greater is valid.
5.12.5 MMCPLUS Configuration
MMCPLUS Configuration
Address: 0x10
Name
Reset = 0x0
Type: RW
Bit
Function
Reset
Reserved
31-14
Reserved
data_width
13:12
Configures the width of the external data bus.
00 = 1-bit data
0x0
01 = 4-bit data
10 = 8-bit data
11 = reserved
reserved
11:10
Reserved
SCP220x ICP Family, Rev.2.1
150
Freescale Semiconductor
Registers
tx_fifo_size
rx_fifo_size
enable
9-8
7-6
5
Although the asynchronous fifo supports writes of varying sizes (8,16,32 or
64) the size must be configured prior to using the fifo. This size refers to the
side of the fifo that the internal bus or dma engine writes to. If this field is being
updated, the fifo must be flushed to ensure that the internal pointers are
properly aligned.
00 = 8 bit
01 = 16 bit
10 = 32 bit
11 = 64 bit
0x0
Although the asynchronous fifo supports reads of varying sizes (8,16,32 or 64)
the size must be configured prior to using the fifo. This size refers to the side
of the fifo that the internal bus or dma engine reads from. If this field is being
updated, the fifo must be flushed to ensure that the internal pointers are
properly aligned.
00 = 8 bit
01 = 16 bit
10 = 32 bit
11 = 64 bit
0x0
This allows the media interface to function or holds it in an in-operative state.
0x0
0=disable
1=enable.
reserved
4
reserved
0x0
0x0
block_size
3-0
This field indicates how many bytes are associated with a block for any read
or write transaction. The hardware uses this field to break larger data lengths
into block size chunks. The block size is defined as 2block_size.
0=reserved, 1=2bytes, 2=4bytes, 3=8bytes, 4=16bytes, 5=32bytes,
6=64bytes, 7=128bytes, 8=256bytes, 9=512bytes, 10=1Kbytes, 11=2Kbytes,
12=4Kbytes, 13=8Kbytes, 14=16Kbytes, 15=32Kbytes
5.12.6 MMCPLUS Data Control
This register is used to indicate to hardware the data path activity associated with a particular command. This
register must be configured prior to writing to the command register.
MMCPLUS Data Control
Address: 0x14
Reset = 0x0
Type: RW
Name
Bit
Function
Reset
data_size
31-16
This field indicates how many bytes are transferred before signaling a
completion interrupt. This field must be an integer multiple of the configured
block size. When this register is read, the data_size field will reflect how many
bytes of data remain to be transferred.
0x0
15-2
1
data_ena
Data path operation will not commence until this bit is enabled.
0=disable
1=enable.
0x0
0x0
data_direction
0
0=read
1=write.
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
151
Registers
5.12.7 MMCPLUS Agreement
MMCPLUS Argument
Address: 0x18
Reset = 0x0
Type: RW
Name
Bit
Function
Reset
cmd_argument
31-0
This contains the argument for the command to be sent to the SD card. A read
of the register will provide the previous command argument that was written
0x0
5.12.8 MMCPLUS Command
MMCPLUS Command
Address: 0x1C
Name
Reset = 0x0
Type: RW
Bit
Function
Reset
Reserved
31-11
10-8
Reserved
response_type
This field indicates to the hardware the type of response that is expected for
the particular command issued.
000=response type R1 or R6
0x0
001=rsponse type R1b
010=response type R2
011=response type R3 or R4
100=no response.
7
6
data_command
This bit is only applicable to SDIO cards that make use of the interrupt feature
on mmc_data1. Also it is only applicable when the interface is configured for
the 4 bit mode of operation which will use mmc_data1 as a data line. Under
this scenario the SDIO interrupt has a window of opportunity that it is valid. For
hardware to understand that window of opportunity it must know whether the
command that is being issued is associated with data or not.
0x0
1 = command is a data related command (read or write operation)
0 = command is not data related.
command_index
5-0
This is the command index to be sent to the SD card. The action of writing to
this register initiates the command transfer process. A read of the register will
provide the previous command index that was written.
0x0
5.12.9 MMCPLUS Command Response
MMCPLUS command response
Address: 0x20
Reset = 0x0
Type: RO
Name
Bit
Function
Reset
Reserved
31-6
Reserved
SCP220x ICP Family, Rev.2.1
152
Freescale Semiconductor
Registers
command_index
5-0
Contains the command index field of the last received response. If the
response is type R2 or R3 the field will be ’111111’.
0x0
5.12.10 MMCPLUS Response
MMCPLUS response
Address: 0x24
Name
Reset = 0x0
Type: RO
Bit
Function
Reset
card_status
CID/CSD[39:8]
31-0
These registers are used to store the current SD response. If the response is
type R1, R1b or R6 only the first 32 bits of the response field are valid
Contains the card status field of the response or contains either the CID fields
or CSD fields if a command is issued that queries this information.
0x0
MMCPLUS response
Address: 0x28
Reset = 0x0
Type: RO
Name
Bit
31-0
Function
Reset
CID/CSD[71:40]
Contains either the CID fields or CSD fields if a command is issued that
queries this information.
0x0
MMCPLUS response
Address: 0x2C
Reset = 0x0
Type: RO
Name
Bit
Function
Reset
CID/CSD[103:72]
31-0
Contains either the CID fields or CSD fields if a command is issued that
queries this information.
0x0
MMCPLUS response
Address: 0x30
Name
Reset = 0x0
Type: RO
Bit
Function
Reset
Reserved
31-24
23-0
Reserved
CID/CSD[127:104]
Contains either the CID fields or CSD fields if a command is issued that
queries this information.
0x0
5.12.11 FIFO Status
FIFO status
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
153
Registers
Address: 0x34
Reset = 0x80
Type: RO/WO
Name
Bit
Function
Reset
rx_flush
31
When this bit is written ‘1’, the receive fifo is flushed.
This bit is a write only bit.
0x0
tx_flush
30
When this bit is written ‘1’, the transmit fifo is flushed.
This bit is a write only bit.
0x0
Reserved
29-16
15-8
Reserved
rx_byte_count
Indicates how many bytes of data is present in the receive fifo.
This is a read only field.
0x0
tx_byte_count
7-0
Indicates how many bytes of free space is available in the transmit fifo.
This is a read only field.
0x80
5.12.12 FIFO Flag Configuration
FIFO flag Configuration
Address: 0x38
Name
Reset = 0x4040
Type: RW
Bit
Function
Reset
Reserved
31-16
15-8
Reserved
rx_half_empty
Sets the FIFO level (in bytes) that asserts the receive “half” empty flag. The
level setting is associated with how much data is in the FIFO. i.e if the setting
is 0x20, then when there is 0x20 bytes of data available in the FIFO, the
interrupt will be asserted.
0x40
tx_half_full
7-0
Sets the FIFO level (in bytes) that asserts the transmit “half” full flag. The level
setting is associated with how much data is in the FIFO. i.e if the setting is
0x20, then when there is 0x20 bytes of data available in the FIFO, the interrupt
will be asserted.
0x40
5.12.13 Transmit FIFO
The Transmit FIFO operates as a fifo even though it has a range of addresses. The wider range allows bus bursting
to fill the fifo.
Transmit FIFO
Address: 0x1000-0x1fff
Name
Reset = 0x0
Type: WO
Bit
31-0
Function
Reset
data
This field contains the data to be written to the fifo. This register supports 8,16
or 32 bit writes and pushes the appropriate amount of data into the fifo. The
size of the access must match the size that is programmed into the tx_fifo_size
field in the Configuration1 register.
0x0
SCP220x ICP Family, Rev.2.1
154
Freescale Semiconductor
Registers
5.12.14 Receive FIFO
The Receive FIFO operates as a fifo even though it has a range of addresses. The wider range allows bus bursting
to drain the fifo.
Receive FIFO
Address: 0x2000-0x2fff
Name
Reset = 0x0
Type: WO
Bit
31-0
Function
Reset
data
This field contains the data to be read from the fifo. This register supports 8,16
or 32 bit reads and pops the appropriate amount of data from the fifo. The size
of the access must match the size that is programmed into the rx_fifo_size
field in the Configuration1 register.
0x0
5.13 I2C Registers
The register map is summarized below and described in the following sections.
Register Address Offset Mode
Interrupt Source 0x00
RO
Interrupt Mask
Interrupt Clear
Configuration1
Configuration2
Configuration3
Slave Address
Target Data
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
RW
WO
RW
RW
RW
RW
RW
RW
WO
Target Address
Control
5.13.1 Interrupt Source Register
The interrupt source register contains the raw unmasked interrupts and can be used for polling purposes (instead
of the external interrupt pin) or for determining which interrupt(s) have caused the external interrupt pin to assert.
Interrupt Source Register
Address: 0x00
Name
Reset = 0x0
Type: RO
Bit
Function
Reset
Reserved
arb_lost
31-4
3
Reserved
Indicates that arbitration has been lost to another I2C master.
0x0
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
155
Registers
no_acknowledge
2
1
0
Indicates that an acknowledge was not received when the Slave ID was
sent or that an acknowledge was not received during the data phase
of a write transaction.
0x0
0x0
0x0
stop
Indicates that the “transaction stop” is complete. The serial interface
runs at a very slow rate and a stop indication must be completed before
software initiates a new “transaction start”.
acknowledge_complete
Indicates that the peripheral has acknowledged the transaction phase.
5.13.2 Interrupt Mask Register
The interrupt mask register provides a mechanism to individually mask one or more of the interrupt sources.
Interrupt Mask Register
Address: 0x04
Reset = 0xf
Type: RW
Name
Bit
Function
Reset
Reserved
31- Reserved
4
arb_lost_mask
no_acknowledge_mask
stop_mask
3
2
1
0
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
Masks the interrupt. 1=mask, 0=unmask.
0x1
0x1
0x1
0x1
acknowledge_mask
5.13.3 Interrupt Clear Register
The interrupt clear register provides the mechanism for clearing the raw interrupt sources. Writing a „1. to the
interrupt bit location will clear the interrupt.
Interrupt Clear Register
Address: 0x08
Name
Reset = 0x0
Type: WO
Bit
Function
Reset
Reserved
arb_lost_clr
31-4
Reserved
3
2
1
0
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
Clears the interrupt when written ‘1’.
0x0
0x0
0x0
0x0
no_acknowledge_clr
stop_clr
acknowledge_clr
5.13.4 Configuration1
Configuration1
SCP220x ICP Family, Rev.2.1
156
Freescale Semiconductor
Registers
Address: 0x0C
Reset = 0x0
Type: RW
Name
Bit
Function
Reset
master_ack
31
This bit provides the flexibility to allow or not allow the master to source an
acknowledge for read transactions. When ‘1’, the master will source an
acknowledge for read transactions. When ‘0’, the serial data line is not driven
during the acknowledge bit period.
0x0
prim_sec
30
The I2C block is physically connected to two sets of IO pins. The primary pins
do not have any sharing but the secondary pins are shared with
dip_data[17:16]. The duplication of I2C pins is required in some
circumstances because of the IO voltage selections. The DIP IOs can be
powered with a different IO voltage than the primary I2C IOs. If the I2C is
required to configure a DAC, them the secondary I2C port will have to be
used if the DIP IOs are not compatible with the I2C IOs. This bit selects which
set of IOs that the I2C communicates with. It is possible to have devices
connected to both primary and secondary IOs as long as this selector is
properly configured for the duration of the I2C communication. When set to
the primary I2C, the secondary I2C sees no activity and vice versa.
0 = I2C connected to primary I2C IOs.
0x0
1 = I2C connected to secondary I2C IOs.
auto_mode_ena
master_arb_ena
29
28
When this bit is set a more auto-mated mode of the I2C interface is
enabled and results in less interrupt over-head. Refer to
Programming Model 4.9.2 for a detailed decription of manual and
automatic modes.
0 = manual mode
1 = auto-matic mode
When this bit is set the arbitration logic for multiple master systems is
enabled.
0 = arbitration logic is disabled.
1 = arbitration logic is enabled.
Reserved
27-16
15-0
Reserved
clock_divider
This field contains the clock divider that is applied to the system clock to
generate the serial data clock. The clock divide ratio applied to the system
clock is this field plus one.
0x0
5.13.5 Configuration2
Configuration2
Address: 0x10
Reset = 0x0
Type: RW
Name
Bit
Function
Reset
TSUSTO
31-16
This field contains the count value that is applied to the system clock to
generate the TSUSTO timing parameter. This parameter is the minimum time
from serial_clock rising to serial_data rising during a “stop” indication. This is
typically 4.0 µsec.
0x0
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
157
Registers
THDSTA
15-0
This field contains the count value that is applied to the system clock to
generate the THDSTA timing parameter. This parameter is the minimum time
from serial_data falling to serial_clock falling during a “start” indication. This is
typically 4.0 µsec.
0x0
5.13.6 Configuration3
Configuration3
Address: 0x14
Reset = 0x0
Type: RW
Name
Bit
Function
Reset
TDELAY
31-16
This field contains the count value that is applied to the system clock to
generate the TDELAY timing parameter. This parameter is the delay time
between a slave address byte transmission and the next byte (read or write),
the time between consecutive bytes (read or write), as well as the time
between the last byte (read or write) and the stop condition. It should be
noted that the hardware also automatically checks for the I2C slave stall
indicator (SCL held low) and will stall its activity until the stall condition is
removed.
0x0
TBUF
15-0
This field contains the count value that is applied to the system clock to
generate the TBUF timing parameter. This parameter is the minimum idle
time between a start and stop condition. This is typically 4.7 µsec.
0x0
5.13.7 Slave Address
Slave Address
Address: 0x18
Reset = 0x0
Type: RW
Name
Bit
Function
Reset
Reserved
slave_id
31-8
7-1
Reserved
This field contains the slave id of the peripheral being accessed. It should be
programmed prior to initiating any transactions.
0x0
0x0
read_write
0
This is the R/W field for the Peripheral slave address. 1=read, 0=write.
5.13.8 Target Data
Target Data
Address: 0x1C
Reset = 0x0
Type: RW
Name
Bit
Function
Reset
Reserved
31-8
Reserved
SCP220x ICP Family, Rev.2.1
158
Freescale Semiconductor
Registers
data
7-0
For I2C write transactions, the target data field is the third byte of data transmitted after
the target address and is the data to be written to that target address. If the interface is
operating in manual mode, new data can be written after the “acknowledge” interrupt is
received.
0x0
For read transactions, this register will not provide valid information until a transaction
is started. Once a transaction is started, when an acknowledge interrupt has been
received, valid read data will be present in this register. If the register is read prior to
issuing a stop command, another read will occur on the serial control bus. If a stop has
been issued, valid data from the read is present and no further action results.
5.13.9 Target Address
Target Address
Address: 0x20
Reset = 0x0
Type: RW
Name
Bit
Function
Reset
Reserved
address
31-8
7-0
Reserved
The first byte of an I2C write transaction (after the slave address byte) is the
address of the register that is being accessed. This field is programmed with
that device address.
0x0
5.13.10 Control
Control
Address: 0x24
Name
Reset = 0x0
Type: WO
Bit
Function
Reset
Reserved
stop
31-2
1
Reserved
When this bit is written “1”, the serial control interface will create a stop
condition.
0x0
0x0
start
0
When this bit is written “1”, the serial control interface will create a start
condition, serialize out the data in the slave address register and either
serialize out the data in the data register for a write or de-serialize the
incoming data for a read.
5.14 PWM Registers
The register map is summarized below and described in the following sections.
Register
Address Offset
0x00
Mode
pwm config
pwm control
RW
RW
RW
0x04
0x08
compare buffer 0
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
159
Registers
count buffer 0
status 0
0x0C
0x10
0x14
0x18
0x1C
0x20
RW
RO
RW
RW
RO
RO
compare buffer 1
count buffer 1
status 1
raw interrupt
5.14.1 PWM Config
PWM Config
Address: 0x00
Reset = 0xc0_0000
Type: RW
Name
Bit
Function
Reset
Reserved
31-26
25
Reserved
0x0
0x0
t1_timeout_clr
Clears the timer 1 timeout interrupt. This bit is self-clearing.
1 = clear interrupt.
t0_timeout_clr
int_mask
24
Clears the timer 0 timeout interrupt. This bit is self-clearing.
1 = clear interrupt.
0x0
0x3
23-22
Mask for the two timer interrupts.
1 = interrupt is masked
0 = interrupt is not masked
t1_clk_sel
21-19
18-16
Mux selector for the PWM timer1.
000: ½
001: ¼
010: 1/8
011: 1/16
1xx: TCLK0
0x0
t0_clk_sel
Mux selector for the PWM timer0.
0x0
000: ½
001: ¼
010: 1/8
011: 1/16
1xx: TCLK0
dead_zone_length
prescaler
15-8
7-0
Specifies the dead zone length
Specifies the pre-scaler value
0x0
0x0
5.14.2 PWM Control
PWM Control
Address: 0x04
Reset = 0x0
Type: RW
SCP220x ICP Family, Rev.2.1
160
Freescale Semiconductor
Registers
Reset
Name
Bit
Function
Reserved
31-9
8
Reserved
0x0
0x0
t1_auto_reload
Controls the auto reload function of timer 1.
0 = one shot
1 = interval mode (auto reload)
t1_inverter
t1_update
7
6
5
4
3
2
1
0
Controls the output inverter for timer 1.
0 = inverter off
1 = inverter on
0x0
0x0
0x0
0x3
0x0
0x0
0x0
0x0
Controls the manual update for timer 1.
0 = no operation
1 = the timer is updated with the count buffer value.
t1_start
Controls the operation of timer 1.
0 = timer stopped
1 = timer started
dead_zone_en
t0_auto_reload
t0_inverter
t0_update
Controls the dead zone operation
0 = disabled
1 = enabled
Controls the auto reload function of timer 0.
0 = one shot
1 = interval mode (auto reload)
Controls the output inverter for timer 0.
0 = inverter off
1 = inverter on
Controls the manual update for timer 0.
0 = no operation
1 = the timer is updated with the count buffer value.
t0_start
Controls the operation of timer 0.
0 = timer stopped
1 = timer started
5.14.3 Compare Buffer 0
Compare buffer 0
Address: 0x08
Name
Reset = 0x0
Type: RW
Bit
Function
Reset
Reserved
31-16
15-0
Reserved
0x0
0x0
t0_com_buffer
Timer 0 compare buffer.
5.14.4 Count Buffer 0
Count buffer 0
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
161
Registers
Address: 0x0C
Reset = 0x0
Type: RW
Type: RO
Type: RW
Type: RW
Type: RO
Name
Bit
Function
Reset
Reserved
31-16
15-0
Reserved
0x0
0x0
t0_count_buffer
Timer 0 count buffer.
5.14.5 Status 0
Status 0
Address: 0x10
Name
Reset = 0x0
Bit
Function
Reset
Reserved
31-16
15-0
Reserved
0x0
0x0
t0_timer_cnt
Timer 0 count observation register.
5.14.6 Compare Buffer 1
Compare buffer 1
Address: 0x14
Name
Reset = 0x0
Bit
Function
Reset
Reserved
31-16
15-0
Reserved
0x0
0x0
t1_com_buffer
Timer 1 compare buffer.
5.14.7 Count Buffer 1
Count buffer 1
Address: 0x18
Reset = 0x0
Name
Bit
Function
Reset
Reserved
31-16
15-0
Reserved
0x0
0x0
t1_count_buffer
Timer 1 count buffer.
5.14.8 Status 1
Status 1
Address: 0x1C
Reset = 0x0
SCP220x ICP Family, Rev.2.1
162
Freescale Semiconductor
Registers
Reset
Name
Bit
Function
Reserved
31-16
15-0
Reserved
0x0
0x0
t1_timer_cnt
Timer 1 count observation register.
5.14.9 Raw Interrupt
Raw Interrupt
Address: 0x20
Reset = 0x0
Type: RO
Name
Bit
Function
Reset
Reserved
t1_timeout
t0_timeout
31-2
Reserved
0x0
0x0
0x0
1
0
Timer 1 timeout interrupt.
Timer 0 timeout interrupt.
5.15 KeyScan Registers
The register map is summarized below and described in the following sections.
Register Address Offset Mode
Interrupt Mask 0x00
RW
RO
RW
RW
RW
RW
RO
Interrupt Source
Interrupt Clear
Keypad control0
Keypad control1
Keypad time
0x04
0x08
0x0C
0x10
0x14
0x18
Keypad value
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
163
Registers
5.15.1 Interrupt Mask Register
The interrupt mask register provides a mechanism to individually mask one or more of the interrupt sources.
Interrupt Mask Register
Address: 0x00
Name
Reset = 0xFFFF
Type: RW
Bit
Function
Reset
Reserved
31-16
Reserved
Key sensing
15-0
Masks the interrupt. 1=mask, 0=unmask.
0xFFFF
5.15.2 Interrupt Source Register
The interrupt source register contains the masked interrupts and can be used for polling purposes (instead of the
external interrupt pin) or for determining which interrupt(s) have caused the external interrupt pin to assert.
Interrupt Source Register
Address: 0x01
Reset = 0x0
Type: RO
Name
Bit
Function
Reset
Reserved
31-16
Reserved
Key sensing
15-0
Each key sense is detected by hardware.
0x0000
5.15.3 Interrupt Clear Register
The interrupt clear register provides the mechanism for clearing the interrupt sources. Writing a „1. to the interrupt
bit location will clear the interrupt.
Reading this register returns unmasked interrupt source that is interrupt source pending register.
Interrupt Clear Register
Address: 0x08
Name
Reset = 0x0
Type: RW
Bit
Function
Reset
Reserved
31-16
Reserved
Key sensing
15-0
Writing a ‘1’ : relative interrupt source will be cleared.
0x0000
Reading : returns unmasked interrupt source
5.15.4 Keypad Control0
Keypad control0
Address: 0x0C
Name
Reset = 0x0
Type: RW
Bit
Function
Reset
SCP220x ICP Family, Rev.2.1
164
Freescale Semiconductor
Registers
Reserved
31-6
5
Reserved
0x0
0x0
keypad_enable
Keypad operation enable
1 = enable
0 = disable
polarity
4
3
Keyscan output and key sense polarity
1 = active high (external pull-down)
0 = active low (external pull-up)
0x0
0x0
mode_sel
1 = single input mode. When in this mode, keypad module will sense only one
button at a time. It is used in typing mode.
0 = multi input mode. When in this mode, keypad module will sense
multi-button at a time. It is useful in gaming mode that requires moving
diagonal and shooting with moving.
Reserved
auto_clr
2
1
Reserved
0
Keypad auto clear enable. When enabled, the keypad value register is
0x0
cleared after it is read.
1 = enabled
0 = disabled
value_clr
0
keypad register clear. This bit is self resetting
1 = the keypad value register is cleared.
0 = no action
0x3
5.15.5 Keypad Control1
Keypad Control 1
Address: 0x10
Name
Reset = 0x0
Type: RW
Bit
Function
Reset
0x0
Reserved
31-8
7
Reserved
keysense3_en
Keysense3 enable
1 : enable
0 : disable
keysense2_en
keysense1_en
keysense0_en
keyscan3_en
6
5
4
3
Keysense2 enable
1 : enable
0 : disable
0x0
Keysense1 enable
1 : enable
0 : disable
0x0
Keysense0 enable
1 : enable
0 : disable
0x0
Keyscan3 enable
1 : enable
0x0
0 : disable
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
165
Registers
keyscan2_en
2
1
0
Keyscan2 enable
1 : enable
0 : disable
0x0
0x0
0x0
keyscan1_en
keyscan0_en
Keyscan1 enable
1 : enable
0 : disable
Keyscan0 enable
1 : enable
0 : disable
5.15.6 Keypad Time
Keypad time
Address: 0x14
Reset = 0x1FFF
Type: RW
Name
Bit
Function
Reset
Reserved
scan_time
31-13
12-0
Reserved
0x0
Key scan driving time. Scan_time_freq = sys_freq / (scan_time+1)
0x1FFF
5.15.7 Keypad Value
Keypad value
Address: 0x18
Reset = 0x0
Reserved
Type: RO
Name
Bit
Function
Reset
0x0
Reserved
sense_value
31-16
15-0
Contains the sense value vector. This vector is a dynamic view of the key
sense information and will change for every key scan interval. If a latched
version of this field is desired, please read the interrupt source register.
0x0
The following table illustrates the sense_value vector.
key_sense3
sense_value15
sense_value11
sense_value7
sense_value3
key_sense2
key_sense1
sense_value13
sense_value9
sense_value5
sense_value1
key_sense0
sense_value12
sense_value8
sense_value4
sense_value0
key_scan3
key_scan2
key_scan1
key_scan0
sense_value14
sense_value10
sense_value6
sense_value2
5.16 GPIO Registers
The General Purpose Input Output (GPIO) pins are controlled with several registers.
•
•
GPIO Enable Registers activate the pin for GPIO use, otherwise the pin has its primary or alternate function.
GPIO Direction Registers determine the GPIO as input or output.
SCP220x ICP Family, Rev.2.1
166
Freescale Semiconductor
Registers
•
•
GPIO OutData Registers determine the level of the GPIO when configured as output.
GPIO InData Registers read the level of GPIO when configured as input.
In case a GPIO pin is used as output, it is preferable to activate the enable bit once the direction and OutData have
been set.
See also Section 2.4, Pin Configuration and Section 4.12, GPIOs and Alternate Functions.
5.16.1 GPIO Enable Registers
Table 84. GPIO Enable Registers
GPIO Enable 1
Address: 0xd00a_0000
Reset = 0
Function
Type: RW
Name
Bit
Reset
Reset
Reset
These bits are used to enable the alternate GPIO functionality for the
external pins listed in the preceding table.
0 = GPIO disabled
gpio_enable[31-0]
31-0
0
1 = GPIO enabled
GPIO Enable 2
Address: 0xd00a_0004
Reset = 0
Function
Type: RW
Name
Bit
These bits are used to enable the alternate GPIO functionality for the
external pins listed in the preceding table.
0 = GPIO disabled
gpio_enable[63-32]]
31-0
0
1 = GPIO enabled
GPIO Enable 3
Address: 0xd00a_0008
Reset = 0
Function
Type: RW
Name
Bit
These bits are used to enable the alternate GPIO functionality for the
external pins listed in the preceding table.
0 = GPIO disabled
gpio_enable[95-64]
31-0
0
1 = GPIO enabled
5.16.2 GPIO Direction Registers
Table 85. GPIO direction Registers
GPIO Direction 1
Address: 0xd00a_000C
Reset = 0xffff_ffff
Function
Type: RW
Name
Bit
Reset
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
167
Registers
Table 85. GPIO direction Registers
gpio_dir[31-0]
31-0
If a GPIO has been enabled these bits configure the GPIO as either
0xffff_ffff
an input or output.
0 = output
1 = input
GPIO Direction 2
Address: 0xd00a_0010
Reset = 0xffff_ffff
Function
Type: RW
Name
Bit
Reset
gpio_dir[63-32]
31-0
If a GPIO has been enabled these bits configure the GPIO as either
0xffff_ffff
an input or output.
0 = output
1 = input
GPIO Direction 3
Address: 0xd00a_0014
Reset = 0xffff_ffff
Function
Type: RW
Name
Bit
Reset
gpio_dir[95-64]
31-0
If a GPIO has been enabled these bits configure the GPIO as either
0xffff_ffff
an input or output.
0 = output
1 = input
5.16.3 GPIO OutData Registers
Table 86. GPIO OutData Registers
GPIO OutData 1
Address: 0xd00a_0018
Reset = 0
Function
Type: RW
Name
Bit
Reset
gpio_out[31-0]
31-0
When the register is written, the GPIO will latch the written value if
the GPIO is an output. For an input the write is ignored. When read,
it will reflect what was previously written (whether or not the GPIO is
configured as an input or output).
0
GPIO OutData 2
Address: 0xd00a_001c
Reset = 0
Function
Type: RW
Name
Bit
Reset
gpio_out[63-32]
31-0
When the register is written, the GPIO will latch the written value if
the GPIO is an output. For an input the write is ignored. When read,
it will reflect what was previously written (whether or not the GPIO is
configured as an input or output).
0
SCP220x ICP Family, Rev.2.1
168
Freescale Semiconductor
Registers
Table 86. GPIO OutData Registers
GPIO OutData 3
Address: 0xd00a_0020
Reset = 0
Function
Type: RW
Name
Bit
Reset
gpio_out[95-64]
31-0
When the register is written, the GPIO will latch the written value if
the GPIO is an output. For an input the write is ignored. When read,
it will reflect what was previously written (whether or not the GPIO is
configured as an input or output).
0
5.16.4 GPIO InData Registers
Table 87. GPIO InData Registers
GPIO InData 1
Address: 0xd00a_0024
Reset = 0
Function
When this register is read, the bits reflect the level of the external
Type: RO
Name
Bit
Reset
gpio_in[31-0]
31-0
0
signal if the GPIO is an input or reflects the previously written value
if the GPIO is an output.
GPIO InData 2
Address: 0xd00a_0028
Reset = 0
Function
Type: RO
Name
Bit
Reset
gpio_in[63-32]
31-0
When this register is read, the bits reflect the level of the external
signal if the GPIO is an input or reflects the previously written value
if the GPIO is an output.
0
GPIO InData 3
Address: 0xd00a_002c
Reset = 0
Function
Type: RO
Name
Bit
Reset
gpio_in[95-64]
31-0
When this register is read, the bits reflect the level of the external
signal if the GPIO is an input or reflects the previously written value
if the GPIO is an output.
0
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
169
Packaging
6
Packaging
6.1
SCP2201
The SCP2201 is available in a 236-ball BGA package of size 9 mm x 9 mm x 1.34 mm. Figure 57 contains SCP220x
packaging information. All dimensions are in mm.
0.10
C
0.08
C
A1 BALL PAD CORNER
C
16 14 12 10
15 13 11
8
6
4
2
9
7
5
3
1
A
C
E
G
J
B
D
F
_
0.30+0.05
5.
6.
0.50
M
M
0.15
0.05
C
C
A B
H
K
M
P
T
SEATING PLANE
L
N
R
(0.75)
_
0.23 +0.05
(0.75)
0.50
_
0.80 +0.05
_
1.24 +0.10
BOTTOM VIEW
0.10 (4X)
236 SOLDER BALLS
SIDE VIEW
9.00
A
A1 BALL PAD CORNER
9.00
TOP VIEW
B
Figure 58. SCP2201 Package
6.2
SCP2207
The SCP2207 is available in a 236-ball BGA package of size 9 mm x 9 mm x 1.34 mm. The following figure contains
SCP220x packaging information. All dimensions are in mm.
SCP220x ICP Family, Rev.2.1
170
Freescale Semiconductor
Packaging
Figure 59. SCP2207 Package
6.3
SCP220x Pinout
The following table describes the physical pins of the devices belonging to the SCP220x series. The pins are
organized into functional groups. External interfaces are grouped together on the IO voltage banks that can be
powered by either 3.0 V DC 10%. Many outputs may be configured as having low or high output drive strength by
programming the device. The output drive capability is indicated in the PAD type column.
Note that ‘-’. indicates the pin does not apply to the device as the signal is not balled out on the package. Pins in the
‘No Connect’ section of the table are used solely for test purposes and should not be used in normal operating mode.
Some pins are designated ‘reserved_#’. These pins may only be used as the corresponding GPIOs or alternate
functionality as defined in section 4.11. Primary functionality of these pins is reserved and not intended for use.
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
171
Packaging
Table 88. SCP220x Pinout
SCP2201
and
SCP2207
Ball
Pin Name
Power Domain
PAD Type
Default PU/PD
Sensor
sensor_D[0]
sensor_D[1]
sensor_D[2]
sensor_D[3]
sensor_D[4]
sensor_D[5]
sensor_D[6]
sensor_D[7]
sensor_D[8]
sensor_D[9]
sensor_fclk
sensor_pclk
sensor_rclk
sensor_fodd
sensor_gpio
sensor_clkout
SIF
SIF
SIF
SIF
SIF
SIF
SIF
SIF
SIF
SIF
SIF
SIF
SIF
SIF
SIF
SIF
Input
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
-
C6
C7
D7
E7
Input
Input
Input
Input
B8
Input
Input
C8
D8
E8
Input
Input
B9
Input
C9
B11
E9
Input
Input
Input
D9
C10
B7
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
-
-
B10
I2C
scl
SIF
SIF
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
-
-
E10
D10
sda
NAND
nand_wen
nand_ren
NAND
NAND
NAND
NAND
NAND
NAND
NAND
NAND
Bi-dir. 2 mA / 4 mA
Bi-dir. 2 mA / 4 mA
Bi-dir. 2 mA / 4 mA
Bi-dir. 2 mA / 4 mA
Bi-dir. 2 mA / 4 mA
Bi-dir. 2 mA / 4 mA
Bi-dir. 2 mA / 4 mA
Bi-dir. 2 mA / 4 mA
-
-
R1
T1
K3
T2
R2
P2
L3
nand_cen[3]
nand_cen[2]
nand_cen[1]
nand_cen[0]
nand_ale
PU
PU
PU
PU
-
nand_cle
-
M3
SCP220x ICP Family, Rev.2.1
172
Freescale Semiconductor
Packaging
Table 88. SCP220x Pinout
nand_D[0]
nand_D[1]
nand_D[2]
nand_D[3]
nand_D[4]
nand_D[5]
nand_D[6]
nand_D[7]
wp_N
NAND
Bi-dir. 2 mA / 4 mA
Bi-dir. 2 mA / 4 mA
Bi-dir. 2 mA / 4 mA
Bi-dir. 2 mA / 4 mA
Bi-dir. 2 mA / 4 mA
Bi-dir. 2 mA / 4 mA
Bi-dir. 2 mA / 4 mA
Bi-dir. 2 mA / 4 mA
Input
-
-
-
-
-
-
-
-
-
N3
P3
K4
N4
P4
K5
N5
N6
-
NAND
NAND
NAND
NAND
NAND
NAND
NAND
NAND
DAC
DAC_comp
DAC_vref_out
DAC_rset
DAC
DAC
DAC
DAC
DAC
Analog I/O
Analog I/O
Analog I/O
Analog I/O
Analog I/O
-
-
-
-
-
L2
M1
M2
N2
L1
DAC_vref_in
DAC_io
Display Interface Port
dip_data[0]
dip_data[1]
dip_data[2]
dip_data[3]
dip_data[4]
dip_data[5]
dip_data[6]
dip_data[7]
dip_data[8]
dip_data[9]
dip_data10]
dip_data[11]
dip_data[12]
dip_data[13]
dip_data[14]
dip_data[15]
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
PD
PU
PD
PD
PU
PD
PD
PD
PD
-
K16
K15
K14
K13
J13
L16
L15
L14
L13
M16
M15
M14
M13
N16
N15
N14
-
-
-
-
-
-
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
173
Packaging
Table 88. SCP220x Pinout
DIP
dip_data[16]
dip_data[17]
dip_data[18]
dip_data[19]
dip_data[20]
dip_data[21]
dip_data[22]
dip_data[23]
dip_RS
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Output 4 mA / 8 mA
Output 4 mA / 8 mA
Output 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Output 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
-
N13
P16
P15
R16
R15
T16
T15
T14
R14
R13
T13
R12
P12
N12
R11
N11
P11
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
-
-
-
-
-
-
-
-
dip_CSn0
PU
PU
PU
PU
-
dip_CSn1
dip_CSn2
dip_CSn3
dip_Wrn
dip_OEn
-
dip_pclk
-
dip_cpu_vsync
-
UART
uart_Rx
uart_Tx
uart_cts
uart_rts
MISCIF
MISCIF
MISCIF
MISCIF
Bi-dir. 2 mA / 4 mA
Bi-dir. 2 mA / 4 mA
Bi-dir. 2 mA / 4 mA
Bi-dir. 2 mA / 4 mA
-
-
-
-
A2
B1
B2
C1
SPI
spi_Clk
spi_CS
spi_Tx
MISCIF
MISCIF
MISCIF
MISCIF
MISCIF
MISCIF
MISCIF
MISCIF
Bi-dir. 2 mA / 4 mA
Bi-dir. 2 mA / 4 mA
Bi-dir. 2 mA / 4 mA
Bi-dir. 2 mA / 4 mA
Bi-dir. 2 mA / 4 mA
Bi-dir. 2 mA / 4 mA
Bi-dir. 2 mA / 4 mA
Bi-dir. 2 mA / 4 mA
-
C2
C3
C4
C5
D1
D2
D3
D4
PU
-
spi_Rx
-
spi1_Clk
spi1_CS
spi1_Tx
spi1_Rx
-
PU
-
-
Media Storage
SCP220x ICP Family, Rev.2.1
174
Freescale Semiconductor
Packaging
Table 88. SCP220x Pinout
sd_clk
sd_cmd
sd_D[0]
sd_D[1]
sd_D[2]
sd_D[3]
SDMMC
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
-
-
-
-
-
-
F1
F2
F3
G1
G2
G3
SDMMC
SDMMC
SDMMC
SDMMC
SDMMC
Audio
audio_clkr
audio_clkx
audio_dr
audio_dx
audio_fsr
audio_fsx
mclk
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
Bi-dir. 2 mA / 4 mA
Bi-dir. 2 mA / 4 mA
Bi-dir. 2 mA / 4 mA
Bi-dir. 2 mA / 4 mA
Bi-dir. 2 mA / 4 mA
Bi-dir. 2 mA / 4 mA
Bi-dir. 2 mA / 4 mA
-
-
-
-
-
-
-
P10
N10
M10
N9
M9
N8
M8
MP2TS
mp2ts_clk
MISCIF
MISCIF
MISCIF
MISCIF
Input
Input
Input
Input
n.a.
n.a.
n.a.
n.a.
E1
E2
E3
E4
mp2ts_valid
mp2ts_sync
mp2ts_data
USB
usb_phy_id
usb_phy_vbus
usb_phy_Plus
USB
USB
USB PAD
USB PAD
n.a.
n.a.
n.a.
n.a.
n.a.
PU
J5
J4
USB
USB PAD
K1
J1
usb_phy_Minus
usb_phy_res
USB
USB PAD
USB
USB PAD
J3
utmiotg_drvvbus
AUDIO
Bi-dir. 4 mA / 8 mA
R10
Smart Card
sc_io
sc_card_detect
sc_card_voltage
sc_fcb
SCCARD
SCCARD
SCCARD
SCCARD
SCCARD
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
-
-
H1
H2
H3
H4
H5
-
-
sc_clk
PU
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
175
Packaging
Table 88. SCP220x Pinout
sc_power_on
sc_rst
SCCARD
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
-
-
H6
J6
SCCARD
SDRAM
DMCLK
DMCLKn
A[0]
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
Output 4 mA / 8 mA
Output 4 mA / 8 mA
Output 4 mA / 8 mA
Output 4 mA / 8 mA
Output 4 mA / 8 mA
Output 4 mA / 8 mA
Output. 4 mA / 8 mA
Output 4 mA / 8 mA
Output 4 mA / 8 mA
Output 4 mA / 8 mA
Output 4 mA / 8 mA
Output 4 mA / 8 mA
Output 4 mA / 8 mA
Output 4 mA / 8 mA
Output 4 mA / 8 mA
Output. 4 mA / 8 mA
Output 4 mA / 8 mA
Output 4 mA / 8 mA
Output 4 mA / 8 mA
Output 4 mA / 8 mA
Output 4 mA / 8 mA
Output 4 mA / 8 mA
Output 4 mA / 8 mA
Output 4 mA / 8 mA
Output 4 mA / 8 mA
Output 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
A[1]
A[2]
A[3]
A[4]
A[5]
A[6]
A[7]
A[8]
A[9]
A[10]
A[11]
A[12]
CKE
WEn
CASn
RASn
CSn
BA[0]
BA[1]
DM[0]
DM[1]
DM[2]
DM[3]
DQS[0]
DQS[1]
DQS[2]
SCP220x ICP Family, Rev.2.1
176
Freescale Semiconductor
Packaging
Table 88. SCP220x Pinout
SDRAM
DQS[3]
DQ[0]
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
DQ[1]
DQ[2]
DQ[3]
DQ[4]
DQ[5]
DQ[6]
DQ[7]
DQ[8]
DQ[9]
DQ[10]
DQ[11]
DQ[12]
DQ[13]
DQ[14]
DQ[15]
DQ[16]
DQ[17]
DQ[18]
DQ[19]
DQ[20]
DQ[21]
DQ[22]
DQ[23]
DQ[24]
DQ[25]
DQ[26]
DQ[27]
DQ[28]
DQ[29]
DQ[30]
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
177
Packaging
Table 88. SCP220x Pinout
DQ[31]
System Signals & JTAG
Clkin
SDRAM
Bi-dir. 4 mA / 8 mA
-
-
OSC
OSC
Oscillator pad
n.a.
H16
J16
H11
P13
A3
A4
B5
B6
B3
B4
A1
P14
-
Clkout
Oscillator pad
n.a.
resetN
HPI
Input
-
hw_deep_secure
rtck
DIP
Input
-
MISCIF
MISCIF
MISCIF
MISCIF
MISCIF
MISCIF
MISCIF
DIP
Output 4 mA / 8 mA
-
tck
Input
Input
PU
Ntrst
PD
tdi
Input
PU
tdo
Output 4 mA / 8 mA
Input
-
tms
PU
testmode
bootmode (1)
pkg_opt0 (2)
pkg_opt1 (2)
pkg_opt2 (2)
jtag_sel_p0 (2)
jtag_sel_p1 (2)
jtag_sel_p2 (2)
No Connects
Input
PD
Input
-
-
-
-
-
-
-
SDRAM
SDRAM
SDRAM
MISCIF
MISCIF
MISCIF
Input
Input
-
Input
-
Input
-
Input
-
Input
-
SCP220x ICP Family, Rev.2.1
178
Freescale Semiconductor
Packaging
Table 88. SCP220x Pinout
NC
-
-
-
A5, A6, A7,
A8, A9,
A10, A11,
A12, A13,
A14, A15,
M7, N7, P5,
P6, P7, P8,
P9, R4, R5,
R6, R7, R8,
R9, T3, T4,
T5, T6, T7,
T8,T9,T10,
T11, T12,
A16, B16,
B15, B14,
B12, C16,
B13, C13,
D16, D15,
D14, D13,
E16, E15,
E14
Reserved Pins
reserved_1
HPI
HPI
HPI
HPI
HPI
HPI
HPI
HPI
HPI
HPI
HPI
HPI
HPI
HPI
HPI
NAND
DIP
DIP
NAND
Bi-dir. 2 mA / 4 mA
Bi-dir. 2 mA / 4 mA
Bi-dir. 2 mA / 4 mA
Bi-dir. 2 mA / 4 mA
Bi-dir. 2 mA / 4 mA
Bi-dir. 2 mA / 4 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 2 mA / 4 mA
Input
-
C14
C15
G11
H13
G12
H12
G14
G15
G16
F13
F14
F15
F16
E13
G13
-
reserved_2
reserved_3
reserved_4
reserved_5
reserved_6
reserved_7
reserved_8
reserved_9
reserved_10
reserved_11
reserved_12
reserved_13
reserved_14
reserved_15
reserved_16
reserved_17
reserved_18
reserved_19
PD
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 2 mA / 4 mA
-
-
-
-
PU
-
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
179
Packaging
Table 88. SCP220x Pinout
reserved_20
reserved_21
reserved_22
reserved_23
reserved_24
reserved_25
reserved_26
reserved_27
reserved_28
reserved_29
NAND
Bi-dir. 2 mA / 4 mA
Bi-dir. 2 mA / 4 mA
Bi-dir. 2 mA / 4 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 2 mA / 4 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
Bi-dir. 4 mA / 8 mA
PU
-
-
-
-
-
-
-
-
-
-
NAND
NAND
DIP
PU
PU
-
-
-
-
-
-
-
DIP
NAND
DIP
DIP
DIP
DIP
Notes:
(1) Must be pulled-up to VDD_DIP (100 KOhms 1/16 W 5% suggested) for correct operation on SCP2201
and SCP2207.
(2) Software queries the SCP2207 pkg_opt[2:0] and jtag_sel_p[2:0] pins to determine the SDRAM used
in the system. Currently CogniVue supports a 128 MB Micron mobile DDR SDRAM, and the pkg_opt[2:0]
and jtag_sel_p[2:0] must both be set to binary ‘101’ (decimal value 5). Consult the factory for interfacing
to any other memory.
Table 89. SCP220x Power Pin
Power Pin Name
Description
SCP2201 and
SCP2207
Ball #
G8, G9, H8, H9
J7, J10, K11, K12
J14
VDD_CORE
VDD_LP
Core supply
Low-power audio/video supply
Analog PLL supply
VDDA_PLL
VSSA_PLL
Return for PLL VDD
H14
(DO NOT CONNECT TO GROUND)
SDRAM core and EBI/SDRAM IO supply
Analog supply for crystal pad
Analog supply for USB
VDD_SDRAM
VDD_OSC
F7,L7
J15
K2
VDD_USB
VDDL_USB
VDDA_DAC
VDD_SENSOR
VDD_GPIO
USB core supply
-
Analog supply for internal DAC
Sensor Interface (SIF) and I2C IO supply
GPIO and keyscan supply
P1
F10
D12
SCP220x ICP Family, Rev.2.1
180
Freescale Semiconductor
Electrical Specifications
Table 89. SCP220x Power Pin
DIP IO supply
VDD_DIP
L10
D5
F4
VDD_MISCIF
VDD_SDMMC
VDD_AUDIO
VDD_SCCARD
VDD_NAND
VSS
MP2TS, JTAG, SPI, UART IO supply
SD/MMC IO supply
Audio IO supply
K9
G5
L4
Smart Card power supply
NAND Flash IO supply
Common ground
C11, C12, D6, D11,
F8, F9, G4, G6, H7,
H10, J8, J9, J11,
J12, K6, K8, L8, L9,
M4, R3
VSS_DAC
VSS_USB
VSSL_USB
VSS_OSC
Analog ground for internal DAC
Analog ground for USB
USB core ground
N1
J2
-
Analog ground for crystal pad
H15
7
Electrical Specifications
7.1
Absolute Maximum Rating
The following table describes the absolute maximum ratings for the SCP220x.
Table 90. SCP220x Absolute Maximum Rating
Item
Rating
Unit
I/O supply voltage
Core supply voltage
-0.2 to +3.3
-0.2 to +1.2
-0.3 to +3.3
-40 to +150
1
V
V
Input voltage for a signal pin
Storage temperature
V
°C
Short circuit duration (single output in high state to GND)
second
SCP220x ICP Family, Rev.2.1
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181
Electrical Specifications
7.2
Recommended Operating Ranges
The following table describes the recommended operating ranges for the SCP220x. Note that IO_VDD refers to the
subset of power supplies for the device I/Os as specified in Table 89. These supplies must be powered up before
VDD_CORE is powered up.
Table 91. SCP220x Recommended Operating Range
Item
Symbol
Min.
Typ.
Max.
Unit
Core supply voltage
Low power voltage
VDD_CORE
VDD_LP
0.9
1.0
1.1
V
I/O Supply Voltage
IO_VDD
2.7
2.7
3.0
3.0
1.8
3.0
1.8
3.3
3.3
3.3
3.3
V
V
Sensor Interface (SIF)
VDD_SENSOR
1.71
2.7
1.98
3.3
V
Analog PLL supply
SDRAM memory supply
Analog supply for USB
VDDA_PLL
VDD_SDRAM
VDD_USB
V
1.7
1.98
3.6
V
3.0
V
Analog supply for internal DAC
Operating temperature
VDDA_DAC
2.97
-40
3.63
105
V
Toperating
(Industrial
°C
Qualified Parts)
Notes:
1. IO_VDD = VDD_GPIO, VDD_DIP, VDD_AUDIO, VDD_NAND, VDD_SENSOR, VDD_SDMMC, VDD_MISCIF,
VDD_SCCARD, VDD_OSC
2.Sensor Interface supply (VDD_SENSOR) shall be part of the IO_VDD group when powered at 3.0V.
3.IO_VDD must always be on.
4. VDDA_PLL, VDD_LP must always be on.
5. VDD_DAC and VDD_USB must be turned on/off when VDD_CORE supply is turned on/off.
7.3
Thermal Characteristics
Table 92. SCP220x Thermal Characteristics
Air Velocity (m/s)
JA
JB
JC
0
25.5 °C/W
19.9 °C/W
8.5 °C/W
SCP220x ICP Family, Rev.2.1
182
Freescale Semiconductor
Electrical Specifications
7.4
DC Characteristics
The following table describes the DC characteristics of the SCP220x.
Table 93. SCP220x DC Characteristics
Item
Symbol
Min.
Typ.
Max.
Unit
Input Voltage, high
Input Voltage, low
V
IH 3.0
IL 3.0
VIH 1.8
IL 1.8
IH 3.0
2
-0.3
3.3
0.8
V
V
V
Input Voltage, high (VDD_SENSOR at 1.8V)
Input Voltage, low (VDD_SENSOR at 1.8V)
Sensor Voltage, high (VDD_SENSOR at 3.0V)
Sensor Voltage, low (VDD_SENSOR at 3.0V)
Output Voltage, high
1.17
1.98
0.63
3.3
V
V
-0.3
V
V
2.7
3.0
1.8
V
VIL 3.0
VOH
1.71
1.98
V
IO_VDD* 0.8
V
Output Voltage, low
VOL
0.4
11.9
27.8
39.6
7.8
V
Output Current High (VDD=3.0V)
IOH_2ma
IOH_4ma
IOH_8ma
IOL_2ma
IOL_4ma
IOL_8ma
CI
2.2
5.1
7.3
2.8
5.6
8.4
6.1
14.4
20.5
5
mA
mA
mA
mA
mA
mA
pF
Output Current Low (VDD=3.0V)
Input Capacitance
9.5
15
15.5
23.5
4
The following table describes the typical and maximum current consumption of the SCP220x.
Table 94. SCP220x Power Consumption
Description
Supply
Typ. (25°C)
Max. (105°C)
Unit
Core supply voltage + Low power voltage
VDD_CORE +
VDD_LP
300
520
mA
I/O Supply
IO_VDD1
VDDA_PLL
VDD_SDRAM
VDD_USB
18
9
30
20
mA
mA
mA
mA
Analog PLL supply
SDRAM memory supply
Analog supply for USB
222
1803
6 disabled
8 enabled
11 disabled
17 enabled
Analog supply for internal DAC (TVOut)
VDDA_DAC
0.6 disabled
39 enabled
1.0 disabled
55 enabled
mA
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
183
Electrical Specifications
Table 94. SCP220x Power Consumption
Notes:
1. IO_VDD is a combined total reading of VDD_GPIO, VDD_DIP, VDD_AUDIO, VDD_NAND, VDD_SENSOR, VDD_SDMMC,
VDD_MISCIF, VDD_SCCARD, VDD_OSC measured at 3.0 V, with no IO activity
2. Measured with an application dewarping a VGA image utilizing a 180° field of view lens.
3. Condition where SDRAM is continuously burst written or read.
SCP220x ICP Family, Rev.2.1
184
Freescale Semiconductor
Revision History
8
Revision History
Revision
Details of Change
Date
1
2
Initial Release
04/2014
03/2015
In Section 1.2.7, POWER Supply
• “1.0V core...I/O” changed to “1.8V...I/O Power.
In Table 2 (SCP220x Power Supply), Added one row for Pin name
VDD_SENSOR.
In Table 11 (Sensor Interface Timing), Added rows for symbol t6(1.8V)
and t7(1.8V).
In Table 91 (SCP220x Recommended Operating Range), Added row
for item Sensor Interface (1.8V) and also updated footnote 2.
In Table 93 (SCP220x DC Characteristics), Added two for item Input
Voltage, high (SIF 1.8V) and Input Voltage, low (SIF 1.8V).
2.1
• Editorial Changes
06/2015
• Table Caption moved to top for all tables.
SCP220x ICP Family, Rev.2.1
Freescale Semiconductor
185
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Document Number: SCP220x
Rev.2.1
06/2015
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