SE050C2HQ1/Z01SDZ [NXP]
Plug & Trust Secure Element;型号: | SE050C2HQ1/Z01SDZ |
厂家: | NXP |
描述: | Plug & Trust Secure Element |
文件: | 总30页 (文件大小:360K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SE050
Plug & Trust Secure Element
Rev. 3.0 — 12 May 2020
504930
Product data sheet
1 Introduction
The SE050 is a ready-to-use IoT secure element solution. It provides a root of trust at the
IC level and it gives an IoT system state-of-the-art, edge-to-cloud security capability right
out of the box.
SE050 allows for securely storing and provisioning credentials and performing
cryptographic operations for security critical communication and control functions. SE050
is versatile in IoT security use cases such as secure connection to public/private clouds,
device-to-device authentication or protection of sensor data.
SE050 has an independent Common Criteria EAL 6+ security certification up to OS level
and supports both RSA & ECC asymmetric cryptographic algorithms with high key length
and future proof ECC curves. The latest security measures protect the IC even against
sophisticated non-invasive and invasive attack scenarios.
The SE050 is a turnkey solution that comes with Java Card operating system and an
applet optimized for IoT security use cases pre-installed. This is complemented by a
comprehensive product support package, enabling fast time to market & easy design-
in with Plug & Trust middleware for host applications, easy to use development kits,
reference designs, and extensive documentation for product evaluation.
The SE050 is a product platform that comes in several pin-to-pin compatible product
variants, see [4].
Additional information on the integration can be found in several application notes on
www.nxp.com. Also see [3].
1.1 SE050 use cases
• Secure connection to public/private clouds, edge computing platforms, infrastructure
• Device-to-device authentication
• Secure data protection
• Secure commissioning support
• Secure CL/MIFARE/Wi-Fi interactions
• Device ID for blockchain
• Secure key storage
• Secure provisioning of credentials
• Ecosystem protection
1.2 SE050 target applications
• Smart Industry
• Smart Home
• Smart Cities
• Smart Supply Chains
NXP Semiconductors
SE050
Plug & Trust Secure Element
SE050
IoT APPLET
JCOP OS
14443
Host
NFC-DEVICE (reader)
MCU/MPU
SENSOR
MW
I2C
Plug & Trust
14443
I2C
7816
SDA SCL
SDA
SCL
I2C slave
LA LB
CLK
RST
IO2: SCL
IO:SDA
SW I2C master
aaa-032990
Figure 1.ꢀSE050 solution block diagram
Note: SE050 is designed to be used as a part of an IoT system. It works as an auxiliary
security device attached to a host controller. The host controller communicates with
SE050 through an I²C interface (with the host controller being the master and the SE050
being the slave). Besides the mandatory connection to the host controller, the SE050
device can optionally be connected to a sensor node or similar element through a
separate I²C interface. In this case, the SE050 device is the master and the sensor node
the slave. Lastly, SE050 has a connection for a native contactless antenna, providing a
wireless interface to an external device like a smartphone.
1.3 SE050 naming convention
The following table explains the naming conventions of the commercial product name
of the SE050 platform. Every SE050 product gets assigned a commercial name, which
includes application specific data.
The SE050 commercial names have the following format.
SE05yagddd/Zrrff
All letters are explained in Table 1 .
Table 1.ꢀSE050 commercial name format
Variable
Meaning
Values
Description
y
JCOP version
Applet Config
0
a
A
B
C
D
Configuration options with different key provisioning
options, see [4]
g
Temperature range
Delivery Type
standard operational ambient temperature
1 = -25 °C - 85 °C ,
1
2
2 = -40 °C - 105 °C
ddd
HQ1
HX2QFN20
mrrff
Letters and
numbers
NXP internal code to identify individual configurations
SE050
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SE050
Plug & Trust Secure Element
2 Features and benefits
2.1 Key benefits
• Plug & Trust for fast and easy design with complete product support package
• Easy integration with different MCU & MPU platforms and OS´ (Linux, RTOS,
Windows, Android, etc.)
• Turnkey solution ideal for system-level security without the need to write security code
• Secure credential injection for root of trust at IC level
• Secure, zero-touch connectivity to public & private clouds
• Real end-to-end security, from sensor to cloud
• Ready-to-use example code for each of the key use cases
2.2 Key features
The SE050 is based on NXP's Integral Security Architecture 3.0™ providing a secure
and efficient protection against various security threats. The efficiency of the security
measures is proven by a Common Criteria EAL6+ certification.
The SE050 operates fully autonomously based on an integrated Javacard operating
system and applet. Direct memory access is possible by the fixed functionalities of the
applet only. With that, the content from the memory is fully isolated from the host system.
• Built on NXP Integral Security Architecture 3.0 ™
• Uses advanced 40 nm silicon foundry technology
• CC EAL 6+ certified HW and OS as environment to run NXP IoT applications,
supporting fully encrypted communications and secured lifecycle management
• Effective protection against advanced attacks, including Power Analysis and Fault
Attacks of various kinds
• Multiple logical and physical protection layers, including metal shielding, end-to-end
encryption, memory encryption, tamper detection
• Support for RSA and ECC asymmetric cryptography algorithms, future proof curves
and high key length, e.g. Brainpool, Edwards and Montgomery curves
• Support for AES and DES symmetric cryptographic algorithms for encryption and
decryption
• HMAC, CMAC, SHA-1, SHA-224/256/384/512 operations
• Various options for key derivation functions, including HKDF, MIFARE KDF, PRF (TLS-
PSK)
• Optional extended temperature range for industrial applications (-40 °C to +105 °C)
• Small footprint HX2QFN20 package (3x3 mm)
• Standard physical interface I2C slave (High-speed mode, 3.4 Mbps), I2C master (Fast
mode, 400 kbps). Both can be active at the same time
• Dedicated CL wireless interface for IoT use cases simplifying configuration set-up,
maintenance in the field and late stage configuration
• Secured user flash memory up to 50 kB for secure data or key storage
• Support for SCP03 protocol (bus encryption and encrypted credential injection) to
securely bind the host with the secure element
• Support for applet level secure messaging channels to allow end-to-end encrypted
communication in multi-tenant ecosystems
SE050
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SE050
Plug & Trust Secure Element
2.3 Features in detail
Table 2.ꢀFeature Overview
Categories
Subcategory
Value
Standards
Security certification
JavaCard version
GlobalPlatform specification version
ECC
CC EAL6+ (HW+JCOP)
3.0.5
GP 2.3.1
Cryptography
ECDSA, ECDH, ECDHE, ECDAA,
EdDSA
MAC
Hash
HMAC, secure HMAC, CMAC
SHA-1, SHA-224, SHA-256, SHA-384,
SHA-512
Key derivation
HKDF, PBKDF2, PRF (TLS-PSK),
CMAC (MIFARE-AES-KDF)
AES
AES (128, 192, 256)
2K, 3K
3DES
RSA
RSA cipher for de-/encryption (up to
4096 bit)
Crypto curves
ECC
ECC NIST (192 to 521 bit)
Brainpool (160 to 512 bit)
Twisted Edwards Ed25519 /
Montgomery Curve25519
Koblitz (192 to 256 bit)
Barreto-Naehrig Curve 256 bit
50 kB
User memory
Memory reliability
Interfaces
up to 100 Mio write cycles / 25 years
High-speed mode (3.4 Mbps)
Fast Mode (400 kbit/s)
ISO14443-A PICC
I2C Slave
I2C Master
Contactless
Power saving modes
Temperature
Power-Down (with state retention)
< 500µA
Deep Power-Down (no state retention) <5 µA
Standard
-25 - 85 °C, see Naming Conventions
Extended
Plastic QFN
-40 - +105 °C, see Naming Conventions
3x3 mm (HX2QFN20)
Packaging
SE050
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SE050
Plug & Trust Secure Element
3 Functional description
3.1 Functional diagram
EdgeLock™ SE050 enablement
Plug and Trust Middleware
Android™, Linux, RTOS
Linux, Windows, macOS
Pre Integration
to Main
OS &
Use Case Based Example Codes
Android KeyMaster
MCU, MPU
PKCS11
OPC-UA
MQTT
TLS
Arm mbed™ TLS
OpenSSL
API
EdgeLock SE050
loT Applet
Java Card Operating System
Hardware
aaa-034211
Figure 2.ꢀSE050 functional diagram - example Open SSL
The SE050 uses I2C as communication interface. Section 4 gives more details. The
SE050 commands are wrapped using the Smartcard T=1 over I²C (T=1o I2C) protocol.
The detailed documentation of the SE050 commands (see [3]) and T=1 over I2C protocol
encapsulation is available on [1].
In order to simplify the product usage a host library which abstracts for SE050 commands
and T=1 over I2C protocol encapsulation is provided. The host library supporting various
platforms is available for download including complete source code on the SE050
website.
SE050 IoT applet features a generic file system capable of securely storing secure
objects and associated privilege management. All objects can either be stored in
persistent memory or in RAM with the capability to securely export and import them to be
stored in an externally provided storage. All secure objects feature basic file operations
such as write, read, delete and update.
3.1.1 Random number generator
The SE050 IoT Applet provides random numbers using an AIS20 compliant pseudo
random number generator (PRNG) with class DRG.3 generator initialized by a TRNG
compliant to AIS31 class PTG.2. The PRNG is implemented according to NIST
SP800-90A.
3.1.2 Supported secure object types
A secure object is an entry in the file system of SE050. Each secure object has certain
features and capabilities. The following secure object types are available:
• Symmetric Key (AES, 3DES)
• ECC Key
SE050
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SE050
Plug & Trust Secure Element
• RSA Key
• HMAC Key
• Binary File
• User ID
• Counter
• Hash-Extend register
3.1.2.1 Symmetric Key
The Symmetric Key object can securely store symmetric keys of AES 128, 192 and 256
bit, 2K3DES and 3K3DES. The following specific operations are available on symmetric
key objects:
• Encrypt
• Decrypt
• Derive
• CMAC
• Secure Import
3.1.2.2 ECC Key
The ECC Key object has the ability to securely store ECC keys of the following curves
and key sizes:
• ECC NIST curve: NIST P-192, NIST P-224, NIST P-256, NIST P-384, NIST P-521
• ECC Brainpool curve: 160 bit, 192 bit, 224 bit, 256 bit, 320 bit, 384 bit, 512 bit
• Curve25519 (Montgomery) and Bi-rationally Equivalent Twisted Edwards Curve
• ECC Koblitz curves: secp160k1, secp192k1, secp224k1, secp256k1
• ECC Barreto-Naehrig 256 bit curve
The following operations are available on ECC key objects (not all operations are
applicable to all curves):
• ECDSA/EdDSA Sign
• ECDSA/EdDSA Verify
• ECDH Generate Shared Secret/ECDHE
• ECDAA Sign
• ECDAA Verify
• Generate Key
• Secure Import
3.1.2.3 RSA Key
The RSA Key object has the ability to securely store RSA Keys up to 4096 bit. The
following specific operations are available on RSA key objects:
• RSA Sign
• RSA Verify
• RSA Encrypt
• RSA Decrypt
• RSA Generate Key
• Secure Import
SE050
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SE050
Plug & Trust Secure Element
3.1.2.4 HMAC Key object
An HMAC key object allows to securely store an HMAC key. The following operations are
supported on HMAC Key objects to compute an HMAC:
• Init
• Update
• Finalize
3.1.2.5 Binary file objects
Binary file objects are byte arrays of a generic type. As in a standard file system, the
values can be accessed using read/write operations.
3.1.2.6 Counter Objects
Counter objects are special kinds of binary file objects with specific functionality
interpreting the content of the file.
The supported operations for counters are:
• Set
• Get
• Increment
3.1.2.7 Hash-Extend register
A hash-extend register secure object stores a hash over all data provided to that secure
object. It therefore contains the complete history of values provided to that register since
last reboot or since creation and can be used for attestation purposes.
3.1.2.8 User ID secure object
User ID secure objects can be used to create sessions based on the User ID in cases
where multi-tenant support without cryptographic credential usage is required.
3.1.3 Access control
Each secure object can be linked to object specific access control policies. An access
control policy associates a user identified by an authentication with a set of privileges
such as read, write, …
To scale the functionality into a broad range of ecosystems, a set of different
authentication options is provided:
• User-ID based authentication
• Symmetric key based authentication with secure messaging
• Asymmetric key based authentication with secure messaging
At creation of a secure object, an optional set of policies is associated with that
secure object. Each policy assigns a set of allowed operations on that object to an
authentication object.
3.1.4 Sessions and multi-threading
The SE050 IoT applet is prepared for ecosystems where multi-threading and multi-
tenant use cases are needed on APDU level. To enable that, the applet supports 2
simultaneous sessions that can span full secure messaging sessions, self-authenticated
SE050
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SE050
Plug & Trust Secure Element
APDUs for tenants not requiring long-lasting sessions and on top one default session for
single tenant use cases .
3.1.5 Attestation and trust provisioning
SE050 applet comes with a set of trust provisioned root credentials allowing the owner of
the device to securely attest all generated secure keys. Next to that, a customer has the
possibility to define own attestation keys.
Attestation certificates signed by an attestation CA are included in certain SE050
configurations as documented in [4].
3.1.6 Application support
For specific ecosystems, SE050 IoT applet has built-in crypto features to simplify the
deployment of specific use cases such as
• MIFARE SAM functionality
• Wifi password protection
• ECC-Key and RSA-Key based cloud connectivity
• Secure Sensor readout using I2C master
• Remote attestation and trust provisioning
• Platform Configuration Registers
3.2 Credential Storage & Memory
Within SE050, all credentials and secure objects are stored inside a dynamic file
structure. At creation, a user has to associate a file identifier with the object created. This
identifier is then used in subsequent operations to access the object. The number of
objects that can be allocated is only limited by the available memory in the system. After
usage, objects can be deleted and the associated memory is freed up again.
There is also the possibility to create transient objects. Transient objects have an object
descriptor stored in non-volatile memory, but the object content is stored in RAM.
Together with the import/export functionality of SE050, transient objects can be used
securely store secret keys in a remote memory system.
3.3 Ease of use configuration
Some generic SE050 variants are offered pre-configured for ease of use and can be
used during development phase and in the field. With this customers have all keys pre-
injected in SE050 that are required for the main use cases as e.g. cloud onboarding. For
more information, see: [4]
3.4 Startup behaviour
If a supply voltage is applied to pins Vin, Vcc within the specified supply voltage operating
range or a RF field according to ISO/IEC 14443 is applied to antenna pins LA, LB the IC
boots up.
During boot the IC checks for active interface according list below (in the order of the list):
• ISO7816: If interface available for this product type, check CLK to be toggling, then wait
for RST to be high
SE050
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SE050
Plug & Trust Secure Element
• ISO14443: If interface available for this product type, check of RF field on LA, LB
antenna pins
• I2C: If interface available for this product type, check if both I2C_SDA, I2C_SCL pins
are at high level (internal weak pull-up active)
• The chosen interface is the only interface the SE050 will receive commands for
processing. To select a different interface the IC needs to be reset.
4 Communication interfaces
4.1 I2C Interfaces
The SE050 has one I2C interface supporting slave and one I2C interface supporting
master mode.
The I2C slave interface is the main communication interface of the device and is used by
the host controller to send arbitrary APDUs to the device. It supports clock frequencies
up to 3.4 MHz when operated in High-Speed Mode (HS). The I2C interface is using the
Smartcard T=1 over I2C protocol.
The default slave address of the SE050 is configured to 0x48.
slave address
1
0
0
1
0
0
0
R/W
aaa-037450
Figure 3.ꢀSlave address
The I2C master interface is supposed to be used with slave devices that need to be
securely written and read. This interface features a maximum SCL clock rate of 400 kHz.
4.1.1 Supported I2C frequencies
The SE050 I2C slave interface supports the I2C high-speed mode with a maximum SCL
clock of up to 3.4 MHz when clock stretching is enabled.
In case clock stretching is disabled the maximum supported SCL clock frequency is
1.7 MHz.
Clock stretching is enabled by default. Clock stretching will occur for frequencies
higher than 600 kHz. In case clock stretching is not supported by the I2C master a
dedicated configuration with disabled clock stretching has to be used to ensure the above
mentioned maximum clock frequency.
The SE050 I2C master interface supports maximum 400 kHz SCL clock frequency.
4.2 ISO7816 and ISO14443 Interface
The SE050 supports in addition to the I2C interface ISO78161 and ISO14443-A
Smartcard interfaces. For the ISO7816 interface SmartCard protocols T=0 and T=1 are
1
ISO7816 is not enabled in generic SE050 configurations (see [4], AN12436) but available on customer
request.
SE050
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SE050
Plug & Trust Secure Element
supported. For the ISO14443 interface protocol T=CL is used. The supported resonance
input capacitance is 56 pF. In addition one additional GPIO pad IO2 is supported.
The RST_N pin can only be used as external reset source if the ISO7816 interface is
enabled. If only the I2C interface is enabled the RST_N pad has no effect. If the SE050 is
kept in reset state the current consumption is as defined for idle, see Table 12.
5 Power-saving modes
The device provides two power-saving operation modes. The Power-down mode (with
state retention) and the Deep Power-down mode (no state retention). These modes are
activated via pad ENA (Deep Power-down mode) or by the SW (Power-down mode).
5.1 Power-down mode
The Power-down mode has the following properties:
• All internal clocks are frozen
• CPU enters power-saving mode with program execution being stopped
• CPU registers keep their contents
• RAM keeps its contents
The SE050 enters into Power-down mode by receiving "End of APDU session request"
via the T=1 over I2C protocol. In Power-down mode, all internal clocks are frozen. The
IOs hold the logical states they had at the time Power-down mode was activated.
To exit from the Power-down mode an external interrupt edge must be triggered by a
falling edge on I2C_SDA2.
5.2 Deep Power-down mode
The SE050 provides a special power-saving mode offering maximum power saving. This
mode is activated by pulling enable PIN (ENA) to a logic zero level.
While in Deep Power-down mode the internal power and VOUT is switched off completely
and only the I2C pads stay supplied.
To leave the Deep Power-down mode pad ENA has to be pulled up to to a logic „1" level.
For usage of Deep Power-down mode the SE050 must be supplied via pin VIN and pin
VCC needs to be supplied by pin VOUT
.
6 Ordering information
6.1 Ordering options
Table 3.ꢀSE050 Ordering information
12NC
Type number
SE050 Variant
SE050A1
Orderable part number
SE050A1HQ1/Z01SGZ
SE050A2HQ1/Z01SHZ
9353 867 22472
9353 869 84472
SE050A1HQ1/Z01SG
SE050A2HQ1/Z01SH
SE050A2
2
In case ISO7816 is enabled a reset signal on RST_N exits the Power-down mode. After wake-up from
Power-down mode via RST_N the device is in idle mode (see Table 12)
SE050
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SE050
Plug & Trust Secure Element
12NC
Type number
SE050 Variant
SE050D2
SE050B1
Orderable part number
SE050D2HQ1/Z01PAZ
SE050B1HQ1/Z01SEZ
SE050B2HQ1/Z01SFZ
SE050C1HQ1/Z01SCZ
SE050C2HQ1/Z01SDZ
935401587472
9353 869 85472
9353 869 86472
9353 869 87472
9353 869 88472
SE050D2HQ1/Z01PA
SE050B1HQ1/Z01SE
SE050B2HQ1/Z01SF
SE050C1HQ1/Z01SC
SE050C2HQ1/Z01SD
SE050B2
SE050C1
SE050C2
Table 4.ꢀSE050 Ordering information for development kit
12NC
Type number
Description
9353 832 82598
OM-SE050ARD
SE050 Arduino-compatible development kit ,
SE050C configuration
6.2 Ordering SE050 samples
Samples can be ordered from NXP Semiconductors via nxp.com using the "Buy Direct"
button on the product information page for SE050. Note that NXP Semiconductors
can provide up to five pieces free of charge. Larger quantities have to be ordered
commercially.
6.3 Configuration
Detailed information about the configuration and available variants of the SE050 are
available in a separate NXP Application Note, see [4]
SE050
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SE050
Plug & Trust Secure Element
7 Pinning information
7.1 Pinning
7.1.1 Pinning HX2QFN20
terminal 1
index area
ISO 14443 LB
n.c.
1
2
3
4
5
15 VOUT
14 ISO 7816 RST_N
13 ISO 7816 CLK
12 VIN
ISO 7816 IO1
SE050
n.c.
n.c.
11 ENA
aaa-031924
Transparent top view
Figure 4.ꢀPin configuration for HX2QFN20 (SOT1969-1)
Note: Terminal 1 index area is marked on the bottom with a notch on the center pad and
on the top with a printed dot.
Table 5.ꢀPin description HX2QFN20
Symbol
Pin
1
Description
ISO 14443 LB
n.c.
ISO14443 Antenna Connection, if not used connect to VSS
2
not connected
ISO 7816 IO1
3
ISO 7816 IO or I2C master SDA, if not used n.c (recommended) or connect to
VCC
n.c.
4
not connected
n.c.
5
not connected
n.c.
6
not connected
n.c.
7
not connected
n.c.
8
not connected
I2C_SDA
I2C_SCL
ENA
VIN
9
I2C slave data, if not used n.c.
I2C slave clock, if not used n.c.
Deep Power-down mode enable, if not used then connect to VCC
power supply voltage input for I2C pads and ISO 7816/14443 interface and
logic supply in case Deep Power-down mode is used
10
11
12
SE050
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SE050
Plug & Trust Secure Element
Symbol
Pin
Description
ISO 7816 CLK
ISO 7816 RST_N
VOUT
13
14
15
ISO 7816 clock input, if not used then n.c (recommended) or connect to VCC
ISO 7816 reset input low active, if not used then connect to Vcc or Vss
supply voltage output to be connected with pad VCC on PCB level, if Deep
Power-down mode is used. N. c. if not used.
ISO 7816 IO2
16
ISO7816 IO2 pad or I2C master SCL. I if not used n.c (recommended) or
connect to VOUT
.
ISO 14443 LA
VCC
17
18
ISO14443 antenna connection, if not used then connect to VSS
logic and ISO7816/ISO14443 interface power supply voltage input, to be
connected with pad VOUT on PCB level, if Deep Power-down mode to be used
VSS
n.c.
19
20
ground
not connected
The center pad of the IC is not connected, although it is recommended to connect it to
ground for thermal reasons.
Reference voltage for ISO 1816 IO1, CLK, RST is VCC; for I2C SDL and SCL reference
voltage is VIN and for IO2 it is VOUT
.
8 Package
9 Marking
SE050 is offered in HX2QFN20 package. The dimensions are 3 mm x 3 mm x 0,32 mm
with a 0,4 mm pitch.
Please refer to the package data sheet [2], SOT1969-1.
Table 6.ꢀMarking codes
Type number
Marking code
Sx050...
Line A: S50
Line B: **** (**** = 4-digit Batch code)
Line C: nDyww
D: RHF-2006 indicator
n: Assembly Center
Y: Year
WW: Week
10 Packing information
10.1 Reel packing
The SE050 product is available in tape on reel.
Table 7.ꢀReel packing options
Symbol
Parameter
7" tape on reel
Numbers of units per reel
HX2QFN20
3000
SE050
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11 Electrical and timing characteristics
The electrical interface characteristics of static (DC) and dynamic (AC) parameters for
pads and functions used for I2C are in accordance with the NXP I2C specification (see
[1]).
12 Limiting values
Table 8.ꢀLimiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS (ground = 0 V).
Symbol
Parameter
Conditions
Min
Max
Unit
VIN, Vcc
supply voltage
-0.3
+6
V
[1]
VI
input voltage
input current
output current
latch-up current
any signal pad
-0.3
+6
V
II
pad I2C_SDA, I2C_SCL
pad I2C_SDA, I2C_SCL
VI < 0 V or VI > VIN, Vcc
-
-
-
10
mA
mA
mA
kV
IO
10
Ilu
100
± 2.0
[2]
[3]
[4]
Vesd_hbm
electrostatic discharge voltage
(Human Body Model)
pads VCC, VSS, RST_N,
I2C_SDA, I2C_SCL, IO1, IO2,
CLK
Vesd_cdm
electrostatic discharge voltage
(Charge Device Model)
pads VCC, VSS, RST_N,
I2C_SDA, I2C_SCL, IO1, IO2,
CLK
± 500
V
Ptot
Tstg
Total power dissipation
Storage temperature
-
600
mW
°C
-55
+125
[1] Maximum supported supply voltage is 6 V. The SE050 is characterized for the specified operating supply voltage range of 1.62 V to 3.6 V. In case of
supply voltages above 3.6 V, Deep Power-down mode current <5 µA is not guaranteed.
[2] MIL Standard 883-D method 3015; human body model; C = 100 pF, R = 1.5 kΩ; Tamb = -40 °C to +105 °C.
[3] JESD22-C101, JEDEC Standard Field induced charge device model test method.
[4] Depending on appropriate thermal resistance of the package.
13 Recommended operating conditions
The SE050 is characterized by its specified operating supply voltage range of 1.62 V to
3.6 V.
Table 9.ꢀRecommended operating conditions
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIN, VCC
Supply voltage
Nominal supply voltage 1.62
1.8
3.6
V
[1]
VI
DC input voltage on digital inputs and
digital I/O pads
-
-0.3
VCC/VIN
V
[2]
+0.3
7.5
H
Field strength
Contactless interface
operation
1.5
-40
A/m
°C
Tamb
Operating ambient temperature[3]
+105
SE050
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[1] Maximum supported supply voltage is 6 V. In case of supply voltages above 3.6 V, Deep Power-down mode current <5 µA is not guaranteed.
[2] IO1, CLK, RST has VCC as reference, SDA, SCL, IO2 and ENA has VIN as reference
[3] All product properties and values specified within this data sheet are only valid within the operating ambient temperature range.
1.62 V
3.6 V
aaa-015200_
Maximum supported supply voltage is 6 V. In case of supply voltages above 3.6 V, Deep Power-
down mode current <5 µA is not guaranteed.
Figure 5.ꢀCharacteristic supply voltage operating range
14 Characteristics
14.1 DC characteristics
Measurement conventions
Testing measurements are performed at the contact pads of the device under test. All
voltages are defined with respect to the ground contact pad VSS. All currents flowing into
the device are considered positive.
14.1.1 General and General Purpose I/O interface
Table 10.ꢀElectrical DC characteristics of Input/Output: IO1/IO2. Conditions: VCC = 1.62 V to 3.6 V (see ; VSS = 0 V;
Tamb = -40 °C to + 105 °C, unless otherwise specified
In Table 10 VCC means for IO1 voltage on VCC pin, for IO2 voltage on VIN pin
Maximum supported supply voltage is 6 V. In case of supply voltages above 3.6 V, Deep Power-down mode current <5 µA
is not guaranteed.
Symbol
VIH
Parameter
Conditions
Min
Typ
Max
Unit
V
HIGH level input voltage
LOW level input voltage
0.7 VCC
-0.3
VCC + 0.3
0.25 VCC
-20
VIL
V
IIH
HIGH level input current in
"weak pull-up" input mode
0.7 VCC ≤ VI ≤ VCC
Test conditions for the
maximum absolute
value: IIH(max):VI = 0.7
VCC, VCC=VCC(max)
μA
IIL
LOW level input current
0 V ≤ VI ≤ 0.3 VCC
;
-50
μA
μA
Test conditions for the
maximum
absolute value:
IIL(max):VI = 0 V, VCC
VCC(max)
=
[1]
ITL
HIGH-to-LOW transition
input current (only "quasi-
bidirectional" mode)
0.3 VCC < VI ≤ VCC
;
-250
Test conditions for the
maximum absolute
value: VI = 0.5 VCC, VCC
= VCC(max)
SE050
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Symbol
Parameter
Conditions
Min
Typ
Max
Unit
II
Input current in "weak pull-up" 0 V ≤ VI ≤ VCC; Test
0
-50
μA
input mode
conditions for the
maximum absolute
value: II(max):VI = 0 V,
VCC = VCC(max)
IILIH
Leakage input current at input VCC < VI ≤ VCC + 0.3 V;
voltage beyond VCC in "weak -40 °C ≤
20
μA
pull-up" input mode
Tamb ≤ +105 °C;
Test conditions: VI = VCC
+ 0.3
V;
VCC = VCC(max)Tamb
+105 °C
=
IILIL
Leakage input current at input -0.3 V ≤ VI < 0 V; -40 °C
-50
μA
μA
μA
voltage below VSS in "weak
pull-up" input mode
≤ Tamb
≤
+30 °C
Test conditions: VI = -0.3
V;
VCC= VCC(max)Tamb
+30 °C
=
-0.3 V ≤ VI < 0 V;+30 °C
≤ Tamb
-1000
≤
+105 °C
Test conditions: VI = -0.3
V;
VCC= VCC(max)Tamb
+105 °C
=
IILIHQ
Leakage input current at
input voltage beyond VCC
(only in "quasi-bidirectional"
mode)
VCC < VI ≤ VCC + 0.3 V;
-40 °C ≤
100
Tamb≤ +105 °C
Test conditions: VI = VCC
+
0.3 V;VCC = VCC(max)
;
Tamb = +105 °C
IILILQ
Leakage input current at input -0.3 V ≤ VI < 0 V; -40 °C
-120
μA
μA
V
voltage below VSS (only in
"quasi-bidirectional"
≤ Tamb
≤
+30 °C
mode)
Test conditions: VI = -0.3
V;
VCC = VCC(max)Tamb
=
+30 °C
-0.3 V ≤ VI < 0 V;+30 °C
≤ Tamb
-1000
≤
+105 °C
Test conditions: VI = -0.3
V;
VCC = VCC(max)Tamb
=
+105 °C
[2]
VOH
HIGH level output voltage
IOH = -20 μA;
0.7 VCC
SE050
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Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOL
LOW level output voltage
IOL = 1.0 mA
IOL = 0.5 mA
0.3
V
0.15 VCC
[1] IO1/IO2 source a transition current when being externally driven from HIGH to LOW. This transition current (ITL) reaches its maximum value when the
input voltage VI is approximately 0.5 VCC. Current IIL is tested at input voltage VI= 0.3 V.
[2] External pull-up resistor 20 kΩ to VCC assumed. The worst case test condition for parameter VOH is present at minimum VCC
.
V
I
I
I
I
I
IH1maxu
IL1maxu
V
CC
0
-0.3 V
0
V
V
IH1min
IL1max
I
I
ILI1maxI
IHI1maxI
aaa-029327
Figure 6.ꢀInput characteristic of RST_N
V
l
l
l
l
ILIHmax
l
l
IHmin
Imin
-0.3 V 0 V
V
V
V
ILmax
IHmin
CC
V
0
+0.3 V
CC
l
l
l
IHmax
ILmax
Imax
l
aaa-007192
ILILmax
Figure 7.ꢀInput characteristic of IO1/IO2
I
I
V
I
I
ILIH1max
I
I
I
IH1max
IL1max
I1max
-0.3 V
0
0 V
V
V
V
+0.3 V
CC
IL1max
IH1min
V
CC
I
I
I1min
IL1min
I
aaa-007191
lLlL1max
Figure 8.ꢀInput characteristic of CLK when the IC is not in reset
SE050
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I
I
V
I
I
lLIH2max
I
I
IH2min
I2min
V
V
V
0 V
-0.3 V
0
IL2max
IH2min
CC
V
+0.3 V
CC
I
I
I2max
I
IH2max
IL2max
I
ILIL2max
aaa-007190
Figure 9.ꢀInput characteristic of CLK during IC reset
14.1.2 I2C Interface
Table 11.ꢀElectrical DC characteristics of I2C pads SDA, SCL. Conditions: VCC, VIN = 1.62 V to 3.6 V; VSS = 0 V; Tamb
= -40 °C to + 105 °C, unless otherwise specified*
Maximum supported supply voltage is 6 V. In case of supply voltages above 3.6 V, Deep Power-down mode current <5 µA
is not guaranteed.
SCL, SDA pads are in open-drain mode.
Symbol
VIH
Parameter
Conditions
Min
Typ
Max
Unit
V
HIGH level input voltage
LOW level input voltage
Input hysteresis voltage
0.7 VIN
-0.3
VIN + 0.3
0.25 VIN
VIL
V
VHYS
VOL(OD)
-
0.081 V
0
V
Low level output voltage
(open-drain mode)
IOL = 3.0 mA
0.4
V
IOL(OD)
Low level output current
(open-drain mode)
VOL = 0.6 V
VIO = 0 V
0.6
mA
IWPU
IILIH
weak pull-up current
-265
-180
0.27
-70
15
µA
µA
Leakage input current high
level
VSDA = 3.6 V, VSCL = 3.6
V
14.1.3 Power consumption
Table 12.ꢀElectrical characteristics of IC supply voltage VCC; VSS = 0 V; Tamb = -40 °C to +105 C
Symbol
Supply
VCC
Parameter
Conditions
Min
Typ
Max
Unit
supply voltage range
VCC = 1.62 - 3.6 V
1.62
1.80
3.6
V
operating mode: Idle mode
operating mode: typical CPU
no coprocessor active
[1]
IDD
fCPU= 48 MHz, fMST = 96 MHz
CPU in idle mode
4.4
6.5
7
mA
mA
AES coprocessor active
(AES 48 MHz)
7.5
SE050
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Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Public Key cryptography Coprocessor CPU in idle mode
active
14.4
16.1
mA
(96 MHz)
DES coprocessor active
(DES 48 MHz)
CPU in idle mode
6.5
7.6
mA
IDD (PD-
supply current Power-down mode
(ISO7816 clock-stop)
VCCmin ≤ VCC ≤ VCCmax; Clock to
input CLK stopped, Tamb= 25 °C
430
3
480
5
μA
μA
μA
ISO7816)
IDDD (DPD) supply current Deep Power-down
mode
IDD (PD-I2C) supply current I2C Power-down mode VCCmin ≤ VCC ≤ VCCmax; Clock
VCCmin ≤ VIN ≤ VCCmax; Tamb
=
25 °C
450
500
(I2C wake-up source)
to input SCL stopped, Tamb=
25 °C SDA, SCL pads in pull-up
Typical value with VCC= 1.8 V
[1] Maximum current consumption with concurrent AES and Public Key Cryptography 19 mA.
14.2 AC characteristics
Table 13.ꢀNon-volatile memory timing characteristics
Conditions: VCC = 1.62 V to 3.6 V; VSS = 0 V; Tamb = -40 °C to +105 °C, unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ[1]
Max Unit
ms
[2]
tEEP
tEEE
tEEW
tEER
NEEC
FLASH erase + program time
2.3
0.9
1.4
FLASH erase time
ms
FLASH program time
FLASH data retention time
ms
Tamb = +55 °C
25
years
cycles
FLASH endurance (maximum
number of programming cycles
applied to the whole memory
block performed by NXP static
and dynamic wear leveling
algorithm)
20 × 106 100 ×
106
[1] Typical values are only referenced for information. They are subject to change without notice.
[2] Given value specifies physical access times of FLASH memory only.
Table 14.ꢀElectrical AC characteristics of I2C_SDA, I2C_SCL, and RST_N[1]; VCC = 1.8 V ± 10 % or 3 V ± 10 % V; VSS
0 V; Tamb = -40 °C to + 105 °C
=
SCL, SDA pads in open-drain mode.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Input/Output: I2C_SDA, I2C_SCL in open-drain mode
[2]
[2]
[2]
trIO
I/O Input rise time
I/O Input fall time
I/O Output fall time
Input/reception mode
Input/reception mode
1
μs
μs
μs
tfIO
1
tfOIO
Output/transmission mode; CL
= 30 pF
0.3
SE050
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Symbol Parameter
Conditions
Min
Typ
Max
Unit
fCLK
External clock frequency in I2C tCLKW, Tamb and VCC in their
applications specified limits
-
3.4
MHz
[3]
[4]
tPD
Power down duration time (I2C CPU clock = 48 MHz
wake-up)
67
97
μs
μs
pF
μs
tWKPD
CPIN
tENalt
Wake-up from power down
duration time (I2C wake-up)
CPU clock = 48 MHz
Pin capacitances RST_N,
I2C_SDA, /I2C_SCL
Test frequency = 1 MHz;
Tamb = 25 °C
-
10.5
[5]
ENA low time and Vout, Vcc
low time for entering deep
power down mode
2
Ron
Iout
Resistance of power switch
Tamb=105 °C, Iload=25 mA,
Vin=1.62 V
1.1
25
Ohm
mA
maximum current driving
capability of pin Vout
Tamb=105 °C
Inputs: RST_N (active only if ISO7816 UART interface is enabled)
tRW
Reset pulse width (RST_N low)
without entering Power-down
mode
40
400
μs
tRDSLP
tWKP
Reset pulse width (RST_N low)
to enter Power-down mode
500
-
μs
μs
Wake-up time from Power-
down mode
fCLKmin < fCLK < fCLKmax
8
10
tWKPIO
Pad LOW time for wake-up
from Power-down mode
level triggered ext.int.
edge triggered ext.int.
-
8
8
10
10
-
μs
μs
μs
-
tWKPRST RST_N LOW time for wake-up
from Power-down mode
40
CPIN
Pin capacitances RST_N,
I2C_SDA, /I2C_SCL
Test frequency = 1 MHz; Tamb
= 25 °C
-
10.5
pF
[1] All appropriately marked values are typical values and only referenced for information. They are subject to change without notice.
[2] tr is defined as rise time between 30 % and 70 % of the signal amplitude.
tf is defined as fall time between 70 % and 30 % of the signal amplitude.
[3] Wakeup from power down: if clock stretching disabled and I2C_SCL=400 kHz; the wakeup time will not be sufficient under the rare condition where host
sends the first command during the time where SE is just entering power down; in this case the SE will send an R block to request retransmission from the
host
[4] Wakeup from power down: if clock stretching disabled and I2C_SCL=1 MHz; the wakeup time will not be sufficient to receive the first host command; the
SE will send an R block to request retransmission from the host
[5] Low glitches below 0.4 V on pin ENA and Vin, Vout, Vcc larger than 30 ns cause Power-On-Reset, respectively entering deep power-down mode.
SE050
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V
high
70 % level
30 % level
0.5 V
CLK (et al)
DD
V
low
t
CLKW
tf
tf
tf
tr
tr
tr
CLK
RST
IO
CLK
RST
IO
1/f
CLK
aaa-037451
1) During AC testing the inputs RST_N, I2C_SDA, I2C_SCL are driven at 0 V to +0.3 V for a LOW
input level and at VCC -0.3 V to VCC for a HIGH input level. Clock period and signal pulse (duty
cycle) timing is measured at 50 % of VCC
.
2) tr is defined as rise time between 30 % and 70 % of the signal amplitude. tf is defined as fall
time between 70 % and 30 % of the signal amplitude.
Figure 10.ꢀExternal clock drive and AC test timing reference points of I2C_SDA, I2C_SCL,
and RST_N (see 1) and 2)) in open-drain mode
Table 15.ꢀElectrical AC characteristics of IO1, IO2, CLK and RST_N (ISO7816 interface)
Conditions: VCC = 1.8 V ± 10 % or 3 V ± 10 % V; VSS = 0 V; Tamb = -40 °C to +105 °C, unless otherwise specified. Typical
values are only referenced for information. They are subject to change without notice.
Symb Parameter
ol
Conditions
Min
Typ
Max
Unit
Input/Output: IO1/IO2
[1]
[2]
trIO
I/O Input rise time
Input/reception mode
1
μs
μs
μs
μs
μs
[3]
[2]
0.25 x
tIOWx_min
[1]
[2]
tfIO
I/O Input fall time
Input/reception mode
1
[3]
[2]
0.25 x
tIOWx_min
[2]
trOIO
I/O Output rise time
I/O Output fall time
Output/transmission mode; CL
= 30 pF
0.1
0.1
[2]
tfOIO
Output/transmission mode; CL
= 30 pF
μs
Inputs: CLK and RST_N
[4]
fCLK
External clock frequency
tCLKW, tamb and VCC in their
specified limits
0.85
40
11.5
60
MHz
%
in ISO/IEC 7816 UART
applications
tCLKW
Clock pulse width i.r.t. clock
period (positive pulse duty
cycle of CLK)
[5]
trCLK
tfCLK
CLK input rise time
CLK input fall time
[6]
[6]
[2]
[6]
[2]
trRST
tfRST
RST_N input rise time
RST_N input fall time
400
400
μs
μs
[2]
[7]
SE050
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[1] At minimum IO1 input signal HIGH or LOW level voltage pulse width of 3.2 μs. This timing specification applies to ISO7816 configurations down to a
minimum etu duration of 16 CLK cycles at a maximum CLK frequency of 5 MHz (TA1=0x96, (Fi/Di)=(512/32)), for example.
[2] tr is defined as rise time between 10 % and 90 % of the signal amplitude.
[3] At minimum IO1 input signal HIGH or LOW level voltage pulse width of less than 3.2 μs. This timing specification applies to ISO7816 configurations
beyond the conditions listed in note [2], down to a minimum etu duration of 8 CLK cycles at a maximum CLK frequency of 5 MHz (TA1=0x97, (Fi/
Di)=(512/64)), for example. An 8 CLKs/etu @ fclk = 5 MHz configuration results in tIOWx_min = 1.6 μs, and in a time of 400 ns for trIO_max and tfIO_
max, matching the (Fi/Di)=(512/64) speed enhancement requirements of ETSI TS 102 221.
[4] ISO/IEC 7816 I/O applications have to supply a clock signal to input CLK in the frequency range of 1 MHz to 10 MHz nominal. A ± 15 % tolerance range
yields the allowed limits of 0.85 MHz and 11.5 MHz.
[5] During AC testing the inputs CLK, RST_N, and IO1 are driven at 0 V to +0.3 V for a LOW input level and at VCC − 0.3 V to VCC for a HIGH input level.
Clock period and signal pulse (duty cycle) timing is measured at 50 % of VCC, see Figure 18.
[6] The maximum CLK rise and fall time is 10 % of the CLK period 1/fCLK - with the following exception: In the CLK frequency range of 1 MHz to 5 MHz the
maximum allowed CLK rise and fall time is 50 ns, if 10 % of the CLK period is shorter than 50 ns.
[7] The ETSI TS102 221/GSM 11.1x specifications specify a maximum reset signal (RST_N) rise time and fall time of 400,000 μs, respectively.
Note: tf is defined as fall time between 90 % and 10 % of the signal amplitude.
Table 16.ꢀElectrical AC characteristics of LA, LB; Conditions: Tamb = -40 °C to 105 °C, unless otherwise specified
Conditions: Tamb = -25 °C to +85 °C, unless otherwise specified.
Symbol Parameter
Conditions
Typ[1]
Max
Unit
Input/Output: LA, LB
[2]
CLALB
Pin capacitance LA, LB
Bare die (SO28 empty package
ground-off)
[3] [4]
[4]
Configured for antenna input with
56 pF capacitance
VLA,LB = 2.1 V (rms)
VLA,LB = 0.3 V (rms)
54.3
50.1
pF
Test frequency = 13.56 MHz;
Tamb= 25 °C
[2]
[3] [4]
[5]
RLALB
Configured for antenna input with
56 pF capacitance. Test frequency
= 13.56 MHz;
VLA,LB = 2.1 V (rms)
level triggered ext.int.
0.913
13.56
kΩ
Tamb= 25 °C
fLALB
Operating frequency LA, LB
MHz
[1] Typical values (± 10 %) are only referenced for information. They are subject to change without notice.
[2] The CLALB and RLALB values stated here assume a parallel RC equivalent circuit for the chip.
[3] The value stated here was measured at estimated start of chip operation and is comparable to the values stated in other SmartMX3 family member data
sheets.
[4] Measured with sine wave at LA, LB.
[5] Parameter is valid in contactless ISO14443 compliant operation valid only.
14.3 I2C Bus Timings
Parameters defined in this chapter replace the parameter definitions of I2C bus, for
specification see [4].
SDA
50 %
50 %
SCL
50 %
50 %
t
t
HDr;DAT50
HDf;DAT50
aaa-036486
Figure 11.ꢀI2C Bus Timings
SE050
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Table 17.ꢀI2C Bus Timing Specification
Symbol
Parameter
Condition
Min
Max
Unit
[1]
[2]
[1]
[2]
tHDf;DAT50
data hold time
Fast mode
8
ns
50% SCL - 50% SDA level
tHDr;DAT50
tHDf;DAT50
tHDr;DAT50
data hold time
Fast mode
Hs mode
Hs mode
24
8
ns
ns
ns
50% SCL - 50% SDA level
data hold time
50% SCL - 50% SDA level
data hold time
9
50% SCL - 50% SDA level
[1] tHDf;DAT50, as defined in Figure 11, replaces parameter tHD;DAT defined in [4]
[2] tHDr;DAT50, as defined in Figure 11, replaces parameter tHD;DAT defined in [4]
14.4 EMC/EMI
EMC and EMI resistance according to IEC 61967-4.
15 Abbreviations
Table 18.ꢀAbbreviations
Acronym
AES
APDU
CL
Description
Advanced Encryption Standard
Application Protocol Data Unit
Contactless
CLK
CC
External clock signal input contact pad
Common Criteria
CMAC
CRC
CRI
Cipher-based MAC
Cyclic Redundancy Check
Cryptography Research Incorporated
Digital Encryption Standard
Differential Power Analysis
Digital Signature Standard
Evaluation Assurance Level
Elliptic Curve Cryptography
Electromagnetic compatibility
Electro Magnetic Immunity
Fast-Mode
DES
DPA
DSS
EAL
ECC
EMC
EMI
FM
FM+
GP
Fast-Mode+
Global Platform
GPIO
HS
General-purpose input/output
High-Speed-Mode
SE050
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Product data sheet
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NXP Semiconductors
SE050
Plug & Trust Secure Element
Acronym
HKDF
HMAC
HW
Description
HMAC-based Extract-and-Expand Key Derivation Function
Keyed-Hash Message Authentication Code
Hardware
IC
Integrated Circuit
I2C
Inter-Integrated Circuit
Input/Output
I/O
IoT
Internet of Things
JCOP
LA
Java Card Open Platform
ISO 14443 Antenna Pad
ISO 14443 Antenna Pad
Near Field Communication
Message Authentication Code
Microcontroller unit
LB
NFC
MAC
MCU
MPU
MW
Microprocessor
Middleware
OS
Operating System
NIST
PCB
PKI
National Institute for Standards and Technology
Protocol Control Byte
Public Key Infrastructure
Pseudo Random Function
Random Access Memory
Rivest-Shamir-Adleman
Reset
PRF
RAM
RSA
RST
SAM
SCL
SDA
SPA
SFI
Secure Access Module
Serial clock
Serial data
Simple Power Analysis
Single Fault Injection
Secure Hash Algorithm
Software
SHA
SW
TLS
VCC
Transport Layer Security
Supply Voltage Input
Voltage Input
VIN
VOUT
VSS
Voltage Output
Ground
SE050
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© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 3.0 — 12 May 2020
504930
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NXP Semiconductors
SE050
Plug & Trust Secure Element
16 References
[1] NXP SE05x T=1 Over I2C Specification User manual, document number UM11225.
Available on NXP website
[2] SOT1969-1; HX2QFN20; Reel packing and package information. Available on NXP
website
[3] SE050 IoT Applet APDU Specification, document number AN 12413. Available on
NXP website
[4] SE050 configurations Application Note, document number AN12436. Available on
NXP website
SE050
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 3.0 — 12 May 2020
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NXP Semiconductors
SE050
Plug & Trust Secure Element
17 Revision history
Table 19.ꢀRevision history
Document ID
504930
Release date
2020-05-12
Data sheet status
Change notice
Supersedes
Product data sheet
504913
Modifications
• updated: Section 7.1.1
• updated: Table 6
• updated: Section 2.3
• added Section 3.4
• added Figure 3
• added Section 14.3
• updated Section 12
• updated Section 14.1.3
• updated Section 14.2
• updated Section 14.1.2
• updated Section 13
504913
504912
504911
20190607
20190510
20181122
Objective data sheet
504912
504911
Objective data sheet
Objective data sheet
SE050
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 3.0 — 12 May 2020
504930
26 / 30
NXP Semiconductors
SE050
Plug & Trust Secure Element
18 Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Product [short] data sheet
Qualification
Production
This document contains data from the preliminary specification.
This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
18.2 Definitions
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences
of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes
no representation or warranty that such applications will be suitable
for the specified use without further testing or modification. Customers
are responsible for the design and operation of their applications and
products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications
and products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with
their applications and products. NXP Semiconductors does not accept any
liability related to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications or products, or
the application or use by customer’s third party customer(s). Customer is
responsible for doing all necessary testing for the customer’s applications
and products using NXP Semiconductors products in order to avoid a
default of the applications and the products or of the application or use by
customer’s third party customer(s). NXP does not accept any liability in this
respect.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not
give any representations or warranties, expressed or implied, as to the
accuracy or completeness of such information and shall have no liability
for the consequences of use of such information. NXP Semiconductors
takes no responsibility for the content in this document if provided by an
information source outside of NXP Semiconductors. In no event shall NXP
Semiconductors be liable for any indirect, incidental, punitive, special or
consequential damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the removal or replacement
of any products or rework charges) whether or not such damages are based
on tort (including negligence), warranty, breach of contract or any other
legal theory. Notwithstanding any damages that customer might incur for
any reason whatsoever, NXP Semiconductors’ aggregate and cumulative
liability towards customer for the products described herein shall be limited
in accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
SE050
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 3.0 — 12 May 2020
504930
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NXP Semiconductors
SE050
Plug & Trust Secure Element
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
18.4 Licenses
ICs with DPA Countermeasures functionality
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
NXP ICs containing functionality
implementing countermeasures to
Differential Power Analysis and Simple
Power Analysis are produced and sold
under applicable license from Cryptography
Research, Inc.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor
tested in accordance with automotive testing or application requirements.
NXP Semiconductors accepts no liability for inclusion and/or use of non-
automotive qualified products in automotive equipment or applications. In
the event that customer uses the product for design-in and use in automotive
applications to automotive specifications and standards, customer (a) shall
use the product without NXP Semiconductors’ warranty of the product for
such automotive applications, use and specifications, and (b) whenever
customer uses the product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at customer’s own
risk, and (c) customer fully indemnifies NXP Semiconductors for any liability,
damages or failed product claims resulting from customer design and use
of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
18.5 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
MIFARE — is a trademark of NXP B.V.
FabKey — is a trademark of NXP B.V.
JCOP — is a trademark of NXP B.V.
EdgeLock — is a trademark of NXP B.V.
SE050
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Product data sheet
Rev. 3.0 — 12 May 2020
504930
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NXP Semiconductors
SE050
Plug & Trust Secure Element
Tables
Tab. 1.
Tab. 2.
Tab. 3.
Tab. 4.
SE050 commercial name format .......................2
Feature Overview ..............................................4
SE050 Ordering information ............................10
Tab. 12. Electrical characteristics of IC supply
voltage VCC; VSS = 0 V; Tamb = -40 °C to
+105 C ...........................................................18
Tab. 13. Non-volatile memory timing characteristics ..... 19
Tab. 14. Electrical AC characteristics of I2C_SDA,
I2C_SCL, and RST_N; VCC = 1.8 V ± 10 %
SE050
Ordering
information
for
development kit ...............................................11
Pin description HX2QFN20 ............................. 12
Marking codes .................................................13
Reel packing options .......................................13
Limiting values ................................................ 14
Recommended operating conditions ...............14
Tab. 5.
Tab. 6.
Tab. 7.
Tab. 8.
Tab. 9.
or 3 V ± 10 % V; VSS = 0 V; Tamb = -40 °C
to + 105 °C ..................................................... 19
Tab. 15. Electrical AC characteristics of IO1, IO2,
CLK and RST_N (ISO7816 interface) ............. 21
Tab. 16. Electrical AC characteristics of LA, LB;
Conditions: Tamb = -40 °C to 105 °C, unless
otherwise specified ..........................................22
Tab. 17. I2C Bus Timing Specification .......................... 23
Tab. 18. Abbreviations ...................................................23
Tab. 19. Revision history ...............................................26
Tab. 10. Electrical DC characteristics of Input/Output:
IO1/IO2. Conditions: VCC = 1.62 V to 3.6 V
(see ; VSS = 0 V; Tamb = -40 °C to + 105
°C, unless otherwise specified ........................ 15
Tab. 11. Electrical DC characteristics of I2C pads
SDA, SCL. Conditions: VCC, VIN = 1.62 V
to 3.6 V; VSS = 0 V; Tamb = -40 °C to + 105
°C, unless otherwise specified* .......................18
Figures
Fig. 1.
Fig. 2.
SE050 solution block diagram ...........................2
SE050 functional diagram - example Open
SSL ....................................................................5
Slave address ................................................... 9
Fig. 7.
Fig. 8.
Input characteristic of IO1/IO2 ........................ 17
Input characteristic of CLK when the IC is not
in reset ............................................................ 17
Input characteristic of CLK during IC reset ......18
Fig. 3.
Fig. 4.
Fig. 9.
Pin
configuration
for
HX2QFN20
Fig. 10. External clock drive and AC test timing
reference points of I2C_SDA, I2C_SCL, and
RST_N (see 1) and 2)) in open-drain mode .... 21
Fig. 11. I2C Bus Timings ..............................................22
(SOT1969-1) ....................................................12
Characteristic supply voltage operating
range ............................................................... 15
Input characteristic of RST_N ......................... 17
Fig. 5.
Fig. 6.
SE050
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Product data sheet
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NXP Semiconductors
SE050
Plug & Trust Secure Element
Contents
1
1.1
1.2
1.3
2
2.1
2.2
2.3
Introduction ......................................................... 1
14.2
14.3
14.4
15
16
17
AC characteristics ............................................19
I2C Bus Timings ..............................................22
EMC/EMI ..........................................................23
Abbreviations .................................................... 23
References .........................................................25
Revision history ................................................ 26
Legal information ..............................................27
SE050 use cases .............................................. 1
SE050 target applications ..................................1
SE050 naming convention .................................2
Features and benefits .........................................3
Key benefits .......................................................3
Key features ...................................................... 3
Features in detail ...............................................4
Functional description ........................................5
Functional diagram ............................................ 5
Random number generator ............................... 5
Supported secure object types ..........................5
Symmetric Key .................................................. 6
ECC Key ............................................................6
RSA Key ............................................................6
HMAC Key object ..............................................7
Binary file objects .............................................. 7
Counter Objects .................................................7
Hash-Extend register .........................................7
User ID secure object ........................................7
Access control ................................................... 7
Sessions and multi-threading ............................ 7
Attestation and trust provisioning .......................8
Application support ............................................ 8
Credential Storage & Memory ........................... 8
Ease of use configuration ..................................8
Startup behaviour .............................................. 8
Communication interfaces ................................. 9
I2C Interfaces .................................................... 9
Supported I2C frequencies ................................9
ISO7816 and ISO14443 Interface ..................... 9
Power-saving modes ........................................ 10
Power-down mode ...........................................10
Deep Power-down mode .................................10
Ordering information ........................................ 10
Ordering options .............................................. 10
Ordering SE050 samples ................................ 11
Configuration ....................................................11
Pinning information .......................................... 12
Pinning .............................................................12
Pinning HX2QFN20 ......................................... 12
Package ..............................................................13
Marking ...............................................................13
Packing information ..........................................13
Reel packing ....................................................13
Electrical and timing characteristics ...............14
Limiting values ..................................................14
Recommended operating conditions .............. 14
Characteristics .................................................. 15
DC characteristics ............................................15
General and General Purpose I/O interface .....15
I2C Interface ....................................................18
Power consumption ......................................... 18
18
3
3.1
3.1.1
3.1.2
3.1.2.1
3.1.2.2
3.1.2.3
3.1.2.4
3.1.2.5
3.1.2.6
3.1.2.7
3.1.2.8
3.1.3
3.1.4
3.1.5
3.1.6
3.2
3.3
3.4
4
4.1
4.1.1
4.2
5
5.1
5.2
6
6.1
6.2
6.3
7
7.1
7.1.1
8
9
10
10.1
11
12
13
14
14.1
14.1.1
14.1.2
14.1.3
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© NXP B.V. 2020.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 12 May 2020
Document number: 504930
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