SE5562 [NXP]
Switched-mode power supply control circuit; 开关电源的控制电路
| 型号： | SE5562 |
| 厂家： | 
NXP |
| 描述： | Switched-mode power supply control circuit |
| 文件： | 总29页 (文件大小：298K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
DESCRIPTION
PIN CONFIGURATION
The NE/SE5562 is a single-output control circuit for switched-mode
power supplies. This single monolithic IC contains all control and
protection features needed for full-featured switched-mode power
supplies.
D, F, N Packages
1
2
20
19
18
17
16
15
14
13
12
11
FEED FORWARD
GROUND
OUTPUT
C
T
The 100mA source/sink output is designed to drive power FETs
directly. The associated output logic is designed to prevent double
pulsing or cross-conduction current spiking on the output.
3
DEMAG OVERVOLT IN
R
T
4
EXTERNAL MOD IN
V
S
5
DUTY CYCLE CONTROL
REMOTE ON/OFF
C DELAY
All of the control and protect features work cycle-by-cycle up to the
maximum operating frequency of 600kHz.
6
OUT INVERT CONTROL
7
CURRENT SENSE
V
I
For ease of interface, all digital inputs are TTL or CMOS compatible.
FEEDBACK VOLTAGE
AUX COMP HYSTERESIS
8
The NE5562 is supplied in 20-pin glass/ceramic (Cerdip), plastic
DIP, and plastic SO packages. The NE grade part is characterized
and guaranteed over the commercial ambient temperature range of
0°C to +70°C and junction temperature range of 0°C to +85°C. The
SE5562 is supplied in the glass/ceramic (Cerdip) package. The SE
grade part is characterized and guaranteed over the ambient
temperature range of -55 to +125°C and junction temperature range
of -55 to +135°C.
9
AUX COMP INPUT
V
Z
ERROR AMP OUT
EXTERNAL SYNC IN
10
TOP VIEW
SL00388
Figure 1. Pin Configuration
• Auxiliary comparator, with adjustable hysteresis
• Loop fault protection
FEATURES
• Demagnetization/overvoltage protection
• Duty cycle adjust and clamp
• Feed-forward control
• Stabilized power supply
• Temperature-compensated reference source
• Sawtooth generator
• External synchronization
• Pulse width modulator
• Total shutdown after adjustable number of overcurrent faults
• Soft-start
• Remote on/off switching
• Current limiting (2 levels)
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
0 to +70°C
ORDER CODE
NE5562D
DWG #
1021B
20-Pin Plastic Small Outline (SO) Package
20-Pin Plastic Dual In-Line Package (DIP)
20-Pin Ceramic Dual In-Line Package (CERDIP)
0 to +70°C
NE5562N
SOT146-1
SOT146-1
-55°C to +125°C
SE5562F
1
1994 Aug 31
853-0811 13721
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
BLOCK DIAGRAM
1
11
FEEDFORWARD
EXTERNAL
SYNC IN
+
+
–
+
S
CLOCK
Q
TIME
DELAY
OSC
LATCH
3
2
–
+
R
DELAYED
CLOCK
OFF
DEMAG/OV
IN
OSCILLATOR
18
0V
OFF
ON
3.80V
ON
1.5V
DEMAG/OV
COMP
REMOTE
ON/OFF
6
NORM
–
+
ON/OFF
COMP
S
ERROR
AMP
Q
OUTPUT
19
PWM
COMP
OUTPUT
LATCH
OUT
10
3.80V
+
+
–
–
–
–
POWR
OUTPUT
NOR
FEEDBACK
VOLTAGE
R
8
OUTPUT
INVERT
CONTROL
OC1
ERROR
AMP
15
–
+
NORM
0.955V
–
+
OVERCURRENT 1
COMP
LOOP FAULT
COMP
2k
0.528V
0.645V
CURRENT
SENSE
EXTERNAL
MOD
14
4
OVERCURRENT 2
COMP
IN
0.955V
–
+
DUTY CYCLE
CONTROL
5
OC2
–
+
GND
20
0.955V
R
NORM
SLOW
START
COMP
V
S
17
START/
OC1
0C2
POWER
SUPPLY
CKTS
CLOCK
STOP
Q
LATCH
S
V
Z
9
OC1-2
LATCHES
LV STOP
OC CHARGE PUMPS
1:1
Q
0.528V
0.645V
3.80V
1:1
TRIP
SHUT
DOWN
LATCH
3.80V
NORM
–
+
C
DELAY
16
S
R
LOW BULK
OC ACCUM
COMP
+V
OC1
11µA
+V
V
I
7
NORM
BULK
+
–
SENSE 3.80V
COMP
OC2
AUXILIARY
COMP
HYSTERESIS
+
–
1µA
80µA
AUXILIARY
COMP
INPUT
13
3.80V
12
SL00389
Figure 2. Block Diagram
2
1994 Aug 31
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
Supply
voltage-fed mode (Pin 17)
V
16
30
V
S
I
current-fed mode (Pin 7)
Output transistor
mA
mA
CC
100
output current
Sync (Pin 11)
V
S
V
Z
V
S
V
S
V
Z
V
Z
V
S
V
S
V
Z
V
S
V
S
V
V
V
V
V
V
V
V
V
V
V
Duty cycle control (Pin 5)
Remote on/off (Pin 6)
Output invert control (Pin 15)
Feedback pin (Pin 8)
C
(Pin 16)
DELAY
External mod in (Pin 4)
Feed-forward (Pin 1)
FF
Demag/overvoltage in (Pin 18)
Current sense (Pin 14)
80Low supply sense and hysteresis
(Pins 12, 13)
T
T
T
Operating junction temperature
Storage temperature range
135
-65 to +150
300
°C
°C
°C
J
STG
Lead soldering temperature (10sec)
SOLD
NOTES:
1. Ground Pin 20 must always be the most negative pin.
2. For power dissipation, see the application section which follows.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
RATING
UNIT
Supply
voltage-fed
current-fed
10 to 16
15
V
mA
T
A
Ambient temperature range
NE grade
0 to +70
°C
°C
SE grade
-55 to +125
T
J
Junction temperature range
NE grade
0 to +85
°C
°C
SE grade
-55 to +135
DC AND AC ELECTRICAL CHARACTERISTICS
V
CC
= 12V, specifications apply over temperature, unless otherwise specified.
SE5562
Typ
NE5562
TEST
PINS
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
Min
Max
Min
Typ
Max
Internal reference
V
REF
V
REF
Reference voltage
Reference voltage
Temperature stability
Internal
Internal
Internal
T =25°C
3.76
3.72
3.80
3.8
30
3.84
3.90
3.76
3.80
3.8
30
3.84
V
V
A
Over temp.
3.725
3.870
ppm/°C
µV/1000
hrs
Long-term stability
Internal
0.5
0.5
3
1994 Aug 31
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
DC AND AC ELECTRICAL CHARACTERISTICS (Continued)
V
CC
= 12V, specifications apply over temperature, unless otherwise specified.
SE5562
Typ
NE5562
TEST
PINS
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
Min
Max
Min
Typ
Max
Reference
I =7mA,
T =25°C
A
L
V
Zener voltage
9
7.35
7.25
7.60
7.75
7.80
7.35
7.20
7.6
7.75
7.78
V
Z
Z
I =7mA,
L
V
Zener voltage
9
9
V
Over temp.
∆V / ∆T
Temperature stability
I <1mA
L
50
50
ppm/°C
Z
Low supply shutdown
Comparator threshold
voltage
Internal
T =25°C
A
8.30
8.45
8.75
8.30
8.45
8.75
V
Comparator threshold
voltage
Internal
Internal
Over temp.
8.00
25
8.45
50
8.90
8.00
8.00
25
8.45
50
8.90
800
V
Hysteresis
mV
Oscillator
Frequency range,
minimum
1, 2,
3, 11
R =42.7kΩ,
T
C =0.47µF
T
f
60
80
60
80
Hz
MIN
Frequency range,
maximum
1, 2,
3, 11
R =2.87kΩ,
T
C =380pF
T
f
600
600
kHz
MAX
f =52kHz,
O
1, 2,
3, 11
R =16kΩ
T
and C =0.0015µF,
T
Initial accuracy
Voltage stability
48.6
54
59.4
500
48.6
54
59.4
500
kHz
T =25°C
A
1, 2, 3,
11, 17
10V<V <18V
-215
300
-215
300
ppm/V
S
1, 2,
3, 11
Temperature stability
Sawtooth peak voltage
ppm/°C
1
2, 3
2, 3
2, 3
2, 3
11
T =25°C
A
5.00
4.80
1.25
1.0
5.25
5.25
1.70
1.7
5.40
5.60
2.00
2.1
5.00
4.80
1.25
1.25
2.0
5.25
5.25
1.70
1.7
5.40
5.60
2.00
2.0
V
V
V
V
V
V
Over temp.
Sawtooth valley voltage
T =25°C
A
Over temp.
Sync. in high level
Sync. in low level
2.0
V
Z
V
Z
11
0.0
0.8
0.0
0.8
(Sourced),
Sync. in bias current
11
1
0.50
2
10.0
0.50
2
10.0
µA
V
11
<0.8V
Feed-forward ratio,
maximum
Feed-forward duty cycle
reduction
V =2V ,
FF Z
T =25°C
A
1
1
9
1
11
6
13.5
13.5
19
22
11
8
13.5
19
22
%
%
V
Over temp.
Feed-forward reference
voltage
V
Z
V
S
V
Z
V
S
Feed-forward bias current
2.5
50.0
2.5
50.0
µA
4
1994 Aug 31
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
DC AND AC ELECTRICAL CHARACTERISTICS (Continued)
V
CC
= 12V, specifications apply over temperature, unless otherwise specified.
SE5562
Typ
NE5562
TEST
PINS
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
Min
Max
Min
Typ
Max
Error amp
I
Input bias current
8
8, 10
10
1.0
86
5.0
1.0
86
5.0
µA
dB
V
BIAS
A
DC open-loop gain
High output voltage
Low output voltage
R >100kΩ
60
5
60
5
VOL
L
V
V
I
=1mA
OH
OL
SOURCE
10
I
=1mA
2.0
2.0
V
SINK
PSRR from V and V
Internal
f <300kHz
O
-40
8
-40
8
dB
Z
S
Small-signal gain bandwidth
product
BW
MHz
Feedback resistor range
Output sink current
1
240
10
1
240
10
kΩ
I
I
V8=V10=5V
mA
SINK
V8=3V,
V10=1V
Output source current
Sawtooth feedthrough
5
5
mA
mV
SOURCE
A =100,
V
200
200
0% duty cycle
PWM comparator and modulator
@V
f=300kHz
<,
COMP
Minimum duty cycle
19
19
0
0
%
%
@V >,
COMP
Maximum duty cycle
f=300kHz,
V15=0V
95
98
55
95
98
55
f=15kHz to
200kHz,
A
CC
Duty cycle
10, 19
41
49
41
49
%
V
IN
=0.472 V
Z
Propagation delay to
output
t
I
I
2, 19
4
V
=0
400
400
ns
PD
15
Bias current, external
modulator input
(Sourced)
(Sourced)
0.20
20
0.20
20
µA
BIAS
BIAS
Bias current, duty cycle
control
5
5
0.20
20
0.20
20
µA
Soft-start trip voltage
.910
0.955
0.990
0.922
0.955
0.988
V
Remote on/off (shutdown)
Output enabled
6
6
0
2
0.80
0
2
0.80
V
V
Output disabled
V
Z
V
Z
I
Bias current
6
1
10
1
10
µA
V
BIAS
V
Maximum input voltage
Delay to output(s)
6
V
Z
V
Z
IN
6, 19
400
400
ns
Current limit comparator(s)
Shutdown, OC2
14
14
14
16
16
16
16
.593
.486
0.645
0.528
0.5
.697
.570
50
0.593
0.486
0.645
0.528
0.5
0.697
0.570
50
V
V
Minimum duty cycle, OC1
I
Bias current
(Sourced)
µA
µA
µA
µA
V
BIAS
OC
C
C
charge current
charge current
-18.2
-770
0.4
-13
-6.5
-250
4.0
-18.2
-770
0.8
-13
-7.8
-330
2.0
1
DELAY
DELAY
OC2
-550
1.4
-550
1.4
C
C
Discharge current
Shut off trip level
V12=V
Z
DELAY
DELAY
T =25°C
A
3.75
3.86
3.97
3.75
3.86
3.97
5
1994 Aug 31
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
DC AND AC ELECTRICAL CHARACTERISTICS (Continued)
V
CC
= 12V, specifications apply over temperature, unless otherwise specified.
SE5562
Typ
NE5562
TEST
PINS
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
Min
Max
Min
Typ
Max
Auxiliary comparator with shutdown
I
Bias current
12
12
(Sourced)
1
3.80
10
10
1
3.80
10
10
µA
V
BIAS
Threshold voltage
Discharge current
Hysteresis
3.69
5
3.91
3.69
5
3.91
C
12
V
IN
=3V
mA
mV
DELAY
12, 13
10
10
Demagnetization overvoltage comparator
I
Bias current
18
18
18
2
10
2
10
µA
V
BIAS
Threshold voltage
Hysteresis
3.62
3.80
10
3.91
3.69
3.80
10
3.91
mV
Output stage
V
High output voltage
19
19
I
=100mA
V -2.5 V -1.9
V -2.5 V -1.9
V
V
OH
SOURCE
S
S
S
S
I
=2mA
0.16
0.4
2.0
0.16
0.4
2.0
SINK
I
I
=100mA,
T =25°C
SINK
19
19
1.4
1.4
V
V
V
OL
Low output voltage
A
=100mA,
over temp.
SINK
2.25
2.25
I
I
max
19
19
19
19
100
100
100
100
mA
mA
ns
SINK
max
SOURCE
t
t
Rise time
Fall time
C =2000pF
160
80
160
80
R
L
C =2000pF
L
ns
F
Supply current/voltage
10V<V <16V
S
I
Supply current
Input voltage
17
(Voltage-fed mode),
V <V
9
15
9
15
mA
V
CC
I
S
I =15mA,
I
V
7, 17
(Current-fed mode)
14.2
15.3
16.7
14.2
600
15.3
16.7
S
V =meter
S
Operating frequency range for all functions but feed-forward working cycle-by-cycle
R =42.7kΩ,
T
f
Minimum frequency
Maximum frequency
All
All
60
80
60
80
Hz
MIN
C =0.47µF
T
R =2.87kΩ,
T
f
600
1000
1000
kHz
MAX
C =380pF
T
3
2
10
10
T
= 25°C
A
R
= 2.5kΩ
T
R
R
= 5kΩ
T
T
= 10kΩ
R
R
= 20kΩ
= 40kΩ
T
T
1
0
10
10
2
2
3
3
4
10
10
5 x 10
10
5 x 10
(pF)
SL00390
C
T
Figure 3. Frequency vs R , C NE/SE5562
T
T
6
1994 Aug 31
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
0
–30
–60
–90
–120
–150
–180
TA = 25°C
PHASE
40
CLOSED-LOOP GAIN
30
20
10
0
100
1k
10k
100k
FREQUENCY
1M
10M
SL00391
Figure 4. Error Amplifier Closed-Loop Response
100
90
80
70
60
50
40
30
20
10
0
V
T
= 12V
CC
= 25°C
A
1
2
3
4
5
6
7
8
9
10
PWM INPUT VOLTAGE (V)
SL00392
Figure 5. Duty Cycle vs PWM Input Voltage
100
90
80
70
60
50
40
30
20
10
0
T
= 25°C
A
5
6
7
8
9
10
11
12
13
14
15
FEED-FORWARD VOLTAGE (V)
SL00393
Figure 6. Duty Cycle vs Feed-forward Voltage
7
1994 Aug 31
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
22
20
18
16
14
12
10
8
T
= 25°C
A
6
4
2
0
0
2
4
6
8
10
12
14
16
18
20
22
24
SUPPLY VOLTAGE (PIN 17)(V)
SL00394
Figure 7. Current-Feed Characteristics
22
20
18
16
14
12
10
8
T
= 25°C
A
6
4
2
0
0
2
4
6
8
10
12
14
16
18
20
22
24
SUPPLY VOLTAGE (PIN 17)(V)
SL00395
Figure 8. Voltage-Feed Characteristics
8
1994 Aug 31
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
THE NE/SE5562 THEORY OF OPERATION
t
ON
SW
WHERE
d
+
T
INTRODUCTION
PERIOD
L
SW
Switched-mode power conversion relies on the principle of pulsed
energy storage in an inductive or capacitive element. Capacitive
switched converters are typically used with low power systems for
which only tens of milliamperes are required. Medium and high
power converters tend to use inductive storage elements as shown
in Figures 9-11 with which a single switch may be moved around to
create step-up (flyback) positive or negative polarity and step-down
(forward or buck) conversion from a fixed-voltage source. The
relationship between input and output voltage in each case is
controlled by the switching on-to-off ratios, which is termed duty
cycle. Duty cycle modulation is the common factor in this basic type
of power control mechanism. By adding a high-gain operational
amplifier, having one input tied to a stable DC reference voltage,
configured in a negative feedback loop to maintain a constant output
voltage as shown in Figure 12, the switched-mode controller
becomes a dynamic voltage regulator. It is this single-switch
topology that is most readily adapted to the NE/SE5562 SMPS
Control IC.
+
+
D
V
B
V
+
dV
IN
C
IN
O
R
OUT
L
δ
COM
–
SL00398
Figure 11. Forward Converter (Single Inductor) Step Down
I
REGULATED
OUTPUT
SW
L
+
+
I
L
V
IN
PWM
UNREGULATED
DC
C
R
L
–
–
The ability to switch inductor currents at rates up to 600kHz with
state-of-the-art power FETs makes the design of small, efficient
switching power converters an attainable reality. Protective features
such as programmable slow-start and cycle-by-cycle current limiting
allow safe, maintenance-free power supplies to be mass-produced
at reduced cost to the manufacturer. Integrated technology makes
long-term reliability a predictably achievable goal.
V
+
REF
A
R
R
2
–
F
SW
D
O
R
1
–
SL00399
* V
IN
1 * d
L
V
C
IN
R
O
V
+
L
OUT
δ
Figure 12. The Forward (Buck) Converter (V
= V (δ))
IN
OUT
+
COM
SL00396
Di
Dt
E
L
+
MAGNETIZATION
CURRENT
Figure 9. Negative Output Flyback Converter
SWITCH
CURRENT
LOAD CURRENT
L
D
O
+
+
DIODE
CURRENT
V
IN
SW
V
V
+
C
IN
R
–
O
L
OUT
1 * d
AVERAGE
INDUCTOR
CURRENT
δ
TOTAL
INDUCTOR
CURRENT
COM
SL00400
SL00397
Figure 10. Positive Output Flyback Converter
Figure 13. PWM Switching Waveforms
9
1994 Aug 31
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
FEED-
FORWARD
EXT.
SYNC
1
11
+
ACTIVE LOW
0.8V
+
I
O
V
Z
(5.25V)
+7.50V
–
+
V
H
R
2
28k
S
3
2
1
TIME BASE
SIGNAL
FF
(1.70V)
C
T
–
R
3
3k
R
TO DELAY
CIRCUIT
+
CURRENT
STEERING
SAWTOOTH
GENERATOR
DISCH.
+3.80V
+
–
–
–
–
OUTPUT TO
LATCH RESET
VOLTAGE
FEEDBACK
ERROR
AMP
8
10
PWM
COMPARATOR
SL00401
Figure 14.
THE NE/SE5562 THEORY OPERATION
The Sawtooth Oscillator
The sawtooth oscillator consists of a gated charge-discharge
capacitor circuit with threshold comparators setting the peak and
valley voltages of the ramp. The resistor divider R1-3 is supplied
THE PULSE WIDTH MODULATOR AND ERROR
AMPLIFIER
The PWM consists of a multi-input voltage comparator (Figure 15)
having its positive input tied to the sawtooth ramp voltage and the
various negative inputs referenced to ORed control signal nodes.
The primary control signal is the error amplifier output voltage node
which sets the active duty cycle termination point of the PWM output
waveform. As the error amplifier input signal derived from the power
supply load voltage varies, for instance in a negative direction, the
amplifier output moves upward, raising the PWM comparator toward
longer duty cycles at the output on Pin 19. The start-up sequence
begins with zero voltage at the input to the error amplifier. Since this
could signal an open feedback loop, the loop fault comparator on
Pin 8 clamps the PWM duty cycle until the feedback voltage
exceeds 0.955V. A second comparator monitors the duty cycle
control, Pin 5, with the same threshold level, inhibiting the output via
the start-stop latch (Figure 16).
with a source voltage derived from either V (7.50V) minus two
Z
diode drops, or, when feed-forward is in control, a voltage greater
than V and proportional to the main supply voltage. The nominal
Z
upper threshold voltage is 5.25V and the lower threshold 1.70V.
These then determine the sawtooth peak and valley voltages,
respectively.
Operation
Beginning with the charge cycle, ramp voltage builds up on the
timing capacitor due to a constant current supplied to the node at
Pin 2. When capacitor voltage reaches the upper threshold,
comparator A switches, setting the latching flip-flop. The output of
the latch goes high, generating a clock pulse. The discharge
transistor is simultaneously turned on, reducing charge on the timing
capacitor to the point at which the lower threshold voltage, 1.70V, is
reached. The lower comparator is then activated, resetting the latch
and terminating the clock pulse. Note that the discharge transistor is
referenced to the same return diodes as the threshold resistor
divider and the discharge current is made to track with the charge
current. This charge and discharge tracking results in a true
sawtooth waveform even at extended frequencies. Figure 17 shows
The charging of the slow-start capacitor provides a controlled
ramp-up of the output duty cycle and a resultant gradual increase in
energy fed to the output magnetics.
The dynamic response of the PWM comparator is shown in the
simulated waveform drawing of Figure 17. The error amplifier output
voltage is depicted as sloping positive (increasing) with time as
referenced to the sawtooth waveform. This causes the duty cycle to
increase with time. This is an indication of an increasing load on the
power supply as output voltage is decreasing. The Pin 5 (δ
)
MAX
a family of curves which explains the relationship between R , C ,
and the frequency of the sawtooth generator. The data sheet shows
the initial accuracy of the oscillator at 60Hz and 600kHz.
T
T
control voltage is also superimposed midway on the sawtooth,
indicating the limits of duty cycle increase as the output waveform
no longer increases in duty cycle after the δ threshold is
MAX
crossed. A hypothetical overcurrent pulse (Pin 14) is shown to
illustrate cycle termination immediately at the output (Pin 19).
10
1994 Aug 31
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
+V
Z
35µA
35µA
35µA
DELTA
MAX
CONTROL
V
H
4
5
10
SAWTOOTH
(–)
(–)
(–)
(–)
+
ERROR
AMP
OUT
SAWTOOTH
UPPER
THRESHOLD
MODULATOR
IN
9k
PWM SIGNAL
TO OUTPUT
NOR GATE
2.5k
100µA
SL00402
Figure 15. PWM Comparator
DELAYED CLOCK
V
REF
+3.80V
S
+
+
δ
R
TO OUTPUT
STAGE
OUTPUT
LATCH
PWM
–
–
NOR
8
–
10
5
DUTY
CYCLE
CONTROL
SL00403
Figure 16. The Duty Cycle Control Circuit, Pulse Width Modulator, and Error Amplifier, Reference, and Output Latch
11
1994 Aug 31
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
SAWTOOTH
WAVEFORM
PIN 5
δ MAX LEVEL
PWM COMPARATOR
(INTERNAL)
FLYBACK PULSE
(INTERNAL)
+0.528V
PIN 14
CURRENT
SENSE INPUT
(OUTPUT)
PIN 19
SL00404
Figure 17. Duty Cycle vs Feedback Error and Overcurrent Sense
The error amplifier’s non-inverting input is tied to a bandgap
reference of 3.80V, accurate to ±2% at 25°C. The temperature
stability of the voltage reference is 30ppm/°C.
95%. The amplifier can sink 10mA and source 5mA. The nominal
DC output for 50% duty cycle is 3.55V. Feedback control resistor
value may range from 1kΩ to 240kΩ without overload or instability.
However, low closed-loop gains must be compensated by lag lead
network techniques for optimum stability. Loop compensation
networks may intersect the open-loop gain curve with a slope 2
closure and must then be compensated to maintain overall phase
and gain margin (Figure 18).
The error amplifier is designed for an open-loop gain of 86dB having
a small-signal unity gain bandwidth of 3MHz. Closed-loop gain is
stable to 10dB, as shown in Figure 19. The DC output excursion of
the amplifier is capable of controlling the full PWM range of 0 to
+V (7.50V)
Z
V
Z
6k
2.5k
V
Z
ERROR AMP
OUT
3.80
V
10
REF
30
N BIAS
7pF
FEEDBACK
SENSE
8
6k
6k
SL00405
Figure 18. Error Amplifier
12
1994 Aug 31
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
EST. –3dB
FREQUENCY
NE5562
ERROR AMPLIFIER
PHASE DELAY
80
PHASE/AMPLITUDE
160°
143°
RESPONSE
70
60
50
40
30
20
10
0
130°
98°
+V
3.75V
REF
+
OFFSET
ADJUST
95°
5k
(8)
–
(10)
92°
83°
80°
10M
360
SLOPE
= (–)1
70°
32°
50
SLOPE
= (–)2
f
f
P1
P2
1
10
100
1000
10000
100000
1000000
FREQUENCY (Hz)
SL00406
Figure 19. Error Amp Response
(7.50V) increases the charge rate on C , causing the duty cycle to
FEED-FORWARD COMPENSATION (PIN 1)
T
be terminated earlier for each cycle that input voltage is increased.
The threshold voltages at the sawtooth limit comparator reference
inputs are changed with Pin 1 also in order to offset any change in
oscillator frequency.
To provide a means of automatically improving line-to-load voltage
regulation, a technique called feed-forward regulation is made a part
of the NE/SE5562 active mechanism. Referring back to the diagram
for the sawtooth oscillator, note that Pin 1 is capable of changing the
internal supply voltage to the charging circuit for the timing capacitor,
The secondary benefit of using feed-forward is the attenuation of
any low-frequency AC riding on the DC supply before it reaches the
regulated output.
C .
t
With a nominal duty cycle of 30%, for instance, increasing Pin 1
voltage by 1V from 10.3 to 11.3 will reduce the output duty cycle by
approximately 5%. Thus, a primary voltage change has caused a
decrease in volt-seconds (duty cycle X primary volts) of 5/30 or 16%
(Figure 6). The result is a small over-compensation in the output
energy, but an overall safe margin in transformer flux.
Note that a start delay circuit is added to the Pin 1 divider in order to
prevent internal race conditions during initial power-up. Once the
turn-on transient has decayed, normal operation of the feed-forward
circuit is assured. Figure 21 shows an RC delay placed in a base
clamping circuit to provide reliable starting.
The mechanism which produces inverse duty cycle modulation is
shown in Figure 20. Increasing Pin 1 voltage beyond the value of V
z
2V
Z
V
Z
+
PWM
COMPARATOR
V
TH
V
TH
–
T
T
δ
δ
SL00407
Figure 20. Feed-Forward
13
1994 Aug 31
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
SYNCHRONIZATION
The synchronization of the sawtooth oscillator to an external pulse
of negative-going polarity is shown in Figure 22. When the sync
input pulse crosses the 1.5V threshold, negative, the sawtooth
oscillator is prevented from discharging the timing capacitor, causing
the charge voltage on the capacitor to remain high (5.25V) until the
sync pulse again goes above 1.5V, allowing reset. This action
stretches the period of the oscillator and results in a lower frequency
under-synchronization control than the free-running frequency.
V
FFWD
2N3906
220k
0.2µF
1
The following relationship holds—
ffree*run
fsync
NE/SE5562
1
fsync
+
t0
A typical recommended starting point in calculating frequency for
synchronous operation is to set the free-run frequency
SL00408
approximately 10% higher than the sync frequency. Then set the
Figure 21. Feed-forward Turn-On Delay Circuit
pulse width, τ, to 10% of t , the free-run period, with the desired new
0
frequency determined by the sum as above.
+V
CC
T
19
+
NE/SE5562
1.5V
SYNC
11
2
d
T
SL00409
Figure 22. Synchronization Signals
PIN 11
SYNC
SIGNAL
+1.5V
τ
SAWTOOTH
WAVEFORM
T
O
SL00410
Figure 23. Sync Signal Relationship to Controlled Sawtooth Waveform
priority level sensing circuit. The lowest level on Pin 4, 5, or 10 gains
control of the duty cycle limit. During normal operation, the δ
DUTY CYCLE LIMIT (PIN 5)
MAX
The forward or buck converter, and even the flyback converters,
may require an automatic duty cycle limit to prevent transformer
saturation or unstable behavior. A special input provides access to
the PWM comparator for this purpose. As discussed previously in
regard to the error amplifier, increasing load demand may drive the
system current beyond safe limits. A simple solution is the
placement of a duty cycle limit within the system dynamic response
before this can occur. Figure 15 shows the PWM comparator with its
multiple input ports. All are inverting in polarity and provide a lowest
circuit sends a continuous threshold signal to the PWM comparator,
setting a fixed limit on how much the error amplifier is allowed to
increase the duty cycle in response to load demand. Figure 24
shows the circuit within the NE/SE5562 which actually controls duty
cycle as listed below:
1. Duty cycle ramp-up (slow-start) during power-up. Time constant
controlled by external R, C ramp voltage at Pin 5.
14
1994 Aug 31
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
2. Slow-start if remote ON/OFF is actuated, if OC2 threshold trips,
demagnetization/overvoltage is sensed, or low supply voltage to
the internal regulator is sensed (VS≤8.45V).
R = 10kΩ, find R
2
1
R2
+ 0.48
R2
R1
3. Note that Pin 8 is monitored by the loop fault comparator. When
the regulated supply feedback drops below this threshold level
(0.955V), the duty cycle is clamped by two diodes in series with
a 2kΩ load across Pin 5 to ground. This implies a minimum duty
cycle condition as long as the low output level remains.
R = 0.48 (R + R )
2
1
2
0.48R = R – 0.48R
1
2
2
R2(1 * 0.48)
0.48
R1
+
Referring to the graph in Figure 25, the designer may choose a
10k (0.52)
0.48
divider ratio which, when referenced to V , 7.5V, provides an easy
Z
+
duty cycle limit control. For example, a 50% limit results in a ratio of
0.48. Setting R at a nominal value between 10 and 20kΩ and
= 10.8kΩ
2
solving for R , the proper limit is obtained.
1
Example:
A duty cycle limit of 50% is required for a forward converter.
DELTA
MAX TO
PWM COMP
R
1
SLOW
START
CAP
R
C
2
V
Z
SS
5
0.9V
V
Z
ERROR
AMP IN
36µA
8
N BIAS
1.5V
0.9V
9k
0.955V
SLOW
START
COMP
50
SLOW
START
COMP
OUT
LOOP
FAULT
COMP
2k
‘A’
FROM
START/STOP
LATCH
+
STOP
SL00411
Figure 24. Duty Cycle Limit Control
15
1994 Aug 31
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
90
80
70
60
V
+
7.50V
Z
50
40
30
20
10
0
DUTY
CYCLE
CONTROL
R
2
R
R
2
1
0.1 0.2
0.6 0.7
0.3 0.4 0.5
0.8
SL00412
Figure 25. Maximum Duty Cycle
DEMAG/OV
SENSE
TO
TO
OUTPUT
NOR
OUTPUT
NOR
OC2
REMOTE
ON/OFF
SENSE
V
Z
LOW SUPPLY
SENSE
R79
10k
1.5V
R78
10k
Q282
R73
10k
R74
10k
R75
18k
R76 R77
15k
10k
Q262
Q261
Q264
Q265
Q276
Q275
Q284
Q277
Q269
Q279
C
Q283
Q266
Q267
SS
DISCHARGE
Q260
OC ACCUM
Q270 Q271 Q272 Q273 Q274
Q280
Q278
Q281
SLOW-START
COMPARATOR
+
Q263
RESET
Q268
Q283B
Q283A
SHUTDOWN LATCH
START STOP LATCH
BULK
SENSE
SIGNAL
+
GND
RESET
0V
20
SL00413
Figure 26. Start-Stop/Shutdown Latches
16
1994 Aug 31
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
duty cycle. The equivalent circuit at this instant in the start-up cycle
which exists at Pin 5 is shown in Figure 28.
THE START-STOP CONTROL SEQUENCE
The start-up circuit involves a sequential set of conditions which
progresses as follows: power-up after OFF condition or remote ON
after OFF. Initially, 0V exist on the supply output, causing zero
feedback volts on Pin 8. The slow-start capacitor is discharged,
forcing Pin 5 to 0V, having been clamped by the internal discharge
transistor. Internal supply regulator input exceeds 8.45V, releasing
low voltage shutdown condition with Pin 5 below 0.955V. The
slow-start comparator output goes high, resetting the start/stop
latch, sending a low output signal to the output stage power NOR
gate. The PWM signal is then enabled to feed the output drive
circuits, starting energy flow through the magnetics. However,
instantaneously the power supply output is still below 0.955V and
the loop fault comparator forces the PWM to remain at a minimum
The actual minimum duty cycle is determined by the parallel source
resistance of R and R combined with the shunt loading internal to
1
2
Pin 5. High values of divider resistance, 20-30kΩ, will supply less
shunt current to Pin 5 and create a lower modulator duty cycle, while
lower values of R and R (5-10kΩ) will generate a higher modulator
1
2
voltage and a greater resultant minimum duty cycle.
As the power conversion circuits become active and Pin 8 feedback
voltage increases above 0.955V, the duty cycle network is
unclamped; duty cycle increases, controlled by the RC time constant
R ||R .C , and as output voltage brings the feedback voltage up to
1
2
SS
equal the reference voltage, 3.80V, the error amplifier takes control
and the supply is in regulation.
+7.50V
DEMAG
OC2
0V
DISCHARGE
R
1
5
S
C
SS
START/
Q
STOP
R
2
–
+
LATCH
R
0.955V
SLOW-START
COMPARATOR
SL00414
Figure 27. Slow-Start Comparator
7.50V
+
R
1
–
–
–
PWM
COMP
MINIMUM
DUTY CYCLE
V
MOD
5
C
SS
ON
R
2
0.2V
FEEDBACK
VOLTAGE
SENSE
5
LOOP FAULT
COMPARATOR
1.4V
2k
SL00415
Figure 28. Loop Fault Comparator and Minimum Duty Cycle Clamp
The stop or shutdown sequence is initiated by any of the following
conditions:
c. Remote ON/OFF voltage at Pin 6 greater than 2V.
d. Sustained OC2 causing C to charge above 3.80V (current
DLY
a. Supply voltage (bulk) sense below 3.80V at Pin 12.
sense on Pin 14 continuously above 0.645V peak).
b. Pin 17 below 8.45V or Pin 7 current below level (less than
9mA).
17
1994 Aug 31
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
If the overcurrent sense feature is not used, it is recommended that
Pin 14 be tied to ground.
DUAL-LEVEL OVERCURRENT COMPARATORS
The overcurrent sensing circuit (Figure 29) consists of a single PNP
input buffer with emitter-follower tied to V , 7.50V, feeding into the
Z
When used for sensing current-derived voltage impulses from the
primary driver, a high-speed, low-impedance transient filter network
base of an NPN split-emitter transistor. This forms the input node to
a set of dual-level voltage comparators with references of 0.528 and
0.645V, respectively. Current sources for the comparator are fixed
biased NPNs.
is advised. An example is shown in Figure 30. Keep C close to the
F
NE/SE5562.
The typical transition time delay for an overcurrent fault is 300ns.
Bias current at the input averages 500nA.
V
= 7.50V
Z
135µA
135µA
135µA
1.5V
3k
OC2
CURRENT
SENSE
INPUT
14
REFERENCE
0.645V
100µA
135µA
1.5V
3k
OC1
0.528V
0.645V
REFERENCE
0.528V
100µA
SL00416
Figure 29. NE/SE5562 Overcurrent Comparator
THEORY—OC1 AND OC2
Overcurrent Logic and Delay Capacitor Operations
The circuit takes a voltage input from Pin 14 and compares the level
to a dual reference comparator with trips at 0.53 and 0.65V. The
lower trip point actuates cycle-by-cycle shutdown of the output stage
with an intrinsic delay of 400ns. The second level actuates the
slow-start function. In addition, there exists a separate
+V
CC
housekeeping circuit whose function is to terminate operation of the
output stage if its threshold is exceeded. This involves a time delay
circuit based on two separate switchable current sources, OC1 and
OC2. The time delay capacitor allows the user to program shutdown
of the system after a predetermined number of overcurrent cycles
have occurred within the period set by the ramp-up of the delay
capacitor. Once shutdown has occurred in this manner, external
reset is required to restart the system. Referring to the logic block
Figure 31, which controls the gating of the two charge pumps into
the delay capacitor at Pin 16, the complete signal flow may be
traced. Logic signals from the overcurrent 1 and 2 comparators are
gated by the clock and delayed clock signals generated by the
NE/SE5562
I
500-1000Ω
10% CARBON
MAG
C
R
F
SH
SL00417
Figure 30. Transient Suppression
18
1994 Aug 31
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
sawtooth oscillator. The complete sequence for an overcurrent fault
may be understood by referring to Figure 32 for OC2. Here it is
shown that an OC2 signal exists indicating that the 0.65V threshold
has been exceeded by a signal at Pin 14.
frame. Consecutive overcurrent pulses of either OC1 or OC2
magnitude will activate the selected charge pump for the total
duration that such overcurrent occurs. The charging cycle will
continue until the delay capacitor reaches the 3.86V trip level.
Note that an overcurrent pulse within a particular clock frame turns
on the respective OC2 charge ramp during the entire next clock
A
C
C
A
A
OC2 IN
C
A
C
Q
B
B
B
OC2
LATCH
OC2 DELAYED
OC2
A
A
C
A
C
B
Q
C
B
B
C
B
DELAYED
CLOCK
OUT
C
B
A
C
A
CLOCK
A
C
C
A
A
A
A
A
C
A
C
C
A
B
A
C
C
Q
B
B
OC1 DLEAYED
OC1
LATCH
OC1
A
A
B
A
C
C
Q
A
B
C
OC1 IN
B
SL00418
Figure 31. Overcurrent Logic
SAWTOOTH
CLOCK
CLOCK
DELAY
CLOCK
LET OC2 GO UP AT ANY TIME BETWEEN DELAY CLOCK RISES AND CLOCK RISES
OC2
Q
A
Q
B
R
S
Q
PUMP
SL00419
Figure 32. Fault Cycle
19
1994 Aug 31
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
3.86V
0.1µF
0.5µF
1µF
C
DELAY
0.00V
100
200
300
OC1 DELAY TIME (MILLISECONDS)
3.66V
SL00421
1µF
5µF
Figure 34. OC1 Ramp and Shutdown Delay
10µF
mode), on the first such pulse. OC2 delays are based on an
interrupted charging cycle with total cycle time determined by the
external slow-start delay capacitor duty cycle maximum
divider—time constant.
C
DELAY
30
For a continuous OC1 overcurrent:
(13X10*6)(Delay time * sec)
0.00V
(1)
CDLY
+
10
20
40
50
60 70
80
3.86V
OC2 DELAY TIME (MILLISECONDS)
(neglecting recycle dfelay)
SL00420
For a continuous OC2 overcurrent:
(550X10*6)(Delay cycles x 1 fSW
)
Figure 33. Overcurrent Shutdown Function
CDLY
+
3.86V
(2)
Some downward adjustment of the OC2 capacitor value may be
necessary to compensate for the 1-2µA of discharge current at Pin
16 during the delay cycles.
CALCULATING THE DELAY CAPACITOR
Actual delay time for a given capacitor value at Pin 16 may be
estimated using the graphs in Figure 33 for OC1 and OC2. By first
determining the allowable overcurrent time product for a particular
power converter, a capacitor delay value may be calculated.
Example: A maximum of 100 OC2 current fault cycles is allowed.
f
=400kHz, find C
DLY
SW
(550X10*6)(100 x 1 4 x 105)
Note that the OC1 charge pump is typically 13µA while OC2 pumps
550µA into the capacitor. If the exact value is to be calculated for a
particular delay requirement, use the following procedure:
CDLY
+
3.86V
=0.036µF
Example: OC2/C
1. Determine the level of overcurrent—OC1 or OC2.
DLY
2. Find the maximum delay time which the supply may safely sus-
tain for this continuous overcurrent condition. Note that OC1 may
be activated on every cycle if OC2 is not reached, causing con-
tinuous charging of C-Delay. However, OC2 overcurrent detec-
tion causes the supply to go into slow-start shutdown (hiccup
Find number of OC1 cycles before shutdown with 0.036µF C
.
DLY
20
1994 Aug 31
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
(3.6 X 10*8)(3.86V)
13 x 10*6A
adjusted near midway, the line voltage will have to exceed V
before the supply will restart. The hysteresis control may then be
calibrated for the desired over-excursion before restart. This
prevents unstable circuit chatter.
NOMINAL
Delay Time +
=10.7ms
10.7 X 10*3
2.5 x 10*6
The reset switch provides a means for resetting the shutdown latch
Total cycles shutdown +
after overcurrent faults have charged C
to its trip threshold. This
DLY
=4280
also provides a discharge path for the delay capacitor. Figure 36
shows internal circuit.
Figure 35 shows an actual OC1 charging cycle for continuous fault
current sensed at Pin 14 and a DLY = 1µF.
V
+V
BULK
S
BULK-SENSE AUXILIARY COMPARATOR WITH
SHUTDOWN
R
1
This circuit is intended to act as an automatic low-line detection
mechanism. As shown in Figure 35, a voltage divider is connected
from the main unregulated DC supply to Pin 12. The lower divider
resistor may be a potentiometer of 5-10kΩ resistance with
center-tap connected to Pin 13. The comparator which senses Pin
12 voltage is referenced to 3.80V and Pin 12 divider voltage must be
greater than this voltage by a sufficient margin to operate within the
prescribed low-line limits. For instance, if a line voltage drop of 25%
12
13
NE/SE5562
HYSTERESIS
ADJUST
R
2
SL00422
is considered the shutdown threshold, then V should be calculated
12
Figure 35. Bulk-Sense Comparator Divider
for a nominal operating voltage as shown in Figure 35.
When the line voltage drops more than 25%, the output stage is
disabled. With the hysteresis connected as shown and the pot
1.5V
++
V
BULK
18k
BULK
SENSE OUT
R
A
V
Z
16
RESET
C
DELAY
BULK
SENSE IN
25k
12
3.80V
36µA
N BIAS
BULK
R
B
13
SENSE
26k
BULK
SENSE
COMP
POTENTIOMETER
HYSTERESIS
26k
SL00423
Figure 36. Bulk-Sense Comparator
power MOS FET gate. This feature protects the output stage from
inadvertent catastrophic overload.
THE OUTPUT DRIVE STAGE
The output stage contains the power NOR inhibit gate, invert logic
function, and source-sink drivers. The driver stage is capable of
sourcing and sinking 100mA at frequencies up to 600kHz. The
output transistors are Schottky clamped to prevent saturation and
the resultant switching delay due to stored charge. A 2.5Ω current
sense resistor in the emitter of Q419 serves to drive active clamp
Q427 when the output sources more than 200mA. This places a limit
on the peak current available during instantaneous charging of a
When sinking current, the output is clamped to a maximum of 1.4V.
Output swing for positive output is typically V -1.9V at 100mA
S
sourcing. Rise time for a 2000pF load at Pin 19 is typically 160ns
with a fall time of 80ns.
The power NOR gate provides a fast response inhibit function to
shutdown the output in the event of a number of different fault
21
1994 Aug 31
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
conditions. All inputs are internal to the device and do not appear
directly on the external pins as is shown on Figure 37.
means of designing with P-channel power MOS FETs without adding
external inverters. The invert logic is controlled by a simple logic
signal at Pin 15. Grounding will cause the output to be a normal
positive output and a high level gives inverted output.
The additional flexibility of an invert control allows the polarity at the
output during duty cycle to be reversed. This provides a simple
17
+V
5
R31
10k
R34
5k
Q128
R30
15
R33
5k
R37
10k
Q131
R38
1k
R35
3k
R32
3k
Q126
Q129
Q125
Q127
Q132
Q155
Q130
Q156
Q133
Q154
PWM
Q158
DEMAG
0.V
OUTPUT
LATCH
Q157
R39
300
R40
2.5
SHUT
DOWN
LATCH
3.80V
START/STOP
LATCH
1.5V
19
OUTPUT
R28
5k
R29
5k
R30
1.25k
Q159
V
Z
Q142
Q144
Q160
Q141
Q143
Q161
R41
5k
P
Q165
BIAS
R43
4k
Q134
Q135
Q136
Q137
Q151
Q162
Q145 Q146Q147
Q149
Q138
1.5V
Q153
Q148
Q152
Q163
Q164
Q165
Q139
Q140
Q150
R42
1k
INVERT
15
OUTPUT NCR
NORM
SL00424
Figure 37. Output Driver Schematic
20-Pin glass/ceramic—NE5562F/ SE5562F: θ 90°C/W
THE INTERNAL VOLTAGE REGULATOR
JA
The internal regulator is configured to provide for external supply to
20-Pin SO: -55 to +85°C/W (board-dependent)
1
the NE/SE5562 from either a voltage feed or a current feed.
NOTE:
1. See Figures 7 and 8 for internal Regulator Response Curves.
For the current-fed mode, a series-dropping resistor may be used to
power the device from voltages greater than 18V with current supply
of 15 to 25mA. Note that supply current stated in the data sheet is
Design Example—An NE5562N is operated at 40°C ambient in the
voltage-fed mode with V =15V; assume I =22mA average:
S
S
for the device only without load on the output or V . Drive currents
Z
also are pulse-related and thus reflect frequency components onto
the current-feed circuit. These must be filtered out at Pin 7 with
adequately large capacitors in order to prevent motor-boating (see
Figure 38 and Figure 39).
++V
47-100µF
35V
Input current to Pin 7 flows through Zeners Z and Z , and shunt
1
2
+
regulator transmitter QR. A differential amplifier with 3.80V reference
provides feedback to regulate V to 15V.
S
7
In the voltage-fed mode using Pin 17, the Zeners prevent current
flow through QR for input voltages less than 19V.
Power dissipation of the device must stay within the allowable
package limits. These limits are derived from the thermal
19
NE/SE5562
characteristics of the particular package chosen. The NE5562N
plastic package is capable of operating within the temperature range
(ambient) of 0 to +70°C. This rating applies to the surface-mount
product NE5562D also. Obviously, the power dissipation of the “D”
package is lower than the standard DIP. Thermal resistance for the
various packages are:
20
SL00425
Figure 38. Current-Feed
20-Pin plastic—NE5562N/SE5562N: θ 61°C/W
JA
22
1994 Aug 31
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
17
V
S
VOLTAGE
SOURCE
7
V
V
I
S
CURRENT
SOURCE
790
FROM BIASING
NETWORK
30k
10k
Q
R
20k
REGULATOR
3.80V
SL00426
Figure 39. Internal Voltage Regulator
-3
P
D
= (22×10 ) (15)
=330mW
Junction temperatures will be 20.1°C above average ambient
temperatures which is 40°C
Solving for the temperature rise from ambient to the IC functions:
Temperature rise = 61°C/W×0.33W
= 20.1°C
T =40°C 20.1°C 60.1°C
J
The allowable maximum junction temperature is 150°C 125°C is
more conservative. The conditions of this example are safe.
+25V
+12–15V
L
O
10k
12
V
Z
17
C
C
L
O
10k
15
19
4
5
(0.472) V
Z
IRF530
NE5562
3
2
1µF
1k
14
V
REF
R
SH
100pF
6
ERROR
AMP
20
8
10k
‘A’
10
10k
VARIABLE
SUPPLY
0-5V
NOTES:
1. Supply will become active as point ‘A’ reaches the level of V
2. Monitor Pin 19 and Pin 2 on dual-trace scope with voltmeter connected to supply output.
, 3.80V.
REF
SL00427
Figure 40. Open-Loop Test Setup
23
1994 Aug 31
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
D
3
L
O
+
+
P
P
S
C
O
1
D
2
1
2
C
V
O
P
n
n
–
V
IN
Q
1
–
NOTE:
The P clamp winding prevents collector voltage from exceeding 2X V during off time.
IN
SL00428
1
Figure 41. Forward Converter
+
–
Flyback Converter Design
Flyback Converter
n
Advantages:
1
• Simple circuit. Only one inductive component even with line isola-
tion.
m
• Economic. Low component count, low cost.
• Work over large input voltage variations.
• Can accommodate multiple outputs.
To Prevent Core Saturation Due to
Flux Staircasing
Disadvantages:
m
dmax
1 *
if m = n δ
n
< .5
max
m
• Large output ripple current due to discontinuous energy transfer.
• Large output capacitor; has to supply part of the load current.
Demagnetization of Core
• Low leakage inductance required to prevent high voltage spikes at
the switching transistors.
m
n
• Relatively large core volume for the output power. Core driven in
(V)
VCEmax + Vimax
X
m
one direction only.
Design Parameters for Flyback Inductor
Maximum Voltage Across Transistor
SL00429
Input
Figure 42. Forward Converter Design Formulas
• Minimum input voltage
• Maximum input voltage
D
1
Output
+
+
• Output voltage or voltages
C
P
• Output current or currents
• Output load
C
V
O
O
–
V
I
Q
1
–
SL00430
Figure 43. Isolated Secondary
24
1994 Aug 31
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
Frequency of Operation
Estimate of Overall Efficiency. (η)
+16V
AUXILIARY
BOOTSTRAP
SUPPLY
(SEE FIGURE 43)
+V=48V
0.47µF
F. FWD
SENSE
+V = 12V
S
3.9
0.01µF
10
D
2N3906
40k
0.01µF
BYV19-35
220k
0.22µF
+V
BYV26C
OUT
1
10k
C
3
+5V
L
0
RESET
[O.C.]
D
2
3.9
D
3
12
1
17
n
n
T
0.01µF
1
COM.
1
3
2
(PIN 9)
13
LOW
CLOCK
DELAY
V
HYSTERESIS
ADJUST
Z
SUPPLY
7.50V
DETECTOR
5.1k
570
pF
4
13k
D
R
I
4.7nF
L
A
T
BUZ41A
3.26V
5
6
PWM
4.7
19
18
15
V
E
R
C
H
BYV26C
10k
C
SS
Q
1
10
START/
STOP
INVERT
LA645V
I
OFF
CC
3.80V
+5V
REMOTE
SHUT
DOWN
PGM
IN914
CL
1
T
14
2
0V
ON
+
SHUT DOWN
100pF
ERROR
AMP
13µA
550µA
1.3k
+5
8
–
C
T
CL
2
V
OUT
100:1
SENSE
OC1
OC2
Q
1
10 20
16
C
1.6k
PIN
14
0.00µF
PIN
14
ALTERNATE
CIRCUIT
R
SH
DELAY
0.24
1k
0.53
I
+
MAX
R
SH
SL00431
Figure 44. Forward Converter, 100W – 5V
25
1994 Aug 31
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
+48V
+17V
100
15V
P
3
n
D40K2
+V
O
+5V
P
2
33k
n
n/2
7
1
P
1
NE/SE5562
n
+3.80V
220k
19
6.8k
+
–
0.22µF
8
10
20
R
F
SL00432
Figure 45. Shunt-Regulated Output With Bootstrap Supply
26
1994 Aug 31
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
S
+
–
CURRENT PATH
WITH SWITCH
CLOSED
CURRENT PATH
WITH SWITCH
OPEN
V
V
O
I
–
+
+
S
CURRENT PATH
WITH SWITCH
CLOSED
CURRENT PATH
WITH SWITCH
OPEN
V
V
O
Negative Output
I
+
+
–
+
V
V
O
I
Positive Output
–
–
Development of Practical Flyback Converter Circuit
TR1 ON OFF
I
I
O
D1
nV
O
i
a
L
i
L
V
T1
N1
CE
V
I
I
I
D1
L
+
L1
V
C
O
O
nV
O
I
C
V
V
V
i
I
i
i
CE
CE
b
c
L
L
V
I
L
V
CE
TR1
V
L
I
O
T
T
δ
O
T
T
δ
NOTES:
a. Unlimited choke current
b. Interrupted choke current
Flyback Converter and Current and Voltage Waveforms
Figure 46.
SL00433
27
1994 Aug 31
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
48V +V
S
+5V
T
COM
+12
33k
+12V
2N3906
FEED-
220k
FORWARD
COM
0.1µF
0.22µF
6.8k
NE5562
CERAMIC
1
2
20
19
–12
BUZ41A
V
SENSE
+5V
0’
570pF
4.7
3
4
18
17
16
C
T
R
T
C
DELAY
5.1k
5
1k
6
7
15
14
13
12
11
R
O.C.
HYST.
1
2
R
3.8V
SH
8
100pF
9
R
F
10
R
3.5V
C
SS
LOW
SUPPLY
SENSE
+V
S
EXT
SYNC
+5
RESET
0V–
NOTE:
400kHz operation with feed-forward line regulation and cycle-by-cycle current timing.
SL00434
Figure 47. NE5562 Flyback Converter
++V
(17)
–V
OUT
(10)
(19)
R
F
+
–
(8)
(9)
V
ERROR
AMP
Z
+7.50V
(20)
100
100
2N3906
R
S
+3.80V
I
’
S
R
I
I
S
SL00435
Figure 48. Negative Output Regulator Using Current Mirror
28
1994 Aug 31
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
+48V
(+)
+15V
SLAVED
OUTPUTS
17
(–)
NE/SE5562
–15V
+15V
+
+
4
PWM
–
NE5018
D/A
1–5V
+5V
–12V
5k
NE5034
A/D
15
+
PROGRAMMED
SUPPLY
VOLTAGE
µP
SL00436
Figure 49. Microprocessor Controlled SMPS
3. H. Dean Venable, Stability Analysis Made Simple, Venable
Industries, Inc., 1981.
REFERENCES
1. R.D. Middlebrook and Slobadan Cuk, Advances in Switched
Mode Power Conversion, Volumes I and II, TESLA Co., Pasa-
dena, CA, 1983.
4. J. Jongsma and L.P.M. Bracke, High Frequency Ferrite Power
Transformer and Choke Design, N. V. Philips ELCOMA Publica-
tions, Eindhoven, the Netherlands, September 1982.
2. Rudolf P. Stevens and Gordon E. Bloom, Modern DC to DC
Switchmode Power Convertor Circuits, Van Nostrand Reinhold/
Computer Science and Engineering Series, 1985.
5. Edwin S. Oxner, Power FETs and Their Applications, Prentice-
Hall, 1982.
29
1994 Aug 31
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