SG3524N [NXP]
SMPS control circuit; 开关电源控制电路
| 型号： | SG3524N |
| 厂家： | 
NXP |
| 描述： | SMPS control circuit |
| 文件： | 总5页 (文件大小：130K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
SMPS control circuit
SG3524
DESCRIPTION
PIN CONFIGURATION
This monolithic integrated circuit contains all the control circuitry for
a regulating power supply inverter or switching regulator. Included in
a 16-pin dual-in-line package is the voltage reference, error
amplifier, oscillator, pulse-width modulator, pulse steering flip-flop,
dual alternating output switches and current-limiting and shut-down
circuitry. This device can be used for switching regulators of either
polarity, transformer-coupled DC-to-DC converters, transformerless
voltage doublers and polarity converters, as well as other power
control applications. The SG3524 is designed for commercial
applications of 0°C to +70°C.
D, F, N Packages
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
V
INVERT INPUT
NON-INV INPUT
OSC OUTPUT
(+)CL SENSE
(–)CL SENSE
REF
IN
EMITTER B
COLLECTOR B
COLLECTOR A
EMITTER A
R
T
SHUTDOWN
C
T
COMPENSATION
GROUND
FEATURES
TOP VIEW
SL00174
• Complete PWM power control circuitry
Figure 1. Pin Configuration
• Single ended or push-pull outputs
• Line and load regulation of 0.2%
• 1% maximum temperature variation
• Total supply current is less than 10mA
• Operation beyond 100kHz
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
SG3524N
DWG #
SOT38-4
0582B
16-Pin Plastic Dual In-Line Package (DIP)
16-Pin Ceramic Dual In-Line Package (CERDIP)
16-Pin Small Outline (SO) Package
0 to +70°C
0 to +70°C
0 to +70°C
SG3524F
SG3524D
SOT109-1
BLOCK DIAGRAM
16
3
V
REF
REF
REG
+5V TO ALL
15
V
IN
INTERNAL CIRCUITRY
+5V
12
C
OSCILLATOR
OUTPUT
A
+5V
FLIP FLOP
NOR
6
7
R
C
T
T
OSC
11
13
(RAMP)
+5V
C
B
+
NOR
COMPARATOR
14
E
–
B
+5V
+5V
ERROR
AMP
1
2
+
4
5
–
+
+SENSE
–SENSE
INV INPUT
N.I. INPUT
CL
–
9
1k
COMPENSATION
GROUND
(SUBSTRATE)
10
8
SHUTDOWN
10k
SL00175
Figure 2. Block Diagram
1
1994 Aug 31
853-0891 13721
Philips Semiconductors
Product specification
SMPS control circuit
SG3524
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
V
V
IN
Input voltage
40
100
50
5
I
I
Output current (each output)
Reference output current
Oscillator charging current
Power dissipation
mA
mA
mA
OUT
REF
P
D
Package limitation
1000
8
mW
mW/°C
°C
Derate above 25°C
T
A
Operating temperature range
Storage temperature range
0 to +70
-65 to +150
T
STG
°C
DC ELECTRICAL CHARACTERISTICS
T =0°C to +70°C, V =20V, and f=20kHz, unless otherwise specified.
A
IN
LIMITS
Typ
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
Max
Min
Reference section
V
OUT
Output voltage
4.6
5.0
10
5.4
30
50
V
mV
Line regulation
V =8 to 40V
IN
Load regulation
I =0 to 20mA
L
20
mV
Ripple rejection
f=120Hz, T =25°C
66
dB
A
I
Short circuit current limit
Temperature stability
Long-term stability
V
=0, T =25°C
100
0.3
20
mA
SC
REF
A
Over operating temperature range
T =25°C
1
%
mV/kHz
A
Oscillator section
f
Maximum frequency
Initial accuracy
C =0.001 µF, R =2kΩ
300
5
kHz
%
MAX
T
T
R and C constant
T
T
Voltage stability
V
=8 to 40V, T =25°C
1
2
%
IN
A
Temperature stability
Output amplitude
Output pulse width
Over operating temperature range
Pin 3, T =25°C
%
3.5
0.5
V
P
A
C =0.01 µF, T =25°C
µs
T
A
Error amplifier section
V
Input offset voltage
V
V
=2.5V
=2.5V
2
2
10
10
mV
µA
dB
V
OS
CM
I
Input bias current
BIAS
CM
Open-loop voltage gain
Common-mode voltage
Common-mode rejection ratio
Small-signal bandwidth
Output voltage
68
80
V
CM
T =25°C
1.8
3.4
A
CMRR
BW
T =25°C
70
3
dB
MHz
V
A
A =0dB, T =25°C
V
A
V
OUT
T =25°C
0.5
0
3.8
45
A
Comparator section
Duty cycle
% each output “ON”
Zero duty cycle
%
V
Input threshold
Input threshold
1
3.5
1
Maximum duty cycle
V
I
Input bias current
µA
BIAS
Current limiting section
Sense voltage
Pin 9=2V with error amplifier set for maximum out,
180
-1
200
0.2
220
+1
mV
T =25°C
A
Sense voltage T.C.
mV/°C
V
CM
Common-mode voltage
V
2
1994 Aug 31
Philips Semiconductors
Product specification
SMPS control circuit
SG3524
DC ELECTRICAL CHARACTERISTICS (Continued)
T = 0°C to +70°C, V = 20V, and f = 20kHz, unless otherwise specified.
A
IN
LIMITS
Typ
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
Max
Min
Output section (each output)
Collector-emitter voltage (breakdown)
40
V
Collector-leakage current
Saturation voltage
Emitter output voltage
Rise time
V
=40V
0.1
1
50
2
µA
V
CE
I =50mA
C
V
=20V
17
18
0.2
0.1
V
IN
t
t
R =2kΩ, T =25°C
µs
µs
R
C
A
Fall time
R =2kΩ, T =25°C
F
C
A
Total standby current
(excluding oscillator charging current,
error and current limit dividers, and
with outputs open)
V
IN
=40V
8
10
mA
connecting Pins 15 and 16 together to the input voltage. In this
configuration, the maximum input voltage is 6.0V.
THEORY OF OPERATION
Voltage Reference
This reference regulator may be used as a 5V source for other
circuitry. It will provide up to 50mA of current itself and can easily be
expanded to higher currents with an external PNP as shown in
Figure 3.
An internal series regulator provides a nominal 5V output which is
used both to generate a reference voltage and is the regulated
source for all the internal timing and controlling circuitry. This
regulator may be bypassed for operation from a fixed 5V supply by
Q1
100Ω
V
SG3524
REFERENCE
SECTION
REF
15
16
+V
IN
I
to 1.0A
L
+
DEPENDING
µ
10 F
8
ON CHOICE
FOR Q1
GND
SL00176
Figure 3. Expanded Reference Current Capability
TEST CIRCUIT
2k
1W
2k
1W
I
V
S
IN
15
3
12
13
11
OUTPUTS
OSC OUT
SG3524
16
V
REF
14
8
6
7
2
1
9
10
4
5
CURRENT
LIMIT
COMP
INV.
INPUT
RAMP
N.I.
INPUT
SHUT
DOWN
V
IN
8–40V
2k
10k
1k
0.1
C
10k
2k
T
R
T
SL00177
Figure 4. Test Circuit
3
1994 Aug 31
Philips Semiconductors
Product specification
SMPS control circuit
SG3524
3.6 V ÷ R and should be kept within the approximate range of 30µA
T
to 2mA; i.e., 1.8k<R <100k.
T
The range of values for C also has limits as the discharge time of
T
10
5
C determines the pulse-width of the oscillator output pulse. This
T
pulse is used (among other things) as a blanking pulse to both
outputs to insure that there is no possibility of having both outputs
on simultaneously during transitions. This output dead time
relationship is shown in Figure 5. A pulse width below approximately
0.5µs may allow false triggering of one output by removing the
blanking pulse prior to the flip-flop’s reaching a stable state. If small
3
2
1.0
0.5
0.3
values of C must be used, the pulse-width may still be expanded
T
by adding a shunt capacitance ( 100pF) to ground at the oscillator
output. [(Note: Although the oscillator output is a convenient
oscilloscope sync input, the cable and input capacitance may
increase the blanking pulse-width slightly.)] Obviously, the upper
limit to the pulse width is determined by the maximum duty cycle
.001 .002 .005 .01 .02
TIMING CAPACITOR VALUE (C–)–(µF)
.05
1
SL00178
Figure 5. Output Stage Dead Time as a Function of the Timing
Capacitor Value
acceptable. Practical values of C fall between 0.001 and 0.1 µF.
T
The oscillator period is approximately t=R C where t is in
T
T
microseconds when R =Ω and C =µF. The use of Figure 6 will allow
T
T
selection of R and C for a wide range of operating frequencies.
T
T
Note that for series regulator applications, the two outputs can be
connected in parallel for an effective 0-90% duty cycle and the
frequency of the oscillator is the frequency of the output. For
push-pull applications, the outputs are separated and the flip-flop
divides the frequency such that each output’s duty cycle is 0-45%
and the overall frequency is one-half that of the oscillator.
100
50
20
10
5
External Synchronization
2
If it is desired to synchronize the SG3524 to an external clock, a
pulse of +3V may be applied to the oscillator output terminal with
1
R C set slightly greater than the clock period. The same
considerations of pulse-width apply. The impedance to ground at
T
T
5
10 20 50 100 200 5001ms2ms
OSCILLATOR PERIOD (µs)
this point is approximately 2kΩ.
SL00179
If two or more SG3524s must be synchronized together, one must
Figure 6. Oscillator Period
be designated as master with its R C set for the correct period.
T
T
as a Function of R and C
T
T
The slaves should each have an R C set for approximately 10%
T
T
longer period than the master with the added requirement that
C (slave)=one-half C (master). Then connecting Pin 3 on all units
T
T
together will insure that the master output pulse—which occurs first
and has a wider pulse width—will reset the slave units.
R
R
= 30MΩ
L
80
60
40
20
0
Error Amplifier
This circuit is a simple differential input transconductance amplifier.
The output is the compensation terminal, Pin 9, which is a
= 1MΩ
L
R
R
= 300kΩ
L
L
high-impedance node (R 5MΩ). The gain is
= 100kΩ
L
R
= 30kΩ
L
8 IC RL
AV + gMRL
+
[ 0.002RL
2kT
R
= RESISTANCE FROM
L
PIN 9 TO GND
100 1k 10k
FREQUENCY - (Hz)
and can easily be reduced from a nominal of 10,000 by an external
shunt resistance from Pin 9 to ground, as shown in Figure 7.
10
100k 1M
10M
SL00180
In addition to DC gain control, the compensation terminal is also the
place for AC phase compensation. The frequency response curves
of Figure 7 show the uncompensated amplifier with a single pole at
approximately 200Hz and a unity gain crossover at 5MHz.
Figure 7. Amplifiers Open-Loop Gain as a Function of
Frequency and Loading on Pin 9
Typically, most output filter designs will introduce one or more
additional poles at a significantly lower frequency. Therefore, the
best stabilizing network is a series RC combination between Pin 9
and ground which introduces a zero to cancel one of the output filter
poles. A good starting point is 50kΩ plus 0.001µF.
Oscillator
The oscillator in the SG3524 uses an external resistor (R ) to
T
establish a constant charging current into an external capacitor (C ).
T
While this uses more current than a series-connected RC, it
provides a linear ramp voltage on the capacitor which is also used
as a reference for the comparator. The charging current is equal to
4
1994 Aug 31
Philips Semiconductors
Product specification
SMPS control circuit
SG3524
One final point on the compensation terminal is that this is also a
convenient place to insert any programming signal which is to
override the error amplifier. Internal shutdown and current limit
circuits are connected here, but any other circuit which can sink
200µA can pull this point to ground, thus shutting off both outputs.
V
REF
R
2
POSITIVE
OUTPUT
VOLTAGES
5k
5k
2
+
1
–
While feedback is normally applied around the entire regulator, the
error amplifier can be used with conventional operational amplifier
feedback and is stable in either the inverting or non-inverting mode.
Regardless of the connections, however, input common-mode limits
must be observed or output signal inversions may result. For
conventional regulator applications, the 5V reference voltage must
be divided down as shown in Figure 8. The error amplifier may also
be used in fixed duty cycle applications by using the unity gain
configuration shown in the open-loop test circuit.
R
1
GND
REF
V
R
1
5k
2
+
–
1
Current Limiting
The current limiting circuitry of the SG3524 is shown in Figure 9.
NEGATIVE
OUTPUT
VOLTAGES
5k
R
2
GND
By matching the base-emitter voltages of Q1 and Q2, and assuming
a negligible voltage drop across R :
1
SL00181
Threshold=V (Q1)+I R -V (Q2)
Figure 8. Error Amplifier Biasing Circuits
BE
1
2
BE
=I R
1
200mV
2
9
Although this circuit provides a relatively small threshold with a
negligible temperature coefficient, there are some limitations to its
use, the most important of which is the ±1V common-mode range
which requires sensing in the ground line. Another factor to consider
RAMP
t
1
ERROR
AMPLIFIER
C
COMPARATOR
1
is that the frequency compensation provided by R C and Q1
1
1
R
1
provides a roll-off pole at approximately 300Hz.
R
1
Q1
Since the gain of this circuit is relatively low, there is a transition
region as the current limit amplifier takes over pulse width control
from the error amplifier. For testing purposes, threshold is defined as
the input voltage required to get 25% duty cycle with the error
amplifier signaling maximum duty cycle.
Q2
5
4
–
SENSE
+
SL00182
In addition to constant current limiting, Pins 4 and 5 may also be
used in transformer-coupled circuits to sense primary current and to
shorten an output pulse, should transformer saturation occur.
Another application is to ground Pin 5 and use Pin 4 as an additional
shutdown terminal: i.e., the output will be off with Pin 4 open and on
when it is grounded. Finally, foldback current limiting can be
provided with the network of Figure 10. This circuit can reduce the
Figure 9. Current Limiting Circuitry of the SG3524
V
= 5V
O
S
/S
B
A
R
R
1
2
short-circuit current (I ) to approximately one-third the maximum
SC
available output current (I
).
MAX
R
S
–
5
4
SENSE
+
V
R
2
R
0
1
I
+
V
MAX
TH
R
R
1
2
S
V
TH
I
+
SC
V
R
where
S
= 200mV
TH
NOTE:
Foldback current limiting can be used to reduce power dissipation
under shorted output conditions.
SL00183
Figure 10. Foldback Current Limiting
5
1994 Aug 31
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