SJA1105 [NXP]
5-port automotive Ethernet switch;
| 型号： | SJA1105 |
| 厂家： | 
NXP |
| 描述： | 5-port automotive Ethernet switch |
| 文件： | 总34页 (文件大小：301K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SJA1105
5-port automotive Ethernet switch
Rev. 1 — 7 November 2016
Product data sheet
1. General description
The SJA1105 is an IEEE 802.3-compliant 5-port automotive Ethernet switch. Each of the
five ports can be individually configured to operate in MII, RMII and RGMII modes. This
arrangement provides the flexibility to connect a mix of switches, microprocessors and
PHY devices such as the TJA1100 BroadR-Reach PHY from NXP Semiconductors
(Ref. 1 and Ref. 2) and other commercially available Fast Ethernet and Gigabit Ethernet
PHYs. The high-speed interface makes it easy to cascade multiple SJA1105s for
scalability. It can be used in various automotive scenarios such as gateway applications,
body domain controllers or for interconnecting multiple ECUs in a daisy chain. Audio
Video Bridging (AVB) support (Ref. 3) fully leverages infotainment and advanced driver
assistance systems.
The SJA1105 comes in two pin-compatible variants. The SJA1105EL supports Ethernet
and AVB. The SJA1105TEL includes additional functionality to support Time-Triggered
Ethernet (TTEthernet) and Time-Sensitive Networking (TSN).
2. Features and benefits
2.1 General features
5-port store and forward architecture
Each port individually configurable for MII and RMII operation at 10 Mbit/s or
100 Mbit/s and RGMII operation at 10 Mbit/s, 100 Mbit/s or 1000 Mbit/s
Interface-dependent selectable I/O supply voltages; 1.2 V core voltage
Small footprint: LFBGA159 (12 mm 12 mm) package
Automotive Grade 2 ambient operating temperature: 40 C to +105 C
Automotive product qualification in accordance with AEC-Q100
2.2 Ethernet switching and AVB features
IEEE 802.3 compliant
128 kB frame buffer
1024 entry MAC address learning table
Address learning space can be configured for static and learned addresses
2 kB frame length handling
IEEE 802.1Q defined tag support
4096 VLANs
Egress tagging/untagging on a per-VLAN basis per port
QoS handling based on IEEE 802.1Q
Per-port priority remapping and 8 configurable egress queues per port
SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
Ingress rate-limiting on a per-port and per-priority basis for Unicast/Multicast and
Broadcast traffic
Frame replication and retagging of traffic
Frame mirroring for enhanced diagnostics
Hardware support for IEEE 802.1AS and IEEE 802.1Qav for AVB traffic support
Ingress and egress timestamping per port
Ten IEEE 802.1Qav credit-based shapers available; shapers can be freely allocated to
any priority queue on a per port basis
Support for AVB SR Class A, Class B and Class C traffic
IEEE 1588v2 one-step sync forwarding in hardware
IEEE 802.1X support for setting port reachability and disabling address learning
Broadcast storm protection
Statistics for dropped frames and buffer load
2.3 TT and TSN features (SJA1105TEL only)
IEEE 802.1Qbv time-aware traffic
IEEE 802.1Qci per-stream policing (pre-standard)
Support for ring-based redundancy (for time-triggered traffic only)
1024 deterministic Ethernet flows with per-flow based:
Time-triggered traffic transmission
Ingress policing and reception window check
Active and redundant routes
Statistics
2.4 Interface features
MII/RMII interfaces supporting all standard Ethernet PHY technologies such as (but
not limited to) Fast Ethernet (IEEE 100BASE-TX), IEEE 100BASE-T1 and optical
PHYs
RGMII for interfacing with Gigabit Ethernet (1000BASE-T) PHYs (Gigabit Ethernet;
Ref. 4)
MAC and PHY modes for interfacing (MII/RMII/RGMII) directly with another switch or
host processor
Programmable drive strength for all interfaces
SPI at up to 25 MHz for host processor access
2.5 Other features
25 MHz system clock input from crystal oscillator or AC-coupled single-ended clock
25 MHz reference clock output
Device reset input from host processor
IEEE 1149.1 compliant JTAG interface for TAP controller access and boundary scan
SJA1105
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 7 November 2016
2 of 34
SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
3. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
SJA1105EL
LFBGA159 plastic low profile fine-pitch ball grid array package; 159 balls
SOT1427-1
SJA1105TEL
4. Block diagram
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Fig 1. Block diagram of SJA1105EL
SJA1105
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 7 November 2016
3 of 34
SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
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Fig 2. Block diagram of SJA1105TEL
SJA1105
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 7 November 2016
4 of 34
SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
5. Pinning information
5.1 Pinning
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SJA1105
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 7 November 2016
5 of 34
SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
5.2 Pin description
Table 2.
Symbol
Pin description - xMII interface[1]
Pin
Type[2] Description
MII interface:
0
1
2
3
4
VDDIO_
MIIx
D4
E4
G4
D5 D10 G11 L8
D7 D11 H11 L10
D8 E11 K11 L11
P
3.3 V/2.5 V I/O supply voltage
TX_CLK/ D1
REF_CLK/
TXC
A7 C14 K14 N9 I/O
TX_CLK: MII interface transmit clock (also configurable as output)
REF_CLK: RMII interface reference clock (also configurable as input)
TXC: RGMII interface transmit clock
I/O
O
TX_EN/
TX_CTL
D2
B7 C13 K13 P9
O
TX_EN: MII/RMII interface transmit enable input
TX_CTL: RGMII interface transmit control output
TX_ER
TXD0
TXD1
TXD2
TXD3
A3
A2
B1
C2
C1
A10 F14 N14 P6
B9 E13 M13 P7
A9 E14 M14 N7
B8 D13 L13 P8
A8 D14 L14 N8
O
O
O
O
O
MII/RMII interface transmit coding error output
MII/RMII/RGMII interface transmit data output, bit 0
MII/RMII/RGMII interface transmit data output, bit 1
MII/RGMII interface transmit data output, bit 2
MII/RGMII interface transmit data output, bit 3
RX_CLK/ E2
RXC
B6 B14 J13 P10 I/O
I
RX_CLK: MII interface receive clock (also configurable as output)
RXC: RGMII interface receive clock
RX_ER
H2
G1
B3 B10 F13 P13
I
MII/RMII interface receive error input
RX_DV/
CRS_DV/
RX_CTL
A4 A11 G14 N12 I
RX_DV: MII interface receive data valid input
CRS_DV: RMII interface carrier sense/data valid input
RX_CTL: RGMII interface receive control input
RXD0
RXD1
RXD2
RXD3
E1
F2
F1
G2
A6 A13 J14 N10 I
MII/RMII/RGMII interface receive data input, bit 0
MII/RMII/RGMII interface receive data input, bit 1
MII/RGMII interface receive data input, bit 2
MII/RGMII interface receive data input, bit 3
B5 B12 H13 P11
A5 A12 H14 N11
B4 B11 G13 P12
I
I
I
[1] xMII I/O pins will be floating until the configuration has been loaded.
[2] I: digital input; O: digital output; P: power supply.
Table 3.
Symbol
Pin description - core supply and ground
Pin
Type[1] Description
VDD_CORE
VSS
D6, D9, F4, F11, J4, J11, L6, L9
P
1.2 V core supply voltage
A1, A14, B13, E5, E6, E7, E8, E9, E10, F5, F6, F7, F8, F9, F10,
G5, G6, G7, G8, G9, G10, H5, H6, H7, H8, H9, H10, J5, J6, J7,
J8, J9, J10, K4, K5, K6, K7, K8, K9, K10, L7, N2, N13, P1, P14
G
supply ground
[1] P: power supply; G: ground.
SJA1105
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© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 7 November 2016
6 of 34
SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
Table 4.
Symbol
RST_N[2]
PTP_CLK
VDDIO_HOST
i.c.
Pin description - general
Pin
P3
N4
L5
Type[1]
Description
I
reset input (active LOW)
PTP clock
O
P
G
host interface supply voltage
L4
internally connected; must be connected to ground
Clock generation (CGU)
VDDA_OSC
VSSA_OSC
VDDA_PLL
VSSA_PLL
VDDIO_CLO
CLK_OUT
OSC_IN
OSC_OUT
SPI interface
SCK
K1
L2
J1
P
G
P
G
P
O
I
oscillator supply voltage
oscillator supply ground
PLL supply voltage
PLL supply ground
J2
H4
H1
K2
L1
clock output supply voltage (CLK_OUT)
clock output
oscillator input
O
oscillator output
P5
N5
P4
N6
I
SPI clock
SDI
I
SPI data input
SDO
O
I
SPI data output
SS_N
SPI slave select (active LOW)
JTAG interface[3]
TRST_N
TDI
M1
M2
N1
P2
N3
I
test reset (active LOW)
test data in
I
TCK
I
test clock
TMS
I
test mode state
test data out
TDO
O
[1] I: digital input; O: digital output; P: power supply, G: ground.
[2] Pins RST_N and TRST_N must be held LOW simultaneously to reset the device.
[3] JTAG pins have internal pull-ups.
SJA1105
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© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 7 November 2016
7 of 34
SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
6. Functional description
The SJA1105 is designed to provide a cost-optimized and flexible solution for automotive
Ethernet switches. Each port can be independently configured for MII, RMII or RGMII
operation. Switch configuration is performed via an SPI interface. A typical system
diagram is shown in Figure 5.
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Fig 5. System diagram showing the SJA1105 Ethernet switch connected to PHYs and a
host processor
6.1 Functional overview
The SJA1105 contains the following functional modules (see the block diagrams in
Figure 1 and Figure 2):
6.1.1 Auxiliary Configuration Unit (ACU)
This module contains the pin configuration and status registers. The host can configure
the I/O pads of the chip (pull-up/-down, speed etc.) and monitor the product configuration
and temperature sensor status via these registers.
6.1.2 Clock Generation Unit (CGU)
This module contains the oscillator and PLLs used to generate clocks for all internal
blocks and a number of interface output clocks.
6.1.3 Reset Generation Unit (RGU)
This block ensures that the device transitions to a pre-defined state after power-up or an
externally asserted reset.
SJA1105
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© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 7 November 2016
8 of 34
SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
6.1.4 Serial Peripheral Interface (SPI)
The host controller manages access to the internal configuration and programming space
via the SPI.
6.1.5 Status and Control Unit (SCU)
This block contains the switch core status and configuration registers. The host processor
accesses these registers via the SPI.
6.1.6 Configuration Stream Decoder/Configuration Controller (CSD/CC)
This block handles the distribution of the configuration stream from the host processor to
the other modules and performs a CRC check on the configuration blocks.
6.1.7 xMII
This block is a wrapper and multiplexer for the MII interface options. The device supports
MII, RMII and RGMII.
6.1.8 Dynamic Memory Management (DMM)/Frame Memory Controller (FMC)/
Frame Buffer Management (FBM)
These blocks deal with the storage and handling of frames in the memory buffer. The
DMM provides memory handles for ingress frames and holds meta information related to
the frames. The DMM releases frame handles for frames that are transmitted or dropped.
The FMC converts frame handles into virtual memory addresses and the FBM optimizes
the use of on-chip frame memory based on frame size.
6.1.9 Receive MAC (RXM)
The RXM loads the data from the xMII interface block and checks the IFG, the preamble,
the SOF delimiter, the CRC and the frame length. It provides timestamps for clock
synchronization frames, extracts frame metadata such as MAC addresses and VLAN
information and drops runt and oversized frames. The RXM collects memory handles from
the DMM and transfers frame data to the FMC block for writing to memory.
6.1.10 Input Queue (IQ)
The IQ arranges the frame processing order so that the switching fabric behaves in a
deterministic manner. If two ports each receive the last byte of a complete frame in the
same clock cycle, the lower port ID is processed first.
6.1.11 VLAN Lookup (VLAN_LU)
The forwarding limitations and tagging/untagging options are determined in the VLAN_LU
block.
6.1.12 Address Lookup (L2ADDR_LU)
The forwarding information for frames based on the destination MAC address in
combination with the VLAN ID are determined in this block. The lookup table is addressed
using an 8-bit hash value computed from the destination MAC address and the VLAN ID.
Up to four entries are supported per hash value. The table holds dynamically learned as
well as statically configured entries. Dynamically learned entries can be configured to
time-out. The address lookup process can be configured to use shared or independent
address learning.
SJA1105
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 7 November 2016
9 of 34
SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
6.1.13 Policing (L2_POLICE)
Ingress policing rules are enforced in the L2_POLICE block. The transmission rate can be
limited for any of the eight priority levels and for broadcast traffic at each port.
Non-compliant traffic is dropped and is indicated by associated flags and counters.
6.1.14 Forwarding (L2_FORW)
The L2_FORW block forwards frames to the destination ports. It maintains a vector of
reachable ports for unicast traffic for each ingress port. In addition, it maintains a vector of
destination ports for broadcast traffic and for unknown multicast traffic. This block also
maintains a memory partition account for traffic received per port and drops frames if there
is insufficient space. This block also handles priority remapping and egress queue priority
mapping.
6.1.15 Transmit MAC (TXM)
This block handles frame output via the xMII interface. It supports eight priority queues
and implements strict-priority scheduling. The AVB block can interrupt the scheduling from
specific priority queues in case shapers are allocated to queues. When a frame is
selected for transmission, this block gets the frame data from the FMC using the memory
handle of the frame. It passes the free memory handle back to the DMM once the frame
has been transmitted. It also inserts VLAN tags into packet headers. It can be configured
to perform the IEEE 1588v2 transparent clock update for synchronization frames.
6.1.16 Audio Video Bridging (AVB)
This block implements credit-based traffic shaping and interrupts transmission from
priority queues in the TXM when necessary to ensure that shaping occurs. It also captures
high-resolution timestamps for IEEE 802.1AS and IEEE 1588v2 operation. The host
processor can adjust the IEEE 1588v2 hardware clock via this block.
6.1.17 Loopback Port (LBP)
This block uses an internal port to replicate a frame internally and change the VLAN tag to
support ingress and egress retagging of traffic. The replicated frame-handling information
is fed back to the IQ which processes the frame in the same way as a frame from a
regular traffic port.
6.1.18 Virtual Link Lookup (VL_LU); SJA1105TEL only
The VL_LU block performs a lookup of time-triggered and rate-constrained traffic based
on the configured Virtual Link Multicast addresses, the VLAN ID and the VLAN priority
identifying time-triggered or rate-constrained traffic.
6.1.19 Virtual Link Policing (VL_POLICE); SJA1105TEL only
The VL_POLICE block executes policing functions based on the time-triggered Ethernet
or rate-constrained traffic rule set. Policing mechanisms can be configured individually per
flow (i.e. per virtual link). Time-triggered Ethernet policing verifies that a frame received by
the switch was sent at the correct point in time by the neighboring node. Non-compliant
frames are dropped and are indicated by associated flags and counters.
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5-port automotive Ethernet switch
6.1.20 Virtual Link Forwarding (VL_FORW); SJA1105TEL only
The VL_FORW block forwards time-triggered or rate-constrained traffic to the destination
ports. Time-triggered traffic is stored in this module until the running traffic schedule fires a
transmit trigger for the respective Virtual Link. Rate-constrained traffic is immediately
routed to the destination ports. All time-triggered frames are dropped if synchronization is
lost.
6.1.21 Clock Synchronization Subsystem (CSS) and Schedule Engine (SCH);
SJA1105TEL only
This block implements the clock synchronization protocol and executes the message
schedules.
6.2 Media Independent Interfaces (xMII)
The SJA1105 xMII interfaces can be configured to support a wide variety of PHYs and
host controllers. Each port can be configured for MAC-to-PHY or MAC-to-MAC
communication. The following configurations are supported:
MII: 25 MHz clock for 100 Mbit/s or 2.5 MHz for 10 Mbit/s operation, 14 interface signals,
full duplex only, 3.3 V (Ref. 5)
RMII: 50 MHz clock for 100 Mbit/s and 10 Mbit/s operation, 8 interface signals (reference
clock can be an input to both devices or may be driven from MAC to PHY), full duplex
only, 3.3 V specification (Ref. 6)
RGMII: 125 MHz clock (both edges) for 1000 Mbit/s, 25 MHz for 100 Mbit/s or 2.5 MHz for
10 Mbit/s operation, 12 interface signals; full duplex only, 2.5 V (Ref. 4)
Depending on how the switch is configured, the following interface signals are available at
each of the five ports:
Table 5.
MII pin multiplexing
MII (14 interface signals)
TX_CLK
TX_EN
RMII (8 interface signals)
RGMII (12 interface signals)
REF_CLK
TXC
TX_EN
TX_CTL
-
TX_ER
TX_ER
TXD0
TXD0
TXD0
TXD1
TXD2
TXD3
RXC
TXD1
TXD1
TXD2
-
TXD3
-
RX_CLK
RX_ER
RX_DV
RXD0
-
RX_ER
CRS_DV
RXD0
RXD1
-
-
RX_CTL
RXD0
RXD1
RXD2
RXD3
RXD1
RXD2
RXD3
-
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5-port automotive Ethernet switch
6.2.1 MII signaling and encoding
Figure 6 shows the PHY-MAC and MAC-MAC connections in an MII interface. Data is
exchanged via 4-bit wide data nibbles TXD[3:0] and RXD[3:0]. Data transmission is
synchronous with the transmit (TX_CLK) and receive (RX_CLK) clocks. For the PHY-MAC
interface, both clock signals are provided by the PHY and are typically derived from an
external crystal running at a nominal 25 MHz (100 ppm) or from the CLK_OUT signal on
the switch. When the Ethernet Switch is configured for MAC-MAC communication, the
switch provides the clocks and acts like a PHY.
A HIGH level on TX_EN initiates data transmission; a HIGH level on RX_DV signals data
reception.
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a. PHY-MAC interface
Fig 6. MII interface connections
b. MAC-MAC interface
6.2.2 RMII signaling and encoding
RMII data is exchanged via 2-bit data signals TXD[1:0] and RXD[1:0] as shown in
Figure 7. Transmit and receive signals are synchronous with the shared reference clock,
REF_CLK.
In the PHY-MAC configuration, the REF_CLK shared reference clock can be generated by
the Ethernet switch. In the MAC-MAC configuration, the external MAC can supply the
reference clock.
To achieve the same data rate as MII, the interface is clocked at a nominal 50 MHz
(50 ppm) for 100 Mbit/s and 10 Mbit/s operation.
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Product data sheet
Rev. 1 — 7 November 2016
12 of 34
SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
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a. PHY-MAC interface
Fig 7. RMII interface connections
b. MAC-MAC interface
6.2.3 RGMII signaling and encoding
The PHY-MAC and MAC-MAC connections in an RGMII-configured interface are shown in
Figure 8. The RGMII protocol is intended to be an alternative to the IEEE 802.3z GMII
standard (not supported on the SJA1105). The objective is to reduce the number of pins
needed to connect the MAC and PHY in a cost-effective and technology-independent
way. RGMII has the added advantage over RMII in that it supports Gigabit operation.
In order to achieve a reduced pin count, the number of data signals and associated
control signals is reduced. Control signals are multiplexed together and transmitted data is
synchronized with both clock edges (double data rate).
RGMII is a symmetrical interface. For 1000 Mbit/s, 100 Mbit/s and 10 Mbit/s operation, the
clocks operate at 125 MHz, 25 MHz and 2.5 MHz (50 ppm) respectively. The TXC signal
is always generated by the MAC. The PHY generates the RXC. Note that RGMII requires
an external delay of between 1.5 ns and 2 ns on TXC and RXC.
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a. PHY-MAC interface
Fig 8. RGMII interface connections
b. MAC-MAC interface
SJA1105
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Product data sheet
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SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
6.3 SPI interface
The SJA1105 provides an SPI bus slave as the host control interface. The host can
control/configure the SJA1105 by accessing the configuration address space and the
programming address space.
This interface acts as a slave in a synchronous serial data link that conforms with the SPI
standard as defined in the SPI Block Guide from Motorola (Ref. 7). The interface operates
in SPI Transfer mode 1 (CPOL = 0, CPHA = 1).
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Fig 9. SPI transfer timing (example)
An example SPI timing diagram is shown in Figure 9. Data is captured on the falling edge
of the clock and transmitted on the rising edge. Both master and slave must operate in the
same mode.
When CGU registers are read, a 64 ns delay must be inserted between the control and
data phases to allow the device to retrieve the data. Alternatively, the access can be
performed at a frequency below 17.8 MHz. In addition, a read-after-write time of >130 ns
between an SPI write and read transaction to the same register must be guaranteed. See
the SJA1105 software user manuals (Ref. 8) for further details on the data format.
The number of SPI clock cycles must be between 64 and 2080 and be a multiple of 32. In
order to ensure support for a wide a range of microcontrollers, the SPI interface can
operate at a supply voltage of 3.3 V, 2.5 V or 1.8 V (determined by the voltage connected
to VDDIO_HOST; see Section 11).
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Product data sheet
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SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
7. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VDDA(osc)
oscillator analog supply
voltage
on pin VDDA_OSC
0.5
+1.6
V
VDDA(PLL)
VDDC
PLL analog supply voltage
core supply voltage
host supply voltage
clock supply voltage
MII supply voltage
on pin VDDA_PLL
on pins VDD_CORE
on pin VDDIO_HOST
on pin VDDIO_CLO
on pins VDDIO_MIIx
0.5
0.5
0.5
0.5
0.5
+1.6
+1.6
+5
V
V
V
V
V
V
VDD(host)
VDD(clk)
VDD(MII)
VESD
+5
+5
[1]
[2]
electrostatic discharge voltage Human Body Model (HBM); 100 pF, 1.5 k
2000 +2000
Charged Device Model (CDM)
corner balls
other balls
750
500
40
+750
+500
+125
+150
V
V
Tj
junction temperature
C
C
Tstg
storage temperature
55
[1] According to AEC-Q100-002.
[2] According to AEC-Q100-011.
8. Thermal characteristics
Table 7.
Symbol
Rth(j-a)
Thermal characteristics
Parameter
Conditions
Typ
Unit
K/W
K/W
K/W
thermal resistance from junction to ambient
thermal resistance from junction to lead
4-layer board (JESD51-9)
4-layer board (JESD51-9)
29
Rth(j-lead)
j-top
15
thermal characterization parameter from junction to top 4-layer board (JESD51-9)
of package
0.33
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5-port automotive Ethernet switch
9. Static characteristics
Table 8.
Static characteristics
Tj = 40 C to +125 C; all voltages are defined with respect to ground unless otherwise specified; positive currents flow into
the IC.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Supply voltages; see Figure 15
Clock and host interface supply (pins VDDIO_CLO and VDDIO_HOST)
VDD(clk)
clock supply voltage
3.3 V signaling
2.5 V signaling
1.8 V signaling
3.3 V signaling
2.5 V signaling
1.8 V signaling
3.00
2.30
1.65
3.00
2.30
1.65
3.30
2.50
1.80
3.30
2.50
1.80
3.60
2.70
1.95
3.60
2.70
1.95
V
V
V
V
V
V
VDD(host) host supply voltage
MII interface supply (pins VDDIO_MII0 to VDDIO_MII4)
VDD(MII)
MII supply voltage
MII/RMII
RGMII
3.00
2.30
3.30
2.50
3.60
2.70
V
V
Core, oscillator and PLL supply (pins VDD_CORE, VDDA_OSC and VDDA_PLL)
VDDC core supply voltage see Figure 15
1.14
1.10
1.10
1.20
1.20
1.20
1.30
1.30
1.30
V
V
V
VDDA(osc) oscillator analog supply voltage
VDDA(PLL) PLL analog supply voltage
Supply currents
Clock and host interface supply (pins VDDIO_CLO and VDDIO_HOST)
IDD(host)
IDD(clk)
host supply current
clock supply current
VDD(HOST) = 3.30 V
VVDD(CLK) = 3.30 V
-
-
-
-
2.8
3.5
mA
mA
MII interface supply (pins VDDIO_MII0 to VDDIO_MII4)
IDD(MII)
MII supply current
port set to RGMII, 1 Gbit/s
CL = 18 pF
-
-
-
-
65.5
mA
mA
mA
25 % load PRBS
100 % load PRBS
port set to RMII, 100 Mbit/s
CL = 25 pF
14.3
31.8
-
-
-
-
-
-
15.5
mA
mA
mA
25 % load PRBS
100 % load PRBS
port set to MII, 100 Mbit/s
CL = 25 pF
6.8
8.5
-
-
-
-
-
-
11.5
mA
mA
mA
25 % load PRBS
100 % load PRBS
0.7
2.4
-
-
SJA1105
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5-port automotive Ethernet switch
Table 8.
Static characteristics …continued
Tj = 40 C to +125 C; all voltages are defined with respect to ground unless otherwise specified; positive currents flow into
the IC.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Core, oscillator and PLL supply (pins VDD_CORE, VDDA_OSC and VDDA_PLL)
IDDC
core supply current
worst case
-
-
110
mA
all ports set to RGMII,
1 Gbit/s
25 % PRBS
-
-
37.7
54.3
-
-
mA
mA
100 % PRBS
all ports set to MII/RMII, 100 Mbit/s
25 % PRBS
-
-
-
-
31.0
-
mA
mA
mA
mA
100 % PRBS
33.2
-
IDDA(PLL) PLL analog supply current
PLL0 enabled; see Ref. 8
-
-
1.2
2.4
PLL0 and PLL1 enabled; see
Ref. 8
IDDA(osc)
oscillator analog supply current
-
350
1.0
-
A
Istartup(osc) oscillator start-up current
Power-On Reset (POR)
0.2
2.5
mA
Vtrip(POR) power-on reset trip voltage
HIGH level
LOW level
0.65
0.60
0.76
0.72
1.01
0.91
V
V
pin RST_N[1]
Vhys(i)
input hysteresis voltage
0.1
VVDD(HOST)
-
-
-
-
-
V
V
V
V
VIH
HIGH-level input voltage
3.3 V signaling
2.5 V signaling
1.8 V signaling
2.0
1.7
VVDD(HOST)
+ 0.5
VVDD(HOST)
+ 0.5
0.65
VVDD(HOST)
VVDD(HOST)
+ 0.5
VIL
LOW-level input voltage
3.3 V signaling
2.5 V signaling
1.8 V signaling
0.5
0.5
0.5
-
-
-
+0.8
+0.7
V
V
V
+0.35
VVDD(HOST)
Rpu(weak) weak pull-up resistance
Ci input capacitance
40
-
50
-
57
k
8.0
pF
Oscillator (pins OSC_IN and OSC_OUT)
Crystal oscillator mode
Ci
input capacitance
on pin OSC_IN
-
-
-
-
-
3.5
7.0
-
pF
pF
pF
pF
Cshunt
CL(ext)
shunt capacitance
-
[2]
[2]
external load capacitance
on pin OSC_IN
8
8
on pin OSC_OUT
-
Clock mode
Cdec
decoupling capacitance
-
100
-
-
pF
V
Vi(OSC_IN) input voltage on pin OSC_IN
RMS value
0.20
VDDA(OSC)
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5-port automotive Ethernet switch
Table 8.
Static characteristics …continued
Tj = 40 C to +125 C; all voltages are defined with respect to ground unless otherwise specified; positive currents flow into
the IC.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
I/O pins (VDDIO_MII0 to VDDIO_MII4, SPI, JTAG, CLK_OUT, PTP_CLK)
VIH
HIGH-level input voltage
3.3 V signaling (supported for
MII/RMII operation)
2.0
-
-
-
VDDx + 0.5[3]
V
2.5 V signaling (supported for
RGMII operation)
1.7
VDDx[3] + 0.5 V
VDDx[3] + 0.5 V
1.8 V signaling (not supported
for MII, RMII or RGMII)
0.65
VDDx
[3]
VIL
LOW-level input voltage
input hysteresis voltage
3.3 V signaling
2.5 V signaling
1.8 V signaling
0.5
0.5
0.5
-
-
-
+0.8
V
V
V
+0.7
+0.35
VDDx
[3]
Vhys(i)
0.1
VDDx
-
-
V
[3]
Rpu(weak) weak pull-up resistance
Rpd(weak) weak pull-down resistance
VIO = 0 V
40.0
40.0
-
50.0
50.0
-
57.0
k
k
mA
VIO = VDDx
57.0
IOSH
HIGH-level short-circuit output
current
111.7
IOSL
LOW-level short-circuit output
current
-
-
110.2
mA
Ci
input capacitance
output impedance
-
-
-
5.0
pF
Zo
40.0
67.5
[1] Pins RST_N and TRST_N must be held LOW simultaneously to reset the device.
[2] Value is crystal dependent.
[3] Supply voltage on I/O pin x.
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5-port automotive Ethernet switch
10. Dynamic characteristics
Table 9.
Dynamic characteristics
Tj = 40 C to +125 C; capacitive load of 4 pF; all voltages are defined with respect to ground unless otherwise specified;
positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
I/O pins (VDDIO_MII0 to VDDIO_MII4, SPI, JTAG, CLK_OUT, PTP_CLK)
tr(o)
output rise time
3.3 V signaling
high-speed mode
fast-speed mode
medium-speed mode
low-speed mode
2.5 V signaling
0.3
0.5
0.8
1.4
-
-
-
-
0.8
1.3
2.0
2.7
ns
ns
ns
ns
high-speed mode
fast-speed mode
medium-speed mode
low-speed mode
1.8 V signaling
0.4
0.6
1.1
1.8
-
-
-
-
1.1
1.7
2.4
3.1
ns
ns
ns
ns
high-speed mode
fast-speed mode
medium-speed mode
low-speed mode
3.3 V signaling
0.5
0.9
1.5
2.3
-
-
-
-
1.9
2.5
3.2
4.1
ns
ns
ns
ns
tf(o)
output fall time
high-speed mode
fast-speed mode
medium-speed mode
low-speed mode
2.5 V signaling
0.6
0.6
0.6
1.2
-
-
-
-
0.8
1.0
1.8
2.7
ns
ns
ns
ns
high-speed mode
fast-speed mode
medium-speed mode
low-speed mode
1.8 V signaling
0.5
0.5
1.0
1.6
-
-
-
-
0.9
1.4
2.3
3.0
ns
ns
ns
ns
high-speed mode
fast-speed mode
medium-speed mode
low-speed mode
0.5
0.7
1.4
2.0
-
-
-
-
1.6
2.3
3.0
3.9
ns
ns
ns
ns
Oscillator (pins OSC_IN and OSC_OUT)
Crystal oscillator mode[1]
fxtal
crystal frequency
start-up time
-
-
25
-
MHz
tstartup
25 MHz crystal;
275
800
s
COSC_IN = COSC_OUT = 8 pF
duty cycle
45
50
55
%
SJA1105
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Product data sheet
Rev. 1 — 7 November 2016
19 of 34
SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
Table 9.
Dynamic characteristics …continued
Tj = 40 C to +125 C; capacitive load of 4 pF; all voltages are defined with respect to ground unless otherwise specified;
positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Ncy(clk)startup
number of start-up clock cycles
until clock is stable;
25 MHz crystal;
-
1000
-
-
COSC_IN = COSC_OUT = 8 pF
Clock mode
fclk(i)
input clock frequency
-
-
25
10
-
-
MHz
-
Ncy(clk)startup
number of start-up clock cycles
until clock is stable
pin RST_N
tw
pulse width
5.0
-
-
s
pin CLK_OUT
fclk
clock frequency
duty cycle
-
25
50
-
MHz
%
40
60
pin PTP_CLK
fclk
clock frequency
duty cycle
-
-
100
50
-
-
kHz
%
SPI: pins SS_N, SCK, SDI and SDO
[2]
fclk
clock frequency
0.1
45
12.4
18
0
-
25
55
-
MHz
%
duty cycle
50
-
tsu(D)
th(D)
td(clk-data)
data input set-up time
data input hold time
clock to data delay time
w.r.t. SCK sampling edge
w.r.t. SCK sampling edge
ns
-
-
ns
w.r.t. SCK launching edge;
-
14
ns
high-speed mode; 25 pF load
td(W-R)
write to read delay time
130
64
-
-
-
-
ns
ns
td(addr-data)
address to data delay time
JTAG: pins TRST_N, TDI, TCK, TMS and TDO
fclk
clock frequency
duty cycle
0.1
40
-
16
MHz
%
50
60
tw
pulse width
on pin TRST_N
100.0 -
-
ns
tsu(D)
th(D)
td(clk-data)
data input set-up time
data input hold time
clock to data delay time
w.r.t. TCK sampling edge
w.r.t. TCK sampling edge
4.0
25
-
-
-
-
-
ns
-
ns
w.r.t. TCK launching edge;
20.0
ns
high-speed mode; 25 pF load
xMII ports
port configured by host for MII MAC mode; pad speed selection: medium noise, fast speed
fclk
clock frequency
transmit (TX_CLK) and receive
(RX_CLK) clocks; 100 Mbit/s
operating speed
-
25
-
MHz
duty cycle
of transmit and receive clocks
35
10
50
-
65
-
%
tsu(D)
data input set-up time
on pins RXDx, RX_DV and RX_ER
w.r.t. rising edge on RX_CLK
ns
th(D)
data input hold time
on pins RXDx, RX_DV and RX_ER
w.r.t. rising edge on RX_CLK
10
-
-
ns
SJA1105
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Product data sheet
Rev. 1 — 7 November 2016
20 of 34
SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
Table 9.
Dynamic characteristics …continued
Tj = 40 C to +125 C; capacitive load of 4 pF; all voltages are defined with respect to ground unless otherwise specified;
positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
td(clk-data)
clock to data delay time
on pins TXDx, TX_EN and TX_ER
w.r.t. rising edge on TX_CLK
0
-
25
ns
port configured by host for MII PHY mode; pad speed selection: medium noise, fast speed
tsu(D)
data input set-up time
data input hold time
clock to data delay time
on pins RXDx, RX_DV and RX_ER
w.r.t. rising edge on RX_CLK
10
0
-
-
-
-
ns
ns
ns
th(D)
on pins RXDx, RX_DV and RX_ER
w.r.t. rising edge on RX_CLK
-
td(clk-data)
on pins TXDx, TX_EN and TX_ER
w.r.t. rising edge on TX_CLK
12
25
port configured by host for RMII mode; pad speed selection: medium noise, fast speed
fclk
clock frequency
reference clock (REF_CLK);
100 Mbit/s operating speed
-
50
-
MHz
duty cycle
of reference clock
35
4
50
-
65
-
%
tsu(D)
data input set-up time
on pins RXDx, CRS_DV and
RX_ER w.r.t. rising edge on
REF_CLK
ns
th(D)
data input hold time
on pins RXDx, CRS_DV and
RX_ER w.r.t. rising edge on
REF_CLK
0
2
-
-
-
ns
ns
td(clk-data)
clock to data delay time
on pins RXDx, CRS_DV and
RX_ER w.r.t. rising edge on
REF_CLK; fast speed I/O setting
10
port configured by host for RGMII mode; pad speed selection: high noise, high speed
fclk
clock frequency
transmit (TXC) and receive (RXC)
clocks
1 Gbit/s operating speed
100 Mbit/s operating speed
10 Mbit/s operating speed
-
-
-
125
25
-
-
-
MHz
MHz
MHz
2.5
duty cycle
of transmit and receive clocks
1 Gbit/s operating speed
45
50
50
-
55
%
%
ns
ns
100/10 Mbit/s operating speed
at the transmitter w.r.t. edge on TXC
at the receiver w.r.t. edge on RXC
40
60
tsk(o)
tsk(I)
output skew time
input skew time
0.5
1.0
+0.5
2.6
[3]
-
[1] A 100 ppm crystal is needed for MII and a 50 ppm crystal for RMII/RGMII.
[2] CGU configuration register read-access timing is stricter at 25 MHz (max); see Section 6.3.
[3] Implies that PCB board design requires the clock to be routed such that an additional trace delay of more than 1.5 ns and less than
2.0 ns is added to the associated clock signal or an external delay line is used.
SJA1105
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Product data sheet
Rev. 1 — 7 November 2016
21 of 34
SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
W
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Fig 11. RMII timing diagram
SJA1105
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© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 7 November 2016
22 of 34
SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
7;&ꢀꢁDWꢀWUDQVPLWWHUꢂ
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Fig 12. RGMII timing diagram
SJA1105
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© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 7 November 2016
23 of 34
SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
11. Application information
The SJA1105 features a programmable traffic interface. Each of the five ports can be
individually configured for 10 Mbit/s or 100 Mbit/s MII/RMII/RGMII, or for 1 Gbit/s RGMII
operation. A typical use case is illustrated in Figure 13.
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(1) RGMII requires an external delay of between 1.5 ns and 2 ns on TXC and RXC.
Fig 13. Typical SJA1105 application circuit
In this configuration, four TJA1100 BroadR-Reach PHYs are connected to the SJA1105
for MII/RMII operation while a host processor has RGMII connectivity with the SJA1105.
The I/O supply voltage needed at a port depends on the selected configuration: 3.3 V for
MII/RMII operation and 2.5 V for RGMII operation.
SJA1105
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© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 7 November 2016
24 of 34
SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
Port 1 to Port 4 are configured for MII/RMII operation, so a 3.3 V supply is connected to
pins VDDIO_MII1 to VDDIO_MII4. A 2.5 V supply is connected to VDDIO_MII1 since it is
configured for RGMII operation.
The SPI, JTAG and PTP_CLK interfaces are supplied via VDDIO_HOST. The 25 MHz
clock output, CLK_OUT, is supplied from VDDIO_CLO. Both VDDIO_HOST and
VDDIO_CLO accept a 1.8 V, 2.5 V or 3.3 V supply.
SJA1105 devices can be cascaded, as illustrated in Figure 14. Note that Ethernet
connectivity to the host processor is only needed if the system has to support AVB
operation or other bridge management protocols such as STP/RSTP. If such operations
are not needed, all the ports can be used for data traffic.
In Crystal oscillator mode, the SJA1105 oscillator is used as a crystal oscillator with an
external 25 MHz crystal and, typically, a 2 8 pF load. In Clock mode, the SJA1105
oscillator is used as a clock input with an external clock connected to input terminal
OSC_IN with OSC_OUT left open.
SJA1105
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© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 7 November 2016
25 of 34
SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
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(1) RGMII requires an external delay of between 1.5 ns and 2 ns on TXC and RXC.
Fig 14. Cascading SJA1105 devices
SJA1105
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© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 7 November 2016
26 of 34
SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
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c. core
d. PLL and oscillator
PCB layout guidelines showing capacitor placement can be found in AH1604 ‘SJA1105 Hardware Design Application Hints’
Fig 15. Power supply filtering
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b. Clock mode
Fig 16. Device clocking
11.1 Application hints
Further information on the application of the SJA1105 can be found in NXP application
hints AH1402 ‘Application Hints - 5-port Ethernet Switch’, AH1601 ‘Device Configuration
Application Hints‘, and AH1604 ‘SJA1105 Hardware Design Application Hints’.
SJA1105
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 7 November 2016
27 of 34
SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
12. Test information
12.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q100 Rev-H - Failure mechanism based stress test qualification for
integrated circuits, and is suitable for use in automotive applications.
SJA1105
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 7 November 2016
28 of 34
SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
13. Package outline
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Fig 17. Package outline SOT1427-1 (LFBGA159)
SJA1105
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 7 November 2016
29 of 34
SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
14. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate precautions are taken as
described in JESD625-A or equivalent standards.
15. Abbreviations
Table 10. Abbreviations
Abbreviation
AVB
Description
Audio Video Bridging
CMC
CRC
ECU
Gbit
Common Mode Choke
Cyclic Redundancy Check
Electronic Control Unit
Gigabit
IFG
InterFrame Gap
JTAG
LAN
Joint Test Action Group
Local Area Network
MAC
Mbit
Medium Access Controller
Megabit
MII
Media Independent Interface
N-channel Metal-Oxide Silicon
One-Time Programmable
Physical Layer (of the interface)
Phase-Locked Loop
NMOS
OTP
PHY
PLL
PMOS
PRBS
PTP
P-channel Metal-Oxide Silicon
Pseudo Random Binary Sequence
Precision Time Protocol
Quality of Service
QoS
RGMII
RMII
RSTP
SMI
Reduced Gigabit Media Independent Interface
Reduced Media Independent Interface
Rapid Spanning Tree Protocol
Serial Management Interface
Start Of Frame
SOF
SPI
Serial Peripheral Interface
Stream Reservation (class)
Spanning Tree Protocol
Test Access Port
SR
STP
TAP
TSN
Time-Sensitive Networking
Time-Triggered Ethernet
Unshielded Twisted Pair
Virtual Link
TTEthernet
UTP
VL
VLAN
Virtual LAN
SJA1105
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 7 November 2016
30 of 34
SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
16. References
[1] OPEN Alliance BroadR-Reach Physical Layer Transceiver Specification for
Automotive Applications, V3.2, 24 June 2014
[2] TJA1100 OPEN Alliance BroadR-Reach PHY for Automotive Ethernet data sheet
available from NXP Semiconductors
[3] IEEE 802.1BA - Audio Video Bridging (AVB) Systems
[4] Reduced Gigabit Media Independent Interface (RGMII), V1.3, 12 October
2000, V1.3, Broadcom Corporation, Hewlett Packard, Marvell
[5] IEEE Std. 802.3
[6] Reduced Media Independent Interface (RMII), March 20, 1998, RMII Consortium
Copyright AMD Inc., Broadcom Corp., National Semiconductor Corp., and Texas
Instruments Inc., 1997
[7] SPI Block Guide, V03.06, 04 February 2003, Motorola Inc.
[8] UM10851 SJA1105EL and UM10944 SJA1105TEL software user manuals available
from NXP Semiconductors
17. Revision history
Table 11. Revision history
Document ID
Release date
20161107
Data sheet status
Change notice
Supersedes
SJA1105 v.1.1
Product data sheet
-
-
SJA1105
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 7 November 2016
31 of 34
SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use in automotive applications — This NXP
18.2 Definitions
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
SJA1105
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 7 November 2016
32 of 34
SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
SJA1105
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 7 November 2016
33 of 34
SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
20. Contents
1
General description. . . . . . . . . . . . . . . . . . . . . . 1
7
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 15
Thermal characteristics . . . . . . . . . . . . . . . . . 15
Static characteristics . . . . . . . . . . . . . . . . . . . 16
Dynamic characteristics. . . . . . . . . . . . . . . . . 19
Application information . . . . . . . . . . . . . . . . . 24
Application hints. . . . . . . . . . . . . . . . . . . . . . . 27
Test information . . . . . . . . . . . . . . . . . . . . . . . 28
Quality information. . . . . . . . . . . . . . . . . . . . . 28
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 29
Handling information . . . . . . . . . . . . . . . . . . . 30
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 30
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Revision history . . . . . . . . . . . . . . . . . . . . . . . 31
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
General features. . . . . . . . . . . . . . . . . . . . . . . . 1
Ethernet switching and AVB features . . . . . . . . 1
TT and TSN features (SJA1105TEL only) . . . . 2
Interface features . . . . . . . . . . . . . . . . . . . . . . . 2
Other features. . . . . . . . . . . . . . . . . . . . . . . . . . 2
8
2.1
2.2
2.3
2.4
2.5
9
10
11
11.1
12
12.1
13
14
15
16
17
3
4
Ordering information. . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
6
6.1
Functional description . . . . . . . . . . . . . . . . . . . 8
Functional overview . . . . . . . . . . . . . . . . . . . . . 8
Auxiliary Configuration Unit (ACU) . . . . . . . . . . 8
Clock Generation Unit (CGU). . . . . . . . . . . . . . 8
Reset Generation Unit (RGU). . . . . . . . . . . . . . 8
Serial Peripheral Interface (SPI). . . . . . . . . . . . 9
Status and Control Unit (SCU) . . . . . . . . . . . . . 9
Configuration Stream Decoder/Configuration
Controller (CSD/CC). . . . . . . . . . . . . . . . . . . . . 9
xMII. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Dynamic Memory Management (DMM)/Frame
Memory Controller (FMC)/ Frame Buffer
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
18
Legal information . . . . . . . . . . . . . . . . . . . . . . 32
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 32
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 33
18.1
18.2
18.3
18.4
19
20
Contact information . . . . . . . . . . . . . . . . . . . . 33
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.1.7
6.1.8
Management (FBM) . . . . . . . . . . . . . . . . . . . . . 9
Receive MAC (RXM) . . . . . . . . . . . . . . . . . . . . 9
Input Queue (IQ). . . . . . . . . . . . . . . . . . . . . . . . 9
VLAN Lookup (VLAN_LU) . . . . . . . . . . . . . . . . 9
Address Lookup (L2ADDR_LU) . . . . . . . . . . . . 9
Policing (L2_POLICE) . . . . . . . . . . . . . . . . . . 10
Forwarding (L2_FORW) . . . . . . . . . . . . . . . . . 10
Transmit MAC (TXM) . . . . . . . . . . . . . . . . . . . 10
Audio Video Bridging (AVB) . . . . . . . . . . . . . . 10
Loopback Port (LBP) . . . . . . . . . . . . . . . . . . . 10
Virtual Link Lookup (VL_LU);
6.1.9
6.1.10
6.1.11
6.1.12
6.1.13
6.1.14
6.1.15
6.1.16
6.1.17
6.1.18
SJA1105TEL only . . . . . . . . . . . . . . . . . . . . . . 10
Virtual Link Policing (VL_POLICE);
SJA1105TEL only . . . . . . . . . . . . . . . . . . . . . . 10
Virtual Link Forwarding (VL_FORW);
SJA1105TEL only . . . . . . . . . . . . . . . . . . . . . . 11
Clock Synchronization Subsystem (CSS) and
Schedule Engine (SCH); SJA1105TEL only. . 11
Media Independent Interfaces (xMII) . . . . . . . 11
MII signaling and encoding. . . . . . . . . . . . . . . 12
RMII signaling and encoding . . . . . . . . . . . . . 12
RGMII signaling and encoding . . . . . . . . . . . . 13
SPI interface. . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1.19
6.1.20
6.1.21
6.2
6.2.1
6.2.2
6.2.3
6.3
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2016.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 7 November 2016
Document identifier: SJA1105
相关型号：
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