SJA2020HL/623_技术文档

SJA2020

ARM7 microcontroller with CAN and LIN controllers

Rev. 02 — 24 November 2006

Product data sheet

1. Introduction

1.1 About this document

This document lists detailed information about the SJA2020 device. It focuses on factual

information like pin information, register views, characteristics etc. Short descriptions are

used to outline the concept of the features and functions. More details and background on

developing applications for this device is given in the SJA2020 User manual (see Ref. 1).

No explicit references are made to the User manual.

Please refer to the SJA2020 Application note ‘Known issues’ (see Ref. 2) for corrections

and additional product information.

1.2 Intended audience

This document is written for engineers evaluating and/or developing systems, hard- and/or

software for the SJA2020. Some basic knowledge of ARM processors and architecture

and ARM7 in particular is assumed (see Ref. 3).

2. General description

2.1 Architectural overview

The SJA2020 consists of an ARM7TDMI-S processor with real-time emulation support,

the AMBA Advanced High-performance Bus (AHB) for interface to the on-chip memory

controllers, a DTL bus (a universal Philips interface) for interface to the interrupt controller

and three VLSI Peripheral Buses (VPB - a compatible superset of ARMs AMBA advanced

peripheral bus) for connection to the on-chip peripherals clustered in so-called

subsystems. The SJA2020 conﬁgures the ARM7TDMI-S processor in little endian byte

order. All peripherals run on the same system clock frequency as the ARM7TDMI-S

processor to minimize the access latency time. The AHB2VPB bridge used in the

subsystems contain a write-ahead buffer of 1 deep. This implies that when the ARM7

writes to a register located at the VPB side of the bridge, it will continue even though the

actual write may not yet have taken place. Completion of a second write to the same

subsystem will not be executed until the ﬁrst write is ﬁnished.

2.2 ARM7TDMI-S processor

The ARM7TDMI-S is a general purpose 32-bit processor, which offers high performance

and very low power consumption. The ARM architecture is based on Reduced Instruction

Set Computer (RISC) principles, and the instruction set and related decode mechanism

are much simpler than those of microprogrammed Complex Instruction Set Computers

(CISC). This simplicity results in a high instruction throughput and impressive real-time

interrupt response from a small and cost-effective controller core.

SJA2020

NXP Semiconductors

ARM7 microcontroller with CAN and LIN controllers

Pipeline techniques are employed so that all parts of the processing and memory systems

can operate continuously. Typically, while one instruction is being executed, its successor

is being decoded, and a third instruction is being fetched from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known as

Thumb, which makes it ideally suited to high-volume applications with memory

restrictions, or applications where code density is an issue.

The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the

ARM7TDMI-S processor has two instruction sets:

• Standard 32-bit ARM set

• 16-bit Thumb set

The Thumb set's 16-bit instruction length allows it to approach twice the density of

standard ARM code while retaining most of the ARM's performance advantage over a

traditional 16-bit controller using 16-bit registers. This is possible because Thumb code

operates on the same 32-bit register set as ARM code.

Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the

performance of an equivalent ARM controller connected to a 16-bit memory system.

The ARM7TDMI-S processor is described in detail in the ARM7TDMI-S data sheet (see

Ref. 3).

2.3 On-chip ﬂash memory system

The SJA2020 includes up to 384 kB ﬂash memory system. This memory may be used for

both code and data storage. Programming of the ﬂash memory may be accomplished in

several ways. It may be programmed in-system via a serial port, like e.g. CAN. The

application program may also erase and/or program the ﬂash while the application is

running, allowing a great degree of ﬂexibility for data storage ﬁeld upgrades.

2.4 On-chip static RAM

The SJA2020 includes a 24 kB static RAM memory that may be used for code and/or data

storage.

3. Features

3.1 General

I ARM7TDMI-S processor at 60 MHz maximum

I Up to 384 kB on-chip ﬂash program memory

I 24 kB static RAM

I One 550 UART with 16 bytes TX and RX FIFO depths

I Three full-duplex SPIs with 16 bits wide, 8 locations deep TX FIFO and RX FIFO

I Four 32-bit timers containing each four capture and compare registers linked to I/Os

I 10-bit, 400 ksample/s, 4-channel ADC with external trigger start option

I Real time clock with on-chip 32 kHz crystal oscillator and (battery) supply

I 32-bit watchdog with timer change protection

SJA2020_2

Product data sheet

Rev. 02 — 24 November 2006

2 of 176

SJA2020

NXP Semiconductors

ARM7 microcontroller with CAN and LIN controllers

I 94 general purpose I/O pins with programmable pull-up

I Vectored interrupt controller with 16 priority levels

I External 8-bit, 16-bit or 32-bit bus with four memory banks

I Standard ARM test and debug interface with real-time in-circuit emulator

I Dual power supply:

N CPU operating voltage: 1.8 V ± 5 %

N I/O operating voltage: 3.3 V

N 5 V tolerant port pins (without pull-up)

I Conﬁgurable system power management

I Twelve level sensitive external interrupt pins

I Processor wake-up from power down via external interrupt pins, CAN or LIN activity

I On-chip low power ring-oscillator with operating range from 25 kHz to 1 MHz

I On-chip crystal oscillator with operating range from 10 MHz to 20 MHz

I On-chip PLL allows CPU operation up to maximum CPU rate of 60 MHz

I Automotive product qualiﬁcation according AEC-Q100 Rev-F:

N Temperature grade 2 compliant; ambient operating temperature from

−40 °C to +105 °C

I Boundary scan test supported

I Small 144-pin LQFP package

3.2 Flash memory

I 384 kB ﬂash consisting of 48 sectors of 8 kB

I Supporting in-system and in-application programming

I Fast programming capability at 4 Mbit/s

I Provisions against over-burning and over-erasing

I Source code protection

3.3 CAN gateway

I Six CAN controllers

I Full CAN mode for message reception

I Triple transmit buffers with automatic priority scheduling

I Extensive global CAN acceptance ﬁlter for high performance gateway functionality

3.4 LIN master controller

I Four dedicated LIN master controllers

I Four standard 450 UARTs with LIN enhancement for LIN slaves or general purposes

4. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

SJA2020HL/623

LQFP144 plastic low proﬁle quad ﬂat package; 144 leads;

SOT486-1

body 20 × 20 × 1.4 mm

SJA2020_2

Product data sheet

Rev. 02 — 24 November 2006

3 of 176

SJA2020

NXP Semiconductors

ARM7 microcontroller with CAN and LIN controllers

5. Block diagram

ARM7TDMI-S

JTAGSEL

TRST_N

TMS

AHB WRAPPER

1149.1 JTAG TEST and

DEBUG INTERFACE

AHB DECODER

TCK

TDI

CS0 to CS3

WE_N

RTCK

TDO

OE_N

EXTERNAL MEMORY

CONTROLLER

FLASH CONTROLLER

BLS0 to BLS3

D[0:31]

384 kB EMBEDDED FLASH

MEMORY

A[0:23]

AHB2VPB BRIDGE

GENERAL SUBSYSTEM

STATIC RAM CONTROLLER

24 kB EMBEDDED SRAM

MEMORY

10-BIT ADC

V

DD(ADC)

AHB2DTL ADAPTER

ADC INTERFACE

VREFN

AI0 to AI3

VECTORED INTERRUPT

CONTROLLER

SCS0 to SCS2

SCK0 to SCK2

SDI0 to SCI2

SPI 0, 1, 2

AHB2VPB BRIDGE

PERIPHERAL SUBSYSTEM

SDO0 to SDO2

SYSTEM CONTROL UNIT

WATCHDOG TIMER

EVENT ROUTER

CAP0[0] to CAP3[3]

MAT0[0] to MAT3[3]

CAPTURE and COMPARE

TIMER 0, 1, 2, 3

EI0 to EI3

P0[0:31]

P1[0:31]

P2[0:29]

RXDC0 to RXDC5

RXDL0 to RXDL3

GENERAL PURPOSE

I/O 0, 1, 2

V

DD(RTC)

SS(RTC)

REAL TIME CLOCK

TXD

RXD

550 UART

XIN_RTC

32 kHz OSCILLATOR

POWER-ON RESET

XOUT_RTC

AHB2VPB BRIDGE

IVN SUBSYSTEM

V

SS(PLL)

TXDC0 to TXDC5

RXDC0 to RXDC5

CLOCK GENERATION UNIT

CAN CONTROLLER

0, 1, 2, 3, 4, 5

DD(OSC_PLL)

SS(OSC)

LOW POWER RING OSCILLATOR

10 MHz to 20 MHz OSCILLATOR

XIN_OSC

GLOBAL ACCEPTANCE

FILTER

XOUT_OSC

RESET_N

LOW POWER PLL

POWER-ON RESET

SJA2020

2 kB STATIC RAM

TXDL0 to TXDL3

RXDL0 to RXDL3

LIN MASTER

CONTROLLER 0, 1, 2, 3

V

DD(CORE)

CORE SUPPLY 1.8 V

V

SS(CORE)

DD(IO)

450 UART 0, 1, 2, 3

I/O PINS SUPPLY 3.3 V

001aaa165

V

SS(IO)

Fig 1. Block diagram

SJA2020_2

Product data sheet

Rev. 02 — 24 November 2006

4 of 176

SJA2020

NXP Semiconductors

ARM7 microcontroller with CAN and LIN controllers

6. Pinning information

6.1 Pinning

1

108

SJA2020HL

36

73

001aac517

Fig 2. Pin conﬁguration for SOT486-1

6.2 Pin description

Table 2.

Symbol

LQFP144 pin assignment

Description

Default function Function 1

Function 2

Function 3

JTAGSEL

1

TAP controller select input; LOW level selects ARM debug mode and HIGH

level selects boundary scan and ﬂash programming; pulled-up internally

RESET_N

V_SS(RTC)

2

external reset input; pulled-up internally (active LOW)

real time clock oscillator ground

real time clock crystal output

3

XOUT_RTC

XIN_RTC

4

5

real time clock crystal input or external clock input

real time clock oscillator supply voltage

oscillator ground

V_DD(RTC)

6

V_SS(OSC)

7

XOUT_OSC

XIN_OSC

V_{DD(OSC_PLL)}

V_SS(PLL)

8

oscillator crystal output

9

oscillator crystal input or external clock input

oscillator and PLL supply voltage

PLL ground

10

11

12

13

14

15

16

17

18

19

20

21

P0[31]/SDO0

P0[30]/SDI0

P0[29]/SCK0

P0[28]/SCS0

V_SS(IO)

GPIO 0; pin 31

GPIO 0; pin 30

GPIO 0; pin 29

GPIO 0; pin 28

I/O pins ground

GPIO 0; pin 27

GPIO 0; pin 31

GPIO 0; pin 30

GPIO 0; pin 29

GPIO 0; pin 28

SPI0 SDO

SPI0 SDI

SPI0 SCK

SPI0 SCS

SPI0 SDO

SPI0 SDI

SPI0 SCK

SPI0 SCS

P0[27]/SDO1

V_DD(CORE)

V_SS(CORE)

GPIO 0; pin 27

SPI1 SDO

core supply voltage 1.8 V

digital core ground

P0[26]/SDI1

P0[25]/SCK1

GPIO 0; pin 26

GPIO 0; pin 25

GPIO 0; pin 26

GPIO 0; pin 25

SPI1 SDI

SPI1 SCK

SPI1 SDI

SPI1 SCK

SJA2020_2

Product data sheet

Rev. 02 — 24 November 2006

5 of 176

SJA2020

NXP Semiconductors

ARM7 microcontroller with CAN and LIN controllers

Table 2.

Symbol

LQFP144 pin assignment …continued

Description

Default function Function 1

GPIO 0; pin 24 GPIO 0; pin 24

I/O pins supply voltage 3.3 V

Function 2

Function 3

P0[24]/SCS1

V_DD(IO)

22

23

24

25

26

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

SPI1 SCS

P0[23]/SDO2/A[23]

P0[22]/SDI2/A[22]

P0[21]/SCK2/A[21]

P0[20]/SCS2/A[20]

V_SS(IO)

GPIO 0; pin 23

GPIO 0; pin 22

GPIO 0; pin 21

GPIO 0; pin 20

I/O pins ground

GPIO 0; pin 19

GPIO 0; pin 18

GPIO 0; pin 17

GPIO 0; pin 16

SPI2 SDO

SPI2 SDI

SPI2 SCK

SPI2 SCS

EXT BUS A23

EXT BUS A22

EXT BUS A21

EXT BUS A20

EXT BUS A23

EXT BUS A22

EXT BUS A21

EXT BUS A20

P0[19]/A[19]

P0[18]/A[18]

P0[17]/A[17]

P0[16]/A[16]

V_DD(IO)

GPIO 0; pin 19

GPIO 0; pin 18

GPIO 0; pin 17

GPIO 0; pin 16

EXT BUS A19

EXT BUS A18

EXT BUS A17

EXT BUS A16

EXT BUS A19

EXT BUS A18

EXT BUS A17

EXT BUS A16

I/O pins supply voltage 3.3 V

P0[15]/A[15]

P0[14]/A[14]

TDI

GPIO 0; pin 15

GPIO 0; pin 14

GPIO 0; pin 15

GPIO 0; pin 14

EXT BUS A15

EXT BUS A14

EXT BUS A15

EXT BUS A14

test data input; pulled-up internally

test data output

TDO

P0[13]/A[13]

P0[12]/A[12]

V_SS(IO)

GPIO 0; pin 13

GPIO 0; pin 12

I/O pins ground

GPIO 0; pin 11

GPIO 0; pin 10

GPIO 0; pin 9

GPIO 0; pin 8

GPIO 0; pin 13

GPIO 0; pin 12

EXT BUS A13

EXT BUS A12

EXT BUS A13

EXT BUS A12

P0[11]/A[11]

P0[10]/A[10]

P0[9]/A[9]

GPIO 0; pin 11

GPIO 0; pin 10

GPIO 0; pin 9

GPIO 0; pin 8

EXT BUS A11

EXT BUS A10

EXT BUS A9

EXT BUS A8

EXT BUS A11

EXT BUS A10

EXT BUS A9

EXT BUS A8

P0[8]/A[8]

V_DD(IO)

I/O pins supply voltage 3.3 V

P0[7]/A[7]

GPIO 0; pin 7

GPIO 0; pin 6

GPIO 0; pin 5

GPIO 0; pin 4

I/O pins ground

GPIO 0; pin 3

GPIO 0; pin 2

GPIO 0; pin 1

digital core ground

GPIO 0; pin 7

EXT BUS A7

EXT BUS A6

EXT BUS A5

EXT BUS A4

EXT BUS A7

EXT BUS A6

EXT BUS A5

EXT BUS A4

P0[6]/A[6]

GPIO 0; pin 6

GPIO 0; pin 5

GPIO 0; pin 4

P0[5]/A[5]

P0[4]/A[4]

V_SS(IO)

P0[3]/A[3]

GPIO 0; pin 3

GPIO 0; pin 2

GPIO 0; pin 1

EXT BUS A3

EXT BUS A2

EXT BUS A1

EXT BUS A3

EXT BUS A2

EXT BUS A1

P0[2]/A[2]

P0[1]/A[1]

V_SS(CORE)

V_DD(CORE)

core supply voltage 1.8 V

P0[0]/A[0]

GPIO 0; pin 0

EXT BUS A0

V_DD(IO)

I/O pins supply voltage 3.3 V

P2[29]/CS0

P2[28]/CS1

P2[27]/EI3/CS2

P2[26]/EI2/CS3

GPIO 2; pin 29

GPIO 2; pin 28

GPIO 2; pin 27

GPIO 2; pin 26

GPIO 2; pin 29

EXT BUS CS0

EXT BUS CS1

EXT BUS CS2

EXT BUS CS3

EXT BUS CS0

EXT BUS CS1

EXT BUS CS2

EXT BUS CS3

GPIO 2; pin 28

EXTINT3

EXTINT2

SJA2020_2

Product data sheet

Rev. 02 — 24 November 2006

6 of 176

SJA2020

NXP Semiconductors

ARM7 microcontroller with CAN and LIN controllers

Table 2.

Symbol

LQFP144 pin assignment …continued

Description

Default function Function 1

Function 2

EXTINT1

Function 3

EXTINT1

P2[25]/EI1

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

GPIO 2; pin 25

GPIO 2; pin 24

GPIO 2; pin 23

GPIO 2; pin 22

GPIO 2; pin 25

GPIO 2; pin 24

GPIO 2; pin 23

GPIO 2; pin 22

P2[24]/EI0

EXTINT0

P2[23]/CAP1[0]/MAT1[0]

P2[22]/CAP2[0]/MAT2[0]

V_DD(ADC)

TIMER1 CAP0

TIMER2 CAP0

TIMER1 MAT0

TIMER2 MAT0

ADC supply voltage and high reference level

ADC low reference level

VREFN

AI3

analog input for channel 3 and channel 7

analog input for channel 2 and channel 6

analog input for channel 1 and channel 5

analog input for channel 0 and channel 4

test reset input; pulled-up internally (active LOW)

I/O pins ground

AI2

AI1

AI0

TRST_N

V_SS(IO)

P2[21]/RXDL0

P2[20]/TXDL0

P2[19]/RXD/RXDL1

P2[18]/TXD/TXDL1

P2[17]/RXDL2/RXDC5

P2[16]/TXDL2/TXDC5

P2[15]/RXDL3/RXDC4

P2[14]/TXDL3/TXDC4

V_DD(IO)

GPIO 2; pin 21

GPIO 2; pin 20

GPIO 2; pin 19

GPIO 2; pin 18

GPIO 2; pin 17

GPIO 2; pin 16

GPIO 2; pin 15

GPIO 2; pin 14

GPIO 2; pin 21

GPIO 2; pin 20

UART RXD

UART TXD

LIN2 RXDL

LIN2 TXDL

LIN3 RXDL

LIN3 TXDL

LIN0 RXDL

LIN0 TXDL

LIN1 RXDL

LIN1 TXDL

CAN5 RXDC

CAN5 TXDC

CAN4 RXDC

CAN4 TXDC

LIN0 RXDL

LIN0 TXDL

LIN1 RXDL

LIN1 TXDL

CAN5 RXDC

CAN5 TXDC

CAN4 RXDC

CAN4 TXDC

I/O pins supply voltage 3.3 V

P2[13]/RXDC3

P2[12]/TXDC3

P2[11]/RXDC2

P2[10]/TXDC2

P2[9]/RXDC1

P2[8]/TXDC1

P2[7]/RXDC0

V_SS(CORE)

GPIO 2; pin 13

GPIO 2; pin 12

GPIO 2; pin 11

GPIO 2; pin 10

GPIO 2; pin 9

GPIO 2; pin 8

GPIO 2; pin 7

digital core ground

GPIO 2; pin 13

CAN3 RXDC

CAN3 TXDC

CAN2 RXDC

CAN2 TXDC

CAN1 RXDC

CAN1 TXDC

CAN0 RXDC

CAN3 RXDC

CAN3 TXDC

CAN2 RXDC

CAN2 TXDC

CAN1 RXDC

CAN1 TXDC

CAN0 RXDC

GPIO 2; pin 12

GPIO 2; pin 11

GPIO 2; pin 10

GPIO 2; pin 9

GPIO 2; pin 8

GPIO 2; pin 7

V_DD(CORE)

core supply voltage 1.8 V

P2[6]/TXDC0

V_SS(IO)

GPIO 2; pin 6

I/O pins ground

GPIO 2; pin 5

GPIO 2; pin 4

GPIO 2; pin 3

GPIO 2; pin 2

GPIO 2; pin 1

GPIO 2; pin 0

GPIO 2; pin 6

CAN0 TXDC

P2[5]/BLS3

GPIO 2; pin 5

GPIO 2; pin 4

GPIO 2; pin 3

GPIO 2; pin 2

GPIO 2; pin 1

GPIO 2; pin 0

EXT BUS BLS3

EXT BUS BLS2

EXT BUS BLS1

EXT BUS BLS0

EXT BUS WEN

EXT BUS OEN

EXT BUS BLS3

EXT BUS BLS2

EXT BUS BLS1

EXT BUS BLS0

EXT BUS WEN

EXT BUS OEN

P2[4]/BLS2

P2[3]/BLS1

P2[2]/BLS0

P2[1]/WE_N

P2[0]/OE_N

V_DD(IO)

I/O pins supply voltage 3.3 V

GPIO 1; pin 0 GPIO 1; pin 0

P1[0]/D[0]

EXT BUS D0

SJA2020_2

Product data sheet

Rev. 02 — 24 November 2006

7 of 176

SJA2020

NXP Semiconductors

ARM7 microcontroller with CAN and LIN controllers

Table 2.

Symbol

LQFP144 pin assignment …continued

Description

Default function Function 1

Function 2

Function 3

P1[1]/D[1]

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

GPIO 1; pin 1

GPIO 1; pin 2

GPIO 1; pin 3

I/O pins ground

GPIO 1; pin 4

GPIO 1; pin 5

GPIO 1; pin 1

GPIO 1; pin 2

GPIO 1; pin 3

EXT BUS D1

EXT BUS D2

EXT BUS D3

EXT BUS D1

EXT BUS D2

EXT BUS D3

P1[2]/D[2]

P1[3]/D[3]

V_SS(IO)

P1[4]/D[4]

GPIO 1; pin 4

GPIO 1; pin 5

EXT BUS D4

EXT BUS D5

EXT BUS D4

EXT BUS D5

P1[5]/D[5]

TMS

test mode select input; pulled-up internally

test clock input

TCK

P1[6]/D[6]

GPIO 1; pin 6

GPIO 1; pin 7

GPIO 1; pin 6

GPIO 1; pin 7

EXT BUS D6

EXT BUS D7

EXT BUS D6

EXT BUS D7

P1[7]/D[7]

V_DD(IO)

I/O pins supply voltage 3.3 V

P1[8]/D[8]

GPIO 1; pin 8

GPIO 1; pin 9

GPIO 1; pin 10

GPIO 1; pin 11

I/O pins ground

GPIO 1; pin 12

GPIO 1; pin 13

GPIO 1; pin 14

GPIO 1; pin 15

GPIO 1; pin 8

EXT BUS D8

EXT BUS D9

EXT BUS D10

EXT BUS D11

EXT BUS D8

EXT BUS D9

EXT BUS D10

EXT BUS D11

P1[9]/D[9]

GPIO 1; pin 9

GPIO 1; pin 10

GPIO 1; pin 11

P1[10]/D[10]

P1[11]/D[11]

V_SS(IO)

P1[12]/D[12]

GPIO 1; pin 12

GPIO 1; pin 13

GPIO 1; pin 14

GPIO 1; pin 15

EXT BUS D12

EXT BUS D13

EXT BUS D14

EXT BUS D15

EXT BUS D12

EXT BUS D13

EXT BUS D14

EXT BUS D15

P1[13]/D[13]

P1[14]/D[14]

P1[15]/D[15]

V_DD(IO)

I/O pins supply voltage 3.3 V

P1[16]/CAP3[3]/D[16]/MAT3[3]

P1[17]/CAP3[2]/D[17]/MAT3[2]

P1[18]/CAP3[1]/D[18]/MAT3[1]

V_DD(CORE)

GPIO 1; pin 16

GPIO 1; pin 17

GPIO 1; pin 18

TIMER3 CAP3

EXT BUS D16

EXT BUS D17

EXT BUS D18

TIMER3 MAT3

TIMER3 MAT2

TIMER3 MAT1

TIMER3 CAP2

TIMER3 CAP1

core supply voltage 1.8 V

digital core ground

V_SS(CORE)

P1[19]/CAP3[0]/D[19]/MAT3[0]

V_SS(IO)

GPIO 1; pin 19

I/O pins ground

GPIO 1; pin 20

GPIO 1; pin 21

GPIO 1; pin 22

GPIO 1; pin 23

TIMER3 CAP0

EXT BUS D19

TIMER3 MAT0

P1[20]/CAP2[3]/D[20]/MAT2[3]

P1[21]/CAP2[2]/D[21]/MAT2[2]

P1[22]/CAP2[1]/D[22]/MAT2[1]

P1[23]/CAP1[3]/D[23]/MAT1[3]

V_DD(IO)

TIMER2 CAP3

TIMER2 CAP2

TIMER2 CAP1

TIMER1 CAP3

EXT BUS D20

EXT BUS D21

EXT BUS D22

EXT BUS D23

TIMER2 MAT3

TIMER2 MAT2

TIMER2 MAT1

TIMER1 MAT3

I/O pins supply voltage 3.3 V

P1[24]/CAP1[2]/D[24]/MAT1[2]

P1[25]/CAP1[1]/D[25]/MAT1[1]

P1[26]/CAP0[3]/D[26]/MAT0[3]

P1[27]/CAP0[2]/D[27]/MAT0[2]

V_SS(IO)

GPIO 1; pin 24

GPIO 1; pin 25

GPIO 1; pin 26

GPIO 1; pin 27

I/O pins ground

GPIO 1; pin 28

GPIO 1; pin 29

TIMER1 CAP2

EXT BUS D24

EXT BUS D25

EXT BUS D26

EXT BUS D27

TIMER1 MAT2

TIMER1 MAT1

TIMER0 MAT3

TIMER0 MAT2

TIMER1 CAP1

TIMER0 CAP3

TIMER0 CAP2

P1[28]/CAP0[1]/D[28]/MAT0[1]

P1[29]/CAP0[0]/D[29]/MAT0[0]

TIMER0 CAP1

TIMER0 CAP0

EXT BUS D28

EXT BUS D29

TIMER0 MAT1

TIMER0 MAT0

SJA2020_2

Product data sheet

Rev. 02 — 24 November 2006

8 of 176

SJA2020

NXP Semiconductors

ARM7 microcontroller with CAN and LIN controllers

Table 2.

Symbol

LQFP144 pin assignment …continued

Description

Default function Function 1

Function 2

Function 3

P1[30]/RTCK/D[30]

P1[31]/D[31]

V_DD(IO)

142

143

144

GPIO 1; pin 30

GPIO 1; pin 31

RTCK

EXT BUS D30

EXT BUS D31

EXT BUS D30

EXT BUS D31

GPIO 1; pin 31

I/O pins supply voltage 3.3 V

7. Functional description

7.1 Reset and power-up behavior

The SJA2020 contains an external reset input and an internal power-up reset circuitry.

This circuitry ensures a reset is internally extended until oscillators, PLL and Flash have

reached a stable state. See Section 12 for characteristics of the several start-up and

initialization times. Table 3 shows the reset pin.

Table 3.

Symbol

Reset pin

Direction

Description

RESET_N IN

external reset input, active LOW; pulled-up internally

7.2 JTAG interface and debug pins

The SJA2020 contains boundary scan test logic according to IEEE 1149.1, in this

document further referred to as ‘JTAG’. The JTAG pins can be used to connect a

debugger probe for the embedded ARM processor. Pin JTAGSEL selects between the

boundary scan mode and debug mode. See User manual for more information (see

Ref. 1). Table 4 shows the JTAG pins.

Table 4.

JTAG and debug interface

Symbol Direction Description

JTAGSEL IN

TAP controller select input; LOW level selects ARM debug mode and

HIGH level selects boundary scan and ﬂash programming; pulled-up

internally

TRST_N IN

test reset input; pulled-up internally (active LOW)

test mode select input; pulled-up internally

test data input, pulled-up internally

test data output

TMS

TDI

IN

TDO

TCK

RTCK

OUT

IN

test clock input

OUT

synchronized ARM debug return clock output (multiplexed with other

functions on a device pin, see Section 6)

7.3 Power supply pins description

Table 5 shows the power supply pins. See User manual (see Ref. 1) for more information

on physical constraints and board design issues.

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Table 5.

Power supplies

Description

Symbol

V_DD(CORE)

V_SS(CORE)

V_DD(IO)

core supply voltage 1.8 V

core ground

I/O supply voltage 3.3 V

I/O ground

V_SS(IO)

V_{DD(OSC_PLL)}

V_SS(OSC)

V_DD(RTC)

V_SS(RTC)

V_DD(ADC)

V_SS(PLL)

oscillator and PLL supply voltage 1.8 V

oscillator ground

real time clock oscillator supply voltage 1.8 V

real time clock oscillator ground

ADC supply voltage 3.3 V

PLL ground

7.4 Clock architecture

As can be seen in Figure 3, the SJA2020 is partitioned into so called subsystems or

blocks. The subsystems concept allows the several functional parts to be conﬁgured

individually with respect to the power mode that is used in each of them. Subsystems and

or blocks are grouped into ‘clock-domains’. In this way clocks can be switched on or off

and the response to sleep/wake-up events can be set per clock domain. In Section 8.3.1

these features are described in more detail.

Figure 3 gives a simpliﬁed view of how the SJA2020 is split into several ‘clock-domains’.

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EMBEDDED

FLASH MEMORY

up to 384 kB

ARM7TDMI-S

0

FLASH CONTROLLER

1

EXTERNAL

MEMORY

CONTROLLER

IN-VEHICLE NETWORKING

SUBSYSTEM

EMBEDDED

SRAM MEMORY

24 kB

CAN

3

SRAM CONTROLLER

LIN

2

GENERAL

SUBSYSTEM

PERIPHERAL

SUBSYSTEM

SPI

SCU

VIC

TIMERS

GPIO

WATCHDOG TIMER

EVENT ROUTER

ADC

RTC

UART

CLOCK GENERATION UNIT

001aac565

Fig 3. Clock domains in the SJA2020

7.5 Memory maps

ARM7 processors have 4 GB address space. The SJA2020 has divided this memory

space into 8 regions of 512 MB each. Each region is used for a dedicated purpose.

An exception to this is region 0; several of the other regions (or a part of it) can be

shadowed in the memory map at this region. This shadowing can be controlled by

software via the programmable re-mapping registers.

Figure 4 gives a graphical overview of the SJA2020 memory map.

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4 GB

FFFF FFFFh

REGION 7

BUS PERIPHERALS

E000 0000h

REGION 6

(not used)

C000 0000h

3 GB

REGION 5

EXTERNAL STATIC

MEMORY CONTROLLER

A000 0000h

REGION 4

(not used)

8000 0000h

2 GB

REGION 3

INTERNAL SRAM

Programmable selection

of shadowed region

via re-map registers

6000 0000h

4000 0000h

2000 0000h

0000 0000h

REGION 2

(not used)

1 GB

REGION 1

EMBEDDED FLASH

Embedded flash

region shadowed

after reset

REGION 0

SHADOW AREA

001aaa167

Fig 4. AHB system memory map graphical overview

7.5.1 Region 0: remap area

The ARM7TDMI-S processor has its exception vectors located at address logic 0. Since

ﬂash is the only non-volatile memory available in the SJA2020, the exception vectors in

the ﬂash must be located at address logic 0 after reset. Memory re-mapping from ﬂash to

SRAM is therefore introduced to improve performance.

To enable memory re-mapping, the SJA2020 AHB system memory map provides a

shadow area (region 0) starting at address logic 0. This is a virtual memory region, i.e. no

actual memory is present at the shadow area addresses. A selectable region of the AHB

system memory map is, apart from its own speciﬁc region, also accessible via this

shadow area region.

After reset, the region 1 embedded ﬂash area is always available at the shadow area.

After booting, any other region of the AHB system memory map (e.g. internal SRAM) can

be re-mapped to region 0 by means of the shadow memory mapping register. For more

details about the shadow area see Section 8.3.2.4.

7.5.2 Region 1: embedded ﬂash area

Figure 5 gives a graphical overview of the embedded ﬂash memory map.

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1FFF FFFFh

0040 0000h

0020 0FFFh

FLASH IF1

CONFIGURATION AREA (4 kB)

0020 0000h

0004 6000h

FLASH IF1

DATA TRANSFER AREA (384 kB)

0000 0000h

001aaa168

(offset address)

Address: 2000 0000h to 3FFF FFFFh.

Fig 5. Region 1 embedded ﬂash memory

Region 1 is reserved for the embedded ﬂash. For each embedded ﬂash instance a data

area of 2 MB (to be prepared for larger ﬂash memory instance) and a conﬁguration area of

4 kB are reserved. Although the SJA2020 contains only one embedded ﬂash instance, the

memory aperture per embedded ﬂash instance is deﬁned at 4 MB.

7.5.3 Region 2: not used

7.5.4 Region 3: internal SRAM area

Figure 6 gives a graphical overview of the internal SRAM memory map.

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1FFF FFFFh

INTERNAL SRAM INTERFACE 2 to n

(not used)

0008 0000h

INTERNAL SRAM INTERFACE 1

(reserved for increased data area)

0000 8000h

0000 6000h

INTERNAL SRAM INTERFACE 1

shadowed lower data area (8 kB)

INTERNAL SRAM INTERFACE 1

data transfer area (24 kB)

0000 0000h

001aaa169

(offset address)

Address: 6000 0000h to 7FFF FFFFh.

Fig 6. Region 3 internal SRAM memory

Region 3 is reserved for internal SRAM. For each internal SRAM instance a data area of

512 kB is reserved. Although the SJA2020 has only one internal SRAM instance, the

memory aperture per internal SRAM instance is deﬁned at 512 kB.

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7.5.5 Region 4: not used

7.5.6 Region 5: external static memory controller area

1FFF FFFFh

CONFIGURATION AREA (4 kB)

1FFF F000h

1000 0000h

MEMORY BANK 4 to 7

(not used)

SHADOW MEMORY BANK 3 (16 MB)

MEMORY BANK 3 (16 MB)

0D00 0000h

0C00 0000h

SHADOW MEMORY BANK 2 (16 MB)

MEMORY BANK 2 (16 MB)

0900 0000h

0800 0000h

SHADOW MEMORY BANK 1 (16 MB)

MEMORY BANK 1 (16 MB)

0500 0000h

0400 0000h

SHADOW MEMORY BANK 0 (16 MB)

MEMORY BANK 0 (16 MB)

0100 0000h

0000 0000h

001aaa170

(offset address)

Address: A000 0000h to BFFF FFFFh.

Fig 7. Region 5 external static memory controller

Figure 7 gives a graphical overview of the external static memory controller memory map.

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Region 5 is reserved for the external static memory controller. The SJA2020 provides I/O

pins for 4 bank select signals and 24 address lines. This implies that 4 memory banks of

16 MB each can be externally addressed. Due to the external static memory controller

hardware conﬁguration, each bank of 16 MB data area is mirrored four times in a 64 MB

region memory map.

The external static memory controller conﬁguration area is located on top of region 5.

7.5.7 Region 6: not used

7.5.8 Region 7: bus peripherals area

Figure 8 gives a graphical overview of the bus peripherals area memory map.

1FFF FFFFh

VECTORED

INTERRUPT CONTROLLER

1FFF 0000h

MMIO AREA

(not used)

VPB CLUSTER 5 to n

(not used)

000A 0000h

VPB CLUSTER 4

(ivn subsystem)

0008 0000h

VPB CLUSTER 3

(not used)

0006 0000h

VPB CLUSTER 2

(peripheral subsystem)

0004 0000h

VPB CLUSTER 1

(not used)

0002 0000h

VPB CLUSTER 0

(general subsystem)

0000 0000h

001aaa171

(offset address)

Address: E000 0000h to FFFF FFFFh.

Fig 8. Region 7 bus peripherals area memory

Region 7 is reserved for all ‘stand-alone’ memory mapped register interfaces. Examples

of such peripherals are DTL target modules connected to the AHB bus via AHB2DTL

adapters and VPB peripherals connected via AHB2VPB bridges.

The lower part of region 7 is again divided into VPB clusters. A VPB cluster is typically

used as the address space for a set of VPB peripherals connected to a single AHB2VPB

bridge, the slave on the AHB system bus. The clusters are aligned on 128 kB boundaries.

In the SJA2020 three VPB clusters are in use. The VPB peripherals are aligned on 4 kB

boundaries inside the VPB clusters.

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The upper part of region 7 is used as the memory area where memory mapped register

interfaces of ‘stand-alone’ AHB peripherals reside. Each of these peripherals will be a

slave on the AHB system bus. In the SJA2020 only one of such slave is present: the

interrupt controller. It is a DTL target connected to the AHB system bus via an AHB2DTL

adapter.

7.5.9 Memory map concepts operation

The basic concept on the SJA2020 is that each memory area has a ‘natural’ location in

the memory map. This is the address range for which code residing in that area is written.

Each memory space remains permanently ﬁxed in the same location, eliminating the need

to have portions of the code designed to run in different address ranges.

Because of the location of the interrupt vectors on the ARM7 processor (at addresses

0000 0000h through 0000 001Ch) (see Table 6), the embedded ﬂash, internal SRAM or

even external memories can be re-mapped to the shadow memory area in order to allow

alternative uses of interrupts in the different operating modes. After reset, the embedded

ﬂash is re-mapped into the shadow memory area by default.

The SJA2020 generates the appropriate bus cycle abort exception if an access is

attempted for an address that is in a reserved or not used address region and unassigned

peripheral spaces. For these areas, both attempted data access and instruction fetch

generate an exception. Note that write access address should be word aligned in ARM

code or halfword aligned in Thumb code. Byte aligned writes are performed as word or

halfword aligned writes without error signalling.

Within the address space of an existing peripheral, a data abort exception is not

generated in response to an access to an undeﬁned address. Address decoding within

each peripheral is limited to that needed to distinguish deﬁned registers within the

peripheral itself. Details of address aliasing within a peripheral space are not deﬁned in

the SJA2020 documentation and are not a supported feature.

Note that the ARM stores the prefetch abort ﬂag along with the associated instruction

(which will be meaningless) in the pipeline and processes the abort only if an attempt is

made to execute the instruction fetched from the illegal address. This prevents accidental

aborts that could be caused by prefetches that occur when code is executed very near a

memory boundary.

Table 7 gives the base address overview of all peripherals.

Table 6.

Interrupt vectors address table

Exception

Address

0000 0000h

0000 0004h

0000 0008h

reset

undeﬁned instruction

software interrupt

0000 000Ch

0000 0010h

0000 0014h

0000 0018h

0000 001Ch

prefetch abort (instruction fetch memory fault)

data abort (data access memory fault)

reserved

IRQ

FIQ

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Table 7.

Peripherals base address overview

Base address

Memory region 0 to 6

0000 0000h

Base name

AHB peripherals

shadow area memory

2000 0000h

embedded ﬂash memory

2020 0000h

FMC RegBase

SMC RegBase

embedded ﬂash controller

conﬁguration registers

6000 0000h

A000 0000h

BFFF F000h

internal SRAM memory

external static memory

external static memory controller

conﬁguration registers

VPB cluster 0: general subsystem

E000 0000h

E000 1000h

E000 2000h

E000 3000h

E000 4000h

E000 5000h

E000 6000h

E000 8000h

E000 A000h

CGU RegBase

clock generation unit

system control unit

SPI 0

SCU RegBase

SPI RegBase

ADC RegBase

WD RegBase

ER RegBase

RTC RegBase

SPI 1

SPI 2

ADC

watchdog

event router

real time clock

VPB cluster 2: peripheral subsystem

E004 0000h

E004 1000h

E004 2000h

E004 3000h

E004 4000h

E004 5000h

E004 6000h

E004 7000h

TIMER RegBase

timer 0

TIMER RegBase

UART RegBase

GPIO RegBase

timer 1

timer 2

timer 3

16C550 UART

general purpose I/O 0

general purpose I/O 1

general purpose I/O 2

VPB cluster 4: in-vehicle networking subsystem

E008 0000h

E008 1000h

E008 2000h

E008 3000h

E008 4000h

E008 5000h

E008 6000h

E008 7000h

E008 8000h

E008 9000h

E008 A000h

E008 B000h

CANC RegBase

CANAFM RegBase

CANAFR RegBase

CANCS RegBase

LIN RegBase

CAN controller 0

CAN controller 1

CAN controller 2

CAN controller 3

CAN controller 4

CAN controller 5

CAN ID-look-up table memory

CAN acceptance ﬁlter registers

CAN central status registers

LIN master controller 0

LIN master controller 1

LIN master controller 2

LIN RegBase

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Table 7.

Peripherals base address overview …continued

Base address

Base name

AHB peripherals

E008 C000h

LIN RegBase

LIN master controller 3

Vector interrupt controller

FFFF F000h

VIC RegBase

vectored interrupt controller

8. Block description

8.1 Flash memory controller

8.1.1 Overview

The Flash Memory Controller (FMC) interfaces to the embedded ﬂash memory with two

tasks:

• Providing memory data transfer

• Memory conﬁguration via triggering, programming and erasing

The ﬂash memory has a 128-bit wide data interface and the ﬂash controller offers two

128-bit buffer lines to improve the system performance. Initially, the ﬂash has to be

programmed via JTAG. In-system programming must be supported by the boot loader.

In-application programming is possible. The ﬂash memory contents can be protected by

disabling the JTAG access. Suspending of burning or erasing is not supported.

The key features are:

• Programming by CPU via AHB

• Programming by external programmer via JTAG

• JTAG access protection

• Burn-ﬁnished and erased-ﬁnished interrupt

After reset, the ﬂash initialization is started which takes t_inittime. During this initialization

ﬂash access is not possible and AHB transfers to the ﬂash are stalled, thus blocking the

AHB bus.

During the ﬂash initialization, the index sector is read to identify the status of the JTAG

access protection and sector security. In case the JTAG access protection is active, the

ﬂash is not accessible via JTAG anymore and the ARM debug facilities have been

disabled to protect the ﬂash memory contents against unwanted reading out externally. If

the sector security is active, the concerning sector is read only.

The ﬂash can be read synchronously or asynchronously to the system clock. In

synchronous operation, the ﬂash goes into standby after returning the read data. Started

reads cannot be stopped and therefore speculative reading and dual buffering is not

supported.

With asynchronous reading, the transfer of the address to the ﬂash, and read data from

the ﬂash are done asynchronously, yielding in the fastest possible response time. Started

reads can be stopped and therefore speculative reading and dual buffering is supported.

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Buffering is offered because the ﬂash has a 128-bit wide data interface, while the AHB

interface has only 32 bits. With buffering, a buffer line holds the complete 128 bits ﬂash

word, from which 4 words can be read. Without buffering, every AHB data port read starts

a ﬂash read. A ﬂash read is a slow process compared to the minimum AHB cycle time.

With buffering, the average read time is reduced which can improve the system

performance.

With single buffering, the most recently read ﬂash word stays available until the next ﬂash

read. When an AHB data port read transfer requires data from the same ﬂash word as the

previous read transfer, no new ﬂash read is done, and the read data is given without wait

cycles.

When an AHB data port read transfer requires data from a different ﬂash word as the

previous read transfer, a new ﬂash read is done, and wait states are given until the new

read data is available.

With dual buffering, a secondary buffer line is used. The output of the ﬂash is considered

as the primary buffer. On a primary buffer hit, data can be copied to the secondary buffer

line, which allows the ﬂash to start a speculative read of the next ﬂash word.

Both buffer lines are invalidated after:

• Initialization

• Conﬁguration register access

• Data latch reading

• Index sector reading

The modes of operation are listed in Table 8.

Table 8.

Flash read modes

Conﬁguration bit

FS_DCR FS_CACHEBYP CACHE2EN SPECALWAYS

Synchronous timing

Buffering

Characteristics and features

No buffer line

0

1

X

for single (non linear) reads, one ﬂash

word read per word read

Single buffer

line

0

X

default mode of operation; most recently

read ﬂash word is kept until another ﬂash

word is required

Asynchronous timing

No buffer line

1

0

X

one ﬂash word read per word read

Single buffer

line

most recently read ﬂash word is kept until

another ﬂash word is required

Dual buffer

line, single

speculative

1

0

1

0

on a buffer miss, a ﬂash read is done,

followed by at most one speculative read;

optimized for execution of code with small

loops (< 8 words) from ﬂash

Dual buffer

line, always

speculative

1

0

1

most recently used ﬂash word is copied

into second buffer line, next ﬂash word

read is started; highest performance for

linear reads

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8.1.2 Flash memory controller pin description

The ﬂash memory controller has no external pins.

8.1.3 Flash memory layout

The ARM processor can program the ﬂash for ISP and IAP. Note that the ﬂash always has

to be programmed by ﬂash words (of 128-bit).

The ﬂash memory is organized in equal sectors of 8 kB that must be erased before data

can be written into them. The ﬂash memory also has sector wise protection. Writing

occurs per page which consists of 4096 bits (32 ﬂash words). Thus a sector contains

16 pages.

Table 9 and Table 10 give an overview of the ﬂash sector and page addressing.

Table 9.

Flash sector overview

Sector number

Sector base address

0000 0000h

0000 2000h

0000 4000h

0000 6000h

0000 8000h

0000 A000h

0000 C000h

0000 E000h

0001 0000h

0001 2000h

0001 4000h

0001 6000h

0001 8000h

0001 A000h

0001 C000h

0001 E000h

0002 0000h

0002 2000h

0002 4000h

0002 6000h

0002 8000h

0002 A000h

0002 C000h

0002 E000h

0003 0000h

0003 2000h

0003 4000h

0003 6000h

0003 8000h

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

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Table 9.

Flash sector overview …continued

Sector number

Sector base address

0003 A000h

0003 C000h

0003 E000h

0004 0000h

0004 2000h

0004 4000h

0004 6000h

0004 8000h

0004 A000h

0004 C000h

0004 E000h

0005 0000h

0005 2000h

0005 4000h

0005 6000h

0005 8000h

0005 A000h

0005 C000h

0005 E000h

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

Table 10. Page addressing overview

Page number

Page base address

0000 0000h

0000 0200h

0000 0400h

0000 0600h

0000 0800h

0000 0A00h

0000 0C00h

0000 0E00h

0000 1000h

0000 1200h

0000 1400h

0000 1600h

0000 1800h

0000 1A00h

0000 1C00h

0000 1E00h

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

The index sector is a special sector in which the JTAG access protection and sector

security are located. The address space becomes visible by setting the FS_ISS bit and

overlaps the regular ﬂash sectors address space.

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Note that the index sector can not be erased and access to index sector has to be

performed via code outside the ﬂash.

8.1.4 Register mapping

The ﬂash memory controller registers are shown in Table 11. The ﬂash memory controller

registers have an offset to the base address FMC RegBase which can be found in the

memory map (see Table 7).

Table 11. Flash memory controller register summary

Address Type Reset

Name

Description

Reference

offset

000h

004h

value

R/W 0005h

FCTR

ﬂash control register

see Table 12

-

reserved

reserved register; do not

modify

008h

00Ch

R/W 0000h

FPTR

ﬂash program time register

see Table 13

see Table 15

-

reserved

reserved register; do not

modify

010h

014h

018h

R/W C004h

FBWST

reserved

ﬂash bridge wait state

register

-

reserved register; do not

modify

reserved register; do not

modify

01Ch

020h

R/W 000h

FCRA

ﬂash clock divider register

see Table 16

see Table 17

R/W 0000h

FMSSTART

ﬂash BIST start address

register

024h

028h

02Ch

030h

034h

038h

FD8h

FDCh

R/W 0 0000h FMSSTOP

ﬂash BIST stop address

register

see Table 18

-

reserved

FMSW0

FMSW1

FMSW2

FMSW3

reserved register; do not

modify

R

W

ﬂash 128-bit signature word 0 see Table 19

register

ﬂash 128-bit signature word 1 see Table 20

register

ﬂash 128-bit signature word 2 see Table 21

register

ﬂash 128-bit signature word 3 see Table 22

register

INT_CLR_ENABLE ﬂash clear interrupt enable

register

see Table 28

INT_SET_ENABLE ﬂash set interrupt enable

register

see Table 27

FE0h

FE4h

FE8h

R

0h

-

INT_STATUS

ﬂash interrupt status register see Table 23

ﬂash interrupt enable register see Table 26

R

INT_ENABLE

W

INT_CLR_STATUS

ﬂash clear interrupt status

register

see Table 25

FECh

W

-

INT_SET_STATUS

ﬂash set interrupt status

register

see Table 24

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8.1.5 Flash control register (FCTR)

The ﬂash control register is used to select read modes, and to control the programming of

the ﬂash memory.

The ﬂash has data latches to store the data that is to be programmed into the ﬂash.

Instead of reading the ﬂash contents, the data latch contents of the ﬂash can be read.

Data latch reading is always done without buffering, with the programmed number of wait

states (WST) on every beat of the burst. Data latch reading can be done both

synchronously and asynchronously. Data latch reading is selected with the FS_RLD bit.

Index sector reading is always done without buffering, with the programmed number of

wait states (WST) on every beat of the burst. Index sector reading can be done both

synchronously and asynchronously. Index sector reading is selected with the FS_ISS bit.

Table 12 shows the bit assignment of the FCTR register.

Table 12. FCTR register bit description

Legend: * reset value

Bit

Symbol

Access Value

Description

31 to 16 reserved

-

reserved; do not modify, read as logic 0, write

as logic 0

15

FS_LOADREQ

R/W

data load request

1

the ﬂash is written if FS_WRE has been set;

the data load is automatically triggered after

the last word was written to the load register;

this bit is automatically cleared and thus

always read as logic 0

0*

14

13

12

11

10

9

FS_CACHECLR

FS_CACHEBYP

FS_PROGREQ

FS_RLS

R/W

-

buffer line clear

1

all bits of the data transfer register are set

0*

buffering bypass

1

reading from ﬂash is without buffering

the read buffering is active

programming request

0*

1

ﬂash programming is requested

0*

select sector latches for reading

the sector latches are read

the ﬂash array is read

1

0*

FS_PDL

preset data latches

1

all bits in the data latches are set

0*

FS_PD

power down

1

0*

-

the ﬂash is in power down

the ﬂash is not in power down

8

reserved

reserved; do not modify, write as logic 0, read

as logic 0

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Table 12. FCTR register bit description …continued

Legend: * reset value

Bit

Symbol

Access Value

Description

7

FS_WPB

R/W

program and erase protection

program and erase have been enabled

program and erase have been disabled

index sector selection

1

0*

6

5

FS_ISS

R/W

1

the index sector will be read

the ﬂash array will be read

read data latches

0*

FS_RLD

R/W

1

the data latches are read for veriﬁcation of

data that is loaded to be programmed

0*

the ﬂash array is read

4

FS_DCR

R/W

DC read mode

1

asynchronous reading has been selected

synchronous reading has been selected

0*

3

2

reserved

FS_WEB

-

reserved; do not modify, write as logic 0, read

as logic 0

R/W

program and erase enable

program and erase have been disabled

program and erase have been enabled

program and erase selection

program and data load have been selected

erase has been selected

1*

0

1

0

FS_WRE

FS_CS

R/W

1

0*

ﬂash chip select

1*

0

the ﬂash is active

the ﬂash is in standby

8.1.6 Flash program time register (FPTR)

The ﬂash program time register controls the timer for burning and erasing the ﬂash

memory. It also allows to read the remaining burn or erase time.

The erase time to be programmed can be calculated from the following formula:

t_er(sect)

TR =

--------------------------------

512 × t_clk(sys)

The burn time to be programmed can be calculated from the following formula:

t_wr(pg)

TR =

--------------------------------

512 × t_clk(sys)

Table 13 shows the bit assignment of the FPTR register.

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Table 13. FPTR register bit description

Legend: * reset value

Bit Symbol

31 to 16 reserved

Access Value

Description

-

reserved; do not modify, read as logic 0, write

as logic 0

15

EN_T

R/W

program timer enable

1

the ﬂash program timer has been enabled

the ﬂash program timer has been disabled

0*

14 to 0 TR[14:0]

R/W

0000h* program timer; the (remaining) burn and erase

time is 512 × TR clock cycles

8.1.7 Flash bridge wait states register (FBWST)

The ﬂash bridge wait states register controls the number of wait states that is inserted for

ﬂash read transfers. This register also controls the second buffer line for asynchronous

reading.

To eliminate the delay that is associated with synchronizing the ﬂash read data, a

predeﬁned number of wait states has to be programmed which depends on the ﬂash

response time and the system clock period. The correlation between maximum system

clock frequency wait states value WST and ﬂash read mode is given by Table 14.

Table 14. Flash read modes versus WST values

Flash read modes

WST value

0

1

2

≥ 3

Synchronous timing

No buffer lines

15

30

45

60

Single buffer lines

Asynchronous timing

No buffer lines

20

40

30

60

Single buffer lines

Dual buffer line, single speculative

Dual buffer line, always speculative

In case the programmed number of wait states is more than three, ﬂash data reading

cannot be performed at full speed if speculative reading is active.

Table 15 shows the bit assignment of the FBWST register.

Table 15. FBWST register bit description

Legend: * reset value

Bit

Symbol

Access Value

Description

31 to 16 reserved

-

reserved; do not modify, read as logic 0, write

as logic 0

15

CACHE2EN

R/W

dual buffering enable

1*

0

the second buffer line has been enabled

the second buffer line has been disabled

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Table 15. FBWST register bit description …continued

Legend: * reset value

Bit

Symbol

Access Value

Description

14

SPECALWAYS

R/W

speculative reading

1*

always speculative reading is performed

single speculative reading is performed

0

13 to 8 reserved

7 to 0 WST[7:0]

-

reserved; do not modify, read as logic 0, write

as logic 0

R/W

04h*

number of wait states; contains the number of

wait states to be inserted for ﬂash reading; the

minimum calculated value must be

programmed for proper ﬂash read operation

8.1.8 Flash clock divider register (FCRA)

The ﬂash clock divider register controls the clock divider for the ﬂash program and erase

clock CRA. This clock should be programmed to 66 kHz during burning or erasing.

The CRA clock frequency fed to the ﬂash memory is the system clock frequency divided

by 3 × (FCRA + 1). The programmed value must result in a CRA clock frequency of

66 kHz ± 20 %.

Table 16 shows the bit assignment of the FCRA register.

Table 16. FCRA register bit description

Legend: * reset value

Bit

Symbol

Access Value

Description

31 to 12 reserved

-

reserved; do not modify, read as logic 0, write

as logic 0

11 to 0 FCRA[11:0]

R/W

000h*

clock divider setting; when logic 0, no CRA

clock is fed to the ﬂash memory

8.1.9 Flash BIST control registers (FMSSTART and FMSSTOP)

The ﬂash BIST control registers control the embedded BIST signature generation via the

BIST start address register FMSSTART and the BIST stop address register FMSSTOP.

A signature can be generated for any part of the ﬂash contents. The address range to be

used for the generation is deﬁned by writing the start address to the BIST start address

register and the stop address to the BIST stop address register. The BIST start and stop

addresses must be ﬂash word aligned and can be derived from the AHB byte addresses

through division by 16. The signature generation is started by setting the BIST start bit in

the BIST stop address register. Setting the BIST start bit is typically combined with

deﬁning the signature stop address.

Note that the ﬂash access is blocked during the BIST signature calculation. The duration

of the ﬂash BIST is t_BIST= (t _fl(BIST)+ 3 × t_clk(sys)) × (FMSSTOP – FMSSTART + 1)

See Section 12 for t_ﬂ(BIST)

.

Table 17 and Table 18 show the bit assignment of the FMSSTART and FMSSTOP

registers, respectively.

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Table 17. FMSSTART register bit description

Legend: * reset value

Bit Symbol

31 to 17 reserved

Access Value

Description

-

reserved; do not modify, read as logic 0,

write as logic 0

16 to 0 FMSSTART[16:0] R/W

0 0000h* BIST start address (corresponds to AHB byte

address [20:4])

Table 18. FMSSTOP register bit description

Legend: * reset value

Bit

Symbol

Access Value

Description

31 to 18 reserved

-

reserved; do not modify, read as logic 0,

write as logic 0

17

MISR_START

R/W

BIST start

1

the BIST signatures generation is initiated

0*

16 to 0

FMSSTOP[16:0] R/W

0 0000h* BIST stop address (corresponds to AHB byte

address [20:4])

8.1.10 Flash BIST signature registers (FMSW0, FMSW1, FMSW2 and FMSW3)

The ﬂash BIST signature registers return the signatures as produced by the embedded

signature generator. There is a a 128-bit signature reﬂected by the four registers FMSW0,

FMSW1, FMSW2 and FMSW3.

The generated signature by the ﬂash can be used to verify the ﬂash contents. The

generated signature can be compared with an expected signature and makes the more

time and code consuming procedure of reading back all contents superﬂuous.

Table 19, Table 20, Table 21 and Table 22 show the bit assignment of the FMSW0 and

FMSW1, FMSW2, FMSW3 registers, respectively.

Table 19. FMSW0 register bit description

Legend: * reset value

Bit

Symbol

Access Value

Description

31 to 0 FMSW0[31:0]

R

-

ﬂash BIST 128-bit signature (bits 31 to 0)

Table 20. FMSW1 register bit description

Legend: * reset value

Bit

Symbol

Access Value

Description

31 to 0 FMSW1[63:32]

R

-

ﬂash BIST 128-bit signature (bits 63 to 32)

Table 21. FMSW2 register bit description

Legend: * reset value

Bit

Symbol

Access Value

Description

31 to 0 FMSW2[95:64]

R

-

ﬂash BIST 128-bit signature (bits 95 to 64)

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Table 22. FMSW3 register bit description

Legend: * reset value

Bit Symbol

31 to 0 FMSW3[127:96]

Access Value

Description

R

-

ﬂash BIST 128-bit signature (bits 127 to 96)

8.1.11 Flash interrupt status register (INT_STATUS)

The ﬂash interrupt status register shows the active interrupt requests. The corresponding

interrupt enable needs to be set.

The INT_STATUS is read only. Table 23 shows the bit assignment of the INT_STATUS

register.

Table 23. INT_STATUS register bit description

Legend: * reset value

Bit

Symbol

Access Value

Description

31 to 3 reserved

-

reserved; do not modify, read as logic 0

signature interrupt

2

1

0

END_OF_MISR

R

1

the BIST signature generation has ﬁnished or

logic 1 is written to bit INT_SET_STATUS[2]

0*

no interrupt is pending or logic 1 is written to

bit INT_CLR_STATUS[2]

END_OF_BURN

END_OF_ERASE

R

burn interrupt

1

the page burning has ﬁnished or logic 1 is

written to bit INT_SET_STATUS[1]

0*

no interrupt is pending or logic 1 is written to

bit INT_CLR_STATUS[1]

erase interrupt

1

the erasing of one or more sectors has

ﬁnished or logic 1 is written to bit

INT_SET_STATUS[0]

0*

no interrupt is pending or logic 1 is written to

bit INT_CLR_STATUS[0]

8.1.12 Flash set interrupt status (INT_SET_STATUS)

The ﬂash set interrupt status register sets the bits in the ﬂash interrupt status register.

The INT_SET_STATUS register is write only. Table 24 shows the bit assignment of the

INT_SET_STATUS register.

Table 24. INT_SET_STATUS register bit description

Legend: * reset value

Bit

31 to 3 reserved

2 to 0 INT_SET_STATUS[2:0] W

Symbol

Access Value Description

-

reserved; do not modify, read as write

-

1

the corresponding bit in the ﬂash interrupt

status register is set

0

the corresponding bit in the ﬂash interrupt

status register is unchanged

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8.1.13 Flash clear interrupt status (INT_CLR_STATUS)

The ﬂash clear interrupt status register clears the bits in the ﬂash interrupt status register.

The INT_CLR_STATUS register is write only. Table 25 shows the bit assignment of the

INT_CLR_STATUS register.

Table 25. INT_CLR_STATUS register bit description

Legend: * reset value

Bit

31 to 3 reserved

2 to 0 INT_CLR_STATUS[2:0] W

Symbol

Access Value Description

-

reserved; do not modify, read as write

-

1

the corresponding bit in the ﬂash interrupt

status register is cleared

0

the corresponding bit in the ﬂash interrupt

status register is unchanged

8.1.14 Flash interrupt enable (INT_ENABLE)

The ﬂash interrupt enable register determines when the ﬂash interface gives an interrupt

request if the corresponding interrupt enable has been set.

The INT_ENABLE register is read only. Table 26 shows the bit assignment of the

INT_ENABLE register.

Table 26. INT_ENABLE register bit description

Legend: * reset value

Bit

Symbol

Access Value Description

31 to 3 reserved

-

reserved; do not modify, read as logic 0

BIST signature interrupt enable

2

1

0

END_OF_MISR

R

1

bit INT_SET_ENABLE[2] is set to enable the

BIST signature interrupt

0*

bit INT_CLR_ENABLE[2] is reset to disable the

interrupt

END_OF_BURN

END_OF_ERASE

R

BIST signature interrupt enable

1

bit INT_SET_ENABLE[1] is set to enable the

BIST signature interrupt

0*

bit INT_CLR_ENABLE[1] is reset to disable the

interrupt

BIST signature interrupt enable

1

bit INT_SET_ENABLE[0] is set to enable the

BIST signature interrupt

0*

bit INT_CLR_ENABLE[0] is reset to disable the

interrupt

8.1.15 Flash set interrupt enable (INT_SET_ENABLE)

The ﬂash set interrupt enable register sets the bits in the ﬂash interrupt enable register.

The INT_SET_ENABLE register is write only. Table 27 shows the bit assignment of the

INT_SET_ENABLE register.

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Table 27. INT_SET_ENABLE register bit description

Legend: * reset value

Bit Symbol

31 to 3 reserved

2 to 0 SET_ENABLE[2:0]

Access Value Description

-

reserved; do not modify, read as write

W

-

1

the corresponding bit in the ﬂash interrupt

enable register is set

0

the corresponding bit in the ﬂash interrupt

enable register is unchanged

8.1.16 Flash clear interrupt enable (INT_CLR_ENABLE)

The ﬂash clear interrupt enable register clears the bits in the ﬂash interrupt enable

register.

The INT_CLR_ENABLE register is write only. Table 28 shows the bit assignment of the

INT_CLR_ENABLE register.

Table 28. INT_CLR_ENABLE register bit description

Legend: * reset value

Bit

31 to 3 reserved

2 to 0 CLR_ENABLE[2:0]

Symbol

Access Value Description

-

reserved; do not modify, read as write

W

-

1

the corresponding bit in the ﬂash interrupt

enable register is cleared

0

the corresponding bit in the ﬂash interrupt

enable register is unchanged

8.2 External static memory controller

8.2.1 Overview

The external Static Memory Controller (SMC) provides an interface for external (off-chip)

memory devices.

The key features are:

• Supports static memory-mapped devices including RAM, ROM, ﬂash, burst ROM and

external I/O devices

• Asynchronous page mode read operation in non-clocked memory subsystems

• Asynchronous burst mode read access to burst mode ROM devices

• Independent conﬁguration for up to 4 banks, each up to 16 MB

• Programmable bus turnaround (idle) cycles (1 to 16)

• Programmable read and write wait states (up to 32), for static RAM devices

• Programmable initial and subsequent burst read wait state, for burst ROM devices

• Programmable write protection

• Programmable burst mode operation

• Programmable external data width: 8 bits, 16 bits or 32 bits

• Programmable read byte lane enable control

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The SMC supports up to four independently conﬁgurable memory banks simultaneously.

Each memory bank can be 8 bits, 16 bits or 32 bits wide and is capable of supporting

SRAM, ROM, ﬂash EPROM, burst ROM memory or external I/O devices.

A separate chip select output is available for each bank. The chip select lines are

conﬁgurable to be active HIGH or LOW. The memory bank selection is controlled by

memory addressing. Table 29 shows the address mapping for the external memory

banks; see also Figure 7.

Table 29. External memory bank address bit description

Bit

Symbol

Description

31 to 29

BA[2:0]

external static memory base address; the base address can be found

in the memory map (see Table 7).

28

-

reserved; write as logic 0

chip select address space for 4 memory banks

00: bank 0

27 to 26

CS[1:0]

01: bank 1

10: bank 2

11: bank 3

25 to 24

23 to 0

-

reserved; write as logic 0

16 MB memory banks address space

A[23:0]

8.2.2 External static memory controller pin description

The SMC module in the SJA2020 has the following pins. The pins are combined with

other functions on the port pins of the SJA2020, see Section 8.3.2. Table 30 shows the

external memory controller pins.

Table 30. External memory controller pins

Symbol

Direction

OUT

Description

EXTBUS CSx

EXTBUS BLSy

memory bank x select, x runs from 0 to 3

byte lane select y, y runs from 0 to 3

write enable (active LOW)

output enable (active LOW)

address bus

OUT

EXTBUS WE_N OUT

EXTBUS OE_N OUT

EXTBUS A[23:0] OUT

EXTBUS D[31:0] IN/OUT

data bus

8.2.3 Register mapping

The SMC memory banks conﬁguration registers are shown in Table 31.

The memory banks conﬁguration registers have an offset to the base address SMC

RegBase which can be found in the memory map (see Table 7).

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Table 31. External static memory controller register summary

Address Type Width Reset Name

Description

Reference

offset

Bank 0

000h

value

R/W

4

5

4

Fh

SMBIDCYR0

SMBWST1R0

SMBWST2R0

idle cycle control register for memory bank 0

wait state 1 control register for memory bank 0

wait state 2 control register for memory bank 0

see Table 32

see Table 33

see Table 34

see Table 35

004h

1Fh

0h

008h

00Ch

SMBWSTOENR0 output enable assertion delay control register for

memory bank 0

010h

R/W

4

1h

SMBWSTWENR0 write enable assertion delay control register for

memory bank 0

see Table 36

014h

018h

Bank 1

01Ch

020h

024h

028h

R/W

8

2

80h

0h

SMBCR0

SMBSR0

conﬁguration register for memory bank 0

status register for memory bank 0

see Table 37

see Table 38

R/W

4

5

4

Fh

SMBIDCYR1

SMBWST1R1

SMBWST2R1

idle cycle control register for memory bank 1

wait state 1 control register for memory bank 1

wait state 2 control register for memory bank 1

see Table 32

see Table 33

see Table 34

see Table 35

1Fh

0h

SMBWSTOENR1 output enable assertion delay control register for

memory bank 1

02Ch

R/W

4

1h

SMBWSTWENR1 write enable assertion delay control register for

memory bank 1

see Table 36

030h

034h

Bank 2

038h

03Ch

040h

044h

R/W

8

2

00h

0h

SMBCR1

SMBSR1

conﬁguration register for memory bank 1

status register for memory bank 1

see Table 37

see Table 38

R/W

4

5

4

Fh

SMBIDCYR2

SMBWST1R2

SMBWST2R2

idle cycle control register for memory bank 2

wait state 1 control register for memory bank 2

wait state 2 control register for memory bank 2

see Table 32

see Table 33

see Table 34

see Table 35

1Fh

0h

SMBWSTOENR2 output enable assertion delay control register for

memory bank 2

048h

R/W

4

1h

SMBWSTWENR2 write enable assertion delay control register for

memory bank 2

see Table 36

04Ch

050h

Bank 3

054h

058h

05Ch

060h

R/W

8

2

40h

0h

SMBCR2

SMBSR2

conﬁguration register for memory bank 2

status register for memory bank 2

see Table 37

see Table 38

R/W

4

5

4

Fh

SMBIDCYR3

SMBWST1R3

SMBWST2R3

idle cycle control register for memory bank 3

wait state 1 control register for memory bank 3

wait state 2 control register for memory bank 3

see Table 32

see Table 33

see Table 34

see Table 35

1Fh

0h

SMBWSTOENR3 output enable assertion delay control register for

memory bank 3

064h

R/W

4

1h

SMBWSTWENR3 write enable assertion delay control register for

memory bank 3

see Table 36

068h

06Ch

R/W

8

2

00h

0h

SMBCR3

SMBSR3

conﬁguration register for memory bank 3

status register for memory bank 3

see Table 37

see Table 38

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8.2.4 Bank idle cycle control registers (SMBIDCYR)

The bank idle cycle control register conﬁgures the external bus turn around cycles

between read and write memory accesses to avoid bus contention on the external

memory data bus. The bus turn-around wait time is inserted between external bus

transfers in case of:

• Read-to-read, to different memory banks

• Read-to-write, to the same memory bank

• Read-to-write, to different memory banks

Table 32 shows the bit assignment of the SMBIDCYR0 to SMBIDCYR3 registers.

Table 32. SMBIDCYRn register bit description

Legend: * reset value

Bit

31 to 4 reserved

3 to 0 IDCY[3:0] R/W

Symbol

Access Value Description

-

reserved; do not modify, read as logic 0, write as logic 0

Fh*

idle or turn-around cycles; this register contains the

number of bus turn-around cycles added between read

and write accesses; the turn-round time is the

programmed number of cycles times the system clock

period

8.2.5 Bank wait state 1 control registers (SMBWST1R)

The bank wait state 1 control register conﬁgures the external transfer wait states in read

accesses. The bank conﬁguration register contains the enable and polarity setting for the

external wait.

The minimum wait states value WST1 can be calculated from the following formula:

t_a(R)int+ t

WST1 =

^d(R)em– 1

---------------------------------------

t_clk(sys)

Where:

t_a(R)int= internal read access time, see Section 12.

t_d(R)em= external memory read delay.

Table 33 shows the bit assignment of the SMBWST1R0 to SMBWST1R3 registers.

Table 33. SMBWST1Rn register bit description

Legend: * reset value

Bit

Symbol

Access Value Description

31 to 5

reserved

-

reserved; do not modify, read as logic 0, write as

logic 0

4 to 0

WST1[4:0] R/W

1Fh*

wait state 1; this register contains the length of read

accesses, except for burst ROM where it deﬁnes the

length of the ﬁrst read access only; the read access

time is the programmed number of wait states times the

system clock period

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8.2.6 Bank wait state 2 control registers (SMBWST2R)

The bank wait state 2 control register conﬁgures the external transfer wait states in write

accesses or the external transfer wait states in burst read accesses. The bank

conﬁguration register contains the enable and polarity setting for the external wait.

Sequential access burst reads from burst ﬂash devices of the same type of as for burst

ROM are supported. Due to sharing of the SMBWST2R register between write and burst

read transfers, it is only possible to have one setting at a time for burst ﬂash, either write

delay or the burst read delay. This means that for write transfer the SMBWST2R register

must be programmed with the write delay value, and for a burst read transfer the

SMBWST2R register must be programmed with the burst access delay.

The minimum wait states value WST2 can be calculated from the following formula:

t_a(W)int+ t

WST2 =

^d(W)em– 1

------------------------------------------

t_clk(sys)

Where:

t

_a(W)int= internal write access time, see Section 12.

t_d(W)em= external memory write delay.

Table 34 shows the bit assignment of the SMBWST2R0 to SMBWST2R3 registers.

Table 34. SMBWST2Rn register bit description

Legend: * reset value

Bit

31 to 5 reserved

4 to 0 WST2[4:0] R/W

Symbol

Access Value Description

-

reserved; do not modify, read as logic 0, write as logic 0

1Fh*

wait state 2; this register contains the length of write

accesses, except for burst ROM where it deﬁnes the

length of the burst read accesses; the write access time

c.q. the burst ROM read access time is the programmed

number of wait states times the system clock period

8.2.7 Bank output enable assertion delay control register (SMBWSTOENR)

The bank output enable assertion delay control register conﬁgures the delay between the

assertion of the chip select and the output enable. This delay is used to reduce the power

consumption for memories that are not able to provide valid data immediately after the

chip select is asserted. The programmed value must be equal to, or less than the bank

wait state 1 programmed value, as the access is timed by the wait states. The output

enable is always de-asserted at the same time as the chip select, at the end of the

transfer. The bank conﬁguration register contains the enable for output assertion delay.

Table 35 shows the bit assignment of the SMBWSTOENR register.

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Table 35. SMBWSTOENR register bit description

Legend: * reset value

Bit Symbol

31 to 4 reserved

3 to 0 WSTOEN R/W

Access Value Description

-

reserved; do not modify, read as logic 0, write as logic 0

0h*

output enable assertion delay; this register contains the

length of the output enable delay after the chip select

assertion; the output enable assertion delay time is the

programmed number of wait states times the system

clock period

8.2.8 Bank write enable assertion delay control register (SMBWSTWENR)

The bank write enable assertion delay control register conﬁgures the delay between the

assertion of the chip select and the write enable. This delay is used to reduce the power

consumption for memories. The programmed value must be equal to, or less than the

bank wait state 2 programmed value, as the access is timed by the wait states. The write

enable is asserted half a system clock cycle after the assertion of the chip select for

logic 0 wait states. The write enable is de-asserted half a system clock cycle before the

chip select, at the end of the transfer. The byte lane select outputs have the same timing

as the write enable output for writes to 8-bit devices that use the byte lane selects instead

of the write enables. The bank conﬁguration register contains the enable for output

assertion delay.

Table 36 shows the bit assignment of the SMBWSTWENR register.

Table 36. SMBWSTWENR register bit description

Legend: * reset value

Bit

31 to 4 reserved

3 to 0 WSTWEN R/W

Symbol

Access Value Description

-

reserved; do not modify, read as logic 0, write as logic 0

1h*

write enable assertion delay; this register contains the

length of the write enable delay after the chip select

assertion; the write enable assertion delay time is the

programmed number of wait states times the system

clock period

8.2.9 Bank conﬁguration register (SMBCR)

The bank conﬁguration register deﬁnes the memory bank access for the connected

memory device.

It is allowed to initiate a wider data transfer to the external memory than the width of the

external memory data bus. In this case the external transfer is automatically split up into

several transfers to complete.

Table 37 shows the bit assignment of the SMBCR register.

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Table 37. SMBCR register bit description

Legend: * reset value

Bit

Symbol Access Value

reserved

MW[1:0] R/W

Description

reserved; do not modify, read as logic 0, write as logic 0

31 to 8

7 to 6

-

bank default* memory width; memory width conﬁguration including the default memory

width after reset

00

01

10

11

8-bit, bank 3 and bank 1 reset (default)

16-bit, bank 2 reset (default)

32-bit, bank 0 reset (default)

reserved

5

BM

R/W

burst mode

1

sequential access burst reads to a maximum of four consecutive locations

is supported to increase the bandwidth by using reduced access time;

however, bursts crossing quad boundaries are split up so that the ﬁrst

transfer after the boundary uses the slow wait state 1 read timing

0*

the memory bank is conﬁgured for nonburst memory

write protect

4

3

WP

R/W

1

the connected device is write protected e.g. (burst) ROM, read only ﬂash, or

SRAM

0*

no write protection is required e.g. SRAM or write enabled ﬂash

chip select polarity

CSPOL

1

0*

-

the chip select input is active HIGH

the chip select input is active LOW

2 to 1

0

reserved

RBLE

-

reserved; do not modify, read as logic 0, write as logic 0

read byte lane enable

R/W

1

the byte lane select pins are held asserted (logic 0) during a read access;

this is for 16-bit or 32-bit devices where the separate write enable signal is

used and the byte lane selects must be held asserted during a read; the

write enable pin WEN is used as the write enable in this conﬁguration

0*

the byte lane select pins BLSn are all de-asserted (logic 1) during a read

access; this is for 8-bit devices where the byte lane enable is connected to

the write enable pin, so it must be de-asserted during a read access

(default at reset); the byte lane select pins are used as write enables in this

conﬁguration

8.2.10 Bank status register (SMBSR)

The bank status register reﬂects the status ﬂags of each memory bank. Table 38 shows

the bit assignment of the SMBSR register.

Table 38. SMBSR register bit description

Legend: * reset value

Bit

Symbol

Access Value Description

31 to 2 reserved

-

reserved; do not modify, read as logic 0, write as logic 0

write protect error

1

WRITEPROTERR R/W

1

a write access to a write protected memory device was initiated; writing

logic 1 to this register clears the write protect status ﬂag

0*

-

writing a logic 0 has no effect

0

reserved

-

reserved; do not modify, read as logic 0, write as logic 0

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8.3 General subsystem

8.3.1 Clock generation unit

8.3.1.1 Overview

The key features are:

• Power mode management

• Reset control

• Control oscillator

• Control PLL

• Fractional clock divider for ADC clock

• Watchdog bark register

8.3.1.2 Description

The clock generation unit conﬁgures all internal clocks. There are four options for the

source for the system clock:

• Crystal/external oscillator

• PLL

• Ring oscillator (ringo)

• Real time clock

Furthermore, the control of the oscillators and PLL takes part here, generally also used for

power mode management. The clock switching between the several sources is performed

in a safe way (glitch free).

8.3.1.3 CGU pin description

The CGU module in the SJA2020 has the following pins. Table 39 shows the CGU pins.

Table 39. CGU pins

Symbol

Direction Description

IN external reset input, active LOW; pulled-up internally

RESET_N

XOUT_OSC OUT

XIN_OSC IN

oscillator crystal output

oscillator crystal input or external clock input

8.3.1.4 Register mapping

The clock generation unit registers are shown in Table 40.

The clock generation unit registers have an offset to the base address CGU RegBase

which can be found in the memory map (see Table 7).

Note: any clock frequency adjustment has direct impact on the timing of on-board

peripherals such as UART, SPI, watchdog, timers, CAN controller, LIN master controller,

ADC, ﬂash memory interface.

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Table 40. CGU register summary

Address Type Reset

value

Name

Description

Reference

000h

004h

008h

00Ch

010h

014h

018h

R/W 1h

CSC

clock switch conﬁguration register

clock frequency select 1 register

clock frequency select 2 register

clock switch status register

see Table 41

see Table 42

see Table 44

see Table 45

R/W 0h

CFS1

CFS2

CSS

R

1h

R/W 1h

CPC0

CPC1

CPC2

AHB clock power control register

ﬂash clock power control register

general and peripheral subsystem

clock power control register

01Ch

R/W 1h

CPC3

in-vehicle networking subsystem clock see Table 45

power control register

020h

024h

028h

02Ch

030h

R/W 0h

CPC4

reserved

CPS0

ADC clock power control register

reserved register; do not modify

AHB clock power status register

ﬂash clock power status register

see Table 45

-

R

3h

see Table 47

CPS1

CPS2

general and peripheral subsystem

clock power status register

034h

R

3h

CPS3

in-vehicle networking subsystem clock see Table 47

power status register

038h

03Ch

040h

044h

048h

04Ch

050h

054h

058h

R

-

2h

-

CPS4

ADC clock power status register

reserved register; do not modify

ADC fractional clock enable register

reserved register; do not modify

fractional clock divider register

see Table 47

reserved

CFCE4

reserved

CFD

-

R/W 0h

see Table 48

see Table 49

-

R/W 7FFC

3FECh

C00h

C04h

C08h

R/W 1h

CPM

power mode register

see Table 50

see Table 52

R

0h

CWDB

watchdog bark register

R/W 1h

CRTCOPM real time clock oscillator power mode see Table 53

register

C0Ch

C10h

C14h

C18h

C1Ch

C20h

C24h

C28h

C2Ch

C30h

-

reserved

COPM

reserved register; do not modify

oscillator power mode register

reserved register; do not modify

oscillator lock status register

R/W 1h

see Table 54

see Table 55

-

reserved

COLS

R

-

1h

-

reserved

reserved register; do not modify

-

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Table 40. CGU register summary …continued

Address Type Reset

Name

Description

Reference

value

C34h

C38h

C3Ch

C40h

C44h

C48h

C4Ch

C50h

C54h

C58h

C5Ch

C60h

C64h

-

reserved

CPCSS

CPPDM

reserved

CPLS

reserved register; do not modify

PLL clock source select register

PLL Power-down mode register

reserved register; do not modify

PLL lock status register

R/W 0h

R/W 1h

see Table 56

see Table 57

-

R

-

0h

-

see Table 58

reserved

CPMR

reserved register; do not modify

PLL multiplication ratio register

PLL post divider register

R/W 0h

R/W 18h

R/W 5h

see Table 59

see Table 61

see Table 63

see Table 64

CPPD

CRPM

ring oscillator power mode register

ring oscillator post divider register

CRPD

CRFS

ring oscillator frequency select register see Table 66

8.3.1.5 Clock switch conﬁguration register (CSC)

The clock switch conﬁguration register conﬁgures the side of the clock switch to be used

as the system clock. There are two clock switch sides to avoid clock glitches when

switching between the four clock source inputs: the oscillator frequency, the PLL

frequency, the ringo and the real time clock.

Table 41 shows the bit assignment of the CSC register.

Table 41. CSC register bit description

Legend: * reset value

Bit

Symbol

Access Value Description

31 to 2 reserved

-

reserved; do not modify, read as logic 0, write as

logic 0

1 to 0 ENF

R/W

switch select

3h

2h

1h*

0h

reserved, do not use

the clock switch uses side 2 as source clock

the clock switch uses side 1 as source clock

reserved, do not use

8.3.1.6 Clock frequency select registers (CFS1 and CFS2)

The clock frequency select registers determines the input clock source of side 1 and side

2 respectively of the frequency switch.

Table 42 shows the bit assignment of the CFS1 and CFS2 registers.

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Table 42. CFS1 and CFS2 register bit assignment

Legend: * reset value

Bit Symbol

31 to 2 reserved

Access Value Description

-

reserved; do not modify, read as logic 0, write as

logic 0

1 to 0

FS1 for CFS1

FS2 for CFS2

R/W

0h*

input frequency select; see Table 43

Table 43. Input clock frequency sources

FS[1:0]

00

Function

oscillator frequency

PLL frequency

01

10

ring oscillator frequency (ringo)

RTC frequency

11

8.3.1.7 Clock switch status register (CSS)

The clock switch status control register represents the selected input clock source and

clock switch status.

Table 44 shows the bit assignment of the CSS register.

Table 44. CSS register bit description

Legend: * reset value

Bit

Symbol

Access Value Description

31 to 4 reserved

-

reserved; do not modify, read as logic 0, write as

logic 0

3 to 2

1 to 0

FSS

R

0h*

frequency select status; see Table 43

switch select

FS_SELECT

3h

2h

1h*

0h

reserved

the clock switch uses side 2 as source clock

the clock switch uses side 1 as source clock

reserved

8.3.1.8 Clock power control registers (CPC0, CPC1, CPC2, CPC3 and CPC4)

The AHB clock power control register (CPC0) conﬁgures the clock operation for the ARM

processor, SRAM and external static memory controller.

The ﬂash clock power control register (CPC1) conﬁgures the clock operation for the ﬂash.

The general and peripheral subsystem clock power control register (CPC2) conﬁgures the

clock operation for the general subsystem, the peripheral subsystem and the modulation

and sampling control subsystem.

The in-vehicle networking subsystem clock power control register (CPC3) conﬁgures the

clock operation for the in-vehicle networking subsystem VPB cluster.

The ADC clock power control register (CPC4) conﬁgures the clock operation for the ADC.

Table 45 shows the bit assignment of the CPC registers.

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Table 45. CPC register bit description

Legend: * reset value

Bit Symbol

31 to 3 reserved

Access Value Description

-

reserved; do not modify, read as logic 0, write as

logic 0

2 to 1

WAKE

R/W

-

0h*

1*

wake mode; see Table 46

0 in

CPC0

reserved

reserved; do not modify, read as logic 1, write as

logic 1

0 in

RUN

R/W

run enable

CPC1

1*

0

the clock is enabled

the clock is disabled

0 in

CPC2

reserved

RUN

-

1*

reserved; do not modify, read as logic 1, write as

logic 1

0 in

R/W

run enable

CPC3

1*

0

the clock is enabled

the clock is disabled

run enable

0 in

RUN

R/W

CPC4

1

the clock is enabled

the clock is disabled

0*

Table 46. Wake mode conﬁguration bits

PM[1:0] Function

00

wake up disabled, the clock is not switched off when entering a low power mode and

not switched on an a wake up event

01

10

11

unsupported, results in unpredicted behavior

wake up enabled, the clock is switched off when entering a low power mode and

switched on an a wake up event

8.3.1.9 Clock power status registers (CPS0, CPS1, CPS2, CPS3 and CPS4)

The AHB clock power status register (CPS0) reﬂects the operational status of the clock for

the ARM processor, SRAM and external static memory controller.

The ﬂash clock power status register (CPS1) reﬂects the operational status of the clock for

the ﬂash.

The general and peripheral subsystem clock power status register (CPS2) reﬂects the

operational status of the clock for the general and peripheral subsystem VPB clusters.

The in-vehicle networking subsystem clock power status register (CPS3) reﬂects the

operational status of the clock for the in-vehicle networking subsystem VPB cluster.

The ADC clock power status register (CPS4) reﬂects the operational status of the clock for

the ADC.

Table 47 shows the bit assignment of the CPS0 register.

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Table 47. CPS register bit description

Legend: * reset value

Bit

Symbol Access Value

Description

31 to 2 reserved

-

reserved; do not modify, read as logic 0, write as

logic 0

1

0

WAKEUP R

wake up

1*

0

the wake up condition is activated

the wake up condition is not activated

active

ACTIVE

R

1* for CPS0,

CPS1, CPS2

and CPS3; 0*

for CPS4

1

0

the clock is functional

the clock is not functional

8.3.1.10 Fractional clock enable register (CFCE4)

The fractional clock enable register conﬁgures the fractional clock as clock source instead

of the clock from the selected switch side. The fractional clock is only targeted for the

ADC.

Table 48 shows the bit assignment of the CFCE4 register.

Table 48. CFCE4 register bits

Legend: * reset value

Bit

Symbol

Access Value Description

31 to 1 reserved

-

reserved; do not modify, read as logic 0, write as

logic 0

0

FCE

R/W

fractional clock enable

1

the fractional clock is the clock source

0*

the clock from the selected switch side is the clock

source

8.3.1.11 Fractional clock divider register (CFD)

The fractional clock divider register determines the clock input frequency for the ADC

which may be maximum 4.5 MHz for correct operation.

n

The ADC clock frequency is determined by the following formula: f _i(ADC)= f _clk(sys)

×

---

m

To minimize the power consumption the values for n and m should be selected as large as

possible. Note that the system clock frequency is at least twice ADC clock frequency:

1

2

f _i(ADC)≤ f _clk(sys)

×

--

Table 49 shows the bit assignment of the CFD register.

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Table 49. CFD register bit description

Legend: * reset value

Bit

Symbol

Access Value

Description

31

reserved

-

reserved; do not modify, read as logic 0, write as

logic 0

30 to 17 MSUB[13:0] R/W

3FFEh* fractional clock divider parameter MSUB; signed

value deﬁned by (− n)

16 to 3

2

MADD[13:0] R/W

07FDh* fractional clock divider parameter MADD; unsigned

value deﬁned by (m − n)

STRETCH

RESET

R/W

clock stretching

1*

0

must be set to logic 1 to feed the required

approximately 50 % duty cycle clock to the ADC

1

0

fractional divider reset

1

the fractional clock divider is reset asynchronously;

the reset must be active while changing the ADC

clock frequency

0*

1

EN

R/W

enable

the fractional clock divider is running to serve as

the ADC clock if the ADC fractional clock is enabled

in the fractional clock enable register

0*

8.3.1.12 Power mode register (CPM)

The power mode register conﬁgures the operation mode and wake up mechanism.

Table 50 shows the bit assignment of the CPM register.

Table 50. CPM register bit description

Legend: * reset value

Bit

Symbol

Access Value

Description

31 to 2 reserved

-

reserved; do not modify, read as logic 0, write as

logic 0

1 to 0

PM[1:0]

R/W

1h*

power mode; see Table 51

Table 51. Power mode conﬁguration bits

PM[1:0]

00

Function

unsupported

01

normal operation mode, this mode is automatically set after wake-up

unsupported, results in unpredicted behavior

10

11

Idle mode, wake-up event results in resume

8.3.1.13 Watchdog bark register (CWDB)

The watchdog bark register indicates whether a system reset was caused by the

watchdog or not. This register is cleared only by an external or power-on reset.

Table 52 shows the bit assignment of the CWDB register.

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Table 52. CWDB register bit description

Legend: * reset value

Bit Symbol

31 to 1 reserved

WDB

Access Value Description

-

reserved; do not modify, read as logic 0, write as logic 0

watchdog bark

0

R

1

a watchdog reset occurred

0*

an external or power-on reset occurred

8.3.1.14 Real time clock oscillator power mode register (CRTCOPM)

The real time clock oscillator power mode register can switch off the 32 kHz oscillator.

This is recommended in case the real time clock is not used. It is not allowed to switch on

the real time clock oscillator again once switched off.

Table 53 shows the bit assignment of the CRTCOPM register.

Table 53. CRTCOPM register bit description

Legend: * reset value

Bit

Symbol Access Value Description

31 to 1

reserved

-

reserved; do not modify, read as logic 0, write as

logic 0

0

RTCOPM R/W

real time clock oscillator power mode

the 32 kHz oscillator is active

1*

0

the 32 kHz oscillator is inactive and in Power-down

mode

8.3.1.15 Oscillator power mode register (COPM)

The oscillator power mode register is used to switch on and off the system oscillator.

Table 54 shows the bit assignment of the COPM register.

Table 54. COPM register bit description

Legend: * reset value

Bit

31 to 1 reserved

OPM

Symbol Access Value Description

-

reserved; do not modify, read as logic 0, write as logic 0

oscillator power mode

0

R/W

1*

0

the oscillator is active

the system oscillator is inactive and in Power-down

mode

8.3.1.16 Oscillator lock status register (COLS)

The oscillator lock status register represents the status of the oscillator clock frequency

stability. The lock detector goes high after a delay based on a gray code counter.

Table 58 shows the bit assignment of the COLS register.

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Table 55. COLS register bit description

Legend: * reset value

Bit

Symbol Access Value Description

31 to 1

0

reserved

OLS

-

reserved; do not modify, read as logic 0, write as logic 0

oscillator lock status

R

1*

0

the oscillator is locked

the oscillator is not in lock or in Power-down mode

8.3.1.17 PLL clock source select register (CPCSS)

The PLL clock source select register determines the input frequency for the PLL.

Table 56 shows the bit assignment of the CPCSS register.

Table 56. CPCSS register bit description

Legend: * reset value

Bit

31 to 1 reserved

PCSS

Symbol Access Value Description

-

reserved; do not modify, read as logic 0, write as logic 0

PLL clock source select

0

R/W

1

the oscillator frequency is the input frequency for the PLL

no clock is fed to the PLL

0*

8.3.1.18 PLL Power-down mode register (CPPDM)

The PLL Power-down mode register is used to switch on and off the PLL. The PLL must

be in Power-down mode during conﬁguration change.

Table 57 shows the bit assignment of the CPPDM register.

Table 57. CPPDM register bit description

Legend: * reset value

Bit

31 to 1 reserved

PPDM

Symbol Access Value Description

-

reserved; do not modify, read as logic 0, write as logic 0

PLL Power-down mode

0

R/W

1*

0

the PLL is inactive and in Power-down mode

the PLL is active

8.3.1.19 PLL lock status register (CPLS)

The PLL lock status register represents the status of the PLL clock frequency stability. The

lock detector measures the phase difference between the rising edges of the input and

feedback clocks.

Only when this difference is smaller than the so called ‘lock criterion’ for more than eight

consecutive input clock periods, the lock output switches from LOW to HIGH. A single too

large phase difference immediately resets the counter and causes the lock signal to drop

(if it was HIGH). Requiring eight phase measurements in a row to be below a certain

ﬁgure ensures that the lock detector will not indicate lock until both the phase and

frequency of the input and feedback clocks are very well aligned. This effectively prevents

false lock indications, and thus ensures a glitch free lock signal.

Table 58 shows the bit assignment of the CPLS register.

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Table 58. CPLS register bit description

Legend: * reset value

Bit

Symbol Access Value Description

31 to 1 reserved

-

reserved; do not modify, read as logic 0, write as logic 0

PLL lock status

0

PLS

R

1

the PLL is locked

0*

the PLL is not in lock or in Power-down mode

8.3.1.20 PLL multiplication ratio register (CPMR)

The PLL multiplication ratio register deﬁnes the ratio between the PLL output clock and

the input clock.

f _clk(sys)

The multiplication ratio can be calculated from the following formula: PMR =

-------------------

f _i(osc)

Table 59 shows the bit assignment of the CPMR register.

Table 59. CPMR register bit description

Legend: * reset value

Bit

31 to 3 reserved

2 to 0 PMR[2:0] R/W

Symbol

Access Value Description

-

reserved; do not modify, read as logic 0, write as logic 0

PLL multiplication ratio; see Table 60

00h*

Table 60. Multiplication ratio conﬁguration bits

PMR[2:0]

000

Function

input frequency multiplication by 1

input frequency multiplication by 2

input frequency multiplication by 3

input frequency multiplication by 4

input frequency multiplication by 5

input frequency multiplication by 6

unsupported, results in unpredicted behavior

001

010

011

100

101

110

111

8.3.1.21 PLL post divider register (CPPD)

The PLL post divider register deﬁnes division ratio between the PLL CCO frequency and

PLL output clock frequency. The post division guarantees an output clock with a 50 % duty

cycle. The CCO frequency must fulﬁl the speciﬁed limits.

f _CCO

The post division ratio can be calculated from the following formula: PPD =

-------------------

f _clk(sys)

Table 61 shows the bit assignment of the CPPD register.

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Table 61. CPPD register bits

Legend: * reset value

Bit

Symbol

Access Value Description

31 to 2

reserved

-

reserved; do not modify, read as logic 0, write as

logic 0

1 to 0

PPD[1:0]

R/W

0h*

PLL post divider; see Table 62

Table 62. PLL post divider conﬁguration bits

PPD[1:0]

Function

00

01

10

11

post division by 2

post division by 4

post division by 8

post division by 16

8.3.1.22 Ring oscillator power mode register (CRPM)

The ring oscillator power mode register is used to switch on and off the ring oscillator.

Figure 9 shows the structure of the ring oscillator.

RPM

RFS[3:0]

RPD[4:0]

FREQUENCY SELECT

MULTIPLY BY

POST DIVIDER

DIVIDE BY

2 TO 64

LOW POWER RING

OSCILLATOR

f

ref(RO)

i(RO)

o(RO)

0.45 TO 1.73

001aae433

Fig 9. Ring oscillator block diagram

Table 63 shows the bit assignment of the CRPM register.

Table 63. CRPM register bit description

Legend: * reset value

Bit

31 to 1 reserved

RPM

Symbol Access Value Description

-

reserved; do not modify, read as logic 0, write as logic 0

oscillator power mode

0

R/W

1

the ring oscillator is active

0*

the ring oscillator is inactive and in Power-down mode

8.3.1.23 Ring oscillator post divider register (CRPD)

The ring oscillator post divider register deﬁnes division ratio between the calibrated

internal ring oscillator frequency (see Section 8.3.1.24) and ring oscillator output clock

frequency. The post division guarantees an output clock with a 50 % duty cycle.

The post division ratio can be calculated from the following formula:

f _i(RO)

f _o(RO)

=

-----------------------------------

2 × (RPD + 1)

Table 64 shows the bit assignment of the CRPD register.

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Table 64. CRPD register bit description

Legend: * reset value

Bit

Symbol Access Value Description

31 to 5 reserved

-

reserved; do not modify, read as logic 0, write as logic 0

ring oscillator post divider; see Table 65

4 to 0

RPD[4:0] R/W

18h*

Table 65. Ring oscillator post divider conﬁguration bits

RPD[4:0]

00000

00001

00010

00011

...

Function

post division by 2

post division by 4

post division by 6

post division by 8

...

11110

11111

post division by 62

post division by 64

8.3.1.24 Ring oscillator frequency select register (CRFS)

The ring oscillator frequency select ratio register is used to calibrate the internal ring

oscillator frequency f_i(RO)to compensate for frequency variation in the internal ring

oscillator reference frequency f_ref(RO). See Section 12 for the speciﬁed range of f_ref(RO)

.

Table 66 shows the bit assignment of the CRFS register.

Table 66. CRFS register bit description

Legend: * reset value

Bit

Symbol

Access Value Description

31 to 4

reserved

-

reserved; do not modify, read as logic 0, write as

logic 0

3 to 0

RFS[3:0]

R/W

5h*

ring oscillator frequency select; see Table 67

Table 67. Ring oscillator frequency select conﬁguration bits

RFS[3:0]

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

Function

f_i(RO)= 0 Hz

f_i(RO)= f_ref(RO)× 0.45

f_i(RO)= f_ref(RO)× 0.63

f_i(RO)= f_ref(RO)× 0.77

f_i(RO)= f_ref(RO)× 0.89

f_i(RO)= f_ref(RO)× 1.00

f_i(RO)= f_ref(RO)× 1.10

f_i(RO)= f_ref(RO)× 1.18

f_i(RO)= f_ref(RO)× 1.26

f_i(RO)= f_ref(RO)× 1.34

f_i(RO)= f_ref(RO)× 1.41

f_i(RO)= f_ref(RO)× 1.48

f_i(RO)= f_ref(RO)× 1.55

SJA2020_2

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ARM7 microcontroller with CAN and LIN controllers

Table 67. Ring oscillator frequency select conﬁguration bits …continued

RFS[3:0] Function

1101

1110

1111

f_i(RO)= f_ref(RO)× 1.61

f_i(RO)= f_ref(RO)× 1.67

f_i(RO)= f_ref(RO)× 1.73

8.3.2 System control unit

8.3.2.1 Overview

The system control unit takes care of system related functions.

The key features are:

• Shadow memory remapping

• Conﬁguration of I/O port pins multiplexer

Firstly, the mapping of a (partially) region into the shadow memory area. After reset, the

ﬂash region is shadowed. To increase the overall system performance, (a part of) the

internal SRAM region is advised to shadow for interrupt handling.

Secondly, the function of each I/O pin. The I/O pin conﬁguration should be consistent with

the peripheral function usage.

8.3.2.2 SCU pin description

The SCU has no external pins.

8.3.2.3 Register mapping

The system control unit registers are shown in Table 68.

The system control unit registers have an offset to the base address SCU RegBase which

can be found in the memory map (see Table 7).

Table 68. SCU register summary

Address Type Reset value Name

Description

Reference

00h

04h

08h

0Ch

10h

14h

18h

1Ch

20h

24h

R/W 2000 0000h SSMM

shadow memory mapping register

see Table 69

see Table 71

see Table 72

see Table 71

see Table 72

see Table 71

see Table 72

see Table 76

R/W 0000 0000h SFSAP0 function select A port 0 register

R/W 0000 0000h SFSBP0 function select B port 0 register

R/W 0000 0000h SFSAP1 function select A port 1 register

R/W 0000 0000h SFSBP1 function select B port 1 register

R/W 0000 0000h SFSAP2 function select A port 2 register

R/W 0000 0000h SFSBP2 function select B port 2 register

R/W 0000 0000h SPUCP0 pull-up control port 0 register

R/W 0000 0000h SPUCP1 pull-up control port 1 register

R/W 0000 0000h SPUCP2 pull-up control port 2 register

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8.3.2.4 Shadow memory mapping register (SSMM)

The shadow memory mapping register deﬁnes which part of the memory region is present

in the shadow memory area. The shadow memory mapping start address is the pointer

within a region indicating the for shadowing in the shadow area starting at location

0000 0000h. In this way a whole region or only a part of the ﬂash, SRAM or external

memory bank can be remapped to the shadow area.

Table 69 shows the bit assignment of the SSMM register.

Table 69. SSMM register bit description

Legend: * reset value

Bit

Symbol

Access Value

Description

31 to 10 SMMSA[21:0] R/W

2000 0000h* shadow memory map start address; memory

start address for mapping (a part of) a region

to the shadow area; the start address is

aligned on 1 kB boundaries and therefore the

lowest 10 bits must be always logic 0

9 to 0

reserved

-

reserved; do not modify, read as logic 0, write

as logic 0

8.3.2.5 Port function select registers (SFSAP0 to SFSAP2 and SFSBP0 to SFSBP2)

The port function select register conﬁgures the pin functions individually on the

corresponding I/O port. The function select A registers deﬁne the lower 16 port pins and

the function select B registers deﬁne the upper 16 port pins. For port 2, the two most

upper port pins are reserved.

See Table 73 to Table 75 for the pin function multiplex content.

The pin function selection is done with 2 bits in the port function select registers (see

Table 70).

Table 70. Pin function select conﬁguration bits

Value bits [1:0] Function

00

01

10

11

select pin function 0 from corresponding I/O port conﬁguration

select pin function 1 from corresponding I/O port conﬁguration

select pin function 2 from corresponding I/O port conﬁguration

select pin function 3 from corresponding I/O port conﬁguration

Table 71 shows the bit assignment of the SFSAP0, SFSAP1 and SFSAP2 registers and

Table 72 shows the bit assignment of the SFSBP0, SFSBP1 and SFSBP2 registers.

Table 71. SFSAP0, SFSAP1 and SFSAP2 register bit description

Legend: * reset value

Bit

Symbol

Access Value Description

31 to 30

29 to 28

27 to 26

25 to 24

23 to 22

21 to 20

PFSP15[1:0]

PFSP14[1:0]

PFSP13[1:0]

PFSP12[1:0]

PFSP11[1:0]

PFSP10[1:0]

R/W

0h*

port pin 15 function select

port pin 14 function select

port pin 13 function select

port pin 12 function select

port pin 11 function select

port pin 10 function select

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Table 71. SFSAP0, SFSAP1 and SFSAP2 register bit description …continued

Legend: * reset value

Bit

Symbol

Access Value Description

19 to 18

17 to 16

15 to 14

13 to 12

11 to 10

9 to 8

PFSP9[1:0]

PFSP8[1:0]

PFSP7[1:0]

PFSP6[1:0]

PFSP5[1:0]

PFSP41:0]

PFSP3[1:0]

PFSP2[1:0]

PFSP1[1:0]

PFSP0[1:0]

R/W

0h*

port pin 9 function select

port pin 8 function select

port pin 7 function select

port pin 6 function select

port pin 5 function select

port pin 4 function select

port pin 3 function select

port pin 2 function select

port pin 1 function select

port pin 0 function select

7 to 6

5 to 4

3 to 2

1 to 0

Table 72. SFSBP0, SFSBP1 and SFSBP2 register bit description

Legend: * reset value

Bit

Symbol

Access Value Description

31 to 30

29 to 28

27 to 26

25 to 24

23 to 22

21 to 20

19 to 18

17 to 16

15 to 14

13 to 12

11 to 10

9 to 8

PFSP31[1:0]

PFSP30[1:0]

PFSP29[1:0]

PFSP28[1:0]

PFSP27[1:0]

PFSP26[1:0]

PFSP25[1:0]

PFSP24[1:0]

PFSP23[1:0]

PFSP22[1:0]

PFSP21[1:0]

PFSP20[1:0]

PFSP19[1:0]

PFSP18[1:0]

PFSP17[1:0]

PFSP16[1:0]

R/W

0h*

port pin 31 function select; reserved for port 2

port pin 30 function select; reserved for port 2

port pin 29 function select

port pin 28 function select

port pin 27 function select

port pin 26 function select

port pin 25 function select

port pin 24 function select

port pin 23 function select

port pin 22 function select

port pin 21 function select

port pin 20 function select

port pin 19 function select

port pin 18 function select

port pin 17 function select

port pin 16 function select

7 to 6

5 to 4

3 to 2

1 to 0

Table 73. Port 0 function assignment

Symbol

Description

Default function Function 1

Function 2

Function 3

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

GPIO 0; pin 0

GPIO 0; pin 1

GPIO 0; pin 2

GPIO 0; pin 3

GPIO 0; pin 4

GPIO 0; pin 5

GPIO 0; pin 6

GPIO 0; pin 0

GPIO 0; pin 1

GPIO 0; pin 2

GPIO 0; pin 3

GPIO 0; pin 4

GPIO 0; pin 5

GPIO 0; pin 6

EXT BUS A0

EXT BUS A1

EXT BUS A2

EXT BUS A3

EXT BUS A4

EXT BUS A5

EXT BUS A6

EXT BUS A0

EXT BUS A1

EXT BUS A2

EXT BUS A3

EXT BUS A4

EXT BUS A5

EXT BUS A6

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Table 73. Port 0 function assignment …continued

Symbol Description

Default function Function 1

Function 2

Function 3

P0.7

GPIO 0; pin 7

GPIO 0; pin 8

GPIO 0; pin 9

GPIO 0; pin 10

GPIO 0; pin 11

GPIO 0; pin 12

GPIO 0; pin 13

GPIO 0; pin 14

GPIO 0; pin 15

GPIO 0; pin 16

GPIO 0; pin 17

GPIO 0; pin 18

GPIO 0; pin 19

GPIO 0; pin 20

GPIO 0; pin 21

GPIO 0; pin 22

GPIO 0; pin 23

GPIO 0; pin 24

GPIO 0; pin 25

GPIO 0; pin 26

GPIO 0; pin 27

GPIO 0; pin 28

GPIO 0; pin 29

GPIO 0; pin 30

GPIO 0; pin 31

GPIO 0; pin 7

GPIO 0; pin 8

GPIO 0; pin 9

GPIO 0; pin 10

GPIO 0; pin 11

GPIO 0; pin 12

GPIO 0; pin 13

GPIO 0; pin 14

GPIO 0; pin 15

GPIO 0; pin 16

GPIO 0; pin 17

GPIO 0; pin 18

GPIO 0; pin 19

SPI2 SCS

EXT BUS A7

EXT BUS A8

EXT BUS A9

EXT BUS A10

EXT BUS A11

EXT BUS A12

EXT BUS A13

EXT BUS A14

EXT BUS A15

EXT BUS A16

EXT BUS A17

EXT BUS A18

EXT BUS A19

EXT BUS A20

EXT BUS A21

EXT BUS A22

EXT BUS A23

SPI1 SCS

EXT BUS A7

EXT BUS A8

EXT BUS A9

EXT BUS A10

EXT BUS A11

EXT BUS A12

EXT BUS A13

EXT BUS A14

EXT BUS A15

EXT BUS A16

EXT BUS A17

EXT BUS A18

EXT BUS A19

EXT BUS A20

EXT BUS A21

EXT BUS A22

EXT BUS A23

SPI1 SCS

P0.8

P0.9

P0.10

P0.11

P0.12

P0.13

P0.14

P0.15

P0.16

P0.17

P0.18

P0.19

P0.20

P0.21

P0.22

P0.23

P0.24

P0.25

P0.26

P0.27

P0.28

P0.29

P0.30

P0.31

SPI2 SCK

SPI2 SDI

SPI2 SDO

GPIO 0; pin 24

GPIO 0; pin 25

GPIO 0; pin 26

GPIO 0; pin 27

GPIO 0; pin 28

GPIO 0; pin 29

GPIO 0; pin 30

GPIO 0; pin 31

SPI1 SCK

SPI1 SDI

SPI1 SDO

SPI0 SCS

SPI0 SCK

SPI0 SDI

SPI0 SDO

Table 74. Port 1 function assignment

Symbol

Description

Default function Function 1

Function 2

Function 3

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

P1.8

P1.9

P1.10

GPIO 1; pin 0

GPIO 1; pin 1

GPIO 1; pin 2

GPIO 1; pin 3

GPIO 1; pin 4

GPIO 1; pin 5

GPIO 1; pin 6

GPIO 1; pin 7

GPIO 1; pin 8

GPIO 1; pin 9

GPIO 1; pin 10

GPIO 1; pin 0

GPIO 1; pin 1

GPIO 1; pin 2

GPIO 1; pin 3

GPIO 1; pin 4

GPIO 1; pin 5

GPIO 1; pin 6

GPIO 1; pin 7

GPIO 1; pin 8

GPIO 1; pin 9

GPIO 1; pin 10

EXT BUS D0

EXT BUS D1

EXT BUS D2

EXT BUS D3

EXT BUS D4

EXT BUS D5

EXT BUS D6

EXT BUS D7

EXT BUS D8

EXT BUS D9

EXT BUS D10

EXT BUS D0

EXT BUS D1

EXT BUS D2

EXT BUS D3

EXT BUS D4

EXT BUS D5

EXT BUS D6

EXT BUS D7

EXT BUS D8

EXT BUS D9

EXT BUS D10

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Table 74. Port 1 function assignment …continued

Symbol Description

Default function Function 1

Function 2

Function 3

P1.11

P1.12

P1.13

P1.14

P1.15

P1.16

P1.17

P1.18

P1.19

P1.20

P1.21

P1.22

P1.23

P1.24

P1.25

P1.26

P1.27

P1.28

P1.29

P1.30

P1.31

GPIO 1; pin 11

GPIO 1; pin 12

GPIO 1; pin 13

GPIO 1; pin 14

GPIO 1; pin 15

GPIO 1; pin 16

GPIO 1; pin 17

GPIO 1; pin 18

GPIO 1; pin 19

GPIO 1; pin 20

GPIO 1; pin 21

GPIO 1; pin 22

GPIO 1; pin 23

GPIO 1; pin 24

GPIO 1; pin 25

GPIO 1; pin 26

GPIO 1; pin 27

GPIO 1; pin 28

GPIO 1; pin 29

GPIO 1; pin 30

GPIO 1; pin 31

GPIO 1; pin 11

GPIO 1; pin 12

GPIO 1; pin 13

GPIO 1; pin 14

GPIO 1; pin 15

TIMER3 CAP3

TIMER3 CAP2

TIMER3 CAP1

TIMER3 CAP0

TIMER2 CAP3

TIMER2 CAP2

TIMER2 CAP1

TIMER1 CAP3

TIMER1 CAP2

TIMER1 CAP1

TIMER0 CAP3

TIMER0 CAP2

TIMER0 CAP1

TIMER0 CAP0

RTCK

EXT BUS D11

EXT BUS D12

EXT BUS D13

EXT BUS D14

EXT BUS D15

EXT BUS D16

EXT BUS D17

EXT BUS D18

EXT BUS D19

EXT BUS D20

EXT BUS D21

EXT BUS D22

EXT BUS D23

EXT BUS D24

EXT BUS D25

EXT BUS D26

EXT BUS D27

EXT BUS D28

EXT BUS D29

EXT BUS D30

EXT BUS D31

EXT BUS D11

EXT BUS D12

EXT BUS D13

EXT BUS D14

EXT BUS D15

TIMER3 MAT3

TIMER3 MAT2

TIMER3 MAT1

TIMER3 MAT0

TIMER2 MAT3

TIMER2 MAT2

TIMER2 MAT1

TIMER1 MAT3

TIMER1 MAT2

TIMER1 MAT1

TIMER0 MAT3

TIMER0 MAT2

TIMER0 MAT1

TIMER0 MAT0

EXT BUS D30

EXT BUS D31

GPIO 1; pin 31

Table 75. Port 2 function assignment

Symbol

Description

Default function Function 1

Function 2

Function 3

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

P2.8

P2.9

P2.10

P2.11

P2.12

P2.13

P2.14

GPIO 2; pin 0

GPIO 2; pin 1

GPIO 2; pin 2

GPIO 2; pin 3

GPIO 2; pin 4

GPIO 2; pin 5

GPIO 2; pin 6

GPIO 2; pin 7

GPIO 2; pin 8

GPIO 2; pin 9

GPIO 2; pin 10

GPIO 2; pin 11

GPIO 2; pin 12

GPIO 2; pin 13

GPIO 2; pin 14

GPIO 2; pin 0

GPIO 2; pin 1

GPIO 2; pin 2

GPIO 2; pin 3

GPIO 2; pin 4

GPIO 2; pin 5

GPIO 2; pin 6

GPIO 2; pin 7

GPIO 2; pin 8

GPIO 2; pin 9

GPIO 2; pin 10

GPIO 2; pin 11

GPIO 2; pin 12

GPIO 2; pin 13

LIN3 TXDL

EXT BUS OEN

EXT BUS WEN

EXT BUS BLS0

EXT BUS BLS1

EXT BUS BLS2

EXT BUS BLS3

CAN0 TXDC

CAN0 RXDC

CAN1 TXDC

CAN1 RXDC

CAN2 TXDC

CAN2 RXDC

CAN3 TXDC

CAN3 RXDC

CAN4 TXDC

EXT BUS OEN

EXT BUS WEN

EXT BUS BLS0

EXT BUS BLS1

EXT BUS BLS2

EXT BUS BLS3

CAN0 TXDC

CAN0 RXDC

CAN1 TXDC

CAN1 RXDC

CAN2 TXDC

CAN2 RXDC

CAN3 TXDC

CAN3 RXDC

CAN4 TXDC

SJA2020_2

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Table 75. Port 2 function assignment …continued

Symbol Description

Default function Function 1

Function 2

Function 3

P2.15

P2.16

P2.17

P2.18

P2.19

P2.20

P2.21

P2.22

P2.23

P2.24

P2.25

P2.26

P2.27

P2.28

P2.29

GPIO 2; pin 15

GPIO 2; pin 16

GPIO 2; pin 17

GPIO 2; pin 18

GPIO 2; pin 19

GPIO 2; pin 20

GPIO 2; pin 21

GPIO 2; pin 22

GPIO 2; pin 23

GPIO 2; pin 24

GPIO 2; pin 25

GPIO 2; pin 26

GPIO 2; pin 27

GPIO 2; pin 28

GPIO 2; pin 29

LIN3 RXDL

CAN4 RXDC

CAN5 TXDC

CAN5 RXDC

LIN1 TXDL

CAN4 RXDC

CAN5 TXDC

CAN5 RXDC

LIN1 TXDL

LIN2 TXDL

LIN2 RXDL

UART TXD

UART RXD

LIN1 RXDL

GPIO 2; pin 20

GPIO 2; pin 21

GPIO 2; pin 22

GPIO 2; pin 23

GPIO 2; pin 24

GPIO 2; pin 25

EXTINT2

LIN0 TXDL

LIN0 RXDL

TIMER2 CAP0

TIMER1 CAP0

EXTINT0

TIMER2 MAT0

TIMER1 MAT0

EXTINT0

EXTINT1

EXT BUS CS3

EXT BUS CS2

EXT BUS CS1

EXT BUS CS0

EXT BUS CS3

EXT BUS CS2

EXT BUS CS1

EXT BUS CS0

EXTINT3

GPIO 2; pin 28

GPIO 2; pin 29

8.3.2.6 Pull-up control registers (SPUCP0, SPUCP1 and SPUCP2)

The pull-up control register conﬁgures the pull-up per pin on the corresponding I/O port.

For port 2, the two most upper port pins are reserved. Note that the pull-up must be

switched off before a 5 V signal is applied to the respective port pin.

Table 71 shows the bit assignment of the SPUCP0, SPUCP1 and SPUCP2 registers.

Table 76. SPUCP0, SPUCP1 and SPUCP2 register bit description

Legend: * reset value

Bit

Symbol

Access Value

Description

31 to 0 PUC[31:0] ^[1]R/W

0000 0000h* port pin pull-up control

1

0

corresponding port pin is ﬂoating when 3-state

corresponding port pin is pulled-up

[1] PUC[31:30] are reserved for port 2.

8.3.3 SPI

8.3.3.1 Overview

Three SPIs are included to enable synchronous serial communication with slave or

master peripherals.

The key features are:

• Master or slave operation

• Programmable clock bit rate and prescale

• Separate transmit and receive ﬁrst-in, ﬁrst-out memory buffers, 16-bit wide,

8 locations deep

SJA2020_2

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• Programmable choice of interface operation: Motorola SPI, National Semiconductors

Microwire or Texas Instruments (synchronous serial)

• Programmable data frame size from 4 bits to 16 bits

• Independent masking of transmit FIFO, receive FIFO, and receive overrun interrupts

• Internal loopback test mode

Note that in case the receive FIFO is not empty and the serial port remains idle for a ﬁxed

32-bit period of the system clock, the receive time-out is asserted to ensure proper

servicing of the received data.

More information about SPI can also be found in ARM PrimeCell documentation (see

Ref. 4).

8.3.3.2 SPI pin description

The three SPI modules in the SJA2020 have the following pins. The pins are combined

with other functions on the port pins of the SJA2020, see Section 8.3.2. Table 77 shows

the SPI pins, x runs from 0 to 2.

Table 77. SPI pins

Symbol

Direction

IN/OUT^[1]

IN

Description

SPIx SCS

SPIx SCK

SPIx SDI

SPIx SDO

SPI x chip select

SPI x clock

SPI x data input

SPI x data output

OUT

[1] Direction depends on master or slave mode.

8.3.3.3 Register mapping

The SPI registers are shown in Table 78. The SPI registers have an offset to the base

address SPI RegBase which can be found in the memory map (see Table 7).

Table 78. SPI register summary

Address Type Reset

value

Name

Description

Reference

00h

04h

08h

0Ch

10h

14h

18h

1Ch

20h

R/W 0000h

R/W 0h

SSPCR0

SSPCR1

SSPDR

control register 0

see Table 79

see Table 82

see Table 83

see Table 84

see Table 85

see Table 86

see Table 87

see Table 88

see Table 89

control register 1

R/W

R

-

FIFO data register

03h

SSPSR

status register

R/W 00h

R/W 0h

SSPCPSR

SSPIMSC

SSPRIS

SSPMIS

SSPICR

clock prescale register

interrupt enable register

raw interrupt status register

masked interrupt status register

interrupt clear register

R

8h

0h

R

W

8.3.3.4 SPI control register 0 (SSPCR0)

The SPI control register 0 conﬁgures the SPI operation mode.

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In all modes, the SPI clock is only active during transmission and reception of data. The

SPI clock idle state is utilized to provide time-out indication that occurs when the receive

FIFO still contains data after a time-out period.

Table 79 shows the bit assignment of the SSPCR0 register.

Table 79. SSPCR0 register bit description

Legend: * reset value

Bit

31 to 16 reserved

15 to 8 SCR[7:0] R/W

Symbol Access Value Description

-

reserved; do not modify, read as logic 0, write as logic 0

serial clock rate ^[1]

00h*

7

6

SPH

SPO

R/W

clock phase which is applicable to Motorola frame format

only; the clock phase bit selects the clock edge that

captures data after the chip select SCSn becomes active

LOW

1

data is captured on the second clock edge

data is captured on the ﬁrst clock edge

0*

R/W

clock polarity which is applicable to Motorola frame format

only; the clock polarity bit selects the SPI clock steady

state level

1

the SPI clock output is HIGH when no data is being

transferred

0*

the SPI clock output is LOW when no data is being

transferred

5 to 4

3 to 0

FRF[1:0] R/W

DSS[2:0] R/W

0h*

frame format; see Table 80

data size select; see Table 81

f _clk(sys)

[1] The transmit and receive bit rate is determined by following formula: bit rate =

---------------------------------------------------------

SPSDVSR × (1 + SCR)

Where: f_clk(sys)= system clock frequency; SPSDVSR = clock prescale divisor, see Table 85; SCR = serial

clock rate, see Table 79.

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Table 80. SPI frame format conﬁguration

FRF[1:0] Function

00

01

10

Motorola SPI frame format.

Full-duplex, 4-wire synchronous transfers; the transmit data line SDOn is arbitrarily

forced logic 0 if inactive; the chip select line SCSn is active logic 0 and is asserted

during the entire frame transmission; continuous transfers are separated by a one SPI

clock period idle (HIGH) state of the chip select line SCSn; the clock phase and

polarity are programmable

Texas instruments synchronous serial frame format.

Full-duplex, 4-wire synchronous transfer; transmit data line SDOn is 3-stateable when

not transmitting; the chip select line SCSn is always pulsed high for one serial clock

starting at its rising edge, prior to the transmission of each frame; for this frame format

the output data is driven on the rising edge of the SPI clock and latches the data on

the falling edge

National Semiconductors Microwire frame format.

Half-duplex transfer using 8-bit control message; the transmit data line SDOn is

arbitrarily forced logic 0 if inactive; the chip select line SCSn is active logic 0 and is

asserted during the entire frame transmission; continuous transfers keep the chip

select line logic 0; the frame starts with transmitting an 8-bit control message to the

slave device; after this message has been sent, the slave device decodes it and, after

waiting one serial clock after the 8-bit control message has been sent, responds with

the requested data; the returned data can be 4 bits to 16 bits in length, making a total

frame length anywhere from 13 bits to 25 bits

11

reserved; undeﬁned operation

Table 81. SPI data size select conﬁguration

DSS[3:0]

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Function

reserved; undeﬁned operation

4-bit data

5-bit data

6-bit data

7-bit data

8-bit data

9-bit data

10-bit data

11-bit data

12-bit data

13-bit data

14-bit data

15-bit data

16-bit data

8.3.3.5 SPI control register 1 (SSPCR1)

The SPI control register 1 controls several SPI conﬁguration functions.

Table 82 shows the bit assignment of the SSPCR1 register.

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Table 82. SSPCR1 register bit description

Legend: * reset value

Bit

Symbol Access Value Description

31 to 4 reserved

-

reserved; do not modify, read as logic 0, write as logic 0

3

SOD

R/W

slave mode output disable; this bit is relevant only in the

slave mode (bit MS = 1); in multiple slave systems, it is

possible for a master to broadcast a message to all slaves

in the system while ensuring that only one slave drives

data onto its serial output line; to operate in such systems,

the slave output mode bit can be set if the slave is not

supposed to drive the data output line

1

the slave must not drive the data output line SDOn

the slave can drive to data output line SDOn

0*

2

MS

R/W

master or slave mode select; this bit can be modiﬁed only

when the serial port is disabled (bit SSE = 0)

1

the device is conﬁgured as slave

the device is conﬁgured as master

synchronous serial port enable

the serial port is enabled

0*

1

0

SSE

LBM

R/W

1

0*

the serial port is disabled

loop back mode; when logic 1 the output of the transmit

serial shifter is connected to the input of the receive serial

shifter internally; when logic 0, normal serial port operation

is enabled

1

the output of the transmit serial shifter is connected to the

input of the receive serial shifter internally

0*

normal serial port operation is enabled

8.3.3.6 SPI FIFO data register (SSPDR)

The SPI FIFO data register written is 16 bits wide. When read, the data entry in the

receive FIFO is accessed. When written, the data is written to the entry in the transmit

FIFO. When a data size of less than 16 bits is selected, the user must right-justify data

written to the transmit FIFO. The transmit logic ignores unused bits. Received data less

than 16 bits is automatically right-justiﬁed in the receive buffer; unused bits are undeﬁned

and should be discarded.

When programmed for National Semiconductors Microwire frame format, the default size

for transmit data is eight bits. The receive data size is programmable.

The transmit FIFO and the receive FIFO are not cleared even when the serial port enable

bit is set to logic 0. This allows the software to ﬁll the transmit FIFO before enabling the

serial port.

Table 83 shows the bit assignment of the SSPDR register.

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Table 83. SSPDR register bit description

Legend: * reset value

Bit Symbol

31 to 16 reserved

Access Value Description

-

reserved; do not modify, read as logic 0, write as

logic 0

15 to 0 DATA[15:0] R/W

-

transmit or receive FIFO data; when read, data from

the receive FIFO is accessed; when written, data is

written into the transmit FIFO

8.3.3.7 SPI status register (SSPSR)

The SPI status register reﬂects the FIFO status and the serial port busy status.

The SPS register is read only. Table 84 shows the bit assignment of the SPS register.

Table 84. SPSR register bit description

Legend: * reset value

Bit

Symbol Access Value Description

31 to 5 reserved

-

reserved; do not modify, read as logic 0, write as logic 0

busy ﬂag

4

BSY

R

1

the serial port is transmitting and/or receiving a frame or

the transmit FIFO is not empty

0*

the serial port is idle

3

2

1

0

RFF

RNE

TNF

TFE

R

receive FIFO full

1

the receive FIFO is full

the receive FIFO is not full

receive FIFO not empty

the receive FIFO is not empty

the receive FIFO is empty

transmit FIFO not full

0*

1

0*

1*

0

the transmit FIFO is not full

the transmit FIFO is full

transmit FIFO empty

1*

0

the transmit FIFO is empty

the transmit FIFO is not empty

8.3.3.8 SPI clock prescale register (SSPCPSR)

The SPI clock prescale register speciﬁes the system clock frequency prescale division

factor.

Table 85 shows the bit assignment of the SSPCPSR register.

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Table 85. SSPCPSR register bit description

Legend: * reset value

Bit Symbol

31 to 8 reserved

7 to 0 SPSDVSR R/W

Access Value Description

-

reserved; do not modify, read as logic 0, write as logic 0

00h*

clock prescale divisor; the system clock frequency is

divided by the clock prescale value which must be an

even number from 2 to 254; the least signiﬁcant bit

always returns logic 0 on reads

8.3.3.9 SPI interrupt enable register (SSPIMSC)

The SPI interrupt enable register is used to enable the four types of interrupts referred to

in the interrupt status register.

Table 86 shows the bit assignment of the SSPIMSC register.

Table 86. SSPIMSC register bit description

Legend: * reset value

Bit

Symbol Access Value Description

31 to 4 reserved

-

reserved; do not modify, read as logic 0, write as logic 0

transmit FIFO interrupt enable

3

2

1

0

TXIM

R/W

1

the transmit FIFO half empty or less condition interrupt is

not masked

0*

the transmit FIFO half empty or less condition interrupt is

masked

RXIM

RTIM

RORIM

R/W

receive FIFO interrupt enable

1

the receive FIFO half full or less condition interrupt is not

masked

0*

the receive FIFO half full or less condition interrupt is

masked

receive time-out interrupt enable

1

the receive FIFO not empty and no read prior to time-out

period interrupt is not masked

0*

the receive FIFO not empty and no read prior to time-out

period interrupt is masked

receive overrun interrupt enable

1

the receive FIFO written to while full condition interrupt is

not masked

0*

the receive FIFO written to while full condition interrupt is

masked

8.3.3.10 SPI raw interrupt status register (SSPRIS)

The SPI raw interrupt status register reﬂects the raw interrupt status prior to interrupt

masking.

The SSPRIS register is read only. Table 87 shows the bit assignment of the SSPRIS

register.

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Table 87. SSPRIS register bit description

Legend: * reset value

Bit

Symbol Access Value Description

31 to 4 reserved

-

reserved; do not modify, read as logic 0, write as logic 0

transmit FIFO raw interrupt status

3

2

1

0

TXRIS

RXRIS

RTRIS

RORRIS

R

1*

0

the transmit FIFO half empty or less condition interrupt

prior to masking has occurred

R

receive FIFO raw interrupt status

1

the receive FIFO half full or less condition interrupt prior to

masking has occurred

0*

receive time-out raw interrupt status

1

the receive FIFO not empty and no read prior to time-out

period interrupt prior to masking has occurred

0*

receive overrun raw interrupt status

1

the receive FIFO written to while full condition interrupt

prior to masking has occurred

0*

8.3.3.11 SPI masked interrupt status register (SSPMIS)

The SPI masked interrupt status register reﬂects the masked interrupt status.

The SSPMIS register is read only. Table 88 shows the bit assignment of the SSPMIS

register.

Table 88. SSPMIS register bit description

Legend: * reset value

Bit

Symbol Access Value Description

31 to 4 reserved

-

reserved; do not modify, read as logic 0, write as logic 0

transmit FIFO masked interrupt status

3

TXMIS

R

1

the transmit FIFO interrupt enable was set and the

transmit FIFO half empty or less condition interrupt has

occurred

0*

2

1

RXMIS

RTMIS

R

receive FIFO masked interrupt status

1

the receive FIFO interrupt enable was set and the receive

FIFO half full or less condition interrupt has occurred

0*

receive time-out masked interrupt status

1

the receive time-out interrupt enable was set and the

receive FIFO not empty and no read prior to time-out

period interrupt has occurred

0*

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Table 88. SSPMIS register bit description …continued

Legend: * reset value

Bit

Symbol Access Value Description

0

RORMIS

R

receive overrun masked interrupt status

1

the receive FIFO overrun interrupt enable was set and the

receive FIFO written to while full condition interrupt has

occurred

0*

8.3.3.12 SPI interrupt clear register (SSPICR)

The SPI interrupt clear register clears the set raw and masked interrupt status.

The SSPICR register is write only. Table 89 shows the bit assignment of the SSPMICR

register.

Table 89. SSPICR register bit description

Legend: * reset value

Bit

Symbol Access Value Description

31 to 2 reserved

-

reserved; do not modify, read as logic 0, write as logic 0

receive time-out clear interrupt

1

0

RTIC

W

1

0

the raw and masked receive time-out interrupt are cleared

writing logic 0 has no effect

RORIC

W

receive overrun masked interrupt status

1

0

the raw and masked receive FIFO overrun interrupt are

cleared

writing logic 0 has no effect

8.3.4 Watchdog

8.3.4.1 Overview

The purpose of the watchdog is to reset the ARM7 processor within a reasonable amount

of time if it enters an erroneous state. The watchdog will generate a system reset if the

user program fails to trigger the watchdog correctly within a predetermined amount of

time.

The key features are:

• Internally chip reset if not periodically triggered

• Debug mode with interrupt instead of reset

• Watchdog time period change protected with access sequence

• Programmable 32-bit watchdog timer period

The watchdog consists of a 32-bit counter. The clock is directly fed to the timer. The timer

increments when clocked.

The watchdog should be used in the following manner:

• For debugging purposes the watchdog debug mode in the watchdog mode register

should be set before the watchdog has been locked. The debug mode is locked by

programming a new watchdog reload value

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• Enable access to the watchdog reload value register by writing AAAA AAAAh followed

by 5555 5555h

• Program the watchdog timer reload value in watchdog reload value register

• Trigger the watchdog by writing the watchdog trigger register periodically before the

watchdog counter overﬂows

To generate watchdog interrupts in the watchdog debug mode, the interrupt has to be

enabled via the watchdog interrupt status enable register. A watchdog overﬂow interrupt

can be cleared by writing the watchdog interrupt clear status register. In case a watchdog

overﬂow occurred in the watchdog debug mode, clearing the watchdog overﬂow interrupt

is the only way to trigger the watchdog again resulting in restart of counting the

programmed watchdog period. If the watchdog interrupt is not enabled in watchdog debug

mode, the watchdog can be triggered again by writing the watchdog trigger register.

The watchdog is stalled when the AHB clock or the general and peripheral subsystem

clock is stopped for entering power saving modes. In this case the watchdog counter value

is maintained. Therefore, it is recommended to trigger the watchdog before switching off

the AHB clock or the general and peripheral subsystem clock to avoid unexpected

watchdog reset after leaving power savings modes.

A watchdog reset is equal to an external reset: the program counter will start from

0000 0000h and registers are cleared. The clock generation unit contains a watchdog

bark register to distinguish between both events.

8.3.4.2 Watchdog pin description

The watchdog has no external pins.

8.3.4.3 Register mapping

The watchdog registers are shown in Table 90. The watchdog registers have an offset to

the base address WD RegBase which can be found in the memory map (see Table 7).

Table 90. Watchdog register summary

Address Type Reset value

Name

Description

Reference

00h

04h

08

R/W 0h

WDMOD

WDRV

WDCV

WDTRIG

WDISS

WDICS

WDIE

watchdog mode register

watchdog timer reload value

watchdog timer counter value

watchdog trigger

see Table 91

see Table 92

see Table 93

see Table 94

see Table 95

R/W 00FF FFFFh

R/W 0000 0000h

0Ch

10h

14h

18h

1Ch

20h

24h

W

R

-

watchdog interrupt set status

-

watchdog interrupt clear status see Table 96

0h

-

watchdog interrupt enable

watchdog interrupt status

watchdog interrupt set enable

see Table 97

see Table 98

see Table 99

R

WDIS

W

WDISE

WDICE

-

watchdog interrupt clear enable see Table 100

8.3.4.4 Watchdog mode register (WDMOD)

The watchdog debug bit can be set after reset only before the watchdog reload value has

been programmed. After setting this bit, it can always be cleared to enable normal

watchdog operation.

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Table 91 shows the bit assignment of the WDMOD register.

Table 91. WDMOD register bit description

Legend: * reset value

Bit

Symbol

Access Value Description

31 to 4 reserved

-

reserved; do not modify, read as logic 0, write as logic 0

time out ﬂag

3

2

1

WDTOF

R

1

a watchdog time out has occurred in debug mode

0*

WDCEF

R

counter enable ﬂag

1

the watchdog timer is active

the watchdog timer is inactive

debug lock

0*

WDDBLCK

1

the watchdog debug mode has been locked and can not

be entered again; the lock is activated after writing a new

value in watchdog reload value register

0*

0

WDDB

R/W

debug mode

1

a watchdog overﬂow results in an interrupt

0*

a watchdog overﬂow results in a reset; this bit can be

reset any time but only be set when the debug lock is not

active

8.3.4.5 Watchdog reload value register (WDRV)

The watchdog reload value register contains the watchdog value which is reloaded into

the watchdog timer on a trigger. The actual watchdog time period depends on the clock

frequency. The watchdog reload value register is protected against erroneously changing.

Programming a new watchdog value is only accepted after the write sequence

AAAA AAAAh followed by 5555 5555h to this register.

Table 92 shows the bit assignment of the WDRV register.

Table 92. WDRV register bit description

Legend: * reset value

Bit

Symbol

Access Value

Description

31 to 0 WDRV[31:0] R/W

00FF FFFFh* watchdog reload value; reading this register

shows programmed watchdog value

8.3.4.6 Watchdog counter value register (WDCV)

The watchdog counter value register contains the actual watchdog timer counter value.

Table 93 shows the bit assignment of the WDCV register.

Table 93. WDCV register bit description

Legend: * reset value

Bit

Symbol

Access Value

Description

31 to 0 WDCV[31:0]

R

00FF FFFFh* watchdog counter value; reading this register

shows the current value of the watchdog timer

counter

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8.3.4.7 Watchdog trigger register (WDTRIG)

The watchdog trigger register is used to (re)start the watchdog time-out period as

programmed in the watchdog reload value register.

Table 94 shows the bit assignment of the WDTRIG register.

Table 94. WDTRIG register bit description

Legend: * reset value

Bit

31 to 1 reserved

KICKDOG

Symbol

Access Value Description

-

reserved; do not modify, read as logic 0, write as logic 0

watchdog trigger

0

W

1

0

triggers the watchdog resulting in (re)start of counting the

programmed watchdog period

writing logic 0 has no effect

8.3.4.8 Watchdog interrupt set status (WDISS)

The watchdog interrupt set status register sets the bits in the watchdog interrupt status

register.

The WDISS register is write only. Table 95 shows the bit assignment of the WDISS

register.

Table 95. WDISS register bit description

Legend: * reset value

Bit

31 to 1 reserved

INT_SET_STATUS[0]

Symbol

Access Value Description

-

reserved; do not modify, read as write

0

W

1

0

the corresponding bit in the watchdog interrupt

status register is set

the corresponding bit in the watchdog interrupt

status register is unchanged

8.3.4.9 Watchdog interrupt clear status (WDICS)

The watchdog interrupt clear status register clears the bits in the watchdog interrupt status

register.

The WDICS register is write only. Table 96 shows the bit assignment of the WDICS

register.

Table 96. WDICS register bit description

Legend: * reset value

Bit

31 to 1 reserved

INT_CLR_STATUS[0]

Symbol

Access Value Description

-

reserved; do not modify, read as write

0

W

1

0

the corresponding bit in the watchdog interrupt

status register is cleared

the corresponding bit in the watchdog interrupt

status register is unchanged

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8.3.4.10 Watchdog interrupt enable (WDIE)

The watchdog interrupt enable register determines when the watchdog gives an interrupt

request if the corresponding interrupt enable has been set.

The WDIE register is read only. Table 97 shows the bit assignment of the WDIE register.

Table 97. WDIE register bit description

Legend: * reset value

Bit

31 to 1 reserved

OVERFLOW

Symbol

Access Value Description

-

reserved; do not modify, read as logic 0

watchdog overﬂow interrupt enable

0

R

1

bit INT_SET_ENABLE[0] is set to enable the watchdog

overﬂow interrupt

0*

bit INT_CLR_ENABLE[0] is reset to disable the

interrupt

8.3.4.11 Watchdog interrupt status register (WDIS)

The watchdog interrupt status register determines when the watchdog gives an interrupt

request if the corresponding interrupt enable has been set.

The WDIS is read only. Table 98 shows the bit assignment of the WDIS register.

Table 98. WDIS register bit description

Legend: * reset value

Bit

31 to 1 reserved

OVERFLOW

Symbol

Access Value Description

-

reserved; do not modify, read as logic 0

watchdog overﬂow interrupt

0

R

1

a watchdog overﬂow occurred in watchdog debug

mode or logic 1 is written to bit INT_SET_STATUS[0]

0*

no interrupt is pending or logic 1 is written to bit

INT_CLR_STATUS[0]

8.3.4.12 Watchdog interrupt set enable (WDISE)

The watchdog interrupt set enable register sets the bits in the watchdog interrupt enable

register.

The WDISE register is write only. Table 99 shows the bit assignment of the WDISE

register.

Table 99. WDISE register bit description

Legend: * reset value

Bit

31 to 1 reserved

SET_ENABLE[0] W

Symbol

Access Value Description

-

reserved; do not modify, read as write

0

-

1

the corresponding bit in the watchdog interrupt

enable register is set

0

the corresponding bit in the watchdog interrupt

enable register is unchanged

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8.3.4.13 Watchdog interrupt clear enable (WDICE)

The watchdog interrupt clear enable register clears the bits in the watchdog interrupt

status enable register.

The WDICE register is write only. Table 100 shows the bit assignment of the WDICE

register.

Table 100. WDICE register bit description

Legend: * reset value

Bit

31 to 1 reserved

CLR_ENABLE[0]

Symbol

Access Value Description

-

reserved; do not modify, read as write

0

W

-

1

the corresponding bit in the watchdog interrupt

enable register is cleared

0

the corresponding bit in the watchdog interrupt

enable register is unchanged

8.3.5 Analog-to-digital converter

8.3.5.1 Overview

The SJA2020 includes a 10-bit successive approximation analog-to-digital converter.

The basic characteristics of the ADC interface module are:

• Four dedicated analog inputs for eight channels, selected by an analog multiplexer

• Measurement range up to 3.6 V

• 400 ksample/s at 10-bit resolution up to 1500 ksample/s at 2-bit resolution

• Programmable resolution from 2 bits to 10 bits

• Single analog-to-digital conversion scan mode and continuous analog-to-digital

conversion scan mode

• Optional conversion on transition on GPIO pin, external input or timer capture/match

signal

• Converted digital values are stored in a register per channel

• Power-down mode

The ADC clock must be less than half the system clock frequency, but is limited to

4.5 MHz as maximum frequency. The clock generation unit provides a programmable

fractional system clock divider dedicated for the ADC clock to fulﬁl this constraint or to

select the desired lower sampling frequency. The conversion rate is determined by the

ADC clock frequency divided by the number of resolution bits plus one. Accessing ADC

registers requires an enabled ADC clock which is controllable via the clock generation

unit. The analog inputs 0 … 3 are connected to channel 0 … 3 and 4 … 7 respectively.

8.3.5.2 ADC pin description

The ADC has the following pins. Some pins are combined with other functions on the port

pins of the SJA2020, see Section 8.3.2. Table 101 shows the ADC pins.

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Table 101. Analog-to-digital converter pins

Symbol

Direction

Description

VREFN

AI0

IN

ADC low reference level

analog input for channel 0 and channel 4

analog input for channel 1 and channel 5

analog input for channel 2 and channel 6

analog input for channel 3 and channel 7

ADC start trigger 0 input

AI1

AI2

AI3

TR0

TR1

ADC start trigger 1 input

8.3.5.3 Register mapping

The ADC registers are shown in Table 102. The ADC registers have an offset to the base

address ADC RegBase which can be found in the memory map (see Table 7).

Table 102. AD converter register summary

Address Type Reset

value

Name Description

Reference

00h

04h

08h

0Ch

10h

14h

18h

1Ch

20h

24h

28h

2Ch

30h

R

000h

ACD0 ADC channel 0 conversion data register

ACD1 ADC channel 1 conversion data register

ACD2 ADC channel 2 conversion data register

ACD3 ADC channel 3 conversion data register

ACD4 ADC channel 4 conversion data register

ACD5 ADC channel 5 conversion data register

ACD6 ADC channel 6 conversion data register

ACD7 ADC channel 7 conversion data register

ACON ADC control register

see Table 103

see Table 104

see Table 106

see Table 108

see Table 109

see Table 110

R/W 00h

R/W 0000h

R/W 0h

ACC

AIE

AIS

AIC

ADC channel conﬁguration register

ADC interrupt enable register

ADC interrupt status register

ADC interrupt clear register

R

0h

-

W

8.3.5.4 ADC channel conversion data registers (ACD0 to ACD7)

The SJA2020 contains a conversion data register for each of the eight ADC channel

inputs. These eight registers store the result of an analog-to-digital conversion scan

through all active channels. The selected bit resolution in the ADCn (n from 0 to 7)

channel conﬁguration register simultaneously deﬁnes the number of valid most signiﬁcant

conversion data bits in the ADC channel conversion data registers. The remaining

conversion data bits become logic 0 accordingly.

The ACD registers are read only. Table 103 shows the bit assignment of the ACD

registers.

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Table 103. ACD register bit description

Legend: * reset value

Bit

Symbol Access Value Description

31 to 10 reserved

-

reserved; do not modify, read as logic 0, write as logic 0

9 to 0

ACD[9:0]

R

000h* conversion data; the value represents the voltage on the

corresponding channel input pin, divided by the voltage

on the V_DD(ADC)pin

8.3.5.5 ADC control register (ACON)

The ADC control register provides the conﬁguration of ADC operation mode and reﬂects

the analog-to-digital conversion status.

Table 104 shows the bit assignment of the ACON register.

Table 104. ACON register bit description

Legend: * reset value

Bit

31 to 7 reserved

AS

Symbol Access Value Description

-

reserved; do not modify, read as logic 0, write as logic 0

ADC status

6

R

1

the analog-to-digital conversion scan is in progress

the ADC is idle

0*

0h*

5 to 3 ASC[2:0] R/W

ADC scan conﬁguration; see Table 105

ADC scan mode

2

ASM

R/W

1

a repetitive conversion scan is performed after the start

trigger as conﬁgured in the ADC scan conﬁguration bits

(ASC); the ADC conversion data registers are updated

continuously; a continuous scan process is terminated by

clearing the ADC scan mode bit

0*

a single conversion scan is performed after the start trigger

as conﬁgured in the ADC scan conﬁguration; the results

are stored in the ADC conversion data registers

1

0

AEN

R/W

ADC enable

1

the ADC is enabled for conversion scans

0*

the ADC will be switched into low power mode; starting a

new conversion scan is not possible; an ongoing

conversion scan is completed before disabling

reserved

-

reserved; do not modify, read as logic 0, write as logic 0

Table 105. Conversion scan conﬁguration bits

ASC[2:0]

000

Function

ADC in inactive operational mode

start conversion scan through all active channels^[1]

001

010

011

100

start conversion scan through all active channels after rising edge on pin 64

(P2[23]/CAP1[0]/MAT1[0])

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Table 105. Conversion scan conﬁguration bits …continued

ASC[2:0] Function

101

110

111

start conversion scan through all active channels after falling edge on pin 64

(P2[23]/CAP1[0]/MAT1[0])

start conversion scan through all active channels after rising edge on pin 65

(P2[22]/CAP2[0]/MAT2[0])

start conversion scan through all active channels after falling edge on pin 65

(P2[22]/CAP2[0]/MAT2[0])

[1] In single scan conversion mode (ASM = 0), the ASC value should be set to ‘inactive’ as soon as the ADC

conversion is started. This is because in single scan mode, a new conversion will be started according the

trigger condition deﬁned by the ASC bits when the AEN bit is set after the conversion has completed.

8.3.5.6 ADC channel conﬁguration register (ACC)

The ADC channel conﬁguration register deﬁnes which analog input channels are included

during an analog-to-digital conversion scan. Furthermore, the resolution per channel can

be deﬁned from 2 bits to 10 bits.

Table 106 shows the bit assignment of the ACC register.

Table 106. ACC register bit description

Legend: * reset value

Bit

Symbol

Access Value Description

31 to 28

27 to 24

23 to 20

19 to 16

15 to 12

11 to 8

7 to 4

ACC7[3:0]

ACC6[3:0]

ACC5[3:0]

ACC4[3:0]

ACC3[3:0]

ACC2[3:0]

ACC1[3:0]

ACC0[3:0]

R/W

0h*

channel 7 conﬁguration; see Table 107

channel 6 conﬁguration; see Table 107

channel 5 conﬁguration; see Table 107

channel 4 conﬁguration; see Table 107

channel 3 conﬁguration; see Table 107

channel 2 conﬁguration; see Table 107

channel 1 conﬁguration; see Table 107

channel 0 conﬁguration; see Table 107

3 to 0

Table 107. Channel selection and resolution value bits

ACCn[3:0]

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

Function

channel not selected

reserved

2-bit resolution

3-bit resolution

4-bit resolution

5-bit resolution

6-bit resolution

7-bit resolution

8-bit resolution

9-bit resolution

10-bit resolution

reserved

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Table 107. Channel selection and resolution value bits …continued

ACCn[3:0]

Function

reserved

1101

1110

1111

8.3.5.7 ADC interrupt enable register (AIE)

The ADC interrupt enable register contains the enable for the scan interrupt.

Table 108 shows the bit assignment of the AIE register.

Table 108. AIE register bit description

Legend: * reset value

Bit

31 to 1 reserved

ASIE

Symbol Access Value Description

-

reserved; do not modify, read as logic 0, write as logic 0

ADC scan interrupt enable

0

R/W

1

an interrupt is generated if a single conversion scan has

ﬁnished

0*

8.3.5.8 ADC interrupt status register (AIS)

The ADC interrupt status register indicates the presence of the scan interrupt.

The AIS register is read only. Table 109 shows the bit assignment of the AIS register.

Table 109. AIS register bit description

Legend: * reset value

Bit

31 to 1 reserved

ASI

Symbol Access Value Description

-

reserved; read as logic 0

ADC scan interrupt

0

R

1

an interrupt is pending due to a completed conversion

scan

0*

8.3.5.9 ADC interrupt clear register (AIC)

The ADC interrupt clear register provides the mechanism to clear scan interrupt.

The AIC register is write only. Table 110 shows the bit assignment of the AIC register.

Table 110. AIC register bit description

Legend: * reset value

Bit

31 to 1 reserved

ASIC

Symbol Access Value Description

-

reserved; do not modify, write as logic 0

analog-to-digital conversion scan interrupt clear

the scan interrupt ﬂag is cleared

0

W

-

1

0

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8.3.6 Event router

8.3.6.1 Overview

The event router provides bus controlled routing of input events to the vectored interrupt

controller for use as interrupt or wake up signals.

The key features are:

• Input events can be used either directly or latched (edge detected) as interrupt source

• Direct events will disappear when the event becomes inactive

• Latched events will remain active until they are explicitly cleared

• Programmable input level and edge polarity

• Event detection maskable

• Event detection is fully asynchronous, thus no clock is required

The event router allows the event source to be deﬁned, its polarity to be selected, its

activation type to be selected and the interrupt to be masked or enabled. The event router

can be used to start a clock on an external event.

The real-time clock tick interrupt event needs to be captured on the rising edge.

The vectored interrupt controller interrupt inputs are active HIGH.

8.3.6.2 Event router pin description and mapping to register bit positions

The event router module in the SJA2020 is connected to the following pins. The pins are

combined with other functions on the port pins of the SJA2020, see Section 8.3.2.

Table 111 shows the pins connected to the event router. It also shows the corresponding

bit position in the event router registers and the default polarity, see Table 119.

Table 111. Event router pin connections

Symbol

Direction Bit

position

Description

Default polarity,

see Table 119

EXTINT0

EXTINT1

EXTINT2

EXTINT3

IN

0

external interrupt input 0

external interrupt input 1

external interrupt input 2

external interrupt input 3

1

2

3

4

CAN0

RXDC

CAN0 receive data input and wake-up 0

CAN1 receive data input and wake-up 0

CAN2 receive data input and wake-up 0

CAN3 receive data input and wake-up 0

CAN4 receive data input and wake-up 0

CAN5 receive data input and wake-up 0

CAN1

RXDC

IN

5

CAN2

RXDC

6

CAN3

RXDC

7

CAN4

RXDC

8

CAN5

RXDC

9

LIN0 RXDC IN

10

LIN0 receive data input and wake-up

0

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Table 111. Event router pin connections …continued

Symbol

Direction Bit

position

Description

Default polarity,

see Table 119

LIN1 RXDC IN

LIN2 RXDC IN

LIN3 RXDC IN

11

LIN1 receive data input and wake-up

LIN2 receive data input and wake-up

LIN3 receive data input and wake-up

RTC tick event

0

1

12

13

14

15

-

IN

n.a.

CAN interrupt (internal), combined

general interrupt of all CAN

controllers and the CAN look-up

table, see Section 8.5.1.33

-

n.a.

16

17

VIC IRQ (internal)

VIC FIQ (internal)

1

8.3.6.3 Register mapping

The event router registers are shown in Table 112. The event router registers have an

offset to the base address ER RegBase which can be found in the memory map (see

Table 7).

Table 112. Event router register summary

Address Type Reset value

Name

Description

Reference

C00h

C20h

C40h

C60h

C80h

CA0h

CC0h

CE0h

D00h

D20h

R

0 0000h

PEND

event status register

event status clear register

event status set register

event enable register

see Table 113

see Table 114

see Table 115

see Table 116

see Table 117

see Table 118

see Table 119

see Table 120

W

R

-

INT_CLR

INT_SET

MASK

-

3 FFFFh

W

-

MASK_CLR event enable clear register

MASK_SET event enable set register

R/W 3 C00Fh

R/W 3 FFFFh

APR

activation polarity register

activation type register

reserved; do not modify

raw status register

ATR

-

reserved

RSR

R/W 0 0000h

see Table 121

8.3.6.4 Event status register (PEND)

The event status register determines when the event router forwards an interrupt request

to the vectored interrupt controller if the corresponding event enable has been set.

Table 113 shows the bit assignment of the PEND register.

Table 113. PEND register bit description

Legend: * reset value

Bit

Symbol

Access Value Description

31 to 18 reserved

-

reserved; do not modify, read as logic 0, write as

logic 0

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Table 113. PEND register bit description …continued

Legend: * reset value

Bit Symbol

Access Value Description

17 to 0 PEND[17:0] R

1

an event on corresponding pin x has occurred or logic 1

is written to the corresponding bit in the INT_SET

register

0*

no event is pending or logic 1 has been written to the

corresponding bit in the INT_CLR register

8.3.6.5 Event status clear register (INT_CLR)

The event status clear register clears the bits in the event status register.

Table 114 shows the bit assignment of the INT_CLR register.

Table 114. INT_CLR register bit description

Legend: * reset value

Bit

Symbol

Access Value Description

31 to 18 reserved

-

reserved; do not modify, read as logic 0, write as

logic 0

17 to 0 INT_CLR[17:0]

W

-

1

the corresponding bit in the event status register is

cleared

0

the corresponding bit in the event status register is

unchanged

8.3.6.6 Event status set register (INT_SET)

The event status set register sets the bits in the event status register.

Table 115 shows the bit assignment of the INT_SET register.

Table 115. INT_SET register bit description

Legend: * reset value

Bit

Symbol

Access Value Description

31 to 18 reserved

-

reserved; do not modify, read as logic 0, write as

logic 0

17 to 0 INT_SET[17:0]

W

-

1

the corresponding bit in the event status register is

set

0

the corresponding bit in the event status register is

unchanged

8.3.6.7 Event enable register (MASK)

The event enable register determines when the event router sets the event status and

forwards this to the vectored interrupt controller if the corresponding event enable has

been set.

Table 116 shows the bit assignment of the MASK register.

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Table 116. MASK register bit description

Legend: * reset value

Bit Symbol

31 to 18 reserved

Access Value

Description

-

reserved; do not modify, read as logic 0, write as

logic 0

17 to 0 MASK[17:0] R

3 FFFFh* event enable; this bit is set by writing a logic 1 to the

corresponding bit in the MASK_SET register; this bit

is cleared by writing a logic 1 to the corresponding

bit in the MASK_CLR register

1

the event router sets the event status and forwards

the corresponding event to the vectored interrupt

controller

0

the event router masks the event status and does not

forward the corresponding event to the vectored

interrupt controller

8.3.6.8 Event enable clear register (MASK_CLR)

The event enable clear register clears the bits in the event enable register.

Table 117 shows the bit assignment of the MASK_CLR register.

Table 117. MASK_CLR register bit description

Legend: * reset value

Bit

Symbol

Access Value Description

31 to 18 reserved

-

reserved; do not modify, read as logic 0, write as

logic 0

17 to 0 MASK_CLR[17:0]

W

1

0

the corresponding bit in the event enable register

is cleared

the corresponding bit in the event enable register

is unchanged

8.3.6.9 Event enable set register (MASK_SET)

The event enable set register sets the bits in the event enable register.

Table 118 shows the bit assignment of the MASK_SET register.

Table 118. MASK_SET register bit description

Legend: * reset value

Bit

Symbol

Access Value Description

31 to 18 reserved

-

reserved; do not modify, read as logic 0, write as

logic 0

17 to 0 MASK_SET[17:0]

W

-

1

the corresponding bit in the event enable register

is set

0

the corresponding bit in the event enable register

is unchanged

8.3.6.10 Activation polarity register (APR)

The activation polarity register is used to conﬁgure which level is the active state for the

event source.

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Table 119 shows the bit assignment of the APR register.

Table 119. APR register bit description

Legend: * reset value

Bit

Symbol

Access Value

Description

31 to 18 reserved

-

reserved; do not modify, read as logic 0, write as

logic 0

17 to 0 APR[17:0] R/W

3 C00Fh*

1

the corresponding event is high sensitive (HIGH level

or rising edge)

0

the corresponding event is low sensitive (LOW level or

falling edge)

8.3.6.11 Activation type register (ATR)

The activation type register is used to conﬁgure whether an event is used directly or if it is

latched. If it is latched, the interrupt will persist after its event source has become inactive

until it is cleared by an interrupt clear write action. The event router includes an edge

detection circuit which prevents reassertion of an event interrupt if the input remains at the

active level after the latch is cleared. Level sensitive events are expected to be held and

removed by the event source.

Table 120 shows the bit assignment of the ATR register.

Table 120. ATR register bit description

Legend: * reset value

Bit

Symbol

Access Value

Description

31 to 18 reserved

-

reserved; do not modify, read as logic 0, write as

logic 0

17 to 0 ATR[17:0] R/W

3 FFFFh*

1

0

the corresponding event is latched (edge sensitive)

the corresponding event is directly forwarded (level

sensitive)

8.3.6.12 Raw status register (RSR)

The raw status shows unmasked events including latched events. Level sensitive events

are removed by the event source. Edge sensitive events need to be cleared via the event

clear register.

Table 121 shows the bit assignment of the RSR register.

Table 121. RSR register bit description

Legend: * reset value

Bit

Symbol

Access Value

Description

31 to 18 reserved

-

reserved; do not modify, read as logic 0, write as

logic 0

17 to 0 RSR[17:0]

R

0 0000h*

1

0

the corresponding event has occurred

the corresponding event has not occurred

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8.3.7 Real-time clock

8.3.7.1 Overview

The real time clock is driven by a dedicated low power, low frequency crystal oscillator.

Battery backed solutions are enabled by separated voltage domains on-chip.

The key features are:

• Real time and date

• Separate voltage domain to enable separate battery solutions

• Optimized for accurate 32.678 kHz crystal oscillator frequency

• Minute tick for interrupt handling

The real time clock is capable to represent the real time and date via standard C library

functions. Every minute, a tick is generated for interrupt handling purposes.

The real time clock is initialized via an on-chip power-on reset within its own voltage

domain only. Accessing the real-time clock registers requires a running 32 kHz oscillator

and a system clock frequency of at least twice the real time clock frequency. In case of no

RTC supply, the registers content is undeﬁned.

8.3.7.2 RTC pin description

The RTC in the SJA2020 has the following pins, see Table 122.

Table 122. Real time clock pins

Symbol

Direction

IN

Description

XIN_RTC

XOUT_RTC

real time clock crystal input or external clock input

real time clock crystal output

OUT

8.3.7.3 Register mapping

The real-time clock registers are shown in Table 123.

The real-time clock registers have an offset to the base address RTC RegBase which can

be found in the memory map (see Table 7).

Table 123. Real-time clock register summary

Address Type

Reset

value

Name

Description

Reference

000h

010h

020h

FC0h

R

0000 0000h RTC_TIME_SECONDS elapsed time

seconds register

see Table 124

see Table 125

see Table 126

see Table 127

R

0000h

RTC_TIME_FRACTION seconds fraction

register

R/W

0000 0000h RTC_PORTIME

real-time offset

register

1h RTC_CONTROL

real-time control

register

8.3.7.4 RTC elapsed time seconds register (RTC_TIME_SECONDS)

The RTC elapsed time seconds register reﬂects the time in seconds since power-up.

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The RTC_TIME_SECONDS register is read only. Table 124 shows the bit assignment of

the RTC_TIME_SECONDS register.

Table 124. RTC_TIME_SECONDS register bit description

Legend: * reset value

Bit

Symbol

Access Value

Description

31 to 0 RTC_TIME_ SECONDS[31:0]

R

0000 0000h* elapsed time in seconds;

provides the number of

seconds passed after

power-on event occurred

8.3.7.5 RTC seconds fraction register (RTC_TIME_FRACTION)

The RTC seconds fraction register reﬂects the passed number of clock cycles from the

current second. Note that the RTC seconds fraction register is only updated when reading

the RTC elapsed time seconds register.

The RTC_TIME_FRACTION register is read only. Table 125 shows the bit assignment of

the RTC_TIME_FRACTION register.

Table 125. RTC_TIME_FRACTION register bit description

Legend: * reset value

Bit

Symbol

Access Value Description

31 to 15 reserved

-

reserved; read as logic 0

14 to 0 RTC_TIME_ FRACTION[14:0]

R

0000h* seconds fraction register; provides

the fractional part of a second in

clock ticks

8.3.7.6 RTC real time offset register (RTC_PORTIME)

The RTC real time offset register holds the offset to the real time and date. Providing the

offset of power-up time in elapsed seconds since 1 January 1970, standard C libraries can

be used in order to easily access the current time and date.

Table 126 shows the bit assignment of the RTC_PORTIME register.

Table 126. RTC_PORTIME register bit description

Legend: * reset value

Bit

Symbol

Access Value

Description

31 to 0 RTC_PORTIME[31:0] R/W

0000 0000h* real time offset value; contains the real

time offset value in seconds at

power-on event

8.3.7.7 RTC real time control register (RTC_CONTROL)

The RTC real time control register provides the minute tick enable for real time clock

applications.

Table 127 shows the bit assignment of the RTC_CONTROL register.

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Table 127. RTC_CONTROL register bit description

Legend: * reset value

Bit

Symbol

Access Value Description

31

RTC_TICK_ENABLE R/W

real time clock tick enable

the minute tick is inactive

1*

0

the real time clock sends every minute a tick

interrupt request to the event router

30 to 0 reserved

-

reserved; do not modify, read as logic 0,

write as logic 0

8.4 Peripheral subsystem

8.4.1 Timer

8.4.1.1 Overview

Four identical timers are present which are designed to count cycles of the clock and

optionally generate interrupts or perform other actions at speciﬁed timer values, based on

four match registers. They also include capture inputs to trap the timer value when a

transition occurs in an input signal, optionally generating an interrupt

The key features are:

• 32-bit timer/counter with programmable 32-bit prescaler

• Up to four 32-bit capture channels per timer, that take a snapshot of the timer value

when a transition occurs in an input signal; a capture event may also optionally

generate an interrupt

• Four 32-bit match registers per timer that allow:

– Continuous operation with optional interrupt generation on match

– Stop timer on match with optional interrupt generation

– Reset timer on match with optional interrupt generation

• Up to four external outputs per timer corresponding to match registers, with the

following capabilities:

– Set LOW on match

– Set HIGH on match

– Toggle on match

– Do nothing on match

8.4.1.2 Timer pin description

The four timers in the SJA2020 have the following pins. The timer pins are combined with

other functions on the port pins of the SJA2020, see Section 8.3.2. Table 128 shows the

timer pins, x runs from 0 to 3.

Table 128. Timer pins

Symbol

Direction

Description

TIMERx CAP[0]

TIMERx CAP[1]

TIMERx CAP[2]

IN

TIMER x capture input 0

TIMER x capture input 1

TIMER x capture input 2

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Table 128. Timer pins …continued

Symbol

Direction

IN

Description

TIMERx CAP[3]

TIMERx MAT[0]

TIMERx MAT[1]

TIMERx MAT[2]

TIMERx MAT[3]

TIMER x capture input 3

TIMER x match output 0

TIMER x match output 1

TIMER x match output 2

TIMER x match output 3

OUT

8.4.1.3 Register mapping

The timer registers are shown in Table 129. The timer registers have an offset to the base

address TMR RegBase which can be found in the memory map (see Table 7).

Table 129. Timer register summary

Address

00h

Type Reset value

R/W 00h

Name

IR

Description

Reference

timer interrupt register

timer control register

timer counter value

prescale register

see Table 130

see Table 131

see Table 132

see Table 133

see Table 134

see Table 135

see Table 136

see Table 137

see Table 138

see Table 139

04h

R/W 0h

TCR

TC

08h

R/W 0000 0000h

R/W 000h

0Ch

10h

PR

PC

prescale counter value

match control register

match register 0

14h

MCR

MR0

MR1

MR2

MR3

CCR

CR0

CR1

CR2

CR3

EMR

18h

R/W 0000 0000h

R/W 000h

1Ch

20h

match register 1

match register 2

24h

match register 3

28h

capture control register

capture register 0

capture register 1

capture register 2

capture register 3

external match register

2Ch

30h

R

0000 0000h

34h

38h

3Ch

R/W 000h

8.4.1.4 Timer interrupt register (IR)

The timer interrupt register consists of 4 bits for the interrupts on the match register

matches and 4 bits for the interrupts on capture events. If an interrupt is being generated,

then the corresponding bit in the timer interrupt register will be logic 1. Otherwise, the bit

will be logic 0. Writing a logic 1 to the corresponding timer interrupt register bit will reset

the interrupt. Writing logic 0 has no effect. Writing a logic 1 instead of logic 0 allows to

write the contents of the interrupt register to itself thus providing a quick method of

clearing.

An interrupt is generated if one of the match registers matches the contents of the timer

counter and the interrupt is enabled through the match control register or the concerned

capture input satisﬁes one of the conditions in the capture control register and the

interrupts are enabled via the capture control register.

Table 130 shows the bit assignment of the IR register.

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Table 130. IR register bit description

Legend: * reset value

Bit Symbol

31 to 8 reserved

Access Value Description

-

reserved; do not modify, read as logic 0, write as logic 0

7

6

5

4

3

2

1

0

INTR_C3 R/W

INTR_C2 R/W

INTR_C1 R/W

INTR_C0 R/W

INTR_M3 R/W

INTR_M2 R/W

INTR_M1 R/W

INTR_M0 R/W

0*

interrupt bit for a CR3 load on capture 3 event; writing

logic 1 clears the interrupt ﬂag

0*

interrupt bit for a CR2 load on capture 2 event; writing

logic 1 clears the interrupt ﬂag

interrupt bit for a CR1 load on capture 1 event; writing

logic 1 clears the interrupt ﬂag

interrupt bit for a CR0 load on capture 0 event; writing

logic 1 clears the interrupt ﬂag

interrupt bit for a MR3 and TC match; writing logic 1

clears the interrupt ﬂag

interrupt bit for a MR2 and TC match; writing logic 1

clears the interrupt ﬂag

interrupt bit for a MR1 and TC match; writing logic 1

clears the interrupt ﬂag

interrupt bit for a MR0 and TC match; writing logic 1

clears the interrupt ﬂag

8.4.1.5 Timer control register (TCR)

The timer control register maintains 2 bits which are used to control the operation of the

timer counter. Bit COUNTER_ENABLE switches on and off the timer and prescale

counter. Bit COUNTER_RESET clears the timer and prescale counter.

Table 131 shows the bit assignment of the TCR register.

Table 131. TCR register bit description

Legend: * reset value

Bit

Symbol

Access Value Description

31 to 2 reserved

-

reserved; do not modify, read as logic 0,

write as logic 0

1

0

COUNTER_ RESET R/W

COUNTER_ ENABLE R/W

0*

reset timer and prescale counter; if this bit is

set, the counters remain reset until this bit is

cleared again

0*

enable timer and prescale counter; if this bit

is set, the counters are running

8.4.1.6 Timer counter (TC)

The timer counter represents the timer count value which is incremented every prescale

cycle.

Table 132 shows the bit assignment of the TC register.

Table 132. TC register bit description

Legend: * reset value

Bit

Symbol Access Value

TC[31:0] R/W

Description

31 to 0

0000 0000h* timer counter; it is advised not to access this

register

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8.4.1.7 Prescale register (PR)

The prescale register determines the number of clock cycles as prescale value for the

timer counter clock.

Table 133 shows the bit assignment of the PR register.

Table 133. PR register bit description

Legend: * reset value

Bit

Symbol Access Value

Description

31 to 0 PR[31:0] R/W

0000 0000h* prescale register; this register speciﬁes the

maximum value for the prescale counter

8.4.1.8 Prescale counter (PC)

The prescale counter represents the prescale count value which is incremented every

clock cycle.

Table 134 shows the bit assignment of the PC register.

Table 134. PC register bit description

Legend: * reset value

Bit

Symbol Access Value

Description

31 to 0 PC[31:0]

R

0000 0000h* prescale counter; this register reﬂects the prescale

counter value

8.4.1.9 Match control register (MCR)

Each match register can be conﬁgured through the match control register to stop both the

timer counter and prescale counter thus maintaining their value at the time of the match,

to restart the timer counter at logic 0, to allow the counters to continue counting and/or

generate an interrupt when its contents match those of the timer counter. A stop on match

has higher priority than reset on match.

An interrupt is generated if one of the match registers matches the contents of the timer

counter and the interrupt is enabled through the match control register.

The match control register is used to control what operations are performed when one of

the match registers matches the timer counter.

Table 135 shows the bit assignment of the MCR register.

Table 135. MCR register bit description

Legend: * reset value

Bit

Symbol

Access Value Description

31 to 12 reserved

-

reserved; do not modify, read as logic 0, write as

logic 0

11

STOP_3

R/W

stop on match MR3 and TC

1

the timer and prescale counter stop counting and bit

COUNTER_ENABLE will be cleared if MR3 matches

TC

0*

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Table 135. MCR register bit description …continued

Legend: * reset value

Bit

Symbol

Access Value Description

10

RESET_3 R/W

reset on match MR3 and TC

1

the timer counter is reset if MR3 matches TC

0*

9

8

INTR_3

R/W

interrupt on match MR3 and TC

1

an interrupt is generated if MR3 matches TC

0*

STOP_2

stop on match MR2 and TC

1

the timer and prescale counter stop counting and bit

COUNTER_ENABLE will be cleared if MR2 matches

TC

0*

7

6

5

RESET_2 R/W

reset on match MR2 and TC

1

the timer counter is reset if MR2 matches TC

0*

INTR_2

R/W

interrupt on match MR2 and TC

1

an interrupt is generated if MR2 matches TC

0*

STOP_1

stop on match MR1 and TC

1

the timer and prescale counter stop counting and bit

COUNTER_ENABLE will be cleared if MR1 matches

TC

0*

4

3

2

RESET_1 R/W

reset on match MR1 and TC

1

the timer counter is reset if MR1 matches TC

0*

INTR_1

R/W

interrupt on match MR1 and TC

1

an interrupt is generated if MR1 matches TC

0*

STOP_0

stop on match MR0 and TC

1

the timer and prescale counter stop counting and bit

COUNTER_ENABLE will be cleared if MR0 matches

TC

0*

1

0

RESET_0 R/W

reset on match MR0 and TC

1

the timer counter is reset if MR0 matches TC

0*

INTR_0

R/W

interrupt on match MR0 and TC

1

an interrupt is generated if MR0 matches TC

0*

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8.4.1.10 Match registers (MR0 to MR3)

The match registers determine the timer counter match value. Four match registers are

available per timer.

Table 136 shows the bit assignment of the MRn registers, n from 0 to 3.

Table 136. MR register bit description

Legend: * reset value

Bit

Symbol Access Value

Description

31 to 0 MR[31:0] R/W

0000 0000h* match register; this register speciﬁes the match

value for the timer counter

8.4.1.11 Capture control register (CCR)

The capture control register is used to control when one of the possible four capture

registers is loaded with the value in the timer counter and if an interrupt is generated,

when the capture occurs.

A rising edge is detected if the sequence of logic 0 followed by logic 1 is found. A falling

edge is detected if the sequence of logic 1 followed by logic 0 is found. The capture

control register maintains 2 bits for each of the counter registers to allow the sequence

detection to be enabled for each of the capture registers. If the enabled sequence is

detected, the timer counter value is loaded in the capture register. If enabled through the

capture control register, then an interrupt is generated. Setting both the rising and falling

bits at the same time is a valid conﬁguration.

A reset clears the CCR register.

Table 137 shows the bit assignment of the CCR register.

Table 137. CCR register bit description

Legend: * reset value

Bit

Symbol

Access Value Description

31 to 12 reserved

-

reserved; do not modify, read as logic 0, write as logic 0

interrupt on capture event by input 3

11

10

EVENT_3 R/W

1

a CR3 load due to a capture event on input 3 will

generate an interrupt

0*

FALL_3

RISE_3

R/W

capture on capture input 3 falling

1

a sequence of logic 1 followed by logic 0 from capture

input 3 will cause CR3 to be loaded with the contents of

TC

0*

1

9

capture on capture input 3 rising

a sequence of logic 0 followed by logic 1 from capture

input 3 will cause CR3 to be loaded with the contents of

TC

0*

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Table 137. CCR register bit description …continued

Legend: * reset value

Bit

Symbol

Access Value Description

8

EVENT_2 R/W

interrupt on capture event by input 2

1

a CR2 load due to a capture event on input 2 will

generate an interrupt

0*

7

6

FALL_2

RISE_2

R/W

capture on capture input 2 falling

1

a sequence of logic 1 followed by logic 0 from capture

input 2 will cause CR2 to be loaded with the contents of

TC

0*

1

capture on capture input 2 rising

a sequence of logic 0 followed by logic 1 from capture

input 2 will cause CR2 to be loaded with the contents of

TC

0*

5

4

EVENT_1 R/W

interrupt on capture event by input 1

1

a CR1 load due to a capture event on input 1 will

generate an interrupt

0*

FALL_1

RISE_1

R/W

capture on capture input 1 falling

1

a sequence of logic 1 followed by logic 0 from capture

input 1 will cause CR1 to be loaded with the contents of

TC

0*

1

3

capture on capture input 1 rising

a sequence of logic 0 followed by logic 1 from capture

input 1 will cause CR1 to be loaded with the contents of

TC

0*

2

1

EVENT_0 R/W

interrupt on capture event by input 0

1

a CR0 load due to a capture event on input 0 will

generate an interrupt

0*

FALL_0

RISE_0

R/W

capture on capture input 0 falling

1

a sequence of logic 1 followed by logic 0 from capture

input 0 will cause CR0 to be loaded with the contents of

TC

0*

1

0

capture on capture input 0 rising

a sequence of logic 0 followed by logic 1 from capture

input 0 will cause CR0 to be loaded with the contents of

TC

0*

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8.4.1.12 Capture registers (CR0 to CR3)

The capture registers are loaded with the timer counter value when there is an event on

the concerned capture input. Four capture registers are available per timer.

Table 138 shows the bit assignment of the CRn registers, n from 0 to 3.

Table 138. CR register bit description

Legend: * reset value

Bit

Symbol Access Value

Description

31 to 0 CR[31:0]

R

0000 0000h* capture register; this register reﬂects after a

capture event the timer counter captured value

8.4.1.13 External match register (EMR)

The external match register provides both control and status of the external match pins.

The external match ﬂags and the match outputs can either toggle, go logic 0, go logic 1 or

maintain state when the contents of match register is equal to the contents of timer

counter. Writing directly to external match bits is allowed to change the level of the ﬂags

and outputs.

Table 139 shows the bit assignment of the EMR register.

Table 139. EMR register bit description

Legend: * reset value

Bit

Symbol

Access Value Description

31 to 12 reserved

-

reserved; do not modify, read as logic 0, write as

logic 0

11 to 10 CTRL_3[1:0]

R/W

0h*

0*

external match control 3; see Table 140

external match control 2; see Table 140

external match control 1; see Table 140

external match control 0; see Table 140

9 to 8

7 to 6

5 to 4

3

CTRL_2[1:0]

CTRL_1[1:0]

CTRL_0[1:0]

EMR_3

external match 3; when MR3 matches TC, the

external match ﬂag 3 can either toggle, go logic 0, go

logic 1, or do nothing; bit CTRL_3 controls the

functionality of this output; this bit can also be driven

onto the match output 3 in a positive-logic manner

(logic 0 = LOW, logic 1 = HIGH)

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Table 139. EMR register bit description …continued

Legend: * reset value

Bit

Symbol

Access Value Description

2

EMR_2

R/W

0*

external match 2; when MR2 matches TC, the

external match ﬂag 2 can either toggle, go logic 0, go

logic 1, or do nothing; bit CTRL_2 controls the

functionality of this output; this bit can also be driven

onto the match output 2 in a positive-logic manner

(logic 0 = LOW, logic 1 = HIGH)

1

0

EMR_1

EMR_0

external match 1; when MR1 matches TC, the

external match ﬂag 1 can either toggle, go logic 0, go

logic 1, or do nothing; bit CTRL_1 controls the

functionality of this output; this bit can also be driven

onto the match output 1 in a positive-logic manner

(logic 0 = LOW, logic 1 = HIGH)

external match 0; when MR0 matches TC, the

external match ﬂag 0 can either toggle, go logic 0, go

logic 1, or do nothing; bit CTRL_0 controls the

functionality of this output; this bit can also be driven

onto the match output 0 in a positive-logic manner

(logic 0 = LOW, logic 1 = HIGH)

Table 140. External match control bit description

CTRL_n[1:0]

Function

do nothing

set logic 0

set logic 1

toggle

00

01

10

11

8.4.2 UART

8.4.2.1 Overview

The UART is commonly used to implement a serial interface such as an RS232. The

SJA2020 contains an industry standard 550 UART with 16-byte transmit and receive

FIFOs, but can also be put into 450 mode without FIFOs.

The key features are:

• 16-byte receive and transmit FIFOs

• Register locations conform to 550 industry standard

• Receiver FIFO trigger points at 1 byte, 4 bytes, 8 bytes and 14 bytes

• Built-in baud rate generator

Note that each LIN controller has also a standard 450 UART without FIFOs.

8.4.2.2 UART pin description

The UART in the SJA2020 have the following pins. The UART pins are combined with

other functions on the port pins of the SJA2020, see Section 8.3.2. Table 141 shows the

UART pins.

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Table 141. UART pins

Symbol

Direction

OUT

Description

UARTx TXD

UARTx RXD

UART channel x transmit data output

UART channel x receive data input

IN

8.4.2.3 Register mapping

The UART registers are shown in Table 143.

The UART registers have an offset to the base address UART RegBase which can be

found in the memory map (see Table 7).

Some UART registers are dependent on the setting of bit DLAB, see Table 150.

Table 142. UART register summary

Address Bit

Type Reset Name

value

Description

Reference

00h

DLAB = 0 R

-

RBR

THR

DLL

IER

DLM

IIR

receiver buffer register

transmit holding register

divisor latch LSB register

interrupt enable register

divisor latch MSB register

interrupt ID register

see Table 143

see Table 144

see Table 155

see Table 145

see Table 156

see Table 146

see Table 148

see Table 150

W

DLAB = 1 R/W 01h

DLAB = 0 R/W 0h

DLAB = 1 R/W 00h

04h

08h

R

01h

00h

W

FCR

LCR

-

FIFO control register

0Ch

10h

14h

18h

1Ch

R/W 00h

line control register

[1]

-

R

-

60h

-

LSR

-

line status register

see Table 153

see Table 154

[1]

R/W 00h

SCR

scratch register

[1] Reserved for future expansion; write all logic 0 only.

8.4.2.4 Receive buffer register (RBR)

The receive buffer register is the top byte of the receive FIFO. The top byte of the receive

FIFO contains the oldest character received and can be read via the bus interface. In 450

mode, received data is passed from the receive shift register to the top byte of the receive

buffer register, essentially producing an 1-byte Rx FIFO. The least signiﬁcant bit

represents the oldest received data bit. If the character received is less than 8 bits, the

unused most signiﬁcant bits are padded with logic 0.

The RBR register is read only and the divisor latch access bit DLAB must be logic 0 for

access.

Table 143 shows the bit assignment of the RBR register.

Table 143. RBR register bit description

Legend: * reset value

Bit

31 to 8 reserved

7 to 0 RBR[7:0]

Symbol

Access Value Description

-

reserved; read as logic 0

R

receive buffer register; contains the oldest

received byte in the receive FIFO

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8.4.2.5 Transmit holding register (THR)

The transmit holding register is the top byte of the transmit FIFO. The top byte is the

newest character in the transmit FIFO and can be written via the bus interface. In 450

mode, data is passed from the THR to the transmit shift register, essentially producing a

1-byte transmit FIFO. The least signiﬁcant bit represents the ﬁrst bit to transmit.

The THR register is write only and the divisor latch access bit DLAB must be logic 0 for

access. Table 144 shows the bit assignment of the THR register.

Table 144. THR register bit description

Legend: * reset value

Bit

31 to 8 reserved

7 to 0 THR[7:0]

Symbol Access Value Description

-

reserved; do not modify, write as logic 0

W

transmit holding register; writing to the transmit holding

register causes the data to be stored in the transmit FIFO;

the byte will be sent when it reaches the bottom of the

FIFO and the transmitter is available

8.4.2.6 Interrupt enable register (IER)

The interrupt enable register is used to enable the four types of interrupts referred to in the

interrupt identiﬁcation register. The divisor latch access bit DLAB must be logic 0 in order

to access the IER register.

Table 145 shows the bit assignment of the IER register.

Table 145. IER register bits

Legend: * reset value

Bit

Symbol Access Value Description

31 to 3 reserved

-

reserved; do not modify, read as logic 0, write as logic 0

receiver line status interrupt enable

2

1

0

LSIE

R/W

1

the receive line status interrupt is enabled

0*

TBEIE

RBIE

R/W

transmit holding register empty interrupt enable

1

the transmit holding register empty interrupt is enabled

0*

receive buffer register interrupt register enable

the receive data available interrupt is enabled

1

0*

8.4.2.7 Interrupt ID register (IIR)

The interrupt ID register provides a status code that denotes the priority and source of a

pending interrupt. When an interrupt is generated, the interrupt ID register indicates that

an interrupt is pending and encodes the type in its three least signiﬁcant bits. The

interrupts are frozen during an access to the interrupt ID register. If an interrupt occurs

during an access, the interrupt is recorded for the next interrupt ID register access.

The IIR register is read only.

Table 146 shows the bit assignment of the IIR register.

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Table 146. IIR register bit description

Legend: * reset value

Bit Symbol

31 to 8 reserved

Access Value Description

-

reserved; read as logic 0

7

FIFO_ EN

R

0*

FIFOs enabled; represents FIFO enable bit of the FIFO

control register; in 450 mode this bit is always logic 0

6

FIFO_ EN

R

0*

FIFOs enabled; represents FIFO enable bit of the FIFO

control register; in 450 mode this bit is always logic 0

5 to 4

3 to 0

reserved

-

reserved; read as logic 0

INT_ID[3:0]

R

1h*

interrupt identiﬁcation; see Table 147

Table 147. Interrupt identiﬁcation conﬁguration bits

INT_ID[3:0] Priority level Interrupt

Type

Source

Reset method

0001

0110

none

1

none

receiver line

status

overrun error, parity error,

framing error, or break

interrupt

read line status

register

0100

1100

2

received data

available

receiver data available in

450 mode or trigger level

reached in 550 mode

read receive buffer

register

character time-out no characters have been

indication

read receive buffer

register

removed from or input to

receiver FIFO during the last

four character times, and

there is at least one

character in it during this

time

0010

3

transmitter

holding register

empty

transmit holding register

empty

read interrupt ID

register (if source

of interrupt) or

writing into

transmitterholding

register

8.4.2.8 FIFO control register (FCR)

The FIFO control register enables and clears the FIFOs, sets the receiver FIFO level, and

selects the type of DMA signalling.

The FCR register is write only.

Table 148 shows the bit assignment of the FCR register.

Table 148. FCR register bit description

Legend: * reset value

Bit

31 to 8 reserved

7 to 6 REV_TRIG[1:0] W

Symbol

Access Value Description

-

reserved; do not modify, write as logic 0

0h*

trigger level for receiver FIFO interrupt; see

Table 149

5 to 4 reserved

-

reserved; write as logic 0

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Table 148. FCR register bit description …continued

Legend: * reset value

Bit

Symbol

Access Value Description

3

DMA_M

W

DMA mode

1

when logic 1 and in FIFO mode, multiple character

transfers are performed until the transmitter FIFO is

ﬁlled or the receiver FIFO is empty; the receiver

direct memory access becomes active when the

receive FIFO trigger level is reached or a character

time-out occurred

0*

1

only single character transfers are done as default in

450 mode

2

1

0

TX_FIFO_R

RX_FIFO_R

FIFO_EN

W

transmitter FIFO reset

when logic 1 and in FIFO mode, all bytes in the

transmitter FIFO and the transmitter FIFO pointer

are cleared; the shift register is not cleared; the

transmitter FIFO reset bit is self clearing

0*

1

receiver FIFO reset

when logic 1 and in FIFO mode, all bytes in the

receiver FIFO and the receiver FIFO pointer are

cleared; the shift register is not cleared; the receiver

FIFO reset bit is self clearing

0*

1

the transmitter and receiver FIFOs are enabled and

the UART operates in FIFO mode; the FIFO enable

bit must be set when other FIFO control register bits

are written to or they are not programmed; changing

this bit clears the FIFOs

0*

the UART operates in 450 mode

Table 149. Receiver trigger level conﬁguration bits

REV_TRIG [1:0] Function

00

01

10

11

receiver FIFO contains 1 byte

receiver FIFO contains 4 bytes

receiver FIFO contains 8 bytes

receiver FIFO contains 14 bytes

8.4.2.9 Line control register (LCR)

The line control register controls the format of the asynchronous data communication

exchange.

Table 150 shows the bit assignment of the LCR register.

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Table 150. LCR register bit description

Legend: * reset value

Bit

Symbol Access Value Description

31 to 8 reserved

-

reserved; do not modify, read as logic 0, write as logic 0

divisor latch access bit

7

DLAB

R/W

1

the divisor latch registers of the baud rate generator can be

accessed

0*

the receiver buffer register, the transmit holding register,

and the interrupt enable register can be accessed

6

BC

R/W

break control

1

a break transmission condition is forced which puts the

TXD output to LOW

0*

the break transmission condition is disabled; the break

condition has no affect on the transmitter logic; it only

affects the TXD line

5 to 4 PS[1:0]

R/W

0h*

1

parity select; see Table 151

parity enable

3

PEN

a parity bit is generated in transmitted data between the

last data word bit and the ﬁrst stop bit; in received data the

parity is checked

0*

1

2

STB

R/W

number of stop bits

the number of generated stop bits are 2; except the word

length is 5 bits, then 1.5 stop bits are generated

0*

only 1 stop bit is generated

1 to 0 WLS[1:0] R/W

0h*

word length select; see Table 152

Table 151. Parity select conﬁguration bits

PS [1:0]

00

Function

odd parity: an odd number of logic 1 in the data and parity bits

even parity: an even number of logic 1 in the data and parity bits

forced logic 1 stick parity

01

10

11

forced logic 0 stick parity

Table 152. Word length conﬁguration bits

WLS [1:0]

Function

00

01

10

11

5-bit character length

6-bit character length

7-bit character length

8-bit character length

8.4.2.10 Line status register (LSR)

The line status register provides the information concerning the data transfers.

The LSR register is read only.

Table 153 shows the bit assignment of the LSR register.

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Table 153. LSR register bit description

Legend: * reset value

Bit

Symbol Access Value Description

31 to 8 reserved

-

reserved; read as logic 0

error in receiver FIFO

7

RXFE

R

1

the receiver FIFO contains at least one parity, framing, or

break error; in 450 mode the error in receiver FIFO bit is

always cleared

0*

1*

6

TEMT

R

transmitter empty

the transmitter holding register, transmitter FIFO and the

transmitter shift register are both empty; the transmitter

empty bit is cleared when either the transmitter holding

register or the transmitter shift register contains a data

character

0

5

THRE

transmitter holding register empty

1*

the transmitter holding register or transmitter FIFO is

empty; if the transmitter holding register empty interrupt

enable is set, an interrupt is generated; the transmitter

holding register empty bit is set when the contents of the

transmitter holding register is transferred to the transmitter

shift register; the transmitter holding register empty bit is

cleared concurrently with loading the transmitter holding

register or transmitter FIFO

0

1

4

BI

R

break interrupt

the received data input was held low for longer than a

full-word transmission time; a full-word transmission time is

deﬁned as the total time to transmit the start, data, parity,

and stop bits; the break interrupt bit is cleared upon

reading; in FIFO mode, this error is associated with the

particular character in the receiver FIFO to which it applies;

this error is revealed when its associated character is at the

top of the receiver FIFO; when a break occurs, only one

logic 0 is loaded into the receiver FIFO; the UART tries to

resynchronize after a framing error; to accomplish this, it is

assumed that the framing error is due to the next start bit;

the UART samples this start bit twice and then accepts the

input data

0*

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Table 153. LSR register bit description …continued

Legend: * reset value

Bit

Symbol Access Value Description

3

FE

R

framing error

1

the received character did not have a valid (set) stop bit;

the framing error is cleared upon Ring; in FIFO mode, this

error is associated with the particular character in the

receiver FIFO to which it applies; this error is revealed

when its associated character is at the top of the receiver

FIFO; when a break occurs, only one logic 0 is loaded into

the receiver FIFO; the next character transfer is enabled

after the RXD input line goes to the marking state (all

logic 1) for at least two sample times and then receives the

next valid start bit

0*

1

2

PE

R

parity error

the parity of the received data character does not match

the parity selected in the line control register; the parity

error is cleared upon reading; in FIFO mode, this error is

associated with the particular character in the receiver

FIFO to which it applies; this error is revealed when its

associated character is at the top of the receiver FIFO

0*

1

OE

R

overrun error

the character in the receiver buffer register was overwritten

by the next character transferred into this register before it

was read; the overrun error is cleared upon reading; if the

FIFO mode data continues to ﬁll the receiver FIFO beyond

the trigger level, an overrun error occurs only after the

receiver FIFO is full and the next character has been

completely received in the shift register; an overrun error is

signalled as soon it happens; the character in the shift

register is overwritten, but not transferred to the receiver

FIFO

0*

1

0

DR

R

data ready

a complete incoming character has been received and

transferred to the receiver buffer register or the receiver

FIFO; the data ready bit is cleared by reading all of the data

in the receiver buffer register or the receiver FIFO

0*

8.4.2.11 Scratch register (SCR)

The scratch register is intended for the programmer’s use as scratch pad in the sense that

it temporarily holds the programmer’s data without affecting any other UART operation.

Table 154 shows the bit assignment of the SCR register.

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Table 154. SCR register bit description

Legend: * reset value

Bit

Symbol Access Value Description

31 to 8 reserved

-

reserved; do not modify, write as logic 0, read as logic 0

7 to 0 SCR[7:0] R/W

00h*

scratch register; this register can be written and/or read at

user’s discretion

8.4.2.12 Divisor latch LSB and divisor latch MSB registers (DLL and DLM)

The two divisor latch registers store the divisor in 16-bit binary format for the

programmable baud generator. The output frequency of the baud generator is 16 times

the baud rate. The input frequency of the baud generator is the system clock frequency

divided by the divisor value. A written value of 0000h into the divisor will be treated like

value 0001h.

The divisor latch access bit DLAB must be set in order to access the DLL and DLM

register.

Table 155 and Table 156 show the bit assignment of respective the DLL and DLM register.

Table 155. DLL register bits

Legend: * reset value

Bit

Symbol Access Value Description

31 to 8 reserved

7 to 0 DLL

-

reserved; do not modify, write as logic 0, read as logic 0

R/W

01h*

divisor latch LSB register; the divisor latch LSB register

contains the lower byte of the 16-bit divisor

Table 156. DLM register bits

Legend: * reset value

Bit

Symbol Access Value Description

31 to 8 reserved

7 to 0 DLM

-

reserved; do not modify, write as logic 0, read as logic 0

R/W

00h*

divisor latch MSB register; the divisor latch MSB register

contains the higher byte of the 16-bit divisor

8.4.3 General purpose I/O

8.4.3.1 Overview

Three general purpose I/O ports provide individual control over each bidirectional port pin.

There are two registers to control the I/O direction and output level. The inputs are

synchronized to achieve stable read levels. The I/O pad behavior depends on the

conﬁguration programmed in the I/O pad multiplex register.

The key features are:

• General purpose parallel inputs and outputs

• Direction control of individual bits

• Synchronized input sampling for stable input data values

• All I/O defaults to input at reset to avoid any possible bus conﬂicts

To generate an open-drain output, set the bit in the output register to the desired value.

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Use the direction register to control the signal. When set to output, the output driver will

actively drive the value on the output; when set to input, the signal is ﬂoating and can be

pulled externally.

8.4.3.2 GPIO pin description

The three GPIO ports in the SJA2020 have the following pins. The GPIO pins are

combined with other functions on the port pins of the SJA2020, see Section 8.3.2.

Table 158 shows the GPIO pins.

Table 157. GPIO pins

Symbol

Direction

IN/OUT

Description

GPIO0 pin[31:0]

GPIO1 pin[31:0]

GPIO2 pin[29:0]

GPIO port 0, pins 31 to 0

GPIO port 1, pins 31 to 0

GPIO port 2, pins 29 to 0

8.4.3.3 Register mapping

The general purpose I/O registers have an offset to the base address GPIO RegBase

which can be found in the memory map (see Table 7).

The general purpose I/O registers are shown in Table 158.

Table 158. General purpose I/O register summary

Address Type Reset value Name

Description

Reference

0h

4h

8h

R

-

PINS

port input register

port output register

port direction register

see Table 159

see Table 160

see Table 161

R/W 0000 0000h OR

R/W 0000 0000h DR

8.4.3.4 Port input register (PINS)

The port input register is used to reﬂect the synchronized input level on each I/O pin

individually. In case of writing to the port input register, the contents is written into the port

output register.

Table 159 shows the bit assignment of the PINS register.

Table 159. PINS register bit description

Legend: * reset value

Bit

Symbol

Access Value Description

31 to 0 PINS[31:0] R/W

-

port input value; bit 0 corresponds to pin Pn[0], etc.; if a

input pin is HIGH, then the respective bit is logic 1 and

if a input pin is LOW, then the respective bit is logic 0

8.4.3.5 Port output register (OR)

The port output register is used to deﬁne the output level on each I/O pin individually in

case this pin is conﬁgured as output by the port direction register. If the port input register

is written, the port output register is written.

Table 160 shows the bit assignment of the OR register.

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Table 160. OR register bits

Legend: * reset value

Bit

Symbol Access Value

Description

31 to 0 OR[31:0] R/W

0000 0000h* port output value; bit 0 corresponds to pin Pn[0],

etc.; if conﬁgured as output, then a logic 1 drives the

respective port to HIGH

8.4.3.6 Port direction register (DR)

The port direction register is used to control each I/O pin output driver enable individually.

Table 161 shows the bit assignment of the DR register.

Table 161. DR register bit

Legend: * reset value

Bit

Symbol Access Value

Description

31 to 0 DR[31:0] R/W

0000 0000h* port direction control; bit 0 corresponds to pin Pn[0],

etc.; if the bit is logic 1, then the respective port pin is

conﬁgured as output

8.5 In-vehicle networking subsystem

8.5.1 CAN

8.5.1.1 Overview

Controller Area Network (CAN) is the deﬁnition of a high performance communication

protocol for serial data communication. The six CAN controllers in the SJA2020 provide a

full implementation of the CAN protocol according to the CAN speciﬁcation version 2.0B.

The gateway concept is fully scalable with the number of CAN controllers and always

operates together with a separated powerful and ﬂexible hardware acceptance ﬁlter.

The key features are:

• Supports 11-bit identiﬁer as well as 29-bit identiﬁer

• Double receive buffer and triple transmit buffer

• Programmable error warning limit and error counters with read/write access

• Arbitration lost capture and error code capture with detailed bit position

• Single shot transmission (no re-transmission)

• Listen only mode (no acknowledge, no active error ﬂags)

• Reception of ‘own’ messages (self reception request)

8.5.1.2 CAN pin description

The six CAN controllers in the SJA2020 have the following pins. The CAN pins are

combined with other functions on the port pins of the SJA2020, see Section 8.3.2.

Table 162 shows the CAN pins, x runs from 0 to 5.

Table 162. CAN pins

Symbol

Direction

OUT

Description

CANx TXDC

CANx RXDC

CAN channel x transmit data output

CAN channel x receive data input

IN

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8.5.1.3 Register mapping

The CAN registers are shown in Table 163.

The CAN registers have an offset to the CAN base addresses which can be found in the

memory map (see Table 7).

Table 163. CAN register summary

Address Type Reset value Name

CAN controller; CANC RegBase offset

Description

Reference

00h

04h

R/W 01h

00h

CCMODE

CCCMD

CAN controller mode register

see Table 164

see Table 165

W

CAN controller command

register

08h

0Ch

10h

14h

18h

R/W 0000 003Ch CCGS

0000 0000h CCIC

CAN controller global status

register

see Table 166

see Table 167

R

CAN controller interrupt and

capture register

R/W 000h

R/W 1C 0000h

R/W 60h

CCIE

CAN controller interrupt enable see Table 170

register

CCBT

CAN controller bus timing

register

see Table 171

CCEWL

CCSTAT

CAN controller error warning

limit register

see Table 172

1Ch

20h

R

3C 3C3Ch

CAN controller status register

see Table 173

see Table 174

R/W 0000 0000h CCRXBMI

R/W 0000 0000h CCRXBID

R/W 0000 0000h CCRXBDA

R/W 0000 0000h CCRXBDB

R/W 0000 0000h CCTXB1MI

R/W 0000 0000h CCTXB1ID

CAN controller receive buffer

message info register

24h

28h

2Ch

30h

34h

38h

3Ch

40h

44h

48h

4Ch

50h

CAN controller receive buffer

identiﬁer register

see Table 175

see Table 176

see Table 177

CAN controller receive buffer

data A register

CAN controller receive buffer

data B register

CAN controller transmit buffer 1 see Table 178

message info register

CAN controller transmit buffer 1 see Table 179

identiﬁer register

R/W 0000 0000h CCTXB1DA CAN controller transmit buffer 1 see Table 180

data A register

R/W 0000 0000h CCTXB1DB CAN controller transmit buffer 1 see Table 181

data B register

R/W 0000 0000h CCTXB2MI

CAN controller transmit buffer 2 see Table 178

message info register

R/W 0000 0000h CCTXB2ID

CAN controller transmit buffer 2 see Table 179

identiﬁer register

R/W 0000 0000h CCTXB2DA CAN controller transmit buffer 2 see Table 180

data A register

R/W 0000 0000h CCTXB2DB CAN controller transmit buffer 2 see Table 181

data B register

R/W 0000 0000h CCTXB3MI

CAN controller transmit buffer 3 see Table 178

message info register

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Table 163. CAN register summary …continued

Address Type Reset value Name

Description

Reference

54h

58h

5Ch

R/W 0000 0000h CCTXB3ID

CAN controller transmit buffer 3 see Table 179

identiﬁer register

R/W 0000 0000h CCTXB3DA CAN controller transmit buffer 3 see Table 180

data A register

R/W 0000 0000h CCTXB3DB CAN controller transmit buffer 3 see Table 181

data B register

CAN ID-look-up table memory; CANAFM RegBase offset

000h to

7FCh

R/W

-

CAFMEM

CAN ID-look-up table memory

see Table 182

see Table 189

CAN acceptance ﬁlter; CANAFR RegBase offset

00h

R/W 1h

CAMODE

CAN acceptance ﬁlter mode

register

04h

R/W 000h

CASFESA

CAN acceptance ﬁlter standard see Table 190

frame explicit start address

register

08h

0Ch

10h

R/W 000h

CASFGSA

CAEFESA

CAEFGSA

CAN acceptance ﬁlter standard see Table 191

frame group start address

register

CAN acceptance ﬁlter extended see Table 192

frame explicit start address

register

CAN acceptance ﬁlter extended see Table 193

frame group start address

register

14h

18h

1Ch

CAEOTA

CALUTEA

CALUTE

CAN acceptance ﬁlter end of

table address register

see Table 194

see Table 195

see Table 196

R

000h

0h

CAN acceptance ﬁlter look-up

table error address register

CAN acceptance ﬁlter look-up

table error register

CAN central status; CANCS RegBase offset

0h

4h

8h

R

3F 3F3Fh

00 003Fh

0000h

CCCTS

CCCRS

CCCMS

CAN controllers central transmit see Table 197

status register

CAN controllers central receive see Table 198

status register

CAN controllers central

see Table 199

miscellaneous status register

The following CAN controller register tables have a soft reset mode value besides the

reset value:

• A hardware reset overrules the soft reset mode

• If no soft reset value is speciﬁed the content is unchanged by the soft reset mode

• Bit ﬁelds with ‘X’ means that the content is unchanged upon setting the soft reset

mode

The reset value shows the result of hardware reset, while the soft reset mode value

indicates the result when the RM bit is set either by software or due to a bus-off condition.

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8.5.1.4 CAN controller mode register (CCMODE)

The CAN controller mode register is used to change the behavior of the CAN controller.

Table 164 shows the bit assignment of the CCMODE register.

Table 164. CCMODE register bit description

Legend: * reset value

Bit

Symbol

Access Value Soft reset

mode value

Description

31 to 6 reserved

-

reserved; do not modify, read as logic 0,

write as logic 0

5

RPM ^[1]

R/W

X

reverse polarity mode

1

0*

-

RXDC and TXDC pins are HIGH for a

dominant bit

RXDC and TXDC pins are LOW for a

dominant bit

4

3

reserved

TPM ^[1][2]

-

reserved; do not modify, read as logic 0,

write as logic 0

R/W

X

transmit priority mode

1

the priority depends on the contents of

the transmit priority register within the

transmit buffer

0*

the transmit priority depends on the CAN

identiﬁer

2

STM ^[1]

R/W

X

self test mode; this bit is only writable in

soft reset mode

1

the controller will consider a transmitted

message successful if there is no

acknowledgment; use this state in

conjunction with the self reception

request bit in the CAN controller

command register

0*

a transmitted message must be

acknowledged to be considered

successful

1

LOM ^[1][3]

R/W

X

listen only mode; this bit is only writable

in soft reset mode

1

the controller gives no acknowledgment

on CAN, even if a message is

successfully received; messages cannot

be sent, and the controller operates in

error passive mode

0*

the CAN controller acknowledges a

successfully-received message

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Table 164. CCMODE register bit description …continued

Legend: * reset value

Bit

Symbol

Access Value Soft reset

mode value

Description

0

RM ^[4][5]

R/W

1

soft reset mode

1*

0

soft reset mode active; CAN operation is

disabled, and writable registers can be

written. Bits having a soft reset mode

value are being reset.

soft reset mode inactive; the CAN

controller in normal operation and certain

registers can not be written

[1] A write access to the RPM, TPM, STM and LOM registers is possible only if the soft reset mode is entered

previously.

[2] In cases where the same transmit priority or the same ID is chosen for more than one buffer, then the

transmit buffer with the lowest buffer number is sent ﬁrst.

[3] This mode of operation forces the CAN controller to be error passive. Message transmission is not possible.

[4] During a hardware reset or when the bus status bit is set 1 (bus-off), the soft reset mode bit is set 1

(present). After the soft reset mode bit is set 0 the CAN controller will wait for:

a) One occurrence of bus-free signal (11 recessive bits), if the preceding reset has been caused by a

Hardware reset or a CPU-initiated reset.

b) 128 occurrences of bus-free, if the preceding reset has been caused by a CAN controller initiated

bus-off, before re-entering the bus-on mode.

[5] When entering soft reset mode, it is not possible to access any other register within the same instruction.

8.5.1.5 CAN controller command register (CCCMD)

The CAN controller command register initiates an action within the transfer layer of the

CAN controller.

The CCCMD register is write only. Table 165 shows the bit assignment of the CCCMD

register.

Table 165. CCCMD register bit description

Legend: * reset value

Bit

Symbol

Access Value Soft reset

mode value

Description

31 to 8 reserved

-

reserved; do not modify, read as logic 0,

write as logic 0

7

6

5

STB3

STB2

STB1

W

-

select transmit buffer 3; when logic 1,

transmit buffer 3 is selected for

transmission

W

-

select transmit buffer 2; when logic 1,

transmit buffer 2 is selected for

transmission

select transmit buffer 1; when logic 1,

transmit buffer 1 is selected for

transmission

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Table 165. CCCMD register bit description …continued

Legend: * reset value

Bit

Symbol

Access Value Soft reset

mode value

Description

4

SRR ^[1][2][3]

W

-

self reception request; when logic 1, a

message shall be transmitted from the

selected transmit buffer and received

simultaneously; transmission and self

reception request has to be set

simultaneously with STB3, STB2 or

STB1

3

CDO

W

-

clear data overrun; when logic 1, the

data overrun bit in the CAN controller

status register is cleared; this command

bit is used to clear the Data Overrun

condition signalled by the Data Overrun

Status bit; as long as the Data Overrun

Status bit is set no further Data Overrun

Interrupt is generated

2

1

RRB ^[4]

W

-

release receive buffer; when logic 1, the

receive buffer, representing the

message memory space in the double

receive buffer is released

AT ^[5][3]

abort transmission; when logic 1, if not

already in progress, a pending

transmission request is cancelled; if the

abort transmission and transmit request

bits are set in the same write operation,

frame transmission is attempted once

and no retransmission is attempted if an

error is ﬂagged nor if arbitration is lost

0

TR ^[2][6][3]

W

-

transmission request; when logic 1, a

message from the selected transmit

buffer is queued for transmission

[1] Upon self reception request a message is transmitted and simultaneously received if the acceptance ﬁlter is

set to the corresponding identiﬁer. A receive and a transmit interrupt will indicate correct self reception (see

also self test mode in mode register).

[2] It is possible to select more than one message buffer for transmission. If more than one buffer is selected

for transmission (TR = 1 or SRR = 1) the internal transmit message queue is organized such as that

depending on the Transmit Priority Mode (TPM) the transmit buffer with the lowest CAN identiﬁer (ID) or the

lowest ‘local priority’ (TXPRIO) wins the prioritization and is sent ﬁrst.

[3] Setting the command bits TR and AT simultaneously results in transmitting a message once. No

re-transmission will be performed in case of an error or arbitration lost (single shot transmission). Setting

the command bits SRR and AT simultaneously results in sending the transmit message once using the

self-reception feature. No re-transmission will be performed in case of an error or arbitration lost. Setting the

command bits TR, AT and SRR simultaneously results in transmitting a message once as described for TR

and AT. The moment the transmit status bit is set within the status register, the internal transmission request

bit is cleared automatically. Setting TR and SRR simultaneously will ignore the set SRR bit.

[4] After reading the contents of the receive buffer, the CPU can release this memory space by setting the

release receive buffer bit to 1. This may result in another message becoming immediately available. If there

is no other message available, the receive interrupt bit is reset. If the RRB command is given, it will take at

least 2 internal clock cycles before a new interrupt is generated.

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[5] The abort transmission bit is used when the CPU requires the suspension of the previously requested

transmission, e.g. to transmit a more urgent message before. A transmission already in progress is not

stopped. In order to see if the original message has been either transmitted successfully or aborted, the

transmission complete status bit should be checked. This should be done after the Transmit Buffer Status

bit has been set 1 or a transmit interrupt has been generated.

[6] If the transmission request or the self-reception request bit was set 1 in a previous command, it cannot be

cancelled by resetting the bits. The requested transmission may only be cancelled by setting the abort

transmission bit.

8.5.1.6 CAN controller global status register (CCGS)

The CAN controller global status register reﬂects the global status of the CAN controller

including the transmit and receive error counter values.

Table 166 shows the bit assignment of the CCGS register.

Table 166. CCGS register bit description

Legend: * reset value

Bit

Symbol

Access Value Soft reset

mode value

Description

31 to TXERR[7:0] R/W

24

00h*

X

transmit error counter; this register

reﬂects the current value of the transmit

error counter; this register is only writable

in soft reset mode; if a bus off event

occurs, the transmit error counter is

initialized to 127 to count the minimum

protocol-deﬁned time (128 occurrences

of the bus free signal); reading the

transmit error counter during this time

gives information about the status of the

bus off recovery; if bus off is active, a

write access to transmit error counter in

the range of 0 to 254 clears the bus off

ﬂag and the controller will wait for one

occurrence of 11 consecutive recessive

bits (bus free) after clearing of soft reset

mode bit

23 to RXERR[7:0] R/W

16

00h*

X

receive error counter; this register

reﬂects the current value of the receive

error counter; this register is only writable

in soft reset mode; if a bus off event

occurs, the receive error counter is

initialized to 00h; as long as the bus off

condition is valid, writing to this register

has no effect

15 to reserved

8

-

reserved; do not modify, read as logic 0,

write as logic 0

7

BS ^[1]

R

0

bus status

1

the CAN controller is currently prohibited

from bus activity because the transmit

error counter reached its limiting value of

FFh

0*

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Table 166. CCGS register bit description …continued

Legend: * reset value

Bit

Symbol

Access Value Soft reset

mode value

Description

6

ES ^[2]

R

0

error status

1

one or both of the transmit and receive

error counters has reached the limit set in

the error warning limit register

0*

5

4

3

TS ^[3]

R

1

X

transmit status

1*

0

the CAN controller is transmitting a

message

RS ^[3]

receive status

1*

0

the CAN controller is receiving a

message

TCS ^[4]

transmission complete status

1*

0

all requested message transmissions

have been successfully completed

at least one of the previously requested

transmission is not yet completed

2

1

0

TBS

R

1

0

transmit buffer status

1*

0

all transmit buffers are available for the

CPU

at least one of the transmit buffers

contains a previously queued message

that has not yet been sent

DOS ^[5]

data overrun status

1

a message was lost because the

preceding message to this CAN

controller was not read and released

quickly enough

0*

1

no data overrun has occurred

receive buffer status

RBS ^[6]

at least one complete message is

available in the double receive buffer; this

bit is cleared by the release receive buffer

command in the CAN controller

command register if no subsequent

received message is available

0*

no message is available in the double

receive buffer

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[1] When the transmit error counter exceeds the limit of 255, the bus status bit is set 1 (bus-off), the CAN

controller will set the soft reset mode bit to 1 (present) and an error warning interrupt is generated, if

enabled. Afterwards the transmit error counter is set to ‘127’ and the receive error counter is cleared. It will

stay in this mode until the CPU clears the soft reset mode bit. Once this is completed the CAN controller will

wait the minimum protocol-deﬁned time (128 occurrences of the bus-free signal) counting down the transmit

error counter. After that the bus status bit is cleared (bus-on), the error status bit is set 0 (ok), the error

counters are reset and an error warning interrupt is generated, if enabled. Reading the TX error counter

during this time gives information about the status of the bus-off recovery.

[2] Errors detected during reception or transmission will affect the error counters according to the CAN

speciﬁcation. The error status bit is set when at least one of the error counters has reached or exceeded

the error warning Limit. An error warning interrupt is generated, if enabled. The default value of the error

warning limit after hardware reset is 96 decimal, see also CCEWL register bits.

[3] If both the receive status and the transmit status bits are 0 (idle) the CAN-bus is idle. If both bits are set the

controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be

detected until idle status is reached. After bus-off this will take 128 times of 11 consecutive recessive bits.

[4] The transmission complete status bit is set 0 (incomplete) whenever the transmission request bit or the self

reception request bit is set 1 at least for one of the three transmit buffers. The transmission complete status

bit will remain 0 until all messages are transmitted successfully.

[5] If there is not enough space to store the message within the receive buffer, that message is dropped and

the data overrun condition is signalled to the CPU in the moment this message becomes valid. If this

message is not completed successfully (e.g. because of an error), no overrun condition is signalled.

[6] After reading all messages and releasing their memory space with the command ‘release receive buffer’

this bit is cleared.

8.5.1.7 CAN controller interrupt and capture register (CCIC)

The CAN controller interrupt and capture register allows the identiﬁcation of an interrupt

source. Reading the interrupt register clears all interrupt bits except the receive interrupt

bit which requires release receive buffer command. If there is another message available

within the receive buffer after the release receive buffer command, the receive interrupt is

set again. Otherwise the receive interrupt keeps cleared.

Bus errors are captured in a detailed error report. When a transmitted message loses

arbitration, the bit where the arbitration has lost is captured. Once either of these registers

is captured, its value will remain the same until it is read, at which time it is released to

capture a new value.

The CCIC register is read only. Table 167 shows the bit assignment of the CCIC register.

Table 167. CCIC register bit description

Legend: * reset value

Bit

Symbol

Access Value Soft reset

mode value

Description

31 to 29 reserved

-

reserved; do not modify, read as

logic 0

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Table 167. CCIC register bit description …continued

Legend: * reset value

Bit Symbol

Access Value Soft reset

mode value

Description

28 to 24 ALCBIT[4:0]

R

00h*

X

arbitration lost bit; in case the

arbitration is lost while transmitting a

message, the bit number within the

frame is captured into this register)

00h*

arbitration lost in the ﬁrst, most

signiﬁcant bit of the identiﬁer

:

0Bh

11: arbitration lost in SRTR bit (RTR bit

for standard frame messages)

0Ch

12: arbitration lost in IDE bit 13:

arbitration lost in 12th bit of identiﬁer

(extended frame only)

:

1Eh

30: arbitration lost in last bit of

identiﬁer (extended frame only)

0Fh

0h*

31: arbitration lost in RTR bit

(extended frames only)

23 to 22 ERRT[1:0]

21 ERRDIR

R

X

error type; the bus error type is

captured in this register; see Table 168

error direction

1

he bus error is captured during

receiving

0*

the bus error is captured during

transmitting

20 to 16 ERRCC[4:0]

15 to 11 reserved

R

00h*

X

error code capture; the location of the

error within the frame is captured in

this register; see Table 169

-

reserved; do not modify, read as

logic 0, write as logic 0

10

TI3

TI2

IDI

R

0

transmit interrupt 3

1

the transmit buffer status 3 is released

(transition from logic 0 to logic 1) and

the transmit interrupt enable 3 is set

0*

1

9

R

0

transmit interrupt 2

the transmit buffer status 2 is released

(transition from logic 0 to logic 1) and

the transmit interrupt enable 2 is set

0*

8

ID ready interrupt

1

a CAN identiﬁer has been received

and the ID ready interrupt enable is set

0*

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Table 167. CCIC register bit description …continued

Legend: * reset value

Bit

Symbol

Access Value Soft reset

mode value

Description

7

BEI

R

X

0

bus error interrupt

1

a CAN controller has detected a bus

error and the bus error interrupt enable

is set

0*

1

6

5

ALI

EPI

arbitration lost interrupt

the CAN controller has lost arbitration

while attempting to transmit and the

arbitration lost interrupt enable is set

0*

1

error passive interrupt

the CAN controller has reached the

error passive status (at least one error

counter exceeds the CAN protocol

deﬁned level of 127) or if the CAN

controller is in error passive status and

enters the error active status again

and the error passive interrupt enable

is set

0*

-

4

3

reserved

DOI

-

reserved; read as logic 0

data overrun interrupt

R

0

1

the data overrun occurred and the data

overrun interrupt enable is set

0*

2

1

0

EWI

TI1

R

X

0

error warning interrupt

1

a change of either the error status or

bus status occurred and the error

warning interrupt enable is set

0*

1

transmit interrupt 1

the transmit buffer status 1 is released

(transition from logic 0 to logic 1) and

the transmit interrupt enable 1 is set

0*

RI ^[1]

receive interrupt

1

the receive buffer status is logic 1 and

the receive interrupt enable is set

0*

[1] The receive interrupt bit is not cleared upon a read access to the interrupt register. Giving the command

‘release receive buffer’ will clear RI temporarily. If there is another message available within the receive

buffer after the release command, RI is set again. Otherwise RI keeps cleared.

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Table 168. Bus error type values

ERRT[1:0]

Function

bit error

00

01

10

11

form error

stuff error

other error

Table 169. Bus error capture code values

ERRCC [4:0]

0 0000

0 0001

0 0010

0 0011

0 0100

0 0101

0 0110

0 0111

0 1000

0 1001

0 1010

0 1011

0 1100

0 1101

0 1110

0 1111

1 0000

1 0001

1 0010

1 0011

1 0100

1 0101

1 0110

1 0111

1 1000

1 1001

1 1010

1 1011

1 1100

1 1101

1 1110

1 1111

Function

reserved

identiﬁer bits 21 to 28

start of frame

standard frame RTR bit

IDE bit

reserved

identiﬁer bits 13 to 17

CRC sequence

reserved bit 0

data ﬁeld

data length code

extended frame RTR bit

reserved bit 1

identiﬁer bits 0 to 4

identiﬁer bits 5 to 12

reserved

active error ﬂag

intermission

tolerate dominant bits

reserved

passive error ﬂag

error delimiter

CRC delimiter

acknowledge slot

end of frame

acknowledge delimiter

overload ﬂag

reserved

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8.5.1.8 CAN controller interrupt enable register (CCIE)

The CAN controller interrupt enable register allows enabling the different types of CAN

controller interrupts.

Table 170 shows the bit assignment of the CCIE register.

Table 170. CCIE register bit description

Legend: * reset value

Bit

Symbol

Access Value Soft reset

mode value

Description

31 to 11 reserved

-

reserved; do not modify, read as logic 0,

write as logic 0

10

TI3E

TI2E

R/W

X

transmit interrupt enable 3

1

an interrupt is generated if the transmit

buffer status 3 is released (transition from

logic 0 to logic 1)

0*

1

9

R/W

X

transmit interrupt enable 2

an interrupt is generated if the transmit

buffer status 2 is released (transition from

logic 0 to logic 1)

0*

8

7

6

IDIE

BEIE

ALIE

R/W

X

ID ready interrupt enable

1

an interrupt is generated if a CAN

identiﬁer has been received

0*

bus error interrupt enable

1

an interrupt is generated if a CAN

controller has detected a bus error

0*

arbitration lost interrupt enable

1

an interrupt is generated if the CAN

controller has lost arbitration while

attempting to transmit

0*

1

5

EPIE

R/W

X

error passive interrupt enable

an interrupt is generated if the CAN

controller has reached the error passive

status (at least one error counter

exceeds the CAN protocol deﬁned level

of 127) or if the CAN controller is in error

passive status and enters the error active

status again

0*

-

4

reserved

-

reserved; do not modify, read as logic 0,

write as logic 0

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Table 170. CCIE register bit description …continued

Legend: * reset value

Bit

Symbol

Access Value Soft reset

mode value

Description

3

DOIE

R/W

X

data overrun interrupt enable

1

an interrupt is generated if the data

overrun occurred

0*

2

1

0

EWIE

TIE1

RIE

R/W

X

error warning interrupt enable

1

an interrupt is generated if a change of

either the error status or bus status

occurred

0*

1

R/W

X

transmit interrupt enable 1

an interrupt is generated if the transmit

buffer status 1 is released (transition from

logic 0 to logic 1)

0*

receive interrupt enable

1

an interrupt is generated if the receive

buffer is not empty

0*

8.5.1.9 CAN controller bus timing register (CCBT)

The CAN controller bus timing register deﬁnes the timing characteristics of the CAN bus.

The bus timing register is only writable in soft reset mode.

Table 171 shows the bit assignment of the CCBT register.

Table 171. CCBT register bit description

Legend: * reset value

Bit

31 to 24 reserved

23 SAM

Symbol

Access Value Soft reset

mode value

Description

-

reserved; do not modify, read as

logic 0, write as logic 0

R/W

X

1

the bus is sampled three times;

recommended for low/medium speed

buses, where ﬁltering spikes on the

bus-line is beneﬁcial

0*

the bus is sampled once;

recommended for high speed buses

22 to 20 TSEG2[2:0]

19 to 16 TSEG1[3:0]

R/W

1h*

X

timing segment 2; time segment after

the sample point which is determined

by the formula of ^[1]

Ch*

timing segment 1; time segment

before the sample point which is

determined by the formula of ^[2]

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Table 171. CCBT register bit description …continued

Legend: * reset value

Bit Symbol

Access Value Soft reset

mode value

Description

15 to 14 SJW[1:0]

13 to 10 reserved

R/W

0h*

X

synchronization jump width; the

synchronization jump length is

determined by the formula of ^[3]

-

reserved; do not modify, read as

logic 0, write as logic 0

9 to 0

BRP[9:0]

R/W

000h*

X

baud rate prescaler; the baud rate

prescaler derives the CAN clock t_scl

from the system clock f_clk(sys); the

CAN controller clock period is

calculated by the formula of ^[4]

[1] t_seg2= t_scl× (TSEG2 + 1)

[2] t_seg1= t_scl× (TSEG1 + 1)

[3] t_SJW= t_scl× (SJW + 1)

BRP + 1

f _clk(sys)

[4] t_scl

=

--------------------

8.5.1.10 CAN controller error warning limit register (CCEWL)

The CAN controller error warning limit register sets the limit on the transmit or receive

errors at which an interrupt can occur. This register is only writable in soft reset mode.

Table 172 shows the bit assignment of the CCEWL register.

Table 172. CCEWL register bit description

Legend: * reset value

Bit

Symbol Access Value Soft reset

mode value

Description

31 to 8 reserved

-

reserved; do not modify, read as logic 0,

write as logic 0

7 to 0 EWL[7:0] R/W

60h*

X

error warning limit; during CAN operation,

this value is compared to both the transmit

and receive error counters; if either of

these counters matches this value, the

error status bit is set

8.5.1.11 CAN controller status register (CCSTAT)

The CAN controller status register reﬂects the transmit status of all three transmit buffers

including the global status of the CAN controller.

The CCSTAT register is read only. Table 173 shows the bit assignment of the CCSTAT

register.

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Table 173. CCSTAT register bit description

Legend: * reset value

Bit Symbol

Access Value Soft reset

mode value

Description

31 to 24 reserved

-

reserved; do not modify, read as logic 0,

write as logic 0

23

22

BS

ES

R

0

bus status

1

the CAN controller is currently

prohibited from bus activity because the

transmit error counter reached its

limiting value of FFh

0*

1

R

0

error status

one or both of the transmit and receive

error counters has reached the limit set

in the error warning limit register

0*

21

20

19

TS3

R

1

X

transmit status 3

1*

0

the CAN controller is transmitting a

message from transmit buffer 3

RS

receive status

1*

0

the CAN controller is receiving a

message

TCS3 ^[1]

transmission complete status 3

1*

0

the last requested message

transmissions from transmit buffer 3 has

been successfully completed

the previously requested transmission is

not yet completed

18

17

TBS3 ^[2]

R

1

0

transmit buffer status 3

1*

0

transmit buffer 3 is available for the CPU

transmit buffer 3 contains a previously

queued message that has not yet been

sent

DOS

data overrun status

1

a message was lost because the

preceding message to this CAN

controller was not read and released

quickly enough

0*

no data overrun has occurred

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Table 173. CCSTAT register bit description …continued

Legend: * reset value

Bit

Symbol

Access Value Soft reset

mode value

Description

16

RBS

R

0

receive buffer status

1

at least one complete message is

available in the double receive buffer;

this bit is cleared by the release receive

buffer command in the CAN controller

command register if no subsequent

received message is available

0*

1

no message is available in the double

receive buffer

15

14

BS

ES

R

0

bus status

the CAN controller is currently

prohibited from bus activity because the

transmit error counter reached its

limiting value of FFh

0*

1

error status

one or both of the transmit and receive

error counters has reached the limit set

in the error warning limit register

0*

13

12

11

TS2

R

1

X

transmit status 2

1*

0

the CAN controller is transmitting a

message from transmit buffer 2

RS

receive status

1*

0

the CAN controller is receiving a

message

TCS2 ^[1]

transmission complete status 2

1*

0

the requested message transmission

from transmit buffer 2 has been

successfully completed

the previously requested transmission

from transmit buffer 2 is not yet

completed

10

TBS2 ^[2]

R

1

transmit buffer status 2

1*

0

transmit buffer 2 is available for the CPU

transmit buffer 2 contains a previously

queued message that has not yet been

sent

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Table 173. CCSTAT register bit description …continued

Legend: * reset value

Bit

Symbol

Access Value Soft reset

mode value

Description

9

DOS

R

0

data overrun status; when logic 1, a

message was lost because the

preceding message to this CAN

controller was not read and released

quickly enough; when logic 0, no data

overrun has occurred

1

a message was lost because the

preceding message to this CAN

controller was not read and released

quickly enough

0*

1

no data overrun has occurred

receive buffer status

8

RBS

R

0

at least one complete message is

available in the double receive buffer;

this bit is cleared by the release receive

buffer command in the CAN controller

command register if no subsequent

received message is available

0*

1

no message is available in the double

receive buffer

7

6

BS

ES

R

0

bus status

the CAN controller is currently

prohibited from bus activity because the

transmit error counter reached its

limiting value of FFh

0*

1

error status

one or both of the transmit and receive

error counters has reached the limit set

in the error warning limit register

0*

5

4

3

TS1

R

1

X

transmit status 1

1*

0

the CAN controller is transmitting a

message from transmit buffer 1

RS

receive status

1*

0

the CAN controller is receiving a

message

TCS1 ^[1]

transmission complete status 1

1*

0

the requested message transmission

from transmit buffer 1 has been

successfully completed

the previously requested transmission

from transmit buffer 1 is not yet

completed

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Table 173. CCSTAT register bit description …continued

Legend: * reset value

Bit

Symbol

Access Value Soft reset

mode value

Description

2

TBS1 ^[2]

R

1

transmit buffer status

1*

0

transmit buffer 1 is available for the CPU

transmit buffer 1 contains a previously

queued message that has not yet been

sent

1

0

DOS

RBS

R

0

data overrun status

1

a message was lost because the

preceding message to this CAN

controller was not read and released

quickly enough

0*

1

no data overrun has occurred

receive buffer status

R

0

at least one complete message is

available in the double receive buffer;

this bit is cleared by the release receive

buffer command in the CAN controller

command register if no subsequent

received message is available

0*

no message is available in the double

receive buffer

[1] The transmission complete status bit is set 0 (incomplete) whenever the transmission request bit or the self

reception request bit is set 1 for this TX buffer. The transmission complete status bit will remain 0 until a

message is transmitted successfully.

[2] If the CPU tries to write to this transmit buffer when the transmit buffer status bit is 0 (locked), the written

byte will not be accepted and will be lost without this being signalled.

8.5.1.12 CAN controller receive buffer message info register (CCRXBMI)

The CAN controller receive buffer message info register reﬂects the characteristics of the

received message. This register is read only.

Table 174 shows the bit assignment of the CCRXBMI register.

Table 174. CCRXBMI register bit description

Legend: * reset value

Bit

Symbol

Access Value Soft reset

mode value

Description

31

FF

R

X

frame format

1

an extended frame format message

has been received

0*

a standard frame format message

has been received

30

RTR

R

-

X

-

remote frame request

1

0*

-

a remote frame has been received

a data frame has been received

29 to 20 reserved

reserved; do not modify, read as

logic 0, write as logic 0

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Table 174. CCRXBMI register bit description …continued

Legend: * reset value

Bit Symbol

Access Value Soft reset

mode value

Description

19 to 16 DLC[3:0]

R

0h*

X

data length code; this register

contains the number of data bytes

received in case bit RTR is logic 0 or

the requested number of data bytes

in case bit RTR is logic 1; values

larger than eight are handled as eight

data bytes

15 to 11 reserved

-

reserved; do not modify, read as

logic 0, write as logic 0

10

BP

R

X

bypass mode

1

the message was received in the

acceptance ﬁlter bypass mode which

makes the identiﬁer index ﬁeld

meaningless

0*

9 to 0

IDI[9:0]

R

000h*

X

identiﬁer index; in case bit BP is not

set, this register contains the

zero-based number of the look-up

table entry at which the acceptance

ﬁlter matched the received identiﬁer;

disabled entries in the standard

tables are included in this numbering,

but will not be considered for ﬁltering

8.5.1.13 CAN controller receive buffer identiﬁer register (CCRXBID)

The CAN controller receive buffer identiﬁer register contains the identiﬁer ﬁeld of the

received message. This register is read only.

Table 175 shows the bit assignment of the CCRXBID register.

Table 175. CCRXBID register bit description

Legend: * reset value

Bit

Symbol Access Value

Soft reset

Description

mode value

31 to 29 reserved

28 to 0 ID[28:0]

-

reserved; do not modify, read as

logic 0, write as logic 0

R

0000 0000h*

X

identiﬁer; this register contains the

identiﬁer of received CAN message;

in case a standard frame format has

been received, the least signiﬁcant

11 bits represent the 11-bit identiﬁer

8.5.1.14 CAN controller receive buffer data A register (CCRXBDA)

The CAN controller receive buffer data A register contains the ﬁrst four data bytes of the

received message. This register is read only.

Table 176 shows the bit assignment of the CCRXBDA register.

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Table 176. CCRXBDA register bit description

Legend: * reset value

Bit

Symbol Access Value Soft reset

Description

mode value

31 to 24 DB4[7:0]

R

00h*

X

data byte 4; if the data length code value

is four or more, this register contains the

fourth data byte of the received message

23 to 16 DB3[7:0]

X

data byte 3; if the data length code value

is three or more, this register contains the

third data byte of the received message

15 to 8

7 to 0

DB2[7:0]

DB1[7:0]

data byte 2; if the data length code value

is two or more, this register contains the

second data byte of the received

message

R

00h*

X

data byte 1; if the data length code value

is one or more, this register contains the

ﬁrst data byte of the received message

8.5.1.15 CAN controller receive buffer data B register (CCRXBDB)

The CAN controller receive buffer data B register contains the second four data bytes of

the received message. This register is read only.

Table 177 shows the bit assignment of the CCRXBDB register.

Table 177. CCRXBDB register bit description

Legend: * reset value

Bit

Symbol

Access Value Soft reset

mode value

Description

31 to 24 DB8[7:0]

23 to 16 DB7[7:0]

R

00h*

X

data byte 8; if the data length code value

is eight or more, this register contains the

eighth data byte of the received message

R

00h*

X

data byte 7; if the data length code value

is seven or more, this register contains

the seventh data byte of the received

message

15 to 8 DB6[7:0]

R

00h*

X

data byte 6; if the data length code value

is six or more, this register contains the

sixth data byte of the received message

7 to 0

DB5[7:0]

data byte 5; if the data length code value

is ﬁve or more, this register contains the

ﬁfth data byte of the received message

8.5.1.16 CAN controller transmit buffer message info register (CCTXB1MI, CCTXB2MI and

CCTXB3MI)

The CAN controller transmit buffer message info register reﬂects the characteristics of the

transmit message. This register is only writable when the transmit buffer is released

(corresponding transmit buffer status bit is logic 1).

Table 178 shows the bit assignment of the CCTXB1MI, CCTXB2MI and CCTXB3MI

registers.

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Table 178. CCTXB1MI, CCTXB2MI and CCTXB3MI register bit description

Legend: * reset value

Bit

Symbol

Access Value Soft reset

mode value

Description

31

FF

R/W

X

frame format

1

an extended frame format message is

transmitted

0*

a standard frame format message is

transmitted

30

RTR

R/W

X

remote frame request

1

a remote frame format message is

transmitted

0*

-

a data frame format message is

transmitted

29 to 20 reserved

19 to 16 DLC[3:0]

-

reserved; do not modify, read as

logic 0, write as logic 0

R/W

0h*

X

data length code; this register contains

the number of data bytes to be

transmitted in case bit RTR is logic 0

or the requested number of data bytes

in case bit RTR is logic 1; values larger

than eight are handled as eight data

bytes

15 to 8 reserved

-

reserved; do not modify, read as

logic 0, write as logic 0

7 to 0

TXPRIO[7:0] R/W

00h*

X

transmit priority; if the transmit priority

mode bit in the CAN controller mode

register is set, the transmit buffer with

the lowest transmit priority value wins

the prioritization and is sent ﬁrst; in

cases where the same transmit priority

or the same ID is chosen for more than

one transmit buffer, then the transmit

buffer with the lowest buffer number is

send ﬁrst

8.5.1.17 CAN controller transmit buffer identiﬁer register (CCTXB1ID, CCTXB2ID and

CCTXB3ID)

The CAN controller transmit buffer identiﬁer register contains the identiﬁer ﬁeld of the

transmit message. This register is only writable when the transmit buffer is released

(corresponding transmit buffer status bit is logic 1).

Table 179 shows the bit assignment of the CCTXB1ID, CCTXB2ID and CCTXB3ID

registers.

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Table 179. CCTXB1ID, CCTXB2ID and CCTXB3ID register bit description

Legend: * reset value

Bit

Symbol Access Value

Soft reset

Description

mode value

31 to 29 reserved

-

reserved; do not modify, read as

logic 0, write as logic 0

28 to 0 ID[28:0] R/W

0000 0000h*

X

identiﬁer; this register contains the

identiﬁer of transmit CAN message;

in case a standard frame format is

transmitted, the least signiﬁcant

11 bits must represent the 11-bit

identiﬁer

8.5.1.18 CAN controller transmit buffer data A register (CCTXB1DA, CCTXB2DA and

CCTXB3DA)

The CAN controller transmit buffer data A register contains the ﬁrst four data bytes of the

transmit message. This register is only writable when the transmit buffer is released

(corresponding transmit buffer status bit is logic 1).

Table 180 shows the bit assignment of the CCTXB1DA, CCTXB2DA and CCTXB3DA

registers.

Table 180. CCTXB1DA, CCTXB2DA and CCTXB3DA register bit description

Legend: * reset value

Bit

Symbol Access Value

Soft reset

Description

mode value

31 to 24 DB4[7:0] R/W

23 to 16 DB3[7:0] R/W

15 to 8 DB2[7:0] R/W

00h*

X

data byte 4; if the data length code value

is four or more, this register contains the

fourth data byte of the received message

data byte 3; if the data length code value

is three or more, this register contains the

third data byte of the received message

data byte 2; if the data length code value

is two or more, this register contains the

second data byte of the received

message

7 to 0

DB1[7:0] R/W

00h*

X

data byte 1; if the data length code value

is one or more, this register contains the

ﬁrst data byte of the received message

8.5.1.19 CAN controller transmit buffer data B register (CCTXB1DB, CCTXB2DB and

CCTXB3DB)

The CAN controller transmit buffer data B register contains the second four data bytes of

the transmit message. This register is only writable when the transmit buffer is released

(corresponding transmit buffer status bit is logic 1).

Table 181 shows the bit assignment of the CCTXB1DB, CCTXB2DB and CCTXB3DB

registers.

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Table 181. CCTXB1DB, CCTXB2DB and CCTXB3DB register bit description

Legend: * reset value

Bit

Symbol Access Value Soft reset

Description

mode value

31 to 24 DB8[7:0] R/W

00h*

X

data byte 8; if the data length code value is

eight or more, this register contains the

eighth data byte of the received message

23 to 16 DB7[7:0] R/W

15 to 8 DB6[7:0] R/W

X

data byte 7; if the data length code value

is seven or more, this register contains the

seventh data byte of the received

message

00h*

X

data byte 6; if the data length code value is

six or more, this register contains the sixth

data byte of the received message

7 to 0

DB5[7:0] R/W

data byte 5; if the data length code value is

ﬁve or more, this register contains the ﬁfth

data byte of the received message

8.5.1.20 Global acceptance ﬁlter

The Global acceptance ﬁlter provides look-up for received identiﬁers, called acceptance

ﬁltering in CAN terminology, for all the CAN controllers. It includes a CAN ID look-up table

memory, in which software maintains one to ﬁve sections of identiﬁers. The CAN ID

look-up table memory is 2 kB large (512 words each 32 bits). It can contain up to 1024

standard frame identiﬁers (SFF) or 512 extended frame identiﬁers (EFF) or a mixture of

both types.

Note that the whole CAN ID look-up table memory is only word accessible.

The CAN ID look-up table memory is structured into up to ﬁve sections. In each section

the identiﬁers of a certain CAN message type are listed, see Table 182.

Table 182. Overview of sections in CAN ID look-up table memory

Name of section

Reception method CAN message

frame format

Explicit IDs or

Group of IDs

Standard Frame Format

FullCAN identiﬁer section

stored directly in

memory

Standard Frame

Format (SFF)

explicit

group

Standard Frame Format

explicit identiﬁer section

buffered

Standard Frame

Format (SFF)

Standard Frame Format

group identiﬁer section

Standard Frame

Format (SFF)

Extended Frame Format

explicit identiﬁer section

Extended Frame

Format (EFF)

explicit

group

Extended frame format group buffered

identiﬁer section

Extended Frame

Format (EFF)

To indicate the boundaries of the different sections within the ID look-up table memory,

ﬁve start address registers exist. In those start address registers the offset regarding the

base address CANAFM (see Table 7) is stored. The Standard Frame Format FullCAN

identiﬁer section always starts at the offset 00h, the following sections start as deﬁned in

the start address registers. The look-up table ends with the FullCAN message object

section, starting at the offset CAEOTA. A non-existing section is indicated by equal values

in consecutive start-address registers.

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See Figure 10 for the structure of the CAN ID look-up table memory.

11-bit index 0

11-bit index 2

11-bit index 1

11-bit index 3

standard frame

format FullCAN

identifier section

h entries

:

11-bit index (h − 2)

11-bit index (h − 1)

CASFESA

i entries

11-bit index (h)

11-bit index (h + 1)

standard frame

format explicit

identifier section

:

11-bit index (h + i − 1)

11-bit index (h + i) upper bound

:

11-bit index (h + i − 2)

11-bit index (h + i) lower bound

:

CASFGSA

j groups

standard frame

format group

identifier section

11-bit index (h + i + j − 1) lower bound

11-bit index (h + i + j − 1) upper bound

CAEFESA

k entries

29-bit index (h + i + j)

extended frame

format explicit

identifier section

29-bit index (h + i + j + 1)

:

29-bit index (h + i + j + k − 1)

CAEFGSA

l groups

29-bit index (h + i + j + k) lower bound

29-bit index (h + i + j + k) upper bound

:

extended frame

format group

identifier section

29-bit index (h + i + j + k + l − 1) lower bound

29-bit index (h + i + j + k + l − 1) upper bound

CAEOTA

FullCAN message

object section

001aaa175

Fig 10. ID look-up table memory

8.5.1.21 Standard frame format FullCAN identiﬁer section

If the CAN acceptance ﬁlter is set into FullCAN mode (EFCAN = 1) the FullCAN identiﬁer

section in the look-up table is enabled. Otherwise the acceptance ﬁlter ignores this

section. The entries of the FullCAN identiﬁer section must be arranged in ascending

numerical order, one per half word, two per word (see Figure 10).

Since each CAN controller has its own address map, each table entry also contains the

number of the CAN controller to which it applies. This section starts at the offset 00h and

contains identiﬁers index 0 to (h - 1). The bit allocation is given in Table 183.

Table 183. SFF FullCAN identiﬁer section bit description

Bit

Symbol Description

31 to 29

28

SCC

MDB

even index: CAN controller number

even index: message disable bit; logic 0 is message enabled and logic 1 is

message disabled

27

-

not used

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Table 183. SFF FullCAN identiﬁer section bit description …continued

Bit

Symbol Description

ID[28:18] even index: 11-bit CAN 2.0 B identiﬁer

26 to 16

15 to 13

12

SCC

MDB

odd index: CAN controller number

odd index: message disable bit; logic 0 is message enabled and logic 1 is

message disabled

11

-

not used

10 to 0

ID[28:18] odd index: 11-bit CAN 2.0 B identiﬁer

If an incoming message is detected, the acceptance ﬁlter tries to ﬁnd the ID in the

FullCAN section ﬁrst and continues searching in the following sections. In case of an

identiﬁer match during the acceptance ﬁlter process, the received FullCAN message

object data is moved from the receive buffer of the appropriate CAN controller into the

FullCAN message object section.

Table 184 shows the detailed layout structure of one FullCAN message stored in the

FullCAN message object section of the look-up table.

The base address of a speciﬁc message object data can be calculated by the contents of

the CAEOTA and the index i of the ID in the section (see Figure 10). Message object data

address = CAEOTA + (12 × i).

Table 184. FullCAN message object layout

Bit

Symbol

Description

Msg_ObjAddr + 0

31

FF

CAN frame format

remote frame request

not used

30

RTR

29 to 26

25 to 24

23 to 23

22 to 16

15 to 11

10 to 0

-

SEM[1:0]

semaphore bits

not used

-

RXDLC[6:0]

data length code

not used

-

ID[28:18]

identiﬁer bits 28 to 18

Msg_ObjAddr + 4

31 to 24

23 to 16

15 to 8

RXDATA4[7:0]

RXDATA3[7:0]

RXDATA2[7:0]

RXDATA1[7:0]

receive data 4

receive data 3

receive data 2

receive data 1

7 to 0

Msg_ObjAddr + 8

31 to 24

23 to 16

15 to 8

RXDATA8[7:0]

RXDATA7[7:0]

RXDATA6[7:0]

RXDATA5[7:0]

receive data 8

receive data 7

receive data 6

receive data 5

7 to 0

Since the FullCAN message object section of the look-up table RAM can be accessed

both by the acceptance ﬁlter internal state machine and the CPU, there is a method for

insuring that no CPU reads from a FullCAN message object occurs while the internal state

machine is writing to that object.

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For this purpose the acceptance ﬁlter uses a 3-state semaphore, encoded with the two

semaphore bits SEM[1:0] for each message object. This mechanism provides the CPU

with information about the current state of the acceptance ﬁlter internal state machine

activity in the FullCAN message object section.

The semaphore operates in the following manner:

• SEM[1:0] = 01: Acceptance ﬁlter is in the process of updating the buffer

• SEM[1:0] = 11: Acceptance ﬁlter has ﬁnished updating the buffer

• SEM[1:0] = 00: CPU is in the process of reading from the buffer / no update since last

reading from the buffer

Before writing the ﬁrst data byte into a message object SEM[1:0] is set to 01. After having

written the last data byte into the message object, the acceptance ﬁlter internal state will

update the semaphore bits by setting SEM[1:0] = 11.

Before reading from a message object, the CPU should read SEM[1:0] to determine the

current state of the message object. If SEM[1:0] = 01, the internal state machine is

currently active in this message object. If SEM[1:0] = 11, the message object is available

to be read.

Before the CPU begins reading from the message object, it should clear SEM[1:0] = 00.

When the CPU has ﬁnished reading, it should check SEM[1:0] again. In case of SEM[1:0]

unequal to 00, the message object has been changed during reading. Therefore the

contents of the message object should be read out once again. If, on the other hand,

SEM[1:0] = 00 as expected, the valid data has been successfully read by the CPU.

Conditions to activate the FullCAN mode:

• The EFCAN bit in the CAMODE register has to be set

• The start address offset of the Standard Frame Format explicit identiﬁer section

CASFESA has to be larger than logic 0

• The available space for the FullCAN message object section must be large enough to

store one FullCAN object for any FullCAN identiﬁer

8.5.1.22 Standard frame format explicit identiﬁer section

The entries of the SFF explicit identiﬁer section must be arranged in ascending numerical

order, one per half word, two per word (see Figure 10). Since each CAN controller has its

own address map, each entry also contains the number of the CAN controller to which it

applies.

This section starts with the CASFESA start address register and contains the identiﬁers

index h to index (h + i − 1). The bit allocation of the ﬁrst word is given in Table 185.

Table 185. SFF explicit identiﬁer section bit description

Bit

Symbol Description

31 to 29

28

SCC

MDB

even index: CAN controller number

even index: message disable bit; logic 0 is message enabled and logic 1 is

message disabled

27

-

not used

26 to 16

ID[28:18] even index: 11-bit CAN 2.0 B identiﬁer

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Table 185. SFF explicit identiﬁer section bit description …continued

Bit

Symbol Description

15 to 13

12

SCC

MDB

odd index: CAN controller number

odd index: message disable bit; logic 0 is message enabled and logic 1 is

message disabled

11

-

not used

10 to 0

ID[28:18] odd index: 11-bit CAN 2.0 B identiﬁer

By means of the message disable bits particular CAN identiﬁers can be turned on and off

dynamically from acceptance ﬁltering. When the acceptance ﬁlter function is enabled, only

the message disable bits in the acceptance ﬁlter look-up table memory can be changed by

software. Disabled entries must maintain the ascending sequence of identiﬁers.

8.5.1.23 Standard frame format group identiﬁer section

The table of SFF group identiﬁer section contains paired upper and lower bounds, one

pair per word. These pairs must be arranged in ascending numerical order (see

Figure 10).

This section starts with the CASFGSA start address register and contains the identiﬁers

index (h + i) lower bound to index (h + i + j − 1) upper bound. The bit allocation of the ﬁrst

word is given in Table 186.

Table 186. SFF group identiﬁer section bit description

Bit

Symbol Description

31 to 29

28

SCC

MDB

lower bound: CAN controller number

lower bound: message disable bit; logic 0 is message enabled and logic 1

is message disabled

27

-

not used

26 to 16

15 to 13

12

ID[28:18] lower bound: 11-bit CAN 2.0 B identiﬁer

SCC

MDB

upper bound: CAN controller number

upper bound: message disable bit; logic 0 is message enabled and logic 1

is message disabled

11

-

not used

10 to 0

ID[28:18] upper bound: 11-bit CAN 2.0 B identiﬁer

By means of the message disable bits particular CAN identiﬁer groups can be turned on

and off dynamically from acceptance ﬁltering. When the acceptance ﬁlter function is

enabled, only the message disable bits in the acceptance ﬁlter look-up table memory can

be changed by software. Note that in this section the lower bound and upper bound

message disable bit must always have the same value. Disabled entries must maintain the

ascending sequence of identiﬁers.

8.5.1.24 Extended frame format explicit identiﬁer section

If extended identiﬁers (29-bit) are used in the application, at least one of the other two

tables in acceptance ﬁlter look-up table must not be empty, one for explicit extended

identiﬁers and one for ranges of extended identiﬁers. The table of explicit extended

identiﬁers must be arranged in ascending numerical order (see Figure 10).

This section with start address EFF contains the identiﬁers ID (i + j + 1) to ID (i + j + k).

The bit allocation of the ﬁrst word is given in Table 187.

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Table 187. EFF explicit identiﬁer section bit description

Bit

Symbol

SCC

Description

31 to 29

28 to 0

CAN controller number

29-bit CAN 2.0 B identiﬁer

ID[28:0]

8.5.1.25 Extended frame format group identiﬁer section

The Extended Frame Format (EFF) group identiﬁer section must contain an even number

of entries, of the same form as in the EFF explicit identiﬁer section (see Figure 10). Like

the EFF explicit identiﬁer section, the EFF group identiﬁer section must be arranged in

ascending numerical order. The upper and lower bounds in the section are implicitly

paired as an inclusive group of extended addresses, such that any received address that

falls in the inclusive group is accepted and received. Software must maintain the section

to consist of such word pairs.

This section starts with CAEFGSA start address register and contains the identiﬁers index

(h + i + j + k) lower bound to index (h + i + j + k + l − 1) upper bound. The bit allocation is

given in Table 188.

Table 188. EFF group identiﬁer section bit description

Bit

CAEFGSA start address

31 to 29 SCC lower bound: CAN controller number

ID[28:0] lower bound: 29-bit CAN 2.0 B identiﬁer

Symbol Description

28 to 0

CAEFGSA start address + 4

31 to 29 SCC

upper bound: CAN controller number

28 to 0

ID[28:0] upper bound: 29-bit CAN 2.0 B identiﬁer

8.5.1.26 CAN acceptance ﬁlter mode register (CAMODE)

The CAN acceptance ﬁlter mode register is used to change the behavior of the

acceptance ﬁlter.

Table 189 shows the bit assignment of the CAMODE register.

Table 189. CAMODE register bit description

Legend: * reset value

Bit

31 to 3 reserved

EFCAN

Symbol Access Value

Description

-

reserved; do not modify, read as logic 0, write as logic 0

FullCAN extension mode

2

R/W

1

the FullCAN functionality is enabled

the FullCAN functionality is disabled

0*

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Table 189. CAMODE register bit description …continued

Legend: * reset value

Bit

Symbol Access Value

ACCBP R/W

Description

1

acceptance ﬁlter bypass

1

all Rx messages are accepted on enabled CAN

controllers; software must set this bit before modifying

the contents of any of the acceptance ﬁlter registers, and

before modifying the contents of look-up table RAM in

any way other than setting or clearing disable bits in

standard identiﬁer entries

0*

when both this bit and bit ACCOFF are logic 0, the

acceptance ﬁlter operates to screen received CAN

identiﬁers

0

ACCOFF R/W

acceptance ﬁlter off

1*

0

if bit ACCBP = 0, the acceptance ﬁlter is not operational;

all received CAN messages are ignored

the acceptance ﬁlter is operational

8.5.1.27 CAN acceptance ﬁlter standard frame explicit start address register (CASFESA)

The CAN acceptance ﬁlter standard frame explicit start address register.

Table 190 shows the bit assignment of the CASFESA register.

Table 190. CASFESA register bit description

Legend: * reset value

Bit

Symbol

Access Value Description

31 to 12 reserved

-

reserved; do not modify, read as logic 0, write as

logic 0

11 to 2

SFESA[9:0] R/W

00h*

standard frame explicit start address; this register

deﬁnes the start address of the section of explicit

standard identiﬁers in acceptance ﬁlter look-up table;

if the section is empty, write the same value in this

register and the SFGSA register; if bit EFCAN = 1,

this value also indicates the size of the section of

standard identiﬁers which the acceptance ﬁlter will

search and (if found) automatically store received

messages in acceptance ﬁlter section; write access is

only possible during the acceptance ﬁlter bypass or

acceptance ﬁlter off mode; read access is possible in

acceptance ﬁlter on and off mode; the standard frame

explicit start address is aligned on word boundaries

and therefore the lowest 2 bits must be always logic 0

1 to 0

reserved

-

reserved; do not modify, read as logic 0, write as

logic 0

8.5.1.28 CAN acceptance ﬁlter standard frame group start address register (CASFGSA)

The CAN acceptance ﬁlter standard frame group start address register.

Table 191 shows the bit assignment of the CASFGSA register.

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Table 191. CASFGSA register bit description

Legend: * reset value

Bit Symbol

31 to 12 reserved

Access Value

Description

-

reserved; do not modify, read as logic 0, write as

logic 0

11 to 2

SFGSA[9:0] R/W

00h*

standard frame group start address; this register

deﬁnes the start address of the section of grouped

standard identiﬁers in acceptance ﬁlter look-up table;

if the section is empty, write the same value in this

register and the EFESA register; the largest value

that should be written to this register is 7FCh, when

only the standard explicit section is used, and the

last word (address 7F8h) in acceptance ﬁlter look-up

table is used; write access is only possible during the

acceptance ﬁlter bypass or acceptance ﬁlter off

mode; read access is possible in acceptance ﬁlter on

and off mode; the standard frame group start

address is aligned on word boundaries and therefore

the lowest 2 bits must be always logic 0

1 to 0

reserved

-

reserved; do not modify, read as logic 0, write as

logic 0

8.5.1.29 CAN acceptance ﬁlter extended frame explicit start address register (CAEFESA)

The CAN acceptance ﬁlter extended frame explicit start address register.

Table 192 shows the bit assignment of the CAEFESA register.

Table 192. CAEFESA register bit description

Legend: * reset value

Bit

Symbol

Access Value Description

31 to 12 reserved

-

reserved; do not modify, read as logic 0, write as

logic 0

11 to 2

EFESA[9:0] R/W

00h*

extended frame explicit start address; this register

deﬁnes the start address of the section of explicit

extended identiﬁers in acceptance ﬁlter look-up table;

if the section is empty, write the same value in this

register and the EFGSA register; the largest value

that should be written to this register is 7FCh, when

both extended sections are empty and the last word

(address 7F8h) in acceptance ﬁlter look-up table is

used; write access is only possible during the

acceptance ﬁlter bypass or acceptance ﬁlter off mode;

read access is possible in acceptance ﬁlter on and off

mode; the extended frame explicit start address is

aligned on word boundaries and therefore the lowest

2 bits must be always logic 0

1 to 0

reserved

-

reserved; do not modify, read as logic 0, write as

logic 0

8.5.1.30 CAN acceptance ﬁlter extended frame group start address register (CAEFGSA)

The CAN acceptance ﬁlter extended frame group start address register.

Table 193 shows the bit assignment of the CAEFGSA register.

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Table 193. CAEFGSA register bit description

Legend: * reset value

Bit Symbol

31 to 12 reserved

Access Value Description

-

reserved; do not modify, read as logic 0, write as

logic 0

11 to 2

EFGSA[9:0] R/W

00h*

extended frame group start address; this register

deﬁnes the start address of the section of grouped

extended identiﬁers in acceptance ﬁlter look-up table;

if the section is empty, write the same value in this

register and the EOTA register; the largest value that

should be written to this register is 7FCh, when this

section is empty and the last word (address 7F8h) in

acceptance ﬁlter look-up table is used; write access is

only possible during the acceptance ﬁlter bypass or

acceptance ﬁlter off mode; read access is possible in

acceptance ﬁlter on and off mode; the extended frame

group start address is aligned on word boundaries

and therefore the lowest 2 bits must be always logic 0

1 to 0

reserved

-

reserved; do not modify, read as logic 0, write as

logic 0

8.5.1.31 CAN acceptance ﬁlter end of look up table address register (CAEOTA)

The CAN acceptance ﬁlter end of look up table address register.

Table 194 shows the bit assignment of the CAEOTA register.

Table 194. CAEOTA register bit description

Legend: * reset value

Bit

Symbol

Access Value Description

31 to 12 reserved

-

reserved; do not modify, read as logic 0, write as

logic 0

11 to 2

EOTA[9:0] R/W

00h*

End of look-up table address. The largest value of the

register CAEOTA should never exceed 7FC.

If bit EFCAN = 0, the register should contain the next

address above the last active acceptance ﬁlter identiﬁer

section.

If bit EFCAN = 1, the register contains the start address

of the FullCAN message object section. In case of an

identiﬁer match in the standard frame format FullCAN

identiﬁer section during the acceptance ﬁlter process,

the received FullCAN message object data is moved

from the receive buffer of the appropriate CAN

controller into the FullCAN message object section.

Each deﬁned FullCAN message needs three address

lines for the message data in the FullCAN message

object data section. Write access is only possible

during the acceptance ﬁlter bypass or acceptance ﬁlter

off mode; read access is possible in acceptance ﬁlter

on and off mode.

1 to 0

reserved

-

reserved; do not modify, read as logic 0, write as

logic 0

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8.5.1.32 CAN acceptance ﬁlter look-up table error address register (CALUTEA)

The CAN acceptance ﬁlter look-up table error address register represents the address in

the look-up table at which a problem has been detected when the look-up table error bit is

set.

The CALUTEA register is read only. Table 195 shows the bit assignment of the CALUTEA

register.

Table 195. CALUTEA register bit description

Legend: * reset value

Bit

Symbol

Access Value

Description

31 to 11 reserved

-

reserved; do not modify, read as logic 0, write as

logic 0

10 to 2

LUTEA[8:0]

reserved

R

00h*

look-up table error address; this register contains the

address in the look-up table at which the acceptance

ﬁlter encountered an error in the content of the

tables; this address is valid when the look-up table

error bit is set; reading this register clears the LUTE

look-up table error bit

1 to 0

-

reserved; do not modify, read as logic 0, write as

logic 0

8.5.1.33 CAN acceptance ﬁlter look-up table error register (CALUTE)

The CAN acceptance ﬁlter look-up table error register provides the conﬁguration status of

the look-up table contents. In case of an error an interrupt is generated via the general

CAN interrupt input source of the vectored interrupt controller.

The CALUTE register is read-only. Table 196 shows the bit assignment of the CALUTE

register.

Table 196. CALUTE register bit description

Legend: * reset value

Bit

31 to 1 reserved

LUTE

Symbol Access Value

Description

-

reserved; do not modify, read as logic 0, write as logic 0

look-up table error

0

R

1

the acceptance ﬁlter has encountered an error in the

content of the look-up table; reading the LUTEA register

clears this bit; this error condition is part of the general

CAN interrupt input source

0*

8.5.1.34 CAN controllers central transmit status register (CCCTS)

The CAN controllers central transmit status register provides bundled access to

transmission status of all the CAN controllers. The status ﬂags are the same as present in

the status register of the corresponding CAN controller.

The CCCTS register is read only. Table 197 shows the bit assignment of the CCCTS

register.

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Table 197. CCCTS register bit description

Legend: * reset value

Bit

Symbol Access Value

Description

31 to 22 reserved

-

reserved; do not modify, read as logic 0, write as

logic 0

21

20

19

18

17

16

TCS5

TCS4

TCS3

TCS2

TCS1

TCS0

R

CAN controller 5 transmission completed status

the transmission was completed successfully

1*

0

R

CAN controller 4 transmission completed status

the transmission was completed successfully

1*

0

CAN controller 3 transmission completed status

the transmission was completed successfully

1*

0

CAN controller 2 transmission completed status

the transmission was completed successfully

1*

0

CAN controller 1 transmission completed status

the transmission was completed successfully

1*

0

CAN controller 0 transmission completed status

the transmission was completed successfully

1*

0

-

15 to 14 reserved

-

reserved; do not modify, read as logic 0, write as

logic 0

13

12

11

10

9

TBS5

TBS4

TBS3

TBS2

TBS1

TBS0

R

CAN controller 5 transmit buffer status

the transmit buffers are empty

1*

0

R

CAN controller 4 transmit buffer status

the transmit buffers are empty

1*

0

CAN controller 3 transmit buffer status

the transmit buffers are empty

1*

0

CAN controller 2 transmit buffer status

the transmit buffers are empty

1*

0

CAN controller 1 transmit buffer status

the transmit buffers are empty

1*

0

8

CAN controller 0 transmit buffer status

the transmit buffers are empty

1*

0

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Table 197. CCCTS register bit description …continued

Legend: * reset value

Bit

Symbol Access Value

Description

7 to 6

reserved

-

reserved; do not modify, read as logic 0, write as

logic 0

5

4

3

2

1

0

TS5

R

CAN controller 5 transmit status

a message is being transmitted

1*

0

TS4

TS3

TS2

TS1

TS0

R

CAN controller 4 transmit status

a message is being transmitted

1*

0

CAN controller 3 transmit status

a message is being transmitted

1*

0

CAN controller 2 transmit status

a message is being transmitted

1*

0

CAN controller 1 transmit status

a message is being transmitted

1*

0

CAN controller 0 transmit status

a message is being transmitted

1*

0

8.5.1.35 CAN controllers central receive status register (CCCRS)

The CAN controllers central receive status register provides bundled access to reception

status of all the CAN controllers. The status ﬂags are the same as present in the status

register of the corresponding CAN controller.

The CCCRS register is read only. Table 198 shows the bit assignment of the CCCRS

register.

Table 198. CCCRS register bit description

Legend: * reset value

Bit

Symbol Access Value

Description

31 to 22 reserved

-

reserved; do not modify, read as logic 0, write as

logic 0

21

20

DOS5 ^[1]

DOS4 ^[1]

R

CAN controller 5 data overrun status

1

the received message was lost due to not fast enough

read out of preceding message

0*

R

CAN controller 4 data overrun status

1

the received message was lost due to not fast enough

read out of preceding message

0*

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Table 198. CCCRS register bit description …continued

Legend: * reset value

Bit

Symbol Access Value

Description

19

DOS3 ^[1]

DOS2 ^[1]

DOS1 ^[1]

DOS0 ^[1]

R

CAN controller 3 data overrun status

1

the received message was lost due to not fast enough

read out of preceding message

0*

18

17

16

CAN controller 2 data overrun status

1

the received message was lost due to not fast enough

read out of preceding message

0*

CAN controller 1 data overrun status

1

the received message was lost due to not fast enough

read out of preceding message

0*

CAN controller 0 data overrun status

1

the received message was lost due to not fast enough

read out of preceding message

0*

-

15 to 14 reserved

-

reserved; do not modify, read as logic 0, write as

logic 0

13

12

11

10

9

RBS5 ^[1]

RBS4 ^[1]

RBS3 ^[1]

RBS2 ^[1]

RBS1 ^[1]

RBS0 ^[1]

R

CAN controller 5 receive buffer status

1

the receive buffers contains a received message

0*

R

CAN controller 4 receive buffer status

1

the receive buffers contains a received message

0*

CAN controller 3 receive buffer status

1

the receive buffers contains a received message

0*

CAN controller 2 receive buffer status

1

the receive buffers contains a received message

0*

CAN controller 1 receive buffer status

1

the receive buffers contains a received message

0*

8

CAN controller 0 receive buffer status

1

0*

-

the receive buffers contains a received message

7 to 6

5

reserved

RS5

-

reserved; do not modify, read as logic 0, write as

logic 0

R

CAN controller 5 receive status

a message is being received

1*

0

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Table 198. CCCRS register bit description …continued

Legend: * reset value

Bit

Symbol Access Value

Description

4

RS4

RS3

RS2

RS1

RS0

R

CAN controller 4 receive status

a message is being received

1*

0

3

2

1

0

CAN controller 3 receive status

a message is being received

1*

0

CAN controller 2 receive status

a message is being received

1*

0

CAN controller 1 receive status

a message is being received

1*

0

CAN controller 0 receive status

a message is being received

1*

0

[1] This bit is unchanged in case a FullCAN message is received.

8.5.1.36 CAN controllers central miscellaneous status register (CCCMS)

The CAN controllers central miscellaneous status register provides bundled access to the

bus and error status of all the CAN controllers. The status ﬂags are the same as present in

the status register of the corresponding CAN controller.

The CCCMS register is read only. Table 199 shows the bit assignment of the CCCMS

register.

Table 199. CCCMS register bit description

Legend: * reset value

Bit

Symbol Access Value

Description

31 to 14 reserved

-

reserved; do not modify, read as logic 0, write as

logic 0

13

12

BS5

BS4

R

CAN controller 5 bus status

1

the CAN controller is currently prohibited from bus

activity because the transmit error counter reached its

limiting value of FFh

0*

1

R

CAN controller 4 bus status

the CAN controller is currently prohibited from bus

activity because the transmit error counter reached its

limiting value of FFh

0*

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Table 199. CCCMS register bit description …continued

Legend: * reset value

Bit

Symbol Access Value

Description

11

BS3

BS2

BS1

BS0

R

CAN controller 3 bus status

1

the CAN controller is currently prohibited from bus

activity because the transmit error counter reached its

limiting value of FFh

0*

1

10

CAN controller 2 bus status

the CAN controller is currently prohibited from bus

activity because the transmit error counter reached its

limiting value of FFh

0*

1

9

CAN controller 1 bus status

the CAN controller is currently prohibited from bus

activity because the transmit error counter reached its

limiting value of FFh

0*

1

8

CAN controller 0 bus status

the CAN controller is currently prohibited from bus

activity because the transmit error counter reached its

limiting value of FFh

0*

-

7 to 6

5

reserved

ES5

-

reserved; do not modify, read as logic 0, write as

logic 0

R

CAN controller 5 error status

1

error warning limit has been exceeded

0*

4

ES4

R

CAN controller 4 error status; when logic 1, error

warning limit has been exceeded

1

error warning limit has been exceeded

0*

3

2

1

0

ES3

ES2

ES1

ES0

R

CAN controller 3 error status

1

error warning limit has been exceeded

0*

CAN controller 2 error status

1

error warning limit has been exceeded

0*

CAN controller 1 error status

1

error warning limit has been exceeded

0*

CAN controller 0 error status

1

error warning limit has been exceeded

0*

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8.5.2 LIN

ARM7 microcontroller with CAN and LIN controllers

8.5.2.1 Overview

The SJA2020 contains four LIN master controllers which can be used as dedicated LIN

master controller or as standard 450 UART with additional support for the sync break

generation.

The key features are:

• Complete LIN message handling and transfer

• One interrupt per LIN message

• Slave response time out detection

• Programmable sync break length

• Automatic sync ﬁeld generation

• Programmable inter byte space

• Hardware of software parity generation

• Automatic checksum generation

• Fault conﬁnement

• Fractional baud rate generator

• Conﬁgurable as standard UART

8.5.2.2 LIN pin description

The four LIN controllers in the SJA2020 have the following pins. The LIN pins are

combined with other functions on the port pins of the SJA2020, see Section 8.3.2.

Table 200 shows the LIN pins, x runs from 0 to 3.

Table 200. LIN controller pins

Symbol

Direction

OUT

Description

LINx TXDL

LINx RXDL

LIN channel x transmit data output

LIN channel x receive data input

IN

8.5.2.3 Register mapping

The LIN master controller registers are shown in Table 201.

The LIN master controller registers have an offset to the base address LIN RegBase

which can be found in the memory map (see Table 7). The function of a register is

dependent on the LIN master controller mode (bit LM).

Table 201. LIN register summary

Address Type

Reset value Name

Description

Reference

LIN master controller common registers

00h

04h

08h

R/W

01h

00h

LMODE LIN master controller mode

register

see Table 202

see Table 203

see Table 206

LCFG

LIN master controller

conﬁguration register

LCMD

LIN master controller command

register

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Table 201. LIN register summary …continued

Address Type Reset value Name

0Ch R/W 0 0001h LFBRG

Description

Reference

LIN master controller fractional

baud rate generator register

see Table 207

LIN master controller registers (bit LM = 0)

10h

14h

18h

R

342h

000h

10h

LSTAT

LIN master controller status

register

see Table 208

see Table 209

see Table 211

R

LIC

LIN master controller interrupt

and capture register

R/W

LIE

LIN master controller interrupt

enable register

1Ch

20h

-

reserved reserved for future expansion

R/W

00h

LCS

LTO

LID

LIN master controller check sum see Table 212

register

24h

28h

2Ch

30h

34h

38h

R/W

00h

LIN master controller time-out

register

see Table 213

see Table 214

see Table 215

see Table 216

see Table 217

see Table 218

000 0000h

LIN master controller message

buffer identiﬁer register

0000 0000h LDATA

0000 0000h LDATB

0000 0000h LDATC

0000 0000h LDATD

LIN master controller message

buffer data A register

LIN master controller message

buffer data B register

LIN master controller message

buffer data C register

LIN master controller message

buffer data D register

LIN UART registers (bit LM = 1)

10h

R

-

RBR

THR

IER

IIR

receiver buffer register

transmit holding register

interrupt enable register

interrupt ID register

see Table 219

see Table 220

see Table 221

see Table 222

see Table 224

W

-

14h

18h

1Ch

20h

24h

28h

2Ch

R/W

R

0h

1h

00h

-

R/W

-

LCR

line control register

reserved reserved for future expansion

LSR line status register

reserved reserved for future expansion

SCR scratch register

R

60h

-

see Table 227

see Table 228

-

R/W

00h

8.5.2.4 LIN master controller mode register (LMODE)

The LIN master controller mode register provides the selection between the LIN master

controller and UART conﬁguration.

Table 202 shows the bit assignment of the LMODE register.

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Table 202. LMODE register bit description

Legend: * reset value

Bit

Symbol Access Value

Description

31 to 8 reserved

-

reserved; do not modify, read as logic 0, write as logic 0

LIN master controller mode.

7

LM

R/W

Changing from LIN master controller mode to UART

mode is only possible if the LIN reset mode was set

before and should be done with bit LM = 1 and bit

LRM = 1; changing from UART mode to LIN master

controller mode should be done with bit LM = 0 and bit

LRM = 1

1

the LIN master controller operates in UART mode

0*

the LIN master controller operates as LIN master

controller

6 to 1 reserved

LRM

-

reserved; do not modify, read as logic 0, write as logic 0

0

R/W

LIN reset mode; only writable in LIN master controller

mode

1*

the LIN master controller is in reset mode and the current

message transmission or reception is aborted; the

registers LCMD, LSTAT, LIC, LCS, LID, LDATA, LDATB,

LDATC and LDATD get their reset value

0

the LIN master controller is in normal operation mode

8.5.2.5 LIN master controller conﬁguration register (LCFG)

The LIN master controller conﬁguration register is used to change the length for the sync

break ﬁeld, the inter byte space and contains software enable bits for the identiﬁer parity

and checksum calculation. In LIN master controller mode, the register is only writable if

the LIN master controller is in reset mode.

Table 203 shows the bit assignment of the LCFG register.

Table 203. LCFG register bit description

Legend: * reset value

Bit

Symbol

Access Value

Description

31 to 8 reserved

-

reserved; do not modify, read as logic 0, write as logic 0

software ID parity

7

SWPA

R/W

1

the software generated ID parity from the message

buffer is used to send onto the LIN bus

0*

only the hardware generated parity is used to send onto

the LIN bus

6

5

SWCS

R/W

software checksum

1

the checksum is generated by software

the checksum is generated by hardware

reserved; do not modify, read as logic 0, write as logic 0

0*

-

reserved

-

4 to 3 IBS[1:0]

R/W

0h*

inter byte space length; the inter byte space length is

inserted during transmission; see Table 204

2 to 0 SBL[2:0]

R/W

0h*

sync break logic 0 length; writing a value of 7h will

always read as 6h; see Table 205

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Table 204. Inter byte space length conﬁguration bits

IBS[1:0] Function

00

01

10

11

0 bits inter byte space length

1 bits inter byte space length

2 bits inter byte space length

3 bits inter byte space length

Table 205. Sync break length conﬁguration bits

SBL[2:0]

000

Function

10 bits sync break length

11 bits sync break length

12 bits sync break length

13 bits sync break length

14 bits sync break length

15 bits sync break length

16 bits sync break length

001

010

011

100

101

110

111

8.5.2.6 LIN master controller command register (LCMD)

The LIN master controller command register is used to initiate a LIN message

transmission. In LIN master controller mode, the register is only writable if the LIN master

controller is in reset mode.

A dedicated sync break generator is added to the standard UART functionality to ease the

sync break generation for LIN messages with a standard UART. A break interrupt is

generated after the sync break delimiter has been transmitted if enabled.

Table 206 shows the bit assignment of the LCMD register.

Table 206. LCMD register bit description

Legend: * reset value

Bit

31 to 8 reserved

SSB

Symbol Access Value

Description

-

reserved; do not modify, read as logic 0, write as logic 0

send sync break; only writable in LIN UART mode

7

R/W

1

a sync break is send onto the LIN bus; this bit is

automatically cleared

0*

-

6 to 1 reserved

TR

-

reserved; do not modify, read as logic 0, write as logic 0

0

R/W

transmit request; only writable in LIN master controller

mode

1

a transmission of a complete LIN message will be

initiated; this bit is automatically cleared

0*

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8.5.2.7 LIN master controller fractional baud rate generator register (LFBRG)

The LIN master controller fractional baud rate generator register stores the divisor in

16-bit binary format and the fraction in 4-bit binary format for the programmable baud

generator. The output frequency of the baud generator is 16 times the baud rate. The

input frequency of the baud generator is the system clock frequency f_clk(sys)divided by the

divisor plus fraction value. In LIN master controller mode this register is only writeable in

reset mode.

The baud rate can be calculated from the following formula:

f _clk(sys)

baudrate =

--------------------------------------------

16 × INT + FRAC

Table 207 shows the bit assignment of the LFBRG register.

Table 207. LFBRG register bit description

Legend: * reset value

Bit

Symbol Access Value

Description

31 to 20 reserved

-

reserved; do not modify, read as logic 0, write as

logic 0

19 to 16 FRAC

R/W

0h*

fractional value; in LIN UART mode only writable if in

reset mode; contains the 4-bit fraction of the baud

division

15 to 0

INT

R/W

0001h* integer value; in LIN UART mode only writable if in

reset mode; contains the 16-bit baud rate divisor

8.5.2.8 LIN master controller status register (LSTAT)

The LIN master controller status register reﬂects the status of the LIN master controller.

Figure 11 shows the status ﬂag handling in terms of transmitting and receiving header and

response ﬁelds.

The LSTAT register is read only. Table 208 shows the bit assignment of the LSTAT

register.

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Header fields

Response fields

Case 1:

DD = 0

Master: sending, Slave: receiving

Transmit message complete interrupt

Case 2:

DD = 1

Master: sending, Slave: receiving

Receive message complete interrupt

Case 1

TS

Cleared with transmit message complete

or bit error or line clamped error condition

RS

Case 2

TS

RS

Cleared with receive message complete

or bit error or line clamped error condition

or time-out condition

MR

HS

Released/Idle with transmit message complete or receive message complete

or bit error or line clamped error condition or time-out condition

IS = MBA

001aaa173

Fig 11. LIN master controller status ﬂag handling

Table 208. LSTAT register bit description

Legend: * reset value

Bit

Symbol Access Value

Description

31 to 10 reserved

-

reserved; read as logic 0

TXD line level

9

8

7

TTL

R

1*

0

the current TXD line level is dominant

the current TXD line level is recessive

RXD line level

RLL

R

-

1*

0

-

the current RXD line level is dominant

the current RXD line level is recessive

reserved; read as logic 0

reserved

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Table 208. LSTAT register bit description …continued

Legend: * reset value

Bit

Symbol Access Value

Description

6

IS

R

idle status

1*

0

the LIN bus is idle

the LIN bus is active

5

ES

R

error status

1

a bit-error of line clamped error condition was detected

0*

no errors have been detected; the error status is

cleared automatically when a new transmission is

initiated

4

3

2

1

TS

R

transmit status

1

the LIN master controller is transmitting LIN response

ﬁelds

0*

RS

receive status

1

the LIN master controller is receiving LIN response

ﬁelds

0*

HS

header status

1

the LIN master controller is transmitting the LIN header

ﬁelds

0*

MBA

message buffer access

1*

0

the message buffer is released and available for CPU

access

the message buffer is locked and the CPU cannot

access the message buffer; a message is either waiting

for transmission or is in transmitting process or

receiving a message

0

MR

R

message received

1

the message buffer contains a valid received message

0*

the message buffer does not contain a valid message;

the message received status is cleared automatically

with a write access to the message buffer or by a new

transmission request

8.5.2.9 LIN master controller interrupt and capture register (LIC)

The LIN master controller interrupt and capture register determines when the LIN master

controller gives an interrupt request if the corresponding interrupt enable has been set.

Reading the interrupt register clears the interrupt source. A detailed bus error capture is

reported.

The LIC register is read only. Table 209 shows the bit assignment of the LIC register.

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Table 209. LIC register bit description

Legend: * reset value

Bit

Symbol Access Value

Description

31 to 12 reserved

-

reserved; read as logic 0

error capture; see Table 210

reserved; read as logic 0

wake-up and LIN protocol error interrupt

11 to 8

EC[3:0]

reserved

WPI

R

-

0h*

-

7

6

R

1

a dominant bus level has been detected when the LIN

bus was idle; a dominant bus level on the LIN bus can

be caused by a wake-up message of a slave node as

well as by arbitrary created or faulty generated

messages of LIN slaves or by a stuck dominant level

0*

5

4

RTLCEI

NRI

R

line clamped error interrupt^[1]

1

no valid message can be generated on the LIN bus due

to clamped dominant or recessive RXD or TXD line

0*

slave not responding error interrupt

1

the slave response is not completed within a certain

time out period; the time out period is conﬁgurable via

the time out register

0*

1

3

2

CSI

BEI

R

checksum error interrupt

the received checksum ﬁeld does not match with the

calculated checksum

0*

bit error interrupt^[1]; the error capture bits represent the

detailed status in case of (when this bit is logic 1):

a difference between transmit and receive bit stream

is detected

the conﬁgured inter byte space length is violated

a stop bit of ﬁelds from received slave responses

was not recessive

1

0

TI

R

transmit message complete interrupt

1

a complete LIN message frame was transmitted or in

cases where data length code is set to logic 0 (no

response ﬁelds can be expected)

0*

1

RI

receive message complete interrupt

the last byte, the checksum ﬁeld of the incoming bit

stream is moved from receive shift register into the

message buffer

0*

[1] Line clamped error interrupt (RTLCEI) and bit error interrupt (BEI) must be jointly enabled. Enabling only

one of them is not allowed.

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Table 210. Bus error capture interpretation bits

EC[3:0] Function

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

:

bit error in sync break ﬁeld

bit error in sync ﬁeld

bit error in identiﬁer ﬁeld

bit error in data ﬁeld

bit error in checksum ﬁeld

bit error in inter byte space

bit error in stop bit of received slave responses

reserved

recessive line clamped error; RXD / TXD line stuck recessive

dominant line clamped error; RXD / TXD line stuck dominant

reserved

:

1111

reserved

8.5.2.10 LIN master controller interrupt enable register (LIE)

The LIN master controller interrupt enable register determines when the LIN master

controller gives an interrupt request if the corresponding interrupt enable has been set.

Table 211 shows the bit assignment of the LIE register.

Table 211. LIE register bit description

Legend: * reset value

Bit

Symbol Access Value

Description

31 to 7 reserved

-

reserved; do not modify, read as logic 0, write as logic 0

wake up and LIN protocol error interrupt enable

6

5

4

WPIE

R/W

1

detection of a dominant bus level when the LIN bus was

idle results in the respective interrupt

0*

RTLCEIE R/W

line clamped error interrupt enable^[1]

1

whenever no valid message can be generated on the LIN

bus results in the respective interrupt

0*

NRIE

CSIE

R/W

slave not responding error interrupt enable

1

whenever the slave response is not completed within the

conﬁgured time out period results in the respective

interrupt

0*

1

3

checksum error interrupt enable

whenever the received checksum ﬁeld does not match

with the calculated checksum results in the respective

interrupt

0*

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Table 211. LIE register bit description …continued

Legend: * reset value

Bit

Symbol Access Value

Description

2

BEIE

R/W

bit error interrupt enable^[1]

1

detection of a bit error results in the respective interrupt

0*

1

0

TIE

R/W

transmit message complete interrupt enable

1

whenever a complete LIN message frame was

transmitted or in cases where data length code is set to

logic 0 (no response ﬁelds can be expected) results in the

respective interrupt

0*

1

RIE

R/W

receive message complete interrupt enable

whenever the last byte, the checksum ﬁeld of the

incoming bit stream is moved from receive shift register

into the message buffer results in the respective interrupt

0*

[1] Line clamped error interrupt enable (RTLCEI) and bit error interrupt enable (BEI) must be jointly enabled.

Enabling only one of them is not allowed.

8.5.2.11 LIN master controller checksum register (LCS)

The LIN master controller LIN master controller checksum register contains the checksum

value. In cases when the LIN master controller is transmitting the response ﬁelds, the

checksum register contains the checksum value to be transmitted onto the LIN bus. In

cases when the LIN master controller is receiving the response ﬁelds, the checksum

register contains the received checksum from the slave. If the software checksum bit in

the conﬁguration register is set to logic 0, the checksum register appears to the CPU as a

read only memory. By setting the software checksum bit the checksum register appears to

the CPU as a read/write memory. In this case and before a transmission is initiated, the

software has to provide the checksum to the checksum register.

Table 212 shows the bit assignment of the LCS register.

Table 212. LCS register bit description

Legend: * reset value

Bit

Symbol Access Value

Description

31 to 8 reserved

7 to 0 CS

-

reserved; do not modify, read as logic 0, write as logic 0

R/W

00h*

LIN message checksum; when the LIN master controller

is transmitting, the checksum register contains the

hardware or software calculated checksum value

depending on the software checksum bit; when the LIN

master controller is receiving, the checksum register

contains the received checksum value from the slave

node

8.5.2.12 LIN master controller time-out register (LTO)

The LIN master controller time-out register is used to deﬁne the maximum number of bit

times (t_bit) within a response from all LIN slaves connected to one node should be

completed. The time-out starts as soon as the LIN header was transmitted (the value of

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the time-out register is decremented with every bit time) and a slave response is

expected. When enabled, the Slave not responding error interrupt (NRI) gets asserted as

soon as the time-out limit is exceeded.

The time-out (t_to) time to be programmed can be calculated from the following formulas:

t_resp(nom)

t_resp(max)

t_to

=

= 1.4 ×

----------------------

t_bit

with

N_data+ 1

t_resp(nom)= 10 ×

----------------------

t_bit

Note: t_bitis the nominal time required to transmit a bit, as deﬁned in LIN physical layer;

N_datais the number of data ﬁelds sent with the slave response.

Table 213 shows the bit assignment of the LTO register.

Header

Response

data field(s) + checksum field

expected message

minimum frame length

maximum frame length

complete time frame

time-out period

Slave is sending and Master is receiving

001aaa220

Fig 12. Time-out period for all LIN slave nodes

Table 213. LTO register bit description

Legend: * reset value

Bit

Symbol Access Value

Description

31 to 8 reserved

7 to 0 TO

-

reserved; do not modify, read as logic 0, write as logic 0

R/W

00h*

LIN message time-out; this register deﬁnes the maximum

number of bit times when a response from all slave nodes

should be completed

8.5.2.13 LIN master controller message buffer registers (LID, LDATA, LDATB, LDATC and

LDATD)

The access to the message buffer is limited and controlled by the message buffer access

bit of the status register. The access to the LIN master controller message buffer registers

is only possible when the LIN master controller IP is in operating mode. Before accessing

the message buffer the CPU should always read the message buffer access bit ﬁrst to

determine whether an access is possible or not. In cases where the message buffer is

locked a write access is not successful whereas a read delivers logic 0 as result.

The ﬁrst part of the message buffer is the LIN message identiﬁer register (LID) containing

the header information and control format of the LIN message.

Table 214 shows the bit assignment of the LID register.

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Table 214. LID register bits

Legend: * reset value

Bit

Symbol Access Value

Description

31 to 26 reserved

-

reserved; do not modify, read as logic 0, write as

logic 0

25

24

CSID

DD

R/W

checksum ID inclusion

1

the identiﬁer ﬁeld is included in the checksum

calculation

0*

the identiﬁer ﬁeld is not included in the checksum

calculation

R/W

data direction

1

the response ﬁeld is expected to be send by a slave

node

0*

-

the response ﬁeld is sent by the LIN master controller

23 to 21 reserved

-

reserved; do not modify, read as logic 0, write as

logic 0

20 to 16 DLC[4:0] R/W

00h*

data length code; represents the binary number of data

bytes in the LIN message response ﬁeld; data length

code values larger than 16 are handled as the

maximum number of 16

15 to 8

reserved

-

reserved; do not modify, read as logic 0, write as

logic 0

7

P1

P0

ID

R/W

0*

LIN message parity bit 1

LIN message parity bit 0

LIN message identiﬁer

6

0*

5 to 0

00h*

The rest of the message buffer contains the LIN message data registers (LDATA, LDATB,

LDATC and LDATD).

Table 215, Table 216, Table 217 and Table 218 show the bit assignment of the LDATA,

LDATB, LDATC and LDATD registers, respectively.

Table 215. LDATA register bits

Legend: * reset value

Bit

Symbol

Access Value

Description

31 to 24 DF4[7:0]

23 to 16 DF3[7:0]

R/W

00h*

LIN message data ﬁeld 4

LIN message data ﬁeld 3

LIN message data ﬁeld 2

LIN message data ﬁeld 1

15 to 8

7 to 0

DF2[7:0]

DF1[7:0]

Table 216. LDATB register bits

Legend: * reset value

Bit

Symbol

Access Value

Description

31 to 24 DF8[7:0]

23 to 16 DF7[7:0]

R/W

00h*

LIN message data ﬁeld 8

LIN message data ﬁeld 7

LIN message data ﬁeld 6

LIN message data ﬁeld 5

15 to 8

7 to 0

DF6[7:0]

DF5[7:0]

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Table 217. LDATC register bits

Legend: * reset value

Bit Symbol

Access Value

Description

31 to 24 DF12[7:0]

23 to 16 DF11[7:0]

R/W

00h*

LIN message data ﬁeld 12

LIN message data ﬁeld 11

LIN message data ﬁeld 10

LIN message data ﬁeld 9

15 to 8

7 to 0

DF10[7:0]

DF9[7:0]

Table 218. LDATD register bits

Legend: * reset value

Bit

Symbol

Access Value

Description

31 to 24 DF16[7:0]

23 to 16 DF15[7:0]

R/W

00h*

LIN message data ﬁeld 16

LIN message data ﬁeld 15

LIN message data ﬁeld 14

LIN message data ﬁeld 13

15 to 8

7 to 0

DF14[7:0]

DF13[7:0]

8.5.2.14 Receive buffer register (RBR)

The receive buffer register is a 1-byte buffer and can be read via the bus interface. The

received data is passed from the receive shift register to the receive buffer. The least

signiﬁcant bit represents the oldest received data bit. If the character received is less than

8 bits, the unused most signiﬁcant bits are padded with logic 0.

The RBR register is read only. Table 219 shows the bit assignment of the RBR register.

Table 219. RBR register bit description

Legend: * reset value

Bit

Symbol

reserved

RBR[7:0]

Access Value

Description

31 to 8

7 to 0

-

reserved; read as logic 0

R

receive buffer register; contains the received byte

8.5.2.15 Transmit holding register (THR)

The transmit holding register is a 1-byte transmit buffer and can be written via the bus

interface. The data is passed from the transmit holding register to the transmit shift

register when the last one is idle. The least signiﬁcant bit represents the ﬁrst bit to

transmit.

The THR register is write only. Table 220 shows the bit assignment of the THR register.

Table 220. THR register bit description

Legend: * reset value

Bit

31 to 8 reserved

7 to 0 THR[7:0]

Symbol Access Value

Description

-

reserved; do not modify, write as logic 0

W

transmit holding register; writing to the transmit holding

register causes the data to be stored in the transmit

buffer; the byte will be sent when the transmitter is

available

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8.5.2.16 Interrupt enable register (IER)

The interrupt enable register is used to enable the three types of interrupts referred to in

the interrupt identiﬁcation register.

Table 221 shows the bit assignment of the IER register.

Table 221. IER register bit description

Legend: * reset value

Bit

Symbol Access Value

Description

31 to 3 reserved

-

reserved; do not modify, read as logic 0, write as logic 0

receiver line status interrupt enable

the receive line status interrupt is enabled

2

1

0

LSIE

R/W

1

0*

TBEIE

RBIE

R/W

transmit holding register empty interrupt enable

1

the transmit holding register empty interrupt is enabled

0*

receive buffer register interrupt register enable

the receive data available interrupt is enabled

1

0*

8.5.2.17 Interrupt ID register (IIR)

The interrupt ID register provides a status code that denotes the priority and source of a

pending interrupt. When an interrupt is generated, the interrupt ID register indicates that

an interrupt is pending and encodes the type in its three bits. The interrupts are frozen

during an access to the interrupt ID register. If an interrupt occurs during an access, the

interrupt is recorded for the next interrupt ID register access.

The IIR register is read only. Table 222 shows the bit assignment of the IIR register.

Table 222. IIR register bit description

Legend: * reset value

Bit

Symbol

Access Value

Description

31 to 3

2 to 0

reserved

INT_ID[2:0]

-

reserved; read as logic 0

interrupt identiﬁcation; see Table 223

R

1h*

Table 223. Interrupt identiﬁcation control functions details

INT_ID[2:0] Priority Interrupt

level

Type

Source

Method

001

none

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Table 223. Interrupt identiﬁcation control functions details …continued

INT_ID[2:0] Priority Interrupt

level

Type

Source

Method

110

1

receiver line status

overrun error, parity

read the line status

error, framing error, or register LSR

break interrupt

100

010

2

3

received data available receiver data available read the receive buffer

register RBR

transmitter holding

register empty

transmit holding

register empty

read the interrupt

identiﬁcation register

(if source of interrupt)

or writing into the

transmitter holding

register THR

8.5.2.18 Line control register (LCR)

The line control register controls the format of the asynchronous data communication

exchange.

Table 224 shows the bit assignment of the LCR register.

Table 224. LCR register bit description

Legend: * reset value

Bit

31 to 7 reserved

BC

Symbol Access Value

Description

-

reserved; do not modify, read as logic 0, write as logic 0

break control

6

R/W

1

a break transmission condition is forced which puts the

TXD output low

0*

the break transmission condition is disabled; the break

condition has no affect on the transmitter logic; it only

affects the TXD line

5 to 4 PS[5:4]

R/W

0h*

1

parity select; see Table 225

parity enable

3

PEN

a parity bit is generated in transmitted data between the

last data word bit and the ﬁrst stop bit; in received data

the parity is checked

0*

1

2

STB

R/W

number of stop bits

the number of generated stop bits are 2; except the word

length is 5 bits, then 1.5 stop bits are generated

0*

1 stop bit is generated

1 to 0 WLS[1:0] R/W

0h*

word length select; see Table 226

Table 225. Parity select conﬁguration bits

PS[5:4]

00

Function

odd parity (an odd number of logic 1s in the data and parity bits)

even parity (an even number of logic 1s in the data and parity bits)

forced logic 1 stick parity

01

10

11

forced logic 0 stick parity

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Table 226. Word length conﬁguration

WLS[1:0] Function

00

01

10

11

5-bit character length

6-bit character length

7-bit character length

8-bit character length

8.5.2.19 Line status register (LSR)

The line status register provides the information concerning the data transfers.

The LSR register is read only. Table 227 shows the bit assignment of the LSR register.

Table 227. LSR register bit description

Legend: * reset value

Bit

Symbol Access Value

Description

31 to 7 reserved

-

reserved; read as logic 0

transmitter empty

6

5

TEMT

THRE

R

1*

the transmitter holding register and the transmitter shift

register are both empty; the transmitter empty bit is

cleared when either the transmitter holding register or

the transmitter shift register contains a data character

0

R

transmitter holding register empty

1*

the transmitter holding register is empty; if the

transmitter holding register empty interrupt enable is set,

an interrupt is generated; the transmitter holding register

empty bit is set when the contents of the transmitter

holding register is transferred to the transmitter shift

register; the transmitter holding register empty bit is

cleared concurrently with loading the transmitter holding

register

0

1

4

BI

R

break interrupt

the received data input was held low for longer than a

full-word transmission time; a full-word transmission time

is deﬁned as the total time to transmit the start, data,

parity, and stop bits; the break interrupt bit is cleared

upon reading; the UART tries to resynchronize after a

framing error; to accomplish this, it is assumed that the

framing error is due to the next start bit; the UART

samples this start bit twice and then accepts the input

data

0*

1

3

FE

R

framing error

the received character did not have a valid (set) stop bit;

the framing error is cleared upon reading; the next

character transfer is enabled after the RXD input line

goes to the marking state (1s) for at least two sample

times and then receives the next valid start bit

0*

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Table 227. LSR register bit description …continued

Legend: * reset value

Bit

Symbol Access Value

Description

2

PE

R

parity error

1

the parity of the received data character does not match

the parity selected in the line control register; the parity

error is cleared upon reading

0*

1

0

OE

R

overrun error

the character in the receiver buffer register was

overwritten by the next character transferred into this

register before it was read; the overrun error is cleared

upon reading

0*

1

DR

R

data ready

a complete incoming character has been received and

transferred to the receiver buffer register; the data ready

bit is cleared by reading the data in the receiver buffer

register

0*

8.5.2.20 Scratch register (SCR)

The scratch register is intended for the programmer’s use as scratch pad in the sense that

it temporarily holds the programmer’s data without affecting any other UART operation.

Table 228 shows the bit assignment of the SCR register.

Table 228. SCR register bit description

Legend: * reset value

Bit

31 to 8 reserved

7 to 0 SCR[7:0] R/W

Symbol Access Value

Description

-

reserved; do not modify, write as logic 0, read as logic 0

00h*

scratch register; this register can be written and/or read at

the discretion of the user

8.6 Vectored interrupt controller

8.6.1 Overview

The SJA 2020 contains a very ﬂexible and powerful Vectored Interrupt Controller (VIC) to

interrupt the ARM processor on request.

The key features are:

• Level active interrupt request with programmable polarity

• 31 interrupt requests inputs

• Software interrupt request capability associated to each request input

• Observability of interrupt request state before masking

• Software programmable priority assignments to interrupt request up to 15 levels

• Software programmable routing of interrupt requests towards the ARM processor

inputs IRQ and FIQ

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• Fast identiﬁcation of interrupt request through vector

• Support for nesting of interrupt service routines

The vectored interrupt controller routes incoming interrupt requests to the ARM processor.

The interrupt target is conﬁgured for each interrupt request input of the interrupt controller.

The targets are deﬁned as follows:

• Target 0 is ARM processor IRQ (standard interrupt service)

• Target 1 is ARM processor FIQ (fast interrupt service)

Interrupt request masking is performed individually per interrupt target by comparing the

priority level assigned to a speciﬁc interrupt request with a target speciﬁc priority

threshold. The priority levels are deﬁned as follows:

• Priority level 0 corresponds to ‘masked’; interrupt requests with priority 0 will never

lead to an interrupt request

• Priority 1 corresponds to the lowest priority

• Priority 15 corresponds to the highest priority

Software interrupt support is provided and can be supplied for:

• Test the RTOS interrupt handling without using device speciﬁc interrupt service

routines

• Software emulation of an interrupt requesting device, including interrupts

8.6.2 VIC pin description

The vectored interrupt controller module in the SJA2020 has no external pins.

8.6.3 Register mapping

The vectored interrupt controller registers are shown in Table 229. The vectored interrupt

controller registers have an offset to the base address VIC RegBase which can be found

in the memory map (see Table 7).

Table 229. Vectored interrupt controller register summary

Address Access Reset

value

Name

Description

Reference

000h

004h

100h

104h

200h

300h

404h

R/W

R

-

INT_PRIORITY MASK_0 target 0 priority mask see Table 230

register

INT_PRIORITY MASK_1 target 1 priority mask see Table 230

register

INT_VECTOR_0

target 0 vector

register

see Table 231

see Table 232

see Table 233

see Table 235

INT_VECTOR_1

target 1 vector

register

INT_ PENDING_1_31

interrupt pending

status register

R

1 0F1Fh INT_FEATURES

interrupt controller

features register

R/W

-

INT_REQUEST_1

interrupt request 1

control register

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Table 229. Vectored interrupt controller register summary …continued

Address Access Reset

Name

Description

Reference

value

408h

40Ch

410h

414h

418h

41Ch

420h

424h

428h

42Ch

430h

434h

438h

43Ch

440h

444h

448h

44Ch

450h

454h

458h

45Ch

460h

R/W

-

INT_REQUEST_2

INT_REQUEST_3

INT_REQUEST_4

INT_REQUEST_5

INT_REQUEST_6

INT_REQUEST_7

INT_REQUEST_8

INT_REQUEST_9

INT_REQUEST_10

INT_REQUEST_11

INT_REQUEST_12

INT_REQUEST_13

INT_REQUEST_14

INT_REQUEST_15

INT_REQUEST_16

INT_REQUEST_17

INT_REQUEST_18

INT_REQUEST_19

INT_REQUEST_20

INT_REQUEST_21

INT_REQUEST_22

INT_REQUEST_23

INT_REQUEST_24

interrupt request 2

control register

see Table 235

-

interrupt request 3

control register

interrupt request 4

control register

interrupt request 5

control register

interrupt request 6

control register

interrupt request 7

control register

interrupt request 8

control register

interrupt request 9

control register

interrupt request 10

control register

interrupt request 11

control register

interrupt request 12

control register

interrupt request 13

control register

interrupt request 14

control register

interrupt request 15

control register

interrupt request 16

control register

interrupt request 17

control register

interrupt request 18

control register

interrupt request 19

control register

interrupt request 20

control register

interrupt request 21

control register

interrupt request 22

control register

interrupt request 23

control register

interrupt request 24

control register

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Table 229. Vectored interrupt controller register summary …continued

Address Access Reset

Name

Description

Reference

value

464h

468h

46Ch

470h

474h

478h

47Ch

R/W

-

INT_REQUEST_25

INT_REQUEST_26

INT_REQUEST_27

INT_REQUEST_28

INT_REQUEST_29

INT_REQUEST_30

INT_REQUEST_31

interrupt request 25

control register

see Table 235

-

interrupt request 26

control register

interrupt request 27

control register

interrupt request 28

control register

interrupt request 29

control register

interrupt request 30

control register

interrupt request 31

control register

8.6.4 Interrupt priority mask register (INT_PRIORITYMASK)

The interrupt priority mask registers deﬁne the thresholds for priority level masking. Each

interrupt target has its own priority limiter. The priority limiter can be used to deﬁne the

minimum priority level for nesting interrupts; typically, the priority limiter is set to the

priority level of the interrupt service routine that is currently being executed. By doing this,

only interrupt requests at a higher priority level will lead to a nested interrupt service.

Nesting can be disabled by setting the priority level to Fh in the interrupt request register.

Table 230 shows the bit assignment of the INT_PRIORITYMASK_n registers.

Table 230. INT_PRIORITYMASK register bit description

Legend: * reset value

Bit

Symbol

Access Value Description

31 to 4 reserved

-

reserved; do not modify, read as logic 0,

write as logic 0

3 to 0 PRIORITY_LIMITER[3:0] R/W

-

priority limiter; this register determines a

priority threshold that incoming interrupt

requests must exceed to trigger interrupt

requests towards the CPU and the event

router

8.6.5 Interrupt vector register (INT_VECTOR)

The interrupt vector registers identify, individually for each interrupt target, the highest

priority enabled pending interrupt request that is present at the time when the register is

being read. The software interrupt service routine must always read the vector register

that corresponds to the interrupt target. The interrupt vector content can be used as vector

into a memory based table like shown in Figure 13. This table has 32 entries. To be able to

use the register content as a full 32-bit address pointer, the table must be aligned to a

256 byte address boundary (or 2048 to be future proof). If only the index variable is used

as offset into the table, then this address alignment is not required. Each table entry has

64-bit width. It is recommended to pack per table entry:

• The start address of a peripheral speciﬁc interrupt service routine, plus

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• The associated priority limiter value (if nesting of interrupt service routine shall be

performed)

A vector with index 0 indicates that no interrupt with priority above the priority threshold is

pending. The vector table should implement for this entry a ‘no interrupt’ handler to treat

this special case.

Interrupt service routine 2

Entry point

Interrupt service routine 1

Index

Priority limiter 2

010h

Vector 2

Entry point

Pointer

00Ch

008h

Priority limiter 1

Vector 1

unused

Vector 0

no interrupt handler

004h

TABLE_ADDR + 000h

Entry point

Interrupt vector table

in memory

Device specific

interrupt service routine

in memory

001aaa172

Fig 13. Memory based interrupt vector and priority table

Table 231 shows the bit assignment of the INT_VECTOR register.

Table 231. INT_VECTOR register bit description

Legend: * reset value

Bit

Symbol

Access Value Description

31 to 11 TABLE_ADDR[20:0] R/W

-

table start address; indicates the lower address

boundary of a 256 byte aligned vector table in

memory; to be compatible with future extension

an address boundary of 2048 byte is

recommended

10 to 8

7 to 3

reserved

-

reserved; read as logic 0

INDEX[4:0]

R

index; indicates the interrupt request line of the

interrupt request to be served by the controller:

INDEX = 0 means no interrupt request to be

served

INDEX = 1 means serve interrupt request at

input 1

INDEX = n means serve interrupt request at

input n

2 to 0

NULL[2:0]

R

-

always reﬂecting logic 0s

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8.6.6 Interrupt pending register (INT_PENDING_1_31)

The interrupt pending register gathers the pending bits of all interrupt request registers.

Software can make use of the interrupt pending to gain a faster overview on pending

interrupts than by reading the individual interrupt request registers.

The INT_PENDING_1_31 register is read only.

Table 232 shows the bit assignment of the INT_PENDING_1_31 register.

Table 232. INT_PENDING_1_31 register bit description

Legend: * reset value

Bit

Symbol

Access Value Description

31 to 1 PENDING

R

-

pending interrupt request; the bit position reﬂects the

pending state of the corresponding interrupt request line

1

0

-

an interrupt request is pending

there is no interrupt request

reserved; read as logic 0

0

reserved

-

8.6.7 Interrupt controller features register (INT_FEATURES)

The interrupt controller features register indicates the vectored interrupt controller

conﬁguration of which an ISR can make use of for implementing interrupt controller

conﬁguration speciﬁc behavior.

The INT_FEATURES register is read only.

Table 233 shows the bit assignment of the INT_FEATURES register.

Table 233. INT_FEATURES register bits

Legend: * reset value

Bit

Symbol

Access Value

Description

31 to 16 reserved

-

reserved; read as don’t care

number of targets (minus one)

number of priorities (minus one)

number of interrupt requests

21 to 16

15 to 8

7 to 0

T

P

N

R

01h*

0Fh*

1Fh*

8.6.8 Interrupt request register (INT_REQUEST)

The reference between the interrupt source and interrupt request line is reﬂected in

Table 234.

Table 234. Interrupt source and request reference

Interrupt Interrupt source

request

Activation Description

level

1

2

3

4

5

6

7

timer 0

timer 1

timer 2

timer 3

UART

SPI 0

low

capture or match interrupt from timer 0

low

capture or match interrupt from timer 1

capture or match interrupt from timer 2

capture or match interrupt from timer 3

general interrupt from 16C550 UART

general interrupt from SPI 0

low

high

SPI 1

general interrupt from SPI 1

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Table 234. Interrupt source and request reference …continued

Interrupt Interrupt source

request

Activation Description

level

8

9

SPI 2

high

general interrupt from SPI 2

event router

event, wake-up or real time clock tick interrupt from

event router

10

11

12

13

14

15

ADC

high

low

conversion scan completed interrupt from ADC

signature, burn or erase ﬁnished interrupt from ﬂash

debug underﬂow interrupt from watchdog

communications RX for ARM debug mode

communications TX for ARM debug mode

general interrupt from LIN master controller 0

ﬂash

watchdog

embedded RT-ICE high

LIN master

controller 0

high

16

17

18

19

LIN master

controller 1

general interrupt from LIN master controller 1

general interrupt from LIN master controller 2

general interrupt from LIN master controller 3

LIN master

controller 2

LIN master

controller 3

all CAN controllers high

combined general interrupt of all CAN controllers

and the CAN Look-Up table ^[1]

20

21

22

23

24

25

26

27

28

29

30

31

CAN controller 0

CAN controller 1

CAN controller 2

CAN controller 3

CAN controller 4

CAN controller 5

CAN controller 0

CAN controller 1

CAN controller 2

CAN controller 3

CAN controller 4

CAN controller 5

high

message received interrupt from CAN controller 0 ^[2]

message received interrupt from CAN controller 1 ^[2]

message received interrupt from CAN controller 2 ^[2]

message received interrupt from CAN controller 3 ^[2]

message received interrupt from CAN controller 4 ^[2]

message received interrupt from CAN controller 5 ^[2]

message transmitted interrupt from CAN controller 0

message transmitted interrupt from CAN controller 1

message transmitted interrupt from CAN controller 2

message transmitted interrupt from CAN controller 3

message transmitted interrupt from CAN controller 4

message transmitted interrupt from CAN controller 5

[1] Combined general interrupt of all CAN controllers and the CAN look-up table; the following interrupts are

combined here: error warning interrupt (EWI), data overrun interrupt (DOI), error passive interrupt (EPI),

arbitration lost interrupt (ALI), bus error interrupt (BEI) and look-up table error interrupt (CALUTE); see

Section 8.5.1.7 and Section 8.5.1.33 for details.

[2] Message received interrupt from CAN controller x; the Receive Interrupt (RI) and the ID ready interrupt (IDI)

are combined here; see Section 8.5.1.7 for details.

The interrupt request registers hold the conﬁguration information related to interrupt

request inputs of the interrupt controller and allow to issue software interrupt requests.

Each interrupt line has its own interrupt request register.

Table 235 shows the bit assignment of the INT_REQUEST register.

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Table 235. INT_REQUEST register bit description

Legend: * reset value

Bit

Symbol

Access Value Description

31

PENDING

R/W

pending interrupt request; reﬂects the state

of the interrupt source channel; the pending

status is also visible in the interrupt pending

register. Writing this bit has no effect.

1

0

an interrupt request is pending

there is no interrupt request

set software interrupt request

30

29

SET_SWINT

CLR_SWINT

1

0

writing logic 1 sets the local software

interrupt request state

writing a logic 0 has no effect on the local

software interrupt request state; this bit is

always read as logic 0

clear software interrupt request

1

0

writing logic 1 clears the local software

interrupt request state

writing a logic 0 has no effect on the local

software interrupt request state; this bit is

always read as logic 0

28

27

WE_PRIORITY_LEVEL R/W

write enable priority level

1

0

writing logic 1 enables the bit state change

during the same register access

writing logic 0 does not change the bit state;

this bit is always read as logic 0

WE_TARGET

R/W

write enable target

1

writing logic 1 enables the bit state change

during the same register access; for

changing the bit state, software must ﬁrst

disable the interrupt request

(bit ENABLE = 0), then change this bit and

ﬁnally re-enable the interrupt request

(bit ENABLE = 1) again

0

writing logic 0 does not change this bit state;

this bit is always read as logic 0

26

25

WE_ENABLE

WE_ACTIVE_LOW

reserved

R/W

-

write enable

1

0

writing logic 1 enables this bit state change

during the same register access

writing logic 0 does not change this bit state;

this bit is always read as logic 0

write enable active LOW

1

0

writing logic 1 enables the bit state change

during the same register access

writing logic 0 does not change the bit state;

this bit is always read as logic 0

24 to

18

reserved; do not modify, write as logic 0,

read as logic 0

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Table 235. INT_REQUEST register bit description …continued

Legend: * reset value

Bit

Symbol

Access Value Description

17

ACTIVE_LOW

R/W

active LOW interrupt line; selects the polarity

of the interrupt request line; state changing is

only possible if the corresponding write

enable bit has been set

1

the interrupt request is active LOW

the interrupt request is active HIGH

0*

16

ENABLE

R/W

enable interrupt request; controls the

interrupt request processing by the interrupt

controller; state changing is only possible if

the corresponding write enable bit has been

set

1

the interrupt request may cause an ARM

processor interrupt request if further

conditions for this become true

0*

-

the interrupt request is discarded and will not

cause an ARM processor interrupt

15 to 9 reserved

TARGET

-

reserved; do not modify, write as logic 0,

read as logic 0

8

R/W

interrupt target; deﬁnes the interrupt target of

an interrupt request; state changing is only

possible if the corresponding write enable bit

has been set

1

0*

-

the target is the FIQ

the target is the IRQ

7 to 4 reserved

-

reserved; do not modify, write as logic 0,

read as logic 0

3 to 0 PRIORITY_LEVEL[3:0] R/W

-

interrupt priority level; determines the priority

level of the interrupt request; state changing

is only possible if the corresponding write

enable bit has been set

1

0

priority level 0 masks the interrupt request,

thus it is ignored

priority level 1 has the lowest priority level

and 15 the highest

9. Limiting values

Table 236. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Supply pins

P_tot

Parameter

Conditions

Min

Max

Unit

[1]

total power dissipation

core supply voltage

-

1

W

V

V_DD(CORE)

−0.5

+2.0

V_{DD(OSC_PLL)}oscillator and PLL supply

voltage

V

V_DD(RTC)

RTC supply voltage

−0.5

+2.0

V

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Table 236. Limiting values …continued

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DD(ADC)

V_DD(IO)

I_DD

Parameter

Conditions

Min

−0.5

-

Max

+3.6

+4.6

98

Unit

V

ADC supply voltage

I/O supply voltage

supply current

V

[2]

average value

per supply pin

mA

I_SS

ground current

average value

per ground pin

-

98

mA

Input pins and I/O pins

V_{XIN_OSC}

V_{XIN_RTC}

V_I(IO)

voltage on pin XIN_OSC

−0.5

+2.0

V

voltage on pin XIN_RTC

I/O input voltage

[3][4]

[5]

DC input voltage on 5 V

tolerant port pins

−0.5

V_DD(IO)

+ 3.0

V

DC input voltage on all

other I/O and input pins

V_DD(IO)

+ 0.5

V_I(ADC)

V_VREFN

I_I(ADC)

ADC input voltage

voltage on pin VREFN

ADC input current

−0.5

-

+3.6

35

V

[2]

average value

per input pin

mA

Output pins and I/O pins conﬁgured as output

[6]

I_OHS

HIGH-state short-circuit

output current

drive high,

output shorted

to V_SS(IO)

-

33

mA

I_OLS

LOW-state short-circuit

output current

drive low,

output shorted

to V_DD(IO)

−38

General

T_stg

storage temperature

−40

+150

+105

+125

°C

T_amb

ambient temperature

virtual junction temperature

[7]

T_vj

Memory

n_endu(ﬂ)

t_ret(ﬂ)

endurance of ﬂash memory

ﬂash memory retention time

-

1000

20

cycle

year

ESD

V_esd

electrostatic discharge

voltage

on all pins

HBM

[8]

[9]

−2000

−200

−500

+2000

+200

+500

V

MM

[10]

[11]

CDM

on corner pins

CDM

[10]

−750

+750

V

[1] Based on package heat transfer, not device power consumption.

[2] Peak current must be limited at 25 times average current.

[3] V_DD(IO)must be present.

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[4] Not 5 V tolerant when pull-up is on.

[5] 6 V should not be exceeded.

[6] 112 mA per V_DD(IO)or V_SS(IO)should not be exceeded.

[7] In accordance with IEC 60747-1. An alternative deﬁnition of the virtual junction temperature is:

T_vj= T_amb+ P_tot× R_th(j-a)where R_th(j-a)is a ﬁxed value (see Section 10). The rating for T_vjlimits the

allowable combinations of power dissipation and ambient temperature.

[8] Human body model: according AEC-Q100 Rev-F, H2.

[9] Machine model: according AEC-Q100 Rev-F, M3.

[10] Charged device model: according AEC-Q100 Rev-F, C3B.

[11] Except for the V_{DD(OSC_PLL)}pin, which is guaranteed up to 375 V.

10. Thermal characteristics

Table 237. Thermal characteristics

Symbol

Parameter

Conditions

Typ

Unit

R_th(j-a)

thermal resistance from junction in free air

to ambient

50

K/W

11. Static characteristics

Table 238. Static characteristics

V_DD(CORE)= V_{DD(OSC_PLL)}= V_DD(RTC)= 1.8 V ± 5 %; V_DD(IO)= 2.7 V to 3.6 V; V_DD(ADC)= 3.0 V to 3.6 V;

T_vj= −40 °C to +125 °C; all voltages are measured with respect to ground; positive currents ﬂow into the IC; unless otherwise

speciﬁed ^[1]

.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Supplies

Core supply

V_DD(CORE)

I_DD(CORE)

core supply voltage

core supply current

1.71

-

1.80

1.1

1.89

1.2

V

[2]

[3]

ARM7 and all peripherals

active

mA/MHz

all clocks off

-

10

-

300

3.6

µA

V

I/O supply

V_DD(IO)

I/O supply voltage

2.7

1.71

Oscillator

V_{DD(OSC_PLL)}oscillator and PLL

supply voltage

1.80

1.89

V

I_{DD(OSC_PLL)}oscillator and PLL

supply current

start-up

1.5

-

3

1

mA

µA

normal

-

power-down

Real time clock

V_DD(RTC)

I_DD(RTC)

RTC supply voltage

RTC supply current

1.71

1.80

1.89

6

V

normal

-

µA

power-down

1

Analog-to-digital converter

V_DD(ADC)

ADC supply voltage

3.0

3.3

3.6

V

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Table 238. Static characteristics …continued

V_DD(CORE)= V_{DD(OSC_PLL)}= V_DD(RTC)= 1.8 V ± 5 %; V_DD(IO)= 2.7 V to 3.6 V; V_DD(ADC)= 3.0 V to 3.6 V;

T_vj= −40 °C to +125 °C; all voltages are measured with respect to ground; positive currents ﬂow into the IC; unless otherwise

speciﬁed ^[1]

.

Symbol

Parameter

Conditions

normal

Min

Typ

Max

400

1

Unit

µA

I_DD(ADC)

ADC supply current

-

power-down

µA

Input pins and I/O pins conﬁgured as input

[4]

V_I

input voltage

all port pins and V_DD(IO)

applied

−0.5

-

+5.5

V

all port pins and V_DD(IO)not

applied

+3.6

all other I/O pins, RESET_N,

TRST_N, TDI, JTAGSEL,

TMS, TCK

V_DD(IO)

V_IH

V_IL

HIGH-state input

voltage

all port pins, RESET_N,

TRST_N, TDI, JTAGSEL,

TMS, TCK

2.0

-

V

LOW-state input

voltage

all port pins, RESET_N,

TRST_N, TDI, JTAGSEL,

TMS, TCK

0.8

V_hys

I_LIH

hysteresis voltage

0.4

-

V

HIGH-state input

leakage current

1

µA

I_LIL

LOW-state input

leakage current

-

1

µA

I_I(pd)

I_I(pu)

pull-down input current all port pins, V_I= 3.3 V;

V_I= 5.5 V

25

−25

50

−50

100

−100

pull-up input current

all port pins, RESET_N,

TRST_N, TDI, JTAGSEL,

TMS: V_I= 0 V; V_I> 3.6 V is

not allowed

C_i

input capacitance

-

8

pF

Output pins and I/O pins conﬁgured as output

V_O

output voltage

0

-

V_DD(IO)

-

V

V_OH

HIGH-state output

voltage

TDO: I_OH= −8 mA; all other

pins: I_OH= −4 mA

V_DD(IO)– 0.4

V_OL

LOW-state output

voltage

TDO: I_OL= 8 mA; all other

pins: I_OL= 4 mA

-

0.4

V

Analog-to-digital converter

V_VREFN

voltage on pin VREFN

0

V_DD(ADC)

− 2

V_I

Z_i

input voltage

at pins AI0, AI1, AI2, AI3

V_VREFN

-

V_DD(ADC)

-

V

input impedance

between V_VREFNand

V_DD(ADC)

30

kΩ

C_i

input capacitance

full scale range

at pins AI0, AI1, AI2, AI3

-

1

pF

FSR

INL

2

10

+1

bit

[5]

integral non-linearity

−1

LSB

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Table 238. Static characteristics …continued

V_DD(CORE)= V_{DD(OSC_PLL)}= V_DD(RTC)= 1.8 V ± 5 %; V_DD(IO)= 2.7 V to 3.6 V; V_DD(ADC)= 3.0 V to 3.6 V;

T_vj= −40 °C to +125 °C; all voltages are measured with respect to ground; positive currents ﬂow into the IC; unless otherwise

speciﬁed ^[1]

Symbol

DNL

.

Parameter

Conditions

Min

−1

Typ

Max

+1

Unit

LSB

mV

[5]

[6]

differential non-linearity

offset error voltage

full-scale error voltage

-

V_err(offset)

V_err(FS)

−20

+20

mV

Oscillator

R_s(xtal)

crystal series

resistance

f_osc= 10 MHz to 15 MHz

C_xtal= 10 pF;

-

160

60

Ω

C

_L(ext)= 18 pF

C_xtal= 20 pF;

_L(ext)= 39 pF

C

[6]

f_osc= 15 MHz to 20 MHz

C_xtal= 10 pF;

-

80

Ω

C

_L(ext)= 18 pF

Real time clock

R_s(xtal)crystal series

resistance

[6]

C_xtal= 11 pF; C_L(ext)= 18 pF

C_xtal= 13 pF; C_L(ext)= 22 pF

C_xtal= 15 pF; C_L(ext)= 27 pF

-

100

Ω

Power-up reset

[7]

V_trip(high)

V_trip(low)

V_trip(dif)

high trip level voltage

on V_DD(CORE)

1.2

1.1

50

1.4

1.3

120

1.6

1.5

180

V

low trip level voltage

V

difference between

high and low trip level

voltage

mV

[1] All parameters are guaranteed over the virtual junction temperature range by design. Production testing is performed at T_amb= 125 °C

on wafer level. Cased products are tested at T_amb= 25 °C. Production testing uses correlated test conditions to cover the speciﬁed

temperature and power supply voltage range.

[2] Excluding ﬂash programming and erasing.

[3] Leakage current is exponential to temperature; worst case value is at T_vj= 125 °C.

[4] Not 5 V tolerant when pull-up is on.

[5] INL and DNL are indirectly measured during production test by measuring the Dynamic Noise Reduction (DNR) and Effective Numbers

of Bits (ENB).

[6] C_xtalis crystal load capacitance and C_L(ext)are the two external load capacitors.

[7] The power-up reset has a time ﬁlter: V_DD(CORE)must be above V_trip(high)for 2 µs before the internal reset is de-asserted; V_DD(CORE)must

be below V_trip(low)for 11 µs before internal reset is asserted.

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12. Dynamic characteristics

Table 239. Dynamic characteristics

V_DD(CORE)= V_{DD(OSC_PLL)}= V_DD(RTC)= 1.8 V ± 5 %; V_DD(IO)= 2.7 V to 3.6 V; V_DD(ADC)= 3.0 V to 3.6 V;

T_vj= −40 °C to +125 °C; all voltages are deﬁned with respect to ground; positive currents ﬂow into the IC; unless otherwise

speciﬁed ^[1]

Symbol

I/O pins

t_THL

.

Parameter

Conditions

Min

Typ

Max

Unit

HIGH-to-LOW

transition time

30 pF load capacitance

4

-

13.8

ns

t_TLH

LOW-to-HIGH

transition time

Internal clock

f_clk(sys)

system clock

frequency

10

16

-

60

MHz

ns

T_clk(sys)

system clock period

100

Ring oscillator

f_ref(RO)

RO reference

frequency

before ringo calibration

(CRFS) and post (CRPD)

dividers

1.0

-

1.80

MHz

[2]

t_startup

start-up time

at maximum frequency

-

6

-

100

1

µs

t_jit(cc)(p-p)

cycle-to-cycle jitter

ns

(peak-to-peak value)

Oscillator

f_i(osc)

oscillator input

frequency

10

-

20

MHz

[3]

[2]

t_startup

start-up time

-

500

-

µs

t_jit(cc)(p-p)

cycle-to-cycle jitter

240

ps

(peak-to-peak value)

PLL

f_o(PLL)

PLL output

frequency

10

-

60

MHz

f_CCO

CCO frequency

start-up time

156

-

320

100

300

MHz

µs

[2]

t_startup

t_jit(cc)(p-p)

-

cycle-to-cycle jitter

ps

(peak-to-peak value)

Real time clock

f_i(RTC)

RTC input frequency

-

32.768

-

kHz

s

[2]

t_startup

start-up time

-

1

t_jit(cc)(p-p)

cycle-to-cycle jitter

20

ns

(peak-to-peak value)

Analog-to-digital converter

f_i(ADC)

ADC input frequency

-

4.5

MHz

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Table 239. Dynamic characteristics …continued

V_DD(CORE)= V_{DD(OSC_PLL)}= V_DD(RTC)= 1.8 V ± 5 %; V_DD(IO)= 2.7 V to 3.6 V; V_DD(ADC)= 3.0 V to 3.6 V;

T_vj= −40 °C to +125 °C; all voltages are deﬁned with respect to ground; positive currents ﬂow into the IC; unless otherwise

speciﬁed ^[1]

Symbol

f_s

.

Parameter

Conditions

Min

Typ

Max

Unit

sampling frequency f_i(ADC)= 4.5 MHz;

f_s= f_i(ADC)/ (n+1) with

n = resolution

in kilo samples per

second

400

-

1500

ksample/s

in bits

10

3

-

2

bit

t_conv

conversion time

in number of ADC clock

cycles

11

cycle

in number of bits

2

-

10

bit

Flash

t_init

initialization time

clock access time

address access time

page write time

-

150

67.5

49

-

µs

ns

ms

ns

t_a(clk)

t_a(A)

-

[4]

[2]

t_wr(pg)

t_er(sect)

t_ﬂ(BIST)

1

sector erase time

ﬂash word BIST time

100

42

-

70

External static memory controller

[2]

t_a(R)int

internal read access

time

-

18

19

ns

t_a(W)int

internal write access

time

UART

f_UART

SPI

UART frequency

1/65024f_clk(sys)

-

1/2f_clk(sys)MHz

f_SPI

SPI operating

frequency

master operation

slave operation

1/65024f_clk(sys)

-

1/2f_clk(sys)MHz

1/12f_clk(sys)MHz

[1] All parameters are guaranteed over the virtual junction temperature range by design. Pre-testing is performed at T_amb= 125 °C on wafer

level. Cased products are tested at T_amb= 25 °C. Production testing uses correlated test conditions to cover the speciﬁed temperature

and power supply voltage range.

[2] This parameter is not part of production test; worst case ﬁgure stated is based on simulations.

[3] Oscillator start-up time depends on the quality of the crystal. For most crystals it takes about 1000 clock pulses until the clock is fully

stable.

[4] Maximum deviation should be within ±5 %.

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13. Package outline

LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm

SOT486-1

y

X

A

108

109

73

72

Z

E

e

H

A

E

2

A

E

(A )

3

A

1

θ

w M

p

L

p

b

L

pin 1 index

detail X

37

144

1

36

v

M

A

Z

w M

D

b

p

e

D

B

H

v

M

B

D

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

E

θ

1

2

3

p

E

p

D

max.

7^o

0^o

0.15 1.45

0.05 1.35

0.27 0.20 20.1 20.1

0.17 0.09 19.9 19.9

22.15 22.15

21.85 21.85

0.75

0.45

1.4

1.1

1.4

1.1

mm

1.6

0.25

1

0.2 0.08 0.08

0.5

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-03-14

03-02-20

SOT486-1

136E23

MS-026

Fig 14. Package outline SOT486-1 (LQFP144)

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14. Soldering

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

14.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

14.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus PbSn soldering

14.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

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14.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 15) than a PbSn process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 240 and 241

Table 240. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 241. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 15.

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maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 15. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

15. References

[1] UM — SJA2020 User manual

[2] ANKI — SJA2020 Application note ‘Known issues’

[3] ARM — ARM web site

[4] ARM-SSP — ARM PrimeCell synchronous serial port (PL022) technical reference

manual

[5] CAN — ISO 11898-1: 2002 road vehicles - Controller Area Network (CAN) - part 1:

data link layer and physical signalling

[6] LIN — LIN speciﬁcation package, revision 2.0

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16. Revision history

Table 242. Revision history

Document ID

SJA2020_2

Release date

20061124

Data sheet status

Change notice

Supersedes

Product data sheet

-

SJA2020_1

Modiﬁcations:

• The status of this data sheet has been changed from Objective data sheet to Product data

sheet.

• The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• In Figure 1, the memory types for the ﬂash controller and static RAM controller have been

changed to “Embedded”.

• Throughout the data sheet, the “static memory” has been changed to “external static

memory”.

• Text has been changed in the second paragraph of Section 8.1.7.

• Values have been changed in Table 8, Table 237 and Table 238.

• A new Table 14 has been created and inserted.

• Table notes have been added to Table 209, Table 211 and Table 238.

SJA2020_1

20060405

Objective data sheet

-

(9397 750 12148)

SJA2020_2

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17. Legal information

17.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of a NXP Semiconductors product can reasonably be expected to

17.2 Deﬁnitions

result in personal injury, death or severe property or environmental damage.

NXP Semiconductors accepts no liability for inclusion and/or use of NXP

Semiconductors products in such equipment or applications and therefore

such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

17.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

17.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

18. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

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19. Contents

1

1.1

1.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

About this document. . . . . . . . . . . . . . . . . . . . . 1

Intended audience . . . . . . . . . . . . . . . . . . . . . . 1

8.1.10

8.1.11

8.1.12

8.1.13

Flash BIST signature registers

(FMSW0, FMSW1, FMSW2 and FMSW3). . . 28

Flash interrupt status register

(INT_STATUS) . . . . . . . . . . . . . . . . . . . . . . . . 29

Flash set interrupt status

(INT_SET_STATUS). . . . . . . . . . . . . . . . . . . . 29

Flash clear interrupt status

(INT_CLR_STATUS) . . . . . . . . . . . . . . . . . . . 30

Flash interrupt enable (INT_ENABLE). . . . . . 30

Flash set interrupt enable

(INT_SET_ENABLE) . . . . . . . . . . . . . . . . . . . 30

Flash clear interrupt enable

(INT_CLR_ENABLE) . . . . . . . . . . . . . . . . . . . 31

External static memory controller. . . . . . . . . . 31

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

External static memory controller

2

General description . . . . . . . . . . . . . . . . . . . . . . 1

Architectural overview. . . . . . . . . . . . . . . . . . . . 1

ARM7TDMI-S processor. . . . . . . . . . . . . . . . . . 1

On-chip ﬂash memory system . . . . . . . . . . . . . 2

On-chip static RAM. . . . . . . . . . . . . . . . . . . . . . 2

2.1

2.2

2.3

2.4

8.1.14

8.1.15

3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Flash memory. . . . . . . . . . . . . . . . . . . . . . . . . . 3

CAN gateway . . . . . . . . . . . . . . . . . . . . . . . . . . 3

LIN master controller . . . . . . . . . . . . . . . . . . . . 3

3.1

3.2

3.3

3.4

8.1.16

8.2

8.2.1

8.2.2

4

5

Ordering information. . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

pin description . . . . . . . . . . . . . . . . . . . . . . . . 32

Register mapping. . . . . . . . . . . . . . . . . . . . . . 32

Bank idle cycle control registers

(SMBIDCYR) . . . . . . . . . . . . . . . . . . . . . . . . . 34

Bank wait state 1 control registers

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

8.2.3

8.2.4

7

7.1

7.2

7.3

7.4

7.5

7.5.1

7.5.2

7.5.3

7.5.4

7.5.5

7.5.6

Functional description . . . . . . . . . . . . . . . . . . . 9

Reset and power-up behavior. . . . . . . . . . . . . . 9

JTAG interface and debug pins. . . . . . . . . . . . . 9

Power supply pins description . . . . . . . . . . . . . 9

Clock architecture. . . . . . . . . . . . . . . . . . . . . . 10

Memory maps. . . . . . . . . . . . . . . . . . . . . . . . . 11

Region 0: remap area. . . . . . . . . . . . . . . . . . . 12

Region 1: embedded ﬂash area . . . . . . . . . . . 12

Region 2: not used . . . . . . . . . . . . . . . . . . . . . 13

Region 3: internal SRAM area . . . . . . . . . . . . 13

Region 4: not used . . . . . . . . . . . . . . . . . . . . . 15

Region 5: external static memory

8.2.5

8.2.6

8.2.7

8.2.8

(SMBWST1R) . . . . . . . . . . . . . . . . . . . . . . . . 34

Bank wait state 2 control registers

(SMBWST2R) . . . . . . . . . . . . . . . . . . . . . . . . 35

Bank output enable assertion delay control

register (SMBWSTOENR) . . . . . . . . . . . . . . . 35

Bank write enable assertion delay control

register (SMBWSTWENR). . . . . . . . . . . . . . . 36

Bank conﬁguration register (SMBCR) . . . . . . 36

Bank status register (SMBSR) . . . . . . . . . . . . 37

General subsystem . . . . . . . . . . . . . . . . . . . . 38

Clock generation unit . . . . . . . . . . . . . . . . . . . 38

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

CGU pin description. . . . . . . . . . . . . . . . . . . . 38

Register mapping. . . . . . . . . . . . . . . . . . . . . . 38

Clock switch conﬁguration register (CSC) . . . 40

Clock frequency select registers

8.2.9

8.2.10

8.3

8.3.1

controller area. . . . . . . . . . . . . . . . . . . . . . . . . 15

Region 6: not used . . . . . . . . . . . . . . . . . . . . . 16

Region 7: bus peripherals area. . . . . . . . . . . . 16

Memory map concepts operation . . . . . . . . . . 17

8.3.1.1

8.3.1.2

8.3.1.3

8.3.1.4

8.3.1.5

8.3.1.6

7.5.7

7.5.8

7.5.9

8

8.1

Block description. . . . . . . . . . . . . . . . . . . . . . . 19

Flash memory controller. . . . . . . . . . . . . . . . . 19

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Flash memory controller pin description. . . . . 21

Flash memory layout . . . . . . . . . . . . . . . . . . . 21

Register mapping . . . . . . . . . . . . . . . . . . . . . . 23

Flash control register (FCTR) . . . . . . . . . . . . . 24

Flash program time register (FPTR). . . . . . . . 25

Flash bridge wait states register (FBWST). . . 26

Flash clock divider register (FCRA) . . . . . . . . 27

Flash BIST control registers

8.1.1

8.1.2

8.1.3

8.1.4

8.1.5

8.1.6

8.1.7

8.1.8

8.1.9

(CFS1 and CFS2) . . . . . . . . . . . . . . . . . . . . . 40

Clock switch status register (CSS). . . . . . . . . 41

Clock power control registers

(CPC0, CPC1, CPC2, CPC3 and CPC4). . . . 41

Clock power status registers

8.3.1.7

8.3.1.8

8.3.1.9

(CPS0, CPS1, CPS2, CPS3 and CPS4) . . . . 42

8.3.1.10 Fractional clock enable register (CFCE4). . . . 43

8.3.1.11 Fractional clock divider register (CFD) . . . . . . 43

8.3.1.12 Power mode register (CPM). . . . . . . . . . . . . . 44

8.3.1.13 Watchdog bark register (CWDB) . . . . . . . . . . 44

(FMSSTART and FMSSTOP) . . . . . . . . . . . . . 27

continued >>

SJA2020_2

Product data sheet

Rev. 02 — 24 November 2006

173 of 176

SJA2020

NXP Semiconductors

ARM7 microcontroller with CAN and LIN controllers

8.3.1.14 Real time clock oscillator power mode register

(CRTCOPM) . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.3.5.1

8.3.5.2

8.3.5.3

8.3.5.4

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

ADC pin description . . . . . . . . . . . . . . . . . . . . 68

Register mapping. . . . . . . . . . . . . . . . . . . . . . 69

ADC channel conversion data registers

(ACD0 to ACD7). . . . . . . . . . . . . . . . . . . . . . . 69

ADC control register (ACON) . . . . . . . . . . . . . 70

ADC channel conﬁguration register (ACC). . . 71

ADC interrupt enable register (AIE) . . . . . . . . 72

ADC interrupt status register (AIS). . . . . . . . . 72

ADC interrupt clear register (AIC) . . . . . . . . . 72

Event router . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Event router pin description and mapping to

8.3.1.15 Oscillator power mode register (COPM). . . . . 45

8.3.1.16 Oscillator lock status register (COLS). . . . . . . 45

8.3.1.17 PLL clock source select register (CPCSS) . . . 46

8.3.1.18 PLL Power-down mode register (CPPDM) . . . 46

8.3.1.19 PLL lock status register (CPLS) . . . . . . . . . . . 46

8.3.1.20 PLL multiplication ratio register (CPMR). . . . . 47

8.3.1.21 PLL post divider register (CPPD) . . . . . . . . . . 47

8.3.1.22 Ring oscillator power mode register (CRPM) . 48

8.3.1.23 Ring oscillator post divider register (CRPD) . . 48

8.3.1.24 Ring oscillator frequency select register

8.3.5.5

8.3.5.6

8.3.5.7

8.3.5.8

8.3.5.9

8.3.6

8.3.6.1

8.3.6.2

(CRFS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

8.3.2

System control unit . . . . . . . . . . . . . . . . . . . . . 50

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

SCU pin description . . . . . . . . . . . . . . . . . . . . 50

Register mapping . . . . . . . . . . . . . . . . . . . . . . 50

Shadow memory mapping register (SSMM). . 51

Port function select registers (SFSAP0 to

register bit positions . . . . . . . . . . . . . . . . . . . . 73

Register mapping. . . . . . . . . . . . . . . . . . . . . . 74

Event status register (PEND) . . . . . . . . . . . . . 74

Event status clear register (INT_CLR) . . . . . . 75

Event status set register (INT_SET). . . . . . . . 75

Event enable register (MASK) . . . . . . . . . . . . 75

Event enable clear register (MASK_CLR) . . . 76

Event enable set register (MASK_SET). . . . . 76

8.3.2.1

8.3.2.2

8.3.2.3

8.3.2.4

8.3.2.5

8.3.6.3

8.3.6.4

8.3.6.5

8.3.6.6

8.3.6.7

8.3.6.8

8.3.6.9

SFSAP2 and SFSBP0 to SFSBP2) . . . . . . . . 51

Pull-up control registers

8.3.2.6

(SPUCP0, SPUCP1 and SPUCP2) . . . . . . . . 55

SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

SPI pin description . . . . . . . . . . . . . . . . . . . . . 56

Register mapping . . . . . . . . . . . . . . . . . . . . . . 56

SPI control register 0 (SSPCR0) . . . . . . . . . . 56

SPI control register 1 (SSPCR1) . . . . . . . . . . 58

SPI FIFO data register (SSPDR) . . . . . . . . . . 59

SPI status register (SSPSR). . . . . . . . . . . . . . 60

SPI clock prescale register (SSPCPSR). . . . . 60

SPI interrupt enable register (SSPIMSC) . . . . 61

8.3.6.10 Activation polarity register (APR) . . . . . . . . . . 76

8.3.6.11 Activation type register (ATR). . . . . . . . . . . . . 77

8.3.6.12 Raw status register (RSR) . . . . . . . . . . . . . . . 77

8.3.3

8.3.3.1

8.3.3.2

8.3.3.3

8.3.3.4

8.3.3.5

8.3.3.6

8.3.3.7

8.3.3.8

8.3.3.9

8.3.7

Real-time clock. . . . . . . . . . . . . . . . . . . . . . . . 78

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

RTC pin description . . . . . . . . . . . . . . . . . . . . 78

Register mapping. . . . . . . . . . . . . . . . . . . . . . 78

RTC elapsed time seconds register

8.3.7.1

8.3.7.2

8.3.7.3

8.3.7.4

(RTC_TIME_SECONDS) . . . . . . . . . . . . . . . . 78

RTC seconds fraction register

(RTC_TIME_FRACTION). . . . . . . . . . . . . . . . 79

RTC real time offset register

(RTC_PORTIME) . . . . . . . . . . . . . . . . . . . . . . 79

RTC real time control register

8.3.7.5

8.3.7.6

8.3.7.7

8.3.3.10 SPI raw interrupt status register (SSPRIS). . . 61

8.3.3.11 SPI masked interrupt status register

(SSPMIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

8.3.3.12 SPI interrupt clear register (SSPICR) . . . . . . . 63

(RTC_CONTROL) . . . . . . . . . . . . . . . . . . . . . 79

Peripheral subsystem. . . . . . . . . . . . . . . . . . . 80

Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Timer pin description . . . . . . . . . . . . . . . . . . . 80

Register mapping. . . . . . . . . . . . . . . . . . . . . . 81

Timer interrupt register (IR) . . . . . . . . . . . . . . 81

Timer control register (TCR) . . . . . . . . . . . . . 82

Timer counter (TC). . . . . . . . . . . . . . . . . . . . . 82

Prescale register (PR) . . . . . . . . . . . . . . . . . . 83

Prescale counter (PC) . . . . . . . . . . . . . . . . . . 83

Match control register (MCR). . . . . . . . . . . . . 83

8.3.4

Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Watchdog pin description . . . . . . . . . . . . . . . . 64

Register mapping . . . . . . . . . . . . . . . . . . . . . . 64

Watchdog mode register (WDMOD). . . . . . . . 64

Watchdog reload value register (WDRV) . . . . 65

Watchdog counter value register (WDCV) . . . 65

Watchdog trigger register (WDTRIG) . . . . . . . 66

Watchdog interrupt set status (WDISS) . . . . . 66

Watchdog interrupt clear status (WDICS). . . . 66

8.4

8.4.1

8.3.4.1

8.3.4.2

8.3.4.3

8.3.4.4

8.3.4.5

8.3.4.6

8.3.4.7

8.3.4.8

8.3.4.9

8.4.1.1

8.4.1.2

8.4.1.3

8.4.1.4

8.4.1.5

8.4.1.6

8.4.1.7

8.4.1.8

8.4.1.9

8.3.4.10 Watchdog interrupt enable (WDIE). . . . . . . . . 67

8.3.4.11 Watchdog interrupt status register (WDIS). . . 67

8.3.4.12 Watchdog interrupt set enable (WDISE). . . . . 67

8.3.4.13 Watchdog interrupt clear enable (WDICE) . . . 68

8.4.1.10 Match registers (MR0 to MR3). . . . . . . . . . . . 85

8.4.1.11 Capture control register (CCR) . . . . . . . . . . . 85

8.4.1.12 Capture registers (CR0 to CR3). . . . . . . . . . . 87

8.4.1.13 External match register (EMR). . . . . . . . . . . . 87

8.3.5

Analog-to-digital converter . . . . . . . . . . . . . . . 68

continued >>

SJA2020_2

Product data sheet

Rev. 02 — 24 November 2006

174 of 176

SJA2020

NXP Semiconductors

ARM7 microcontroller with CAN and LIN controllers

8.4.2

UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

8.5.1.16 CAN controller transmit buffer message info

register (CCTXB1MI, CCTXB2MI

and CCTXB3MI). . . . . . . . . . . . . . . . . . . . . . 118

8.5.1.17 CAN controller transmit buffer identiﬁer

register (CCTXB1ID, CCTXB2ID

and CCTXB3ID) . . . . . . . . . . . . . . . . . . . . . . 119

8.5.1.18 CAN controller transmit buffer data

A register (CCTXB1DA, CCTXB2DA

and CCTXB3DA) . . . . . . . . . . . . . . . . . . . . . 120

8.5.1.19 CAN controller transmit buffer data

B register (CCTXB1DB, CCTXB2DB

8.4.2.1

8.4.2.2

8.4.2.3

8.4.2.4

8.4.2.5

8.4.2.6

8.4.2.7

8.4.2.8

8.4.2.9

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

UART pin description . . . . . . . . . . . . . . . . . . . 88

Register mapping . . . . . . . . . . . . . . . . . . . . . . 89

Receive buffer register (RBR). . . . . . . . . . . . . 89

Transmit holding register (THR) . . . . . . . . . . . 90

Interrupt enable register (IER) . . . . . . . . . . . . 90

Interrupt ID register (IIR). . . . . . . . . . . . . . . . . 90

FIFO control register (FCR) . . . . . . . . . . . . . . 91

Line control register (LCR) . . . . . . . . . . . . . . . 92

8.4.2.10 Line status register (LSR). . . . . . . . . . . . . . . . 93

8.4.2.11 Scratch register (SCR) . . . . . . . . . . . . . . . . . . 95

8.4.2.12 Divisor latch LSB and divisor latch

and CCTXB3DB) . . . . . . . . . . . . . . . . . . . . . 120

8.5.1.20 Global acceptance ﬁlter . . . . . . . . . . . . . . . . 121

8.5.1.21 Standard frame format FullCAN

MSB registers (DLL and DLM) . . . . . . . . . . . . 96

8.4.3

General purpose I/O. . . . . . . . . . . . . . . . . . . . 96

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

GPIO pin description . . . . . . . . . . . . . . . . . . . 97

Register mapping . . . . . . . . . . . . . . . . . . . . . . 97

Port input register (PINS) . . . . . . . . . . . . . . . . 97

Port output register (OR) . . . . . . . . . . . . . . . . 97

Port direction register (DR). . . . . . . . . . . . . . . 98

In-vehicle networking subsystem . . . . . . . . . . 98

CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

CAN pin description . . . . . . . . . . . . . . . . . . . . 98

Register mapping . . . . . . . . . . . . . . . . . . . . . . 99

CAN controller mode register

(CCMODE) . . . . . . . . . . . . . . . . . . . . . . . . . . 101

CAN controller command register

(CCCMD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

CAN controller global status register

(CCGS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

CAN controller interrupt and capture

register (CCIC) . . . . . . . . . . . . . . . . . . . . . . . 106

CAN controller interrupt enable

identiﬁer section . . . . . . . . . . . . . . . . . . . . . . 122

8.5.1.22 Standard frame format explicit

identiﬁer section . . . . . . . . . . . . . . . . . . . . . . 124

8.5.1.23 Standard frame format group

identiﬁer section . . . . . . . . . . . . . . . . . . . . . . 125

8.5.1.24 Extended frame format explicit

identiﬁer section . . . . . . . . . . . . . . . . . . . . . . 125

8.5.1.25 Extended frame format group

8.4.3.1

8.4.3.2

8.4.3.3

8.4.3.4

8.4.3.5

8.4.3.6

8.5

8.5.1

identiﬁer section . . . . . . . . . . . . . . . . . . . . . . 126

8.5.1.26 CAN acceptance ﬁlter mode

8.5.1.1

8.5.1.2

8.5.1.3

8.5.1.4

register (CAMODE) . . . . . . . . . . . . . . . . . . . 126

8.5.1.27 CAN acceptance ﬁlter standard frame

explicit start address register (CASFESA) . . 127

8.5.1.28 CAN acceptance ﬁlter standard frame

group start address register (CASFGSA). . . 127

8.5.1.29 CAN acceptance ﬁlter extended frame

explicit start address register (CAEFESA) . . 128

8.5.1.30 CAN acceptance ﬁlter extended frame group

start address register (CAEFGSA). . . . . . . . 128

8.5.1.31 CAN acceptance ﬁlter end of look up table

address register (CAEOTA) . . . . . . . . . . . . . 129

8.5.1.32 CAN acceptance ﬁlter look-up table error

address register (CALUTEA) . . . . . . . . . . . . 130

8.5.1.33 CAN acceptance ﬁlter look-up table error

register (CALUTE) . . . . . . . . . . . . . . . . . . . . 130

8.5.1.34 CAN controllers central transmit status

register (CCCTS) . . . . . . . . . . . . . . . . . . . . . 130

8.5.1.35 CAN controllers central receive status

register (CCCRS). . . . . . . . . . . . . . . . . . . . . 132

8.5.1.36 CAN controllers central miscellaneous

status register (CCCMS) . . . . . . . . . . . . . . . 134

8.5.1.5

8.5.1.6

8.5.1.7

8.5.1.8

8.5.1.9

register (CCIE) . . . . . . . . . . . . . . . . . . . . . . . 110

CAN controller bus timing register

(CCBT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

8.5.1.10 CAN controller error warning limit register

(CCEWL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

8.5.1.11 CAN controller status register

(CCSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

8.5.1.12 CAN controller receive buffer message

info register (CCRXBMI). . . . . . . . . . . . . . . . 116

8.5.1.13 CAN controller receive buffer identiﬁer

register (CCRXBID) . . . . . . . . . . . . . . . . . . . 117

8.5.1.14 CAN controller receive buffer data

A register (CCRXBDA) . . . . . . . . . . . . . . . . . 117

8.5.1.15 CAN controller receive buffer data

B register (CCRXBDB) . . . . . . . . . . . . . . . . . 118

8.5.2

LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

LIN pin description . . . . . . . . . . . . . . . . . . . . 136

Register mapping. . . . . . . . . . . . . . . . . . . . . 136

LIN master controller mode register

8.5.2.1

8.5.2.2

8.5.2.3

8.5.2.4

(LMODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

continued >>

SJA2020_2

Product data sheet

Rev. 02 — 24 November 2006

175 of 176

SJA2020

NXP Semiconductors

ARM7 microcontroller with CAN and LIN controllers

8.5.2.5

8.5.2.6

8.5.2.7

8.5.2.8

8.5.2.9

LIN master controller conﬁguration register

(LCFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

LIN master controller command register

(LCMD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

LIN master controller fractional baud rate

generator register (LFBRG) . . . . . . . . . . . . . 140

LIN master controller status register

(LSTAT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

LIN master controller interrupt and capture

register (LIC). . . . . . . . . . . . . . . . . . . . . . . . . 142

15

16

References. . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Revision history . . . . . . . . . . . . . . . . . . . . . . 171

17

Legal information . . . . . . . . . . . . . . . . . . . . . 172

Data sheet status . . . . . . . . . . . . . . . . . . . . . 172

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . 172

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . 172

17.1

17.2

17.3

17.4

18

19

Contact information . . . . . . . . . . . . . . . . . . . 172

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

8.5.2.10 LIN master controller interrupt enable

register (LIE). . . . . . . . . . . . . . . . . . . . . . . . . 144

8.5.2.11 LIN master controller checksum register

(LCS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

8.5.2.12 LIN master controller time-out register

(LTO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

8.5.2.13 LIN master controller message buffer

registers (LID, LDATA, LDATB, LDATC

and LDATD) . . . . . . . . . . . . . . . . . . . . . . . . . 146

8.5.2.14 Receive buffer register (RBR). . . . . . . . . . . . 148

8.5.2.15 Transmit holding register (THR) . . . . . . . . . . 148

8.5.2.16 Interrupt enable register (IER) . . . . . . . . . . . 149

8.5.2.17 Interrupt ID register (IIR). . . . . . . . . . . . . . . . 149

8.5.2.18 Line control register (LCR) . . . . . . . . . . . . . . 150

8.5.2.19 Line status register (LSR). . . . . . . . . . . . . . . 151

8.5.2.20 Scratch register (SCR) . . . . . . . . . . . . . . . . . 152

8.6

Vectored interrupt controller . . . . . . . . . . . . . 152

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

VIC pin description . . . . . . . . . . . . . . . . . . . . 153

Register mapping . . . . . . . . . . . . . . . . . . . . . 153

Interrupt priority mask register

8.6.1

8.6.2

8.6.3

8.6.4

(INT_PRIORITYMASK) . . . . . . . . . . . . . . . . 155

Interrupt vector register (INT_VECTOR). . . . 155

Interrupt pending register

8.6.5

8.6.6

(INT_PENDING_1_31) . . . . . . . . . . . . . . . . . 157

Interrupt controller features register

(INT_FEATURES). . . . . . . . . . . . . . . . . . . . . 157

Interrupt request register

8.6.7

8.6.8

(INT_REQUEST) . . . . . . . . . . . . . . . . . . . . . 157

9

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . 160

Thermal characteristics. . . . . . . . . . . . . . . . . 162

Static characteristics. . . . . . . . . . . . . . . . . . . 162

Dynamic characteristics . . . . . . . . . . . . . . . . 165

Package outline . . . . . . . . . . . . . . . . . . . . . . . 167

10

11

12

13

14

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Introduction to soldering . . . . . . . . . . . . . . . . 168

Wave and reﬂow soldering . . . . . . . . . . . . . . 168

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 168

Reﬂow soldering . . . . . . . . . . . . . . . . . . . . . . 169

14.1

14.2

14.3

14.4

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 24 November 2006

Document identifier: SJA2020_2


型号：	SJA2020HL/623
厂家：	NXP
描述：	IC 32-BIT, FLASH, 60 MHz, RISC MICROCONTROLLER, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-486-1, LQFP-144, Microcontroller 时钟微控制器外围集成电路
文件：	总176页 (文件大小：721K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SJA2020HL/623 [NXP]

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