SL3S1214FTB01 [NXP]
UCODE 7m;型号: | SL3S1214FTB01 |
厂家: | NXP |
描述: | UCODE 7m |
文件: | 总34页 (文件大小:308K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SL3S1214
UCODE 7m
Rev. 3.4 — 6 March 2019
307434
Product data sheet
COMPANY PUBLIC
1 General description
UCODE 7m is a derivative of the UCODE 7 and offers on top of the UCODE 7 features a
32-bit User Memory.
NXP’s UCODE 7m IC is the leading-edge EPC Gen2 RFID chip that offers best-in-class
performance and features for use in the most demanding RFID tagging applications.
Particularly well suited for inventory management application, like e.g Retail and Fashion,
with its leading edge RF performance for any given form factor, UCODE 7m enables
long read distance and fast inventory of dense RFID tag population. With its broadband
design, it offers the possibility to manufacture true global RFID label with best-in-class
performance over worldwide regulations.
The device also provides a pre-serialized 96-bit EPC, and a Parallel encoding feature.
For applications where the same 58-bit Stock Keeping Unit (SKU) needs to be encoded
on multiple tags, at the same time, a combination of both features improves and
simplifies the tag initialization process.
On top UCODE 7m offers a Tag Power Indicator for RFID tag initialization optimization
and a Product Status Flag for Electronic Article Surveillance (EAS) application.
NXP Semiconductors
SL3S1214
UCODE 7m
2 Features and benefits
2.1 Key features
• Read sensitivity -21 dBm
• Write sensitivity -16 dBm
• Parallel encoding mode: 100 items in 60ms
• Encoding speed: 16 bits per millisecond
• Innovative functionalities
– Tag Power Indicator
– Pre-serialization for 96-bit EPC
– Integrated Product Status Flag (PSF)
• Compatible with single-slit antenna
• Up to 128-bit EPC
• 96-bit Unique Tag Identifier (TID) factory locked,
including 48-bit unique serial number
• 32-bit User Memory
• EPC Gen2 v2.0 ready
2.1.1 Memory
• 32-bit User Memory
• Up to 128-bit of EPC memory
• Pre-serialization for 96-bit EPC
• 96-bit Tag IDentifier (TID) factory locked
• 48-bit unique serial number factory-encoded into TID
• 32-bit access password
• Wide operating temperature range: -40 °C up to +85 °C
• Minimum 100.000 write cycle endurance
2.2 Key benefits
2.2.1 End user benefit
• Long READ and WRITE ranges due to leading edge chip sensitivity
• Very fast bulk encoding
• Product identification through unalterable extended TID range, including a 48-bit serial
number
• Reliable operation in dense reader and noisy environments through high interference
rejection
2.2.2 Antenna design benefits
• High sensitivity enables smaller and cost efficient antenna designs for the same retail
category
• Tag Power Indicator features enables very high density of inlay on rolls without cross-
talk issues during writing/encoding
SL3S1214
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SL3S1214
UCODE 7m
• The different input capacitance for the single slit antenna solution enables a finer tuning
of the impedance for the antenna design
2.2.3 Label manufacturer benefit
• Large RF pad-to-pad distance to ease antenna design
• Symmetric RF inputs are less sensitive to process variation
• Single slit antenna for a more mechanically stable antenna connection
• Automatic self pre-serialization of the 96-bit EPC anytime its EPC serial number is
erased
• Extremely fast encoding of the EPC content
2.3 Supported features
• All mandatory commands of EPC global specification V.1.2.0 are implemented
including:
– (Perma)LOCK
• The following optional commands are implemented in conformance with the EPC
specification:
– Access
– BlockWrite (2 words, 32-bit)
• Product Status Flag bit: enables the UHF RFID tag to be used as EAS
(Electronic Article Surveillance) tag without the need for a back-end data base.
• Tag Power Indicator: enables the reader to select only ICs/tags that have enough
power to be written to.
• Parallel encoding: allows for the ability to bring (multiple) tag(s) quickly to the OPEN
state and hence allowing single tags to be identified simply, without timing restrictions,
or multiple tags to be e.g. written to at the same time, considerably reducing the
encoding process
All supported features of UCODE 7m can be activated using standard EPCglobal READ /
WRITE / ACCESS / SELECT commands. No custom commands are needed to take
advantage of all the features in case of unlocked EPC memory. The parallel encoding
feature may however require a firmware upgrade of the reader to use its full potential.
SL3S1214
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SL3S1214
UCODE 7m
3 Applications
3.1 Markets
• Retail/Fashion (apparel, footwear, jewelry, cosmetics)
• Fast Moving Consumer Goods
3.2 Applications
• Retail Inventory management
• Supply chain management
• Loss prevention
• Asset management
Outside the applications mentioned above, please contact NXP Semiconductors for
support.
SL3S1214
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SL3S1214
UCODE 7m
4 Ordering information
Table 1.ꢀOrdering information
Type number
Package
Name
IC type
Description
Version
SL3S1214FUD/BG1 Wafer
UCODE 7m
bumped die on sawn 8" 120 μm wafer 7 μm Polyimide not applicable
spacer
SL3S1214FTB0/1
XSON6
UCODE 7m
plastic extremely thin small outline package; no leads; SOT886F1
6 terminals; body 1 × 1.45 × 0.5 mm
SL3S1214
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SL3S1214
UCODE 7m
5 Marking
Table 2.ꢀMarking codes
Type number
Marking code
Comment
Version
SL3S1214FTB0/1
YN
UCODE 7m
SOT886
SL3S1214
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SL3S1214
UCODE 7m
6 Block diagram
The SL3S1214 IC consists of three major blocks:
- Analog Interface
- Digital Control
- EEPROM
The analog part provides stable supply voltage and demodulates data received from the
reader which is then processed by the digital part. Further, the modulation transistor of
the analog part transmits data back to the reader.
The digital section includes the state machines, processes the protocol and handles
communication with the EEPROM, which contains the EPC and the user data.
ANALOG
RF INTERFACE
DIGITAL CONTROL
ANTICOLLISION
EEPROM
VREG
VDD
RF1
READWRITE
CONTROL
data
in
RECT
RF2
DEMOD
MOD
MEMORY
antenna
ACCESS CONTROL
data
out
R/W
EEPROM INTERFACE
CONTROL
RF INTERFACE
CONTROL
SEQUENCER
CHARGE PUMP
aaa-005856
Figure 1.ꢀBlock diagram of UCODE 7m IC
SL3S1214
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SL3S1214
UCODE 7m
7 Pinning information
TP1
RF2
SL3S1214 trademark
SL3S12x4FTB0
RF2
n.c.
n.c.
1
2
3
6
5
4
RF1
n.c.
n.c.
TP2
RF1
aaa-018831
Transparent top view
aaa-013423
Figure 2.ꢀPinning bare die
Figure 3.ꢀPin configuration for SOT886
7.1 Pin description
Table 3.ꢀPin description bare die
Symbol
TP1
Description
test pad 1
RF1
antenna connector 1
test pad 2
TP2
RF2
antenna connector 2
Table 4.ꢀPin description SOT886
Pin
1
Symbol
RF2
n.c.
Description
antenna connector
not connected
not connected
not connected
not connected
antenna connector
2
3
n.c.
4
n.c.
5
n.c.
6
RF1
SL3S1214
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UCODE 7m
8 Wafer layout
8.1 Wafer layout
(1)
TP1
RF2
(5)
Y
(4)
(6)
X
(7)
TP2
RF1
(8)
(2)
(3)
not to scale!
aaa-005606
1. Die to Die distance (metal sealring - metal sealring) 21,4 μm, (X-scribe line width: 15 μm)
2. Die to Die distance (metal sealring - metal sealring) 21,4 μm, (Y-scribe line width: 15 μm)
3. Chip step, x-length: 460 μm
4. Chip step, y-length: 505 μm
5. Bump to bump distance X (TP1 - RF2): 358 μm
6. Bump to bump distance Y (RF1 - RF2): 403 μm
7. Distance bump to metal sealring X: 40,3 μm (outer edge - top metal)
8. Distance bump to metal sealring Y: 40,3 μm
Bump size X x Y: 60 μm x 60 μm
Remark: TP1 and TP2 are physically disconnected
Figure 4.ꢀUCODE 7m wafer layout
SL3S1214
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UCODE 7m
9 Mechanical specification
The UCODE 7m wafer is available in 120 μm thickness with 7 μm Polyimide spacer.
9.1 Wafer specification
See [2].
9.1.1 Wafer
Table 5.ꢀSpecifications
Wafer
Designation
each wafer is scribed with batch number and
wafer number
Diameter
200 mm (8") unsawn - 205 mm typical sawn
on foil
Thickness
SL3S1214FUD/BG
Number of pads
Pad location
120 μm ± 15 μm
4
non-diagonal / placed in chip corners
Distance pad to pad RF1-RF2
Distance pad to pad TP1-RF2
Process
403.0 μm
358.0 μm
CMOS 0.14 μm
25 wafers
126.524
Batch size
Potential good dies per wafer
Wafer backside
Material
Si
Treatment
ground and stress release
Ra max. 0.5 μm, Rt max. 5 μm
Roughness
Chip dimensions
Die size excluding scribe
Scribe line width:
0.490 mm × 0.445 mm = 0.218 mm2
x-dimension = 15 μm
y-dimension = 15 μm
Passivation on front
Type
Sandwich structure
Material
PE-Nitride (on top)
Thickness
1.75 μm total thickness of passivation
7 μm ± 1 μm (SL3S1214FUD/BG only)
Polyimide spacer
Au bump
Bump material
Bump hardness
> 99.9 % pure Au
35 – 80 HV 0.005
SL3S1214
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UCODE 7m
Bump shear strength
Bump height
SL3S1214FUD/BG
> 70 MPa
25 μm[1]
Bump height uniformity
within a die
± 2 μm
± 3 μm
± 4 μm
± 1.5 μm
– within a wafer
– wafer to wafer
Bump flatness
Bump size
– RF1, RF2
60 × 60 μm
60 × 60 μm
± 5 μm
– TP1, TP2
Bump size variation
[1] Because of the 7 μm spacer, the bump will measure 18 μm relative height protruding the spacer.
9.1.2 Fail die identification
No ink dots are applied to the wafer.
Electronic wafer mapping (SECS II format) covers the electrical test results and
additionally the results of mechanical/visual inspection.
See [2]
9.1.3 Map file distribution
See [2]
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UCODE 7m
10 Functional description
10.1 Air interface standards
The UCODE 7m fully supports all parts of the "Specification for RFID Air Interface
EPCglobal, EPC Radio-Frequency Identity Protocols, Class-1 Generation-2 UHF RFID,
Protocol for Communications at 860 MHz to 960 MHz, Version 1.2.0".
10.2 Power transfer
The interrogator provides an RF field that powers the tag, equipped with a UCODE 7m.
The antenna transforms the impedance of free space to the chip input impedance in
order to get the maximum possible power for the UCODE 7m on the tag.
The RF field, which is oscillating on the operating frequency provided by the interrogator,
is rectified to provide a smoothed DC voltage to the analog and digital modules of the IC.
The antenna that is attached to the chip may use a DC connection between the two
antenna pads. Therefore the UCODE 7m also enables loop antenna design.
10.3 Data transfer
10.3.1 Interrogator to tag Link
An interrogator transmits information to the UCODE 7m by modulating an UHF RF
signal. The UCODE 7m receives both information and operating energy from this RF
signal. Tags are passive, meaning that they receive all of their operating energy from the
interrogator's RF waveform.
An interrogator is using a fixed modulation and data rate for the duration of at least one
inventory round. It communicates to the UCODE 7m by modulating an RF carrier.
For further details refer to [1]. Interrogator-to-tag (R=>T) communications.
10.3.2 Tag to interrogator Link
Upon transmitting a valid command an interrogator receives information from a UCODE
7m tag by transmitting an unmodulated RF carrier and listening for a backscattered
reply. The UCODE 7m backscatters by switching the reflection coefficient of its antenna
between two states in accordance with the data being sent. For further details refer to [1],
chapter 6.3.1.3.
The UCODE 7m communicates information by backscatter-modulating the amplitude
and/or phase of the RF carrier. Interrogators shall be capable of demodulating either
demodulation type.
The encoding format, selected in response to interrogator commands, is either FM0
baseband or Miller-modulated subcarrier.
10.4 Supported commands
The UCODE 7m supports all mandatory EPCglobal V1.2.0 commands including
• (perma) LOCK command
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UCODE 7m
In addition the UCODE 7m supports the following optional commands:
• ACCESS
• Block Write (32 bit)
The Kill Password of the UCODE 7m is zero-valued and permanent read/write locked,
which disallows the IC from being killed.
10.5 UCODE 7m memory
The UCODE 7m memory is implemented according EPCglobal Class1Gen2 and
organized in three sections:
Table 6.ꢀUCODE 7m memory sections
Name
Size
Bank
00b
01b
01b
10b
11b
Reserved memory (32-bit Kill password and 32-bit Access password)
EPC (excluding 16 bit CRC-16 and 16 bit PC)
UCODE 7m Configuration Word
64 bit
128 bit
16 bit
96 bit
32 bit
TID (including permalocked unique 48 bit serial number)
User Memory
The logical address of all memory banks begin at zero (00h).
In addition to the four memory banks one configuration word to handle the UCODE 7m
specific features is available at EPC bank 01 address bit-200h. The configuration word is
described in detail in 9.6.
The TID complies to the extended tag Identification scheme according GS1 EPC Tag
Data Standard 1.6.
10.5.1 UCODE 7m overall memory map
Table 7.ꢀUCODE 7m overall memory map
Bank
address
Memory
address
Type
Content
Initial
Remark
Bank 00
00h to 1Fh
20h to 3Fh
00h to 0Fh
reserved
reserved
EPC
Kill password
Access password
CRC-16
hard wired 00h
all 00h
permanent read/write locked
unlocked memory
Bank 01
EPC
memory mapped calculated
CRC
10h to 14h
15h
EPC
EPC
EPC
EPC
EPC
EPC
EPC
EPC
EPC
EPC length
UMI
00110b
0b
unlocked memory
unlocked memory
hardwired to 0
16h
XPC indicator
0b
17h to 1Fh
20h to 9Fh
200h
numbering system indicator 00h
unlocked memory
unlocked memory
locked memory
locked memory
Action bit[2]
[1]
EPC
Bank 01
RFU
0b
0b
0b
0b
Config Word
201h
RFU
202h
Parallel encoding
RFU
203h
locked memory
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SL3S1214
UCODE 7m
Bank
address
Memory
address
Type
Content
Initial
Remark
204h
EPC
EPC
EPC
EPC
EPC
EPC
EPC
EPC
EPC
EPC
EPC
EPC
TID
Tag Power Indicator
0b
Action bit[2]
205h
RFU
0b
locked memory
locked memory
locked memory
locked memory
permanent bit[3]
locked memory
locked memory
locked memory
locked memory
locked memory
Permanent bit[3]
locked memory
206h
RFU
0b
207h
RFU
0b
208h
RFU
0b
209h
max. backscatter strength
1b
20Ah
RFU
0b
20Bh
RFU
0b
20Ch
RFU
0b
20Dh
RFU
0b
20Eh
RFU
0b
20Fh
PSF alarm flag
allocation class identifier
0b
Bank 10
TID
00h to 07h
08h to 13h
14h
1110 0010b
TID
tag mask designer identifier 1000 0000 0110b locked memory
TID
config word indicator
tag model number
XTID header
1b[4]
locked memory
locked memory
locked memory
locked memory
unlocked memory
14h to 1Fh
20h to 2Fh
30h to 5Fh
TID
TMNR[5]
2000h
SNR
TID
TID
Serial Number
Bank 11 User 00h to 1Fh
Memory
UM
User memory
all 00h
[1] HEX E280 6891 0000 nnnn nnnn nnnn
where n are the nibbles of the SNR from the TID
[2] Action bits: meant to trigger a feature upon a SELECT command on the related bit, see Section 10.6.1
[3] Permanent bit: permanently stored bits in the memory; Read/Writeable according to EPC bank lock status, see Section 10.6.1
[4] Indicates the existence of a Configuration Word at the end of the EPC number
[5] See Figure 5
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SL3S1214
UCODE 7m
10.5.2 UCODE 7m TID memory details
Model Number
Sub
Mask
Designer
ID
First 48 bit of TID
Config
Word
Indicator
Class ID
E2h
Version
XTID
Header
memory
Version Nr. (Silicon) Nr.
UCODE 7m E28068912000
806h
1b
0001b 0010001b
2000h
Addresses 00h
5Fh
TID
MS Byte
LS Byte
MSBit
00h
LSBit
MSBit
LSBit
5Fh
Bit
Address
07h 08h
13h 14h
1Fh 20h
2Fh 30h
Serial Number
Class Identifier
Mask-Designer Identifier
Model Number
XTID
11
15
Bits
7
0
11
0
0
0
47
0
E2h
(EAN.UCC)
806h
(NXP; with XTID)
891h
(UCODE 7m)
2000h
(indication of 48bit
unique SNR)
000000000000h to FFFFFFFFFFFFh
Address
Bits
14h
18h 19h
1Fh
C.
W.
I.
Sub Version Number
0001b
Model Number
0
3
6
0
0
1b
0010001b
(UCODE 7m)
aaa-013424
Figure 5.ꢀUCODE 7m TID memory structure
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UCODE 7m
10.6 Supported features
The UCODE 7m is equipped with a number of additional features, which are
implemented in such a way that standard EPCglobal READ / WRITE / ACCESS /
SELECT commands can be used to operate these features.
The Configuration Word, as mentioned in the memory map, describes the additional
features located at address 200h of the EPC memory.
Bit 14h of the TID indicates the existence of a Configuration Word. This flag will enable
the selection of configuration word enhanced transponders in mixed tag populations.
Please refer to [3] for additional reference.
10.6.1 UCODE 7m features control mechanism
The different features of the UCODE 7m can be activated / de-activated by addressing
or changing the content of the corresponding bit in the configuration word located at
address 200h in the EPC memory bank (see Table 8). The de-activation of the action bit
features will only happen after chip reset.
Table 8.ꢀConfiguration word UCODE 7m
Locked memory
Action bit
Locked memory
RFU
RFU
Parallel
encoding
RFU
Tag Power
Indicator
RFU
RFU
RFU
0
1
2
3
4
5
6
7
Table 9.ꢀConfiguration word UCODE 7m ... continued
Locked Permanent
memory bit
Locked memory
Permanent bit
PSF Alarm bit
RFU
max.
RFU
RFU
RFU
RFU
RFU
backscatter
strength
8
9
10
11
12
13
14
15
The configuration word contains 2 different type of bits:
• Action bits: meant to trigger a feature upon a SELECT command on the related bit:
Parallel encoding
Tag Power indicator
• Permanent bits: permanently stored bits in the memory
Max. Backscatter Strength
PSF Alarm bit
The activation or the de-activation of the feature behind the permanent bits happens only
when attempting to write a "1" value to the related bit (value toggling) - writing "0" value
will have no effect.
If the feature is activated, the related bit will be read with a "1" value and, if de-activated,
with a "0" value.
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UCODE 7m
The permanent bits can only be toggled using standard EPC WRITE if the EPC bank is
unlocked or within the SECURED state if the EPC is locked. If the EPC is perma locked,
they cannot be changed.
Action bits will trigger a certain action only if the pointer of the SELECT command exactly
matches the action-bit address (i.e. 202h or 204h), if the length=1 and if mask=1b (no
multiple trigger of actions possible within one single SELECT command).
After issuing a SELECT to any action bits an interrogator shall transmit CW for RTCal [1]
+ 80 μs before sending the next command.
If the truncate bit in the SELECT command is set to "1" the SELECT will be ignored.
A SELECT on action bits will not change the digital state of the chip.
The action bits can be triggered regardless if the EPC memory is unlocked, locked or
perma locked.
10.6.2 Backscatter strength reduction
The UCODE 7m features two levels of backscatter strengths. Per default maximum
backscatter is enabled in order to enable maximum read rates. When clearing the flag
the strength can be reduced if needed.
10.6.3 Pre-serialization of the 96-bit EPC
Description
The 96-bit EPC, which is the initial EPC length settings of UCODE7, will be delivered
pre-serialized with the 48-bit serial number from the TID.
Use cases and benefits
With a pre-serialized EPC, the encoding process of the tags with UCODE 7 gets simpler
and faster as it only needs to encode the SKU (58-bit header of the EPC).
10.6.4 Parallel encoding
Description
This feature of the UCODE 7m can be activated by the "Parallel encoding bit" in the
Configuration-Word located at (202h).
Upon issuing a EPC SELECT command on the "Parallel encoding bit", in a population of
UCODE 7m tags, a subsequent QUERY brings all tags go the OPEN state with a specific
handle ("AAAAh").
Once in the OPEN state, for example a WRITE command will apply to all tags in the
OPEN state (see Figure 7). This parallel encoding is considerably lowering the encoding
time compared to a standard implementation (see Figure 6).
The amount of tags that can be encoded at the same time will depend on the strength of
the reader signal. Since all tags will backscatter their ACKNOWLEDGE (ACK) response
at the same time, the reader will observe collision in the signal from the tags.
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UCODE 7m
QUERY/Adjust/Rep
QUERY/Adjust/Rep
READER
(16-bit)
(16-bit)
TAG 1
Tags
TAG 2
Only TAG 1 is being addressed
Only TAG 2 is being addressed
aaa-006843
Figure 6.ꢀExample of 16-bit Write command with standard EPC Gen 2 commands
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UCODE 7m
SELECT on
Parallel
QUERY (Q=0)
encoding bit
(16-bit)
READER
TAG 1
TAG 2
Tags
TAG n
All UCODE 7 tags receive the Command
aaa-006844
Figure 7.ꢀIllustration of Parallel encoding for 16-bit Write command
Use cases and benefits
Parallel encoding feature of UCODE 7m can enable ultra fast bulk encoding.
Taking in addition advantage of the pre-serialization scheme of UCODE 7m, the same
SKU can be encoded in multiple tags as the EPC will be delivered pre-serialized already.
In the case of only one tag answering (like in printer encoding), this feature could be used
to save some overhead in commands to do direct EPC encoding after the handle reply.
Since this is a UCODE 7m specific feature the use of this features requires support on
the reader side.
10.6.5 Tag Power Indicator
Description
Upon a SELECT command on the "Tag Power Indicator", located in the config word
204h, an internal power check on the chip is performed to see if the power level is
sufficient to perform a WRITE command. The decision level is defined as nominal WRITE
sensitivity minus 1dB. In the case there is enough power, the SELECT command is
matching and non-matching if not enough power. The tag can then be singulated by the
standard inventory procedure.
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Use cases and benefits
This feature gives the possibility to select only the tag(s) that receive enough power to
be written during e.g. printer encoding in a dense environment of tags even though the
reader may read more than one tag (see Figure 8 for illustration). The power level still
needs to be adjusted to transmit enough writing power to one tag only to do one tag
singulation.
Power level for READ/WRITE
too low/too low
OK/too low
OK/too low
Only this tag will select itself
OK/OK
OK/too low
OK/too low
too low/too low
aaa-005662
Figure 8.ꢀSelection of tags with Tag Power Indicator feature
10.6.6 Product Status Flag (PSF)
Description
The PSF is a general purpose bit located in the Configuration word at address 20Fh with
a value that can be freely changed.
Use cases and benefits
The PSF bit can be used as an EAS (Electronic Article Surveillance) flag, quality checked
flag or similar.
In order to detect the tag with the PSF activated, a EPC SELECT command selecting
the PSF flag of the Configuration word can be used. In the following inventory round only
PSF enabled chips will reply their EPC number.
10.6.7 Single-slit antenna solution
Description
In UCODE 7m the test pads TP1 and TP2 are electrically disconnected meaning they are
not electrically active and can be safely short-circuited to the RF pads RF1 and RF2 (see
Figure 9).
Standard assembly
Single-slit assembly
Supporting pads
aaa-005857
Figure 9.ꢀStandard antenna design versus single-slit antenna
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Uses cases and benefits
Using single-slit antenna enables easier assembly and antenna design. Inlay
manufacturer will only have to take care about one slit of the antenna instead of two in
case all pads need to be disconnected from each other.
Additionally single-slit antenna assembly and the related increased input capacitance
(see Table 11) can be used advantageously over the standard antenna design as
additional room for optimization to different antenna design.
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UCODE 7m
11 Limiting values
Table 10.ꢀLimiting values[1][2]
In accordance with the Absolute Maximum Rating System (IEC 60134).
Voltages are referenced to RFN
Symbol
Parameter
Conditions
Min
Max
Unit
Bare die limitations
Tstg
storage temperature
-55
-40
-
+125
+85
± 2
°C
°C
kV
Tamb
VESD
ambient temperature
[3][4]
electrostatic discharge
voltage
Human body model
Pad limitations
Pi input power
maximum power
-
100
mW
dissipation, RFP pad
[1] Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any conditions other than those described in the
Operating Conditions and Electrical Characteristics section of this specification is not implied.
[2] This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of
excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater
than the rated maxima.
[3] ANSI/ESDA/JEDEC JS-001
[4] For ESD measurement, the die chip has been mounted into a CDIP20 package.
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Observe
precautions for handling electrostatic sensitive devices.
Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5,
JESD625-A or equivalent standards.
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UCODE 7m
12 Characteristics
12.1 UCODE 7m bare die characteristics
Table 11.ꢀUCODE 7m RF interface characteristics (RF1, RF2)
Symbol
fi
Parameter
Conditions
Min
Typ
Max
Unit
MHz
dBm
dBm
ms
ms
pF
input frequency
840
-
960
[1][2][3]
[4]
Pi(min)
Pi(min)
t 16bit
minimum input power
minimum input power
encoding speed
READ sensitivity
WRITE sensitivity
16-bit
-
-
-
-
-
-
-
-
-
-
-21
-
-
-
-
-
-
-
-
-
-
-16
[5]
1
[5]
32-bit (block write)
parallel
1.8
[2][6]
[2][6]
[2][6]
[2][6]
[8]
Ci
Z
chip input capacitance
chip impedance
0.63
866 MHz
14.5-j293
12.5-j277
12.5-j267
18-j245
13.5-j195
Ω
915 MHz
Ω
953 MHz
Ω
Z
Z
typical assembled impedance [7]
typical assembled impedance [7] in
case of single-slit antenna assembly
915MHz
Ω
[8][9]
915MHz
Ω
Tag Power Indicator mode
Pi(min) minimum input power level to be
[4]
-
-15
-
dBm
able to select the tag
[1] Power to process a QUERY command
[2] Measured with a 50 Ω source impedance directly on the chip
[3] Results in approximately -21,5dBm tag sensitivity with a 2dBi gain antenna
[4] Tag sensitivity on a 2dBi gain antenna
[5] When the memory content is "0000...".
[6] At minimum operating power
[7] Assuming a 80fF additional input capacitance, 250fF in case of single slit antenna
[8] The antenna shall be matched to this impedance
[9] Depending on the specific assembly process, sensitivity losses of few tenths of dB might occur
Table 12.ꢀUCODE 7m memory characteristics
Symbol
Parameter
Conditions
Min
Typ
Max Unit
EEPROM characteristics
tret
retention time
Tamb ≤ 55 °C
20
-
-
-
-
year
Nendu(W)
write endurance
100k
cycle
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UCODE 7m
12.2 UCODE 7m SOT886 characteristics
Table 13.ꢀUCODE 7m RF interface characteristics (RF1, RF1)
Symbol Parameter
Pi(min) minimum input power
Conditions
Min
Typ
Max Unit
[1][2]
[3]
READ
sensitivity
-
-21
-
dBm
Z
impedance
915 MHz
-
12.8 -j248
-
Ω
[1] Power to process a Query command.
[2] Measured with a 50 Ω source impedance.
[3] At minimum operating power.
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UCODE 7m
13 Package outline
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b
1
2
3
4x
(2)
L
L
1
e
6
5
4
e
e
1
1
6x
(2)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
Dimensions (mm are the original dimensions)
(1)
Unit
A
A
b
D
E
e
e
L
L
1
1
1
max 0.5 0.04 0.25 1.50 1.05
0.35 0.40
0.30 0.35
0.27 0.32
nom
min
0.20 1.45 1.00 0.6
0.17 1.40 0.95
mm
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
sot886_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
MO-252
JEITA
04-07-22
12-01-05
SOT886
Figure 10.ꢀPackage outline SOT886
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14 Packing information
14.1 Wafer
See [2]
14.2 SOT886
See: www.nxp.com/packages/SOT886.html
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UCODE 7m
15 Abbreviations
Table 14.ꢀAbbreviations
Acronym
CRC
Description
Cyclic Redundancy Check
Continuous Wave
CW
DSB-ASK
DC
Double Side Band-Amplitude Shift Keying
Direct Current
EAS
Electronic Article Surveillance
Electrically Erasable Programmable Read Only Memory
EEPROM
EPC
Electronic Product Code (containing Header, Domain Manager, Object Class
and Serial Number)
FM0
G2
Bi phase space modulation
Generation 2
IC
Integrated Circuit
PIE
PSF
RF
Pulse Interval Encoding
Product Status Flag
Radio Frequency
UHF
SECS
TID
Ultra High Frequency
Semi Equipment Communication Standard
Tag IDentifier
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16 References
[1] EPCglobal: EPC Radio-Frequency Identity Protocols Class-1 Generation-2 UHF
RFID Protocol for Communications at 860 MHz – 960 MHz, Version 1.2.0 (October
23, 2008)
[2] Data sheet - Delivery type description – General specification for 8" wafer on UV-
tape with electronic fail die marking, BU-ID document number: 1093**1
[3] Application note - AN11274 – FAQ on UCODE 7
1
** ... document version number
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17 Revision history
Table 15.ꢀRevision history
Document ID
SL3S1214 v. 3.4
Modifications:
SL3S1214 v. 3.3
Modifications:
SL3S1214 v. 3.2
Modifications:
Release date
Data sheet status
Change notice Supersedes
20190306
Product data sheet
-
-
-
SL3S1214 v. 3.3
SL3S1214 v. 3.2
SL3S1214 v. 3.1
• Section 16: updated
20161212
Product data sheet
• Figure 5: corrected
20160727
Product data sheet
• Update Automatic Pre-serialization functionality
• Figure 5 -change of TID
SL3S1214 v. 3.1
Modifications:
20150727
Product data sheet
-
-
SL3S1214 v. 3.0
-
• SOT886 package added
20141023
SL3S1214 v. 3.0
Product data sheet
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18 Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Product [short] data sheet
Qualification
Production
This document contains data from the preliminary specification.
This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
18.2 Definitions
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences
of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes
no representation or warranty that such applications will be suitable
for the specified use without further testing or modification. Customers
are responsible for the design and operation of their applications and
products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications
and products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with
their applications and products. NXP Semiconductors does not accept any
liability related to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications or products, or
the application or use by customer’s third party customer(s). Customer is
responsible for doing all necessary testing for the customer’s applications
and products using NXP Semiconductors products in order to avoid a
default of the applications and the products or of the application or use by
customer’s third party customer(s). NXP does not accept any liability in this
respect.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not
give any representations or warranties, expressed or implied, as to the
accuracy or completeness of such information and shall have no liability
for the consequences of use of such information. NXP Semiconductors
takes no responsibility for the content in this document if provided by an
information source outside of NXP Semiconductors. In no event shall NXP
Semiconductors be liable for any indirect, incidental, punitive, special or
consequential damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the removal or replacement
of any products or rework charges) whether or not such damages are based
on tort (including negligence), warranty, breach of contract or any other
legal theory. Notwithstanding any damages that customer might incur for
any reason whatsoever, NXP Semiconductors’ aggregate and cumulative
liability towards customer for the products described herein shall be limited
in accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
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UCODE 7m
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor
tested in accordance with automotive testing or application requirements.
NXP Semiconductors accepts no liability for inclusion and/or use of non-
automotive qualified products in automotive equipment or applications. In
the event that customer uses the product for design-in and use in automotive
applications to automotive specifications and standards, customer (a) shall
use the product without NXP Semiconductors’ warranty of the product for
such automotive applications, use and specifications, and (b) whenever
customer uses the product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at customer’s own
risk, and (c) customer fully indemnifies NXP Semiconductors for any liability,
damages or failed product claims resulting from customer design and use
of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Bare die — All die are tested on compliance with their related technical
specifications as stated in this data sheet up to the point of wafer sawing
and are handled in accordance with the NXP Semiconductors storage and
transportation conditions. If there are data sheet limits not guaranteed,
these will be separately indicated in the data sheet. There are no post-
packing tests performed on individual die or wafers. NXP Semiconductors
has no control of third party procedures in the sawing, handling, packing or
assembly of the die. Accordingly, NXP Semiconductors assumes no liability
for device functionality or performance of the die or systems after third party
sawing, handling, packing or assembly of the die. It is the responsibility of
the customer to test and qualify their application in which the die is used.
All die sales are conditioned upon and subject to the customer entering into
a written die sale agreement with NXP Semiconductors through its legal
department.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
18.4 Trademarks
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
UCODE — is a trademark of NXP B.V.
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UCODE 7m
Tables
Tab. 1.
Tab. 2.
Tab. 3.
Tab. 4.
Tab. 5.
Tab. 6.
Tab. 7.
Tab. 8.
Tab. 9.
Ordering information ..........................................5
Tab. 10. Limiting values ................................................ 22
Tab. 11. UCODE 7m RF interface characteristics
(RF1, RF2) ...................................................... 23
Tab. 12. UCODE 7m memory characteristics ............... 23
Tab. 13. UCODE 7m RF interface characteristics
(RF1, RF1) ...................................................... 24
Marking codes ...................................................6
Pin description bare die .................................... 8
Pin description SOT886 .................................... 8
Specifications .................................................. 10
UCODE 7m memory sections .........................13
UCODE 7m overall memory map ....................13
Configuration word UCODE 7m ...................... 16
Configuration word UCODE 7m ... continued ...16
Tab. 14. Abbreviations ...................................................27
Tab. 15. Revision history ...............................................29
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UCODE 7m
Figures
Fig. 1.
Fig. 2.
Fig. 3.
Fig. 4.
Fig. 5.
Fig. 6.
Block diagram of UCODE 7m IC .......................7
Fig. 7.
Fig. 8.
Fig. 9.
Illustration of Parallel encoding for 16-bit
Write command ............................................... 19
Selection of tags with Tag Power Indicator
feature ............................................................. 20
Standard antenna design versus single-slit
antenna ............................................................20
Pinning bare die ................................................8
Pin configuration for SOT886 ............................8
UCODE 7m wafer layout ...................................9
UCODE 7m TID memory structure ..................15
Example of 16-bit Write command with
standard EPC Gen 2 commands .................... 18
Fig. 10. Package outline SOT886 ................................ 25
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UCODE 7m
Contents
1
General description ............................................ 1
18
Legal information ..............................................30
2
2.1
Features and benefits .........................................2
Key features ...................................................... 2
Memory ..............................................................2
Key benefits .......................................................2
End user benefit ................................................ 2
Antenna design benefits ....................................2
Label manufacturer benefit ................................3
Supported features ............................................ 3
Applications .........................................................4
Markets .............................................................. 4
Applications ........................................................4
Ordering information .......................................... 5
Marking .................................................................6
Block diagram ..................................................... 7
Pinning information ............................................ 8
Pin description ...................................................8
Wafer layout ........................................................ 9
Wafer layout ...................................................... 9
Mechanical specification ..................................10
Wafer specification .......................................... 10
Wafer ............................................................... 10
Fail die identification ........................................11
Map file distribution ......................................... 11
Functional description ......................................12
Air interface standards .....................................12
Power transfer ................................................. 12
Data transfer ....................................................12
Interrogator to tag Link .................................... 12
Tag to interrogator Link ................................... 12
Supported commands ......................................12
UCODE 7m memory ........................................13
UCODE 7m overall memory map .................... 13
UCODE 7m TID memory details ..................... 15
Supported features .......................................... 16
UCODE 7m features control mechanism .........16
Backscatter strength reduction ........................ 17
Pre-serialization of the 96-bit EPC ...................17
Parallel encoding ............................................. 17
Tag Power Indicator ........................................ 19
Product Status Flag (PSF) ...............................20
Single-slit antenna solution ..............................20
Limiting values ..................................................22
Characteristics .................................................. 23
UCODE 7m bare die characteristics ................23
UCODE 7m SOT886 characteristics ................24
Package outline .................................................25
Packing information ..........................................26
Wafer ............................................................... 26
SOT886 ............................................................26
Abbreviations .................................................... 27
References .........................................................28
Revision history ................................................ 29
2.1.1
2.2
2.2.1
2.2.2
2.2.3
2.3
3
3.1
3.2
4
5
6
7
7.1
8
8.1
9
9.1
9.1.1
9.1.2
9.1.3
10
10.1
10.2
10.3
10.3.1
10.3.2
10.4
10.5
10.5.1
10.5.2
10.6
10.6.1
10.6.2
10.6.3
10.6.4
10.6.5
10.6.6
10.6.7
11
12
12.1
12.2
13
14
14.1
14.2
15
16
17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© NXP B.V. 2019.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 6 March 2019
Document identifier: SL3S1214
Document number: 307434
相关型号:
UL1042
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