SPAKXC309VF100A_技术文档

Technical Data

Advance Information

DSP56309/D

Rev. 3, 9/2002

24-Bit Digital Signal

Processor

16

6

3

Memory Expansion Area

Triple

Timer

X Data

RAM

7168 × 24

bits

Y Data

RAM

7168 × 24

bits

PrograM

RAM

20480 × 24

bits

HI08

ESSI

SCI

(default)

Peripheral

Expansion Area

The DSP56309 is

intended for

applications benefiting

from a large amount of

on-chip memory, such

as wireless

YAB

18

Address

External

XAB

PAB

DAB

Generation

Unit

Address

Bus

Address

Switch

Six-Channel

DMA Unit

External

Bus

24-Bit

13

Interface

and Inst.

Cache

Bootstrap

ROM

DSP56300

Core

Control

infrastructure

applications.

DDB

YDB

XDB

PDB

GDB

24

External

Data Bus

Switch

Internal

Data

Bus

Data

Switch

Power

Management

EXTAL

XTAL

Clock

Generator

Data ALU

5

Program

Interrupt

Controller

Program

Decode

Program

Address

Generator

+

→

56-bit MAC

24 × 24 56

JTAG

Two 56-bit Accumulators

56-bit Barrel Shifter

PLL

2

Controller

OnCE™

DE

MODA/IRQA

MODB/IRQB

MODC/IRQC

MODD/IRQD

RESET

PINIT/NMI

Figure 1. DSP56309 Block Diagram

The DSP56309 is a member of the DSP56300

core family of programmable CMOS digital

signal processors (DSPs). The DSP56300 core

includes a barrel shifter, 24-bit addressing, an

instruction cache, and direct memory access

(DMA). The DSP56309 offers 100 MIPS at

3.0–3.6 V using an internal 100 MHz clock.

The large on-chip memory is ideal for

wireless infrastructure and wireless local-loop

applications. The DSP56300 core family

offers a new level of performance in speed

and power provided by its rich instruction set

and low-power dissipation, thus enabling a

new generation of wireless, multimedia, and

telecommunications products.

Note: This document contains information on a new product. Specifications and information herein are subject to change without notice.

Table of Contents

DSP56309 Features............................................................................................................................................ iii

Target Applications ............................................................................................................................................ iv

Product Documentation...................................................................................................................................... iv

Chapter 1

Signal Connections

1.1 Signal Groupings.............................................................................................................................................. 1-1

1.2 Power................................................................................................................................................................ 1-3

1.3 Ground.............................................................................................................................................................. 1-3

1.4 Clock ................................................................................................................................................................ 1-4

1.5 PLL................................................................................................................................................................... 1-4

1.6 External Memory Expansion Port (Port A)...................................................................................................... 1-5

1.7 Interrupt and Mode Control ............................................................................................................................. 1-8

1.8 Host Interface (HI08)....................................................................................................................................... 1-9

1.9 Enhanced Synchronous Serial Interface 0 (ESSI0)........................................................................................ 1-13

1.10 Enhanced Synchronous Serial Interface 1 (ESSI1)........................................................................................ 1-14

1.11 Serial Communication Interface (SCI)........................................................................................................... 1-16

1.12 Timers............................................................................................................................................................. 1-17

1.13 JTAG and OnCE Interface ............................................................................................................................. 1-18

Chapter 2

Chapter 3

Chapter 4

Specifications

2.1 Introduction...................................................................................................................................................... 2-1

2.2 Maximum Ratings............................................................................................................................................ 2-1

2.4 Thermal Characteristics ................................................................................................................................... 2-2

2.5 DC Electrical Characteristics........................................................................................................................... 2-3

2.6 AC Electrical Characteristics........................................................................................................................... 2-4

Packaging

3.1 Pin-Out and Packages ...................................................................................................................................... 3-1

3.2 TQFP Package.................................................................................................................................................. 3-2

3.3 TQFP Package Mechanical Drawing............................................................................................................... 3-9

3.4 MAP-BGA Package....................................................................................................................................... 3-10

3.5 MAP-BGA Package Mechanical Drawing .................................................................................................... 3-19

Design Considerations

4.1 Thermal Design Considerations....................................................................................................................... 4-1

4.2 Electrical Design Considerations..................................................................................................................... 4-2

4.3 Power Consumption Considerations................................................................................................................ 4-4

4.4 PLL Performance Issues .................................................................................................................................. 4-5

4.5 Input (EXTAL) Jitter Requirements................................................................................................................. 4-5

Appendix A

Index

Power Consumption Benchmark

Data Sheet Conventions

OVERBAR

“asserted”

“deasserted”

Examples:

Indicates a signal that is active when pulled low (For example, the RESET pin is active when low.)

Means that a high true (active high) signal is high or that a low true (active low) signal is low

Means that a high true (active high) signal is low or that a low true (active low) signal is high

Signal/Symbol

Logic State

True

Signal State

Asserted

Voltage

V /V

IL OL

False

Deasserted

Asserted

V

/V

IH OH

True

/V

IH OH

False

Deasserted

V /V

IL OL

Note: Values for V , V , V , and V are defined by individual product specifications.

IL

OL

IH

OH

ii

DSP56309 Features

High-Performance DSP56300 Core

• 100 million instructions per second (MIPS) with a 100 MHz clock at 3.3 V nominal

• Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24 × 24-bit parallel

Multiplier-Accumulator (MAC), 56-bit parallel barrel shifter (fast shift and normalization; bit stream

generation and parsing), conditional ALU instructions, and 24-bit or 16-bit arithmetic support under

software control

• Program Control Unit (PCU) with Position Independent Code (PIC) support, addressing modes

optimized for DSP applications (including immediate offsets), on-chip instruction cache controller,

on-chip memory-expandable hardware stack, nested hardware DO loops, and fast auto-return interrupts

• Direct Memory Access (DMA) with six DMA channels supporting internal and external accesses;

one-, two-, and three-dimensional transfers (including circular buffering); end-of-block-transfer

interrupts; and triggering from interrupt lines and all peripherals

• Phase Lock Loop (PLL) allows change of low-power Divide Factor (DF) without loss of lock and

output clock with skew elimination

• Hardware debugging support including On-Chip Emulation (OnCE ) module, Joint Test Action

Group (JTAG) Test Access Port (TAP)

Internal Peripherals

• Enhanced 8-bit parallel host interface (HI08) supports a variety of buses (for example, ISA) and

provides glueless connection to a number of industry-standard microcomputers, microprocessors, and

DSPs

• Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters

(allows six-channel home theater)

• Serial communications interface (SCI) with baud rate generator

• Triple timer module

• Up to thirty-four programmable general-purpose input/output (GPIO) pins, depending on which

peripherals are enabled

Internal Memory

• 192 × 24-bit bootstrap ROM

• 128 K RAM total

• Program RAM, Instruction Cache, X data RAM, and Y data RAM sizes are programmable:

Program RAM

Size

Instruction

Cache Size

X Data RAM

Size

Y Data RAM

Size

Instruction

Cache

Switch Mode

20480 × 24 bits

19456 × 24 bits

24576 × 24 bits

23552 × 24 bits

0

7168 × 24 bits

5120 × 24 bits

7168 × 24 bits

5120 × 24 bits

disabled

enabled

disabled

enabled

disabled

enabled

1024 × 24-bit

0

1024 × 24-bit

iii

External Memory Expansion

• Data memory expansion to two 256 K × 24-bit word memory spaces using the standard external

address lines

• Program memory expansion to one 256 K × 24-bit words memory space using the standard external

address lines

• External memory expansion port

• Chip Select Logic for glueless interface to static random access memory (SRAMs)

• On-chip DRAM Controller for glueless interface to dynamic random access memory (DRAMs)

Reduced Power Dissipation

• Very low-power CMOS design

• Wait and Stop low-power standby modes

• Fully static design specified to operate down to 0 Hz (dc)

• Optimized power management circuitry (instruction-dependent, peripheral-dependent, and

mode-dependent)

Packaging

The DSP56309 is available in a 144-pin TQFP package or a 196-pin MAP-BGA package.

Target Applications

The DSP56309 is intended for applications benefiting from a large amount of on-chip memory, such as

wireless infrastructure applications.

Product Documentation

The three documents listed in the following table are required for a complete description of the

DSP56309 and are necessary to design properly with the part. Documentation is available from the

following sources. (See the back cover for details.)

• A local Motorola distributor

• A Motorola semiconductor sales office

• A Motorola Literature Distribution Center

• The World Wide Web (WWW)

Table 1. DSP56309 Documentation

Name

Description

Order Number

DSP56300 Family

Manual

Detailed description of the DSP56300 family processor core and

instruction set

DSP56300FM/AD

DSP56309 User’s

Manual

Detailed functional description of the DSP56309 memory

configuration, operation, and register programming

DSP56309UM/D

DSP56309/D

DSP56309

Technical Data

DSP56309 features list and physical, electrical, timing, and

package specifications

iv

Chapter 1

Signal

Connections

1.1 Signal Groupings

The DSP56309 input and output signals are organized into functional groups as shown in Table 1-1.

Figure 1-1 diagrams the DSP56309 signals by functional group. The remainder of this chapter describes

the signal pins in each functional group.

Table 1-1. DSP56309 Functional Signal Groupings

Number of Signals

Functional Group

MAP-

TQFP

BGA

Power (V

)

20

19

2

20

66

2

CC

Ground (GND)

Clock

PLL

3

Address bus

18

24

13

5

18

24

13

5

1

2

Data bus

Port A

Bus control

Interrupt and mode control

Host interface (HI08)

Enhanced synchronous serial interface (ESSI)

Serial communication interface (SCI)

Timer

Port B

16

12

3

16

12

3

Ports C and D

4

Port E

3

OnCE/JTAG Port

6

Notes: 1. Port A signals define the external memory interface port, including the external address bus, data

bus, and control signals.

2. Port B signals are the HI08 port signals multiplexed with the GPIO signals.

3. Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals.

4. Port E signals are the SCI port signals multiplexed with the GPIO signals.

5. There are 5 signal connections in the MAP-BGA package that are not used. These are designated as

no connect (NC) in the package description (see Chapter 3).

Note: This chapter refers to a number of configuration registers used to select individual multiplexed

signal functionality. Refer to the DSP56309 User’s Manual for details on these configuration

registers.

1-1

Signal Groupings

After Reset

IRQA

During Reset

MODA

DSP56309

MODB

MODC

MODD

RESET

IRQB

IRQC

IRQD

RESET

Interrupt/

Mode Control

Power Inputs:

PLL

Internal Logic

I/O

V

CCP

4

3

V

CCQL

CCQH

V

3

4

2

V

Address Bus

Data Bus

Bus Control

HI08

CCA

Non-Multiplexed Multiplexed

Port B

GPIO

PB[0–7]

PB8

PB9

PB10

PB13

V

CCD

Bus

8

V

CCC

H[0–7]

HA0

HA1

HAD[0–7]

HAS/HAS

HA8

V

CCH

2

ESSI/SCI/Timer

CCS

Host

Interface

4

HA2

HA9

Grounds :

1

(HI08) Port

HCS/HCS

Single DS

HRW

HDS/HDS

Single HR

HREQ/HREQ

HACK/HACK

HA10

GND

PLL

P

Double DS

HRD/HRD

HWR/HWR

Double HR

HTRQ/HTRQ PB14

HRRQ/HRRQ PB15

P1

4

PB11

PB12

Internal Logic

Address Bus

Data Bus

Bus Control

HI08

Q

GND

A

D

C

H

4

2

GND

2

GND

ESSI/SCI/Timer

S

Port C GPIO

PC[0–2]

PC3

3

Enhanced

Synchronous Serial

Interface Port 0

SC0[0–2]

SCK0

EXTAL

XTAL

Clock

SRD0

PC4

2

(ESSI0)

STD0

PC5

CLKOUT

PCAP

After

PLL

Port D GPIO

PD[0–2]

PD3

PD4

PD5

3

Enhanced

Synchronous Serial

Interface Port 1

SC1[0–2]

SCK1

SRD1

During

Reset

PINIT

Reset

NMI

2

(ESSI1)

STD1

Port A

18

External

Address Bus

Port E GPIO

PE0

PE1

A[0–17]

D[0–23]

Serial

RXD

TXD

SCLK

Communications

24

4

2

External

Data Bus

Interface (SCI) Port

PE2

Timer GPIO

TIO0

TIO1

AA[0–3]/RAS[0–3]

External

Bus

Control

RD

WR

TA

TIO0

TIO1

TIO2

3

Timers

TIO2

BR

BG

BB

TCK

TDI

OnCE/

TDO

TMS

TRST

DE

JTAG Port

CAS

BCLK

Notes: 1. The HI08 port supports a non-multiplexed or a multiplexed bus, single or double Data Strobe (DS), and single or

double Host Request (HR) configurations. Since each of these modes is configured independently, any combination

of these modes is possible. These HI08 signals can also be configured alternatively as GPIO signals (PB[0–15]).

Signals with dual designations (for example, HAS/HAS) have configurable polarity.

2. The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC[0–5]), Port D GPIO signals

(PD[0–5]), and Port E GPIO signals (PE[0–2]), respectively.

3. TIO[0–2] can be configured as GPIO signals.

4. Ground connections shown in this figure are for the TQFP package. In the MAP-BGA package, in addition to the

GND and GND connections, there are 64 GND connections to a common internal package ground plane.

P

P1

Figure 1-1. Signals Identified by Functional Group

1-2

Power

1.2 Power

Table 1-2. Power Inputs

Power Name

Description

V

PLL Power—V dedicated for PLL use. The voltage should be well-regulated and the input

CC

CCP

should be provided with an extremely low impedance path to the V power rail.

CC

Quiet Power (core)—An isolated power for the core processing logic. This input must be

isolated externally from all other chip power inputs.

CCQL

CCQH

CCA

Quiet External (High) Power—A quiet power source for I/O lines. This input must be tied

externally to all other chip power inputs, except V

.

CCQL

Address Bus Power—An isolated power for sections of the address bus I/O drivers. This

input must be tied externally to all other chip power inputs, except V

.

CCQL

Data Bus Power—An isolated power for sections of the data bus I/O drivers. This input must

be tied externally to all other chip power inputs, except V

CCD

CCC

CCH

CCS

.

CCQL

Bus Control Power—An isolated power for the bus control I/O drivers. This input must be

tied externally to all other chip power inputs, except V

.

CCQL

Host Power—An isolated power for the HI08 I/O drivers. This input must be tied externally to

all other chip power inputs, except V

.

CCQL

ESSI, SCI, and Timer Power—An isolated power for the ESSI, SCI, and timer I/O drivers.

This input must be tied externally to all other chip power inputs, except V

.

CCQL

Note: The user must provide adequate external decoupling capacitors for all power connections.

1.3 Ground

Table 1-3. Grounds¹

Ground

Description

Name

GND

PLL Ground—Ground-dedicated for PLL use. The connection should be provided with an extremely

low-impedance path to ground. V should be bypassed to GND by a 0.47 µF capacitor located as

P

CCP

P

close as possible to the chip package.

GND

PLL Ground 1—Ground-dedicated for PLL use. The connection should be provided with an extremely

low-impedance path to ground.

P1

2

Quiet Ground—An isolated ground for the internal processing logic. This connection must be tied

Q

externally to all other chip ground connections, except GND and GND . The user must provide

P

P1

adequate external decoupling capacitors.

Address Bus Ground—An isolated ground for sections of the address bus I/O drivers. This

connection must be tied externally to all other chip ground connections, except GND and GND . The

2

GND

A

P

P1

user must provide adequate external decoupling capacitors.

Data Bus Ground—An isolated ground for sections of the data bus I/O drivers. This connection must

be tied externally to all other chip ground connections, except GND and GND . The user must

2

D

P

P1

provide adequate external decoupling capacitors.

Bus Control Ground—An isolated ground for the bus control I/O drivers. This connection must be tied

externally to all other chip ground connections, except GND and GND . The user must provide

2

C

P

P1

adequate external decoupling capacitors.

Host Ground—An isolated ground for the HI08 I/O drivers. This connection must be tied externally to

all other chip ground connections, except GND and GND . The user must provide adequate external

2

H

P

P1

decoupling capacitors.

ESSI, SCI, and Timer Ground—An isolated ground for the ESSI, SCI, and timer I/O drivers. This

connection must be tied externally to all other chip ground connections, except GND and GND . The

2

S

P

P1

user must provide adequate external decoupling capacitors.

3

Ground—Connected to an internal device ground plane.

Notes: 1. The user must provide adequate external decoupling capacitors for all GND connections.

2. These connections are only used on the TQFP package.

3. These connections are common grounds used on the MAP-BGA package.

1-3

Clock

1.4 Clock

Table 1-4. Clock Signals

State

During

Reset

Signal

Name

Type

Signal Description

EXTAL

Input

External Clock/Crystal Input—Interfaces the internal crystal oscillator

input to an external crystal or an external clock.

XTAL

Output

Chip-driven

Crystal Output—Connects the internal crystal oscillator output to an

external crystal. If an external clock is used, leave XTAL unconnected.

1.5 PLL

Table 1-5. Phase-Locked Loop Signals

Signal

Name

State During

Type

Signal Description

Reset

CLKOUT

Output

Chip-driven

Clock Output—Provides an output clock synchronized to the

internal core clock phase.

If the PLL is enabled and both the multiplication and division

factors equal one, then CLKOUT is also synchronized to EXTAL.

If the PLL is disabled, the CLKOUT frequency is half the

frequency of EXTAL.

PCAP

Input

PLL Capacitor—An input connecting an off-chip capacitor to the

PLL filter. Connect one capacitor terminal to PCAP and the other

terminal to V

.

CCP

If the PLL is not used, PCAP can be tied to V , GND, or left

CC

floating.

PINIT

NMI

Input

PLL Initial—During assertion of RESET, the value of PINIT is

written into the PLL enable (PEN) bit of the PLL control (PCTL)

register, determining whether the PLL is enabled or disabled.

Nonmaskable Interrupt—After RESET deassertion and during

normal instruction processing, this Schmitt-trigger input is the

negative-edge-triggered NMI request internally synchronized to

CLKOUT.

Note: PINIT/NMI can tolerate 5 V.

1-4

External Memory Expansion Port (Port A)

1.6 External Memory Expansion Port (Port A)

Note: When the DSP56309 enters a low-power standby mode (stop or wait), it releases bus mastership

and tri-states the relevant Port A signals: A[0–17], D[0–23], AA0/RAS0–AA3/RAS3, RD, WR, BB,

CAS.

1.6.1 External Address Bus

Table 1-6. External Address Bus Signals

State During

Reset, Stop, or

Wait

Signal

Name

Type

Signal Description

A[0–17]

Output

Tri-stated

Address Bus—When the DSP is the bus master, A[0–17] are

active-high outputs that specify the address for external

program and data memory accesses. Otherwise, the signals

are tri-stated. To minimize power dissipation, A[0–17] do not

change state when external memory spaces are not being

accessed.

1.6.2 External Data Bus

Table 1-7. External Data Bus Signals

State

During

Reset

Signal

Type

During

Stop or

Wait

Signal Description

Name

D[0–23] Input/ Output

Ignored

Input

Last state: Data Bus—When the DSP is the bus master, D[0–23] are

Input:

active-high, bidirectional input/outputs that provide the

bidirectional data bus for external program and data memory

accesses. Otherwise, D[0–23] drivers are tri-stated. If the last

Ignored

Output:

Last value state is output, these lines have weak keepers to maintain the

last output state if all drivers are tri-stated.

1-5

External Memory Expansion Port (Port A)

1.6.3 External Bus Control

Table 1-8. External Bus Control Signals

State During

Reset, Stop, or

Wait

Signal

Name

Type

Signal Description

AA[0–3]

Output Tri-stated

Address Attribute—When defined as AA, these signals can be used as

chip selects or additional address lines. The default use defines a

priority scheme under which only one AA signal can be asserted at a

time. Setting the AA priority disable (APD) bit (Bit 14) of the Operating

Mode Register, the priority mechanism is disabled and the lines can be

used together as four external lines that can be decoded externally into

16 chip select signals.

RAS[0–3] Output

Row Address Strobe—When defined as RAS, these signals can be

used as RAS for DRAM interface. These signals are tri-statable outputs

with programmable polarity.

RD

WR

TA

Output Tri-stated

Read Enable—When the DSP is the bus master, RD is an active-low

output that is asserted to read external memory on the data bus

(D[0–23]). Otherwise, RD is tri-stated.

Output Tri-stated

Write Enable—When the DSP is the bus master, WR is an active-low

output that is asserted to write external memory on the data bus

(D[0–23]). Otherwise, the signals are tri-stated.

Input

Ignored Input

Transfer Acknowledge—If the DSP56309 is the bus master and there

is no external bus activity, or the DSP56309 is not the bus master, the

TA input is ignored. The TA input is a data transfer acknowledge

(DTACK) function that can extend an external bus cycle indefinitely. Any

number of wait states (1, 2. . .infinity) can be added to the wait states

inserted by the bus control register (BCR) by keeping TA deasserted. In

typical operation, TA is deasserted at the start of a bus cycle, is asserted

to enable completion of the bus cycle, and is deasserted before the next

bus cycle. The current bus cycle completes one clock period after TA is

asserted synchronous to CLKOUT. The number of wait states is

determined by the TA input or by the BCR, whichever is longer. The

BCR can be used to set the minimum number of wait states in external

bus cycles.

To use the TA functionality, the BCR must be programmed to at least

one wait state. A zero wait state access cannot be extended by TA

deassertion; otherwise, improper operation may result. TA can operate

synchronously or asynchronously depending on the setting of the TAS

bit in the Operating Mode Register. TA functionality cannot be used

during DRAM type accesses; otherwise improper operation may result.

BR

Output Reset: Output

(deasserted)

Bus Request—Asserted when the DSP requests bus mastership. BR is

deasserted when the DSP no longer needs the bus. BR may be

asserted or deasserted independently of whether the DSP56309 is a

bus master or a bus slave. Bus “parking” allows BR to be deasserted

even though the DSP56309 is the bus master. (See the description of

bus “parking” in the BB signal description.) The bus request hold (BRH)

bit in the BCR allows BR to be asserted under software control even

though the DSP does not need the bus. BR is typically sent to an

State during

Stop/Wait depends

on BRH bit setting:

• BRH = 0: Output,

deasserted

• BRH = 1: Maintains external bus arbitrator that controls the priority, parking, and tenure of

last state (that is, if

asserted, remains

asserted)

each master on the same external bus. BR is affected only by DSP

requests for the external bus, never for the internal bus. During

hardware reset, BR is deasserted and the arbitration is reset to the bus

slave state.

1-6

External Memory Expansion Port (Port A)

Table 1-8. External Bus Control Signals (Continued)

State During

Reset, Stop, or

Wait

Signal

Name

Type

Signal Description

BG

Input

Ignored Input

Bus Grant—Asserted by an external bus arbitration circuit when the

DSP56309 becomes the next bus master. When BG is asserted, the

DSP56309 must wait until BB is deasserted before taking bus

mastership. When BG is deasserted, bus mastership is typically given

up at the end of the current bus cycle. This may occur in the middle of an

instruction that requires more than one external bus cycle for execution.

The default operation of this bit requires a setup and hold time as

specified in Table 2-14. An alternate mode can be invoked: set the

asynchronous bus arbitration enable (ABE) bit (Bit 13) in the Operating

Mode Register. When this bit is set, BG and BB are synchronized

internally. This eliminates the respective setup and hold time

requirements but adds a required delay between the deassertion of an

initial BG input and the assertion of a subsequent BG input.

BB

Input/

Output

Ignored Input

Bus Busy—Indicates that the bus is active. Only after BB is deasserted

can the pending bus master become the bus master (and then assert

the signal again). The bus master may keep BB asserted after ceasing

bus activity regardless of whether BR is asserted or deasserted. Called

“bus parking,” this allows the current bus master to reuse the bus

without rearbitration until another device requires the bus. BB is

deasserted by an “active pull-up” method (that is, BB is driven high and

then released and held high by an external pull-up resistor).

The default operation of this signal requires a setup and hold time as

specified in Table 2-14. An alternative mode can be invoked by setting

the ABE bit (Bit 13) in the Operating Mode Register. When this bit is set,

BG and BB are synchronized internally. See BG for additional

information.

Note: BB requires an external pull-up resistor.

CAS

Output Tri-stated

Column Address Strobe—When the DSP is the bus master, CAS is an

active-low output used by DRAM to strobe the column address.

Otherwise, if the Bus Mastership Enable (BME) bit in the DRAM control

register is cleared, the signal is tri-stated.

BCLK

Bus Clock

When the DSP is the bus master, BCLK is active when the ATE bit in the

Operating Mode Register is set. When BCLK is active and synchronized

to CLKOUT by the internal PLL, BCLK precedes CLKOUT by one-fourth

of a clock cycle.

BCLK

Output Tri-stated

Bus Clock Not

When the DSP is the bus master, BCLK is the inverse of the BCLK

signal. Otherwise, the signal is tri-stated.

1-7

Interrupt and Mode Control

1.7 Interrupt and Mode Control

The interrupt and mode control signals select the chip operating mode as it comes out of hardware reset.

After RESET is deasserted, these inputs are hardware interrupt request lines.

Table 1-9. Interrupt and Mode Control

State During

Signal Name

Type

Signal Description

Reset

Input

Schmitt-trigger

Input

Mode Select A—MODA, MODB, MODC, and MODD select one

of 16 initial chip operating modes, latched into the Operating

Mode Register when the RESET signal is deasserted.

MODA

Input

External Interrupt Request A—After reset, this input becomes a

level-sensitive or negative-edge-triggered, maskable interrupt

request input during normal instruction processing. If the

processor is in the STOP or WAIT standby state and IRQA is

asserted, the processor exits the STOP or WAIT state.

IRQA

Input

Schmitt-trigger

Input

Mode Select B—MODA, MODB, MODC, and MODD select one

of 16 initial chip operating modes, latched into the Operating

Mode Register when the RESET signal is deasserted.

MODB

IRQB

External Interrupt Request B—After reset, this input becomes a

level-sensitive or negative-edge-triggered, maskable interrupt

request input during normal instruction processing. If the

processor is in the WAIT standby state and IRQB is asserted, the

processor exits the WAIT state.

Input

Schmitt-trigger

Input

Mode Select C—MODA, MODB, MODC, and MODD select one

of 16 initial chip operating modes, latched into the Operating

Mode Register when the RESET signal is deasserted.

MODC

IRQC

External Interrupt Request C—After reset, this input becomes a

level-sensitive or negative-edge-triggered, maskable interrupt

request input during normal instruction processing. If the

processor is in the WAIT standby state and IRQC is asserted, the

processor exits the WAIT state.

Input

Schmitt-trigger

Input

Mode Select D—MODA, MODB, MODC, and MODD select one

of 16 initial chip operating modes, latched into the Operating

Mode Register when the RESET signal is deasserted.

MODD

IRQD

External Interrupt Request D—After reset, this input becomes a

level-sensitive or negative-edge-triggered, maskable interrupt

request input during normal instruction processing. If the

processor is in the WAIT standby state and IRQD is asserted, the

processor exits the WAIT state.

RESET

Input

Schmitt-trigger

Input

Reset—Places the chip in the Reset state and resets the internal

phase generator. The Schmitt-trigger input allows a slowly rising

input (such as a capacitor charging) to reset the chip reliably.

When the RESET signal is deasserted, the initial chip operating

mode is latched from the MODA, MODB, MODC, and MODD

inputs. The RESET signal must be asserted after powerup.

Note: These signals are all 5 V tolerant.

1-8

Host Interface (HI08)

1.8 Host Interface (HI08)

The HI08 provides a fast, 8-bit, parallel data port that connects directly to the host bus. The HI08 supports

a variety of standard buses and connects directly to a number of industry-standard microcomputers,

microprocessors, DSPs, and DMA hardware.

1.8.4 Host Port Usage Considerations

Careful synchronization is required when the system reads multiple-bit registers that are written by

another asynchronous system. This is a common problem when two asynchronous systems are connected

(as they are in the Host port). The considerations for proper operation are discussed in Table 1-10.

Table 1-10. Host Port Usage Considerations

Action

Description

Asynchronous read of receive

byte registers

When reading the receive byte registers, Receive register High (RXH), Receive

register Middle (RXM), or Receive register Low (RXL), use interrupts or poll the

Receive register Data Full (RXDF) flag that indicates data is available. This assures

that the data in the receive byte registers is valid.

Asynchronous write to transmit Do not write to the transmit byte registers, Transmit register High (TXH), Transmit

byte registers

register Middle (TXM), or Transmit register Low (TXL), unless the Transmit register

Data Empty (TXDE) bit is set indicating that the transmit byte registers are empty.

This guarantees that the transmit byte registers transfer valid data to the Host

Receive (HRX) register.

Asynchronous write to host

vector

Change the Host Vector (HV) register only when the Host Command bit (HC) is

clear. This practice guarantees that the DSP interrupt control logic receives a stable

vector.

1.8.5 Host Port Configuration

HI08 signal functions vary according to the programmed configuration of the interface as determined by

the 16 bits in the HI08 Port Control Register.

Table 1-11. Host Interface

StateDuring

Signal Name

Type

Signal Description

Reset^1,2

H[0–7]

Input/Output

Ignored Input Host Data—When the HI08 is programmed to interface with a

non-multiplexed host bus and the HI function is selected, these

signals are lines 0–7 of the bidirectional Data bus.

HAD[0–7]

PB[0–7]

Input/Output

Host Address—When the HI08 is programmed to interface with a

multiplexed host bus and the HI function is selected, these signals

are lines 0–7 of the bidirectional multiplexed Address/Data bus.

Input or Output

Port B 0–7—When the HI08 is configured as GPIO through the

HI08 Port Control Register, these signals are individually

programmed as inputs or outputs through the HI08 Data Direction

Register.

1-9

Host Interface (HI08)

Table 1-11. Host Interface (Continued)

StateDuring

Signal Name

Type

Signal Description

Reset^1,2

HA0

Input

Ignored Input Host Address Input 0—When the HI08 is programmed to

interface with a nonmultiplexed host bus and the HI function is

selected, this signal is line 0 of the host address input bus.

HAS/HAS

Input

Host Address Strobe—When the HI08 is programmed to

interface with a multiplexed host bus and the HI function is

selected, this signal is the host address strobe (HAS)

Schmitt-trigger input. The polarity of the address strobe is

programmable but is configured active-low (HAS) following reset.

PB8

Input or Output

Port B 8—When the HI08 is configured as GPIO through the HI08

Port Control Register, this signal is individually programmed as an

input or output through the HI08 Data Direction Register.

HA1

Input

Ignored Input Host Address Input 1—When the HI08 is programmed to

interface with a nonmultiplexed host bus and the HI function is

selected, this signal is line 1 of the host address (HA1) input bus.

HA8

Input

Host Address 8—When the HI08 is programmed to interface with

a multiplexed host bus and the HI function is selected, this signal

is line 8 of the host address (HA8) input bus.

PB9

HA2

Input or Output

Input

Port B 9—When the HI08 is configured as GPIO through the HI08

Port Control Register, this signal is individually programmed as an

input or output through the HI08 Data Direction Register.

Ignored Input Host Address Input 2—When the HI08 is programmed to

interface with a nonmultiplexed host bus and the HI function is

selected, this signal is line 2 of the host address (HA2) input bus.

HA9

Input

Host Address 9—When the HI08 is programmed to interface with

a multiplexed host bus and the HI function is selected, this signal

is line 9 of the host address (HA9) input bus.

PB10

Input or Output

Input

Port B 10—When the HI08 is configured as GPIO through the

HI08 Port Control Register, this signal is individually programmed

as an input or output through the HI08 Data Direction Register.

HCS/HCS

Ignored Input Host Chip Select—When the HI08 is programmed to interface

with a nonmultiplexed host bus and the HI function is selected, this

signal is the host chip select (HCS) input. The polarity of the chip

select is programmable but is configured active-low (HCS) after

reset.

HA10

PB13

Input

Host Address 10—When the HI08 is programmed to interface

with a multiplexed host bus and the HI function is selected, this

signal is line 10 of the host address (HA10) input bus.

Input or Output

Port B 13—When the HI08 is configured as GPIO through the

HI08 Port Control Register, this signal is individually programmed

as an input or output through the HI08 Data Direction Register.

1-10

Host Interface (HI08)

Table 1-11. Host Interface (Continued)

StateDuring

Signal Name

Type

Signal Description

Reset^1,2

HRW

Input

Ignored Input Host Read/Write—When the HI08 is programmed to interface

with a single-data-strobe host bus and the HI function is selected,

this signal is the Host Read/Write (HRW) input.

HRD/HRD

Input

Host Read Data—When the HI08 is programmed to interface with

a double-data-strobe host bus and the HI function is selected, this

signal is the HRD strobe Schmitt-trigger input. The polarity of the

data strobe is programmable but is configured as active-low (HRD)

after reset.

PB11

Input or Output

Port B 11—When the HI08 is configured as GPIO through the

HI08 Port Control Register, this signal is individually programmed

as an input or output through the HI08 Data Direction Register.

HDS/HDS

Input

Ignored Input Host Data Strobe—When the HI08 is programmed to interface

with a single-data-strobe host bus and the HI function is selected,

this signal is the host data strobe (HDS) Schmitt-trigger input. The

polarity of the data strobe is programmable but is configured as

active-low (HDS) following reset.

HWR/HWR

Input

Host Write Data—When the HI08 is programmed to interface with

a double-data-strobe host bus and the HI function is selected, this

signal is the host write data strobe (HWR) Schmitt-trigger input.

The polarity of the data strobe is programmable but is configured

as active-low (HWR) following reset.

PB12

Input or Output

Output

Port B 12—When the HI08 is configured as GPIO through the

HI08 Port Control Register, this signal is individually programmed

as an input or output through the HI08 Data Direction Register.

HREQ/HREQ

Ignored Input Host Request—When the HI08 is programmed to interface with a

single host request host bus and the HI function is selected, this

signal is the host request (HREQ) output. The polarity of the host

request is programmable but is configured as active-low (HREQ)

following reset. The host request may be programmed as a driven

or open-drain output.

HTRQ/HTRQ

Output

Transmit Host Request—When the HI08 is programmed to

interface with a double host request host bus and the HI function is

selected, this signal is the transmit host request (HTRQ) output.

The polarity of the host request is programmable but is configured

as active-low (HTRQ) following reset. The host request may be

programmed as a driven or open-drain output.

PB14

Input or Output

Port B 14—When the HI08 is configured as GPIO through the

HI08 Port Control Register, this signal is individually programmed

as an input or output through the HI08 Data Direction Register.

1-11

Host Interface (HI08)

Table 1-11. Host Interface (Continued)

StateDuring

Signal Name

Type

Signal Description

Reset^1,2

HACK/HACK

Input

Ignored Input Host Acknowledge—When the HI08 is programmed to interface

with a single host request host bus and the HI function is selected,

this signal is the host acknowledge (HACK) Schmitt-trigger input.

The polarity of the host acknowledge is programmable but is

configured as active-low (HACK) after reset.

HRRQ/HRRQ

Output

Receive Host Request—When the HI08 is programmed to

interface with a double host request host bus and the HI function is

selected, this signal is the receive host request (HRRQ) output.

The polarity of the host request is programmable but is configured

as active-low (HRRQ) after reset. The host request may be

programmed as a driven or open-drain output.

PB15

Input or Output

Port B 15—When the HI08 is configured as GPIO through the

HI08 Port Control Register, this signal is individually programmed

as an input or output through the HI08 Data Direction Register.

Notes: 1. In the Stop state, the signal maintains the last state as follows:

• If the last state is input, the signal is an ignored input.

• If the last state is output, the signal is tri-stated.

2. The Wait processing state does not affect the signal state.

3. All inputs are 5 V tolerant.

1-12

Enhanced Synchronous Serial Interface 0 (ESSI0)

1.9 Enhanced Synchronous Serial Interface 0 (ESSI0)

Two synchronous serial interfaces (ESSI0 and ESSI1) provide a full-duplex serial port for serial

communication with a variety of serial devices, including one or more industry-standard codecs, other

DSPs, microprocessors, and peripherals that implement the Motorola serial peripheral interface (SPI).

Table 1-12. Enhanced Synchronous Serial Interface 0

StateDuring

Signal Name

Type

Signal Description

Reset^1,2

SC00

Input or Output Ignored Input Serial Control 0—For asynchronous mode, this signal is used for

the receive clock I/O (Schmitt-trigger input). For synchronous

mode, this signal is used either for transmitter 1 output or for serial

I/O flag 0.

PC0

Input or Output

Port C 0—The default configuration following reset is GPIO input

PC0. When configured as PC0, signal direction is controlled

through the Port C Direction Register. The signal can be

configured as ESSI signal SC00 through the Port C Control

Register.

SC01

PC1

Input/Output

Ignored Input Serial Control 1—For asynchronous mode, this signal is the

receiver frame sync I/O. For synchronous mode, this signal is

used either for transmitter 2 output or for serial I/O flag 1.

Input or Output

Port C 1—The default configuration following reset is GPIO input

PC1. When configured as PC1, signal direction is controlled

through the Port C Direction Register. The signal can be

configured as an ESSI signal SC01 through the Port C Control

Register.

SC02

Input/Output

Ignored Input Serial Control Signal 2—The frame sync for both the transmitter

and receiver in synchronous mode, and for the transmitter only in

asynchronous mode. When configured as an output, this signal is

the internally generated frame sync signal. When configured as an

input, this signal receives an external frame sync signal for the

transmitter (and the receiver in synchronous operation).

PC2

Input or Output

Input/Output

Port C 2—The default configuration following reset is GPIO input

PC2. When configured as PC2, signal direction is controlled

through the Port C Direction Register. The signal can be

configured as an ESSI signal SC02 through the Port C Control

Register.

SCK0

Ignored Input Serial Clock—Provides the serial bit rate clock for the ESSI. The

SCK0 is a clock input or output, used by both the transmitter and

receiver in synchronous modes or by the transmitter in

asynchronous modes.

Although an external serial clock can be independent of and

asynchronous to the DSP system clock, it must exceed the

minimum clock cycle time of 6T (that is, the system clock

frequency must be at least three times the external ESSI clock

frequency). The ESSI needs at least three DSP phases inside

each half of the serial clock.

PC3

Input or Output

Port C 3—The default configuration following reset is GPIO input

PC3. When configured as PC3, signal direction is controlled

through the Port C Direction Register. The signal can be

configured as an ESSI signal SCK0 through the Port C Control

Register.

1-13

Enhanced Synchronous Serial Interface 1 (ESSI1)

Table 1-12. Enhanced Synchronous Serial Interface 0 (Continued)

StateDuring

Reset^1,2

Signal Name

Type

Signal Description

SRD0

Input

Ignored Input Serial Receive Data—Receives serial data and transfers the data

to the ESSI Receive Shift Register. SRD0 is an input when data is

received.

PC4

Input or Output

Port C 4—The default configuration following reset is GPIO input

PC4. When configured as PC4, signal direction is controlled

through the Port C Direction Register. The signal can be

configured as an ESSI signal SRD0 through the Port C Control

Register.

STD0

PC5

Output

Ignored Input Serial Transmit Data—Transmits data from the Serial Transmit

Shift Register. STD0 is an output when data is transmitted.

Input or Output

Port C 5—The default configuration following reset is GPIO input

PC5. When configured as PC5, signal direction is controlled

through the Port C Direction Register. The signal can be

configured as an ESSI signal STD0 through the Port C Control

Register.

Notes: 1. In the Stop state, the signal maintains the last state as follows:

• If the last state is input, the signal is an ignored input.

• If the last state is output, the signal is tri-stated.

2. The Wait processing state does not affect the signal state.

3. All inputs are 5 V tolerant.

1.10 Enhanced Synchronous Serial Interface 1 (ESSI1)

Table 1-13. Enhanced Serial Synchronous Interface 1

StateDuring

Signal Name

Type

Signal Description

Reset^1,2

SC10

Input or Output Ignored Input Serial Control 0—For asynchronous mode, this signal is used for

the receive clock I/O (Schmitt-trigger input). For synchronous

mode, this signal is used either for transmitter 1 output or for serial

I/O flag 0.

PD0

Input or Output

Port D 0—The default configuration following reset is GPIO input

PD0. When configured as PD0, signal direction is controlled

through the Port D Direction Register. The signal can be

configured as an ESSI signal SC10 through the Port D Control

Register.

SC11

PD1

Input/Output

Ignored Input Serial Control 1—For asynchronous mode, this signal is the

receiver frame sync I/O. For synchronous mode, this signal is

used either for Transmitter 2 output or for Serial I/O Flag 1.

Input or Output

Port D 1—The default configuration following reset is GPIO input

PD1. When configured as PD1, signal direction is controlled

through the Port D Direction Register. The signal can be

configured as an ESSI signal SC11 through the Port D Control

Register.

1-14

Enhanced Synchronous Serial Interface 1 (ESSI1)

Table 1-13. Enhanced Serial Synchronous Interface 1 (Continued)

StateDuring

Reset^1,2

Signal Name

Type

Signal Description

SC12

Input/Output

Ignored Input Serial Control Signal 2—The frame sync for both the transmitter

and receiver in synchronous mode and for the transmitter only in

asynchronous mode. When configured as an output, this signal is

the internally generated frame sync signal. When configured as an

input, this signal receives an external frame sync signal for the

transmitter (and the receiver in synchronous operation).

PD2

Input or Output

Port D 2—The default configuration following reset is GPIO input

PD2. When configured as PD2, signal direction is controlled

through the Port D Direction Register. The signal can be

configured as an ESSI signal SC12 through the Port D Control

Register.

SCK1

Input/Output

Ignored Input Serial Clock—Provides the serial bit rate clock for the ESSI. The

SCK1 is a clock input or output used by both the transmitter and

receiver in synchronous modes or by the transmitter in

asynchronous modes.

Although an external serial clock can be independent of and

asynchronous to the DSP system clock, it must exceed the

minimum clock cycle time of 6T (that is, the system clock

frequency must be at least three times the external ESSI clock

frequency). The ESSI needs at least three DSP phases inside

each half of the serial clock.

PD3

Input or Output

Port D 3—The default configuration following reset is GPIO input

PD3. When configured as PD3, signal direction is controlled

through the Port D Direction Register. The signal can be

configured as an ESSI signal SCK1 through the Port D Control

Register.

SRD1

PD4

Input

Ignored Input Serial Receive Data—Receives serial data and transfers the data

to the ESSI Receive Shift Register. SRD1 is an input when data is

being received.

Input or Output

Port D 4—The default configuration following reset is GPIO input

PD4. When configured as PD4, signal direction is controlled

through the Port D Direction Register. The signal can be

configured as an ESSI signal SRD1 through the Port D Control

Register.

STD1

PD5

Output

Ignored Input Serial Transmit Data—Transmits data from the Serial Transmit

Shift Register. STD1 is an output when data is being transmitted.

Input or Output

Port D 5—The default configuration following reset is GPIO input

PD5. When configured as PD5, signal direction is controlled

through the Port D Direction Register. The signal can be

configured as an ESSI signal STD1 through the Port D Control

Register.

Notes: 1. In the Stop state, the signal maintains the last state as follows:

• If the last state is input, the signal is an ignored input.

• If the last state is output, the signal is tri-stated.

2. The Wait processing state does not affect the signal state.

3. All inputs are 5 V tolerant.

1-15

Serial Communication Interface (SCI)

1.11 Serial Communication Interface (SCI)

The SCI provides a full duplex port for serial communication with other DSPs, microprocessors, or

peripherals such as modems.

Table 1-14. Serial Communication Interface

StateDuring

Signal Name

Type

Signal Description

Reset^1,2

RXD

Input

Ignored Input Serial Receive Data—Receives byte-oriented serial data and

transfers it to the SCI Receive Shift Register.

PE0

Input or Output

Port E 0—The default configuration following reset is GPIO input

PE0. When configured as PE0, signal direction is controlled

through the Port E Direction Register. The signal can be

configured as an SCI signal RXD through the Port E Control

Register.

TXD

PE1

Output

Ignored Input Serial Transmit Data—Transmits data from the SCI Transmit

Data Register.

Input or Output

Port E 1—The default configuration following reset is GPIO input

PE1. When configured as PE1, signal direction is controlled

through the Port E Direction Register. The signal can be

configured as an SCI signal TXD through the Port E Control

Register.

SCLK

PE2

Input/Output

Ignored Input Serial Clock—Provides the input or output clock used by the

transmitter and/or the receiver.

Input or Output

Port E 2—The default configuration following reset is GPIO input

PE2. When configured as PE2, signal direction is controlled

through the Port E Direction Register. The signal can be

configured as an SCI signal SCLK through the Port E Control

Register.

Notes: 1. In the Stop state, the signal maintains the last state as follows:

• If the last state is input, the signal is an ignored input.

• If the last state is output, the signal is tri-stated.

2. The Wait processing state does not affect the signal state.

3. All inputs are 5 V tolerant.

1-16

Timers

1.12 Timers

The DSP56309 has three identical and independent timers. Each timer can use internal or external

clocking and can either interrupt the DSP56309 after a specified number of events (clocks) or signal an

external device after counting a specific number of internal events.

Table 1-15. Triple Timer Signals

StateDuring

Reset^1,2

Signal Name

Type

Signal Description

TIO0

Input or Output Ignored Input

Timer 0 Schmitt-Trigger Input/Output— When Timer 0 functions

as an external event counter or in measurement mode, TIO0 is

used as input. When Timer 0 functions in watchdog, timer, or pulse

modulation mode, TIO0 is used as output.

The default mode after reset is GPIO input. TIO0 can be changed

to output or configured as a timer I/O through the Timer 0

Control/Status Register (TCSR0).

TIO1

Timer 1 Schmitt-Trigger Input/Output— When Timer 1 functions

as an external event counter or in measurement mode, TIO1 is

used as input. When Timer 1 functions in watchdog, timer, or pulse

modulation mode, TIO1 is used as output.

The default mode after reset is GPIO input. TIO1 can be changed

to output or configured as a timer I/O through the Timer 1

Control/Status Register (TCSR1).

TIO2

Timer 2 Schmitt-Trigger Input/Output— When Timer 2 functions

as an external event counter or in measurement mode, TIO2 is

used as input. When Timer 2 functions in watchdog, timer, or pulse

modulation mode, TIO2 is used as output.

The default mode after reset is GPIO input. TIO2 can be changed

to output or configured as a timer I/O through the Timer 2

Control/Status Register (TCSR2).

Notes: 1. In the Stop state, the signal maintains the last state as follows:

• If the last state is input, the signal is an ignored input.

• If the last state is output, the signal is tri-stated.

2. The Wait processing state does not affect the signal state.

3. All inputs are 5 V tolerant.

1-17

JTAG and OnCE Interface

1.13 JTAG and OnCE Interface

The DSP56300 family and in particular the DSP56309 support circuit-board test strategies based on the

IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture, the industry standard

developed under the sponsorship of the Test Technology Committee of IEEE and the JTAG.

The OnCE module provides a means to interface nonintrusively with the DSP56300 core and its

peripherals so that you can examine registers, memory, or on-chip peripherals. Functions of the OnCE

module are provided through the JTAG TAP signals.

For programming models, see the chapter on debugging support in the DSP56300 Family Manual.

Table 1-16. JTAG/OnCE Interface

State

During

Reset

Signal

Name

Type

Signal Description

TCK

Input

Test Clock—A test clock input signal to synchronize the JTAG

test logic.

TDI

Input

Test Data Input—A test data serial input signal for test

instructions and data. TDI is sampled on the rising edge of TCK

and has an internal pull-up resistor.

TDO

Output

Tri-stated

Test Data Output—A test data serial output signal for test

instructions and data. TDO is actively driven in the shift-IR and

shift-DR controller states. TDO changes on the falling edge of

TCK.

TMS

TRST

DE

Input

Test Mode Select—Sequences the test controller’s state

machine. TMS is sampled on the rising edge of TCK and has an

internal pull-up resistor.

Test Reset—Initializes the test controller asynchronously. TRST

has an internal pull-up resistor. TRST must be asserted after

powerup.

Input/ Output

(open-drain)

Debug Event—As an input, initiates Debug mode from an

external command controller, and, as an open-drain output,

acknowledges that the chip has entered Debug mode. As an

input, DE causes the DSP56300 core to finish executing the

current instruction, save the instruction pipeline information,

enter Debug mode, and wait for commands to be entered from

the debug serial input line. This signal is asserted as an output

for three clock cycles when the chip enters Debug mode as a

result of a debug request or as a result of meeting a breakpoint

condition. The DE has an internal pull-up resistor.

This signal is not a standard part of the JTAG TAP controller.

The signal connects directly to the OnCE module to initiate

debug mode directly or to provide a direct external indication that

the chip has entered Debug mode. All other interface with the

OnCE module must occur through the JTAG port.

Note: All inputs are 5 V tolerant.

1-18

Chapter 2

Specifications

2.1 Introduction

The DSP56309 is fabricated in high-density CMOS with Transistor-Transistor Logic (TTL) compatible

inputs and outputs.

Note: The DSP56309 specifications are preliminary and are from design simulations, and may not be

fully tested or guaranteed. Finalized specifications will be published after full characterization

and device qualifications are complete.

2.2 Maximum Ratings

CAUTION

This device contains circuitry protecting

against damage due to high static voltage or

electrical fields; however, normal precautions

should be taken to avoid exceeding maximum

voltage ratings. Reliability is enhanced if

unused inputs are tied to an appropriate logic

voltage level (for example, either GND or V ).

CC

Note: In the calculation of timing requirements, adding a maximum value of one specification to a

minimum value of another specification does not yield a reasonable sum. A maximum

specification is calculated using a worst case variation of process parameter values in one

direction. The minimum specification is calculated using the worst case for the same parameters

in the opposite direction. Therefore, a “maximum” value for a specification never occurs in the

same device that has a “minimum” value for another specification; adding a maximum to a

minimum represents a condition that can never exist.

2-1

Absolute Maximum Ratings

2.3 Absolute Maximum Ratings

Table 2-1. Absolute Maximum Ratings¹

Rating

Symbol

Value

Unit

Supply Voltage

V

−0.3 to +4.0

V

CC

All input voltages excluding “5 V tolerant” inputs

V

GND − 0.3 to V + 0.3

IN

CC

2

All “5 V tolerant” input voltages

V

GND − 0.3 to 5.5

10

V

IN5

Current drain per pin excluding V and GND

I

mA

°C

CC

Operating temperature range

T

−40 to +100

−55 to +150

J

Storage temperature

T

STG

Notes: 1. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not

guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent

damage to the device.

2. At power-up, ensure that the voltage difference between the 5 V tolerant pins and the chip V never

CC

exceeds 3.5 V.

2.4 Thermal Characteristics

Table 2-2. Thermal Characteristics

MAP-BGA³MAP-BGA⁴

Characteristic

Symbol TQFP Value

Unit

Value

1

Junction-to-ambient thermal resistance

R

or θ

49.3

8.2

49.4

12.0

2.0

28.5

—

°C/W

θJA

JA

JC

2

Junction-to-case thermal resistance

θJC

Thermal characterization parameter

Ψ

5.5

—

JT

Notes: 1. Junction-to-ambient thermal resistance is based on measurements on a horizontal single-sided printed

circuit board per JEDEC Specification JESD51-3.

2. Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G30-88,

with the exception that the cold plate temperature is used for the case temperature.

3. These are simulated values. See note 1 for test board conditions.

4. These are simulated values. The test board has two 2-ounce signal layers and two 1-ounce solid

ground planes internal to the test board.

2-2

DC Electrical Characteristics

2.5 DC Electrical Characteristics

Table 2-3. DC Electrical Characteristics⁶

Characteristics

Symbol

Min

Typ

Max

Unit

Supply voltage

V

3.0

3.3

3.6

V

CC

Input high voltage

•

D[0–23], BG, TA

BB

V

2.0

2.3

2.0

—

V

5.25

V

IH

CC

1

MOD /IRQ , RESET, PINIT/NMI and all

JTAG/ESSI/SCI/Timer/HI08 pins

V

IHP

8

•

EXTAL

0.8 × V

—

V

CC

V

IHX

CC

Input low voltage

1

•

D[0–23], BG, BB, TA, MOD /IRQ , RESET, PINIT

V

–0.3

—

0.8

0.2 × V

V

IL

All JTAG/ESSI/SCI/Timer/HI08 pins

V

ILP

ILX

8

EXTAL

CC

Input leakage current

I

–10

—

10

µA

IN

High impedance (off-state) input current (@ 2.4 V / 0.4 V)

I

TSI

Output high voltage

V

OH

5,7

•

TTL (I

CMOS (I = –10 µA)

= –0.4 mA)

2.4

– 0.01

CC

—

V

OH

5

V

OH

Output low voltage

V

OL

5,7

•

TTL (I = 1.6 mA, open-drain pins I = 6.7 mA)

—

0.4

0.01

V

OL

5

CMOS (I = 10 µA)

OL

2

Internal supply current :

•

In Normal mode

I

—

160

7.5

100

—

mA

µA

CCI

3

In Wait mode

I

CCW

4

In Stop mode

I

CCS

PLL supply current

—

1

2.5

10

mA

pF

5

Input capacitance

C

—

IN

Notes: 1. Refers to MODA/IRQA, MODB/IRQB, MODC/IRQC, and MODD/IRQD pins.

2. Secton 4.3 Power Consumption Considerations on page 4-4 provides a formula to compute the

estimated current requirements in Normal mode. In order to obtain these results, all inputs must be

terminated (that is, not allowed to float). Measurements are based on synthetic intensive DSP

benchmarks (see Appendix A). The power consumption numbers in this specification are 90 percent

of the measured results of this benchmark. This reflects typical DSP applications. Typical internal

supply current is measured with V = 3.3 V at T = 100°C.

CC

J

3. In order to obtain these results, all inputs must be terminated (that is, not allowed to float).

4. In order to obtain these results, all inputs that are not disconnected at Stop mode must be terminated

(that is, not allowed to float). PLL and XTAL signals are disabled during Stop state.

5. Periodically sampled and not 100 percent tested.

6.

7. This characteristic does not apply to XTAL and PCAP.

8. Driving EXTAL to the low V or the high V value may cause additional power consumption (DC

V

= 3.3 V ± 0.3 V; T = –40°C to +100 °C, C = 50 pF

CC J L

IHX

ILX

current). To minimize power consumption, the minimum V

should be no lower than

IHX

0.9 × V and the maximum V should be no higher than 0.1 × V .

CC

ILX

CC

2-3

AC Electrical Characteristics

2.6 AC Electrical Characteristics

The timing waveforms shown in the AC electrical characteristics section are tested with a V_ILmaximum

of 0.3 V and a V_IHminimum of 2.4 V for all pins except EXTAL, which is tested using the input levels

shown in Note 6 of the previous table. AC timing specifications, which are referenced to a device input

signal, are measured in production with respect to the 50 percent point of the respective input signal’s

transition. DSP56309 output levels are measured with the production test machine V_OLand V_OH

reference levels set at 0.4 V and 2.4 V, respectively.

Note: Although the minimum value for the frequency of EXTAL is 0 MHz, the device AC test

conditions are 15 MHz and rated speed.

2.6.1 Internal Clocks

Table 2-4. Internal Clocks, CLKOUT

Expression^{1, 2}

Characteristics

Symbol

Min

Typ

Max

Internal operation frequency and

CLKOUT with PLL enabled

f

—

(Ef × MF)/

(PDF × DF)

—

Internal operation frequency and

CLKOUT with PLL disabled

f

—

Ef/2

—

Internal clock and CLKOUT high

period

T

H

•

With PLL disabled

With PLL enabled and MF ≤ 4

—

ET

—

C

0.49 × ET

×

0.51 × ET ×

C

PDF × DF/MF

0.47 × ET

PDF × DF/MF

0.53 × ET

•

With PLL enabled and MF > 4

×

—

×

C

PDF × DF/MF

Internal clock and CLKOUT low

period

T

L

•

With PLL disabled

With PLL enabled and MF ≤ 4

—

ET

—

C

0.49 × ET

×

0.51 × ET ×

C

PDF × DF/MF

0.47 × ET

PDF × DF/MF

0.53 × ET

•

With PLL enabled and MF > 4

×

—

×

C

PDF × DF/MF

Internal clock and CLKOUT cycle

time with PLL enabled

T

—

ET × PDF ×

—

C

DF/MF

Internal clock and CLKOUT cycle

time with PLL disabled

—

2 × ET

—

C

Instruction cycle time

I

T

C

—

CYC

Notes: 1. DF = Division Factor; Ef = External frequency; ET = External clock cycle; MF = Multiplication Factor;

C

PDF = Predivision Factor; T = internal clock cycle

C

2. See the PLL and Clock Generation section in the DSP56300 Family Manual for a detailed discussion

of the PLL.

2-4

AC Electrical Characteristics

2.6.2 External Clock Operation

The DSP56309 system clock is derived from the on-chip oscillator or is externally supplied. To use the

on-chip oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL;

examples are shown in Figure 2-1.

EXTAL

XTAL

EXTAL

XTAL

R

R2

C

R1

Note: Ensure that in

the PCTL Register:

■ XTLD (bit 16) = 0

Note: Ensure that in

the PCTL Register:

■ XTLD (bit 16) = 0

C

XTAL1

■ If f

≤ 200 kHz,

■ If f

> 200 kHz,

OSC

XTLR (bit 15) = 1

XTLR (bit 15) = 0

Fundamental Frequency

Fork Crystal Oscillator

Fundamental Frequency

Crystal Oscillator

Suggested Component Values:

OSC

f

= 20 MHz

f

= 4 MHz

f

= 32.768 kHz

OSC

R = 680 kΩ ± 10%

C = 56 pF ± 20%

R = 680 kΩ ± 10%

C = 22 pF ± 20%

R1 = 3.9 MΩ ± 10%

C = 22 pF ± 20%

R2 = 200 kΩ ± 10%

Calculations are for a 4/20 MHz crystal with the

following parameters:

Calculations are for a 32.768 kHz crystal with the

following parameters:

■ C of 30/20 pF,

L

■ C of 7/6 pF,

■ load capacitance (C ) of 12.5 pF,

0

L

■ series resistance of 100/20 Ω, and

■ drive level of 2 mW.

■ shunt capacitance (C ) of 1.8 pF,

■ series resistance of 40 kΩ, and

■ drive level of 1 µW.

0

Figure 2-1. Crystal Oscillator Circuits

If an externally-supplied square wave voltage source is used, disable the internal oscillator circuit during

bootup by setting XTLD (PCTL Register bit 16 = 1—see the DSP56309 User’s Manual). The external

square wave source connects to EXTAL; XTAL is not physically connected to the board or socket. Figure

2-2 shows the relationship between the EXTAL input and the internal clock and CLKOUT.

V

Midpoint

IHX

EXTAL

ET

H

V

L

ILX

2

3

Note:

The midpoint is 0.5 (V

+ V ).

IHX ILX

4

ET

C

5

CLKOUT with PLL

disabled

7

CLKOUT with PLL

enabled

7

6a

6b

Figure 2-2. External Clock Timing

2-5

AC Electrical Characteristics

Table 2-5. Clock Operation

Characteristics

100 MHz

No.

Symbol

Min

Max

1

2

Frequency of EXTAL (EXTAL Pin Frequency)

The rise and fall time of this external clock should be 3 ns maximum.

Ef

0

100.0

1, 2

EXTAL input high

6

•

With PLL disabled (46.7%–53.3% duty cycle )

ET

4.67 ns

4.25 ns

∞

H

6

•

With PLL enabled (42.5%–57.5% duty cycle )

157.0 µs

1, 2

3

4

EXTAL input low

•

6

With PLL disabled (46.7%–53.3% duty cycle )

With PLL enabled (42.5%–57.5% duty cycle )

ET

4.67 ns

4.25 ns

∞

L

6

157.0 µs

2

EXTAL cycle time

•

With PLL disabled

With PLL enabled

ET

10.00 ns

∞

C

273.1 µs

5

6

Internal clock change from EXTAL fall with PLL disabled

4.3 ns

0.0 ns

11.0 ns

1.8 ns

a.Internal clock rising edge from EXTAL rising edge with PLL enabled

3,5

(MF = 1 or 2 or 4, PDF = 1, Ef > 15 MHz)

b. Internal clock falling edge from EXTAL falling edge with PLL enabled

(MF ≤ 4, PDF ≠ 1, Ef / PDF > 15 MHz)

0.0 ns

1.8 ns

3,5

4

7

Instruction cycle time = I

= T

I

CYC

C

(see Figure 2-4) (46.7%–53.3% duty cycle)

•

With PLL disabled

With PLL enabled

20.0 ns

10.00 ns

∞

8.53 µs

Notes: 1. Measured at 50 percent of the input transition.

2. The maximum value for PLL enabled is given for minimum VCO frequency (see Table 2-4) and

maximum MF.

3. Periodically sampled and not 100 percent tested.

4. The maximum value for PLL enabled is given for minimum VCO frequency and maximum DF.

5. The skew is not guaranteed for any other MF value.

6. The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum

clock high or low time required for correction operation, however, remains the same at lower operating

frequencies; therefore, when a lower clock frequency is used, the signal symmetry may vary from the

specified duty cycle as long as the minimum high time and low time requirements are met.

2.6.3 Phase Lock Loop (PLL) Characteristics

Table 2-6. PLL Characteristics

Characteristics

100 MHz

Unit

Min

Max

Voltage Controlled Oscillator (VCO) frequency when PLL enabled

30

200

MHz

(MF × E × 2/PDF)

f

1

PLL external capacitor (PCAP pin to V

) (C

)

PCAP

CCP

•

@ MF ≤ 4

@ MF > 4

(580 × MF) − 100 (780 × MF) − 140

830 × MF 1470 × MF

pF

Note:

C

is the value of the PLL capacitor (connected between the PCAP pin and V

) computed using the

PCAP

CCP

appropriate expression listed above.

2-6

AC Electrical Characteristics

2.6.4 Reset, Stop, Mode Select, and Interrupt Timing

Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing⁶

100 MHz

No.

Characteristics

Expression

Unit

Min

Max

3

8

Delay from RESET assertion to all pins at reset value

—

26.0

ns

4

9

Required RESET duration

•

Power on, external clock generator, PLL disabled

Power on, external clock generator, PLL enabled

Power on, internal oscillator

During STOP, XTAL disabled (PCTL Bit 16 = 0)

During STOP, XTAL enabled (PCTL Bit 16 = 1)

During normal operation

50 × ET

1000 × ET

75000 × ET

500.0

10.0

0.75

25.0

—

ns

µs

ms

ns

C

2.5 × T

C

ns

10 Delay from asynchronous RESET deassertion to first external address

5

output (internal reset deassertion)

•

Minimum

Maximum

3.25 × T + 2.0

34.5

—

212.5

ns

C

20.25 × T + 10

C

11 Synchronous reset set-up time from RESET deassertion to CLKOUT

Transition 1

•

Minimum

Maximum

T

5.9

—

10.0

ns

C

12 Synchronous reset deasserted, delay time from the CLKOUT Transition 1

to the first external address output

•

Minimum

Maximum

3.25 × T + 1.0

33.5

—

203.5

ns

C

20.25 × T + 1.0

C

13 Mode select setup time

30.0

0.0

—

ns

14 Mode select hold time

15 Minimum edge-triggered interrupt request assertion width

16 Minimum edge-triggered interrupt request deassertion width

6.6

17 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external memory

access address out valid

•

Caused by first interrupt instruction fetch

Caused by first interrupt instruction execution

4.25 × T + 2.0

7.25 × T + 2.0

C

44.5

74.5

—

ns

C

18 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to general-purpose

transfer output valid caused by first interrupt instruction execution

10 × T + 5.0

105.0

—

ns

C

19 Delay from address output valid caused by first interrupt instruction

(WS + 3.75) × T – 10.94

—

Note 8

ns

C

1,

execute to interrupt request deassertion for level sensitive fast interrupts

7, 8

20 Delay from RD assertion to interrupt request deassertion for level

(WS + 3.25) × T – 10.94

—

Note 8

ns

C

1, 7, 8

sensitive fast interrupts

21 Delay from WR assertion to interrupt request deassertion for level

1, 7, 8

sensitive fast interrupts

•

DRAM for all WS

SRAM WS = 1

SRAM WS = 2, 3

SRAM WS ≥ 4

(WS + 3.5) × T – 10.94

—

Note 8

ns

C

(WS + 3.5) × T – 10.94

C

(WS + 3) × T – 10.94

C

(WS + 2.5) × T – 10.94

C

22 Synchronous interrupt set-up time from IRQA, IRQB, IRQC, IRQD, NMI

assertion to the CLKOUT Transition 2

5.9

T

ns

C

23 Synchronous interrupt delay time from the CLKOUT Transition 2 to the

first external address output valid caused by the first instruction fetch after

coming out of Wait Processing state

•

Minimum

Maximum

8.25 × T + 1.0

83.5

—

252.5

ns

C

24.75 × T + 5.0

C

24 Duration for IRQA assertion to recover from Stop state

5.9

—

ns

2-7

AC Electrical Characteristics

Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing⁶(Continued)

100 MHz

No.

Characteristics

Expression

Unit

Min

Max

25 Delay from IRQA assertion to fetch of first instruction (when exiting

2, 3

Stop)

•

PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is

enabled (Operating Mode Register Bit 6 = 0)

PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is not

enabled (Operating Mode Register Bit 6 = 1)

PLC × ET × PDF + (128 K −

1.3

9.1

ms

ns

C

PLC/2) × T

C

PLC × ET × PDF + (23.75 ± 232.5 ns 12.3 ms

C

0.5) × T

C

PLL is active during Stop (PCTL Bit 17 = 1) (Implies No Stop Delay)

(8.25 ± 0.5) × T

87.5

97.5

C

26 Duration of level sensitive IRQA assertion to ensure interrupt service

2, 3

(when exiting Stop)

•

PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is

enabled (Operating Mode Register Bit 6 = 0)

PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is not

enabled (Operating Mode Register Bit 6 = 1)

PLC × ET × PDF + (128K −

13.6

12.3

55.0

—

ms

ns

C

PLC/2) × T

C

PLC × ET × PDF +

C

(20.5 ± 0.5) × T

C

PLL is active during Stop (PCTL Bit 17 = 1) (implies no Stop delay)

5.5 × T

C

27 Interrupt Requests Rate

Maximum:

12 × T

•

HI08, ESSI, SCI, Timer

DMA

IRQ, NMI (edge trigger)

IRQ, NMI (level trigger)

—

120.0

80.0

ns

C

8 × T

C

12 × T

120.0

C

28 DMA Requests Rate

Maximum:

•

Data read from HI08, ESSI, SCI

Data write to HI08, ESSI, SCI

Timer

6 × T

7 × T

2 × T

3 × T

—

60.0

70.0

20.0

30.0

ns

C

IRQ, NMI (edge trigger)

29 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external memory

(DMA source) access address out valid

Minimum:

4.25 × T + 2.0

30.3

—

ns

C

2-8

AC Electrical Characteristics

Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing⁶(Continued)

100 MHz

Min Max

No.

Characteristics

Expression

Unit

Notes: 1. When fast interrupts are used and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to

prevent multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-triggered mode is recommended when

fast interrupts are used. Long interrupts are recommended for Level-sensitive mode.

2. This timing depends on several settings:

• For PLL disable, using internal oscillator (PLL Control Register (PCTL) Bit 16 = 0) and oscillator disabled during Stop (PCTL Bit

17 = 0), a stabilization delay is required to assure that the oscillator is stable before programs are executed. Resetting the Stop

delay (Operating Mode Register Bit 6 = 0) provides the proper delay. While Operating Mode Register Bit 6 = 1 can be set, it is not

recommended, and these specifications do not guarantee timings for that case.

• For PLL disable, using internal oscillator (PCTL Bit 16 = 0) and oscillator enabled during Stop (PCTL Bit 17=1), no stabilization

delay is required and recovery is minimal (Operating Mode Register Bit 6 setting is ignored).

• For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time is defined by the

PCTL Bit 17 and Operating Mode Register Bit 6 settings.

• For PLL enable, if PCTL Bit 17 is 0, the PLL is shutdown during Stop. Recovering from Stop requires the PLL to get locked. The

PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0 to 1000 cycles. This procedure occurs in parallel

with the stop delay counter, and stop recovery ends when the last of these two events occurs. The stop delay counter completes

count or PLL lock procedure completion.

• PLC value for PLL disable is 0.

• The maximum value for ET is 4096 (maximum MF) divided by the desired internal frequency (that is, for 66 MHz it is 4096/66

C

MHz = 62 µs). During the stabilization period, T , T and T is not constant, and their width may vary, so timing may vary as

C

H,

L

well.

3. Periodically sampled and not 100 percent tested.

4. Value depends on clock source:

• For an external clock generator, RESET duration is measured while RESET is asserted, V is valid, and the EXTAL input is

CC

active and valid.

• For an internal oscillator, RESET duration is measured while RESET is asserted and V is valid. The specified timing reflects

CC

the crystal oscillator stabilization time after power-up. This number is affected both by the specifications of the crystal and other

components connected to the oscillator and reflects worst case conditions.

• When the V is valid, but the other “required RESET duration” conditions (as specified above) have not been yet met, the

CC

device circuitry is in an uninitialized state that can result in significant power consumption and heat-up. Designs should minimize

this state to the shortest possible duration.

5. If PLL does not lose lock.

6.

V

= 3.3 V ± 0.3 V; T = –40°C to +100°C, C = 50 pF.

CC J L

7. WS = number of wait states (measured in clock cycles, number of T ).

C

8. Use the expression to compute a maximum value.

V

IH

RESET

9

10

8

All Pins

Reset Value

First Fetch

A[0–17]

Figure 2-3. Reset Timing

2-9

AC Electrical Characteristics

CLKOUT

RESET

11

12

A[0–17]

Figure 2-4. Synchronous Reset Timing

First Interrupt Instruction

Execution/Fetch

A[0–17]

RD

20

21

WR

17

19

IRQA, IRQB,

IRQC, IRQD,

NMI

a) First Interrupt Instruction Execution

General

Purpose

I/O

18

IRQA, IRQB,

IRQC, IRQD,

NMI

b) General-Purpose I/O

Figure 2-5. External Fast Interrupt Timing

2-10

AC Electrical Characteristics

IRQA, IRQB,

IRQC, IRQD, NMI

15

16

IRQA, IRQB,

IRQC, IRQD, NMI

Figure 2-6. External Interrupt Timing (Negative Edge-Triggered)

CLKOUT

IRQA, IRQB,

IRQC, IRQD,

NMI

22

23

A[0–17]

Figure 2-7. Synchronous Interrupt from Wait State Timing

V

IH

RESET

13

14

V

IH

MODA, MODB,

MODC, MODD,

PINIT

IRQA, IRQB,

IRQC, IRQD, NMI

V

IL

Figure 2-8. Operating Mode Select Timing

2-11

AC Electrical Characteristics

24

IRQA

25

First Instruction Fetch

A[0–17]

Figure 2-9. Recovery from Stop State Using IRQA

26

IRQA

25

First IRQA Interrupt

Instruction Fetch

A[0–17]

Figure 2-10. Recovery from Stop State Using IRQA Interrupt Service

DMA Source Address

A[0–17]

RD

WR

29

IRQA, IRQB,

IRQC, IRQD,

NMI

First Interrupt Instruction Execution

Figure 2-11. External Memory Access (DMA Source) Timing

2-12

AC Electrical Characteristics

2.6.5 External Memory Expansion Port (Port A)

2.6.5.1 SRAM Timing

Table 2-8. SRAM Read and Write Accesses

Expression¹

100 MHz

No.

Characteristics

Symbol

Unit

Min Max

2

100 Address valid and AA assertion pulse width

101 Address and AA valid to WR assertion

102 WR assertion pulse width

t

, t

(WS + 1) × T − 4.0

16.0

56.0

—

ns

RC WC

C

[1 ≤ WS ≤ 3]

(WS + 2) × T − 4.0

C

[4 ≤ WS ≤ 7]

(WS + 3) × T − 4.0

106.0

C

[WS ≥ 8]

t

0.25 × T − 2.0

0.5

5.5

—

ns

AS

C

[WS = 1]

0.75 × T − 2.0

C

[2 ≤ WS ≤ 3]

1.25 × T − 2.0

10.5

C

[WS ≥ 4]

t

1.5 × T − 4.0

11.0

16.0

31.0

—

ns

WP

C

[WS = 1]

WS × T − 4.0

C

[2 ≤ WS ≤ 3]

(WS − 0.5) × T − 4.0

C

[WS ≥ 4]

103 WR deassertion to address not valid

t

0.25 × T − 2.0

[1 ≤ WS ≤ 3]

0.5

8.5

—

ns

WR

C

1.25 × T − 4.0

C

[4 ≤ WS ≤ 7]

2.25 × T − 4.0

18.5

C

[WS ≥ 8]

104 Address and AA valid to input data valid

105 RD assertion to input data valid

t

, t

(WS + 0.75) × T − 5.0

—

12.5

7.5

—

ns

AA AC

C

[WS ≥ 1]

t

(WS + 0.25) × T – 5.0

OE

C

[WS ≥ 1]

106 RD deassertion to data not valid (data hold

time)

t

0.0

13.5

4.5

OHZ

2

107 Address valid to WR deassertion

t

(WS + 0.75) × T − 4.0

—

AW

C

[WS ≥ 1]

108 Data valid to WR deassertion (data setup

time)

t

(t

)

(WS − 0.25) × T − 3.0

—

DS DW

C

[WS ≥ 1]

109 Data hold time from WR deassertion

t

0.25 × T − 2.0

[1 ≤ WS ≤ 3]

0.5

—

ns

DH

C

1.25 × T − 2.0

10.5

20.5

C

[4 ≤ WS ≤ 7]

2.25 × T − 2.0

C

[WS ≥ 8]

110 WR assertion to data active

—

0.75 × T − 3.7

3.8

—

ns

C

[WS = 1]

0.25 × T – 3.7

–1.2

–6.2

C

[2 ≤ WS ≤ 3]

–0.25 × T − 3.7

C

[WS ≥ 4]

2-13

AC Electrical Characteristics

Table 2-8. SRAM Read and Write Accesses (Continued)

100 MHz

No.

Characteristics

Symbol

Expression¹

Unit

Min Max

111 WR deassertion to data high impedance

112 Previous RD deassertion to data active (write)

113 RD deassertion time

—

0.25 × T + 0.2

—

2.7

ns

C

[1 ≤ WS ≤ 3]

1.25 × TC + 0.2

[4 ≤ WS ≤ 7]

12.7

22.7

2.25 × T + 0.2

C

[WS > 8]

—

1.25 × T – 4.0

8.5

—

ns

C

[1 ≤ WS ≤ 3]

2.25 × T – 4.0

18.5

28.5

C

[4 ≤ WS ≤ 7]

3.25 × T – 4.0

C

[WS > 8]

0.75 × T − 4.0

3.5

—

ns

C

[1 ≤ WS ≤ 3]

1.75 × T − 4.0

13.5

23.5

C

[4 ≤ WS ≤ 7]

2.75 × T − 4.0

C

[WS ≥ 8]

114 WR deassertion time

0.5 × T − 4.0

1.0

6.0

—

ns

C

[WS = 1]

T

− 4.0

C

[2 ≤ WS ≤ 3]

2.5 × T − 4.0

21.0

31.0

C

[4 ≤ WS ≤ 7]

3.5 × T − 4.0

C

[WS ≥ 8]

115 Address valid to RD assertion

116 RD assertion pulse width

—

0.5 × T − 4.0

1.0

8.5

0.5

—

ns

C

(WS + 0.25) × T −4.0

C

117 RD deassertion to address not valid

0.25 × T − 2.0

C

[1 ≤ WS ≤ 3]

1.25 × T − 2.0

[4 ≤ WS ≤ 7]

10.5

20.5

—

ns

C

2.25 × T − 2.0

C

[WS ≥ 8]

4

118 TA setup before RD or WR deassertion

—

0.25 × T + 2.0

4.5

0

—

ns

C

119 TA hold after RD or WR deassertion

—

Notes: 1. WS is the number of wait states specified in the BCR. An expression is used to compute the number

listed as the minimum or maximum value, as appropriate.

2. Timings 100, 107 are guaranteed by design, not tested.

3. All timings for 100 MHz are measured from 0.5 × Vcc to 0.5 × Vcc.

4. Timing 118 is relative to the deassertion edge of RD or WR even if TA remains asserted.

5.

V

= 3.3 V ± 0.3 V; T = –40°C to +100°C, C = 50 pF

CC J L

2-14

AC Electrical Characteristics

100

A[0–17]

AA[0–3]

117

106

113

116

RD

105

WR

104

118

119

TA

Data

In

D[0–23]

Note: Address lines A[0–17] hold their state after a

read or write operation. AA[0–3] do not hold their

state after a read or write operation.

Figure 2-12. SRAM Read Access

100

A[0–17]

AA[0–3]

107

101

102

103

WR

RD

114

119

118

TA

108

109

Data

Out

D[0–23]

Note: Address lines A[0–17] hold their state after a

read or write operation. AA[0–3] do not hold their

state after a read or write operation.

Figure 2-13. SRAM Write Access

2-15

AC Electrical Characteristics

2.6.5.2 DRAM Timing

The selection guides in Figure 2-14 and Figure 2-17 are for primary selection only. Final selection

should be based on the timing in the following tables. For example, the selection guide suggests that four

wait states must be used for 100 MHz operation with Page Mode DRAM. However, consulting the

appropriate table, a designer can evaluate whether fewer wait states might suffice by determining which

timing prevents operation at 100 MHz, running the chip at a slightly lower frequency (for example, 95

MHz), using faster DRAM (if it becomes available), and manipulating control factors such as capacitive

and resistive load to improve overall system performance.

Note:

This figure should be used for primary selection. For exact

and detailed timings, see the following tables.

DRAM type

(tRAC ns)

100

80

70

60

Chip frequency

(MHz)

50

120

40

66

80

100

1 Wait states

2 Wait states

3 Wait states

4 Wait states

Figure 2-14. DRAM Page Mode Wait State Selection Guide

2-16

AC Electrical Characteristics

Table 2-9. DRAM Page Mode Timings, Three Wait States^1,2,3

Expression⁴

100 MHz

No.

Characteristics

Symbol

Unit

Min Max

131 Page mode cycle time for two consecutive accesses of the

same direction

4 × T

40.0

—

ns

C

Page mode cycle time for mixed (read and write) accesses

132 CAS assertion to data valid (read)

t

3.5 × T

35.0

—

14.3

24.3

—

ns

PC

C

t

2 × T − 5.7

C

CAC

133 Column address valid to data valid (read)

134 CAS deassertion to data not valid (read hold time)

135 Last CAS assertion to RAS deassertion

136 Previous CAS deassertion to RAS deassertion

137 CAS assertion pulse width

t

3 × T − 5.7

—

AA

C

t

0.0

OFF

RSH

t

2.5 × T − 4.0

21.0

41.0

16.0

—

C

t

4.5 × T − 4.0

—

RHCP

C

t

2 × T − 4.0

—

CAS

C

5

138 Last CAS deassertion to RAS assertion

t

CRP

•

BRW[1–0] = 00, 01—not applicable

BRW[1–0] = 10

BRW[1–0] = 11

—

41.5

61.5

—

ns

4.75 × T − 6.0

C

6.75 × T − 6.0

C

139 CAS deassertion pulse width

t

1.5 × T − 4.0

11.0

6.0

—

ns

CP

C

140 Column address valid to CAS assertion

141 CAS assertion to column address not valid

142 Last column address valid to RAS deassertion

143 WR deassertion to CAS assertion

144 CAS deassertion to WR assertion

145 CAS assertion to WR deassertion

146 WR assertion pulse width

t

T − 4.0

C

ASC

t

2.5 × T − 4.0

21.0

36.0

8.5

—

CAH

C

t

4 × T − 4.0

—

RAL

RCS

RCH

C

t

1.25 × T − 4.0

—

C

t

0.75 × T − 4.0

3.5

—

C

t

2.25 × T − 4.2

18.3

30.5

33.2

28.2

0.5

—

WCH

C

t

3.5 × T − 4.5

—

WP

C

147 Last WR assertion to RAS deassertion

148 WR assertion to CAS deassertion

149 Data valid to CAS assertion (write)

150 CAS assertion to data not valid (write)

151 WR assertion to CAS assertion

t

3.75 × T − 4.3

—

RWL

CWL

C

t

3.25 × T − 4.3

—

C

t

0.5 × T – 4.5

—

DS

C

t

2.5 × T − 4.0

21.0

8.2

—

DH

C

t

1.25 × T − 4.3

—

WCS

C

152 Last RD assertion to RAS deassertion

153 RD assertion to data valid

t

3.5 × T − 4.0

31.0

—

ROH

C

t

2.5 × T − 5.7

19.3

—

GA

C

6

154 RD deassertion to data not valid

t

0.0

GZ

155 WR assertion to data active

0.75 × T – 1.5

6.0

—

C

156 WR deassertion to data high impedance

0.25 × T

—

2.5

C

Notes: 1. The number of wait states for Page mode access is specified in the DRAM Control Register.

2. The refresh period is specified in the DRAM Control Register.

3. The asynchronous delays specified in the expressions are valid for the DSP56309.

4. All the timings are calculated for the worst case. Some of the timings are better for specific cases (for

example, t equals 4 × T for read-after-read or write-after-write sequences). An expression is used to

PC

C

compute the number listed as the minimum or maximum value listed, as appropriate.

5. BRW[1–0] (DRAM control register bits) defines the number of wait states that should be inserted in each

DRAM out-of page-access.

6. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t

and not t

.

GZ

OFF

2-17

AC Electrical Characteristics

Table 2-10. DRAM Page Mode Timings, Four Wait States^1,2,3

Expression⁴

100 MHz

No.

Characteristics

Symbol

Unit

Min Max

131 Page mode cycle time for two consecutive accesses of the

same direction

5 × T

50.0

—

ns

C

Page mode cycle time for mixed (read and write) accesses

132 CAS assertion to data valid (read)

t

4.5 × T

45.0

—

21.8

31.8

—

ns

PC

C

t

2.75 × T − 5.7

C

CAC

133 Column address valid to data valid (read)

134 CAS deassertion to data not valid (read hold time)

135 Last CAS assertion to RAS deassertion

136 Previous CAS deassertion to RAS deassertion

137 CAS assertion pulse width

t

3.75 × T − 5.7

—

AA

C

t

0.0

OFF

RSH

t

3.5 × T − 4.0

31.0

56.0

21.0

—

C

t

6 × T − 4.0

—

RHCP

C

t

2.5 × T − 4.0

—

CAS

C

5

138 Last CAS deassertion to RAS assertion

t

CRP

•

BRW[1–0] = 00, 01—Not applicable

BRW[1–0] = 10

BRW[1–0] = 11

—

46.5

66.5

—

ns

5.25 × T − 6.0

C

7.25 × T − 6.0

C

139 CAS deassertion pulse width

t

2 × T − 4.0

16.0

6.0

—

ns

CP

C

140 Column address valid to CAS assertion

141 CAS assertion to column address not valid

142 Last column address valid to RAS deassertion

143 WR deassertion to CAS assertion

144 CAS deassertion to WR assertion

145 CAS assertion to WR deassertion

146 WR assertion pulse width

t

T − 4.0

C

ASC

t

3.5 × T − 4.0

31.0

46.0

8.5

—

CAH

C

t

5 × T − 4.0

—

RAL

RCS

RCH

C

t

1.25 × T − 4.0

—

C

t

1.25 × T – 3.7

8.8

—

C

t

3.25 × T − 4.2

28.3

40.5

43.2

33.2

0.5

—

WCH

C

t

4.5 × T − 4.5

—

WP

C

147 Last WR assertion to RAS deassertion

148 WR assertion to CAS deassertion

149 Data valid to CAS assertion (write)

150 CAS assertion to data not valid (write)

151 WR assertion to CAS assertion

t

4.75 × T − 4.3

—

RWL

CWL

C

t

3.75 × T − 4.3

—

C

t

0.5 × T – 4.5

—

DS

C

t

3.5 × T − 4.0

31.0

8.2

—

DH

C

t

1.25 × T − 4.3

—

WCS

C

152 Last RD assertion to RAS deassertion

153 RD assertion to data valid

t

4.5 × T − 4.0

41.0

—

ROH

C

t

3.25 × T − 5.7

26.8

—

GA

C

6

154 RD deassertion to data not valid

t

0.0

GZ

155 WR assertion to data active

0.75 × T – 1.5

6.0

—

C

156 WR deassertion to data high impedance

0.25 × T

—

2.5

C

Notes: 1. The number of wait states for Page mode access is specified in the DRAM Control Register.

2. The refresh period is specified in the DRAM Control Register.

3. The asynchronous delays specified in the expressions are valid for the DSP56309.

4. All the timings are calculated for the worst case. Some of the timings are better for specific cases (for

example, t equals 3 × T for read-after-read or write-after-write sequences). An expressions is used to

PC

C

calculate the maximum or minimum value listed, as appropriate.

5. BRW[1–0] (DRAM control register bits) defines the number of wait states that should be inserted in each

DRAM out-of-page access.

6. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t

and not t

.

GZ

OFF

2-18

AC Electrical Characteristics

RAS

CAS

136

135

131

137

139

138

142

140

151

141

Column

Address

Last Column

Address

Column

Address

Row

Add

A[0–17]

144

145

147

148

WR

RD

146

155

156

150

149

D[0–23]

Data Out

Figure 2-15. DRAM Page Mode Write Accesses

RAS

CAS

136

135

131

137

140

139

141

138

142

Row

Add

Last Column

Address

Column

Address

Column

Address

A[0–17]

WR

143

132

133

153

152

RD

134

154

D[0–23]

Data In

Figure 2-16. DRAM Page Mode Read Accesses

2-19

AC Electrical Characteristics

DRAM Type

(tRAC ns)

Note:

This figure should be used for primary selection. For exact and

detailed timings, see the following tables.

100

80

70

60

50

Chip Frequency

(MHz)

120

40

66

80

100

4 Wait States

8 Wait States

11 Wait States

15 Wait States

Figure 2-17. DRAM Out-of-Page Wait State Selection Guide

Table 2-11. DRAM Out-of-Page and Refresh Timings, Eleven Wait States^1,2

100 MHz

No.

Characteristics

Symbol

Expression³

Unit

Min Max

157 Random read or write cycle time

t

12 × T

120.0

—

55.5

30.5

38.0

—

ns

RC

C

158 RAS assertion to data valid (read)

159 CAS assertion to data valid (read)

160 Column address valid to data valid (read)

161 CAS deassertion to data not valid (read hold time)

162 RAS deassertion to RAS assertion

163 RAS assertion pulse width

t

6.25 × T − 7.0

C

RAC

t

3.75 × T − 7.0

—

CAC

C

t

4.5 × T − 7.0

—

AA

C

t

0.0

OFF

t

4.25 × T − 4.0

38.5

73.5

48.5

58.5

33.5

21.0

13.5

53.5

36.5

—

RP

C

t

7.75 × T − 4.0

—

RAS

RSH

CSH

C

164 CAS assertion to RAS deassertion

165 RAS assertion to CAS deassertion

166 CAS assertion pulse width

t

5.25 × T − 4.0

—

C

6.25 × T − 4.0

—

C

t

3.75 × T − 4.0

—

CAS

RCD

C

167 RAS assertion to CAS assertion

168 RAS assertion to column address valid

169 CAS deassertion to RAS assertion

170 CAS deassertion pulse width

t

2.5 × T ± 4.0

29.0

21.5

—

C

t

1.75 × T ± 4.0

C

RAD

t

5.75 × T − 4.0

C

CRP

t

4.25 × T – 6.0

—

CP

C

2-20

AC Electrical Characteristics

Table 2-11. DRAM Out-of-Page and Refresh Timings, Eleven Wait States^1,2(Continued)

100 MHz

No.

Characteristics

Symbol

Expression³

Unit

Min Max

171 Row address valid to RAS assertion

172 RAS assertion to row address not valid

173 Column address valid to CAS assertion

174 CAS assertion to column address not valid

175 RAS assertion to column address not valid

176 Column address valid to RAS deassertion

177 WR deassertion to CAS assertion

t

4.25 × T − 4.0

38.5

13.5

3.5

—

93.0

—

2.5

ns

ASR

C

t

1.75 × T − 4.0

C

RAH

t

0.75 × T − 4.0

C

ASC

t

5.25 × T − 4.0

48.5

73.5

56.0

26.0

13.8

0.5

CAH

C

t

7.75 × T − 4.0

C

AR

t

6 × T − 4.0

C

RAL

RCS

RCH

RRH

t

3.0 × T − 4.0

C

4

178 CAS deassertion to WR assertion

t

1.75 × T – 3.7

C

4

179 RAS deassertion to WR assertion

0.25 × T − 2.0

C

180 CAS assertion to WR deassertion

181 RAS assertion to WR deassertion

182 WR assertion pulse width

t

5 × T − 4.2

45.8

70.8

110.5

113.2

98.2

53.5

48.5

73.5

60.7

11.0

23.5

111.0

—

WCH

WCR

C

7.5 × T − 4.2

C

t

11.5 × T − 4.5

C

WP

183 WR assertion to RAS deassertion

184 WR assertion to CAS deassertion

185 Data valid to CAS assertion (write)

186 CAS assertion to data not valid (write)

187 RAS assertion to data not valid (write)

188 WR assertion to CAS assertion

189 CAS assertion to RAS assertion (refresh)

190 RAS deassertion to CAS assertion (refresh)

191 RD assertion to RAS deassertion

192 RD assertion to data valid

t

11.75 × T − 4.3

C

RWL

CWL

t

10.25 × T − 4.3

C

t

5.75 × T − 4.0

C

DS

t

5.25 × T − 4.0

C

DH

t

7.75 × T − 4.0

DHR

WCS

C

t

6.5 × T − 4.3

C

t

1.5 × T − 4.0

C

CSR

t

2.75 × T − 4.0

C

RPC

t

11.5 × T − 4.0

C

ROH

t

10 × T − 7.0

C

GA

5

193 RD deassertion to data not valid

t

0.0

GZ

194 WR assertion to data active

0.75 × T – 1.5

6.0

C

195 WR deassertion to data high impedance

0.25 × T

—

C

Notes: 1. The number of wait states for an out-of-page access is specified in the DRAM Control Register.

2. The refresh period is specified in the DRAM Control Register.

3. Use the expression to compute the maximum or minimum value listed (or both if the expression includes ±).

4. Either t or t must be satisfied for read cycles.

RCH

RRH

5. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t

and not t

.

GZ

OFF

2-21

AC Electrical Characteristics

Table 2-12. DRAM Out-of-Page and Refresh Timings, Fifteen Wait States^1,2

100 MHz

No.

Characteristics

Symbol

Expression³

Unit

Min Max

157 Random read or write cycle time

t

16 × T

160.0

—

76.8

41.8

49.3

—

ns

RC

C

158 RAS assertion to data valid (read)

159 CAS assertion to data valid (read)

160 Column address valid to data valid (read)

161 CAS deassertion to data not valid (read hold time)

162 RAS deassertion to RAS assertion

163 RAS assertion pulse width

t

8.25 × T − 5.7

C

RAC

t

4.75 × T − 5.7

—

CAC

C

t

5.5 × T − 5.7

—

AA

C

t

0.0

OFF

t

6.25 × T − 4.0

58.5

93.5

58.5

78.5

43.5

33.0

25.5

73.5

56.5

58.5

23.5

3.5

—

RP

C

t

9.75 × T − 4.0

—

RAS

RSH

CSH

C

164 CAS assertion to RAS deassertion

165 RAS assertion to CAS deassertion

166 CAS assertion pulse width

t

6.25 × T − 4.0

—

C

8.25 × T − 4.0

—

C

t

4.75 × T − 4.0

—

CAS

RCD

C

167 RAS assertion to CAS assertion

t

3.5 × T ± 2

37.0

29.5

—

C

168 RAS assertion to column address valid

169 CAS deassertion to RAS assertion

170 CAS deassertion pulse width

t

2.75 × T ± 2

C

RAD

t

7.75 × T − 4.0

C

CRP

t

6.25 × T – 6.0

—

CP

C

171 Row address valid to RAS assertion

172 RAS assertion to row address not valid

173 Column address valid to CAS assertion

174 CAS assertion to column address not valid

175 RAS assertion to column address not valid

176 Column address valid to RAS deassertion

177 WR deassertion to CAS assertion

t

6.25 × T − 4.0

—

ASR

RAH

C

t

2.75 × T − 4.0

—

C

t

0.75 × T − 4.0

—

ASC

C

t

6.25 × T − 4.0

58.5

93.5

66.0

46.2

13.8

0.5

—

CAH

C

t

9.75 × T − 4.0

—

AR

C

t

7 × T − 4.0

—

RAL

RCS

RCH

RRH

C

t

5 × T − 3.8

—

C

4

178 CAS deassertion to WR assertion

t

1.75 × T – 3.7

—

C

4

179 RAS deassertion to WR assertion

0.25 × T − 2.0

—

C

180 CAS assertion to WR deassertion

181 RAS assertion to WR deassertion

182 WR assertion pulse width

t

6 × T − 4.2

55.8

90.8

150.5

153.2

138.2

83.5

58.5

93.5

90.7

11.0

43.5

151.0

—

WCH

WCR

C

9.5 × T − 4.2

—

C

t

15.5 × T − 4.5

—

WP

C

183 WR assertion to RAS deassertion

184 WR assertion to CAS deassertion

185 Data valid to CAS assertion (write)

186 CAS assertion to data not valid (write)

187 RAS assertion to data not valid (write)

188 WR assertion to CAS assertion

189 CAS assertion to RAS assertion (refresh)

190 RAS deassertion to CAS assertion (refresh)

191 RD assertion to RAS deassertion

192 RD assertion to data valid

t

15.75 × T − 4.3

—

RWL

CWL

C

t

14.25 × T − 4.3

—

C

t

8.75 × T − 4.0

—

DS

DH

C

t

6.25 × T − 4.0

—

C

t

9.75 × T − 4.0

—

DHR

WCS

C

t

9.5 × T − 4.3

—

C

t

1.5 × T − 4.0

—

CSR

C

t

4.75 × T − 4.0

—

RPC

C

t

15.5 × T − 4.0

—

ROH

C

t

14 × T − 5.7

134.3

—

GA

C

5

193 RD deassertion to data not valid

t

0.0

GZ

194 WR assertion to data active

0.75 × T – 1.5

6.0

—

C

195 WR deassertion to data high impedance

0.25 × T

—

2.5

C

2-22

AC Electrical Characteristics

Table 2-12. DRAM Out-of-Page and Refresh Timings, Fifteen Wait States^1,2(Continued)

100 MHz

No.

Characteristics

Symbol

Expression³

Unit

Min Max

Notes: 1. The number of wait states for an out-of-page access is specified in the DRAM Control Register.

2. The refresh period is specified in the DRAM Control Register.

3. Use the expression to compute the maximum or minimum value listed (or both if the expression includes ±).

4. Either t or t must be satisfied for read cycles.

RCH

RRH

5. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t

and not t

.

GZ

OFF

157

163

162

165

RAS

167

168

164

169

170

166

CAS

171

173

174

175

Row Address

172

Column Address

176

A[0–17]

177

179

191

WR

RD

178

160

159

158

193

192

161

Data

In

D[0–23]

Figure 2-18. DRAM Out-of-Page Read Access

2-23

AC Electrical Characteristics

157

162

163

162

165

RAS

167

164

169

168

166

170

CAS

173

172

171

174

176

Row Address

Column Address

A[0–17]

181

175

188

180

182

WR

184

183

187

RD

186

195

185

194

Data Out

D[0–23]

Figure 2-19. DRAM Out-of-Page Write Access

157

162

163

RAS

190

170

177

165

189

CAS

WR

Figure 2-20. DRAM Refresh Access

2-24

AC Electrical Characteristics

2.6.5.3 Synchronous Timings

Table 2-13. External Bus Synchronous Timings^1,2

100 MHz

Min Max

No.

Characteristics

Expression^3,4,5

Unit

6

198

199

200

201

202

203

204

205

206

207

208

209

210

CLKOUT high to address, and AA valid

0.25 × T + 4.0

—

6.5

ns

C

6

CLKOUT high to address, and AA invalid

TA valid to CLKOUT high (set-up time)

CLKOUT high to TA invalid (hold time)

CLKOUT high to data out active

0.25 × T

2.5

4.0

0.0

2.5

—

C

—

0.25 × T

—

C

CLKOUT high to data out valid

0.25 × T + 4.0

6.5

—

C

CLKOUT high to data out invalid

0.25 × T

2.5

—

C

CLKOUT high to data out high impedance

Data in valid to CLKOUT high (set-up)

CLKOUT high to data in invalid (hold)

CLKOUT high to RD assertion

2.5

—

4.0

0.0

6.7

0.0

5.0

—

maximum: 0.75 × T + 2.5

10.0

4.0

9.3

C

CLKOUT high to RD deassertion

2

CLKOUT high to WR assertion

maximum: 0.5 × T + 4.3

C

for WS = 1 or WS ≥ 4

for 2 ≤ WS ≤ 3

0.0

4.3

3.8

ns

211

CLKOUT high to WR deassertion

Notes: 1. Use external bus synchronous timings only for reference to the clock and not for relative timings.

2. Synchronous Bus Arbitration is not recommended. Use Asynchronous mode whenever possible.

3. WS is the number of wait states specified in the BCR.

4. If WS > 1, WR assertion refers to the next rising edge of CLKOUT.

5. Use the expression to compute the maximum or minimum value listed, as appropriate. For timing

210, the minimum is an absolute value.

6. T198 and T199 are valid for Address Trace mode if the ATE bit in the Operating Mode Register is set.

when this mode is enabled, use the status of BR (See T212) to determine whether the access

referenced by A[0–17] is internal or external.

2-25

AC Electrical Characteristics

198

CLKOUT

A[0–17]

AA[0–3]

199

201

200

TA

211

WR

205

210

203

204

D[0–23]

Data Out

208

202

209

RD

207

206

D[0–23]

Data In

Note: Address lines A[0–17] hold their state after a read or write operation. AA[0–3] do not hold their state

after a read or write operation.

Figure 2-21. Synchronous Bus Timings 1 WS (BCR Controlled)

CLKOUT

A[0–17]

AA[0–3]

199

201

198

201

200

211

TA

200

WR

210

205

203

202

204

Data Out

D[0–23]

208

209

RD

207

206

Data In

D[0–23]

Note: Address lines A[0–17] hold their state after a read or write operation. AA[0–3] do not hold their

state after a read or write operation.

Figure 2-22. Synchronous Bus Timings 2 WS (TA Controlled)

2-26

AC Electrical Characteristics

2.6.5.4 Arbitration Timings

Table 2-14. Arbitration Bus Timings¹

100 MHz

Min Max

No.

Characteristics

Expression²

Unit

3

212

213

CLKOUT high to BR assertion/deassertion

0.0

4.0

ns

BG asserted/deasserted to CLKOUT high

(setup)

4.0

—

ns

214

CLKOUT high to BG deasserted/asserted

(hold)

0.0

—

ns

215

216

217

218

219

220

221

BB deassertion to CLKOUT high (input set-up)

CLKOUT high to BB assertion (input hold)

CLKOUT high to BB assertion (output)

CLKOUT high to BB deassertion (output)

BB high to BB high impedance (output)

CLKOUT high to address and controls active

4.0

0.0

—

ns

4.0

4.5

—

0.25 × T

0.75 × T

2.5

—

C

CLKOUT high to address and controls high

impedance

7.5

222

223

224

CLKOUT high to AA active

0.25 × T

2.5

2.0

—

ns

C

CLKOUT high to AA deassertion

CLKOUT high to AA high impedance

maximum: 0.25 × T + 4.0

6.5

7.5

C

0.75 × T

C

Notes: 1. Synchronous Bus Arbitration is not recommended. Use Asynchronous mode whenever possible.

2. An expression is used to compute the maximum or minimum value listed, as appropriate. For timing

223, the minimum is an absolute value.

3. T212 is valid for Address Trace mode when the ATE bit in the Operating Mode Register is set. BR is

deasserted for internal accesses and asserted for external accesses.

2-27

AC Electrical Characteristics

CLKOUT

BR

214

216

212

213

215

BG

BB

217

220

A[0–17]

RD, WR

222

AA[0–3]

Note: Address lines A[0–17] hold their state after a read or write operation. AA[0–3] do not hold their

state after a read or write operation.

Figure 2-23. Bus Acquisition Timings

CLKOUT

BR

214

213

212

BG

219

218

BB

221

A[0–17]

RD, WR

224

223

AA[0–3]

Note: Address lines A[0–17] hold their state after a read or write operation. AA[0–3] do not hold their

state after a read or write operation.

Figure 2-24. Bus Release Timings Case 1 (BRT Bit in Operating Mode Register Cleared)

2-28

AC Electrical Characteristics

CLKOUT

BR

212

214

213

BG

BB

219

218

221

A[0–17]

RD, WR

224

223

AA[0–3]

Note: Address lines A[0–17] hold their state after a read or write operation. AA[0–3] do not hold their

state after a read or write operation.

Figure 2-25. Bus Release Timings Case 2 (BRT Bit in Operating Mode Register Set)

2-29

AC Electrical Characteristics

2.6.5.5 Asynchronous Bus Arbitration Timings

Table 2-15. Asynchronous Bus Timings^{1, 2}

100 MHz⁴

No.

Characteristics

Expression³

Unit

Min Max

5

250 BB assertion window from BG input deassertion

2.5 × Tc + 5

2 × Tc + 5

—

30

—

ns

5

251 Delay from BB assertion to BG assertion

25

Notes: 1. Bit 13 in the Operating Mode Register must be set to enter Asynchronous Arbitration mode.

2. If Asynchronous Arbitration mode is active, none of the timings in Table 2-14 is required.

3. An expression is used to compute the maximum or minimum value listed, as appropriate.

4. Asynchronous Arbitration mode is recommended for operation at 100 MHz.

5. In order to guarantee timings 250, and 251, BG inputs must be asserted to different DSP56300

devices on the same bus in the non-overlap manner shown in Figure 2-26.

BG1

BB

250

BG2

251

250+251

Figure 2-26. Asynchronous Bus Arbitration Timing

The asynchronous bus arbitration is enabled by internal synchronization circuits on BG and BB inputs.

These synchronization circuits add delay from the external signal until it is exposed to internal logic. As a

result of this delay, a DSP56300 part may assume mastership and assert BB, for some time after BG is

deasserted. This is the reason for timing 250.

Once BB is asserted, there is a synchronization delay from BB assertion to the time this assertion is

exposed to other DSP56300 components that are potential masters on the same bus. If BG input is

asserted before that time, and BG is asserted and BB is deasserted, another DSP56300 component may

assume mastership at the same time. Therefore, some non-overlap period between one BG input active to

another BG input active is required. Timing 251 ensures that overlaps are avoided.

2-30

AC Electrical Characteristics

2.6.6 Host Interface Timing

Table 2-16. Host Interface Timings^1,2,12

100 MHz

No.

Characteristic¹⁰

Expression

Unit

Min Max

5

317 Read data strobe assertion width

HACK assertion width

T

+ 9.9

19.9

—

ns

C

5

318 Read data strobe deassertion width

HACK deassertion width

9.9

5

319 Read data strobe deassertion width after “Last Data Register”

2.5 × T + 6.6

31.6

C

8,11

3

reads

, or between two consecutive CVR, ICR, or ISR reads

HACK deassertion width after “Last Data Register” reads

8,11

6

320 Write data strobe assertion width

—

ns

13.2

8

321 Write data strobe deassertion width

HACK write deassertion width

•

after ICR, CVR and “Last Data Register” writes

2.5 × T + 6.6

31.8

16.5

—

ns

C

after IVR writes, or

after TXH:TXM:TXL writes (with HLEND= 0), or

after TXL:TXM:TXH writes (with HLEND = 1)

322 HAS assertion width

9.9

0.0

9.9

3.3

—

ns

4

323 HAS deassertion to data strobe assertion

6

324 Host data input setup time before write data strobe deassertion

6

325 Host data input hold time after write data strobe deassertion

326 Read data strobe assertion to output data active from high

5

impedance

HACK assertion to output data active from high impedance

5

327 Read data strobe assertion to output data valid

—

24.5

9.9

—

ns

HACK assertion to output data valid

5

328 Read data strobe deassertion to output data high impedance

HACK deassertion to output data high impedance

5

329 Output data hold time after read data strobe deassertion

3.3

Output data hold time after HACK deassertion

5

330 HCS assertion to read data strobe deassertion

T

+ 9.9

19.9

9.9

—

ns

C

6

331 HCS assertion to write data strobe deassertion

332 HCS assertion to output data valid

19.3

—

4

333 HCS hold time after data strobe deassertion

0.0

4.6

334 Address (HAD[0–7]) setup time before HAS deassertion

(HMUX=1)

—

335 Address (HAD[0–7]) hold time after HAS deassertion (HMUX=1)

3.3

—

ns

336 HA[8–10] (HMUX=1), HA[0–2] (HMUX=0), HR/W setup time

4

before data strobe assertion

•

Read

Write

0

4.6

—

ns

337 HA[8–10] (HMUX=1), HA[0–2] (HMUX=0), HR/W hold time after

3.3

—

ns

4

data strobe deassertion

2-31

AC Electrical Characteristics

Table 2-16. Host Interface Timings^1,2,12(Continued)

Characteristic¹⁰

100 MHz

No.

Expression

Unit

Min Max

338 Delay from read data strobe deassertion to host request assertion

T

+ 5.3

15.3

20.3

—

ns

C

5, 7, 8

for “Last Data Register” read

339 Delay from write data strobe deassertion to host request assertion

1.5 × T + 5.3

C

—

6, 7, 8

for “Last Data Register” write

340 Delay from data strobe assertion to host request deassertion for

19.3

300.0

4, 7, 8

“Last Data Register” read or write (HROD=0)

341 Delay from data strobe assertion to host request deassertion for

“Last Data Register” read or write (HROD=1, open drain host

—

4, 7, 8, 9

request)

Notes: 1. See the Programmer’s Model section in the chapter on the HI08 in the DSP56309User’s Manual.

2. In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is

programmable.

3. This timing is applicable only if two consecutive reads from one of these registers are executed.

4. The data strobe is Host Read (HRD) or Host Write (HWR) in the Dual Data Strobe mode and Host

Data Strobe (HDS) in the Single Data Strobe mode.

5. The read data strobe is HRD in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.

6. The write data strobe is HWR in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.

7. The host request is HREQ in the Single Host Request mode and HRRQ and HTRQ in the Double Host

Request mode.

8. The “Last Data Register” is the register at address $7, which is the last location to be read or written in

data transfers. This is RXL/TXL in the Big Endian mode (HLEND = 0; HLEND is the Interface Control

Register bit 7—ICR[7]), or RXH/TXH in the Little Endian mode (HLEND = 1).

9. In this calculation, the host request signal is pulled up by a 4.7 kΩ resistor in the Open-drain mode.

10.

V

= 3.3 V ± 0.3 V; T = –40°C to +100 °C, C = 50 pF

CC J L

11. This timing is applicable only if a read from the “Last Data Register” is followed by a read from the

RXL, RXM, or RXH registers without first polling RXDF or HREQ bits, or waiting for the assertion of the

HREQ signal.

12. After the external host writes a new value to the ICR, the HI08 is ready for operation after three DSP

clock cycles (3 × Tc).

317

318

HACK

328

327

329

326

H[0–7]

HREQ

Note: The IVR is only read by an MC680xx host processor using non-multiplexed mode.

Figure 2-27. Host Interrupt Vector Register (IVR) Read Timing Diagram

2-32

AC Electrical Characteristics

HA[2–0]

336

337

333

337

330

HCS

HRW

HDS

336

317

318

328

332

327

319

329

326

341

H[7–0]

338

340

HREQ (single host request)

HRRQ (double host request)

Figure 2-28. Read Timing Diagram, Non-Multiplexed Bus, Single Data Strobe

HA[2–0]

336

337

333

330

HCS

317

HRD

318

328

332

327

319

329

326

341

H[7–0]

338

340

HREQ (single host request)

HRRQ (double host request)

Figure 2-29. Read Timing Diagram, Non-Multiplexed Bus, Double Data Strobe

2-33

AC Electrical Characteristics

HA[2–0]

336

337

333

337

331

HCS

HRW

HDS

336

320

321

324

325

H[7–0]

339

340

341

HREQ (single host request)

HTRQ (double host request)

Figure 2-30. Write Timing Diagram, Non-Multiplexed Bus, Single Data Strobe

HA[2–0]

336

337

333

331

HCS

320

HWR

321

324

325

H[7–0]

339

340

341

HREQ (single host request)

HTRQ (double host request)

Figure 2-31. Write Timing Diagram, Non-Multiplexed Bus, Double Data Strobe

2-34

AC Electrical Characteristics

,

HA[10–8]

336

337

322

HAS

323

336

337

HRW

317

HDS

334

318

319

335

327

328

329

HAD[7–0]

Address

Data

326

338

340

341

HREQ (single host request)

HRRQ (double host request)

Figure 2-32. Read Timing Diagram, Multiplexed Bus, Single Data Strobe

HA[10–8]

336

337

322

HAS

323

317

HRD

334

318

319

335

327

328

329

HAD[7–0]

Address

Data

326

338

340

341

HREQ (single host request)

HRRQ (double host request)

Figure 2-33. Read Timing Diagram, Multiplexed Bus, Double Data Strobe

2-35

AC Electrical Characteristics

HA[10–8]

336

337

322

HAS

HRW

HDS

323

336

320

334

324

321

325

335

HAD[7–0]

Data

340

Address

339

341

HREQ (single host request)

HTRQ (double host request)

Figure 2-34. Write Timing Diagram, Multiplexed Bus, Single Data Strobe

,

HA[10–8]

336

337

322

HAS

323

320

HWR

334

324

321

325

335

HAD[7–0]

Data

340

Address

339

341

HREQ (single host request)

HTRQ (double host request)

Figure 2-35. Write Timing Diagram, Multiplexed Bus, Double Data Strobe

2-36

AC Electrical Characteristics

2.6.7 SCI Timing

Table 2-17. SCI Timings

100 MHz

No.

Characteristics¹

Symbol

Expression

Unit

Min

Max

2

400 Synchronous clock cycle

t

8 × T

53.3

16.7

8.0

—

ns

SCC

C

401 Clock low period

402 Clock high period

t

/2 − 10.0

SCC

403 Output data setup to clock falling edge

(internal clock)

t

/4 + 0.5 × T −17.0

SCC C

404 Output data hold after clock rising edge

(internal clock)

t

/4 − 0.5 × T

15.0

50.0

—

ns

SCC

C

405 Input data setup time before clock rising

edge (internal clock)

t

/4 + 0.5 × T + 25.0

SCC C

406 Input data not valid before clock rising

edge (internal clock)

t

/4 + 0.5 × T − 5.5

19.5

32.0

—

SCC

C

407 Clock falling edge to output data valid

(external clock)

—

408 Output data hold after clock rising edge

(external clock)

T

+ 8.0

18.0

0.0

9.0

C

409 Input data setup time before clock rising

edge (external clock)

—

410 Input data hold time after clock rising edge

(external clock)

—

3

411 Asynchronous clock cycle

412 Clock low period

t

64 × T

640.0

310.0

290.0

—

ns

ACC

C

t

/2 − 10.0

/2 − 30.0

ACC

413 Clock high period

414 Output data setup to clock rising edge

(internal clock)

415 Output data hold after clock rising edge

(internal clock)

t

/2 − 30.0

290.0

—

ns

ACC

Notes: 1.

2.

V

= 3.3 V ± 0.3 V; T = −40°C to +100 °C, C = 50 pF.

CC J L

t

= synchronous clock cycle time (For internal clock, t

is determined by the SCI clock control

SCC

register and T ).

C

3.

t

= asynchronous clock cycle time; value given for 1X Clock mode (for internal clock, t

is

ACC

determined by the SCI clock control register and T ).

C

4. An expression is used to compute the number listed as the minimum or maximum value as

appropriate.

2-37

AC Electrical Characteristics

400

402

404

401

SCLK

(Output)

403

Data Valid

405

TXD

RXD

406

Data

Valid

a) Internal Clock

400

402

401

SCLK

(Input)

407

408

TXD

RXD

Data Valid

409

410

Data Valid

b) External Clock

Figure 2-36. SCI Synchronous Mode Timing

411

413

415

412

414

1X SCLK

(Output)

TXD

Data Valid

Figure 2-37. SCI Asynchronous Mode Timing

2-38

AC Electrical Characteristics

2.6.8 ESSI0/ESSI1 Timing

Table 2-18. ESSI Timings

100 MHz

Cond-

No.

Characteristics^{4, 5, 7}Symbol Expression⁹

Unit

ition⁵

Min Max

1

430 Clock cycle

t

3 × T

4 × T

30.0

40.0

—

x ck

i ck

ns

SSICC

C

431 Clock high period

•

For internal clock

For external clock

2 × T - 10.0 10.0

—

ns

C

1.5 × T

15.0

C

432 Clock low period

•

For internal clock

For external clock

2 × T − 10.0 10.0

—

ns

C

1.5 × T

15.0

C

433 RXC rising edge to FSR out (bit-length) high

434 RXC rising edge to FSR out (bit-length) low

435 RXC rising edge to FSR out (word-length-relative)

—

37.0

22.0

x ck

i ck a

ns

—

37.0

22.0

x ck

i ck a

—

39.0

37.0

x ck

i ck a

2

high

436 RXC rising edge to FSR out (word-length-relative)

—

39.0

37.0

x ck

i ck a

2

low

437 RXC rising edge to FSR out (word-length) high

438 RXC rising edge to FSR out (word-length) low

—

36.0

21.0

x ck

i ck a

—

37.0

22.0

x ck

i ck a

439 Data in setup time before RXC (SCK in

Synchronous mode) falling edge

10.0

19.0

—

x ck

i ck

440 Data in hold time after RXC falling edge

5.0

3.0

—

x ck

i ck

2

441 FSR input (bl, wr) high before RXC falling edge

1.0

23.0

—

x ck

i ck a

442 FSR input (wl) high before RXC falling edge

443 FSR input hold time after RXC falling edge

444 Flags input setup before RXC falling edge

445 Flags input hold time after RXC falling edge

446 TXC rising edge to FST out (bit-length) high

447 TXC rising edge to FST out (bit-length) low

448 TXC rising edge to FST out (word-length-relative)

3.5

23.0

—

x ck

i ck a

3.0

0.0

—

x ck

i ck a

5.5

19.0

—

x ck

i ck s

6.0

0.0

—

x ck

i ck s

—

29.0

15.0

x ck

i ck

—

31.0

17.0

x ck

i ck

—

31.0

17.0

x ck

i ck

2

high

449 TXC rising edge to FST out (word-length-relative)

—

33.0

19.0

x ck

i ck

2

low

2-39

AC Electrical Characteristics

Table 2-18. ESSI Timings (Continued)

Characteristics^{4, 5, 7}Symbol Expression⁹

100 MHz

Cond-

ition⁵

No.

Unit

Min Max

450 TXC rising edge to FST out (word-length) high

—

30.0

16.0

x ck

i ck

ns

451 TXC rising edge to FST out (word-length) low

—

31.0

17.0

x ck

i ck

452 TXC rising edge to data out enable from high

impedance

—

31.0

17.0

x ck

i ck

453 TXC rising edge to Transmitter #0 drive enable

assertion

—

34.0

20.0

x ck

i ck

8

454 TXC rising edge to data out valid

—

20.0

10.0

x ck

i ck

3

455 TXC rising edge to data out high impedance

—

31.0

16.0

x ck

i ck

456 TXC rising edge to Transmitter #0 drive enable

—

34.0

20.0

x ck

i ck

3

deassertion

457 FST input (bl, wr) setup time before TXC falling

2.0

21.0

—

x ck

i ck

2

edge

458 FST input (wl) to data out enable from high

impedance

—

27.0

—

459 FST input (wl) to Transmitter #0 drive enable

assertion

—

31.0

—

460 FST input (wl) setup time before TXC falling edge

461 FST input hold time after TXC falling edge

462 Flag output valid after TXC rising edge

2.5

21.0

—

x ck

i ck

4.0

0.0

—

x ck

i ck

—

32.0

18.0

x ck

i ck

Notes: 1. For the internal clock, the external clock cycle is defined by Icyc (see Timing 7) and the ESSI control

register.

2. The word-length-relative frame sync signal waveform operates the same way as the bit-length frame

sync signal waveform, but spreads from one serial clock before the first bit clock (same as the Bit

Length Frame Sync signal) until the one before last bit clock of the first word in the frame.

3. Periodically sampled and not 100 percent tested

4.

V

= 3.3 V ± 0.3 V; T = −40°C to +100 °C, C = 50 pF

CC J L

5. TXC (SCK Pin) = Transmit Clock

RXC (SC0 or SCK Pin) = Receive Clock

FST (SC2 Pin) = Transmit Frame Sync

FSR (SC1 or SC2 Pin) Receive Frame Sync

6. i ck = Internal Clock

x ck = External Clock

i ck a = Internal Clock, Asynchronous Mode

(asynchronous implies that TXC and RXC are two different clocks)

i ck s = Internal Clock, Synchronous Mode

(synchronous implies that TXC and RXC are the same clock)

7. bl = bit length; wl = word length; wr = word length relative

8. If the DSP core writes to the transmit register during the last cycle before causing an underrun error,

the delay is 20 ns + (0.5 × T ).

C

9. An expression is used to compute the number listed as the minimum or maximum value as

appropriate.

2-40

AC Electrical Characteristics

430

431

432

TXC

(Input/

Output)

446

447

FST (Bit)

Out

450

451

FST (Word)

Out

454

452

454

455

Data Out

First

Last

459

Transmitter

#0 Drive

Enable

457

453

456

461

460

FST (Bit) In

458

461

FST (Word)

In

462

See Note

Flags Out

Note:

In Network mode, output flag transitions can occur at the start of each time slot within the

frame. In Normal mode, the output flag state is asserted for the entire frame period.

Figure 2-38. ESSI Transmitter Timing

2-41

AC Electrical Characteristics

430

431

432

RXC

(Input/

Output)

433

434

FSR (Bit)

Out

437

438

FSR

(Word)

Out

440

439

443

Data In

Last Bit

First Bit

441

FSR (Bit)

In

443

445

442

FSR

(Word)

In

444

Flags In

Figure 2-39. ESSI Receiver Timing

2-42

AC Electrical Characteristics

2.6.9 Timer Timing

Table 2-19. Timer Timing¹

100 MHz

Unit

No.

Characteristics

Expression²

Min

Max

480

481

482

2 × T + 2.0

22.0

9.0

—

ns

TIO Low

C

TIO High

2 × T + 2.0

C

Timer set-up time from TIO (Input) assertion

to CLKOUT rising edge

10.0

483

484

485

Synchronous timer delay time from CLKOUT

rising edge to the external memory access

address out valid caused by first interrupt

instruction execution

10.25 × T + 1.0

103.5

—

ns

C

CLKOUT rising edge to TIO (Output)

assertion

0.5 × T + 0.5

5.5

—

24.8

ns

C

•

Minimum

Maximum

0.5 × T + 19.8

C

CLKOUT rising edge to TIO (Output)

deassertion

0.5 × T + 0.5

5.5

—

24.8

ns

C

•

Minimum

Maximum

0.5 × T + 19.8

C

Notes: 1.

V

= 3.3 V ± 0.3 V; T = −40°C to +100 °C, C = 50 pF

CC J L

2. An expression is used to compute the number listed as the minimum or maximum value as

appropriate.

480

TIO

481

Figure 2-40. TIO Timer Event Input Restrictions

CLKOUT

TIO (Input)

482

Address

483

First Interrupt Instruction Execution

Figure 2-41. Timer Interrupt Generation

CLKOUT

TIO (Output)

484

485

Figure 2-42. External Pulse Generation

2-43

AC Electrical Characteristics

2.6.10 GPIO Timing

Table 2-20. GPIO Timing

100 MHz

No.

Characteristics

Expression

Unit

Min

Max

490

—

0.0

8.5

0.0

67.5

8.5

—

ns

CLKOUT edge to GPIO out valid (GPIO out delay time)

491 CLKOUT edge to GPIO out not valid (GPIO out hold time)

492 GPIO In valid to CLKOUT edge (GPIO in set-up time)

493 CLKOUT edge to GPIO in not valid (GPIO in hold time)

494 Fetch to CLKOUT edge before GPIO change

Minimum: 6.75 × T

C

Note:

V

= 3.3 V ± 0.3 V; T = −40°C to +100 °C, C = 50 pF

CC

J

L

CLKOUT

(Output)

490

491

GPIO

(Output)

492

493

GPIO

(Input)

Valid

A[0–17]

494

Fetch the instruction MOVE X0,X:(R0); X0 contains the new value of GPIO

and R0 contains the address of the GPIO data register.

Figure 2-43. GPIO Timing

2-44

AC Electrical Characteristics

2.6.11 JTAG Timing

Table 2-21. JTAG Timing

All frequencies

Unit

No.

Characteristics

Min

Max

500

501

502

503

504

505

506

507

508

509

510

511

512

513

TCK frequency of operation

TCK cycle time in Crystal mode

0.0

45.0

20.0

0.0

22.0

—

MHz

ns

TCK clock pulse width measured at 1.5 V

TCK rise and fall times

—

3.0

—

Boundary scan input data setup time

Boundary scan input data hold time

TCK low to output data valid

TCK low to output high impedance

TMS, TDI data setup time

5.0

24.0

0.0

—

40.0

—

0.0

5.0

TMS, TDI data hold time

25.0

0.0

—

TCK low to TDO data valid

44.0

—

TCK low to TDO high impedance

TRST assert time

0.0

100.0

40.0

TRST setup time to TCK low

—

Notes: 1.

V

= 3.3 V ± 0.3 V; T = –40°C to +100 °C, C = 50 pF

CC J L

2. All timings apply to OnCE module data transfers because it uses the JTAG port as an interface.

501

502

V

TCK

(Input)

IH

V

M

V

IL

503

Figure 2-44. Test Clock Input Timing Diagram

2-45

AC Electrical Characteristics

V

TCK

(Input)

IH

V

IL

504

505

Data

Inputs

Input Data Valid

506

507

506

Data

Outputs

Output Data Valid

Data

Outputs

Data

Outputs

Output Data Valid

Figure 2-45. Boundary Scan (JTAG) Timing Diagram

V

IH

TCK

(Input)

V

IL

509

508

Input Data Valid

TDI

TMS

(Input)

510

TDO

(Output)

Output Data Valid

511

TDO

(Output)

510

TDO

(Output)

Output Data Valid

Figure 2-46. Test Access Port Timing Diagram

TCK

(Input)

513

TRST

(Input)

512

Figure 2-47. TRST Timing Diagram

2-46

AC Electrical Characteristics

2.6.12 OnCE Module TimIng

Table 2-22. OnCE Module Timing

Characteristics Expression

No.

Min

Max

Unit

500 TCK frequency of operation

Max 22.0 MHz

1.5 × T + 10.0

0.0

20.0

—

22.0

—

MHz

ns

514 DE assertion time in order to enter Debug mode

C

515 Response time when DSP56309 is executing NOP

instructions from internal memory

5.5 × T + 30.0

67.0

ns

C

516 Debug acknowledge assertion time

3 × T + 5.0

25.0

—

ns

C

Note:

V

= 3.3 V ± 0.3 V; T = –40°C to +100 °C, C = 50 pF

CC J L

DE

514

515

516

Figure 2-48. OnCE—Debug Request

2-47

AC Electrical Characteristics

2-48

Chapter 3

Packaging

3.1 Pin-Out and Packages

This section includes diagrams of the DSP56309 package pin-outs and tables showing how the

signals described in Chapter 1 are allocated for each package.

The DSP56309 is available in two package types:

• 144-pin Thin Quad Flat Pack (TQFP)

• 196-pin Molded Array Process-Ball Grid Array (MAP-BGA)

3-1

TQFP Package

3.2 TQFP Package

Top and bottom views of the TQFP package are shown in Figure 3-1 and Figure 3-2 with their pin-outs.

109

A0

BG

D7

D8

(Top View)

AA0

AA1

RD

V_CCD

GND_D

D9

WR

GND

D10

D11

D12

C

V

CCC

BB

BR

TA

BCLK

D13

D14

V_CCD

GND_D

D15

D16

CLKOUT

GND

D17

C

V

D18

CCC

V

D19

CCQL

EXTAL

V_CCQL

GND_Q

D20

V_CCD

GND_D

D21

GND

Q

XTAL

CAS

AA2

AA3

D22

V

CCQH

D23

GND

P1

P

MODD

MODC

MODB

MODA

TRST

TDO

TDI

TCK

TMS

SC12

SC11

PCAP

V

CCP

RESET

HAD0

HAD1

HAD2

HAD3

Orientation Mark

GND

H

V

CCH

HAD4

37

Notes: Because of size constraints in this figure, only one name is shown for multiplexed pins. Refer to Table 3-1 and Table

3-2 for detailed information about pin functions and signal names.

Figure 3-1. DSP56309 Thin Quad Flat Pack (TQFP), Top View

3-2

TQFP Package

A0

BG

109

D7

D8

(Bottom View)

V_CCD

GND_D

D9

AA0

AA1

RD

WR

GND_C

V_CCC

D10

D11

D12

D13

D14

V_CCD

GND_D

BB

BR

TA

BCLK

D15

D16

D17

D18

BCLK

CLKOUT

GND_C

V_CCC

D19

V_CCQL

GND_Q

EXTAL

GND_Q

D20

V_CCD

XTAL

CAS

GND_D

D21

D22

D23

MODD

MODC

MODB

MODA

TRST

TDO

TDI

TCK

TMS

SC12

SC11

AA2

AA3

V_CCQH

GND_P1

GND_P

PCAP

V_CCP

RESET

HAD0

HAD1

HAD2

HAD3

Orientation Mark

(on top side)

GND

H

V_CC

H

37

HAD4

Notes: Because of size constraints in this figure, only one name is shown for multiplexed pins. Refer to Table 3-1 and Table

3-2 for detailed information about pin functions and signal names.

Figure 3-2. DSP56309 Thin Quad Flat Pack (TQFP), Bottom View

3-3

TQFP Package

Table 3-1. DSP56309 TQFP Signal Identification by Pin Number

No.

Signal Name

1

2

3

4

5

6

7

8

9

SRD1 or PD4

26 GND

27 TIO2

28 TIO1

29 TIO0

51 AA2/RAS2

52 CAS

S

STD1 or PD5

SC02 or PC2

SC01 or PC1

DE

53 XTAL

54 GND

Q

30 HCS/HCS, HA10, or PB13

31 HA2, HA9, or PB10

32 HA1, HA8, or PB9

33 HA0, HAS/HAS, or PB8

34 H7, HAD7, or PB7

35 H6, HAD6, or PB6

36 H5, HAD5, or PB5

37 H4, HAD4, or PB4

55 EXTAL

PINIT/NMI

SRD0 or PC4

56

57

V

CCQL

CCC

V

58 GND

C

CCS

GND

59 CLKOUT

60 BCLK

61 BCLK

62 TA

S

10 STD0 or PC5

11 SC10 or PD0

12 SC00 or PC0

13 RXD or PE0

14 TXD or PE1

15 SCLK or PE2

16 SCK1 or PD3

17 SCK0 or PC3

38

V

63 BR

CCH

39 GND

64 BB

H

40 H3, HAD3, or PB3

41 H2, HAD2, or PB2

42 H1, HAD1, or PB1

43 H0, HAD0, or PB0

44 RESET

65

V

CCC

66 GND

67 WR

68 RD

C

18

V

CCQL

19 GND

69 AA1/RAS1

70 AA0/RAS0

71 BG

Q

20

V

45

V

CCP

CCQH

21 HDS/HDS, HWR/HWR, or

PB12

46 PCAP

22 HRW, HRD/HRD, or PB11

47 GND

48 GND

72 A0

73 A1

P

23 HACK/HACK,

P1

HRRQ/HRRQ, or PB15

24 HREQ/HREQ,

49

V

74

V

CCA

CCQH

HTRQ/HTRQ, or PB14

25

V

50 AA3/RAS3

75 GND

A

CCS

3-4

TQFP Package

Table 3-1. DSP56309 TQFP Signal Identification by Pin Number (Continued)

No.

Signal Name

76 A2

77 A3

78 A4

79 A5

99 A17

100 D0

101 D1

102 D2

122 D16

123 D17

124 D18

125 D19

80

V

103

V

126

V

CCQL

CCA

CCD

81 GND

82 A6

83 A7

84 A8

85 A9

104 GND

105 D3

106 D4

107 D5

108 D6

109 D7

110 D8

127 GND

128 D20

A

D

Q

129

V

CCD

130 GND

131 D21

132 D22

133 D23

D

86

V

CCA

87 GND

88 A10

89 A11

90 GND

A

111

V

134 MODD/IRQD

135 MODC/IRQC

136 MODB/IRQB

137 MODA/IRQA

138 TRST

CCD

112 GND

113 D9

Q

91

V

114 D10

115 D11

116 D12

117 D13

118 D14

CCQL

92 A12

93 A13

94 A14

139 TDO

140 TDI

95

V

141 TCK

CCQH

96 GND

97 A15

98 A16

119

V

142 TMS

A

CCD

120 GND

121 D15

143 SC12 or PD2

144 SC11 or PD1

Notes: Signal names are based on configured functionality. Most pins supply a single signal. Some pins provide a

signal with dual functionality, such as the MODx/IRQx pins that select an operating mode after RESET is

deasserted but act as interrupt lines during operation. Some signals have configurable polarity; these

names are shown with and without overbars, such as HAS/HAS. Some pins have two or more configurable

functions; names assigned to these pins indicate the function for a specific configuration. For example, Pin

34 is data line H7 in non-multiplexed bus mode, data/address line HAD7 in multiplexed bus mode, or GPIO

line PB7 when the GPIO function is enabled for this pin.

3-5

TQFP Package

Table 3-2. DSP56309 TQFP Signal Identification by Name

No.

Signal Name

A0

A1

72

73

88

89

92

93

94

97

98

99

76

77

78

79

82

83

84

85

70

69

51

50

64

60

61

BG

BR

71

D7

D8

109

110

113

5

63

A10

A11

A12

A13

A14

A15

A16

A17

A2

CAS

CLKOUT

D0

52

D9

59

DE

100

101

114

115

116

117

118

121

122

123

124

125

102

128

131

132

133

105

106

107

108

EXTAL

55

D1

GND

75

A

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D2

81

87

A

96

A

58

C

D

H

P

66

A3

104

112

120

130

39

A4

A5

A6

A7

A8

47

A9

D20

D21

D22

D23

D3

GND

48

P1

AA0

AA1

AA2

AA3

BB

GND

19

Q

54

90

127

9

D4

GND

H0

S

BCLK

D5

26

D6

43

3-6

TQFP Package

Table 3-2. DSP56309 TQFP Signal Identification by Name (Continued)

No.

Signal Name

H1

H2

42

41

40

37

36

35

34

33

32

30

31

32

31

23

43

42

41

40

37

36

35

34

33

30

21

HRD/HRD

HREQ/HREQ

HRRQ/HRRQ

HRW

22

24

PB4

PB5

PB6

PB7

PB8

PB9

PC0

PC1

PC2

PC3

PC4

PC5

PCAP

PD0

PD1

PD2

PD3

PD4

PD5

PE0

PE1

PE2

PINIT

RAS0

RAS1

37

36

35

34

33

32

12

4

H3

23

H4

22

H5

HTRQ/HTRQ

HWR/HWR

IRQA

24

H6

21

H7

137

136

135

134

137

136

135

134

6

HA0

IRQB

HA1

IRQC

3

HA10

HA2

IRQD

17

7

MODA

MODB

MODC

MODD

NMI

HA8

10

46

11

144

143

16

1

HA9

HACK/HACK

HAD0

HAD1

HAD2

HAD3

HAD4

HAD5

HAD6

HAD7

HAS/HAS

HCS/HCS

HDS/HDS

PB0

43

PB1

42

PB10

31

PB11

22

2

PB12

21

13

14

15

6

PB13

30

PB14

24

PB15

23

PB2

41

70

69

PB3

40

3-7

TQFP Package

Table 3-2. DSP56309 TQFP Signal Identification by Name (Continued)

No.

Signal Name

RAS2

RAS3

RD

51

50

68

44

13

12

4

STD1

TA

2

V

111

119

129

38

45

20

49

95

18

56

91

126

8

CCD

CCH

CCP

62

TCK

TDI

141

140

139

29

RESET

RXD

TDO

TIO0

TIO1

TIO2

TMS

TRST

TXD

SC00

SC01

SC02

SC10

SC11

SC12

SCK0

SCK1

SCLK

SRD0

SRD1

STD0

V

CCQH

28

3

27

11

144

143

17

16

15

7

142

138

14

V

CCQL

V

74

CCA

CCC

CCD

80

V

CCS

86

V

25

67

53

57

WR

1

65

XTAL

10

103

3-8

TQFP Package Mechanical Drawing

3.3 TQFP Package Mechanical Drawing

0.20 T L-M N

4X

4X 36 TIPS

Pin 1

ident

144

109

1

108

4X

P

J1

M

L

C

L

V

B

X

X=L, M or N

140X

G

B1

V1

View Y

36

73

Notes:

1. Dimensions and tolerancing per ASME

Y14.5, 1994.

2. Dimensions in millimeters.

3. Datums L, M and N to be determined at the

seating plane, datum T.

37

72

N

4. Dimensions S and V to be determined at

the seating plane, datum T.

A1

S1

5. Dimensions A and B do not include mold

protrusion. Allowable protrusionis0.25per

side. Dimensions A and B do include mold

mismatch and are determined at datum

plane H.

A

S

6. Dimension D does not include dambar

protrusion. Allowable dambar protrusion

shall not cause the D dimension to exceed

0.35.

View AB

C

144X

0.1 T

θ2

Millimeters

MIN

MAX

DIM

A

A1

B

B1

C

Seating

plane

20.00 BSC

10.00 BSC

20.00 BSC

10.00 BSC

T

1.40

C1 0.05

C2 1.35

1.60

0.15

1.45

0.27

0.75

0.23

Plating

D

E

F

G

J

0.17

0.45

0.17

J

C2

AA

F

— 0.05

0.50 BSC

R2

0.09

0.20

θ

K

P

0.50 REF

0.25 BSC

R1

R1 0.13

R2 0.13

0.20

S

S1

V

V1

Y

22.00 BSC

11.00 BSC

22.00 BSC

11.00 BSC

0.25 REF

1.00 REF

Base

metal

0.25

Gage plane

D

M

0.08

T L-M N

Z

Section J1-J1

(rotated 90)

144 PL

(K)

E

AA 0.09

θ

θ1

θ2

0.16

C1

0°

7°

θ 1

(Y)

View AB

11°

13°

(Z)

CASE 918-03

ISSUE C

Figure 3-3. DSP56309 Mechanical Information, 144-pin TQFP Package

3-9

MAP-BGA Package

3.4 MAP-BGA Package

Top and bottom views of the MAP-BGA package are shown in Figure 3-4 and Figure 3-5 with their

pin-outs.

Top View

1

2

3

4

5

6

7

8

9

10

11

12

13

14

A

B

NC

SC11

TMS

TDO MODB

TRST MODD

D23

V

D19

D16

D14

D11

D9

D7

NC

CCD

SRD1 SC12

SC02 STD1

PINIT SC01

TDI

D21

D22

D20

D17

D18

D15

D13

D12

D10

D8

D6

D5

D3

NC

D4

TCK MODA MODC

V

CCD

C

CCQL

CCD

DE

GND

PB0

GND

EXTAL

CAS

GND

BCLK

TA

GND

D1

D2

V

CCD

D

E

F

STD0

RXD

V

SRD0 GND

GND

WR

A17

A16

A14

D0

CCS

SC10 SC00

GND

V

A15

A12

A11

A9

CCQH

G

SCK1 SCLK

TXD

A13

V

CCQL

V

SCK0 GND

V

A10

H

J

CCQH

CCQL

CCA

HACK HRW

HDS

GND

A8

A7

A5

K

V

HREQ TIO2

V

A6

CCS

CCA

HCS

HA1

H6

TIO1

HA2

H7

TIO0

HA0

H4

V

A3

A4

L

CCA

CLK

OUT

M

V

RD

A1

A2

CCH

CCP

CCQH

N

P

H2

H1

RESET GND

AA3

V

BR

V

AA0

BG

A0

P

CCQL

CCC

NC

H5

H3

PCAP GND

AA2

XTAL

V

BB

AA1

NC

P1

CCC

Figure 3-4. DSP56309 Molded Array Process-Ball Grid Array (MAP-BGA), Top View

3-10

MAP-BGA Package

Bottom View

14

13

12

11

10

9

8

7

6

5

4

3

2

1

A

B

NC

D7

D9

D11

D14

D16

D19

V

D23

MODB TDO

MODD TRST

TMS

SC11

NC

CCD

NC

D4

D5

D3

D8

D6

D10

D13

D12

D15

D17

D18

D20

D21

D22

TDI

SC12 SRD1

STD1 SC02

SC01 PINIT

V

MODC MODA TCK

C

CCD

CCQL

V

D2

D1

GND

BCLK

TA

GND

EXTAL

CAS

GND

PB0

GND

DE

D

E

F

CCD

D0

A16

A14

A17

GND

WR

GND

GND SRD0

V

STD0

RXD

CCS

A15

A12

A11

A9

V

GND

SC00 SC10

CCQH

G

V

A13

TXD

SCLK SCK1

CCQL

A10

V

GND SCK0

V

CCQH

H

J

CCA

CCQL

A7

A5

A8

GND

HDS

HRW HACK

K

A6

V

TIO2 HREQ

V

CCS

CCA

A4

A3

V

TIO0

HA0

H4

TIO1

HA2

H7

HCS

HA1

H6

L

CCA

CLK

OUT

M

A2

A1

RD

V

CCH

CCQH

CCP

N

P

A0

AA0

BG

V

BR

V

AA3

GND

RESET

PCAP

H2

H1

CCC

CCQL

P

NC

AA1

BB

V

XTAL

AA2 GND

H3

H5

NC

CCC

P1

Figure 3-5. DSP56309 Molded Array Process-Ball Grid Array (MAP-BGA), Bottom View

3-11

MAP-BGA Package

Table 3-3. DSP56309 MAP-BGA Signal Identification by Pin Number

No.

Signal Name

A1 Not Connected (NC), reserved B12

D8

D5

D9

D10

D11

D12

D13

D14

E1

GND

D1

A2

A3

SC11 or PD1

TMS

B13

B14

C1

NC

A4

TDO

SC02 or PC2

STD1 or PD5

TCK

A5

MODB/IRQB

D23

C2

D2

A6

C3

V

CCD

A7

V

C4

MODA/IRQA

MODC/IRQC

D22

STD0 or PC5

CCD

A8

D19

D16

C5

E2

V

CCS

A9

C6

E3

SRD0 or PC4

GND

A10

A11

A12

A13

A14

B1

D14

C7

V

E4

CCQL

D11

C8

D18

E5

GND

D9

C9

V

E6

GND

CCD

D7

C10

C11

C12

C13

C14

D1

D12

E7

GND

NC

V

E8

GND

CCD

SRD1 or PD4

SC12 or PD2

TDI

D6

E9

GND

B2

D3

D4

E10

E11

E12

E13

E14

F1

GND

B3

GND

B4

TRST

MODD/IRQD

D21

PINIT/NMI

SC01 or PC1

DE

A17

B5

D2

A16

B6

D3

D0

B7

D20

D4

GND

RXD or PE0

SC10 or PD0

SC00 or PC0

GND

B8

D17

D5

GND

F2

B9

D15

D6

GND

F3

B10

B11

D13

D7

GND

F4

D10

D8

GND

F5

GND

3-12

MAP-BGA Package

Table 3-3. DSP56309 MAP-BGA Signal Identification by Pin Number (Continued)

No.

Signal Name

F6

F7

F8

GND

H3

H4

H5

SCK0 or PC3

GND

J14

K1

A9

V

CCS

GND

K2

HREQ/HREQ,

HTRQ/HTRQ, or PB14

F9

F10

F11

F12

F13

F14

G1

GND

H6

H7

GND

K3

K4

TIO2

GND

H8

K5

V

H9

K6

CCQH

A14

A15

H10

H11

H12

H13

H14

J1

K7

K8

SCK1 or PD3

SCLK or PE2

TXD or PE1

GND

V

K9

CCA

G2

A10

A11

K10

K11

K12

G3

G4

HACK/HACK,

V

CCA

HRRQ/HRRQ, or PB15

G5

G6

GND

J2

J3

HRW, HRD/HRD, or PB11

K13

K14

A5

A6

HDS/HDS, HWR/HWR, or

PB12

G7

G8

GND

A13

J4

J5

GND

L1

L2

L3

L4

L5

L6

L7

L8

L9

L10

P1

P2

P3

HCS/HCS, HA10, or PB13

GND

TIO1

G9

J6

GND

TIO0

G10

G11

G12

G13

G14

H1

J7

GND

J8

GND

J9

GND

V

J10

J11

J12

J13

M13

M14

N1

GND

CCQL

A12

GND

V

A8

GND

CCQH

H2

V

A7

GND

CCQL

L11

L12

L13

GND

A1

A2

NC

V

H5, HAD5, or PB5

H3, HAD3, or PB3

CCA

A3

H6, HAD6, or PB6

3-13

MAP-BGA Package

Table 3-3. DSP56309 MAP-BGA Signal Identification by Pin Number (Continued)

No.

Signal Name

L14

M1

A4

N2

N3

H7, HAD7, or PB7

H4, HAD4, or PB4

H2, HAD2, or PB2

RESET

P4

P5

H1, HAD1, or PB1

PCAP

HA1, HA8, or PB9

HA2, HA9, or PB10

HA0, HAS/HAS, or PB8

M2

N4

P6

GND

P1

M3

N5

P7

AA2/RAS2

XTAL

M4

V

N6

GND

P8

CCH

P

M5

H0, HAD0, or PB0

N7

AA3/RAS3

CAS

P9

V

CCC

M6

V

N8

P10

P11

P12

P13

P14

TA

BB

CCP

M7

V

N9

V

CCQL

CCQH

M8

EXTAL

CLKOUT

BCLK

WR

N10

N11

N12

N13

N14

BCLK

BR

AA1/RAS1

BG

M9

M10

M11

M12

V

NC

CCC

AA0/RAS0

A0

RD

Notes: Signal names are based on configured functionality. Most connections supply a single signal.

Some connections provide a signal with dual functionality, such as the MODx/IRQx pins that

select an operating mode after RESET is deasserted but act as interrupt lines during operation.

Some signals have configurable polarity; these names are shown with and without overbars,

such as HAS/HAS. Some connections have two or more configurable functions; names

assigned to these connections indicate the function for a specific configuration. For example,

connection N2 is data line H7 in non-multiplexed bus mode, data/address line HAD7 in

multiplexed bus mode, or GPIO line PB7 when the GPIO function is enabled for this pin. Unlike

in the TQFP package, most of the GND pins are connected internally in the center of the

connection array and act as heat sink for the chip. Therefore, except for GND_Pand GND_P1that

support the PLL, other GND signals do not support individual subsystems in the chip.

3-14

MAP-BGA Package

Table 3-4. DSP56309 MAP-BGA Signal Identification by Name

No.

Signal Name

A0

A1

N14

M13

H13

H14

G14

G12

F13

F14

E13

E12

M14

L13

L14

K13

K14

J13

J12

J14

N13

P12

P7

BG

BR

P13

N11

N8

D7

D8

A13

B12

A12

D3

M8

D4

D5

D6

D7

D8

D9

D10

D11

E4

A10

A11

A12

A13

A14

A15

A16

A17

A2

CAS

CLKOUT

D0

D9

M9

DE

E14

D12

B11

A11

C10

B10

A10

B9

EXTAL

GND

D1

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D2

A3

A4

A9

A5

B8

A6

C8

E5

A7

A8

E6

A8

D13

B7

E7

A9

D20

D21

D22

D23

D3

E8

AA0

AA1

AA2

AA3

BB

B6

E9

C6

E10

E11

F4

A6

N7

C13

C14

B13

C12

P11

M10

N10

D4

F5

BCLK

D5

F6

D6

F7

3-15

MAP-BGA Package

Table 3-4. DSP56309 MAP-BGA Signal Identification by Name (Continued)

No.

Signal Name

GND

F8

F9

GND

J9

J10

J11

K4

K5

K6

K7

K8

K9

K10

K11

L4

H4

H5

N3

P2

N1

N2

M3

M1

L1

F10

F11

G4

G5

G6

G7

G8

G9

G10

G11

H4

H5

H6

H7

H8

H9

H10

H11

J4

H6

H7

HA0

HA1

HA10

HA2

M2

M1

M2

J1

HA8

HA9

HACK/HACK

HAD0

M5

P4

N4

P3

N3

P2

N1

N2

M3

L1

L5

HAD1

L6

HAD2

L7

HAD3

L8

HAD4

L9

HAD5

L10

L11

N6

P6

M5

P4

N4

P3

HAD6

HAD7

GND

HAS/HAS

HCS/HCS

HDS/HDS

HRD/HRD

HREQ/HREQ

HRRQ/HRRQ

P

GND

H0

P1

J5

J3

J6

H1

J2

J7

H2

K2

J1

J8

H3

3-16

MAP-BGA Package

Table 3-4. DSP56309 MAP-BGA Signal Identification by Name (Continued)

No.

Signal Name

HRW

HTRQ/HTRQ

HWR/HWR

IRQA

IRQB

IRQC

IRQD

MODA

MODB

MODC

MODD

NC

J2

K2

J3

PB2

PB3

PB4

PB5

PB6

PB7

PB8

PB9

PC0

PC1

PC2

PC3

PC4

PC5

PCAP

PD0

PD1

PD2

PD3

PD4

PD5

PE0

PE1

PE2

PINIT

N4

P3

N3

P2

N1

N2

M3

M1

F3

D2

C1

H3

E3

E1

P5

F2

A2

B2

G1

B1

C2

F1

G3

G2

D1

RAS0

RAS1

RAS2

RAS3

RD

N13

P12

P7

N7

M12

N5

F1

C4

A5

C5

B5

C4

A5

C5

B5

A1

A14

B14

P1

P14

D1

M5

P4

M2

J2

RESET

RXD

SC00

SC01

SC02

SC10

SC11

SC12

SCK0

SCK1

SCLK

SRD0

SRD1

STD0

STD1

TA

F3

D2

C1

F2

A2

B2

H3

G1

G2

E3

B1

E1

C2

P10

C3

B3

A4

L3

NC

NMI

PB0

PB1

PB10

PB11

PB12

PB13

PB14

PB15

J3

TCK

L1

TDI

K2

J1

TDO

TIO0

3-17

MAP-BGA Package

Table 3-4. DSP56309 MAP-BGA Signal Identification by Name (Continued)

No.

Signal Name

TIO1

TIO2

TMS

TRST

TXD

L2

K3

V

P9

A7

V

M7

C7

CCC

CCD

CCH

CCP

CCQH

V

CCQL

A3

C9

G13

H2

B4

C11

D14

M4

M6

F12

H1

G3

N9

V

H12

K12

L12

N12

V

E2

CCA

CCC

CCS

V

K1

V

WR

M11

P8

CCQH

V

XTAL

3-18

MAP-BGA Package Mechanical Drawing

3.5 MAP-BGA Package Mechanical Drawing

Figure 3-6. DSP56309 Mechanical Information, 196-pin MAP-BGA Package

3-19

MAP-BGA Package Mechanical Drawing

3-20

Chapter 4

Design

Considerations

4.1 Thermal Design Considerations

An estimate of the chip junction temperature, T_J, in °C can be obtained from

this equation:

Equation 1: T_J= T_A+ (P_D× R_θJA

)

Where:

T_A

=

ambient temperature °C

R_θJA

P_D

package junction-to-ambient thermal resistance °C/W

power dissipation in package

Historically, thermal resistance has been expressed as the sum of a

junction-to-case thermal resistance and a case-to-ambient thermal resistance,

as in this equation:

Equation 2: R_θJA= R_θJC+ R_θCA

Where:

R_θJA

R_θJC

R_θCA

=

package junction-to-ambient thermal resistance °C/W

package junction-to-case thermal resistance °C/W

package case-to-ambient thermal resistance °C/W

R_θJCis device-related and cannot be influenced by the user. The user controls

the thermal environment to change the case-to-ambient thermal resistance,

R_θCA. For example, the user can change the air flow around the device, add a

heat sink, change the mounting arrangement on the printed circuit board

(PCB) or otherwise change the thermal dissipation capability of the area

surrounding the device on a PCB. This model is most useful for ceramic

packages with heat sinks; some 90 percent of the heat flow is dissipated

through the case to the heat sink and out to the ambient environment. For

ceramic packages, in situations where the heat flow is split between a path to

the case and an alternate path through the PCB, analysis of the device thermal

performance may need the additional modeling capability of a system-level

thermal simulation tool.

The thermal performance of plastic packages is more dependent on the

temperature of the PCB to which the package is mounted. Again, if the

estimates obtained from R_θJAdo not satisfactorily answer whether the thermal

performance is adequate, a system-level model may be appropriate.

4-1

Electrical Design Considerations

A complicating factor is the existence of three common ways to determine the junction-to-case thermal

resistance in plastic packages.

• To minimize temperature variation across the surface, the thermal resistance is measured from the

junction to the outside surface of the package (case) closest to the chip mounting area when that surface

has a proper heat sink.

• To define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance

is measured from the junction to the point at which the leads attach to the case.

• If the temperature of the package case (T_T) is determined by a thermocouple, thermal resistance is

computed from the value obtained by the equation (T_J– T_T)/P_D.

As noted earlier, the junction-to-case thermal resistances quoted in this data sheet are determined using

the first definition. From a practical standpoint, that value is also suitable to determine the junction

temperature from a case thermocouple reading in forced convection environments. In natural convection,

the use of the junction-to-case thermal resistance to estimate junction temperature from a thermocouple

reading on the case of the package will yield an estimate of a junction temperature slightly higher than

actual temperature. Hence, the new thermal metric, thermal characterization parameter or Ψ_JT, has been

defined to be (T_J– T_T)/P_D. This value gives a better estimate of the junction temperature in natural

convection when the surface temperature of the package is used. Remember that surface temperature

readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the

surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a

40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy.

4.2 Electrical Design Considerations

CAUTION

This device contains protective circuitry to

guard against damage due to high static

voltage or electrical fields. However, normal

precautions are advised to avoid application

of any voltages higher than maximum rated

voltages to this high-impedance circuit.

Reliability of operation is enhanced if unused

inputs are tied to an appropriate logic voltage

level (for example, either GND or V ).

CC

4-2

Electrical Design Considerations

Use the following list of recommendations to ensure correct DSP operation.

• Provide a low-impedance path from the board power supply to each V_CCpin on the DSP and from the

board ground to each GND pin.

• Use at least six 0.01–0.1 µF bypass capacitors positioned as close as possible to the four sides of the

package to connect the V_CCpower source to GND.

• Ensure that capacitor leads and associated printed circuit traces that connect to the chip V_CCand GND

pins are less than 0.5 inch per capacitor lead.

• Use at least a four-layer PCB with two inner layers for V_CCand GND.

• Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal.

This recommendation particularly applies to the address and data buses as well as the IRQA, IRQB,

IRQC, IRQD, TA, and BG pins. Maximum PCB trace lengths on the order of 6 inches are recommended.

• Consider all device loads as well as parasitic capacitance due to PCB traces when you calculate

capacitance. This is especially critical in systems with higher capacitive loads that could create higher

transient currents in the V_CCand GND circuits.

• Take special care to minimize noise levels on the V_CCP, GND_P, and GND_P1pins.

• Use the following guidelines during power-up to ensure correct operation:

— RESET must be asserted when power is applied to the device and held low (asserted) until the

proper conditions are met.

— The input clock must be applied and stabilized before RESET is deasserted (pulled high).

— Ensure that the PLL Initial pin (PINIT) is pulled up or down, as appropriate, to determine whether

PLL is enabled or disabled before deasserting RESET.

— Ensure that the mode pins (MOD[A–D]) are pulled up or down, as appropriate, to select the desired

boot mode before deasserting RESET.

— All inputs must be terminated (that is, not allowed to float) by CMOS levels except for the five

pins with internal pull-up resistors (TMS, TDI, TCK, TRST and DE).

— During power-up, ensure that the voltage difference between the 5 V-tolerant pins and the chip

V_CCnever exceeds 3.5 V.

— The duration of the required RESET assertion depends on the clock source:

•

For an external clock generator, the minimum RESET duration is measured while RESET is

asserted, V_CCis valid, and the EXTAL input is active and valid.

For an internal oscillator, the minimum RESET duration is measured while RESET is asserted

and V_CCis valid. Specified timing reflects the crystal oscillator stabilization time after

power-up. Both the crystal specifications and those for other components connected to the

oscillator affect this number, and it reflects worst case conditions.

•

When the V_CCis valid, but the other “required RESET duration” conditions (as specified

previously) are not yet met, the device circuitry is in an uninitialized state that can result in

significant power consumption and heat-up. Designs should minimize this state to the shortest

possible duration.

Note: Failure to comply with any of these requirements may cause high current consumption during or

after power-up or prevent the correct device initialization.

• If multiple DSP devices are on the same board, check for cross-talk or excessive spikes on the supplies

due to synchronous operation of the devices.

• The Port A data bus (D[0–23]) uses internal keepers to maintain the last output value even when the

internal signal is tri-stated. Typically, no pull-up or pull-down resistors should be used with these

signal lines.

4-3

Power Consumption Considerations

4.3 Power Consumption Considerations

Power dissipation is a key issue in portable DSP applications. Some of the factors affecting current

consumption are described in this section. Most of the current consumed by CMOS devices is alternating

current (ac), which is charging and discharging the capacitances of the pins and internal nodes.

Current consumption is described by this formula:

Equation 3: I = C × V × f

Where:

C

V

f

=

node/pin capacitance

voltage swing

frequency of node/pin toggle

Example 4-1. Current Consumption

For a Port A address pin loaded with 50 pF capacitance, operating at 3.3 V, with a 66 MHz clock, toggling at its

maximum possible rate (33 MHz), the current consumption is expressed in Equation 4.

Equation 4: I = 50 × 10^–12× 3.3 × 33 × 10⁶= 5.48 mA

The maximum internal current (I_CCImax) value reflects the typical possible switching of the internal

buses on best-case operation conditions—not necessarily a real application case. The typical internal

current (I_CCItyp) value reflects the average switching of the internal buses on typical operating conditions.

Perform the following steps for applications that require very low current consumption:

1.

Set the EBD bit in the Operating Mode Register (OMR) to disable the external memory bus when

you are not accessing external memory. See the DSP56309 User’s Manual for details.

Minimize external memory accesses, and use internal memory accesses.

Minimize the number of pins that are switching.

Minimize the capacitive load on the pins.

Connect the unused inputs to pull-up or pull-down resistors.

Disable unused peripherals.

2.

3.

4.

5.

6.

7.

Disable unused pin activity (for example, CLKOUT, XTAL).

One way to evaluate power consumption is to use a current-per-MIPS measurement methodology to

minimize specific board effects (that is, to compensate for measured board current not caused by the

DSP). A benchmark power consumption test algorithm is listed in Appendix A. Use the test algorithm,

specific test current measurements, and the following equation to derive the current-per-MIPS value.

Equation 5: I ⁄ MIPS = I ⁄ MHz = (I_typF2– I_typF1) ⁄ (F2 – F1)

Where:

I_typF2

I_typF1

=

current at F2

current at F1

F2

F1

=

high frequency (any specified operating frequency)

low frequency (any specified operating frequency lower than F2)

Note: F1 should be significantly less than F2. For example, F2 could be 66 MHz and F1 could be 33

MHz. The degree of difference between F1 and F2 determines the amount of precision with

which the current rating can be determined for an application.

4-4

PLL Performance Issues

4.4 PLL Performance Issues

The following explanations should be considered as general observations on expected PLL behavior.

There is no test that replicates these exact numbers. These observations were measured on a limited

number of parts and were not verified over the entire temperature and voltage ranges.

4.4.1 Phase Skew Performance

The phase skew of the PLL is defined as the time difference between the falling edges of EXTAL and

CLKOUT for a given capacitive load on CLKOUT, over the entire process, temperature and voltage ranges.

As defined in Figure 2-2, External Clock Timing, on page 2-5 for input frequencies greater than 15 MHz

and the MF ≤ 4, this skew is greater than or equal to 0.0 ns and less than 1.8 ns; otherwise, this skew is

not guaranteed. However, for MF < 10 and input frequencies greater than 10 MHz, this skew is between

−1.4 ns and +3.2 ns.

4.4.2 Phase Jitter Performance

The phase jitter of the PLL is defined as the variations in the skew between the falling edges of EXTAL

and CLKOUT for a given device in specific temperature, voltage, input frequency, MF, and capacitive

load on CLKOUT. These variations are a result of the PLL locking mechanism. For input frequencies

greater than 15 MHz and MF ≤ 4, this jitter is less than ±0.6 ns; otherwise, this jitter is not guaranteed.

However, for MF < 10 and input frequencies greater than 10 MHz, this jitter is less than ±2 ns.

4.4.3 Frequency Jitter Performance

The frequency jitter of the PLL is defined as the variation of the frequency of CLKOUT. For small MF

(MF < 10) this jitter is smaller than 0.5 percent. For mid-range MF (10 < MF < 500) this jitter is between

0.5 percent and approximately 2 percent. For large MF (MF > 500), the frequency jitter is 2–3 percent.

4.5 Input (EXTAL) Jitter Requirements

The allowed jitter on the frequency of EXTAL is 0.5 percent. If the rate of change of the frequency of

EXTAL is slow (that is, it does not jump between the minimum and maximum values in one cycle) or the

frequency of the jitter is fast (that is, it does not stay at an extreme value for a long time), then the allowed

jitter can be 2 percent. The phase and frequency jitter performance results are valid only if the input jitter

is less than the prescribed values.

4-5

Input (EXTAL) Jitter Requirements

4-6

Appendix A

Power

Consumption

Benchmark

The following benchmark program evaluates DSP56309 power use in a test situation. It enables the PLL,

disables the external clock, and uses repeated multiply-accumulate (MAC) instructions with a set of

synthetic DSP application data to emulate intensive sustained DSP operation.

;**************************************************************************

;*

*

;* CHECKS

;*

Typical Power Consumption

;**************************************************************************

page

nolist

200,55,0,0,0

I_VEC EQU $000000; Interrupt vectors for program debug only

START EQU $8000; MAIN (external) program starting address

INT_PROG EQU $100 ; INTERNAL program memory starting address

INT_XDAT EQU $0; INTERNAL X-data memory starting address

INT_YDAT EQU $0; INTERNAL Y-data memory starting address

INCLUDE "ioequ.asm"

INCLUDE "intequ.asm"

list

org

P:START

;

movep #$0243FF,x:M_BCR ;; BCR: Area 3 = 2 w.s (SRAM)

; Default: 2w.s (SRAM)

;

movep

#$0d0000,x:M_PCTL

; XTAL disable

; PLL enable

; CLKOUT disable

;

; Load the program

;

move

do

move

nop

#INT_PROG,r0

#PROG_START,r1

#(PROG_END-PROG_START),PLOAD_LOOP

p:(r1)+,x0

x0,p:(r0)+

PLOAD_LOOP

;

; Load the X-data

;

move

do

move

#INT_XDAT,r0

#XDAT_START,r1

#(XDAT_END-XDAT_START),XLOAD_LOOP

p:(r1)+,x0

x0,x:(r0)+

XLOAD_LOOP

;

; Load the Y-data

;

move

do

move

#INT_YDAT,r0

#YDAT_START,r1

#(YDAT_END-YDAT_START),YLOAD_LOOP

p:(r1)+,x0

x0,y:(r0)+

YLOAD_LOOP

;

jmp

PROG_START

INT_PROG

move

#$0,r0

#$0,r4

#$3f,m0

#$3f,m4

move

;

clr

a

A-1

Power Consumption Benchmark

clr

b

move

bset

#$0,x0

#$0,x1

#$0,y0

#$0,y1

#4,omr

; ebd

;

sbr

dor

mac

add

mac

move

#60,_end

x0,y0,ax:(r0)+,x1

x1,y1,ax:(r0)+,x0

a,b

x0,y0,ax:(r0)+,x1

x1,y1,a

y:(r4)+,y1

y:(r4)+,y0

b1,x:$ff

_end

bra

nop

sbr

PROG_END

nop

XDAT_START

;

org

dc

x:0

$262EB9

$86F2FE

$E56A5F

$616CAC

$8FFD75

$9210A

$A06D7B

$CEA798

$8DFBF1

$A063D6

$6C6657

$C2A544

$A3662D

$A4E762

$84F0F3

$E6F1B0

$B3829

$8BF7AE

$63A94F

$EF78DC

$242DE5

$A3E0BA

$EBAB6B

$8726C8

$CA361

$2F6E86

$A57347

$4BE774

$8F349D

$A1ED12

$4BFCE3

$EA26E0

$CD7D99

$4BA85E

$27A43F

$A8B10C

$D3A55

$25EC6A

$2A255B

$A5F1F8

$2426D1

$AE6536

$CBBC37

$6235A4

$37F0D

$63BEC2

$A5E4D3

$8CE810

$3FF09

$60E50E

$CFFB2F

$40753C

$8262C5

$CA641A

A-2

Power Consumption Benchmark

dc

$EB3B4B

$2DA928

$AB6641

$28A7E6

$4E2127

$482FD4

$7257D

$E53C72

$1A8C3

$E27540

XDAT_END

YDAT_START

;

org

dc

y:0

$5B6DA

$C3F70B

$6A39E8

$81E801

$C666A6

$46F8E7

$AAEC94

$24233D

$802732

$2E3C83

$A43E00

$C2B639

$85A47E

$ABFDDF

$F3A2C

$2D7CF5

$E16A8A

$ECB8FB

$4BED18

$43F371

$83A556

$E1E9D7

$ACA2C4

$8135AD

$2CE0E2

$8F2C73

$432730

$A87FA9

$4A292E

$A63CCF

$6BA65C

$E06D65

$1AA3A

$A1B6EB

$48AC48

$EF7AE1

$6E3006

$62F6C7

$6064F4

$87E41D

$CB2692

$2C3863

$C6BC60

$43A519

$6139DE

$ADF7BF

$4B3E8C

$6079D5

$E0F5EA

$8230DB

$A3B778

$2BFE51

$E0A6B6

$68FFB7

$28F324

$8F2E8D

$667842

$83E053

$A1FD90

$6B2689

$85B68E

$622EAF

$6162BC

$E4A245

YDAT_END

;**************************************************************************

A-3

Power Consumption Benchmark

;

EQUATES for DSP56309 I/O registers and ports

Last update: June 11 1995

;**************************************************************************

page

opt

132,55,0,0,0

mex

ioequ

ident

1,0

;------------------------------------------------------------------------

;

EQUATES for I/O Port Programming

;------------------------------------------------------------------------

;

Register Addresses

M_HDR EQU $FFFFC9

M_HDDR EQU $FFFFC8

M_PCRC EQU $FFFFBF

M_PRRC EQU $FFFFBE

M_PDRC EQU $FFFFBD

M_PCRD EQU $FFFFAF

M_PRRD EQU $FFFFAE

M_PDRD EQU $FFFFAD

M_PCRE EQU $FFFF9F

M_PRRE EQU $FFFF9E

M_PDRE EQU $FFFF9D

M_OGDB EQU $FFFFFC

; Host port GPIO data Register

; Host port GPIO direction Register

; Port C Control Register

; Port C Direction Register

; Port C GPIO Data Register

; Port D Control register

; Port D Direction Data Register

; Port D GPIO Data Register

; Port E Control register

; Port E Direction Register

; Port E Data Register

; OnCE GDB Register

;------------------------------------------------------------------------

;

EQUATES for Host Interface

;------------------------------------------------------------------------

;

Register Addresses

M_HCR EQU $FFFFC2

M_HSR EQU $FFFFC3

M_HPCR EQU $FFFFC4

M_HBAR EQU $FFFFC5

M_HRX EQU $FFFFC6

M_HTX EQU $FFFFC7

; Host Control Register

; Host Status Register

; Host Polarity Control Register

; Host Base Address Register

; Host Receive Register

; Host Transmit Register

;

HCR bits definition

M_HRIE EQU $0

M_HTIE EQU $1

M_HCIE EQU $2

M_HF2 EQU $3

M_HF3 EQU $4

; Host Receive interrupts Enable

; Host Transmit Interrupt Enable

; Host Command Interrupt Enable

; Host Flag 2

; Host Flag 3

;

HSR bits definition

M_HRDF EQU $0

M_HTDE EQU $1

M_HCP EQU $2

M_HF0 EQU $3

M_HF1 EQU $4

; Host Receive Data Full

; Host Receive Data Empty

; Host Command Pending

; Host Flag 0

; Host Flag 1

;

HPCR bits definition

M_HGEN EQU $0

M_HA8EN EQU $1

M_HA9EN EQU $2

M_HCSEN EQU $3

M_HREN EQU $4

M_HAEN EQU $5

M_HEN EQU $6

M_HOD EQU $8

M_HDSP EQU $9

M_HASP EQU $A

M_HMUX EQU $B

M_HD_HS EQU $C

M_HCSP EQU $D

M_HRP EQU $E

M_HAP EQU $F

; Host Port GPIO Enable

; Host Address 8 Enable

; Host Address 9 Enable

; Host Chip Select Enable

; Host Request Enable

; Host Acknowledge Enable

; Host Enable

; Host Request Open Drain mode

; Host Data Strobe Polarity

; Host Address Strobe Polarity

; Host Multiplexed bus select

; Host Double/Single Strobe select

; Host Chip Select Polarity

; Host Request Polarity

; Host Acknowledge Polarity

A-4

Power Consumption Benchmark

;------------------------------------------------------------------------

;

EQUATES for Serial Communications Interface (SCI)

;------------------------------------------------------------------------

;

Register Addresses

M_STXH EQU $FFFF97

M_STXM EQU $FFFF96

M_STXL EQU $FFFF95

M_SRXH EQU $FFFF9A

M_SRXM EQU $FFFF99

M_SRXL EQU $FFFF98

M_STXA EQU $FFFF94

M_SCR EQU $FFFF9C

M_SSR EQU $FFFF93

M_SCCR EQU $FFFF9B

; SCI Transmit Data Register (high)

; SCI Transmit Data Register (middle)

; SCI Transmit Data Register (low)

; SCI Receive Data Register (high)

; SCI Receive Data Register (middle)

; SCI Receive Data Register (low)

; SCI Transmit Address Register

; SCI Control Register

; SCI Status Register

; SCI Clock Control Register

;

SCI Control Register Bit Flags

M_WDS EQU $7

M_WDS0 EQU 0

M_WDS1 EQU 1

M_WDS2 EQU 2

M_SSFTD EQU 3

M_SBK EQU 4

; Word Select Mask (WDS0-WDS3)

; Word Select 0

; Word Select 1

; Word Select 2

; SCI Shift Direction

; Send Break

M_WAKE EQU 5

M_RWU EQU 6

; Wakeup Mode Select

; Receiver Wakeup Enable

; Wired-OR Mode Select

; SCI Receiver Enable

; SCI Transmitter Enable

; Idle Line Interrupt Enable

; SCI Receive Interrupt Enable

; SCI Transmit Interrupt Enable

; Timer Interrupt Enable

; Timer Interrupt Rate

; SCI Clock Polarity

M_WOMS EQU 7

M_SCRE EQU 8

M_SCTE EQU 9

M_ILIE EQU 10

M_SCRIE EQU 11

M_SCTIE EQU 12

M_TMIE EQU 13

M_TIR EQU 14

M_SCKP EQU 15

M_REIE EQU 16

; SCI Error Interrupt Enable (REIE)

;

SCI Status Register Bit Flags

M_TRNE EQU 0

M_TDRE EQU 1

M_RDRF EQU 2

M_IDLE EQU 3

M_OR EQU 4

; Transmitter Empty

; Transmit Data Register Empty

; Receive Data Register Full

; Idle Line Flag

; Overrun Error Flag

M_PE EQU 5

; Parity Error

M_FE EQU 6

M_R8 EQU 7

; Framing Error Flag

; Received Bit 8 (R8) Address

;

SCI Clock Control Register

M_CD EQU $FFF

M_COD EQU 12

M_SCP EQU 13

M_RCM EQU 14

M_TCM EQU 15

; Clock Divider Mask (CD0-CD11)

; Clock Out Divider

; Clock Prescaler

; Receive Clock Mode Source Bit

; Transmit Clock Source Bit

;------------------------------------------------------------------------

;

EQUATES for Synchronous Serial Interface (SSI)

;------------------------------------------------------------------------

;

Register Addresses Of SSI0

M_TX00 EQU $FFFFBC

M_TX01 EQU $FFFFBB

M_TX02 EQU $FFFFBA

M_TSR0 EQU $FFFFB9

M_RX0 EQU $FFFFB8

M_SSISR0 EQU $FFFFB7

M_CRB0 EQU $FFFFB6

M_CRA0 EQU $FFFFB5

M_TSMA0 EQU $FFFFB4

M_TSMB0 EQU $FFFFB3

M_RSMA0 EQU $FFFFB2

M_RSMB0 EQU $FFFFB1

; SSI0 Transmit Data Register 0

; SSIO Transmit Data Register 1

; SSIO Transmit Data Register 2

; SSI0 Time Slot Register

; SSI0 Receive Data Register

; SSI0 Status Register

; SSI0 Control Register B

; SSI0 Control Register A

; SSI0 Transmit Slot Mask Register A

; SSI0 Transmit Slot Mask Register B

; SSI0 Receive Slot Mask Register A

; SSI0 Receive Slot Mask Register B

A-5

Power Consumption Benchmark

;

Register Addresses Of SSI1

M_TX10 EQU $FFFFAC

M_TX11 EQU $FFFFAB

M_TX12 EQU $FFFFAA

M_TSR1 EQU $FFFFA9

M_RX1 EQU $FFFFA8

M_SSISR1 EQU $FFFFA7

M_CRB1 EQU $FFFFA6

M_CRA1 EQU $FFFFA5

M_TSMA1 EQU $FFFFA4

M_TSMB1 EQU $FFFFA3

M_RSMA1 EQU $FFFFA2

M_RSMB1 EQU $FFFFA1

; SSI1 Transmit Data Register 0

; SSI1 Transmit Data Register 1

; SSI1 Transmit Data Register 2

; SSI1 Time Slot Register

; SSI1 Receive Data Register

; SSI1 Status Register

; SSI1 Control Register B

; SSI1 Control Register A

; SSI1 Transmit Slot Mask Register A

; SSI1 Transmit Slot Mask Register B

; SSI1 Receive Slot Mask Register A

; SSI1 Receive Slot Mask Register B

;

SSI Control Register A Bit Flags

M_PM EQU $FF

; Prescale Modulus Select Mask (PM0-PM7)

; Prescaler Range

M_PSR EQU 11

M_DC EQU $1F000

M_ALC EQU 18

M_WL EQU $380000

M_SSC1 EQU 22

; Frame Rate Divider Control Mask (DC0-DC7)

; Alignment Control (ALC)

; Word Length Control Mask (WL0-WL7)

; Select SC1 as TR #0 drive enable (SSC1)

;

SSI Control Register B Bit Flags

M_OF EQU $3

; Serial Output Flag Mask

; Serial Output Flag 0

; Serial Output Flag 1

M_OF0 EQU 0

M_OF1 EQU 1

M_SCD EQU $1C

M_SCD0 EQU 2

M_SCD1 EQU 3

M_SCD2 EQU 4

M_SCKD EQU 5

M_SHFD EQU 6

M_FSL EQU $180

M_FSL0 EQU 7

M_FSL1 EQU 8

M_FSR EQU 9

M_FSP EQU 10

M_CKP EQU 11

M_SYN EQU 12

M_MOD EQU 13

M_SSTE EQU $1C000

M_SSTE2 EQU 14

M_SSTE1 EQU 15

M_SSTE0 EQU 16

M_SSRE EQU 17

M_SSTIE EQU 18

M_SSRIE EQU 19

M_STLIE EQU 20

M_SRLIE EQU 21

M_STEIE EQU 22

M_SREIE EQU 23

; Serial Control Direction Mask

; Serial Control 0 Direction

; Serial Control 1 Direction

; Serial Control 2 Direction

; Clock Source Direction

; Shift Direction

; Frame Sync Length Mask (FSL0-FSL1)

; Frame Sync Length 0

; Frame Sync Length 1

; Frame Sync Relative Timing

; Frame Sync Polarity

; Clock Polarity

; Sync/Async Control

; SSI Mode Select

; SSI Transmit enable Mask

; SSI Transmit #2 Enable

; SSI Transmit #1 Enable

; SSI Transmit #0 Enable

; SSI Receive Enable

; SSI Transmit Interrupt Enable

; SSI Receive Interrupt Enable

; SSI Transmit Last Slot Interrupt Enable

; SSI Receive Last Slot Interrupt Enable

; SSI Transmit Error Interrupt Enable

; SI Receive Error Interrupt Enable

;

SSI Status Register Bit Flags

M_IF EQU $3

M_IF0 EQU 0

M_IF1 EQU 1

M_TFS EQU 2

M_RFS EQU 3

M_TUE EQU 4

M_ROE EQU 5

M_TDE EQU 6

M_RDF EQU 7

; Serial Input Flag Mask

; Serial Input Flag 0

; Serial Input Flag 1

; Transmit Frame Sync Flag

; Receive Frame Sync Flag

; Transmitter Underrun Error FLag

; Receiver Overrun Error Flag

; Transmit Data Register Empty

; Receive Data Register Full

;

SSI Transmit Slot Mask Register A

M_SSTSA EQU $FFFF

; SSI Transmit Slot Bits Mask A (TS0-TS15)

; SSI Transmit Slot Bits Mask B (TS16-TS31)

; SSI Receive Slot Bits Mask A (RS0-RS15)

; SSI Receive Slot Bits Mask B (RS16-RS31)

;

SSI Transmit Slot Mask Register B

M_SSTSB EQU $FFFF

;

SSI Receive Slot Mask Register A

M_SSRSA EQU $FFFF

;

SSI Receive Slot Mask Register B

M_SSRSB EQU $FFFF

A-6

Power Consumption Benchmark

;------------------------------------------------------------------------

;

EQUATES for Exception Processing

;------------------------------------------------------------------------

;

Register Addresses

M_IPRC EQU $FFFFFF

M_IPRP EQU $FFFFFE

; Interrupt Priority Register Core

; Interrupt Priority Register Peripheral

;

Interrupt Priority Register Core (IPRC)

M_IAL EQU $7

; IRQA Mode Mask

M_IAL0 EQU 0

; IRQA Mode Interrupt Priority Level (low)

; IRQA Mode Interrupt Priority Level (high)

; IRQA Mode Trigger Mode

M_IAL1 EQU 1

M_IAL2 EQU 2

M_IBL EQU $38

M_IBL0 EQU 3

; IRQB Mode Mask

; IRQB Mode Interrupt Priority Level (low)

; IRQB Mode Interrupt Priority Level (high)

; IRQB Mode Trigger Mode

M_IBL1 EQU 4

M_IBL2 EQU 5

M_ICL EQU $1C0

M_ICL0 EQU 6

; IRQC Mode Mask

; IRQC Mode Interrupt Priority Level (low)

; IRQC Mode Interrupt Priority Level (high)

; IRQC Mode Trigger Mode

M_ICL1 EQU 7

M_ICL2 EQU 8

M_IDL EQU $E00

M_IDL0 EQU 9

; IRQD Mode Mask

; IRQD Mode Interrupt Priority Level (low)

; IRQD Mode Interrupt Priority Level (high)

; IRQD Mode Trigger Mode

M_IDL1 EQU 10

M_IDL2 EQU 11

M_D0L EQU $3000

M_D0L0 EQU 12

M_D0L1 EQU 13

M_D1L EQU $C000

M_D1L0 EQU 14

M_D1L1 EQU 15

M_D2L EQU $30000

M_D2L0 EQU 16

M_D2L1 EQU 17

M_D3L EQU $C0000

M_D3L0 EQU 18

M_D3L1 EQU 19

M_D4L EQU $300000

M_D4L0 EQU 20

M_D4L1 EQU 21

M_D5L EQU $C00000

M_D5L0 EQU 22

M_D5L1 EQU 23

; DMA0 Interrupt priority Level Mask

; DMA0 Interrupt Priority Level (low)

; DMA0 Interrupt Priority Level (high)

; DMA1 Interrupt Priority Level Mask

; DMA1 Interrupt Priority Level (low)

; DMA1 Interrupt Priority Level (high)

; DMA2 Interrupt priority Level Mask

; DMA2 Interrupt Priority Level (low)

; DMA2 Interrupt Priority Level (high)

; DMA3 Interrupt Priority Level Mask

; DMA3 Interrupt Priority Level (low)

; DMA3 Interrupt Priority Level (high)

; DMA4 Interrupt priority Level Mask

; DMA4 Interrupt Priority Level (low)

; DMA4 Interrupt Priority Level (high)

; DMA5 Interrupt priority Level Mask

; DMA5 Interrupt Priority Level (low)

; DMA5 Interrupt Priority Level (high)

;

Interrupt Priority Register Peripheral (IPRP)

M_HPL EQU $3

M_HPL0 EQU 0

M_HPL1 EQU 1

M_S0L EQU $C

M_S0L0 EQU 2

M_S0L1 EQU 3

M_S1L EQU $30

M_S1L0 EQU 4

M_S1L1 EQU 5

M_SCL EQU $C0

M_SCL0 EQU 6

M_SCL1 EQU 7

M_T0L EQU $300

M_T0L0 EQU 8

M_T0L1 EQU 9

; Host Interrupt Priority Level Mask

; Host Interrupt Priority Level (low)

; Host Interrupt Priority Level (high)

; SSI0 Interrupt Priority Level Mask

; SSI0 Interrupt Priority Level (low)

; SSI0 Interrupt Priority Level (high)

; SSI1 Interrupt Priority Level Mask

; SSI1 Interrupt Priority Level (low)

; SSI1 Interrupt Priority Level (high)

; SCI Interrupt Priority Level Mask

; SCI Interrupt Priority Level (low)

; SCI Interrupt Priority Level (high)

; TIMER Interrupt Priority Level Mask

; TIMER Interrupt Priority Level (low)

; TIMER Interrupt Priority Level (high)

;------------------------------------------------------------------------

;

EQUATES for TIMER

;------------------------------------------------------------------------

;

Register Addresses Of TIMER0

M_TCSR0 EQU $FFFF8F ; Timer 0 Control/Status Register

A-7

Power Consumption Benchmark

M_TLR0 EQU $FFFF8E

M_TCPR0 EQU $FFFF8D

M_TCR0 EQU $FFFF8C

; TIMER0 Load Reg

; TIMER0 Compare Register

; TIMER0 Count Register

;

Register Addresses Of TIMER1

M_TCSR1 EQU $FFFF8B

M_TLR1 EQU $FFFF8A

M_TCPR1 EQU $FFFF89

M_TCR1 EQU $FFFF88

; TIMER1 Control/Status Register

; TIMER1 Load Reg

; TIMER1 Compare Register

; TIMER1 Count Register

;

Register Addresses Of TIMER2

M_TCSR2 EQU $FFFF87

M_TLR2 EQU $FFFF86

M_TCPR2 EQU $FFFF85

M_TCR2 EQU $FFFF84

M_TPLR EQU $FFFF83

M_TPCR EQU $FFFF82

; TIMER2 Control/Status Register

; TIMER2 Load Reg

; TIMER2 Compare Register

; TIMER2 Count Register

; TIMER Prescaler Load Register

; TIMER Prescalar Count Register

;

Timer Control/Status Register Bit Flags

M_TE EQU 0

; Timer Enable

M_TOIE EQU 1

M_TCIE EQU 2

M_TC EQU $F0

M_INV EQU 8

M_TRM EQU 9

M_DIR EQU 11

M_DI EQU 12

M_DO EQU 13

M_PCE EQU 15

M_TOF EQU 20

M_TCF EQU 21

; Timer Overflow Interrupt Enable

; Timer Compare Interrupt Enable

; Timer Control Mask (TC0-TC3)

; Inverter Bit

; Timer Restart Mode

; Direction Bit

; Data Input

; Data Output

; Prescaled Clock Enable

; Timer Overflow Flag

; Timer Compare Flag

;

Timer Prescaler Register Bit Flags

M_PS EQU $600000

M_PS0 EQU 21

M_PS1 EQU 22

; Prescaler Source Mask

;

Timer Control Bits

M_TC0 EQU 4

M_TC1 EQU 5

M_TC2 EQU 6

M_TC3 EQU 7

; Timer Control 0

; Timer Control 1

; Timer Control 2

; Timer Control 3

;------------------------------------------------------------------------

;

EQUATES for Direct Memory Access (DMA)

;------------------------------------------------------------------------

;

Register Addresses Of DMA

M_DSTR EQU FFFFF4 ; DMA Status Register

M_DOR0 EQU $FFFFF3 ; DMA Offset Register 0

M_DOR1 EQU $FFFFF2 ; DMA Offset Register 1

M_DOR2 EQU $FFFFF1 ; DMA Offset Register 2

M_DOR3 EQU $FFFFF0 ; DMA Offset Register 3

;

Register Addresses Of DMA0

M_DSR0 EQU $FFFFEF ; DMA0 Source Address Register

M_DDR0 EQU $FFFFEE ; DMA0 Destination Address Register

M_DCO0 EQU $FFFFED ; DMA0 Counter

M_DCR0 EQU $FFFFEC ; DMA0 Control Register

;

Register Addresses Of DMA1

M_DSR1 EQU $FFFFEB ; DMA1 Source Address Register

M_DDR1 EQU $FFFFEA ; DMA1 Destination Address Register

M_DCO1 EQU $FFFFE9 ; DMA1 Counter

M_DCR1 EQU $FFFFE8 ; DMA1 Control Register

;

Register Addresses Of DMA2

M_DSR2 EQU $FFFFE7 ; DMA2 Source Address Register

A-8

Power Consumption Benchmark

M_DDR2 EQU $FFFFE6 ; DMA2 Destination Address Register

M_DCO2 EQU $FFFFE5 ; DMA2 Counter

M_DCR2 EQU $FFFFE4 ; DMA2 Control Register

;

Register Addresses Of DMA4

M_DSR3 EQU $FFFFE3 ; DMA3 Source Address Register

M_DDR3 EQU $FFFFE2 ; DMA3 Destination Address Register

M_DCO3 EQU $FFFFE1 ; DMA3 Counter

M_DCR3 EQU $FFFFE0 ; DMA3 Control Register

;

Register Addresses Of DMA4

M_DSR4 EQU $FFFFDF ; DMA4 Source Address Register

M_DDR4 EQU $FFFFDE ; DMA4 Destination Address Register

M_DCO4 EQU $FFFFDD ; DMA4 Counter

M_DCR4 EQU $FFFFDC ; DMA4 Control Register

;

Register Addresses Of DMA5

M_DSR5 EQU $FFFFDB ; DMA5 Source Address Register

M_DDR5 EQU $FFFFDA ; DMA5 Destination Address Register

M_DCO5 EQU $FFFFD9 ; DMA5 Counter

M_DCR5 EQU $FFFFD8 ; DMA5 Control Register

;

DMA Control Register

M_DSS EQU $3

M_DSS0 EQU 0

M_DSS1 EQU 1

M_DDS EQU $C

M_DDS0 EQU 2

M_DDS1 EQU 3

; DMA Source Space Mask (DSS0-Dss1)

; DMA Source Memory space 0

; DMA Source Memory space 1

; DMA Destination Space Mask (DDS-DDS1)

; DMA Destination Memory Space 0

; DMA Destination Memory Space 1

M_DAM EQU $3f0 ; DMA Address Mode Mask (DAM5-DAM0)

M_DAM0 EQU 4 ; DMA Address Mode 0

M_DAM1 EQU 5 ; DMA Address Mode 1

M_DAM2 EQU 6 ; DMA Address Mode 2

M_DAM3 EQU 7 ; DMA Address Mode 3

M_DAM4 EQU 8 ; DMA Address Mode 4

M_DAM5 EQU 9 ; DMA Address Mode 5

M_D3D EQU 10

; DMA Three Dimensional Mode

M_DRS EQU $F800; DMA Request Source Mask (DRS0-DRS4)

M_DCON EQU 16 ; DMA Continuous Mode

M_DPR EQU $60000; DMA Channel Priority

M_DPR0 EQU 17 ; DMA Channel Priority Level (low)

M_DPR1 EQU 18 ; DMA Channel Priority Level (high)

M_DTM EQU $380000; DMA Transfer Mode Mask (DTM2-DTM0)

M_DTM0 EQU 19 ; DMA Transfer Mode 0

M_DTM1 EQU 20 ; DMA Transfer Mode 1

M_DTM2 EQU 21 ; DMA Transfer Mode 2

M_DIE EQU 22

M_DE EQU 23

; DMA Interrupt Enable bit

; DMA Channel Enable bit

;

DMA Status Register

M_DTD EQU $3F ; Channel Transfer Done Status MASK (DTD0-DTD5)

M_DTD0 EQU 0

M_DTD1 EQU 1

M_DTD2 EQU 2

M_DTD3 EQU 3

M_DTD4 EQU 4

M_DTD5 EQU 5

M_DACT EQU

; DMA Channel Transfer Done Status 0

; DMA Channel Transfer Done Status 1

; DMA Channel Transfer Done Status 2

; DMA Channel Transfer Done Status 3

; DMA Channel Transfer Done Status 4

; DMA Channel Transfer Done Status 5

; DMA Active State

8

M_DCH EQU $E00; DMA Active Channel Mask (DCH0-DCH2)

M_DCH0 EQU

M_DCH1 EQU 10 ; DMA Active Channel 1

M_DCH2 EQU 11 ; DMA Active Channel 2

9

; DMA Active Channel 0

;------------------------------------------------------------------------

;

EQUATES for Phase Locked Loop (PLL)

;------------------------------------------------------------------------

;

Register Addresses Of PLL

M_PCTL EQU $FFFFFD ; PLL Control Register

PLL Control Register

;

A-9

Power Consumption Benchmark

M_MF EQU $FFF : Multiplication Factor Bits Mask (MF0-MF11)

M_DF EQU $7000 ; Division Factor Bits Mask (DF0-DF2)

M_XTLR EQU 15 ; XTAL Range select bit

M_XTLD EQU 16 ; XTAL Disable Bit

M_PSTP EQU 17 ; STOP Processing State Bit

M_PEN EQU 18

; PLL Enable Bit

M_PCOD EQU 19 ; PLL Clock Output Disable Bit

M_PD EQU $F00000; PreDivider Factor Bits Mask (PD0-PD3)

;------------------------------------------------------------------------

;

EQUATES for BIU

;------------------------------------------------------------------------

;

Register Addresses Of BIU

M_BCR EQU $FFFFFB; Bus Control Register

M_DCR EQU $FFFFFA; DRAM Control Register

M_AAR0 EQU $FFFFF9; Address Attribute Register 0

M_AAR1 EQU $FFFFF8; Address Attribute Register 1

M_AAR2 EQU $FFFFF7; Address Attribute Register 2

M_AAR3 EQU $FFFFF6; Address Attribute Register 3

M_IDR EQU $FFFFF5 ; ID Register

;

Bus Control Register

M_BA0W EQU $1F ; Area 0 Wait Control Mask (BA0W0-BA0W4)

M_BA1W EQU $3E0; Area 1 Wait Control Mask (BA1W0-BA14)

M_BA2W EQU $1C00; Area 2 Wait Control Mask (BA2W0-BA2W2)

M_BA3W EQU $E000; Area 3 Wait Control Mask (BA3W0-BA3W3)

M_BDFW EQU $1F0000 ; Default Area Wait Control Mask (BDFW0-BDFW4)

M_BBS EQU 21

M_BLH EQU 22

M_BRH EQU 23

; Bus State

; Bus Lock Hold

; Bus Request Hold

;

DRAM Control Register

M_BCW EQU $3

M_BRW EQU $C

; In Page Wait States Bits Mask (BCW0-BCW1)

; Out Of Page Wait States Bits Mask (BRW0-BRW1)

M_BPS EQU $300 ; DRAM Page Size Bits Mask (BPS0-BPS1)

M_BPLE EQU 11 ; Page Logic Enable

M_BME EQU 12

M_BRE EQU 13

; Mastership Enable

; Refresh Enable

M_BSTR EQU 14 ; Software Triggered Refresh

M_BRF EQU $7F8000; Refresh Rate Bits Mask (BRF0-BRF7)

M_BRP EQU 23

; Refresh prescaler

;

Address Attribute Registers

M_BAT EQU $3

M_BAAP EQU 2

M_BPEN EQU 3

M_BXEN EQU 4

M_BYEN EQU 5

M_BAM EQU 6

M_BPAC EQU 7

; Ext. Access Type and Pin Def. Bits Mask (BAT0-BAT1)

; Address Attribute Pin Polarity

; Program Space Enable

; X Data Space Enable

; Y Data Space Enable

; Address Muxing

; Packing Enable

M_BNC EQU $F00 ; Number of Address Bits to Compare Mask (BNC0-BNC3)

M_BAC EQU $FFF000; Address to Compare Bits Mask (BAC0-BAC11)

;

control and status bits in SR

M_CP EQU $c00000; mask for CORE-DMA priority bits in SR

M_CA EQU 0

M_V EQU 1

M_Z EQU 2

M_N EQU 3

M_U EQU 4

M_E EQU 5

M_L EQU 6

M_S EQU 7

M_I0 EQU 8

M_I1 EQU 9

M_S0 EQU 10

M_S1 EQU 11

M_SC EQU 13

M_DM EQU 14

; Carry

; Overflow

; Zero

; Negative

; Unnormalized

; Extension

; Limit

; Scaling Bit

; Interupt Mask Bit 0

; Interupt Mask Bit 1

; Scaling Mode Bit 0

; Scaling Mode Bit 1

; Sixteen_Bit Compatibility

; Double Precision Multiply

A-10

Power Consumption Benchmark

M_LF EQU 15

M_FV EQU 16

M_SA EQU 17

M_CE EQU 19

M_SM EQU 20

M_RM EQU 21

M_CP0 EQU 22

M_CP1 EQU 23

; DO-Loop Flag

; DO-Forever Flag

; Sixteen-Bit Arithmetic

; Instruction Cache Enable

; Arithmetic Saturation

; Rounding Mode

; bit 0 of priority bits in SR

; bit 1 of priority bits in SR

;

control and status bits in OMR

M_CDP EQU $300 ; mask for CORE-DMA priority bits in OMR

M_MA

M_MB

M_MC

M_MD

equ0

; Operating Mode A

equ1

; Operating Mode B

equ2

equ3

; Operating Mode C

; Operating Mode D

M_EBD EQU 4

M_SD EQU 6

; External Bus Disable bit in OMR

; Stop Delay

M_MS EQU 7

; Memory Switch bit in OMR

; bit 0 of priority bits in OMR

; bit 1 of priority bits in OMR

M_CDP0 EQU 8

M_CDP1 EQU 9

M_BEN

EQU 10 ; Burst Enable

M_TAS EQU 11 ; TA Synchronize Select

M_BRT EQU 12 ; Bus Release Timing

M_ATE EQU 15

M_XYS EQU 16

M_EUN EQU 17

M_EOV EQU 18

M_WRP EQU 19

M_SEN EQU 20

; Address Tracing Enable bit in OMR.

; Stack Extension space select bit in OMR.

; Extensed stack UNderflow flag in OMR.

; Extended stack OVerflow flag in OMR.

; Extended WRaP flag in OMR.

; Stack Extension Enable bit in OMR.

;*************************************************************************

;

EQUATES for DSP56309 interrupts

Last update: June 11 1995

;*************************************************************************

page

opt

132,55,0,0,0

mex

intequ ident

if

1,0

@DEF(I_VEC)

;leave user definition as is.

else

I_VEC EQU $0

endif

;------------------------------------------------------------------------

; Non-Maskable interrupts

;------------------------------------------------------------------------

I_RESET EQU I_VEC+$00 ; Hardware RESET

I_STACK EQU I_VEC+$02 ; Stack Error

I_ILL EQU I_VEC+$04

I_DBG EQU I_VEC+$06

I_TRAP EQU I_VEC+$08

I_NMI EQU I_VEC+$0A

; Illegal Instruction

; Debug Request

; Trap

; Non Maskable Interrupt

;------------------------------------------------------------------------

; Interrupt Request Pins

;------------------------------------------------------------------------

I_IRQA EQU I_VEC+$10

I_IRQB EQU I_VEC+$12

I_IRQC EQU I_VEC+$14

I_IRQD EQU I_VEC+$16

; IRQA

; IRQB

; IRQC

; IRQD

;------------------------------------------------------------------------

; DMA Interrupts

;------------------------------------------------------------------------

I_DMA0 EQU I_VEC+$18

I_DMA1 EQU I_VEC+$1A

I_DMA2 EQU I_VEC+$1C

I_DMA3 EQU I_VEC+$1E

; DMA Channel 0

; DMA Channel 1

; DMA Channel 2

; DMA Channel 3

A-11

Power Consumption Benchmark

I_DMA4 EQU I_VEC+$20

I_DMA5 EQU I_VEC+$22

; DMA Channel 4

; DMA Channel 5

;------------------------------------------------------------------------

; Timer Interrupts

;------------------------------------------------------------------------

I_TIM0C EQU I_VEC+$24 ; TIMER 0 compare

I_TIM0OF EQU I_VEC+$26; TIMER 0 overflow

I_TIM1C EQU I_VEC+$28 ; TIMER 1 compare

I_TIM1OF EQU I_VEC+$2A; TIMER 1 overflow

I_TIM2C EQU I_VEC+$2C ; TIMER 2 compare

I_TIM2OF EQU I_VEC+$2E; TIMER 2 overflow

;------------------------------------------------------------------------

; ESSI Interrupts

;------------------------------------------------------------------------

I_SI0RD EQU I_VEC+$30 ; ESSI0 Receive Data

I_SI0RDE EQU I_VEC+$32; ESSI0 Receive Data w/ exception Status

I_SI0RLS EQU I_VEC+$34; ESSI0 Receive last slot

I_SI0TD EQU I_VEC+$36 ; ESSI0 Transmit data

I_SI0TDE EQU I_VEC+$38; ESSI0 Transmit Data w/ exception Status

I_SI0TLS EQU I_VEC+$3A; ESSI0 Transmit last slot

I_SI1RD EQU I_VEC+$40 ; ESSI1 Receive Data

I_SI1RDE EQU I_VEC+$42; ESSI1 Receive Data w/ exception Status

I_SI1RLS EQU I_VEC+$44

I_SI1TD EQU I_VEC+$46

; ESSI1 Receive last slot

; ESSI1 Transmit data

I_SI1TDE EQU I_VEC+$48; ESSI1 Transmit Data w/ exception Status

I_SI1TLS EQU I_VEC+$4A; ESSI1 Transmit last slot

;------------------------------------------------------------------------

; SCI Interrupts

;------------------------------------------------------------------------

I_SCIRD EQU I_VEC+$50

I_SCIRDE EQU I_VEC+$52

I_SCITD EQU I_VEC+$54

I_SCIIL EQU I_VEC+$56

I_SCITM EQU I_VEC+$58

; SCI Receive Data

; SCI Receive Data With Exception Status

; SCI Transmit Data

; SCI Idle Line

; SCI Timer

;------------------------------------------------------------------------

; HOST Interrupts

;------------------------------------------------------------------------

I_HRDF EQU I_VEC+$60

I_HTDE EQU I_VEC+$62

I_HC EQU I_VEC+$64

; Host Receive Data Full

; Host Transmit Data Empty

; Default Host Command

;------------------------------------------------------------------------

; INTERRUPT ENDING ADDRESS

;------------------------------------------------------------------------

I_INTEND EQU I_VEC+$FF

; last address of interrupt vector space

A-12

Index

controller iv

out of page

A

read access 2-23

wait states selection guide 2-20

write access 2-24

ac electrical characteristics 2-4

address bus 1-1

Address Trace mode 2-25, 2-27

applications iv

Page mode

read accesses 2-19

wait states selection guide 2-16

write accesses 2-19

arbitration bus timings 2-27

B

refresh access 2-24

benchmark test algorithm A-1

block diagram i

bootstrap ROM iii

Boundary Scan (JTAG Port) timing diagram 2-46

bus

DSP56300

Family Manual iv

DSP56309

block diagram i

Technical Data iv

User’s Manual iv

acquisition timings 2-28

address 1-2

control 1-1

data 1-2

E

electrical

design considerations 4-2, 4-3

external address 1-5

external data 1-5

multiplexed 1-2

non-multiplexed 1-2

release timings 2-28, 2-29

Enhanced Synchronous Serial Interface (ESSI) iii,

1-1, 1-2, 1-13, 1-14

receiver timing 2-42

transmitter timing 2-41

C

external address bus 1-5

external bus control 1-5, 1-6, 1-7

external bus synchronous timings (SRAM

access) 2-25

external clock operation 2-4

external data bus 1-5

external interrupt timing (negative

edge-triggered) 2-11

external level-sensitive fast interrupt timing 2-10

external memory access (DMA Source)

timing 2-12

clock 1-1, 1-4

external 2-4

clocks

internal 2-4

crystal oscillator circuits 2-5

D

data bus 1-1

data memory expansion iv

Data Strobe (DS) 1-2

dc electrical characteristics 2-3

DE signal 1-18

Debug Event signal (DE signal) 1-18

Debug mode

External Memory Expansion Port 2-13

external memory expansion port 1-5

F

functional groups 1-2

functional signal groups 1-1

entering 1-18

external indication 1-18

Debug support iii

description, general i

design considerations

electrical 4-2, 4-3

PLL 4-5

G

general description i

General-Purpose Input/Output (GPIO) iii, 1-2

ground 1-1, 1-3

PLL 1-3

power consumption 4-4

thermal 4-1

documentation list iv

Double Data Strobe 1-2

DRAM

Index-1

Index

memory expansion port iii

mode control 1-8

Mode select timing 2-7

multiplexed bus 1-2

multiplexed bus timings

read 2-35

H

Host Interface (HI08) iii, 1-1, 1-2, 1-9, 1-10,

1-11, 1-12

Host Port Control Register (HPCR) 1-10,

1-12

write 2-36

host port

configuration 1-9

usage considerations 1-9

Host Port Control Register (HPCR) 1-10, 1-12

Host Request

Double 1-2

Single 1-2

Host Request (HR) 1-2

N

non-multiplexed bus 1-2

non-multiplexed bus timings

read 2-33

write 2-34

O

I

off-chip memory iii

OnCE module iii

information sources iv

instruction cache iii

internal clocks 2-4

interrupt and mode control 1-1, 1-8

interrupt control 1-8

Debug request 2-47

on-chip DRAM controller iv

On-Chip Emulation (OnCE) module

interface 1-18

On-Chip Emulation module iii

on-chip memory iii

interrupt timing 2-7

external level-sensitive fast 2-10

external negative edge-triggered 2-11

synchronous from Wait state 2-11

operating mode select timing 2-11

P

J

package

Joint Test Action Group (JTAG)

interface 1-18

144-pin TQFP 3-1

196-pin MAP-BGA 3-1

MAP-BGA description 3-10, 3-11, 3-12,

3-15, 3-19

JTAG iii

JTAG Port

reset timing diagram 2-46

timing 2-46

JTAG/OnCE Interface signals

Debug Event signal (DE signal) 1-18

JTAG/OnCE port 1-1, 1-2

TQFP description 3-2, 3-3, 3-4, 3-6, 3-9

Phase-Lock Loop (PLL) 1-1, 2-6

design considerations 4-5

performance issues 4-5

PLL 1-4

Port A 1-1, 1-5, 2-13

Port B 1-1, 1-2, 1-11

K

Port C 1-1, 1-2, 1-13

keeper circuit

Port D 1-1, 1-2, 1-14

Port E 1-1

design considerations 4-3

M

power 1-1, 1-2, 1-3

power consumption

MAP-BGA 3-1

design considerations 4-4

power consumption benchmark test A-1

power management iv

power-up sequence guidelines 4-3

program memory expansion iv

program RAM iii

ball list by name 3-15

ball list by number 3-12

mechanical drawing 3-19

molded array process-ball grid drawing

(bottom) 3-11

molded array process-ball grid drawing

(top) 3-10

maximum ratings 2-1, 2-2

Index-2

Index

mechanical drawing 3-9

pin list by name 3-6

R

pin list by number 3-4

pin-out drawing (bottom) 3-3

pin-out drawing (top) 3-2

recovery from Stop state using IRQA 2-12

reset

clock signals 1-4

interrupt signals 1-8

JTAG signals 1-18

mode control 1-8

OnCE signals 1-18

PLL signals 1-4

W

Wait mode iv

World Wide Web iv

Reset timing 2-7, 2-9

synchronous 2-10

ROM, bootstrap iii

X

X-data RAM iii

Y

S

Serial Communication Interface (SCI) iii, 1-1,

1-2, 1-16

Y-data RAM iii

Asynchronous mode timing 2-38

Synchronous mode timing 2-38

signal groupings 1-1

signals 1-1

functional grouping 1-2

Single Data Strobe 1-2

SRAM

read access 2-15

support iv

write access 2-15

Stop mode iv

Stop state

recovery from 2-12

Stop timing 2-7

supply voltage 2-2

Switch mode iii

synchronous bus timings

SRAM

2 wait states 2-26

SRAM 1 wait state (BCR controlled) 2-26

synchronous interrupt from Wait state timing 2-11

synchronous Reset timing 2-10

T

target applications iv

Test Access Port (TAP) iii

timing diagram 2-46

Test Clock (TCLK) input timing diagram 2-45

thermal

design considerations 4-1

Timer

event input restrictions 2-43

Timers 1-1, 1-2, 1-17

interrupt generation 2-43

TQFP 3-1

Index-3

Ordering Information

Consult a Motorola Semiconductor sales office or authorized distributor to determine product availability and place an order.

Core

Frequency

(MHz)

Supply

Voltage

Count

Part

Package Type

Order Number

DSP56309

3.3 V I/O Thin Quad Flat Pack (TQFP)

Molded Array Process-Ball Grid Array (MAP-BGA)

144

196

100

DSP56309PV100

DSP56309VF100

HOW TO REACH US:

Information in this document is provided solely to enable system and software implementers to use

Motorola products. There are no express or implied copyright licenses granted hereunder to design

or fabricate any integrated circuits or integrated circuits based on the information in this document.

USA/EUROPE/LOCATIONS NOT LISTED:

Motorola Literature Distribution;

P.O. Box 5405, Denver, Colorado 80217

1-303-675-2140 or 1-800-441-2447

Motorola reserves the right to make changes without further notice to any products herein. Motorola

makes no warranty, representation or guarantee regarding the suitability of its products for any

particular purpose, nor does Motorola assume any liability arising out of the application or use of any

product or circuit, and specifically disclaims any and all liability, including without limitation

consequential or incidental damages. “Typical” parameters which may be provided in Motorola data

sheets and/or specifications can and do vary in different applications and actual performance may

vary over time. All operating parameters, including “Typicals” must be validated for each customer

application by customer’s technical experts. Motorola does not convey any license under its patent

rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as

components in systems intended for surgical implant into the body, or other applications intended to

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claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or

indirectly, any claim of personal injury or death associated with such unintended or unauthorized use,

even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.

JAPAN:

Motorola Japan Ltd.; SPS, Technical Information Center,

3-20-1, Minami-Azabu Minato-ku, Tokyo 106-8573 Japan

81-3-3440-3569

ASIA/PACIFIC:

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Centre, 2 Dai King Street, Tai Po Industrial Estate,

Tai Po, N.T., Hong Kong

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TECHNICAL INFORMATION CENTER:

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HOME PAGE:

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digital dna are trademarks of Motorola, Inc. All other product or service names are the property of their

respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

DSP56309/D


型号：	SPAKXC309VF100A
厂家：	NXP
描述：	24-BIT, 100MHz, OTHER DSP, PBGA196, 15 X 15 MM, 1 MM PITCH, MOLD ARRAY PROCESS, BGA-196 时钟外围集成电路
文件：	总112页 (文件大小：2288K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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