SPC5200CBV400 [NXP]
400MHz, MICROPROCESSOR, PBGA272, 27 X 27 MM, 1.27 MM PITCH, PLASTIC, BGA-272;型号: | SPC5200CBV400 |
厂家: | NXP |
描述: | 400MHz, MICROPROCESSOR, PBGA272, 27 X 27 MM, 1.27 MM PITCH, PLASTIC, BGA-272 时钟 外围集成电路 |
文件: | 总80页 (文件大小:1068K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MPC5200
Rev. 4, 01/2005
Freescale Semiconductor
Data Sheet
MPC5200 Data Sheet
Table of Contents
NOTE
1
2
3
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Electrical and Thermal Characteristics . . . . . . . . . 6
3.1 DC Electrical Characteristics . . . . . . . . . . . . . 6
3.2 Oscillator and PLL Electrical
Characteristics. . . . . . . . . . . . . . . . . . . . . . . 12
3.3 AC Electrical Characteristics . . . . . . . . . . . . 14
Package Description. . . . . . . . . . . . . . . . . . . . . . 64
4.1 Package Parameters . . . . . . . . . . . . . . . . . . 64
4.2 Mechanical Dimensions. . . . . . . . . . . . . . . . 64
4.3 Pinout Listings . . . . . . . . . . . . . . . . . . . . . . . 66
System Design Information. . . . . . . . . . . . . . . . . 71
5.1 Power UP/Down Sequencing . . . . . . . . . . . 71
5.2 System and CPU Core AVDD power
The information in this
document is subject to
change. For the latest data
on the MPC5200, visit
www.freescale.com and
proceed to the MPC5200
Product Summary Page.
4
5
1 Overview
The MPC5200 integrates a high performance MPC603e
series G2_LE core with a rich set of peripheral functions
focused on communications and systems integration.
The G2_LE core design is based on the PowerPCTM core
architecture. MPC5200 incorporates an innovative
BestComm I/O subsystem, which isolates routine
maintenance of peripheral functions from the embedded
G2_LE core. The MPC5200 contains a SDRAM/DDR
Memory Controller, a flexible External Bus Interface,
PCI Controller, USB, ATA, Ethernet, six Programmable
supply filtering . . . . . . . . . . . . . . . . . . . . . . . 73
5.3 Pull-up/Pull-down Resistor Requirements . . 73
5.4 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Ordering Information. . . . . . . . . . . . . . . . . . . . . . 79
Document Revision History. . . . . . . . . . . . . . . . . 79
6
7
2
Serial Controllers (PSC), I C, SPI, CAN, J1850, Timers,
and GPIOs.
“Definitive Data: Freescale reserves the right to change the production detail specifications
as may be required to permit improvements in the design of its products.”
© Freescale Semiconductor, Inc., 2005, 2006. All rights reserved.
Features
2 Features
Key features are shown below.
•
MPC603e series G2_LE core
— Superscalar architecture
o
— 760 MIPS at 400 MHz (-40 to +85 C)
— 16 k Instruction cache, 16 k Data cache
— Double precision FPU
— Instruction and Data MMU
— Standard and Critical interrupt capability
SDRAM / DDR Memory Interface
•
•
•
— up to 132-MHz operation
— SDRAM and DDR SDRAM support
— 256-MByte addressing range per CS, two CS available
— 32-bit data bus
— Built-in initialization and refresh
Flexible multi-function External Bus Interface
— Supports interfacing to ROM/Flash/SRAM memories or other memory mapped devices
— 8 programmable Chip Selects
— Non multiplexed data access using 8/16/32 bit databus with up to 26-bit address
— Short or Long Burst capable
— Multiplexed data access using 8/16/32 bit databus with up to 25-bit address
Peripheral Component Interconnect (PCI) Controller
— Version 2.2 PCI compatibility
— PCI initiator and target operation
— 32-bit PCI Address/Data bus
— 33- and 66-MHz operation
— PCI arbitration function
•
•
ATA Controller
— Version 4 ATA compatible external interface—IDE Disk Drive connectivity
BestComm DMA subsystem
— Intelligent virtual DMA Controller
— Dedicated DMA channels to control peripheral reception and transmission
— Local memory (SRAM 16 kBytes)
•
6 Programmable Serial Controllers (PSC), configurable for the following:
— UART or RS232 interface
MPC5200 Data Sheet, Rev. 4
2
Freescale Semiconductor
Features
2
— CODEC interface for Soft Modem, Master/Slave CODEC Mode, I S and AC97
— Full duplex SPI mode
— IrDA mode from 2400 bps to 4 Mbps
Fast Ethernet Controller (FEC)
•
•
— Supports 100Mbps IEEE 802.3 MII, 10 Mbps IEEE 802.3 MII, 10 Mbps 7-wire interface
Universal Serial Bus Controller (USB)
— USB Revision 1.1 Host
— Open Host Controller Interface (OHCI)
— Integrated USB Hub, with two ports.
2
•
•
•
Two Inter-Integrated Circuit Interfaces (I C)
Serial Peripheral Interface (SPI)
Dual CAN 2.0 A/B Controller (MSCAN)
—Freescale Scalable Controller Area Network (FSCAN) architecture
— Implementation of version 2.0A/B CAN protocol
— Standard and extended data frames
•
•
J1850 Byte Data Link Controller (BDLC)
— J1850 Class B data communication network interface compatible and ISO compatible for low
speed (<125 kbps) serial data communications in automotive applications.
— Supports 4X mode, 41.6 kbps
— In-frame response (IFR) types 0, 1, 2, and 3 supported
Systems level features
— Interrupt Controller supports four external interrupt request lines and 47 internal interrupt
sources
— GPIO/Timer functions
– Up to 56 total GPIO pins (depending on functional multiplexing selections) that support a
variety of interrupt/WakeUp capabilities.
– Eight GPIO pins with timer capability supporting input capture, output compare, and pulse
width modulation (PWM) functions
— Real-time Clock with one-second resolution
— Systems Protection (watch dog timer, bus monitor)
— Individual control of functional block clock sources
— Power management: Nap, Doze, Sleep, Deep Sleep modes
— Support of WakeUp from low power modes by different sources (GPIO, RTC, CAN)
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
3
Features
•
Test/Debug features
— JTAG (IEEE 1149.1 test access port)
— Common On-chip Processor (COP) debug port
On-board PLL and clock generation
•
Figure 1 shows a simplified MPC5200 block diagram.
MPC5200 Data Sheet, Rev. 4
4
Freescale Semiconductor
Features
MSCAN
2x
J1850
USB
2x
SPI
2
I C
2x
BestComm DMA
SRAM 16K
Ethernet
PSC
6x
Figure 1. Simplified Block Diagram—MPC5200
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
5
Electrical and Thermal Characteristics
3 Electrical and Thermal Characteristics
3.1 DC Electrical Characteristics
3.1.1 Absolute Maximum Ratings
The tables in this section describe the MPC5200 DC Electrical characteristics. Table 1 gives the absolute
maximum ratings.
1
Table 1. Absolute Maximum Ratings
Characteristic
Symbol
Min
Max
Unit
SpecID
Supply voltage - G2_LE core and peripheral logic
Supply voltage - I/O buffers
VDD_CORE
–0.3
–0.3
1.8
3.6
V
V
D1.1
D1.2
VDD_IO,
VDD_MEM_IO
Supply voltage - System APLL
Supply voltage - G2_LE APLL
Input voltage (VDD_IO)
SYS_PLL_AVDD
–0.3
–0.3
–0.3
2.1
2.1
V
V
V
V
D1.3
D1.4
D1.5
D1.6
CORE_PLL_AVDD
Vin
Vin
VDD_IO + 0.3
Input voltage (VDD_MEM_IO)
–0.3 VDD_MEM_IO
+ 0.3
Input voltage overshoot
Input voltage undershoot
Storage temperature range
N1 OTES:
Vinos
Vinus
Tstg
–
–
1.0
1.0
V
V
D1.7
D1.8
D1.9
–55
150
oC
Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed.
Stresses beyond those listed may affect device reliability or cause permanent damage.
3.1.2 Recommended Operating Conditions
Table 2 gives the recommended operating conditions.
Table 2. Recommended Operating Conditions
Characteristic
Symbol
Min1
Max(1)
Unit
SpecID
Supply voltage - G2_LE core and peripheral
logic
VDD_CORE
1.42
1.58
V
D2.1
Supply voltage - standard I/O buffers
Supply voltage - memory I/O buffers (SDR)
Supply voltage - memory I/O buffers (DDR)
Supply voltage - System APLL
VDD_IO
VDD_MEM_IOSDR
VDD_MEM_IODDR
SYS_PLL_AVDD
CORE_PLL_AVDD
Vin
3.0
3.0
2.42
1.42
1.42
0
3.6
V
V
V
V
V
V
V
D2.2
D2.3
D2.4
D2.5
D2.6
D2.7
D2.8
3.6
2.63
1.58
Supply voltage - G2_LE APLL
1.58
Input voltage - standard I/O buffers
Input voltage - memory I/O buffers (SDR)
VDD_IO
VDD_MEM_IOSDR
VinSDR
0
MPC5200 Data Sheet, Rev. 4
6
Freescale Semiconductor
Electrical and Thermal Characteristics
Table 2. Recommended Operating Conditions (continued)
Characteristic
Symbol
Min1
Max(1)
Unit
SpecID
Input voltage - memory I/O buffers (DDR)
Ambient operating temperature range2
VinDDR
TA
0
VDD_MEM_IODDR
V
D2.9
D2.10
D2.11
-40
-40
+85
oC
oC
Extended ambient operating temperature
range3
TAext
+105
Die junction operating temperature range
Tj
-40
-40
+115
+125
oC
oC
D2.12
D2.13
Extended die junction operating temperature
range
Tjext
NOTES:
1
These are recommended and tested operating conditions. Proper device operation outside these conditions is not
guaranteed.
2
3
Maximum G2_LE core operating frequency is 400 MHz
Maximum G2_LE core operating frequency is 264 MHz
3.1.3 DC Electrical Specifications
Table 3 gives the DC Electrical characteristics for the MPC5200 at recommended operating conditions
(see Table 2).
Table 3. DC Electrical Specifications
Characteristic
Input high voltage
Condition
Symbol
Min
Max
Unit
SpecID
Input type = TTL
VIH
2.0
—
V
D3.1
VDD_IO/VDD_MEM_IOSDR
Input high voltage
Input high voltage
Input high voltage
Input type = TTL
VDD_MEM_IODDR
VIH
VIH
VIH
1.7
2.0
2.0
—
—
—
V
V
V
D3.2
D3.3
D3.4
Input type = PCI
VDD_IO
Input type = SCHMITT
VDD_IO
Input high voltage
Input high voltage
Input low voltage
SYS_XTAL_IN
RTC_XTAL_IN
CVIH
CVIH
VIL
2.0
2.0
—
—
—
V
V
V
D3.5
D3.6
D3.7
Input type = TTL
0.8
VDD_IO/VDD_MEM_IOSDR
Input low voltage
Input low voltage
Input low voltage
Input type = TTL
VDD_MEM_IODDR
VIL
VIL
VIL
—
—
—
0.7
0.8
0.8
V
V
V
D3.8
D3.9
Input type = PCI
VDD_IO
Input type = SCHMITT
VDD_IO
D3.10
Input low voltage
Input low voltage
SYS_XTAL_IN
RTC_XTAL_IN
CVIL
CVIL
—
—
0.8
0.8
V
V
D3.11
D3.12
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
7
Electrical and Thermal Characteristics
Table 3. DC Electrical Specifications (continued)
Characteristic
Condition
Symbol
Min
Max
Unit
SpecID
Input leakage current
Vin = 0 or
IIN
—
+10
µA
D3.13
VDD_IO/VDD_IO_MEMSDR
1
(depending on input type )
Input leakage current
SYS_XTAL_IN
Vin = 0 or VDD_IO
IIN
IIN
—
—
40
+10
+10
109
µA
µA
µA
D3.14
D3.15
D3.16
Input leakage current
RTC_XTAL_IN
Vin = 0 or VDD_IO
Input current, pullup resistor
PULLUP
VDD_IO
Vin = 0
IINpu
Input current, pullup resistor -
memory I/O buffers
PULLUP_MEM
VDD_IO_MEMSDR
Vin = 0
IINpu
41
36
111
106
µA
µA
D3.17
D3.18
Input current, pulldown resistor
PULLDOWN
VDD_IO
IINpd
Vin = VDD_IO
Output high voltage
Output high voltage
Output low voltage
Output low voltage
IOH is driver dependent2
VDD_IO, VDD_IO_MEMSDR
VOH
VOHDDR
VOL
2.4
1.7
—
—
—
V
V
V
V
D3.19
D3.20
D3.21
D3.22
IOH is driver dependent2
VDD_IO_MEMDDR
IOL is driver dependent2
VDD_IO, VDD_IO_MEMSDR
0.4
0.4
IOL is driver dependent2
VDD_IO_MEMDDR
VOLDDR
—
DC Injection Current Per Pin3
Capacitance
ICS
Cin
-1.0
—
1.0
15
mA
pF
D3.23
D3.24
Vin = 0V, f = 1 MHz
NOTES:
1
Leakage current is measured with output drivers disabled and pull-up/pull-downs inactive.
See Table 4 for the typical drive capability of a specific signal pin based on the type of output driver associated with that pin
as listed in Table 52.
All injection current is transferred to VDD_IO/VDD_IO_MEM. An external load is required to dissipate this current to maintain
the power supply within the specified voltage range.
2
3
Total injection current for all digital input-only and all digital input/output pins must not exceed 10 mA. Exceeding this limit can
cause disruption of normal operation.
Table 4. Drive Capability of MPC5200 Output Pins
Driver Type
DRV4
DRV8
Supply Voltage
IOH
IOL
Unit SpecID
VDD_IO = 3.3V
VDD_IO = 3.3V
4
8
4
8
mA
mA
D3.25
D3.26
MPC5200 Data Sheet, Rev. 4
8
Freescale Semiconductor
Electrical and Thermal Characteristics
Table 4. Drive Capability of MPC5200 Output Pins (continued)
Driver Type
Supply Voltage
IOH
IOL
Unit SpecID
DRV8_OD
DRV16_MEM
DRV16_MEM
PCI
VDD_IO = 3.3V
VDD_IO_MEM = 3.3V
VDD_IO_MEM = 2.5V
VDD_IO = 3.3V
-
8
mA
mA
mA
mA
D3.27
D3.28
D3.29
D3.30
16
16
16
16
16
16
3.1.4 Electrostatic Discharge
CAUTION
This device contains circuitry that protects against damage due to
high-static voltage or electrical fields. However, it is advised that normal
precautions be taken to avoid application of any voltages higher than
maximum-rated voltages. Operational reliability is enhanced if unused
inputs are tied to an appropriate logic voltage level (i.e., either GND or
V
). Table 7 gives package thermal characteristics for this device.
CC
Table 5. ESD and Latch-Up Protection Characteristics
Sym
Rating
Min
Max
Unit
SpecID
VHBM Human Body Model (HBM)—JEDEC JESD22-A114-B
VMM Machine Model (MM)—JEDEC JESD22-A115
2000
200
—
—
—
V
V
V
D4.1
D4.2
D4.3
D4.4
VCDM Charge Device Model (CDM)—JEDEC JESD22-C101
500
ILAT Latch-up Current at TA=85oC
positive
negative
+100
-100
—
—
mA
mA
ILAT Latch-up Current at TA=27oC
D4.5
positive
negative
+200
-200
3.1.5 Power Dissipation
Power dissipation of the MPC5200 is caused by 3 different components: the dissipation of the internal or
core digital logic (supplied by VDD_CORE), the dissipation of the analog circuitry (supplied by
SYS_PLL_AVDD and CORE_PLL_AVDD) and the dissipation of the IO logic (supplied by
VDD_IO_MEM and VDD_IO). Table 6 details typical measured core and analog power dissipation
figures for a range of operating modes. However, the dissipation due to the switching of the IO pins can
not be given in general, but must be calculated by the user for each application case using the following
formula
2
P
= P
+
N × C × VDD_IO × f
IO
IOint
∑
M
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
9
Electrical and Thermal Characteristics
where N is the number of output pins switching in a group M, C is the capacitance per pin, VDD_IO is the
IO voltage swing, f is the switching frequency and PIOint is the power consumed by the unloaded IO stage.
The total power consumption of the MPC5200 processor must not exceed the value, which would cause
the maximum junction temperature to be exceeded.
P
= P
+ P
+ P
total
core
analog
IO
Table 6. Power Dissipation
Core Power Supply (VDD_CORE)
SYS_XTAL/XLB/PCI/IPG/CORE (MHz)
SpecID
Mode
33/66/33/33/264
Typ
33/132/66/132/396
Typ
Unit
Notes
1 2
Operational
Doze
727.5
—
1080
600
mW
mW
mW
mW
mW
,
D5.1
D5.2
D5.3
D5.4
D5.5
1 3
,
1 4
Nap
—
225
,
1 5
Sleep
—
225
,
1 6
Deep-Sleep
52.5
52.5
,
PLL Power Supplies (SYS_PLL_AVDD, CORE_PLL_AVDD)
Mode
Typ
Unit
Notes
7
Typical
2
mW
D5.6
D5.7
Unloaded I/O Power Supplies (VDD_IO, VDD_MEM_IO8)
Mode
Typ
Unit
Notes
9
Typical
33
mW
N1 OTES:
Typical core power is measured at VDD_CORE = 1.5 V, Tj = 25 C
Operational power is measured while running an entirely cache-resident program with floating-point
multiplication instructions in parallel with a continuous PCI transaction via BestComm.
Doze power is measured with the G2_LE core in Doze mode, the system oscillator, System PLL and Core PLL
are active, all other system modules are inactive
Nap power is measured with the G2_LE core in Nap mode, the stem oscillator, System PLL and Core PLL are
active, all other system modules are inactive
Sleep power is measured with the G2_LE core in Sleep mode, the stem oscillator, System PLL and Core PLL
are active, all other system modules are inactive
Deep-Sleep power is measured with the G2_LE core in Sleep mode, the stem oscillator, System PLL, Core PLL
and all other system modules are inactive
Typical PLL power is measured at SYS_PLL_AVDD = CORE_PLL_AVDD = 1.5 V, Tj = 25 C
IO power figures given in the table represent the worst case scenario. For the mem_io rail connected to 2.5V the
IO power is expected to be lower and bounded by the worst case with VDD_MEM_IO connected to 3.3V.
Unloaded typical I/O power is measured in Deep-Sleep mode at VDD_IO = VDD_MEM_IOSDR= 3.3 V, Tj = 25 C
2
3
4
5
6
7
8
9
MPC5200 Data Sheet, Rev. 4
10
Freescale Semiconductor
Electrical and Thermal Characteristics
3.1.6 Thermal Characteristics
Table 7. Thermal Resistance Data
Rating
Value
Unit
Notes
SpecID
1,2
Junction to Ambient
Natural Convection
Single layer board
(1s)
RθJA
30
°C/W
D6.1
1,3
1,3
1,3
Junction to Ambient
Natural Convection
Four layer board (2s2p)
RθJMA
RθJMA
RθJMA
22
24
19
°C/W
°C/W
°C/W
D6.2
D6.3
D6.4
Junction to Ambient (@200 Single layer board
ft/min) (1s)
Junction to Ambient (@200 Four layer board
ft/min)
(2s2p)
4
5
6
Junction to Board
Junction to Case
Junction to Package Top
N1 OTES:
RθJB
RθJC
ΨJT
14
8
°C/W
°C/W
°C/W
D6.5
D6.6
D6.7
Natural Convection
2
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting
site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and
board thermal resistance.
2
3
4
Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL
SPEC-883 Method 1012.1).
Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter
is written as Psi-JT.
5
6
3.1.7 Heat Dissipation
An estimation of the chip-junction temperature, T , can be obtained from the following equation:
J
T = T +(R
× P )
Eqn. 1
J
A
θJA
D
where:
T
= ambient temperature for the package (°C)
A
R
= junction to ambient thermal resistance (°C/W)
θJA
P
= power dissipation in package (W)
D
The junction to ambient thermal resistance is an industry standard value, which provides a quick and easy
estimation of thermal performance. Unfortunately, there are two values in common usage: the value
determined on a single layer board, and the value obtained on a board with two planes. For packages such
as the PBGA, these values can be different by a factor of two. Which value is correct depends on the power
dissipated by other components on the board. The value obtained on a single layer board is appropriate for
the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually
appropriate if the board has low power dissipation and the components are well separated.
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
11
Electrical and Thermal Characteristics
Historically, the thermal resistance has frequently been expressed as the sum of a junction to case thermal
resistance and a case to ambient thermal resistance:
R
= R
+R
θCA
Eqn. 2
θJA
θJC
where:
R
R
R
= junction to ambient thermal resistance (°C/W)
= junction to case thermal resistance (°C/W)
= case to ambient thermal resistance (°C/W)
θJA
θJC
θCA
R
is device related and cannot be influenced by the user. The user controls the thermal environment to
θJC
change the case to ambient thermal resistance, R
. For instance, the user can change the air flow around
θCA
the device, add a heat sink, change the mounting arrangement on printed circuit board, or change the
thermal dissipation on the printed circuit board surrounding the device. This description is most useful for
ceramic packages with heat sinks where some 90% of the heat flow is through the case to the heat sink to
ambient. For most packages, a better model is required.
A more accurate thermal model can be constructed from the junction to board thermal resistance and the
1-3
junction to case thermal resistance . The junction to case covers the situation where a heat sink will be
used or where a substantial amount of heat is dissipated from the top of the package. The junction to board
thermal resistance describes the thermal performance when most of the heat is conducted to the printed
circuit board. This model can be used for either hand estimations or for a computational fluid dynamics
(CFD) thermal model.
To determine the junction temperature of the device in the application after prototypes are available, the
Thermal Characterization Parameter (Ψ ) can be used to determine the junction temperature with a
JT
measurement of the temperature at the top center of the package case using the following equation:
T = T +(Ψ × P )
Eqn. 3
J
T
JT
D
where:
T
= thermocouple temperature on top of package (°C)
T
Ψ
= thermal characterization parameter (°C/W)
JT
P
= power dissipation in package (W)
D
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned, so
that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over approximately one mm of wire extending from the junction. The
thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling
effects of the thermocouple wire.
3.2 Oscillator and PLL Electrical Characteristics
The MPC5200 System requires a system-level clock input SYS_XTAL. This clock input may be driven
directly from an external oscillator or with a crystal using the internal oscillator.
MPC5200 Data Sheet, Rev. 4
12
Freescale Semiconductor
Electrical and Thermal Characteristics
There is a separate oscillator for the independent Real-Time Clock (RTC) system.
The MPC5200 clock generation uses two phase locked loop (PLL) blocks.
•
The system PLL (SYS_PLL) takes an external reference frequency and generates the internal
system clock. The system clock frequency is determined by the external reference frequency and
the settings of the SYS_PLL configuration.
•
The G2_LE core PLL (CORE_PLL) generates a master clock for all of the CPU circuitry. The
G2_LE core clock frequency is determined by the system clock frequency and the settings of the
CORE_PLL configuration.
3.2.1 System Oscillator Electrical Characteristics
Table 8. System Oscillator Electrical Characteristics
Characteristic
Symbol
Notes
Min
Typical
Max
Unit
SpecID
SYS_XTAL frequency
Oscillator start-up time
fsys_xtal
tup_osc
15.6
—
33.3
—
35.0
100
MHz
O1.1
O1.2
µs
3.2.2 RTC Oscillator Electrical Characteristics
Table 9. RTC Oscillator Electrical Characteristics
Characteristic
Symbol
Notes
Min
Typical
Max
Unit
SpecID
RTC_XTAL frequency
frtc_xtal
—
32.768
—
kHz
O2.1
3.2.3 System PLL Electrical Characteristics
Table 10. System PLL Specifications
Characteristic
Symbol
Notes
Min
Typical
Max
Unit
SpecID
1
SYS_XTAL frequency
SYS_XTAL cycle time
SYS_XTAL clock input jitter
System VCO frequency
System PLL relock time
N1 OTES:
fsys_xtal
Tsys_xtal
tjitter
15.6
66.6
—
33.3
30.0
—
35.0
28.5
150
800
100
MHz
ns
O3.1
O3.2
O3.3
O3.4
O3.5
(1)
2
ps
(1)
3
fVCOsys
tlock
250
—
533
—
MHz
µs
The SYS_XTAL frequency and PLL Configuration bits must be chosen such that the resulting system frequency,
CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating
frequencies.
This represents total input jitter - short term and long term combined - and is guaranteed by design. Two different
types of jitter can exist on the input to core_sysclk, systemic and true random jitter. True random jitter is rejected, but
the PLL. Systemic jitter will be passed into and through the PLL to the internal clock circuitry, directly reducing the
operating frequency.
Relock time is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required
for the PLL lock after a stable Vdd and core_sysclk are reached during the power-on reset sequence. This
specification also applies when the PLL has been disabled and subsequently re-enabled during sleep modes.
2
3
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
13
Electrical and Thermal Characteristics
3.2.4 G2_LE Core PLL Electrical Characteristics
The internal clocking of the G2_LE core is generated from and synchronized to the system clock by means
of a voltage-controlled core PLL.
Table 11. G2_LE PLL Specifications
Characteristic
G2_LE frequency
Symbol
Notes
Min
Typical
Max
Unit
SpecID
1
fcore
tcore
50
2.85
400
25
—
—
—
—
—
—
—
550
40.0
1200
367
MHz
ns
O4.1
O4.2
O4.3
O4.4
O4.5
O4.6
O4.7
(1)
(1)
G2_LE cycle time
G2_LE VCO frequency
G2_LE input clock frequency
G2_LE input clock cycle time
G2_LE input clock jitter
G2_LE PLL relock time
N1 OTES:
fVCOcore
fXLB_CLK
tXLB_CLK
tjitter
MHz
MHz
ns
2.73
—
50.0
150
2
3
ps
tlock
—
100
µs
The XLB_CLK frequency and G2_LE PLL Configuration bits must be chosen such that the resulting system
frequencies, CPU (core) frequency, and G2_LE PLL (VCO) frequency do not exceed their respective maximum or
minimum operating frequencies.
This represents total input jitter - short term and long term combined - and is guaranteed by design. Two different
types of jitter can exist on the input to core_sysclk, systemic and true random jitter. True random jitter is rejected, but
the PLL. Systemic jitter will be passed into and through the PLL to the internal clock circuitry, directly reducing the
operating frequency.
Relock time is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required
for the PLL lock after a stable Vdd and core_sysclk are reached during the power-on reset sequence. This
specification also applies when the PLL has been disabled and subsequently re-enabled during sleep modes.
2
3
3.3 AC Electrical Characteristics
Hyperlinks to the indicated timing specification sections are provided below.
•
•
•
•
•
•
•
•
•
AC Operating Frequency Data
•
•
•
•
•
•
•
•
USB
Clock AC Specifications
Resets
SPI
MSCAN
2
External Interrupts
SDRAM
I C
J1850
PCI
PSC
Local Plus Bus
ATA
GPIOs and Timers
IEEE 1149.1 (JTAG) AC Specifications
Ethernet
AC Test Timing Conditions:
Unless otherwise noted, all test conditions are as follows:
MPC5200 Data Sheet, Rev. 4
14
Freescale Semiconductor
Electrical and Thermal Characteristics
o
•
•
•
TA = -40 to 85 C
o
Tj = -40 to 115 C
VDD_CORE = 1.42 to 1.58 V
VDD_IO = 3.0 to 3.6 V
•
•
Input conditions:
All Inputs: tr, tf <= 1 ns
Output Loading:
All Outputs: 50 pF
3.3.1 AC Operating Frequency Data
Table 12 provides the operating frequency information for the MPC5200.
Table 12. Clock Frequencies
Min
Max
Units
SpecID
1
2
3
4
5
6
G2_LE Processor Core
SDRAM Clock
—
—
400
133
133
133
66
MHz
MHz
MHz
MHz
MHz
MHz
A1.1
A1.2
A1.3
A1.4
A1.5
A1.6
XL Bus Clock
—
IP Bus Clock
—
PCI / Local Plus Bus Clock
PLL Input Range
—
15.6
35
3.3.2 Clock AC Specifications
t
CYCLE
t
t
t
t
DUTY
DUTY
FALL
RISE
CV
IH
V
V
V
M
SYSCLK
M
M
CV
IL
Figure 2. Timing Diagram—SYS_XTAL_IN
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
15
Electrical and Thermal Characteristics
Table 13. SYS_XTAL_IN Timing
Description
Sym
Min
Max
Units SpecID
tCYCLE
tRISE
tFALL
tDUTY
CVIH
CVIL
SYS_XTAL_IN cycle time.1
SYS_XTAL_IN rise time.
SYS_XTAL_IN fall time.
28.6
—
64.1
5.0
5.0
60.0
—
ns
ns
ns
%
V
A2.1
A2.2
A2.3
A2.4
A2.5
A2.6
—
SYS_XTAL_IN duty cycle (measured at VM).2
40.0
2.0
—
SYS_XTAL_IN input voltage high
SYS_XTAL_IN input voltage low
0.8
V
N1 OTES:
CAUTION—The SYS_XTAL_IN frequency and system PLL_CFG[0-6] settings must be chosen such that the
resulting system frequencies do not exceed their respective maximum or minimum operating frequencies. See the
MPC5200 User Manual [1].
SYS_XTAL_IN duty cycle is measured at VM.
2
3.3.3 Resets
The MPC5200 has three reset pins:
•
•
•
PORRESET - Power on Reset
HRESET - Hard Reset
SRESET - Software Reset
These signals are asynchronous I/O signals and can be asserted at any time. The input side uses a Schmitt
trigger and requires the same input characteristics as other MPC5200 inputs, as specified in the DC
Electrical Specifications section. Table 14 specifies the pulse widths of the Reset inputs.
Table 14. Reset Pulse Width
Max Pulse
Width
Name
Description
Min Pulse Width
Reference Clock
SpecID
PORRESET
HRESET
Power On Reset
Hardware Reset
Software Reset
tVDD_stable+tup_osc+tlock
4 clock cycles
—
—
—
SYS_XTAL_IN
SYS_XTAL_IN
SYS_XTAL_IN
A3.1
A3.2
A3.3
SRESET
4 clock cycles
Notes:
1. For PORRESET the value of the minimum pulse width reflects the power on sequence. If PORRESET is asserted afterwards
its minimum pulse width equals the minimum given for HRESET related to the same reference clock.
2. The tVDD_stable describes the time which is needed to get all power supplies stable.
3. For tlock, refer to the Oscillator/PLL section of this specification for further details.
4. For tup_osc, refer to the Oscillator/PLL section of this specification for further details.
5. Following the deassertion of PORRESET, HRESET and SRESET remain low for 4096 reference clock cycles.
6. The deassertion of HRESET for at least the minimum pulse width forces the internal resets to be active for an additional 4096
clock cycles.
NOTE
As long as VDD is not stable the HRESET output is not stable.
MPC5200 Data Sheet, Rev. 4
16
Freescale Semiconductor
Electrical and Thermal Characteristics
Table 15. Reset Rise / Fall Timing
Min
Description
Max
Unit
SpecID
PORRESET fall time
PORRESET rise time
HRESET fall time
HRESET rise time
SRESET fall time
SRESET rise time
—
—
—
—
—
—
1
1
1
1
1
1
ms
ms
ms
ms
ms
ms
A3.4
A3.5
A3.6
A3.7
A3.8
A3.9
For additional information, see the MPC5200 User Manual [1].
NOTE
Make sure that the PORRESET does not carry any glitches. The MPC5200
has no filter to prevent them from getting into the chip.
NOTE
HRESET and SRESET must have a monotonous rise time.
3.3.3.1 Reset Configuration Word
During reset (HRESET and PORRESET) the Reset Configuration Word is cached in the related Reset
Configuration Word Register with each rising edge of the SYS_XTAL signal. If both resets (HRESET and
PORRESET) are inactive (high), the contents of this register get locked after two further SYS_XTAL
cycles (see Figure 3).
4096 clocks
2 clocks
SYS_XTAL
PORRESET
HRESET
RST_CFG_WRD
sample
sample
sample
sample
sample
sample
sample
sample
sample
sample
sample
sample
LOCK
Figure 3. Reset Configuration Word Locking
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
17
Electrical and Thermal Characteristics
NOTE
Beware of changing the values on the pins of the reset configuration word
after the deassertion of PORRESET. This may cause problems because it
may change the internal clock ratios and so extend the PLL locking process.
3.3.4 External Interrupts
The MPC5200 provides three different kinds of external interrupts:
•
•
•
Four IRQ interrupts
Eight GPIO interrupts with simple interrupt capability (not available in power-down mode)
Eight WakeUp interrupts (special GPIO pins)
The propagation of these three kinds of interrupts to the core is shown in the following graphic:
IRQ0
cint
int
core_cint
core_int
Encoder
8
8
8 GPIOs
8 GPIOs
IRQ1
GPIO Std
GPIO WakeUp
G2_LE Core
Grouper
Encoder
IRQ2
PIs
Main Interrupt
Controller
IRQ3
Notes:
1. PIs = Programmable Inputs
2. Grouper and Encoder functions imply programmability in software
Figure 4. External interrupt scheme
Due to synchronization, prioritization, and mapping of external interrupt sources, the propagation of
external interrupts to the core processor is delayed by several IP_CLK clock cycles. The following table
specifies the interrupt latencies in IP_CLK cycles. The IP_CLK frequency is programmable in the Clock
Distribution Module (see Note Table 16).
Table 16. External interrupt latencies
Interrupt Type
Pin Name
Clock Cycles
Reference Clock
Core Interrupt
SpecID
Interrupt Requests
IRQ0
IRQ0
IRQ1
IRQ2
10
10
10
10
10
IP_CLK
IP_CLK
IP_CLK
IP_CLK
IP_CLK
critical (cint)
normal (int)
normal (int)
normal (int)
normal (int)
A4.1
A4.2
A4.3
A4.5
A4.6
IRQ3
MPC5200 Data Sheet, Rev. 4
18
Freescale Semiconductor
Electrical and Thermal Characteristics
Table 16. External interrupt latencies (continued)
Interrupt Type
Pin Name
Clock Cycles
Reference Clock
Core Interrupt
SpecID
Standard GPIO Interrupts
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
IP_CLK
IP_CLK
IP_CLK
IP_CLK
IP_CLK
IP_CLK
IP_CLK
IP_CLK
IP_CLK
IP_CLK
IP_CLK
IP_CLK
IP_CLK
IP_CLK
IP_CLK
normal (int)
normal (int)
normal (int)
normal (int)
normal (int)
normal (int)
normal (int)
normal (int)
normal (int)
normal (int)
normal (int)
normal (int)
normal (int)
normal (int)
normal (int)
A4.7
A4.8
GPIO_PSC3_4
GPIO_PSC3_5
GPIO_PSC3_8
A4.9
GPIO_USB_9
GPIO_ETHI_4
GPIO_ETHI_5
GPIO_ETHI_6
GPIO_ETHI_7
GPIO_PSC1_4
GPIO_PSC2_4
GPIO_PSC3_9
GPIO_ETHI_8
GPIO_IRDA_0
DGP_IN0
A4.10
A4.11
A4.12
A4.13
A4.14
A4.15
A4.16
A4.17
A4.18
A4.19
A4.20
A4.21
GPIO WakeUp Interrupts
DGP_IN1
Notes:
1) The frequency of IP_CLK depends on register settings in Clock Distribution Module. See the MPC5200 User Manual [1].
2) The interrupt latency descriptions in the table above are related to non competitive, non masked but enabled external
interrupt sources. Take care of interrupt prioritization which may increase the latencies.
Since all external interrupt signals are synchronized into the internal processor bus clock domain, each of
these signals has to exceed a minimum pulse width of more than one IP_CLK cycle.
Table 17. Minimum pulse width for external interrupts to be recognized
Name
Min Pulse Width
Max Pulse Width
Reference Clock
SpecID
All external interrupts (IRQs, GPIOs)
> 1 clock cycle
—
IP_CLK
A4.22
NOTES:
1) The frequency of the IP_CLK depends on the register settings in Clock Distribution Module. See the MPC5200 User Manual
[1] for further information.
2) If the same interrupt occurs a second time while its interrupt service routine has not cleared the former one, the second
interrupt will not be recognized at all.
Besides synchronization, prioritization, and mapping the latency of an external interrupt to the start of its
associated interrupt service routine also depends on the following conditions: To get a minimum interrupt
service response time, it is recommended to enable the instruction cache and set up the maximum core
clock, XL bus, and IP bus frequencies (depending on board design and programming). In addition, it is
advisable to execute an interrupt handler, which has been implemented in assembly code.
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
19
Electrical and Thermal Characteristics
3.3.5 SDRAM
3.3.5.1 Memory Interface Timing-Standard SDRAM Read Command
Table 18. Standard SDRAM Memory Read Timing
Sym
tmem_clk MEM_CLK period
tvalid Control Signals, Address and MBA Valid after
Description
Min
Max
Units SpecID
7.5
—
—
ns
ns
A5.1
A5.2
tmem_clk*0.5+0.4
rising edge of MEM_CLK
thold
Control Signals, Address and MBA Hold after
rising edge of MEM_CLK
tmem_clk*0.5
—
ns
A5.3
DMvalid DQM valid after rising edge of MEM_CLK
DMhold DQM hold after rising edge of MEM_CLK
datasetup MDQ setup to rising edge of MEM_CLK
datahold MDQ hold after rising edge of MEM_CLK
—
tmem_clk*0.25+0.4
ns
ns
ns
ns
A5.4
A5.5
A5.6
A5.7
tmem_clk*0.25-0.7
—
0.3
—
—
0.2
MEM_CLK
tvalid
thold
Control Signals
Active
NOP
READ
NOP
NOP
NOP
NOP
NOP
DMvalid
DMhold
DQM (Data Mask)
datasetup
datahold
MDQ (Data)
tvalid
thold
Row
Column
MA (Address)
tvalid
thold
MBA (Bank Selects)
NOTE: Control Signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN
Figure 5. Timing Diagram—Standard SDRAM Memory Read Timing
3.3.5.2 Memory Interface Timing-Standard SDRAM Write Command
In Standard SDRAM, all signals are activated on the Mem_clk from the Memory Controller and captured
on the Mem_clk clock at the memory device.
MPC5200 Data Sheet, Rev. 4
20
Freescale Semiconductor
Electrical and Thermal Characteristics
Table 19. Standard SDRAM Write Timing
Sym
Description
Min
Max
Units SpecID
tmem_clk
tvalid
MEM_CLK period
7.5
—
—
ns
ns
A5.8
A5.9
Control Signals, Address and MBA Valid
after rising edge of MEM_CLK
tmem_clk*0.5+0.4
thold
Control Signals, Address and MBA Hold after
rising edge of MEM_CLK
tmem_clk*0.5
—
ns
A5.10
DMvalid
DMhold
datavalid
datahold
DQM valid after rising edge of MEM_CLK
DQM hold after rising edge of Mem_clk
MDQ valid after rising edge of MEM_CLK
MDQ hold after rising edge of MEM_CLK
—
tmem_clk*0.25+0.4
ns
ns
ns
ns
A5.11
A5.12
A5.13
A5.14
tmem_clk*0.25-0.7
—
—
tmem_clk*0.75+0.4
—
tmem_clk*0.75-0.7
MEM_CLK
tvalid
thold
Active
NOP WRITE
NOP
NOP
NOP
NOP
NOP
Control Signals
DMhold
DMvalid
DQM (Data Mask)
datavalid
datahold
MDQ (Data)
tvalid
thold
Row
Column
MA (Address)
tvalid
thold
MBA (Bank Selects)
NOTE: Control Signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN
Figure 6. Timing Diagram—Standard SDRAM Memory Write Timing
3.3.5.3 Memory Interface Timing-DDR SDRAM Read Command
The SDRAM Memory Controller uses an internally skewed clock for reading DDR memory. The
programmable bits in the Reset Configuration Register used to account for unknown board delays are in
the CDM module. The internal read clock can be delayed up to 3 ns under worst operating conditions in
32 increments of 95 ps, (1.4 ns in 45 ps increments under best case operating conditions) by programming
the CDM Reset Configuration Register tap delay bits. Note: These bits in the CDM Reset Configuration
register are not ‘reset configured’ but have a hard coded reset value and are writable during operation.
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
21
Electrical and Thermal Characteristics
Table 20. DDR SDRAM Memory Read Timing
Sym
Description
MEM_CLK period
Min
Max
Units SpecID
tmem_clk
tvalid
7.5
—
—
ns
ns
A5.15
A5.16
Control Signals, Address and MBA
valid after rising edge of MEM_CLK
tmem_clk*0.5+0.4
thold
Control Signals, Address and MBA
hold after rising edge of MEM_CLK
tmem_clk*0.5
—
ns
A5.17
tdata_sample_max Read Data sample window
tdata_sample_min Read Data sample window
N1 OTES:
—
4.591
—
ns
ns
A5.18
A5.19
1.552
Calculated with maximum number of Tap delay, 31 Tap delay are selected.
Calculated with minimum number of Tap delay, 0 Tap delay are selected.
2
MPC5200 Data Sheet, Rev. 4
22
Freescale Semiconductor
Electrical and Thermal Characteristics
MEM_CLK
MEM_CLK
tvalid
thold
Active
NOP
READ
NOP
NOP
NOP
NOP
NOP
Control Signals
MDQS (Data Strobe)
tdata_valid_min
tdata_valid_max
MDQ (Data)
Sample
position
A
tdata_sample_min
tdata_sample_max
Read Data
Sample Window
MDQS (Data Strobe)
MDQ (Data)
tdata_valid_min
tdata_valid_max
Sample
position
0.5 * MEM_CLK
B
tdata_sample_min
tdata_sample_max
Read Data
Sample Window
tvalid
thold
MA (Address)
Row
Column
tvalid
thold
MBA (Bank Selects)
Sample position A: data are sampled on the expected edge of MEM_CLK, the MDQS signal indicate the valid data
Sample position B: data are sampled on a later edge of MEM_CLK, SDRAM controller is waiting for the vaild MDQS signal
NOTE: Control Signals signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN
Figure 7. Timing Diagram—DDR SDRAM Memory Read Timing
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
23
Electrical and Thermal Characteristics
8.34
delay [ns]
tdata_valid_max
Possible sample
time over PVT for one
selected Tap delay
Memory Data valid window
4.59
tdata_sample_min
tdata_sample_min
tdata_valid_min
Working Tap Delay range
for sample position A
Working Tap Delay range
for sample position B
1.55
0
31
selected Tap delay
Tap delay number
Figure 8. Read Data sample window depend on the number of Tap delay
The position of the t
window is depend on the clock / data flight time on the board. The MDQS
data_valid
signal indicate if the read data are valid. If the controller is not able to detect a valid MDQS signal on the
sample time (sample position A) then the controller will look for valid MDQS / data on the next edge of
the MEM_CLK signal (sample position B). Depend on the board travel time, different working tap delay
configurations are possible. For a fast connection the data will be sampled with the next edge of
MEM_CLK, this shows Figure 8, sample position A. With a longer connection maybe two sample
positions are possible. Figure 8 shows a example with two working sample position (A and B). With a
bigger board delay only sample position B will be possible.
The equation below shows how to calculate the upper and lower limit. The right Tap delay number is
selected, when the possible max and min sample timing is within the memory data valid window.
•
•
t
t
= max((1.55 + TapNum * 0.095), (1.74 + TapNum * 0.045))
= min((1.55 + TapNum * 0.095), (1.74 + TapNum * 0.045))
data_sample_max
data_sample_min
MPC5200 Data Sheet, Rev. 4
24
Freescale Semiconductor
Electrical and Thermal Characteristics
3.3.5.4 Memory Interface Timing-DDR SDRAM Write Command
Table 21. DDR SDRAM Memory Write Timing
Sym
Description
Min
Max
Units SpecID
tmem_clk
tDQSS
MEM_CLK period
7.5
—
—
ns
ns
A5.20
A5.21
Delay from write command to first
rising edge of MDQS
tmem_clk+0.4
MEM_CLK
MEM_CLK
Write
Write
Write
Write
Control Signals
MDQS (Data Strobe)
MDQ (Data)
tdqss
NOTE: Control Signals signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN
Figure 9. DDR SDRAM Memory Write Timing
3.3.6 PCI
The PCI interface on the MPC5200 is designed to PCI Version 2.2 and supports 33-MHz and 66-MHz PCI
operations. See the PCI Local Bus Specification [4]; the component section specifies the electrical and
timing parameters for PCI components with the intent that components connect directly together whether
on the planar or an expansion board, without any external buffers or other “glue logic.” Parameters apply
at the package pins, not at expansion board edge connectors.
The MPC5200 is always the source of the PCI CLK. The clock waveform must be delivered to each
33-MHz or 66-MHz PCI component in the system. Figure 10 shows the clock waveform and required
measurement points for 3.3 V signaling environments. Table 22 summarizes the clock specifications.
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
25
Electrical and Thermal Characteristics
T
cyc
T
T
low
high
0.6Vcc
0.5Vcc
0.4Vcc, p-to-p
(minimum)
0.4Vcc
0.3Vcc
PCI CLK
0.2Vcc
Figure 10. PCI CLK Waveform
Table 22. PCI CLK Specifications
66 MHz
33 MHz
Sym
Description
Units Notes
SpecID
Min
Max
Min
Max
Tcyc
Thigh
tlow
-
PCI CLK Cycle Time
PCI CLK High Time
PCI CLK Low Time
PCI CLK Slew Rate
15
6
30
30
11
ns
ns
1,3
A6.1
A6.2
A6.3
A6.4
6
1.5
4
1
4
V/ns
2
NOTES:
1. In general, all 66-MHz PCI components must work with any clock frequency up to 66 MHz. CLK requirements vary
depending upon whether the clock frequency is above 33 MHz.
2. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum
peak-to-peak portion of the clock waveform as shown in Figure 10.
3. The minimum clock period must not be violated for any single clock cycle, i.e., accounting for all system jitter.
MPC5200 Data Sheet, Rev. 4
26
Freescale Semiconductor
Electrical and Thermal Characteristics
Table 23. PCI Timing Parameters
66 MHz 33 MHz
Sym
Description
Units
Notes
SpecID
Min
Max
Min
Max
Tval
CLK to Signal Valid Delay - bused
signals
2
2
2
6
2
2
2
11
ns
ns
1,2,3
1,2,3
A6.5
A6.6
T
val(ptp) CLK to Signal Valid Delay - point
6
12
28
to point
Ton
Toff
Tsu
Float to Active Delay
Active to Float Delay
ns
ns
ns
1
1
A6.7
A6.8
A6.9
14
Input Setup Time to CLK - bused
signals
3
5
0
7
10,12
0
3,4
Tsu(ptp) Input Setup Time to CLK - point
to point
ns
ns
3,4
4
A6.10
A6.11
Th
Input Hold Time from CLK
NOTES:
1. See the timing measurement conditions in the PCI Local Bus Specification [4]. It is important that all driven signal transitions
drive to their Voh or Vol level within one Tcyc.
2. Minimum times are measured at the package pin with the load circuit, and maximum times are measured with the load circuit
as shown in the PCI Local Bus Specification [4].
3. REQ# and GNT# are point-to-point signals and have different input setup times than do bused signals. GNT# and REQ#
have a setup of 5 ns at 66 MHz. All other signals are bused.
4. See the timing measurement conditions in the PCI Local Bus Specification [4].
For Measurement and Test Conditions, see the PCI Local Bus Specification [4].
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
27
Electrical and Thermal Characteristics
3.3.7 Local Plus Bus
The Local Plus Bus is the external bus interface of the MPC5200. Maximum eight configurable
Chip-selects are provided. There are two main modes of operation: non-MUXed (Legacy and Burst) and
MUXED. The reference clock is the PCI CLK. The maximum bus frequency is 66 MHz.
Definition of Acronyms and Terms:
WS = Wait State
DC = Dead Cycle
LB = Long Burst
DS = Data size in Byte
tPCIck = PCI clock period
tIPBIck = IPBI clock period
tPCIck
PCI CLK
tIPBIck
IPBI CLK
Figure 11. Timing Diagram—IPBI and PCI clock (example ratio: 4:1)
3.3.7.1 Non-MUXed Mode
Table 24. Non-MUXed Mode Timing
Sym
Description
Min
Max
Units Notes SpecID
tCSA PCI CLK to CS assertion
tCSN PCI CLK to CS negation
-
1.8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
A7.1
A7.2
-
1.8
t1
t2
t3
CS pulse width
(2+WS)*tPCIck
(2+WS)*tPCIck
1
2
A7.3
ADDR valid before CS assertion
ADDR hold after CS negation
OE assertion before CS assertion
OE negation before CS negation
RW valid before CS assertion
RW hold after CS negation
tIPBIck
tIPBIck
-
tPCIck
A7.4
-
A7.5
t4
0.4
A7.6
t5
-
0.4
A7.7
t6
tPCIck
tIPBIck
tIPBIck
tIPBIck
2.8
-
A7.8
t7
-
A7.9
t8
DATA output valid before CS assertion
DATA output hold after CS negation
DATA input setup before CS negation
DATA input hold after CS negation
ACK assertion after CS assertion
ACK negation after CS negation
-
A7.10
A7.11
A7.12
A7.13
A7.14
A7.15
t9
-
t10
t11
t12
t13
-
0
(DC+1)*tPCIck
tPCIck
-
-
3
3
tPCIck
MPC5200 Data Sheet, Rev. 4
28
Freescale Semiconductor
Electrical and Thermal Characteristics
Table 24. Non-MUXed Mode Timing (continued)
Sym
Description
Min
Max
Units Notes SpecID
t14
t15
t16
t17
TS assertion before CS assertion
TS pulse width
-
0.8
ns
ns
ns
ns
4
4
5
5
A7.16
A7.17
A7.18
A7.19
tPCIck
tIPBIck
tIPBIck
tPCIck
TSIZ valid before CS assertion
TSIZ hold after CS negation
-
-
NOTES:
1. ACK can shorten the CS pulse width.
Wait States (WS) can be programmed in the Chip Select X Register, Bit field WaitP and WaitX. It can be specified from
0 - 65535.
2. In Large Flash and MOST Graphics mode the shared PCI/ATA pins, used as address lines, are released at the same moment
as the CS. This can cause that the address is changing earlier as CS is deasserted.
3. ACK is input and can be used to shorten the CS pulse width.
4. Only available in Large Flash and MOST Graphics mode.
5. Only available in MOST Graphics mode.
t1
CS[x]
t2
t3
ADDR
t5
t4
OE
R/W
t6
t7
t8
t9
DATA (wr)
t10
t11
t13
DATA (rd)
ACK
t12
t14
t15
TS
t17
TSIZ[1:2]
t16
Figure 12. Timing Diagram—Non-MUXed Mode
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
29
Electrical and Thermal Characteristics
3.3.7.2 Burst Mode
Table 25. Burst Mode Timing
Min
Sym
Description
Max
Units Notes SpecID
tCSA PCI CLK to CS assertion
tCSN PCI CLK to CS negation
-
-
1.8
1.8
ns
ns
ns
A7.20
A7.21
A7.22
t1
CS pulse width
(1+WS+4LB*2*(32/DS))* (1+WS+4LB*2*(32/DS))
1,2
tPCIck
tIPBIck
-
*tPCIck
t2
t3
t4
t5
t6
t7
t8
ADDR valid before CS assertion
ADDR hold after CS negation
OE assertion before CS assertion
OE negation before CS negation
RW valid before CS assertion
RW hold after CS negation
tPCIck
ns
ns
ns
ns
ns
ns
ns
A7.23
A7.24
A7.25
A7.26
A7.27
A7.28
A7.29
-0.7
0.4
0.4
-
-
-
tPCIck
tPCIck
1.8
-
DATA setup before rising edge of
PCI
-
t9
DATA hold after rising edge of PCI
DATA hold after CS negation
ACK assertion after CS assertion
ACK negation before CS negation
ACK pulse width
0
-
(DC+1)*tPCIck
(WS+1)*tPCIck
0.6
ns
ns
ns
ns
ns
ns
ns
A7.30
A7.31
A7.32
A7.33
A7.34
A7.35
A7.36
t10
t11
t12
t13
t14
t15
0
-
-
3
4LB*2*(32/DS)*tPCIck
4LB*2*(32/DS)*tPCIck
2,3
CS assertion after TS assertion
TS pulse width
-
0.8
tPCIck
tPCIck
NOTES:
1. Wait States (WS) can be programmed in the Chip Select X Register, Bit field WaitP and WaitX. It can be specified 0 - 65535.
2. Example:
Long Burst is used, this means the CS related BERx and SLB bits of the Chip Select Burst Control Register are set and a
burst on the internal XLB is executed. => LB = 1
Data bus width is 8 bit. => DS = 8
=> 41*2*(32/8) = 32 => ACK is asserted for 32 PCI cycles to transfer one cache line.
Wait State is set to 10. => WS = 10
1+10+32 = 43 => CS is asserted for 43 PCI cycles.
3. ACK is output and indicates the burst.
MPC5200 Data Sheet, Rev. 4
30
Freescale Semiconductor
Electrical and Thermal Characteristics
PCI CLK
CS[x]
t1
t2
t6
t3
ADDR
t5
t4
OE
t7
R/W
t8
t10
DATA (rd)
t9
t11
t12
ACK
TS
t13
t14
t15
Figure 13. Timing Diagram—Burst Mode
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
31
Electrical and Thermal Characteristics
3.3.7.3 MUXed Mode
Table 26. MUXed Mode Timing
Sym
Description
Min
Max
Units Notes SpecID
tCSA
tCSN
PCI CLK to CS assertion
PCI CLK to CS negation
-
-
-
-
1.8
1.8
1
ns
ns
ns
ns
A7.15
A7.16
A7.16
A7.17
tALEA PCI CLK to ALE assertion
t1
ALE assertion before Address, Bank,
TSIZ assertion
0.8
t2
CS assertion before Address, Bank,
TSIZ negation
-
0.7
ns
A7.18
t3
t4
CS assertion before Data wr valid
Data wr hold after CS negation
Data rd setup before CS negation
Data rd hold after CS negation
ALE pulse width
-
0.7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
A7.19
A7.20
A7.21
A7.22
A7.23
A7.24
A7.24
A7.25
A7.26
A7.27
A7.26
A7.27
A7.28
A7.28
tIPBIck
-
t5
2.8
-
(DC+1)*tPCIck
tPCIck
t6
0
-
1
t7
tTSA
t8
CS assertion after TS assertion
TS pulse width
-
0.8
-
tPCIck
t9
CS pulse width
(2+WS)*tPCIck (2+WS)*tPCIck
tOEA
tOEN
t10
t11
t12
t13
OE assertion before CS assertion
OE negation before CS negation
RW assertion before ALE assertion
RW negation after CS negation
ACK assertion after CS assertion
ACK negation after CS negation
-
0.4
0.4
-
-
tIPBIck
-
tIPBIck
-
tPCIck
-
2
2
tPCIck
Note:
1. ACK can shorten the CS pulse width.
Wait States (WS) can be programmed in the Chip Select X Register, Bit field WaitP and WaitX. It can be specified 0 - 65535.
2. ACK is input and can be used to shorten the CS pulse width.
MPC5200 Data Sheet, Rev. 4
32
Freescale Semiconductor
Electrical and Thermal Characteristics
PCI CLK
t2
t4
t1
AD[31,27] (wr)
AD[30:28] (wr)
Data
Data
TSIZ[0:2] bits
AD[26:25] (wr)
AD[24:0] (wr)
Data
Data
Bank[0:1] bits
Address[7:31]
t3
t5
t6
AD[31:0] (rd)
Data
t7
ALE
TS
Address latch
t8
t9
CSx
OE
t10
t11
RW
t12
ACK
t13
Address tenure
Data tenure
Figure 14. Timing Diagram—MUXed Mode
3.3.8 ATA
The MPC5200 ATA Controller is completely software programmable. It can be programmed to operate
with ATA protocols using their respective timing, as described in the ANSI ATA-4 specification. The ATA
interface is completely asynchronous in nature. Signal relationships are based on specific fixed timing in
terms of timing units (nano seconds).
ATA data setup and hold times, with respect to Read/Write strobes, are software programmable inside the
ATA Controller. Data setup and hold times are implemented using counters. The counters count the
number of ATA clock cycles needed to meet the ANSI ATA-4 timing specifications. For details, see the
ANSI ATA-4 specification [5] and how to program an ATA Controller and ATA drive for different ATA
protocols and their respective timing. See the MPC5200 User Manual [1].
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
33
Electrical and Thermal Characteristics
The MPC5200 ATA Host Controller design makes data available coincidentally with the active edge of the
WRITE strobe in PIO and Multiword DMA modes.
•
Write data is latched by the drive at the inactive edge of the WRITE strobe. This gives ample
setup-time beyond that required by the ATA-4 specification.
•
Data is held unchanged until the next active edge of the WRITE strobe. This gives ample
hold-time beyond that required by the ATA-4 specification.
All ATA transfers are programmed in terms of system clock cycles (IP bus clocks) in the ATA Host
Controller timing registers. This puts constraints on the ATA protocols and their respective timing modes
in which the ATA Controller can communicate with the drive.
Faster ATA modes (i.e., UDMA 0, 1, 2) are supported when the system is running at a sufficient frequency
to provide adequate data transfer rates. Adequate data transfer rates are a function of the following:
•
•
•
The MPC5200 operating frequency (IP bus clock frequency)
Internal MPC5200 bus latencies
Other system load dependent variables
The ATA clock is the same frequency as the IP bus clock in MPC5200. See the MPC5200 User Manual [1].
NOTE
All output timing numbers are specified for nominal 50 pF loads.
Table 27. PIO Mode Timing Specifications
Min/Max Mode 0 Mode 1 Mode 2 Mode 3 Mode 4
PIO Timing Parameter
t0 Cycle Time
SpecID
(ns)
(ns)
(ns)
(ns)
(ns)
(ns)
min
min
600
70
383
50
240
30
180
30
120
25
A8.1
A8.2
A8.3
t1 Address valid to DIOR/DIOW setup
t2 DIOR/DIOW pulse width 16-bit
8-bit
min
min
165
290
125
290
100
290
80
80
70
70
t2i DIOR/DIOW recovery time
t3 DIOW data setup
t4 DIOW data hold
min
min
min
min
min
min
—
60
30
50
5
—
45
20
35
5
—
30
15
20
5
70
30
10
20
5
25
20
10
20
5
A8.4
A8.5
A8.6
A8.7
A8.8
A8.9
t5 DIOR data setup
t6 DIOR data hold
t9 DIOR/DIOW to address
valid hold
20
15
10
10
10
tA IORDY setup
max
max
35
35
35
35
35
A8.10
A8.11
tB IORDY pulse width
1250
1250
1250
1250
1250
MPC5200 Data Sheet, Rev. 4
34
Freescale Semiconductor
Electrical and Thermal Characteristics
CS[0]/CS[3]/DA[2:0]
DIOR/DIOW
t2
t9
t8
t1
t0
t3 t4
WDATA
RDATA
t5
t6
tA
tB
IORDY
Figure 15. PIO Mode Timing
Table 28. Multiword DMA Timing Specifications
Multiword DMA Timing Parameters Min/Max Mode 0(ns) Mode 1(ns)
Mode 2(ns) SpecID
t0 Cycle Time
min
max
min
max
min
min
min
min
min
min
min
max
max
480
—
150
—
80
60
30
5
120
—
70
50
20
5
A8.12
A8.13
A8.14
A8.15
A8.16
A8.17
A8.18
A8.19
A8.20
A8.21
A8.22
A8.23
A8.24
tC DMACK to DMARQ delay
tD DIOR/DIOW pulse width (16-bit)
tE DIOR data access
tG DIOR/DIOW data setup
tF DIOR data hold
215
150
100
5
tH DIOW data hold
20
15
0
10
0
tI
DMACK to DIOR/DIOW setup
0
tJ DIOR/DIOW to DMACK hold
tKr DIOR negated pulse width
tKw DIOW negated pulse width
tLr DIOR to DMARQ delay
20
5
5
50
50
50
40
40
25
25
35
35
215
120
40
tLw DIOW to DMARQ delay
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
35
Electrical and Thermal Characteristics
t0
DMARQ
(Drive)
tL
tC
DMACK
(Host)
tJ
tI
tD
tK
DIOR
DIOW
(Host)
tE
RDATA
(Drive)
tS
tF
WDATA
(Host)
tG
tH
NOTE:Thedirectionof signalassertionis towardsthe
top of the page, and the direction of negation is
towards the bottom of the page, irrespective of the
electrical properties of the signal.
Figure 16. Multiword DMA Timing
Table 29. Ultra DMA Timing Specification
MODE 0
(ns)
MODE 1
(ns)
MODE 2
(ns)
Name
Comment
SpecID
Min Max Min Max Min Max
(t)2CYC
(t)CYC
240
114
235
—
—
—
160
—
—
—
120
—
—
—
Typical sustained average two cycle time.
For information only, do not test.
A8.26
A8.27
A8.28
75
55
Cycle time allowing for asymmetry and clock
variations from STROBE edge to STROBE edge
(t)2CYC
156
117
Two-cycle time allowing for clock variations, from
rising edge to next rising edge or from falling edge to
next falling edge of STROBE.
(t)DS
(t)DH
(t)DVS
(t)DVH
(t)FS
15
5
—
—
10
5
—
—
7
5
—
—
—
—
Data setup time at recipient.
A8.29
A8.30
A8.31
A8.32
Data hold time at recipient.
70
6
—
48
6
—
34
6
Data valid setup time at sender, to STROBE edge.
Data valid hold time at sender, from STROBE edge.
—
—
0
230
0
200
0
170 First STROBE time for drive to first negate DSTROBE A8.33
from STOP during a data-in burst.
MPC5200 Data Sheet, Rev. 4
36
Freescale Semiconductor
Electrical and Thermal Characteristics
Table 29. Ultra DMA Timing Specification (continued)
MODE 0
(ns)
MODE 1
(ns)
MODE 2
(ns)
Name
Comment
SpecID
Min Max Min Max Min Max
(t)LI
(t)MLI
(t)UI
0
20
0
150
—
0
20
0
150
—
0
20
0
150 Limited Interlock time.1,2
A8.34
A8.35
A8.36
A8.37
—
—
Interlock time with minimum.1,2
Unlimited interlock time. 1,2
—
—
(t)AZ
—
10
—
10
—
10 Maximum time allowed for output drivers to release
from being asserted or negated
(t)ZAH
(t)ZAD
(t)ENV
20
0
—
—
70
20
0
—
—
70
20
0
—
—
Minimum delay time required for output drivers to
assert or negate from released state
A8.38
A8.39
A8.40
20
20
20
70 Envelope time—from DMACK to STOP and
HDMARDY during data out burst initiation.
(t)SR
—
50
—
30
—
20 STROBE to DMARDY time, if DMARDY is negated
before this long after STROBE edge, the recipient
receives no more than one additional data word.
A8.41
(t)RFS
(t)RP
—
75
—
—
60
—
—
50 Ready-to-Final STROBE time—no STROBE edges
are sent this long after negation of DMARDY.
A8.42
A8.43
160
125
100
—
Ready-to-Pause time—the time recipient waits to
initiate pause after negating DMARDY.
(t)IORDYZ
(t)ZIORDY
(t)ACK
—
0
20
—
—
—
0
20
—
—
—
0
20 Pull-up time before allowing IORDY to be released.
A8.44
A8.45
—
—
Minimum time drive waits before driving IORDY
20
20
20
Setup and hold times for DMACK, before assertion or A8.46
negation.
(t)SS
50
—
50
—
50
—
Time from STROBE edge to negation of DMARQ or
assertion of STOP, when sender terminates a burst.
A8.47
NOTES:
1
tUI, tMLI, tLI indicate sender-to-recipient or recipient-to-sender interlocks. That is, one agent (either sender or recipient)
is waiting for the other agent to respond with a signal before proceeding.
• tUI is an unlimited interlock that has no maximum time value.
• tMLI is a limited time-out that has a defined minimum.
• tLI is a limited time-out that has a defined maximum.
2
All timing parameters are measured at the connector of the drive to which the parameter applies. For example, the
sender shall stop generating STROBE edges tRFS after negation of DMARDY. Both STROBE and DMARDY timing
measurements are taken at the connector of the sender. Even though the sender stops generating STROBE edges,
the receiver may receive additional STROBE edges due to propagation delays. All timing measurement switching
points (low to high and high to low) are taken at 1.5 V.
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
37
Electrical and Thermal Characteristics
DMARQ
(device)
tUI
DMACK
(device)
tACK
tENV
tFS
tZAD
STOP
(host)
tACK
tENV
tFS
HDMARDY
(host)
tZAD
tZIORDY
DSTROBE
(device)
tDVS
tDVH
tAZ
DD(0:15)
tACK
DA0, DA1, DA2,
CS[0:1]1
Figure 17. Timing Diagram—Initiating an Ultra DMA Data In Burst
t2CYC
tCYC
tCYC
t2CYC
DSTROBE
at device
tDVH
tDVS
tDVH
tDVS
tDVH
DD(0:15)
at device
DSTROBE
at host
tDH
tDS
tDH
tDS
tDH
DD(0:15)
at host
Figure 18. Timing Diagram—Sustained Ultra DMA Data In Burst
MPC5200 Data Sheet, Rev. 4
38
Freescale Semiconductor
Electrical and Thermal Characteristics
DMARQ
(device)
DMARQ
(host)
tRP
STOP
(host)
tSR
HDMARDY
(host)
tRFS
DSTROBE
(device)
DD[0:15]
(device)
Figure 19. Timing Diagram—Host Pausing an Ultra DMA Data In Burst
DMARQ
(device)
DMACK
(host)
tLI
tLI
tMLI
tACK
STOP
(host)
tLI
tACK
HDMARDY
(host)
tSS
tIORDYZ
DSTROBE
(device)
tZAH
tDVS
t AZ
tDVH
CRC
DD[0:15]
tACK
DA0,DA1,DA2,
CS[0:1]
Figure 20. Timing Diagram—Drive Terminating Ultra DMA Data In Burst
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
39
Electrical and Thermal Characteristics
DMARQ
(device)
tLI
tMLI
DMACK
(host)
tRP
tZAH
tACK
STOP
(host)
tACK
HDMARDY
(host)
tMLI
tRFS
tLI
tIORDYZ
DSTROBE
(device)
tDVS
tDVH
CRC
DD[0:15]
tACK
DA0,DA1,DA2,
CS[0:1]
Figure 21. Timing Diagram—Host Terminating Ultra DMA Data In Burst
MPC5200 Data Sheet, Rev. 4
40
Freescale Semiconductor
Electrical and Thermal Characteristics
DMARQ
(device)
tUI
DMACK
(host)
tENV
tACK
STOP
(host)
tLI
tUI
tZIORDY
DDMARDY
(host)
tACK
HSTROBE
(device)
tDVS
tDVH
DD[0:15]
(host)
tACK
DA0,DA1,DA2,
CS[0:1]
Figure 22. Timing Diagram—Initiating an Ultra DMA Data Out Burst
t2CYC
tCYC
tCYC
t2CYC
HSTROBE
(host)
tDVS
tDVS
tDVH
tDVH
tDVH
DD[0:15]
(host)
HSTROBE
(device)
tDS
tDS
tDH
tDH
tDH
DD[0:15]
(device)
Figure 23. Timing Diagram—Sustained Ultra DMA Data Out Burst
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
41
Electrical and Thermal Characteristics
tRP
DMARQ
(device)
DMACK
(host)
STOP
(host)
tSR
DDMARDY
(device)
tRFS
HSTROBE
DD[0:15]
(host)
Figure 24. Timing Diagram—Drive Pausing an Ultra DMA Data Out Burst
DMARQ
(device)
tLI
tMLI
DMACK
(host)
tSS
tACK
tLI
STOP
(host)
tLI
tIORDYZ
DDMARDY
(device)
tACK
HSTROBE
(host)
tDVS
tDVH
DD[0:15]
(host)
CRC
tACK
DA0,DA1,DA2,
CS[0:1]
Figure 25. Timing Diagram—Host Terminating Ultra DMA Data Out Burst
MPC5200 Data Sheet, Rev. 4
42
Freescale Semiconductor
Electrical and Thermal Characteristics
DMARQ
(device)
DMACK
(host)
tLI
tMLI
tACK
STOP
(host)
tRP
tIORDYZ
DDMARDY
(device)
tRFS
tLI
tMLI
tACK
HSTROBE
(host)
tDVS
tDVH
DD[0:15]
(host)
CRC
tACK
DA0,DA1,DA2,
CS[0:1]
Figure 26. Timing Diagram—Drive Terminating Ultra DMA Data Out Burst
Table 30. Timing Specification ata_isolation
Sym
Description
ata_isolation setup time
Min
Max
Units
SpecID
1
2
7
-
-
IP Bus cycles
IP Bus cycles
A8.48
A8.49
ata_isolation hold time
19
DIOR
ATA_ISOLATION
1
2
Figure 27. Timing Diagram-ATA-ISOLATION
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
43
Electrical and Thermal Characteristics
3.3.9 Ethernet
AC Test Timing Conditions:
•
Output Loading
All Outputs: 25 pF
Table 31. MII Rx Signal Timing
Sym
Description
Min
Max
Unit
SpecID
M1
M2
M3
M4
RXD[3:0], RX_DV, RX_ER to RX_CLK setup
RX_CLK to RXD[3:0], RX_DV, RX_ER hold
RX_CLK pulse width high
10
10
—
—
ns
A9.1
A9.2
A9.3
A9.4
ns
35%
35%
65%
65%
RX_CLK Period1
RX_CLK Period1
RX_CLK pulse width low
N1 OTES:
RX_CLK shall have a frequency of 25% of data rate of the received signal. See the IEEE 802.3 Specification [6].
M3
RX_CLK (Input)
M4
RXD[3:0] (inputs)
RX_DV
RX_ER
M1
Figure 28. Ethernet Timing Diagram—MII Rx Signal
M2
MPC5200 Data Sheet, Rev. 4
44
Freescale Semiconductor
Electrical and Thermal Characteristics
Table 32. MII Tx Signal Timing
Sym
Description
Min
Max
Unit
SpecID
M5
TX_CLK rising edge to TXD[3:0], TX_EN, TX_ER
Delay
0
25
ns
A9.5
M6
M7
TX_CLK pulse width high
TX_CLK pulse width low
35%
35%
65%
65%
TX_CLK Period1
TX_CLK Period(1)
A9.6
A9.7
N1 OTES:
the TX_CLK frequency shall be 25% of the nominal transmit frequency, e.g., a PHY operating at 100 Mb/s must
provide a TX_CLK frequency of 25 MHz and a PHY operating at 10 Mb/s must provide a TX_CLK frequency of 2.5
MHz. See the IEEE 802.3 Specification [6].
M6
TX_CLK (Input)
M5
M7
TXD[3:0] (Outputs)
TX_EN
TX_ER
Figure 29. Ethernet Timing Diagram—MII Tx Signal
Table 33. MII Async Signal Timing
Sym
Description
Min
Max
Unit
SpecID
M8
CRS, COL minimum pulse width
1.5
—
TX_CLK Period
A9.8
CRS, COL
M8
Figure 30. Ethernet Timing Diagram—MII Async
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
45
Electrical and Thermal Characteristics
Table 34. MII Serial Management Channel Signal Timing
Sym
Description
Min
Max
Unit
SpecID
M9
MDC falling edge to MDIO output delay
0
25
—
—
—
—
—
ns
ns
ns
ns
ns
ns
A9.9
M10 MDIO (input) to MDC rising edge setup
M11 MDIO (input) to MDC rising edge hold
M12 MDC pulse width high1
10
A9.10
A9.11
A9.12
A9.13
A9.14
10
160
160
400
M13 MDC pulse width low(1)
M14 MDC period2
N1 OTES:
MDC is generated by MPC5200 with a duty cycle of 50% except when MII_SPEED in the FEC MII_SPEED control
register is changed during operation. See the MPC5200 User Manual [1].
2
The MDC period must be set to a value of less then or equal to 2.5 MHz (to be compliant with the IEEE MII
characteristic) by programming the FEC MII_SPEED control register. See the MPC5200 User Manual [1].
M12
M13
MDC (Output)
M14
M9
MDIO (Output)
MDIO (Input)
M10 M11
Figure 31. Ethernet Timing Diagram—MII Serial Management
3.3.10 USB
Table 35. Timing Specifications—USB Output Line
Sym
Description
Min
Max
Units
SpecID
1
USB Bit width1
Transceiver enable time
83.3
83.3
—
667
667
7.9
ns
ns
ns
ns
A10.1
A10.2
A10.3
A10.4
2
3
4
Signal falling time
Signal rising time
—
7.9
N1 OTES:
Defined in the USB config register, (12 Mbit/s or 1.5 Mbit/s mode).
MPC5200 Data Sheet, Rev. 4
46
Freescale Semiconductor
Electrical and Thermal Characteristics
NOTE
Output timing was specified at a nominal 50 pF load.
2
USB_OE
4
3
USB_TXN
USB_TXP
1
1
3
4
Figure 32. Timing Diagram—USB Output Line
3.3.11 SPI
Table 36. Timing Specifications — SPI Master Mode, Format 0 (CPHA = 0)
Sym
Description
Min
Max
Units
SpecID
Cycle time
1
4
2
1024
512
—
IP-Bus Cycle1
A11.1
A11.2
A11.3
A11.4
A11.5
A11.6
A11.7
A11.8
A11.9
A11.10
A11.11
Clock high or low time
Slave select clock delay
2
IP-Bus Cycle1
3
15.0
—
ns
Output Data valid after Slave Select (SS)
Output Data valid after SCK
Input Data setup time
4
20.0
20.0
—
ns
5
—
ns
6
20.0
20.0
15.0
1
ns
Input Data hold time
7
—
ns
Slave disable lag time
Sequential transfer delay
Clock falling time
8
9
—
ns
—
IP-Bus Cycle1
10
—
7.9
7.9
ns
ns
Clock rising time
11
—
N1 OTES:
Inter Peripheral Clock is defined in the MPC5200 User Manual [1].
NOTE
Output timing was specified at a nominal 50 pF load.
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
47
Electrical and Thermal Characteristics
1
11
10
10
11
SCK
(CLKPOL=0)
Output
2
2
SCK
(CLKPOL=1)
Output
9
8
3
SS
Output
5
4
MOSI
Output
6
6
MISO
Input
7
7
Figure 33. Timing Diagram — SPI Master Mode, Format 0 (CPHA = 0)
Table 37. Timing Specifications — SPI Slave Mode, Format 0 (CPHA = 0)
Sym
Description
Min
Max
Units
SpecID
1
Cycle time
4
2
1024
512
—
IP-Bus Cycle1
A11.12
A11.13
A11.14
A11.15
A11.16
A11.17
A11.18
A11.19
A11.20
2
Clock high or low time
IP-Bus Cycle1
3
Slave select clock delay
Output Data valid after Slave Select (SS)
Output Data valid after SCK
Input Data setup time
15.0
—
ns
4
50.0
50.0
—
ns
5
—
ns
6
50.0
0.0
15.0
1
ns
7
Input Data hold time
—
ns
ns
8
9
Slave disable lag time
—
Sequential Transfer delay
—
IP-Bus Cycle1
N1 OTES:
Inter Peripheral Clock is defined in the MPC5200 User Manual [1].
NOTE
Output timing was specified at a nominal 50 pF load.
MPC5200 Data Sheet, Rev. 4
48
Freescale Semiconductor
Electrical and Thermal Characteristics
1
SCK
(CLKPOL=0)
Input
2
2
SCK
(CLKPOL=1)
Input
9
8
3
SS
Input
6
7
MOSI
Input
4
5
MISO
Output
Figure 34. Timing Diagram — SPI Slave Mode, Format 0 (CPHA = 0)
Table 38. Timing Specifications — SPI Master Mode, Format 1 (CPHA = 1)
Sym
Description
Min
Max
Units
SpecID
1
Cycle time
4
2
1024
512
—
IP-Bus Cycle1 A11.21
IP-Bus Cycle1 A11.22
2
Clock high or low time
3
Slave select clock delay
Output data valid
15.0
—
ns
ns
ns
ns
ns
A11.23
A11.24
A11.25
A11.26
A11.27
4
20.0
—
5
Input Data setup time
Input Data hold time
Slave disable lag time
Sequential Transfer delay
Clock falling time
20.0
20.0
15.0
1
6
—
7
—
8
9
—
IP-Bus Cycle1 A11.28
—
7.9
7.9
ns
ns
A11.29
A11.30
10
Clock rising time
—
N1 OTES:
Inter Peripheral Clock is defined in the MPC5200 User Manual [1].
NOTE
Output timing was specified at a nominal 50 pF load.
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
49
Electrical and Thermal Characteristics
1
10
9
9
SCK
(CLKPOL=0)
Output
2
2
10
SCK
(CLKPOL=1)
Output
8
7
3
SS
Output
4
MOSI
Output
5
MISO
Input
6
Figure 35. Timing Diagram — SPI Master Mode, Format 1 (CPHA = 1)
Table 39. Timing Specifications — SPI Slave Mode, Format 1 (CPHA = 1)
Sym
Description
Min
Max
Units
SpecID
1
Cycle time
4
2
1024
512
—
IP-Bus Cycle1 A11.31
IP-Bus Cycle1 A11.32
2
Clock high or low time
3
Slave select clock delay
Output data valid
15.0
—
ns
ns
ns
ns
ns
A11.33
A11.34
A11.35
A11.36
A11.37
4
50.0
—
5
Input Data setup time
Input Data hold time
Slave disable lag time
Sequential Transfer delay
50.0
0.0
15.0
1
6
—
7
8
—
—
IP-Bus Cycle1 A11.38
N1 OTES:
Inter Peripheral Clock is defined in the MPC5200 User Manual [1].
NOTE
Output timing was specified at a nominal 50 pF load.
MPC5200 Data Sheet, Rev. 4
50
Freescale Semiconductor
Electrical and Thermal Characteristics
1
SCK
(CLKPOL=0)
Input
2
2
SCK
(CLKPOL=1)
Input
8
7
3
SS
Input
5
6
MOSI
Input
4
MISO
Output
Figure 36. Timing Diagram — SPI Slave Mode, Format 1 (CPHA = 1)
3.3.12 MSCAN
2
The CAN functions are available as RX and TX pins at normal IO pads (I C1+GPTimer or PSC2). There
is no filter for the WakeUp dominant pulse. Any High-to-Low edge can cause WakeUp, if configured.
2
3.3.13 I C
2
Table 40. I C Input Timing Specifications—SCL and SDA
Sym
Description
Start condition hold time
Min
Max
Units
SpecID
1
2
4
6
7
8
2
8
—
—
—
—
—
—
IP-Bus Cycle1
IP-Bus Cycle1
ns
A13.1
A13.2
A13.3
A13.4
A13.5
A13.6
Clock low period
Data hold time
Clock high time
Data setup time
0.0
4
IP-Bus Cycle1
0.0
2
ns
Start condition setup time (for repeated start condition
only)
IP-Bus Cycle1
9
Stop condition setup time
2
—
IP-Bus Cycle1
A13.7
N1 OTES:
Inter Peripheral Clock is defined in the MPC5200 User Manual [1].
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
51
Electrical and Thermal Characteristics
2
Table 41. I C Output Timing Specifications—SCL and SDA
Sym
Description
Start condition hold time
Min
Max
Units
SpecID
11
21
32
41
51
61
71
81
6
10
—
7
—
—
IP-Bus Cycle3 A13.8
IP-Bus Cycle3 A13.9
Clock low period
SCL/SDA rise time
Data hold time
7.9
—
ns
IP-Bus Cycle3 A13.11
ns A13.12
A13.10
SCL/SDA fall time
Clock high time
Data setup time
—
10
2
7.9
—
IP-Bus Cycle3 A13.13
IP-Bus Cycle3 A13.14
IP-Bus Cycle3 A13.15
—
Start condition setup time (for repeated start condition
only)
20
—
91
Stop condition setup time
10
—
IP-Bus Cycle3 A13.16
N1 OTES:
Programming IFDR with the maximum frequency (IFDR=0x20) results in the minimum output timings listed. The
I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period. The actual
position is affected by the prescale and division values programmed in IFDR.
2
3
Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL
or SDA takes to reach a high level depends on external signal capacitance and pull-up resistor values
Inter Peripheral Clock is defined in the MPC5200 User Manual [1].
NOTE
Output timing was specified at a nominal 50 pF load.
2
5
6
SCL
SDA
3
1
7
8
4
9
2
Figure 37. Timing Diagram—I C Input/Output
3.3.14 J1850
See the MPC5200 User Manual [1].
MPC5200 Data Sheet, Rev. 4
52
Freescale Semiconductor
Electrical and Thermal Characteristics
3.3.15 PSC
3.3.15.1 Codec Mode (8,16,24 and 32-bit) / I2S Mode
2
Table 42. Timing Specifications—8,16, 24 and 32-bit CODEC / I S Master Mode
Sym
Description
Min
Typ
Max
Units SpecID
1
Bit Clock cycle time, programmed in CCS register
Clock pulse width
40.0
—
—
50
—
—
—
—
—
—
—
—
ns
A15.1
A15.2
A15.3
A15.4
A15.5
A15.6
A15.7
A15.8
1
2
%
3
Bit Clock fall time
—
7.9
7.9
8.4
8.4
9.3
—
ns
ns
ns
ns
ns
ns
4
Bit Clock rise time
—
5
FrameSync valid after clock edge
FrameSync invalid after clock edge
Output Data valid after clock edge
Input Data setup time
—
6
—
7
8
—
6.0
N1 OTES:
Bit Clock cycle time
NOTE
Output timing was specified at a nominal 50 pF load.
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
53
Electrical and Thermal Characteristics
1
BitClk
(CLKPOL=0)
3
2
2
Output
4
BitClk
(CLKPOL=1)
Output
4
3
5
Frame
(SyncPol = 1)
6
Output
Frame
(SyncPol = 0)
Output
7
TxD
Output
8
RxD
Input
2
Figure 38. Timing Diagram — 8,16, 24, and 32-bit CODEC / I S Master Mode
2
Table 43. Timing Specifications — 8,16, 24, and 32-bit CODEC / I S Slave Mode
Sym
Description
Min
Typ
Max
Units SpecID
1
Bit Clock cycle time
Clock pulse width
40.0
—
—
50
—
—
—
—
—
—
ns
A15.9
A15.10
A15.11
A15.12
A15.13
A15.14
1
2
%
3
FrameSync setup time
Output Data valid after clock edge
Input Data setup time
1.0
—
—
ns
ns
ns
ns
4
14.0
—
5
6
1.0
1.0
Input Data hold time
—
N1 OTES:
Bit Clock cycle time
NOTE
Output timing was specified at a nominal 50 pF load.
MPC5200 Data Sheet, Rev. 4
54
Freescale Semiconductor
Electrical and Thermal Characteristics
1
BitClk
(CLKPOL=0)
Input
2
2
BitClk
(CLKPOL=1)
Input
3
Frame
(SyncPol = 1)
Input
Frame
(SyncPol = 0)
Input
4
TxD
Output
5
RxD
Input
6
2
Figure 39. Timing Diagram — 8,16, 24, and 32-bit CODEC / I S Slave Mode
3.3.15.2 AC97 Mode
Table 44. Timing Specifications — AC97 Mode
Sym
Description
Min
Typ
Max
Units SpecID
1
2
3
4
5
6
7
Bit Clock cycle time
Clock pulse high time
Clock pulse low time
—
—
81.4
40.7
40.7
—
—
—
ns
ns
ns
ns
ns
ns
ns
A15.15
A15.16
A15.17
A15.18
A15.19
A15.20
A15.21
—
—
Frame valid after rising clock edge
Output Data valid after rising clock edge
Input Data setup time
—
13.0
14.0
—
—
—
1.0
1.0
—
Input Data hold time
—
—
NOTE
Output timing was specified at a nominal 50 pF load.
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
55
Electrical and Thermal Characteristics
1
BitClk
(CLKPOL=0)
3
2
4
5
Input
Sync
(SyncPol = 1)
Output
Sdata_out
Output
6
7
Sdata_in
Input
Figure 40. Timing Diagram — AC97 Mode
3.3.15.3 IrDA Mode
Table 45. Timing Specifications — IrDA Transmit Line
Sym
Description
Min
Max
Units SpecID
1
2
3
4
Pulse high time, defined in the IrDA protocol definition
Pulse low time, defined in the IrDA protocol definition
Transmitter rising time
0.125
0.125
—
10000
10000
7.9
µs
µs
ns
ns
A15.22
A15.23
A15.24
A15.25
Transmitter falling time
—
7.9
NOTE
Output timing was specified at a nominal 50 pF load.
4
IrDA_TX
(SIR / FIR / MIR)
3
1
2
Figure 41. Timing Diagram — IrDA Transmit Line
MPC5200 Data Sheet, Rev. 4
56
Freescale Semiconductor
Electrical and Thermal Characteristics
3.3.15.4 SPI Mode
Table 46. Timing Specifications — SPI Master Mode, Format 0 (CPHA = 0)
Sym
Description
Min
Max
Units SpecID
1
2
3
4
5
6
7
8
9
SCK cycle time, programable in the PSC CCS register
SCK pulse width, 50% SCK cycle time
Slave select clock delay, programable in the PSC CCS register
Output Data valid after Slave Select (SS)
Output Data valid after SCK
30.0
15.0
30.0
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
A15.26
A15.27
A15.28
A15.29
A15.30
A15.31
A15.32
A15.33
A15.34
—
8.9
8.9
—
—
Input Data setup time
6.0
1.0
—
Input Data hold time
—
Slave disable lag time
8.9
—
Sequential Transfer delay, programable in the PSC CTUR / CTLR
register
15.0
10
11
Clock falling time
Clock rising time
—
—
7.9
7.9
ns
ns
A15.35
A15.36
NOTE
Output timing was specified at a nominal 50 pF load.
1
11
10
SCK
(CLKPOL=0)
Output
2
2
10
11
SCK
(CLKPOL=1)
Output
9
8
3
SS
Output
5
4
MOSI
Output
6
6
MISO
Input
7
7
Figure 42. Timing Diagram — SPI Master Mode, Format 0 (CPHA = 0)
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
57
Electrical and Thermal Characteristics
Table 47. Timing Specifications — SPI Slave Mode, Format 0 (CPHA = 0)
Sym
Description
Min
Max
Units SpecID
1
2
3
4
5
6
7
8
9
SCK cycle time, programable in the PSC CCS register
SCK pulse width, 50% SCK cycle time
Slave select clock delay
30.0
15.0
1.0
1.0
1.0
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
—
A15.37
A15.38
A15.39
A15.40
A15.41
A15.42
A15.43
A15.44
A15.45
—
Input Data setup time
—
Input Data hold time
—
Output data valid after SS
14.0
14.0
—
Output data valid after SCK
—
Slave disable lag time
0.0
30.0
Minimum Sequential Transfer delay = 2 * IP Bus clock cycle time
—
NOTE
Output timing was specified at a nominal 50 pF load.
1
SCK
(CLKPOL=0)
Input
2
2
SCK
(CLKPOL=1)
Input
9
8
3
SS
Input
5
4
MOSI
Input
7
6
MISO
Output
Figure 43. Timing Diagram — SPI Slave Mode, Format 0 (CPHA = 0)
MPC5200 Data Sheet, Rev. 4
58
Freescale Semiconductor
Electrical and Thermal Characteristics
Table 48. Timing Specifications — SPI Master Mode, Format 1 (CPHA = 1)
Sym
Description
Min
Max
Units SpecID
1
2
3
4
5
6
7
8
SCK cycle time, programable in the PSC CCS register
SCK pulse width, 50% SCK cycle time
Slave select clock delay, programable in the PSC CCS register
Output data valid
30.0
15.0
30.0
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
A15.46
A15.47
A15.48
A15.49
A15.50
A15.51
A15.52
A15.53
—
8.9
—
Input Data setup time
6.0
Input Data hold time
1.0
—
Slave disable lag time
—
8.9
—
Sequential Transfer delay, programable in the PSC CTUR / CTLR
register
15.0
9
Clock falling time
Clock rising time
—
—
7.9
7.9
ns
ns
A15.54
A15.55
10
NOTE
Output timing was specified at a nominal 50 pF load.
1
10
9
SCK
(CLKPOL=0)
Output
2
2
9
10
SCK
(CLKPOL=1)
Output
8
7
3
4
SS
Output
MOSI
Output
5
MISO
Input
6
Figure 44. Timing Diagram — SPI Master Mode, Format 1 (CPHA = 1)
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
59
Electrical and Thermal Characteristics
Table 49. Timing Specifications — SPI Slave Mode, Format 1 (CPHA = 1)
Sym
Description
Min
Max
Units SpecID
1
2
3
4
5
6
7
8
SCK cycle time, programable in the PSC CCS register
SCK pulse width, 50% SCK cycle time
Slave select clock delay
30.0
15.0
0.0
—
—
ns
ns
ns
ns
ns
ns
ns
ns
A15.56
A15.57
A15.58
A15.59
A15.60
A15.61
A15.62
A15.63
—
Output data valid
—
14.0
—
Input Data setup time
2.0
Input Data hold time
1.0
—
Slave disable lag time
0.0
—
Minimum Sequential Transfer delay = 2 * IP-Bus clock cycle time
30.0
—
NOTE
Output timing was specified at a nominal 50 pF load.
1
SCK
(CLKPOL=0)
Input
2
2
SCK
(CLKPOL=1)
Input
8
7
3
SS
Input
5
6
MOSI
Input
4
MISO
Output
Figure 45. Timing Diagram — SPI Slave Mode, Format 1 (CPHA = 1)
MPC5200 Data Sheet, Rev. 4
60
Freescale Semiconductor
Electrical and Thermal Characteristics
3.3.16 GPIOs and Timers
3.3.16.1 General and Asynchronous Signals
The MPC5200 contains several sets if I/Os that do not require special setup, hold, or valid requirements.
Most of these are asynchronous to the system clock. The following numbers are provided for test and
validation purposes only, and they assume a 133 MHz internal bus frequency.
Figure 46 shows the GPIO Timing Diagram. Table 50 gives the timing specifications.
Table 50. Asynchronous Signals
Sym
Description
Min
Max
Units
SpecID
tCK
tIS
Clock Period
7.52
12
1
—
—
ns
ns
ns
ns
ns
A16.1
A16.2
A16.3
A16.4
A16.5
Input Setup for Async Signal
Input Hold for Async Signals
Output Valid
tIH
—
tDV
tDH
—
1
15.33
—
Output Hold
t
CK
t
DH
t
DV
Output
Input
valid
valid
t
IH
t
IS
Figure 46. Timing Diagram—Asynchronous Signals
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
61
Electrical and Thermal Characteristics
3.3.17 IEEE 1149.1 (JTAG) AC Specifications
Table 51. JTAG Timing Specification
Sym
Characteristic
TCK frequency of operation.
Min
Max
Unit
SpecID
—
1
0
40
1.08
0
25
—
—
3
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
A17.1
A17.2
A17.3
A17.4
A17.5
A17.6
A17.7
A17.8
A17.9
A17.10
A17.11
A17.12
A17.13
A17.14
TCK cycle time.
2
TCK clock pulse width measured at 1.5V.
3
TCK rise and fall times.
4
TRST setup time to tck falling edge1.
TRST assert time.
Input data setup time2.
10
5
—
—
—
—
30
30
—
—
15
15
5
6
5
7
Input data hold time2.
15
0
8
TCK to output data valid3.
TCK to output high impedance3.
TMS, TDI data setup time.
TMS, TDI data hold time.
TCK to TDO data valid.
9
0
10
11
12
13
5
1
0
TCK to TDO high impedance.
0
NOTES:
1
TRST is an asynchronous signal. The setup time is for test purposes only.
Non-test, other than TDI and TMS, signal input timing with respect to TCK.
Non-test, other than TDO, signal output timing with respect to TCK.
2
3
1
2
2
VM
VM
VM
TCK
3
3
VM = Midpoint Voltage
Numbers shown reference Table 51.
Figure 47. Timing Diagram—JTAG Clock Input
MPC5200 Data Sheet, Rev. 4
62
Freescale Semiconductor
Electrical and Thermal Characteristics
TCK
4
TRST
5
Numbers shown reference Table 51.
Figure 48. Timing Diagram—JTAG TRST
TCK
6
7
INPUT DATA VALID
DATA INPUTS
8
9
OUTPUT DATA VALID
DATA OUTPUTS
DATA OUTPUTS
Numbers shown reference Table 51.
Figure 49. Timing Diagram—JTAG Boundary Scan
TCK
TDI, TMS
TDO
10
11
INPUT DATA VALID
12
13
OUTPUT DATA VALID
TDO
Numbers shown reference Table 51.
Figure 50. Timing Diagram—Test Access Port
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
63
Package Description
4 Package Description
4.1 Package Parameters
The MPC5200 uses a 27 mm x 27 mm TE-PBGA package. The package parameters are as provided in the
following list:
•
•
•
Package outline 27 mm x 27 mm
Interconnects 272
Pitch
1.27 mm
4.2 Mechanical Dimensions
Figure 51 provides the mechanical dimensions, top surface, side profile, and pinout for the MPC5200, 272
TE-PBGA package.
MPC5200 Data Sheet, Rev. 4
64
Freescale Semiconductor
Package Description
PIN A1
INDEX
D
C
4X
0.2
A
272X
A
0.2
A
0.35
E
E2
NOTES:
1. DIMENSIONS AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DIMENSION IS MEASURED AT THE MAXIMUM
SOLDER BALL DIAMETER PARALLEL TO
PRIMARY DATUM A.
4. PRIMARY DATUM A AND THE SEATING PLANE
ARE DEFINED BY THE SPHERICAL CROWNS OF
THE SOLDER BALLS.
M
A
B C
D2
0.2
B
TOP VIEW
MILLIMETERS
DIM
A
A1
A2
A3
b
MIN
2.05
0.50
0.50
1.05
0.60
27.00 BSC
24.13 REF
23.30 24.70
MAX
2.65
0.70
0.70
1.25
0.90
(D1)
19X
e
Y
W
V
U
T
R
P
N
M
L
D
19X
e
D1
D2
E
E1
E2
e
27.00 BSC
24.13 REF
23.30
24.70
1.27 BSC
(E1)
K
J
H
G
F
A1
A2
4X
e
/2
A3
E
D
C
B
A
A
SIDE VIEW
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
3
b
272X
M
A
A
B C
0.3
BOTTOM VIEW
M
0.15
CASE 1135A–01
ISSUE B
Figure 51. Mechanical Dimensions and Pinout Assignments for the MPC5200, 272 TE-PBGA
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
65
Package Description
4.3 Pinout Listings
See details in the MPC5200 User Manual [1].
Table 52. MPC5200 Pinout Listing
Output Driver
Type
Input
Type
Pull-up/
down
Name
Alias
Type
Power Supply
SDRAM
MEM_CAS
CAS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD_MEM_IO DRV16_MEM
VDD_MEM_IO DRV16_MEM
VDD_MEM_IO DRV16_MEM
VDD_MEM_IO DRV16_MEM
VDD_MEM_IO DRV16_MEM
VDD_MEM_IO DRV16_MEM
VDD_MEM_IO DRV16_MEM
VDD_MEM_IO DRV16_MEM
VDD_MEM_IO DRV16_MEM
VDD_MEM_IO DRV16_MEM
VDD_MEM_IO DRV16_MEM
VDD_MEM_IO DRV16_MEM
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
MEM_CLK_EN
MEM_CS
CLK_EN
MEM_DQM[3:0]
MEM_MA[12:0]
MEM_MBA[1:0]
MEM_MDQS[3:0]
MEM_MDQ[31:0]
MEM_CLK
DQM
MA
MBA
MDQS
MDQ
MEM_CLK
MEM_RAS
RAS
MEM_WE
PCI
EXT_AD[31:0]
PCI_CBE_0
PCI_CBE_1
PCI_CBE_2
PCI_CBE_3
PCI_CLOCK
PCI_DEVSEL
PCI_FRAME
PCI_GNT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
TTL
TTL
PCI
PCI
PCI
TTL
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
DRV8
DRV8
PCI
PCI_IDSEL
PCI_IRDY
PCI_PAR
PCI
PCI_PERR
PCI_REQ
PCI
DRV8
PCI
PCI_RESET
PCI_SERR
PCI_STOP
PCI
PCI
MPC5200 Data Sheet, Rev. 4
66
Freescale Semiconductor
Package Description
Table 52. MPC5200 Pinout Listing (continued)
Output Driver
Input
Type
Pull-up/
down
Name
PCI_TRDY
Alias
Type
Power Supply
Type
I/O
VDD_IO
PCI
PCI
Local Plus
LP_ACK
LP_ALE
LP_OE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
DRV8
DRV8
DRV8
DRV8
DRV8
DRV8
DRV8
DRV8
DRV8
DRV8
DRV8
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
PULLUP
LP_RW
LP_TS
LP_CS0
LP_CS1
LP_CS2
LP_CS3
LP_CS4
LP_CS5
ATA
ATA_DACK
ATA_DRQ
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
DRV8
DRV8
DRV8
DRV8
DRV8
DRV8
DRV8
TTL
TTL
TTL
TTL
TTL
TTL
TTL
PULLDOWN
PULLDOWN
PULLUP
ATA_INTRQ
ATA_IOCHRDY
ATA_IOR
ATA_IOW
ATA_ISOLATION
Ethernet
ETH_0
ETH_1
ETH_2
TX, TX_EN
I/O
I/O
I/O
VDD_IO
VDD_IO
VDD_IO
DRV4
DRV4
DRV4
TTL
TTL
TTL
RTS, TXD[0]
USB_TXP, TX,
TXD[1]
ETH_3
ETH_4
ETH_5
ETH_6
ETH_7
USB_PRTPWR,
TXD[2]
I/O
I/O
I/O
I/O
I/O
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
DRV4
DRV4
DRV4
DRV4
DRV4
TTL
TTL
TTL
TTL
TTL
USB_SPEED,
TXD[3]
USB_SUPEND,
TX_ER
USB_OE, RTS,
MDC
TXN, MDIO
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
67
Package Description
Name
Table 52. MPC5200 Pinout Listing (continued)
Output Driver
Input
Type
Pull-up/
down
Alias
Type
Power Supply
Type
ETH_8
RX_DV
CD, RX_CLK
CTS, COL
TX_CLK
I/O
I/O
I/O
I/O
I/O
I/O
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
DRV4
DRV4
DRV4
DRV4
DRV4
DRV4
TTL
Schmitt
TTL
ETH_9
ETH_10
ETH_11
ETH_12
ETH_13
Schmitt
TTL
RXD[0]
USB_RXD, CTS,
RXD[1]
TTL
ETH_14
ETH_15
ETH_16
ETH_17
USB_RXP,
UART_RX, RXD[2]
I/O
I/O
I/O
I/O
VDD_IO
VDD_IO
VDD_IO
DRV4
DRV4
DRV4
DRV4
TTL
TTL
TTL
TTL
USB_RXN, RX,
RXD[3]
USB_OVRCNT,
CTS, RX_ER
CD, CRS
VDD_IO
IRDA
PSC6_0
PSC6_1
PSC6_2
PSC6_3
IRDA_RX, TxD
RxD
I/O
I/O
I/O
I/O
VDD_IO
VDD_IO
VDD_IO
VDD_IO
DRV4
DRV4
DRV4
DRV4
TTL
TTL
TTL
TTL
Frame, CTS
IR_USB_CLK,BitC
lk, RTS
USB
USB_0
USB_1
USB_2
USB_3
USB_4
USB_5
USB_6
USB_7
USB_8
USB_9
USB_OE
USB_TXN
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
DRV4
DRV4
DRV4
DRV4
DRV4
DRV4
DRV4
DRV4
DRV4
DRV4
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
USB_TXP
USB_RXD
USB_RXP
USB_RXN
USB_PRTPWR
USB_SPEED
USB_SUPEND
USB_OVRCNT
I2C
I2C_0
I2C_1
I2C_2
SCL
SDA
SCL
I/O
I/O
I/O
VDD_IO
VDD_IO
VDD_IO
DRV4
DRV4
DRV4
Schmitt
Schmitt
Schmitt
MPC5200 Data Sheet, Rev. 4
68
Freescale Semiconductor
Package Description
Table 52. MPC5200 Pinout Listing (continued)
Output Driver
Input
Type
Pull-up/
down
Name
Alias
Type
Power Supply
Type
I2C_3
SDA
I/O
VDD_IO
PSC
DRV4
Schmitt
PSC1_0
PSC1_1
TxD, Sdata_out,
MOSI, TX
I/O
I/O
VDD_IO
DRV4
DRV4
TTL
TTL
RxD, Sdata_in,
MISO, TX
VDD_IO
PSC1_2
PSC1_3
PSC1_4
PSC2_0
Mclk, Sync, RTS
BitClk, SCK, CTS
Frame, SS, CD
I/O
I/O
I/O
I/O
VDD_IO
VDD_IO
VDD_IO
VDD_IO
DRV4
DRV4
DRV4
DRV4
TTL
TTL
TTL
TTL
TxD, Sdata_out,
MOSI, TX
PSC2_1
RxD, Sdata_in,
MISO, TX
I/O
VDD_IO
DRV4
TTL
PSC2_2
PSC2_3
PSC2_4
PSC3_0
Mclk, Sync, RTS
BitClk, SCK, CTS
Frame, SS, CD
I/O
I/O
I/O
I/O
VDD_IO
VDD_IO
VDD_IO
VDD_IO
DRV4
DRV4
DRV4
DRV4
TTL
TTL
TTL
TTL
USB_OE, TxDS,
TX
PSC3_1
PSC3_2
PSC3_3
USB_TXN, RxD,
RX
I/O
I/O
I/O
VDD_IO
VDD_IO
VDD_IO
DRV4
DRV4
DRV4
TTL
TTL
TTL
USB_TXP, BitClk,
RTS
USB_RXD, Frame,
SS, CTS
PSC3_4
PSC3_5
PSC3_6
USB_RXP, CD
USB_RXN
I/O
I/O
I/O
VDD_IO
VDD_IO
VDD_IO
DRV4
DRV4
DRV4
TTL
TTL
TTL
USB_PRTPWR,
Mclk, MOSI
PSC3_7
PSC3_8
PSC3_9
USB_SPEED.
MISO
I/O
I/O
I/O
VDD_IO
VDD_IO
VDD_IO
DRV4
DRV4
DRV4
TTL
TTL
TTL
USB_SUPEND,
SS
USB_OVRCNT,
SCK
GPIO/TIMER
GPIO_WKUP_6
GPIO_WKUP_7
TIMER_0
MEM_CS1
I/O
I/O
I/O
VDD_MEM_IO DRV16_MEM
TTL
TTL
TTL
PULLUP_MEM
VDD_IO
VDD_IO
DRV8
DRV4
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
69
Package Description
Name
Table 52. MPC5200 Pinout Listing (continued)
Output Driver
Input
Type
Pull-up/
down
Alias
Type
Power Supply
Type
TIMER_1
TIMER_2
TIMER_3
TIMER_4
TIMER_5
TIMER_6
TIMER_7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
DRV4
DRV4
DRV4
DRV4
DRV4
DRV4
DRV4
TTL
TTL
TTL
TTL
TTL
TTL
TTL
MOSI
MISO
SS
SCK
Clock
SYS_XTAL_IN
SYS_XTAL_OUT
RTC_XTAL_IN
RTC_XTAL_OUT
Input
Output
Input
VDD_IO
VDD_IO
VDD_IO
VDD_IO
Output
Misc
PORRESET
HRESET
SRESET
IRQ0
Input
I/O
I/O
I/O
I/O
I/O
I/O
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
DRV4
DRV8_OD1
DRV8_OD1
DRV4
Schmitt
Schmitt
Schmitt
TTL
IRQ1
DRV4
TTL
IRQ2
DRV4
TTL
IRQ3
DRV4
TTL
Test/Configuration
SYS_PLL_TPA
TEST_MODE_0
TEST_MODE_1
TEST_SEL_0
TEST_SEL_1
JTAG_TCK
I/O
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
DRV4
DRV4
DRV4
DRV4
DRV8
DRV4
DRV4
DRV8
DRV4
DRV4
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
Input
Input
I/O
PULLUP
I/O
TCK
TDI
Input
Input
I/O
PULLUP
PULLUP
JTAG_TDI
JTAG_TDO
TDO
TMS
TRST
JTAG_TMS
Input
Input
PULLUP
PULLUP
JTAG_TRST
MPC5200 Data Sheet, Rev. 4
70
Freescale Semiconductor
System Design Information
Table 52. MPC5200 Pinout Listing (continued)
Output Driver
Input
Type
Pull-up/
down
Name
Alias
Type
Power Supply
Type
Power and Ground
VDD_IO
-
-
-
-
-
-
VDD_MEM_IO
VDD_CORE
VSS_IO/CORE
SYS_PLL_AVDD
CORE_PLL_AVDD
NOTES:
1
All “open drain” outputs of the MPC5200 are actually regular three-state output drivers with the output data tied low
and the output enable controlled. Thus, unlike a true open drain, there is a current path from the external system to
the MPC5200 I/O power rail if the external signal is driven above the MPC5200 I/O power rail voltage.
5 System Design Information
5.1 Power UP/Down Sequencing
Figure 52 shows situations in sequencing the I/O VDD (VDD_IO), Memory VDD (VDD_IO_MEM), PLL
VDD (PLL_AVDD), and Core VDD (VDD_CORE).
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
71
System Design Information
VDD_IO,
3.3V
2.5V
VDD_IO_MEM (SDR)
VDD_IO_MEM (DDR)
1
VDD_CORE,
PLL_AVDD
1.5V
2
0
Time
Note:
1. VDD_CORE should not exceed VDD_IO, VDD_IO_MEM or PLL_AVDD by more than
0.4 V at any time, including power-up.
2. It is recommended that VDD_CORE/PLL_AVDD should track VDD_IO/VDD_IO_MEM
up to 0.9 V then separate for completion of ramps.
3. Input voltage must not be greater than the supply voltage (VDD_IO, VDD_IO_MEM,
VDD_CORE, or PLL_AVDD) by more than 0.5 V at any time, including during power-up.
4. Use 1 microsecond or slower rise time for all supplies.
Figure 52. Supply Voltage Sequencing
The relationship between VDD_IO_MEM and VDD_IO is non-critical during power-up and power-down
sequences. Both VDD_IO_MEM (2.5 V or 3.3 V) and VDD_IO are specified relative to VDD_CORE.
5.1.1 Power Up Sequence
If VDD_IO/VDD_IO_MEM are powered up with the VDD_CORE at 0V, the sense circuits in the I/O pads
will cause all pad output drivers connected to the VDD_IO/VDD_IO_MEM to be in a high-impedance
state. There is no limit to how long after VDD_IO/VDD_IO_MEM powers up before VDD_CORE must
power up. VDD_CORE should not lead the VDD_IO, VDD_IO_MEM or PLL_AVDD by more than 0.4
V during power ramp up or there will be high current in the internal ESD protection diodes. The rise times
on the power supplies should be slower than 1 microsecond to avoid turning on the internal ESD protection
clamp diodes.
The recommended power up sequence is as follows:
Use one microsecond or slower rise time for all supplies.
MPC5200 Data Sheet, Rev. 4
72
Freescale Semiconductor
System Design Information
VDD_CORE/PLL_AVDD and VDD_IO/VDD_IO_MEM should track up to 0.9 V and then separate for
the completion of ramps with VDD_IO/VDD_IO_MEM going to the higher external voltages. One way
to accomplish this is to use a low drop-out voltage regulator.
5.1.2 Power Down Sequence
If VDD_CORE/PLL_AVDD are powered down first, then sense circuits in the I/O pads will cause all
output drivers to be in a high impedance state. There is no limit on how long after VDD_CORE and
PLL_AVDD power down before VDD_IO or VDD_IO_MEM must power down. VDD_CORE should not
lag VDD_IO, VDD_IO_MEM, or PLL_AVDD going low by more than 0.4V during power down or there
will be undesired high current in the ESD protection diodes. There are no requirements for the fall times
of the power supplies.
The recommended power down sequence is as follows:
Drop VDD_CORE/PLL_AVDD to 0V.
Drop VDD_IO/VDD_IO_MEM supplies.
5.2 System and CPU Core AVDD power supply filtering
Each of the independent PLL power supplies require filtering external to the device. The following
drawing is a recommendation for the required filter circuit.
< 1 Ω
10 Ω
Power
Supply
source
AVDD device pin
10 µF
200-400 pF
Figure 53. Power Supply Filtering
5.3 Pull-up/Pull-down Resistor Requirements
The MPC5200 requires external pull-up or pull-down resistors on certain pins.
5.3.1 Pull-down Resistor Requirements for TEST pins
The MPC5200 requires pull-down resistors on the test pins TEST_MODE_0, TEST_MODE_1,
TEST_SEL_1.
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
73
System Design Information
5.3.2 Pull-up Requirements for the PCI Control Lines
If the PCI interface is NOT used (and internally disabled) the PCI control pins must be terminated as
indicated by the PCI Local Bus specification [4]. This is also required for MOST/Graphics and Large Flash
Mode.
PCI control signals always require pull-up resistors on the motherboard (not the expansion board) to
ensure that they contain stable values when no agent is actively driving the bus. This includes
PCI_FRAME, PCI_TRDY, PCI_IRDY, PCI_DEVSEL, PCI_STOP, PCI_SERR, PCI_PERR, and
PCI_REQ.
5.3.3 Pull-up/Pull-down Requirements for MEM_MDQS pins
(SDRAM)
The MEM_MDQS[3:0] signals are not used with SDR memories and require pull-up or pull-down
resistors in SDRAM mode.
5.4 JTAG
The MPC5200 provides the user an IEEE 1149.1 JTAG interface to facilitate board/system testing. It also
provides a Common On-Chip Processor (COP) Interface, which shares the IEEE 1149.1 JTAG port. The
COP Interface provides access to the MPC5200's imbedded Freescale (formerly Motorola) MPC603e
G2_LE processor. This interface provides a means for executing test routines and for performing software
development & debug functions.
5.4.1 JTAG_TRST
Boundary scan testing is enabled through the JTAG interface signals. The JTAG_TRST signal is optional
in the IEEE 1149.1 specification but is provided on all processors that implement the PowerPC
architecture. To obtain a reliable power-on reset performance, the JTAG_TRST signal must be asserted
during power-on reset.
5.4.1.1 JTAG_TRST and PORRESET
The JTAG interface can control the direction of the MPC5200 I/O pads via the boundary scan chain. The
JTAG module must be reset before the MPC5200 comes out of power-on reset; do this by asserting
JTAG_TRST before PORRESET is released.
For more details refer to the Reset and JTAG Timing Specification.
MPC5200 Data Sheet, Rev. 4
74
Freescale Semiconductor
System Design Information
PORRESET
required assertion of JTAG_TRST
optional assertion of JTAG_TRST
JTAG_TRST
Figure 54. PORRESET vs. JTAG_TRST
5.4.1.2 Connecting JTAG_TRST
The wiring of the JTAG_TRST depends on the existence of a board-related debug interface (see Table 53
below).
Normally this interface is implemented, using a COP (common on-chip processor) connector. The COP
allows a remote computer system (typically, a PC with dedicated hardware and debugging software) to
access and control the internal operations of the MPC5200.
5.4.2 G2_LE COP/BDM Interface
There are two possibilities to connect the JTAG interface: using it with a COP connector and without a
COP connector.
5.4.2.1 Boards interfacing the JTAG port via a COP connector
The MPC5200 functional pin interface and internal logic provides access to the embedded G2_LE
processor core through the Freescale (formerly Motorola) standard COP/BDM interface. Table 53 gives
the COP/BDM interface signals. The pin order shown reflects only the COP/BDM connector order.
Table 53. COP/BDM Interface Signals
BDM
Pin #
MPC5200
I/O Pin
BDM
Connector
Internal
PullUp/Down
External
PullUp/Down
I/O1
16
15
14
13
12
11
10
9
—
TEST_SEL_0
—
GND
ckstp_out
KEY
—
—
—
—
—
I
—
—
—
O
—
O
—
O
HRESET
—
hreset
GND
10k Pull-Up
—
—
SRESET
—
sreset
N/C
10k Pull-Up
—
—
JTAG_TMS
tms
100k Pull-Up
10k Pull-Up
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
75
System Design Information
Table 53. COP/BDM Interface Signals (continued)
BDM
Pin #
MPC5200
I/O Pin
BDM
Connector
Internal
PullUp/Down
External
PullUp/Down
I/O1
8
7
6
—
JTAG_TCK
—
N/C
tck
—
—
—
O
—
I
100k Pull-Up
10k Pull-Up
VDD2
halted3
trst
—
—
5
4
3
2
1
See Note 3.
—
100k Pull-Up
100k Pull-Up
—
—
10k Pull-Up
10k Pull-Up
—
JTAG_TRST
JTAG_TDI
O
O
O
I
tdi
See Note 4.
qack4
JTAG_TDO
tdo
—
—
NOTES:
1
With respect to the emulator tool’s perspective:
Input is really an output from the embedded G2_LE core.
Output is really an input to the core.
From the board under test, power sense for chip power.
HALTED is not available from G2_LE core.
Input to the G2_LE core to enable/disable soft-stop condition during breakpoints. MPC5200
internal ties core_qack_ to GND in its normal/functional mode (always asserted).
2
3
4
For a board with a COP (common on-chip processor) connector, which accesses the JTAG interface and
which needs to reset the JTAG module, simply wiring JTAG_TRST and PORRESET is not recommended.
To reset the MPC5200 via the COP connector, the HRESET pin of the COP should be connected to the
HRESET pin of the MPC5200. The circuitry shown in Figure 55 allows the COP to assert HRESET or
JTAG_TRST separately, while any other board sources can drive PORRESET.
MPC5200 Data Sheet, Rev. 4
76
Freescale Semiconductor
System Design Information
PORRESET
PORRESET
HRESET
COP Header
MPC5200
10Kohm
HRESET
SRESET
VDD
13
11
16
VDD
10Kohm
10Kohm
SRESET
VDD
COP Connector
Physical Pinout
TRST
TMS
4
JTAG_TRST
1
3
5
7
9
2
4
Key 14
10Kohm
10Kohm
VDD
9
JTAG_TMS
6
12
8
TCK
VDD
VDD
7
10
2
JTAG_TCK
6
11 12
13
15 16
10Kohm
TDI
3
VDD
K
Key
JTAG_TDI
CKSTP_OUT
TDO
TEST_SEL_0
JTAG_TDO
15
1
halted
NC
3
5
qack
4
2
NC
NC
NC
10
8
Figure 55. COP Connector Diagram
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
77
System Design Information
5.4.2.2 Boards without COP connector
If the JTAG interface is not used, JTAG_TRST should be tied to PORRESET, so that it is asserted when
the system reset signal (PORRESET) is asserted. This ensures that the JTAG scan chain is initialized
during power on. Figure 56 shows the connection of the JTAG interface without COP connector.
PORRESET
PORRESET
HRESET
MPC5200
10Kohm
10Kohm
HRESET
SRESET
VDD
VDD
SRESET
JTAG_TRST
10Kohm
10Kohm
VDD
JTAG_TMS
VDD
JTAG_TCK
10Kohm
VDD
JTAG_TDI
TEST_SEL_0
JTAG_TDO
Figure 56. JTAG_TRST wiring for boards without COP connector
MPC5200 Data Sheet, Rev. 4
78
Freescale Semiconductor
Ordering Information
6 Ordering Information
Table 54. Ordering Information
Part Number
Speed Ambient Temp
Qualification
MPC5200BV400
MPC5200CBV266
MPC5200CBV400
SPC5200CBV400
400
266
400
400
0C to 70C
-40C to 85C
-40C to 85C
-40C to 85C
Commercial
Industrial
Industrial
Automotive - AEC
7 Document Revision History
Table 55 provides a revision history for this hardware specification.
Table 55. Document Revision History
Rev. No.
Substantive Change(s)
0.1
0.2
First Preliminary release with some TBD’s in spec tables (6/2003)
Added AC specs for missing modules, power-on sequence, misc other updates (7/2003)
Corrected maximum core operating frequency (7/2003)
0.2.1
0.3
Added Memory Interface Timing values, misc other updates (8/2003)
Added Information about JTAG_TRST (11/2003)
1.0
2.0
Added Power Numbers (Section 3.1.5), updated Oscillator and PLL Characteristics (Section 3.2), updated
SDRAM AC Characteristics (Section 3.3.5)
3.0
4.0
Change to Freescale brand and format (8/2004)
Updates to LPC timing, DDR SDRAM timing, JTAG section, replaced TBD’s (1/2005)
Rev 4 has been regenerated with the new Freescale appearance guidelines, the title was changed and
the reference to www.mobilegt.com in the first paragraph (Note) was changed to www. freescale.com
(3/2006).
For more detailed information, refer to the following documentation:
[1] MPC5200 User Manual MPC5200UM
[2] PowerPC Microprocessor Family: The Programming Environments for 32-bit Microprocessors,
Rev. 2: MPCFPE32B/AD
[3] G2 Core Reference Manual, Rev. 0: G2CORERM/D
[4] PCI Local Bus Specification, Revision 2.2, December 18, 1998
[5] ANSI ATA-4 Specification
[6] IEEE 802.3 Specification (ETHERNET)
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
79
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MPC5200
Rev. 4, 01/2005
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