SPC5604CFMMG6R_技术文档

NXP Semiconductors

Data Sheet: Technical Data

Document Number: MPC5604BC

Rev. 14, 11/2017

MPC5604B/C

Microcontroller Data Sheet

208 MAPBGA (17 x 17 x 1.7 mm)

144 LQFP (20 x 20 x 1.4 mm)

100 LQFP (14 x 14 x 1.4 mm)

64 LQFP (10 x 10 x 1.4 mm)

Features

• Up to 6 enhanced full CAN (FlexCAN) modules with

configurable buffers

• Single issue, 32-bit CPU core complex (e200z0)

– Compliant with the Power Architecture® embedded

category

• 1 inter IC communication interface (I2C) module

• Up to 123 configurable general purpose pins supporting

input and output operations (package dependent)

• Real Time Counter (RTC) with clock source from128 kHz

or 16 MHz internal RC oscillator supporting autonomous

wakeup with 1 ms resolution with max timeout of 2

seconds

– Includes an instruction set enhancement allowing

variable length encoding (VLE) for code size footprint

reduction. With the optional encoding of mixed 16-bit

and 32-bit instructions, it is possible to achieve

significant code size footprint reduction.

• Up to 512 KB on-chip code flash supported with the flash

controller and ECC

• Up to 6 periodic interrupt timers (PIT) with 32-bit counter

resolution

• 64 (4 × 16) KB on-chip data flash memory with ECC

• Up to 48 KB on-chip SRAM with ECC

• Memory protection unit (MPU) with 8 region descriptors

and 32-byte region granularity

• Interrupt controller (INTC) with 148 interrupt vectors,

including 16 external interrupt sources and 18 external

interrupt/wakeup sources

• 1 System Module Timer (STM)

• Nexus development interface (NDI) per IEEE-ISTO

5001-2003 Class Two Plus standard

• Device/board boundary Scan testing supported with per

Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1)

• On-chip voltage regulator (VREG) for regulation of

input supply for all internal levels

• Frequency modulated phase-locked loop (FMPLL)

• Crossbar switch architecture for concurrent access to

peripherals, flash memory, or RAM from multiple bus

masters

• Boot assist module (BAM) supports internal flash

programming via a serial link (CAN or SCI)

• Timer supports input/output channels providing a range of

16-bit input capture, output compare, and pulse width

modulation functions (eMIOS-lite)

• 10-bit analog-to-digital converter (ADC)

• 3 serial peripheral interface (DSPI) modules

• Up to 4 serial communication interface (LINFlex)

modules

NXP reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

Table of Contents

1, Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2.19.1 Program/Erase characteristics . . . . . . . . . . . . . 59

2.19.2 Flash power supply DC characteristics . . . . . . 60

2.19.3 Start-up/Switch-off timings . . . . . . . . . . . . . . . . 61

2.20 Electromagnetic compatibility (EMC) characteristics. . 61

2.20.1 Designing hardened software to avoid noise

problems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

2.20.2 Electromagnetic interference (EMI) . . . . . . . . . 62

2.20.3 Absolute maximum ratings (electrical sensitivity)62

2.21 Fast external crystal oscillator (4 to 16 MHz) electrical

characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

2.22 Slow external crystal oscillator (32 kHz) electrical

characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

2.23 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 68

2.24 Fast internal RC oscillator (16 MHz) electrical

characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

2.25 Slow internal RC oscillator (128 kHz) electrical

characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

1.1 Document overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

1.3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Package pinouts and signal descriptions . . . . . . . . . . . . . . . . .7

2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

2.2 Pad configuration during reset phases . . . . . . . . . . . . .11

2.3 Voltage supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

2.4 Pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

2.5 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

2.6 Functional ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

2.7 Nexus 2+ pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

2.8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . .31

2.9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

2.10 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . .31

2.11 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

2.11.1 NVUSRO[PAD3V5V] field description . . . . . . . .32

2.11.2 NVUSRO[OSCILLATOR_MARGIN] field description

32

2

2.26 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . 72

2.26.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

2.26.2 Input impedance and ADC accuracy . . . . . . . . 72

2.26.3 ADC electrical characteristics . . . . . . . . . . . . . 77

2.27 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

2.27.1 Current consumption . . . . . . . . . . . . . . . . . . . . 79

2.27.2 DSPI characteristics. . . . . . . . . . . . . . . . . . . . . 80

2.27.3 Nexus characteristics . . . . . . . . . . . . . . . . . . . . 86

2.27.4 JTAG characteristics. . . . . . . . . . . . . . . . . . . . . 87

Package characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

3.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . 88

3.1.1 64 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

3.1.2 100 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

3.1.3 144 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

3.1.4 208 MAPBGA. . . . . . . . . . . . . . . . . . . . . . . . . . 97

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . 99

2.11.3 NVUSRO[WATCHDOG_EN] field description . .32

2.12 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .33

2.13 Recommended operating conditions . . . . . . . . . . . . . .34

2.14 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .36

2.14.1 Package thermal characteristics . . . . . . . . . . . .36

2.14.2 Power considerations. . . . . . . . . . . . . . . . . . . . .37

2.15 I/O pad electrical characteristics. . . . . . . . . . . . . . . . . .37

2.15.1 I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . .37

2.15.2 I/O input DC characteristics. . . . . . . . . . . . . . . .38

2.15.3 I/O output DC characteristics. . . . . . . . . . . . . . .39

2.15.4 Output pin transition times. . . . . . . . . . . . . . . . .42

2.15.5 I/O pad current specification . . . . . . . . . . . . . . .42

2.16 RESET electrical characteristics. . . . . . . . . . . . . . . . . .48

2.17 Power management electrical characteristics. . . . . . . .51

2.17.1 Voltage regulator electrical characteristics . . . .51

2.17.2 Low voltage detector electrical characteristics .56

2.18 Power consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . .58

2.19 Flash memory electrical characteristics . . . . . . . . . . . .59

3

4

5

MPC5604B/C Microcontroller Data Sheet, Rev. 14

2

NXP Semiconductors

Introduction

1.3

Block diagram

Figure 1 shows a top-level block diagram of the MPC5604B/C device series.

SRAM

48 KB

Code Flash Data Flash

512 KB 64 KB

JTAG

JTAG port

Instructions

Nexus port

SRAM

Flash

controller

e200z0h

Nexus 2+

(Master)

Nexus

controller

Data

NMI

(Slave)

(Master)

SIUL

Voltage

regulator

(Slave)

Interrupt requests

from peripheral

blocks

(Slave)

NMI

MPU

registers

INTC

Clocks

CMU

FMPLL

RTC

MC_RGM MC_CGM MC_ME MC_PCU

SSCM

STM

PIT

BAM

SWT

ECSM

Peripheral bridge

SIUL

36 Ch.

ADC

2 x

eMIOS

4 x

LINFlex

3 x

DSPI

6 x

FlexCAN

2

CTU

I C

Reset control

Interrupt

request

External

interrupt

request

IMUX

WKPU

GPIO and

pad control

Interrupt

request with

wakeup

. . .

I/O

functionality

Legend:

ADC

BAM

Analog-to-Digital Converter

Boot Assist Module

MC_ME

MC_PCU Power Control Unit

MC_RGM Reset Generation Module

Mode Entry Module

FlexCAN Controller Area Network

CMU

CTU

DSPI

Clock Monitor Unit

Cross Triggering Unit

Deserial Serial Peripheral Interface

MPU

Nexus

NMI

Memory Protection Unit

Nexus Development Interface (NDI) Level

Non-Maskable Interrupt

eMIOS

FMPLL

I C

IMUX

INTC

JTAG

Enhanced Modular Input Output System

Frequency-Modulated Phase-Locked Loop

Inter-integrated Circuit Bus

Internal Multiplexer

Interrupt Controller

PIT

RTC

SIUL

SRAM

SSCM

STM

Periodic Interrupt Timer

Real-Time Clock

System Integration Unit Lite

Static Random-Access Memory

System Status Configuration Module

System Timer Module

2

JTAG controller

LINFlex

ECSM

Serial Communication Interface (LIN support)

Error Correction Status Module

SWT

WKPU

Software Watchdog Timer

Wakeup Unit

MC_CGM Clock Generation Module

Figure 1. Block diagram

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

5

Introduction

Table 2 summarizes the functions of all blocks present in the MPC5604B/C series of microcontrollers.

Please note that the presence and number of blocks vary by device and package.

Table 2. MPC5604B/C series block summary

Block

Function

Analog-to-digital converter (ADC) Multi-channel, 10-bit analog-to-digital converter

Boot assist module (BAM)

A block of read-only memory containing VLE code which is executed according

to the boot mode of the device

Clock monitor unit (CMU)

Cross triggering unit (CTU)

Monitors clock source (internal and external) integrity

Enables synchronization of ADC conversions with a timer event from the eMIOS

or from the PIT

Deserial serial peripheral interface Provides a synchronous serial interface for communication with external devices

(DSPI)

Error Correction Status Module

(ECSM)

Provides a myriad of miscellaneous control functions for the device including

program-visible information about configuration and revision levels, a reset status

register, wakeup control for exiting sleep modes, and optional features such as

information on memory errors reported by error-correcting codes

Enhanced Direct Memory Access Performs complex data transfers with minimal intervention from a host processor

(eDMA)

via “n” programmable channels.

Enhanced modular input output

system (eMIOS)

Provides the functionality to generate or measure events

Flash memory

Provides non-volatile storage for program code, constants and variables

FlexCAN (controller area network) Supports the standard CAN communications protocol

Frequency-modulated

Generates high-speed system clocks and supports programmable frequency

phase-locked loop (FMPLL)

modulation

Internal multiplexer (IMUX) SIU

subblock

Allows flexible mapping of peripheral interface on the different pins of the device

Inter-integrated circuit (I²C™) bus A two wire bidirectional serial bus that provides a simple and efficient method of

data exchange between devices

Interrupt controller (INTC)

JTAG controller

Provides priority-based preemptive scheduling of interrupt requests

Provides the means to test chip functionality and connectivity while remaining

transparent to system logic when not in test mode

LINFlex controller

Manages a high number of LIN (Local Interconnect Network protocol) messages

efficiently with a minimum of CPU load

Clock generation module

(MC_CGM)

Provides logic and control required for the generation of system and peripheral

clocks

Mode entry module (MC_ME)

Provides a mechanism for controlling the device operational mode and mode

transition sequences in all functional states; also manages the power control unit,

reset generation module and clock generation module, and holds the

configuration, control and status registers accessible for applications

Power control unit (MC_PCU)

Reduces the overall power consumption by disconnecting parts of the device

from the power supply via a power switching device; device components are

grouped into sections called “power domains” which are controlled by the PCU

Reset generation module

(MC_RGM)

Centralizes reset sources and manages the device reset sequence of the device

MPC5604B/C Microcontroller Data Sheet, Rev. 14

6

NXP Semiconductors

Package pinouts and signal descriptions

Table 2. MPC5604B/C series block summary (continued)

Block

Function

Memory protection unit (MPU)

Provides hardware access control for all memory references generated in a

device

Nexus development interface

(NDI)

Provides real-time development support capabilities in compliance with the

IEEE-ISTO 5001-2003 standard

Periodic interrupt timer (PIT)

Real-time counter (RTC)

Produces periodic interrupts and triggers

A free running counter used for time keeping applications, the RTC can be

configured to generate an interrupt at a predefined interval independent of the

mode of operation (run mode or low-power mode)

System integration unit (SIU)

Provides control over all the electrical pad controls and up 32 ports with 16 bits

of bidirectional, general-purpose input and output signals and supports up to 32

external interrupts with trigger event configuration

Static random-access memory

(SRAM)

Provides storage for program code, constants, and variables

System status configuration

module (SSCM)

Provides system configuration and status data (such as memory size and status,

device mode and security status), device identification data, debug status port

enable and selection, and bus and peripheral abort enable/disable

System timer module (STM)

Provides a set of output compare events to support AUTOSAR (Automotive Open

System Architecture) and operating system tasks

Software watchdog timer (SWT) Provides protection from runaway code

Wakeup unit (WKPU)

The wakeup unit supports up to 18 external sources that can generate interrupts

or wakeup events, of which 1 can cause non-maskable interrupt requests or

wakeup events.

Crossbar (XBAR) switch

Supports simultaneous connections between two master ports and three slave

ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus

width.

2

Package pinouts and signal descriptions

2.1

Package pinouts

The available LQFP pinouts and the 208 MAPBGA ballmap are provided in the following figures. For pin signal descriptions,

please refer to the device reference manual.

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

7

Package pinouts and signal descriptions

48 PA[11]

47 PA[10]

46 PA[9]

PB[3]

PC[9]

PA[2]

PA[1]

PA[0]

1

2

3

45 PA[8]

4

44 PA[7]

43 PA[3]

5

VSS_HV

VDD_HV

VSS_HV

RESET

VSS_LV

VDD_LV

VDD_BV

PC[10]

6

42 PB[15]

41 PB[14]

40 PB[13]

39 PB[12]

38 PB[11]

37 PB[7]

7

8

64 LQFP

Top view

9

10

11

12

13

14

15

16

36 PB[6]

35 PB[5]

34 VDD_HV_ADC

33 VSS_HV_ADC

PB[0]

PB[1]

PC[6]

Figure 2. MPC560xB LQFP 64-pin configuration

48 PA[11]

47 PA[10]

46 PA[9]

PB[3]

PC[9]

1

2

PA[2]

3

45 PA[8]

PA[1]

PA[0]

4

44 PA[7]

5

43 PF[14]

42 PF[15]

41 PG[0]

VSS_HV

VDD_HV

VSS_HV

RESET

VSS_LV

VDD_LV

VDD_BV

PC[10]

PB[0]

6

7

8

64 LQFP

Top view

40 PG[1]

39 PA[3]

38 PB[15]

37 PB[14]

36 PB[11]

35 PB[7]

9

10

11

12

13

14

15

16

PB[1]

PC[6]

34 VDD_HV_ADC

33 VSS_HV_ADC

Figure 3. MPC560xC LQFP 64-pin configuration

MPC5604B/C Microcontroller Data Sheet, Rev. 14

8

NXP Semiconductors

Package pinouts and signal descriptions

PB[3]

PC[9]

PC[14]

PC[15]

PA[2]

PE[0]

PA[1]

PE[1]

PE[8]

1

2

3

4

5

6

7

8

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

PA[11]

PA[10]

PA[9]

PA[8]

PA[7]

VDD_HV

VSS_HV

PA[3]

9

PB[15]

PD[15]

PB[14]

PD[14]

PB[13]

PD[13]

PB[12]

PD[12]

PB[11]

PD[11]

PD[10]

PD[9]

PB[7]

PB[6]

PB[5]

VDD_HV_ADC

VSS_HV_ADC

PE[9]

PE[10]

PA[0]

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

PE[11]

VSS_HV

VDD_HV

VSS_HV

RESET

VSS_LV

VDD_LV

VDD_BV

PC[11]

PC[10]

PB[0]

100 LQFP

Top view

PB[1]

PC[6]

Note:

Availability of port pin alternate functions depends on product selection.

Figure 4. LQFP 100-pin configuration

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

9

Package pinouts and signal descriptions

PB[3]

PC[9]

PC[14]

PC[15]

PG[5]

PG[4]

PG[3]

PG[2]

PA[2]

PE[0]

PA[1]

PE[1]

PE[8]

PE[9]

PE[10]

PA[0]

PE[11]

VSS_HV

VDD_HV

VSS_HV

RESET

VSS_LV

VDD_LV

VDD_BV

PG[9]

1

2

3

4

5

6

7

8

108

107

106

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

PA[11]

PA[10]

PA[9]

PA[8]

PA[7]

PE[13]

PF[14]

PF[15]

VDD_HV

VSS_HV

PG[0]

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

PG[1]

PH[3]

PH[2]

PH[1]

PH[0]

PG[12]

PG[13]

PA[3]

144 LQFP

Top view

PB[15]

PD[15]

PB[14]

PD[14]

PB[13]

PD[13]

PB[12]

PD[12]

PB[11]

PD[11]

PD[10]

PD[9]

PB[7]

PB[6]

PB[5]

VDD_HV_ADC

VSS_HV_ADC

PG[8]

PC[11]

PC[10]

PG[7]

PG[6]

PB[0]

PB[1]

PF[9]

PF[8]

PF[12]

PC[6]

74

73

Note:

Availability of port pin alternate functions depends on product selection.

Figure 5. LQFP 144-pin configuration

MPC5604B/C Microcontroller Data Sheet, Rev. 14

10

NXP Semiconductors

Package pinouts and signal descriptions

1

2

3

4

NC

5

6

7

8

9

10

NC

11

12

NC

13

PE[15]

PG[15]

PE[14]

PG[10]

PG[1]

PH[0]

VDD_HV

MDO3

NC

14

15

NC

16

NC

PC[8]

PC[9]

PC[13]

PB[2]

NC

PH[8]

PE[6]

PH[7]

PH[6]

PH[4]

PH[5]

PE[5]

PE[4]

PC[5]

PC[4]

PE[3]

PE[2]

PC[0]

PH[9]

VSS_LV

NC

PC[2]

PC[3]

PA[5]

PA[6]

NC

A

B

C

D

E

F

A

B

C

D

E

F

NC

PC[12]

PE[7]

NC

PH[10]

PC[1]

PG[11]

NC

PG[14]

PE[12]

PF[14]

PG[0]

PH[1]

NC

PA[11]

PA[9]

PE[13]

PA[10]

PA[8]

PA[7]

PC[14] VDD_HV

PB[3]

PC[15]

PG[3]

PA[1]

PE[10]

NC

VDD_LV VDD_HV

NC

PG[4]

PE[0]

PE[9]

PG[5]

PA[2]

PE[8]

PG[2]

PE[1]

PA[0]

NC

PF[15] VDD_HV

PH[3]

NC

PH[2]

MSEO

MDO1

NC

VSS_HV VSS_HV VSS_HV VSS_HV

G

H

J

G

H

J

VSS_HV PE[11] VDD_HV

MDO2

NC

MDO0

NC

RESET VSS_LV

NC

EVTI

PG[9]

PG[7]

PB[1]

PF[8]

PF[12]

NC

PG[8]

PG[6]

PF[9]

NC

VDD_BV VDD_LV

NC

PG[12]

PD[15]

PD[13]

PD[10]

PA[3]

PD[14]

PD[12]

PD[9]

PB[6]

PG[13]

PB[14]

PB[12]

PD[11]

PB[7]

PB[5]

PB[4]

16

K

L

K

L

NC

PC[10]

PB[0]

PC[7]

PF[10]

NC

EVTO

PC[11]

NC

PB[15]

PB[13]

PB[11]

PD[3]

PD[4]

PD[5]

13

M

N

P

R

T

M

N

P

R

T

NC

PA[4]

VSS_LV

VDD_LV

PA[13]

PA[12]

7

EXTAL VDD_HV

PF[0]

PF[1]

PF[3]

PF[2]

10

PF[4]

PF[5]

PF[7]

PF[6]

11

NC

VDD_HV

_ADC

NC

PA[14]

XTAL

NC

8

PB[10]

PD[0]

PD[2]

PD[1]

12

OSC32K

_XTAL

VSS_HV

_ADC

PC[6]

NC

PF[11] VDD_HV PA[15]

PD[7]

PD[6]

OSC32K

_EXTAL

MCKO

NC

PF[13]

PD[8]

1

2

3

4

5

6

9

14

15

NC

Note: 208 MAPBGA available only as development package for Nexus 2+.

= Not connected

Figure 6. 208 MAPBGA configuration

2.2

Pad configuration during reset phases

All pads have a fixed configuration under reset.

During the power-up phase, all pads are forced to tristate.

After power-up phase, all pads are forced to tristate with the following exceptions:

•

PA[9] (FAB) is pull-down. Without external strong pull-up the device starts fetching from flash.

PA[8] (ABS[0]) is pull-up.

RESET pad is driven low. This is pull-up only after PHASE2 reset completion.

JTAG pads (TCK, TMS and TDI) are pull-up whilst TDO remains tristate.

Precise ADC pads (PB[7:4] and PD[11:0]) are left tristate (no output buffer available).

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

11

Package pinouts and signal descriptions

•

Main oscillator pads (EXTAL, XTAL) are tristate.

Nexus output pads (MDO[n], MCKO, EVTO, MSEO) are forced to output.

2.3

Voltage supply pins

Voltage supply pins are used to provide power to the device. Three dedicated VDD_LV/VSS_LV supply

pairs are used for 1.2 V regulator stabilization.

Table 3. Voltage supply pin descriptions

Pin number

Port pin

Function

208

64 LQFP¹

100 LQFP

144 LQFP

MAPBGA²

VDD_HV

Digital supply voltage

7, 28, 56 15, 37, 70, 84 19, 51, 100, C2, D9, E16,

123

G13, H3, N9,

R5

VSS_HV

Digital ground

6, 8, 26, 55

14, 16, 35,

69, 83

18, 20, 49, G7, G8, G9,

99, 122

G10, H1, H7,

H8, H9, H10,

J7, J8, J9,

J10, K7, K8,

K9, K10

VDD_LV

VSS_LV

VDD_BV

1.2V decoupling pins. Decoupling

11, 23, 57

10, 24, 58

19, 32, 85

18, 33, 86

23, 46, 124 D8, K4, P7

capacitor must be connected between

these pins and the nearest V_{SS_LV}pin.³

1.2V decoupling pins. Decoupling

22, 47, 125

C8, J2, N7

capacitor must be connected between

these pins and the nearest V_{DD_LV}pin.³

Internal regulator supply voltage

12

33

20

51

24

73

K3

VSS_HV_ADC Reference ground and analog ground for

the ADC

R15

VDD_HV_ADC Reference voltage and analog supply for

the ADC

34

52

74

P14

1

2

3

Pin numbers apply to both the MPC560xB and MPC560xC packages.

208 MAPBGA available only as development package for Nexus2+

A decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable

voltage (see the recommended operating conditions in the device datasheet for details).

2.4

Pad types

In the device the following types of pads are available for system pins and functional port pins:

1

S = Slow

1 2

M = Medium

1 2

F = Fast

1. See the I/O pad electrical characteristics in the device datasheet for details.

2. All medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium (see PCR.SRC

in section Pad Configuration Registers (PCR0–PCR122) in the device reference manual).

MPC5604B/C Microcontroller Data Sheet, Rev. 14

12

NXP Semiconductors

Package pinouts and signal descriptions

1

I = Input only with analog feature

J = Input/Output (‘S’ pad) with analog feature

X = Oscillator

2.5

System pins

The system pins are listed in Table 4.

Table 4. System pin descriptions

Pin number

Function

RESET Bidirectional reset with Schmitt-Trigger characteristics

and noise filter.

I/O

M

X

Input, weak

pull-up only

after PHASE2

9

17 21 J1

EXTAL Analog output of the oscillator amplifier circuit, when the I/O

oscillator is not in bypass mode.

Tristate

27 36 50 N8

Analog input for the clock generator when the oscillator is

in bypass mode.³

XTAL Analog input of the oscillator amplifier circuit. Needs to be

grounded if oscillator is used in bypass mode.³

I

X

Tristate

25 34 48 P8

1

2

3

Pin numbers apply to both the MPC560xB and MPC560xC packages.

208 MAPBGA available only as development package for Nexus2+

See the relevant section of the datasheet

2.6

Functional ports

The functional port pins are listed in Table 5.

Table 5. Functional port pin descriptions

Pin number

PA[0]

PCR[0] AF0

GPIO[0]

E0UC[0]

CLKOUT

—

SIUL

eMIOS_0 I/O

CGL

—

WKPU

I/O

M

Tristate

5

12 16 G4

AF1

AF2

AF3

—

O

—

I

WKPU[19]⁴

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

13

Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

PA[1]

PCR[1] AF0

GPIO[1]

E0UC[1]

—

SIUL

eMIOS_0 I/O

—

WKPU

I/O

S

Tristate

4

3

4

3

7

5

11 F3

AF1

AF2

AF3

—

I

—

NMI⁵

—

WKPU[2]⁴

I

PA[2]

PA[3]

PA[4]

PCR[2] AF0

GPIO[2]

E0UC[2]

—

SIUL

eMIOS_0 I/O

—

WKPU

I/O

S

Tristate

9

F2

AF1

AF2

AF3

—

I

—

WKPU[3]⁴

PCR[3] AF0

GPIO[3]

E0UC[3]

—

EIRQ[0]

SIUL

eMIOS_0 I/O

—

SIUL

I/O

43 39 68 90 K15

AF1

AF2

AF3

—

I

PCR[4] AF0

GPIO[4]

E0UC[4]

—

SIUL

eMIOS_0 I/O

—

WKPU

I/O

20 20 29 43 N6

AF1

AF2

AF3

—

I

—

WKPU[9]⁴

PA[5]

PA[6]

PCR[5] AF0

GPIO[5]

E0UC[5]

—

SIUL

eMIOS_0 I/O

I/O

M

S

Tristate

51 51 79 118 C11

52 52 80 119 D11

AF1

AF2

AF3

—

PCR[6] AF0

GPIO[6]

E0UC[6]

—

EIRQ[1]

SIUL

eMIOS_0 I/O

—

SIUL

I/O

AF1

AF2

AF3

—

I

PA[7]

PCR[7] AF0

GPIO[7]

E0UC[7]

LIN3TX

—

SIUL

eMIOS_0 I/O

LINFlex_3

—

I/O

S

Tristate

44 44 71 104 D16

AF1

AF2

AF3

—

O

—

I

EIRQ[2]

SIUL

MPC5604B/C Microcontroller Data Sheet, Rev. 14

14

NXP Semiconductors

Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

PA[8]

PA[9]

PCR[8] AF0

GPIO[8]

E0UC[8]

—

SIUL

eMIOS_0 I/O

—

SIUL

I/O

S

Input, weak 45 45 72 105 C16

pull-up

AF1

AF2

AF3

—

I

—

EIRQ[3]

ABS[0]

LIN3RX

N/A⁶

—

BAM

LINFlex_3

PCR[9] AF0

AF1

GPIO[9]

E0UC[9]

—

FAB

SIUL

eMIOS_0 I/O

—

BAM

I/O

Pull-down

46 46 73 106 C15

AF2

—

I

AF3

N/A⁶

PA[10] PCR[10] AF0

GPIO[10]

E0UC[10]

SDA

SIUL

eMIOS_0 I/O

I2C_0

—

I/O

S

Tristate

47 47 74 107 B16

48 48 75 108 B15

22 22 31 45 T7

AF1

AF2

AF3

I/O

—

PA[11] PCR[11] AF0

GPIO[11]

E0UC[11]

SCL

SIUL

eMIOS_0 I/O

I2C_0

—

I/O

AF1

AF2

AF3

I/O

—

PA[12] PCR[12] AF0

GPIO[12]

—

SIN_0

SIUL

—

DSPI0

I/O

—

I

AF1

AF2

AF3

—

PA[13] PCR[13] AF0

GPIO[13]

SOUT_0

—

SIUL

DSPI_0

—

I/O

O

—

M

Tristate

21 21 30 44 R7

AF1

AF2

AF3

—

PA[14] PCR[14] AF0

GPIO[14]

SCK_0

CS0_0

—

SIUL

DSPI_0

—

I/O

—

I

19 19 28 42 P6

AF1

AF2

AF3

—

EIRQ[4]

SIUL

PA[15] PCR[15] AF0

GPIO[15]

CS0_0

SIUL

DSPI_0

—

I/O

—

I

M

Tristate

18 18 27 40 R6

AF1

AF2

AF3

—

SCK_0

—

WKPU[10]⁴

WKPU

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

15

Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

PB[0]

PB[1]

PCR[16] AF0

GPIO[16]

CAN0TX

—

SIUL

FlexCAN_0

I/O

O

—

M

S

Tristate

14 14 23 31 N3

AF1

AF2

AF3

—

PCR[17] AF0

GPIO[17]

—

SIUL

—

I/O

—

I

15 15 24 32 N1

AF1

AF2

AF3

—

WKPU[4]⁴

CAN0RX

WKPU

FlexCAN_0

—

I

PB[2]

PB[3]

PCR[18] AF0

GPIO[18]

LIN0TX

SDA

SIUL

LINFlex_0

I2C_0

—

I/O

O

I/O

—

M

S

Tristate

64 64 100 144 B2

AF1

AF2

AF3

—

PCR[19] AF0

GPIO[19]

—

SIUL

—

I2C_0

—

WKPU

LINFlex_0

I/O

—

I/O

—

I

1

C3

AF1

AF2

AF3

—

SCL

—

WKPU[11]⁴

LIN0RX

—

I

PB[4]

PB[5]

PB[6]

PB[7]

PCR[20] AF0

GPIO[20]

—

GPI[0]

SIUL

—

ADC

I

Tristate

32 32 50 72 T16

AF1

AF2

AF3

—

I

PCR[21] AF0

GPIO[21]

—

GPI[1]

SIUL

—

ADC

I

35

36

—

53 75 R16

AF1

AF2

AF3

—

I

PCR[22] AF0

GPIO[22]

—

GPI[2]

SIUL

—

ADC

I

54 76 P15

AF1

AF2

AF3

—

I

PCR[23] AF0

GPIO[23]

—

GPI[3]

SIUL

—

ADC

I

37 35 55 77 P16

AF1

AF2

AF3

—

I

MPC5604B/C Microcontroller Data Sheet, Rev. 14

16

NXP Semiconductors

Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

PB[8]

PB[9]

PCR[24] AF0

GPIO[24]

SIUL

—

ADC

SXOSC

I

Tristate

30 30 39 53 R9

29 29 38 52 T9

31 31 40 54 P9

38 36 59 81 N13

AF1

AF2

AF3

—

I

ANS[0]

—

OSC32K_XTAL⁷

I/O

PCR[25] AF0

GPIO[25]

SIUL

—

ADC

SXOSC

I

AF1

AF2

AF3

—

I

ANS[1]

—

OSC32K_EXTAL⁷

I/O

PB[10] PCR[26] AF0

GPIO[26]

—

SIUL

—

ADC

WKPU

I/O

—

I

J

AF1

AF2

AF3

—

ANS[2]

—

WKPU[8]⁴

I

PB[11]⁸PCR[27] AF0

GPIO[27]

E0UC[3]

—

CS0_0

ANS[3]

SIUL

eMIOS_0 I/O

—

DSPI_0

ADC

I/O

J

Tristate

AF1

AF2

AF3

—

I/O

I

PB[12] PCR[28] AF0

GPIO[28]

E0UC[4]

—

CS1_0

ANX[0]

SIUL

eMIOS_0 I/O

—

DSPI_0

ADC

I/O

39

40

—

61 83 M16

AF1

AF2

AF3

—

O

I

PB[13] PCR[29] AF0

GPIO[29]

E0UC[5]

—

CS2_0

ANX[1]

SIUL

eMIOS_0 I/O

—

DSPI_0

ADC

I/O

63 85 M13

AF1

AF2

AF3

—

O

I

PB[14] PCR[30] AF0

GPIO[30]

E0UC[6]

—

CS3_0

ANX[2]

SIUL

eMIOS_0 I/O

—

DSPI_0

ADC

I/O

41 37 65 87 L16

AF1

AF2

AF3

—

O

I

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

17

Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

PB[15] PCR[31] AF0

GPIO[31]

E0UC[7]

—

CS4_0

ANX[3]

SIUL

eMIOS_0 I/O

—

DSPI_0

ADC

I/O

J

Tristate

42 38 67 89 L13

AF1

AF2

AF3

—

O

I

PC[0]⁹PCR[32] AF0

GPIO[32]

SIUL

—

JTAGC

—

I/O

—

I

M

Input, weak 59 59 87 126 A8

pull-up

AF1

AF2

AF3

—

TDI

—

PC[1]⁹PCR[33] AF0

GPIO[33]

—

SIUL

—

JTAGC

—

I/O

—

O

Tristate

54 54 82 121 C9

AF1

AF2

AF3

TDO¹⁰

—

PC[2]

PC[3]

PCR[34] AF0

GPIO[34]

SCK_1

CAN4TX¹¹

—

SIUL

DSPI_1

FlexCAN_4

—

I/O

O

—

I

50 50 78 117 A11

AF1

AF2

AF3

—

EIRQ[5]

SIUL

PCR[35] AF0

GPIO[35]

CS0_1

MA[0]

SIUL

DSPI_1

ADC

I/O

O

—

I

S

Tristate

49 49 77 116 B11

AF1

AF2

AF3

—

CAN1RX

CAN4RX¹¹

EIRQ[6]

FlexCAN_1

FlexCAN_4

SIUL

I

PC[4]

PCR[36] AF0

GPIO[36]

SIUL

—

I/O

—

I

M

62 62 92 131 B7

AF1

AF2

AF3

—

SIN_1

DSPI_1

FlexCAN_3

—

CAN3RX¹¹

I

PC[5]

PC[6]

PCR[37] AF0

GPIO[37]

SOUT_1

CAN3TX¹¹

—

SIUL

DSPI1

FlexCAN_3

—

I/O

O

—

I

M

S

Tristate

61 61 91 130 A7

AF1

AF2

AF3

—

EIRQ[7]

SIUL

PCR[38] AF0

GPIO[38]

LIN1TX

—

SIUL

LINFlex_1

—

I/O

O

—

16 16 25 36 R2

AF1

AF2

AF3

—

MPC5604B/C Microcontroller Data Sheet, Rev. 14

18

NXP Semiconductors

Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

PC[7]

PCR[39] AF0

GPIO[39]

SIUL

—

I/O

—

I

S

Tristate

17 17 26 37 P3

AF1

AF2

AF3

—

LIN1RX

LINFlex_1

WKPU

—

WKPU[12]⁴

I

PC[8]

PC[9]

PCR[40] AF0

GPIO[40]

LIN2TX

—

SIUL

LINFlex_2

—

I/O

O

—

S

Tristate

63 63 99 143 A1

AF1

AF2

AF3

—

PCR[41] AF0

GPIO[41]

SIUL

—

I/O

—

I

2

B1

AF1

AF2

AF3

—

LIN2RX

LINFlex_2

WKPU

—

WKPU[13]⁴

I

PC[10] PCR[42] AF0

GPIO[42]

CAN1TX

CAN4TX¹¹

MA[1]

SIUL

FlexCAN_1

FlexCAN_4

ADC

I/O

O

M

S

Tristate

13 13 22 28 M3

AF1

AF2

AF3

O

PC[11] PCR[43] AF0

GPIO[43]

—

SIUL

—

I/O

—

I

—

21 27 M4

AF1

AF2

AF3

—

CAN1RX

CAN4RX¹¹

WKPU[5]⁴

FlexCAN_1

FlexCAN_4

WKPU

I

PC[12] PCR[44] AF0

GPIO[44]

E0UC[12]

—

SIN_2

SIUL

eMIOS_0 I/O

—

DSPI_2

I/O

M

Tristate

97 141 B4

AF1

AF2

AF3

—

I

PC[13] PCR[45] AF0

GPIO[45]

E0UC[13]

SOUT_2

—

SIUL

eMIOS_0 I/O

DSPI_2

—

I/O

S

Tristate

—

98 142 A2

AF1

AF2

AF3

O

—

PC[14] PCR[46] AF0

GPIO[46]

E0UC[14]

SCK_2

—

SIUL

eMIOS_0 I/O

DSPI_2

—

SIUL

I/O

3

C1

AF1

AF2

AF3

—

I/O

—

I

EIRQ[8]

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

19

Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

PC[15] PCR[47] AF0

GPIO[47]

E0UC[15]

CS0_2

—

SIUL

eMIOS_0 I/O

DSPI_2

—

I/O

M

I

Tristate

—

4

D3

AF1

AF2

AF3

I/O

—

PD[0]

PD[1]

PD[2]

PD[3]

PD[4]

PD[5]

PD[6]

PCR[48] AF0

GPIO[48]

—

GPI[4]

SIUL

—

ADC

I

41 63 P12

42 64 T12

43 65 R12

44 66 P13

45 67 R13

46 68 T13

47 69 T14

AF1

AF2

AF3

—

I

PCR[49] AF0

GPIO[49]

—

GPI[5]

SIUL

—

ADC

I

Tristate

—

AF1

AF2

AF3

—

I

PCR[50] AF0

GPIO[50]

—

GPI[6]

SIUL

—

ADC

I

AF1

AF2

AF3

—

I

PCR[51] AF0

GPIO[51]

—

GPI[7]

SIUL

—

ADC

I

AF1

AF2

AF3

—

I

PCR[52] AF0

GPIO[52]

—

GPI[8]

SIUL

—

ADC

I

AF1

AF2

AF3

—

I

PCR[53] AF0

GPIO[53]

—

GPI[9]

SIUL

—

ADC

I

AF1

AF2

AF3

—

I

PCR[54] AF0

GPIO[54]

SIUL

—

ADC

I

AF1

AF2

AF3

—

I

GPI[10]

MPC5604B/C Microcontroller Data Sheet, Rev. 14

20

NXP Semiconductors

Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

PD[7]

PD[8]

PD[9]

PCR[55] AF0

GPIO[55]

SIUL

—

ADC

I

Tristate

—

48 70 R14

49 71 T15

56 78 N15

57 79 N14

58 80 N16

60 82 M15

62 84 M14

64 86 L15

AF1

AF2

AF3

—

I

GPI[11]

PCR[56] AF0

GPIO[56]

SIUL

—

ADC

I

—

AF1

AF2

AF3

—

I

GPI[12]

PCR[57] AF0

GPIO[57]

SIUL

—

ADC

I

AF1

AF2

AF3

—

I

GPI[13]

PD[10] PCR[58] AF0

GPIO[58]

SIUL

—

ADC

I

AF1

AF2

AF3

—

I

GPI[14]

PD[11] PCR[59] AF0

GPIO[59]

SIUL

—

ADC

I

AF1

AF2

AF3

—

I

GPI[15]

PD[12]⁸PCR[60] AF0

GPIO[60]

CS5_0

E0UC[24]

—

SIUL

DSPI_0

eMIOS_0 I/O

—

ADC

I/O

O

J

AF1

AF2

AF3

—

I

ANS[4]

PD[13] PCR[61] AF0

GPIO[61]

CS0_1

E0UC[25]

—

SIUL

DSPI_1

eMIOS_0 I/O

—

ADC

I/O

AF1

AF2

AF3

—

I

ANS[5]

PD[14] PCR[62] AF0

GPIO[62]

CS1_1

E0UC[26]

—

SIUL

DSPI_1

eMIOS_0 I/O

—

ADC

I/O

O

AF1

AF2

AF3

—

I

ANS[6]

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

21

Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

PD[15] PCR[63] AF0

GPIO[63]

CS2_1

E0UC[27]

—

SIUL

DSPI_1

eMIOS_0 I/O

—

ADC

I/O

O

J

Tristate

—

66 88 L14

AF1

AF2

AF3

—

I

ANS[7]

PE[0]

PCR[64] AF0

GPIO[64]

E0UC[16]

—

SIUL

eMIOS_0 I/O

I/O

S

—

6

8

10 F1

AF1

AF2

AF3

—

I

—

CAN5RX¹¹

WKPU[6]⁴

FlexCAN_5

WKPU

—

I

PE[1]

PE[2]

PCR[65] AF0

GPIO[65]

E0UC[17]

CAN5TX¹¹

—

SIUL

eMIOS_0 I/O

FlexCAN_5

—

I/O

M

Tristate

—

12 F4

AF1

AF2

AF3

O

—

PCR[66] AF0

GPIO[66]

E0UC[18]

—

SIN_1

SIUL

eMIOS_0 I/O

—

DSPI_1

I/O

89 128 D7

AF1

AF2

AF3

—

I

PE[3]

PE[4]

PCR[67] AF0

GPIO[67]

E0UC[19]

SOUT_1

—

SIUL

eMIOS_0 I/O

DSPI_1

—

I/O

M

Tristate

—

90 129 C7

93 132 D6

AF1

AF2

AF3

O

—

PCR[68] AF0

GPIO[68]

E0UC[20]

SCK_1

—

SIUL

eMIOS_0 I/O

DSPI_1

—

SIUL

I/O

AF1

AF2

AF3

—

I/O

—

I

EIRQ[9]

PE[5]

PE[6]

PE[7]

PCR[69] AF0

GPIO[69]

E0UC[21]

CS0_1

SIUL

eMIOS_0 I/O

DSPI_1

ADC

I/O

M

Tristate

—

94 133 C6

95 139 B5

96 140 C4

AF1

AF2

AF3

I/O

O

MA[2]

PCR[70] AF0

GPIO[70]

E0UC[22]

CS3_0

SIUL

eMIOS_0 I/O

DSPI_0

ADC

I/O

AF1

AF2

AF3

O

MA[1]

PCR[71] AF0

GPIO[71]

E0UC[23]

CS2_0

SIUL

eMIOS_0 I/O

DSPI_0

ADC

I/O

AF1

AF2

AF3

O

MA[0]

MPC5604B/C Microcontroller Data Sheet, Rev. 14

22

NXP Semiconductors

Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

PE[8]

PE[9]

PCR[72] AF0

GPIO[72]

CAN2TX¹²

E0UC[22]

CAN3TX¹¹

SIUL

FlexCAN_2

eMIOS_0 I/O

FlexCAN_3

I/O

O

M

S

Tristate

—

9

13 G2

AF1

AF2

AF3

O

PCR[73] AF0

GPIO[73]

—

SIUL

—

eMIOS_0 I/O

—

WKPU

I/O

—

10 14 G1

AF1

AF2

AF3

—

E0UC[23]

—

WKPU[7]⁴

CAN2RX¹²

CAN3RX¹¹

I

FlexCAN_2

FlexCAN_3

PE[10] PCR[74] AF0

GPIO[74]

LIN3TX

CS3_1

—

SIUL

LINFlex_3

DSPI_1

—

I/O

O

—

I

S

Tristate

—

11 15 G3

AF1

AF2

AF3

—

EIRQ[10]

SIUL

PE[11] PCR[75] AF0

GPIO[75]

—

CS4_1

—

SIUL

—

DSPI_1

—

LINFlex_3

WKPU

I/O

—

O

—

I

13 17 H2

AF1

AF2

AF3

—

LIN3RX

—

WKPU[14]⁴

I

PE[12] PCR[76] AF0

GPIO[76]

—

SIUL

—

eMIOS_1 I/O

—

DSPI_2

SIUL

I/O

—

S

Tristate

—

76 109 C14

AF1

AF2

AF3

—

E1UC[19]¹³

—

I

SIN_2

EIRQ[11]

—

PE[13] PCR[77] AF0

GPIO[77]

SOUT2

E1UC[20]

—

SIUL

DSPI_2

eMIOS_1 I/O

I/O

O

S

Tristate

—

103 D15

112 C13

AF1

AF2

AF3

—

PE[14] PCR[78] AF0

GPIO[78]

SCK_2

E1UC[21]

—

SIUL

DSPI_2

eMIOS_1 I/O

—

SIUL

I/O

AF1

AF2

AF3

—

I

EIRQ[12]

PE[15] PCR[79] AF0

GPIO[79]

CS0_2

E1UC[22]

—

SIUL

DSPI_2

eMIOS_1 I/O

I/O

M

Tristate

—

113 A13

AF1

AF2

AF3

—

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

23

Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

PF[0]

PF[1]

PF[2]

PF[3]

PF[4]

PF[5]

PF[6]

PF[7]

PCR[80] AF0

GPIO[80]

E0UC[10]

CS3_1

—

SIUL

eMIOS_0 I/O

DSPI_1

—

ADC

I/O

J

Tristate

—

55 N10

AF1

AF2

AF3

—

O

—

I

ANS[8]

PCR[81] AF0

GPIO[81]

E0UC[11]

CS4_1

—

SIUL

eMIOS_0 I/O

DSPI_1

I/O

—

56 P10

57 T10

58 R10

59 N11

60 P11

61 T11

62 R11

AF1

AF2

AF3

—

O

—

I

—

I

ANS[9]

PCR[82] AF0

GPIO[82]

E0UC[12]

CS0_2

—

SIUL

eMIOS_0 I/O

DSPI_2

—

ADC

I/O

AF1

AF2

AF3

—

I/O

—

I

ANS[10]

PCR[83] AF0

GPIO[83]

E0UC[13]

CS1_2

—

SIUL

eMIOS_0 I/O

DSPI_2

—

ADC

I/O

AF1

AF2

AF3

—

O

—

I

ANS[11]

PCR[84] AF0

GPIO[84]

E0UC[14]

CS2_2

—

SIUL

eMIOS_0 I/O

DSPI_2

—

ADC

I/O

AF1

AF2

AF3

—

O

—

I

ANS[12]

PCR[85] AF0

GPIO[85]

E0UC[22]

CS3_2

—

SIUL

eMIOS_0 I/O

DSPI_2

—

ADC

I/O

AF1

AF2

AF3

—

O

—

I

ANS[13]

PCR[86] AF0

GPIO[86]

E0UC[23]

—

ANS[14]

SIUL

eMIOS_0 I/O

—

ADC

I/O

AF1

AF2

AF3

—

I

PCR[87] AF0

GPIO[87]

SIUL

—

ADC

I/O

—

I

AF1

AF2

AF3

—

ANS[15]

MPC5604B/C Microcontroller Data Sheet, Rev. 14

24

NXP Semiconductors

Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

PF[8]

PF[9]

PCR[88] AF0

GPIO[88]

CAN3TX¹⁴

CS4_0

SIUL

FlexCAN_3

DSPI_0

I/O

O

M

S

Tristate

—

34 P1

AF1

AF2

AF3

CAN2TX¹⁵

FlexCAN_2

O

PCR[89] AF0

GPIO[89]

—

SIUL

—

DSPI_0

—

FlexCAN_2

FlexCAN_3

I/O

—

O

—

I

—

33 N2

AF1

AF2

AF3

—

CS5_0

—

CAN2RX¹⁵

CAN3RX¹⁴

—

I

PF[10] PCR[90] AF0

GPIO[90]

SIUL

—

I/O

—

M

S

Tristate

—

38 R3

39 R4

AF1

AF2

AF3

—

PF[11] PCR[91] AF0

GPIO[91]

SIUL

—

WKPU

I/O

—

I

AF1

AF2

AF3

—

WKPU[15]⁴

PF[12] PCR[92] AF0

GPIO[92]

E1UC[25]

—

SIUL

eMIOS_1 I/O

I/O

M

S

Tristate

—

35 R1

41 T6

AF1

AF2

AF3

—

PF[13] PCR[93] AF0

GPIO[93]

E1UC[26]

—

SIUL

eMIOS_1 I/O

—

WKPU

I/O

AF1

AF2

AF3

—

I

—

WKPU[16]⁴

PF[14] PCR[94] AF0

GPIO[94]

CAN4TX¹¹

E1UC[27]

CAN1TX

SIUL

FlexCAN_4

eMIOS_1 I/O

FlexCAN_4

I/O

O

M

S

Tristate

—

43

42

—

102 D14

101 E15

AF1

AF2

AF3

O

PF[15] PCR[95] AF0

GPIO[95]

—

SIUL

—

I/O

—

I

AF1

AF2

AF3

—

CAN1RX

CAN4RX¹¹

EIRQ[13]

FlexCAN_1

FlexCAN_4

SIUL

I

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

25

Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

PG[0]

PG[1]

PCR[96] AF0

GPIO[96]

CAN5TX¹¹

E1UC[23]

—

SIUL

FlexCAN_5

eMIOS_1 I/O

I/O

O

M

S

Tristate

—

41

—

98 E14

AF1

AF2

AF3

—

PCR[97] AF0

GPIO[97]

—

SIUL

—

eMIOS_1 I/O

I/O

—

40

97 E13

AF1

AF2

AF3

—

E1UC[24]

—

I

CAN5RX¹¹

EIRQ[14]

FlexCAN_5

SIUL

—

PG[2]

PG[3]

PCR[98] AF0

GPIO[98]

E1UC[11]

—

SIUL

eMIOS_1 I/O

I/O

M

S

Tristate

—

8

7

E4

E3

AF1

AF2

AF3

—

PCR[99] AF0

GPIO[99]

E1UC[12]

—

SIUL

eMIOS_1 I/O

—

WKPU

I/O

AF1

AF2

AF3

—

I

—

WKPU[17]⁴

PG[4] PCR[100] AF0

GPIO[100]

E1UC[13]

—

SIUL

eMIOS_1 I/O

I/O

M

S

Tristate

—

6

5

E1

E2

AF1

AF2

AF3

—

PG[5] PCR[101] AF0

GPIO[101]

E1UC[14]

—

SIUL

eMIOS_1 I/O

—

WKPU

I/O

AF1

AF2

AF3

—

I

—

WKPU[18]⁴

PG[6] PCR[102] AF0

GPIO[102]

E1UC[15]

—

SIUL

eMIOS_1 I/O

I/O

M

S

Tristate

—

30 M2

29 M1

26 L2

AF1

AF2

AF3

—

PG[7] PCR[103] AF0

GPIO[103]

E1UC[16]

—

SIUL

eMIOS_1 I/O

I/O

AF1

AF2

AF3

—

PG[8] PCR[104] AF0

GPIO[104]

E1UC[17]

—

CS0_2

EIRQ[15]

SIUL

eMIOS_1 I/O

—

DSPI_2

SIUL

I/O

AF1

AF2

AF3

—

I/O

I

MPC5604B/C Microcontroller Data Sheet, Rev. 14

26

NXP Semiconductors

Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

PG[9] PCR[105] AF0

GPIO[105]

E1UC[18]

—

SIUL

eMIOS_1 I/O

—

DSPI_2

I/O

S

Tristate

—

25 L1

AF1

AF2

AF3

—

I/O

SCK_2

PG[10] PCR[106] AF0

GPIO[106]

E0UC[24]

—

SIUL

eMIOS_0 I/O

I/O

—

114 D13

115 B12

92 K14

91 K16

110 B14

111 B13

93 F13

AF1

AF2

AF3

—

PG[11] PCR[107] AF0

GPIO[107]

E0UC[25]

—

SIUL

eMIOS_0 I/O

I/O

M

S

AF1

AF2

AF3

—

PG[12] PCR[108] AF0

GPIO[108]

E0UC[26]

—

SIUL

eMIOS_0 I/O

I/O

AF1

AF2

AF3

—

PG[13] PCR[109] AF0

GPIO[109]

E0UC[27]

—

SIUL

eMIOS_0 I/O

I/O

AF1

AF2

AF3

—

PG[14] PCR[110] AF0

GPIO[110]

E1UC[0]

—

SIUL

eMIOS_1 I/O

I/O

AF1

AF2

AF3

—

PG[15] PCR[111] AF0

GPIO[111]

E1UC[1]

—

SIUL

eMIOS_1 I/O

I/O

M

AF1

AF2

AF3

—

PH[0] PCR[112] AF0

GPIO[112]

E1UC[2]

—

SIUL

eMIOS_1 I/O

—

DSPI_1

I/O

AF1

AF2

AF3

—

I

—

SIN1

PH[1] PCR[113] AF0

GPIO[113]

E1UC[3]

SOUT1

—

SIUL

eMIOS_1 I/O

DSPI_1

—

I/O

M

Tristate

—

94 F14

AF1

AF2

AF3

O

—

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

27

Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

PH[2] PCR[114] AF0

GPIO[114]

E1UC[4]

SCK_1

—

SIUL

eMIOS_1 I/O

DSPI_1

—

I/O

M

S

Tristate

—

95 F16

AF1

AF2

AF3

I/O

—

PH[3] PCR[115] AF0

GPIO[115]

E1UC[5]

CS0_1

—

SIUL

eMIOS_1 I/O

DSPI_1

—

I/O

—

96 F15

134 A6

135 B6

136 D5

137 C5

138 A5

AF1

AF2

AF3

I/O

—

PH[4] PCR[116] AF0

GPIO[116]

E1UC[6]

—

SIUL

eMIOS_1 I/O

I/O

AF1

AF2

AF3

—

PH[5] PCR[117] AF0

GPIO[117]

E1UC[7]

—

SIUL

eMIOS_1 I/O

I/O

AF1

AF2

AF3

—

PH[6] PCR[118] AF0

GPIO[118]

E1UC[8]

—

SIUL

eMIOS_1 I/O

—

ADC

I/O

M

S

AF1

AF2

AF3

—

O

MA[2]

PH[7] PCR[119] AF0

GPIO[119]

E1UC[9]

CS3_2

SIUL

eMIOS_1 I/O

DSPI_2

ADC

I/O

AF1

AF2

AF3

O

MA[1]

PH[8] PCR[120] AF0

GPIO[120]

E1UC[10]

CS2_2

SIUL

eMIOS_1 I/O

DSPI_2

ADC

I/O

AF1

AF2

AF3

O

MA[0]

PH[9]⁹PCR[121] AF0

GPIO[121]

SIUL

—

JTAGC

—

I/O

—

I

Input, weak 60 60 88 127 B8

pull-up

AF1

AF2

AF3

—

TCK

—

PH[10]⁹PCR[122] AF0

GPIO[122]

SIUL

—

JTAGC

—

I/O

—

I

S

Input, weak 53 53 81 120 B9

pull-up

AF1

AF2

AF3

—

TMS

—

MPC5604B/C Microcontroller Data Sheet, Rev. 14

28

NXP Semiconductors

Package pinouts and signal descriptions

Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIUL module.

PCR.PA = 00 → AF0; PCR.PA = 01 → AF1; PCR.PA = 10 → AF2; PCR.PA = 11 → AF3. This is intended to select

the output functions; to use one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless of the

values selected in the PCR.PA bitfields. For this reason, the value corresponding to an input only function is

reported as “—”.

1

2

Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by

setting the values of the PSMIO.PADSELx bitfields inside the SIUL module.

3

4

5

6

208 MAPBGA available only as development package for Nexus2+

All WKPU pins also support external interrupt capability. See wakeup unit chapter for further details.

NMI has higher priority than alternate function. When NMI is selected, the PCR.AF field is ignored.

“Not applicable” because these functions are available only while the device is booting. Refer to BAM chapter of the

reference manual for details.

7

8

Value of PCR.IBE bit must be 0

Be aware that this pad is used on the MPC5607B 100-pin and 144-pin to provide VDD_HV_ADC and

VSS_HV_ADC1. Therefore, you should be careful in ensuring compatibility between MPC5604B/C and

MPC5607B.

9

Out of reset all the functional pins except PC[0:1] and PH[9:10] are available to the user as GPIO.

PC[0:1] are available as JTAG pins (TDI and TDO respectively).

PH[9:10] are available as JTAG pins (TCK and TMS respectively).

If the user configures these JTAG pins in GPIO mode the device is no longer compliant with IEEE 1149.1-2001.

¹⁰The TDO pad has been moved into the STANDBY domain in order to allow low-power debug handshaking in

STANDBY mode. However, no pull-resistor is active on the TDO pad while in STANDBY mode. At this time the pad

is configured as an input. When no debugger is connected the TDO pad is floating causing additional current

consumption. To avoid the extra consumption TDO must be connected. An external pull-up resistor in the range of

47–100 kΩ should be added between the TDO pin and VDD_HV. Only in case the TDO pin is used as application

pin and a pull-up cannot be used then a pull-down resistor with the same value should be used between TDO pin

and GND instead.

¹¹Available only on MPC560xC versions, MPC5603B 64 LQFP, MPC5604B 64 LQFP and MPC5604B 208 MAPBGA

devices

¹²Not available on MPC5602B devices

¹³Not available in 100 LQFP package

¹⁴Available only on MPC5604B 208 MAPBGA devices

¹⁵Not available on MPC5603B 144-pin devices

2.7

Nexus 2+ pins

In the 208 MAPBGA package, eight additional debug pins are available (see Table 6).

Table 6. Nexus 2+ pin descriptions

Pin number

I/O

direction

Function

after reset

Debug pin

Function

Pad type

100

144

208 MAP

BGA

LQFP

MCKO

MDO0

MDO1

MDO2

MDO3

Message clock out

Message data out 0

Message data out 1

Message data out 2

Message data out 3

O

F

—

T4

M

H15

H16

H14

H13

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

29

Package pinouts and signal descriptions

Table 6. Nexus 2+ pin descriptions (continued)

Pin number

I/O

direction

Function

after reset

Debug pin

Function

Pad type

100

144

208 MAP

BGA

LQFP

EVTI

EVTO

MSEO

Event in

Event out

I

M

Pull-up

—

K1

L4

O

Message start/end out

—

G16

MPC5604B/C Microcontroller Data Sheet, Rev. 14

30

NXP Semiconductors

Package pinouts and signal descriptions

2.8

2.9

Electrical characteristics

Introduction

This section contains electrical characteristics of the device as well as temperature and power

considerations.

This product contains devices to protect the inputs against damage due to high static voltages. However,

it is advisable to take precautions to avoid applying any voltage higher than the specified maximum rated

voltages.

To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (V or V ). This

DD

SS

could be done by the internal pull-up and pull-down, which is provided by the product for most general

purpose pins.

The parameters listed in the following tables represent the characteristics of the device and its demands on

the system.

In the tables where the device logic provides signals with their respective timing characteristics, the

symbol “CC” for Controller Characteristics is included in the Symbol column.

In the tables where the external system must provide signals with their respective timing characteristics to

the device, the symbol “SR” for System Requirement is included in the Symbol column.

2.10 Parameter classification

The electrical parameters shown in this supplement are guaranteed by various methods. To give the

customer a better understanding, the classifications listed in Table 7 are used and the parameters are tagged

accordingly in the tables where appropriate.

Table 7. Parameter classifications

Classification tag

Tag description

P

C

Those parameters are guaranteed during production testing on each individual device.

Those parameters are achieved by the design characterization by measuring a statistically

relevant sample size across process variations.

T

Those parameters are achieved by design characterization on a small sample size from typical

devices under typical conditions unless otherwise noted. All values shown in the typical column

are within this category.

D

Those parameters are derived mainly from simulations.

NOTE

The classification is shown in the column labeled “C” in the parameter

tables where appropriate.

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

31

Package pinouts and signal descriptions

2.11 NVUSRO register

Bit values in the Non-Volatile User Options (NVUSRO) Register control portions of the device

configuration, namely electrical parameters such as high voltage supply and oscillator margin, as well as

digital functionality (watchdog enable/disable after reset).

For a detailed description of the NVUSRO register, please refer to the device reference manual.

2.11.1 NVUSRO[PAD3V5V] field description

The DC electrical characteristics are dependent on the PAD3V5V bit value. Table 8 shows how

NVUSRO[PAD3V5V] controls the device configuration.

Table 8. PAD3V5V field description

Value¹

Description

0

1

High voltage supply is 5.0 V

High voltage supply is 3.3 V

1

Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash.

2.11.2 NVUSRO[OSCILLATOR_MARGIN] field description

The fast external crystal oscillator consumption is dependent on the OSCILLATOR_MARGIN bit value.

Table 9 shows how NVUSRO[OSCILLATOR_MARGIN] controls the device configuration.

Table 9. OSCILLATOR_MARGIN field description

Value¹

Description

0

1

Low consumption configuration (4 MHz/8 MHz)

High margin configuration (4 MHz/16 MHz)

1

Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash.

2.11.3 NVUSRO[WATCHDOG_EN] field description

The watchdog enable/disable configuration after reset is dependent on the WATCHDOG_EN bit value.

Table 10 shows how NVUSRO[WATCHDOG_EN] controls the device configuration.

Table 10. WATCHDOG_EN field description

Value¹

Description

0

1

Disable after reset

Enable after reset

1

Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash.

MPC5604B/C Microcontroller Data Sheet, Rev. 14

32

NXP Semiconductors

Package pinouts and signal descriptions

2.12 Absolute maximum ratings

Table 11. Absolute maximum ratings

Value

Symbol

Parameter

Conditions

Unit

Min

Max

V_SS

V_DD

SR Digital ground on VSS_HV pins

—

0

V

SR Voltage on VDD_HV pins with respect to

−0.3

6.0

ground (V_SS

)

V_{SS_LV}SR Voltage on VSS_LV (low voltage digital

supply) pins with respect to ground

—

V_SS−0.1 V_SS+0.1

V

(V_SS

)

V_{DD_BV}SR Voltage on VDD_BV pin (regulator

supply) with respect to ground (V_SS

—

−0.3

6.0

V

)

Relative to V_DD

V_DD+0.3

V_{SS_ADC}SR Voltage on VSS_HV_ADC (ADC

V_SS−0.1 V_SS+0.1

reference) pin with respect to ground

(V_SS

)

V_{DD_ADC}SR Voltage on VDD_HV_ADC pin (ADC

reference) with respect to ground (V_SS

—

−0.3

6.0

V

)

Relative to V_DD

V_DD−0.3 V_DD+0.3

V_IN

SR Voltage on any GPIO pin with respect to

ground (V_SS

−0.3

—

6.0

V_DD+0.3

10

)

I_INJPADSR Injected input current on any pin during

overload condition

—

−10

mA

I_INJSUMSR Absolute sum of all injected input

currents during overload condition

−50

50

I_AVGSEGSR Sum of all the static I/O current within a V_DD= 5.0 V 10%, PAD3V5V = 0

—

70

64

mA

supply segment

V_DD= 3.3 V 10%, PAD3V5V = 1

I_CORELVSR Low voltage static current sink through

VDD_BV

—

150

mA

°C

T_STORAGESR Storage temperature

—

−55

150

NOTE

Stresses exceeding the recommended absolute maximum ratings may cause

permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those

indicated in the operational sections of this specification are not implied.

Exposure to absolute maximum rating conditions for extended periods may

affect device reliability. During overload conditions (V > V or

IN

DD

V < V ), the voltage on pins with respect to ground (V ) must not

IN

SS

exceed the recommended values.

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

33

Package pinouts and signal descriptions

2.13 Recommended operating conditions

Table 12. Recommended operating conditions (3.3 V)

Value

Symbol

Parameter

Conditions

Unit

Min

Max

V_SS

SR Digital ground on VSS_HV pins

—

0

V

1

V_DD

SR Voltage on VDD_HV pins with respect to ground

3.0

3.6

(V_SS

)

2

V_{SS_LV}

SR Voltage on VSS_LV (low voltage digital supply)

—

V_SS−0.1 V_SS+0.1

3.0 3.6

V

pins with respect to ground (V_SS

)

3

V_{DD_BV}

SR Voltage on VDD_BV pin (regulator supply) with

respect to ground (V_SS

)

Relative to V_DDV_DD−0.1 V_DD+0.1

V_{SS_ADC}

SR Voltage on VSS_HV_ADC (ADC reference) pin

with respect to ground (V_SS

—

V_SS−0.1 V_SS+0.1

V

)

V_{DD_ADC}

SR Voltage on VDD_HV_ADC pin (ADC reference)

with respect to ground (V_SS

—

3.0⁵

3.6

4

)

Relative to V_DDV_DD−0.1 V_DD+0.1

V_IN

SR Voltage on any GPIO pin with respect to ground

(V_SS

—

Relative to V_DD

—

V_SS−0.1

—

V_DD+0.1

5

V

)

I_INJPAD

I_INJSUM

TV_DD

SR Injected input current on any pin during overload

condition

−5

mA

SR Absolute sum of all injected input currents during

overload condition

—

−50

50

SR V_DDslope to ensure correct power up⁶

3.0⁷

0.25[V/µs] V/s

)

T_{A C-Grade Part}SR Ambient temperature under bias

T_{J C-Grade Part}SR Junction temperature under bias

T_{A V-Grade Part}SR Ambient temperature under bias

T_{J V-Grade Part}SR Junction temperature under bias

T_{A M-Grade Part}SR Ambient temperature under bias

T_{J M-Grade Part}SR Junction temperature under bias

f_CPU≤ 64 MHz

−40

85

°C

110

105

130

125

150

1

2

3

100 nF capacitance needs to be provided between each V_DD/V_SSpair

330 nF capacitance needs to be provided between each V_{DD_LV}/V_{SS_LV}supply pair.

400 nF capacitance needs to be provided between V_{DD_BV}and the nearest V_{SS_LV}(higher value may be needed

depending on external regulator characteristics).

4

5

100 nF capacitance needs to be provided between V_{DD_ADC}/V_{SS_ADC}pair.

Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical

characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below V_LVDHVL

device is reset.

,

6

7

Guaranteed by device validation.

Minimum value of TV_DDmust be guaranteed until V_DDreaches 2.6 V (maximum value of V_PORH).

MPC5604B/C Microcontroller Data Sheet, Rev. 14

34

NXP Semiconductors

Package pinouts and signal descriptions

Table 13. Recommended operating conditions (5.0 V)

Value

Symbol

Parameter

Conditions

Unit

Min

Max

V_SS

SR Digital ground on VSS_HV pins

—

0

V

1

V_DD

SR Voltage on VDD_HV pins with respect to

—

Voltage drop²

—

4.5

3.0

5.5

ground (V_SS

)

3

V_{SS_LV}

SR Voltage on VSS_LV (low voltage digital

supply) pins with respect to ground (V_SS

V_SS−0.1 V_SS+0.1

V

)

4

V_{DD_BV}

SR Voltage on VDD_BV pin (regulator supply)

with respect to ground (V_SS

—

4.5

3.0

5.5

)

Voltage drop²

Relative to V_DDV_DD−0.1 V_DD+0.1

V_{SS_ADC}

SR Voltage on VSS_HV_ADC (ADC reference)

pin with respect to ground (V_SS

—

V_SS−0.1 V_SS+0.1

V

5

V_{DD_ADC}

SR Voltage on VDD_HV_ADC pin (ADC

—

4.5

3.0

5.5

reference) with respect to ground (V_SS

)

Voltage drop²

Relative to V_DDV_DD−0.1 V_DD+0.1

V_IN

SR Voltage on any GPIO pin with respect to

ground (V_SS

—

Relative to V_DD

—

V_SS−0.1

—

V_DD+0.1

5

V

)

I_INJPAD

I_INJSUM

SR Injected input current on any pin during

overload condition

−5

mA

SR Absolute sum of all injected input currents

during overload condition

—

−50

50

TV_DD

SR V_DDslope to ensure correct power up⁶

SR Ambient temperature under bias

SR Junction temperature under bias

SR Ambient temperature under bias

SR Junction temperature under bias

SR Ambient temperature under bias

SR Junction temperature under bias

—

3.0⁷

−40

0.25 V/µs V/s

T_{A C-Grade Part}

T_{J C-Grade Part}

T_{A V-Grade Part}

T_{J V-Grade Part}

T_{A M-Grade Part}

T_{J M-Grade Part}

f_CPU≤ 64 MHz

85

°C

110

105

130

125

150

1

2

100 nF capacitance needs to be provided between each V_DD/V_SSpair.

Full device operation is guaranteed by design when the voltage drops below 4.5 V down to 3.0 V. However, certain

analog electrical characteristics will not be guaranteed to stay within the stated limits.

3

4

330 nF capacitance needs to be provided between each V_{DD_LV}/V_{SS_LV}supply pair.

100 nF capacitance needs to be provided between V_{DD_BV}and the nearest V_{SS_LV}(higher value may be needed

depending on external regulator characteristics).

5

1 µF (electrolithic/tantalum) + 47 nF (ceramic) capacitance needs to be provided between V_{DD_ADC}/V_{SS_ADC}pair.

Another ceramic cap of 10 nF with low inductance package can be added.

6

7

Guaranteed by device validation.

Minimum value of TV_DDmust be guaranteed until V_DDreaches 2.6 V (maximum value of V_PORH).

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

35

Package pinouts and signal descriptions

NOTE

RAM data retention is guaranteed with V

not below 1.08 V.

DD_LV

2.14 Thermal characteristics

2.14.1 Package thermal characteristics

1

Table 14. LQFP thermal characteristics

Symbol

C

Parameter

Thermal resistance,

Conditions²

Pin count Value Unit

R_θJACC

D

Single-layer board - 1s

64

100

144

64

60

64

42

51

49

24

36

37

24

34

35

11

22

11

22

°C/W

junction-to-ambient natural

convection³

Four-layer board - 2s2p

Single-layer board - 1s

Four-layer board - 2s2p

Single-layer board - 1s

Four-layer board - 2s2p

Single-layer board - 1s

Four-layer board - 2s2p

100

144

64

R_θJBCC

R_θJCCC

Ψ_JBCC

D

Thermal resistance,

junction-to-board⁴

100

144

64

100

144

64

Thermal resistance,

junction-to-case⁵

100

144

64

100

144

64

Junction-to-board thermal

characterization parameter,

natural convection

TBD °C/W

100

144

64

33

34

TBD

34

100

144

35

MPC5604B/C Microcontroller Data Sheet, Rev. 14

36

NXP Semiconductors

Package pinouts and signal descriptions

Table 14. LQFP thermal characteristics (continued)

1

Symbol

C

Parameter

Conditions²

Pin count Value Unit

Ψ_JCCC

D

Junction-to-case thermal

characterization parameter,

natural convection

Single-layer board - 1s

64

100

144

64

TBD °C/W

9

10

TBD

9

Four-layer board - 2s2p

100

144

10

1

2

3

Thermal characteristics are based on simulation.

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= −40 to 125 °C

Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test

board meets JEDEC specification for this package.

4

5

Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC

specification for the specified package.

Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate

temperature is used for the case temperature. Reported value includes the thermal resistance of the interface

layer.

2.14.2 Power considerations

The average chip-junction temperature, T , in degrees Celsius, may be calculated using Equation 1:

J

T = T + (P x R )

θJA

Eqn. 1

J

A

D

Where:

T is the ambient temperature in °C.

A

R

is the package junction-to-ambient thermal resistance, in °C/W.

θJA

P is the sum of P

and P (P = P

+ P ).

D

INT

I/O

D

INT I/O

P

is the product of I and V , expressed in watts. This is the chip internal power.

DD DD

INT

I/O

represents the power dissipation on input and output pins; user determined.

Most of the time for the applications, P < P

and may be neglected. On the other hand, P may be

I/O

INT

I/O

significant, if the device is configured to continuously drive external modules and/or memories.

An approximate relationship between P and T (if P is neglected) is given by:

D

J

I/O

P = K / (T + 273 °C)

Eqn. 2

Eqn. 3

D

J

Therefore, solving equations 1 and 2:

2

K = P x (T + 273 °C) + R

x P

D

A

θJA

Where:

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

37

Package pinouts and signal descriptions

K is a constant for the particular part, which may be determined from Equation 3 by measuring

P (at equilibrium) for a known T Using this value of K, the values of P and T may be

D

A.

D

J

obtained by solving equations 1 and 2 iteratively for any value of T .

A

2.15 I/O pad electrical characteristics

2.15.1 I/O pad types

The device provides four main I/O pad types depending on the associated alternate functions:

•

Slow pads—These pads are the most common pads, providing a good compromise between

transition time and low electromagnetic emission.

Medium pads—These pads provide transition fast enough for the serial communication channels

with controlled current to reduce electromagnetic emission.

Fast pads—These pads provide maximum speed. There are used for improved Nexus debugging

capability.

Input only pads—These pads are associated to ADC channels and the external 32 kHz crystal

oscillator (SXOSC) providing low input leakage.

Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at the cost of

reducing AC performance.

2.15.2 I/O input DC characteristics

Table 15 provides input DC electrical characteristics as described in Figure 7.

V

IN

V

DD

V

IH

V

HYS

V

IL

PDIx = ‘1’

(GPDI register of SIUL)

PDIx = ‘0’

Figure 7. I/O input DC electrical characteristics definition

MPC5604B/C Microcontroller Data Sheet, Rev. 14

38

NXP Semiconductors

Package pinouts and signal descriptions

Table 15. I/O input DC electrical characteristics

Value

Symbol

C

Parameter

Conditions¹

Unit

Min

Typ

Max

V_IHSR P Input high level CMOS (Schmitt

Trigger)

—

0.65V_DD

—

V_DD+0.4

V

V_ILSR P Input low level CMOS (Schmitt

Trigger)

−0.4

—

0.35V_DD

—

V_HYSCC C Input hysteresis CMOS (Schmitt

Trigger)

0.1V_DD

I_LKGCC D Digital input leakage

No injection

on adjacent

T_A= −40 °C

T_A= 25 °C

T_A= 85 °C

T_A= 105 °C

T_A= 125 °C

—

2

200

300

500

1000

40

nA

D

P

—

5

—

12

70

—

2

W_FISR P Wakeup input filtered pulse

—

ns

2

W_NFISR P Wakeup input not filtered pulse

1000

—

1

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= −40 to 125 °C, unless otherwise specified

In the range from 40 to 1000 ns, pulses can be filtered or not filtered, according to operating temperature and

voltage.

2

2.15.3 I/O output DC characteristics

The following tables provide DC characteristics for bidirectional pads:

•

Table 16 provides weak pull figures. Both pull-up and pull-down resistances are supported.

Table 17 provides output driver characteristics for I/O pads when in SLOW configuration.

Table 18 provides output driver characteristics for I/O pads when in MEDIUM configuration.

Table 19 provides output driver characteristics for I/O pads when in FAST configuration.

Table 16. I/O pull-up/pull-down DC electrical characteristics

Value

Symbol

C

Parameter

Conditions¹

Unit

Min Typ Max

|I_WPU| CC P Weak pull-up current

V_IN= V_IL, V_DD= 5.0 V 10% PAD3V5V = 0

10

—

150 µA

250

absolute value

C

PAD3V5V = 1²10

P

V_IN= V_IL, V_DD= 3.3 V 10% PAD3V5V = 1

10

150

|I_WPD| CC P Weak pull-down current V_IN= V_IH, V_DD= 5.0 V 10% PAD3V5V = 0

absolute value

150 µA

250

C

P

PAD3V5V = 1

V_IN= V_IH, V_DD= 3.3 V 10% PAD3V5V = 1

150

1

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= −40 to 125 °C, unless otherwise specified.

The configuration PAD3V5 = 1 when V_DD= 5 V is only a transient configuration during power-up. All pads but

RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

2

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

39

Package pinouts and signal descriptions

Table 17. SLOW configuration output buffer electrical characteristics

Value

Symbol C

Parameter

Conditions¹

Unit

Min

Typ

Max

V_OHCC P Output high level

SLOW configuration

Push Pull I_OH= −2 mA,

0.8V_DD

—

V

V_DD= 5.0 V 10%, PAD3V5V = 0

(recommended)

C

I

_OH= −2 mA,

0.8V_DD

—

V_DD= 5.0 V 10%, PAD3V5V = 1²

I_OH= −1 mA,

V_DD−0.8

V_DD= 3.3 V 10%, PAD3V5V = 1

(recommended)

V_OLCC P Output low level

SLOW configuration

Push Pull I_OL= 2 mA,

—

0.1V_DD

V

V_DD= 5.0 V 10%, PAD3V5V = 0

(recommended)

C

I

_OL= 2 mA,

—

0.1V_DD

0.5

V_DD= 5.0 V 10%, PAD3V5V = 1²

I_OL= 1 mA,

V_DD= 3.3 V 10%, PAD3V5V = 1

(recommended)

1

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= −40 to 125 °C, unless otherwise specified

The configuration PAD3V5 = 1 when V_DD= 5 V is only a transient configuration during power-up. All pads but

RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

2

Table 18. MEDIUM configuration output buffer electrical characteristics

Value

Symbol C

Parameter

Conditions¹

Unit

Min

Typ Max

V_OHCC C Output high level

MEDIUM configuration

Push Pull I_OH= −3.8 mA,

V_DD= 5.0 V 10%, PAD3V5V = 0

0.8V_DD

—

V

P

I

_OH= −2 mA,

0.8V_DD

—

V_DD= 5.0 V 10%, PAD3V5V = 0

(recommended)

C

I

_OH= −1 mA,

0.8V_DD

—

V_DD= 5.0 V 10%, PAD3V5V = 1²

I_OH= −1 mA,

V_DD−0.8

V_DD= 3.3 V 10%, PAD3V5V = 1

(recommended)

C

I

_OH= −100 µA,

0.8V_DD

—

V_DD= 5.0 V 10%, PAD3V5V = 0

MPC5604B/C Microcontroller Data Sheet, Rev. 14

40

NXP Semiconductors

Package pinouts and signal descriptions

Table 18. MEDIUM configuration output buffer electrical characteristics (continued)

Value

Symbol C

Parameter

Conditions¹

Unit

Min

Typ Max

V_OLCC C Output low level

MEDIUM configuration

Push Pull I_OL= 3.8 mA,

V_DD= 5.0 V 10%, PAD3V5V = 0

—

0.2V_DD

V

P

I

V

_OL= 2 mA,

_DD= 5.0 V 10%, PAD3V5V = 0

—

0.1V_DD

(recommended)

C

I_OL= 1 mA,

V

—

0.1V_DD

0.5

_DD= 5.0 V 10%, PAD3V5V = 1²

I_OL= 1 mA,

V_DD= 3.3 V 10%, PAD3V5V = 1

(recommended)

C

I

_OL= 100 µA,

—

0.1V_DD

V_DD= 5.0 V 10%, PAD3V5V = 0

1

2

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= −40 to 125 °C, unless otherwise specified

The configuration PAD3V5 = 1 when V_DD= 5 V is only a transient configuration during power-up. All pads but

RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

Table 19. FAST configuration output buffer electrical characteristics

Value

Symbol C

Parameter

Conditions¹

Unit

Min

Typ

Max

V_OHCC P Output high level

FAST configuration

Push Pull I_OH= −14mA,

0.8V_DD

—

V

V_DD= 5.0 V 10%, PAD3V5V = 0

(recommended)

C

I

_OH= −7mA,

0.8V_DD

—

V_DD= 5.0 V 10%, PAD3V5V = 1²

I

_OH= −11mA,

V_DD−0.8

V_DD= 3.3 V 10%, PAD3V5V = 1

(recommended)

V_OLCC P Output low level

FAST configuration

Push Pull I_OL= 14mA,

—

0.1V_DD

V

V_DD= 5.0 V 10%, PAD3V5V = 0

(recommended)

C

I

_OL= 7mA,

—

0.1V_DD

0.5

V_DD= 5.0 V 10%, PAD3V5V = 1²

I_OL= 11mA,

V_DD= 3.3 V 10%, PAD3V5V = 1

(recommended)

1

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= −40 to 125 °C, unless otherwise specified

The configuration PAD3V5 = 1 when V_DD= 5 V is only a transient configuration during power-up. All pads but

RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

2

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

41

Package pinouts and signal descriptions

2.15.4 Output pin transition times

Table 20. Output pin transition times

Value

Symbol C

Parameter

Conditions¹

Unit

Min Typ Max

t_trCC D Output transition time output C_L= 25 pF V_DD= 5.0 V 10%, PAD3V5V = 0

pin²

—

50 ns

100

125

50

T

D

T

C_L= 50 pF

SLOW configuration

C_L= 100 pF

C_L= 25 pF V_DD= 3.3 V 10%, PAD3V5V = 1

C_L= 50 pF

100

125

10 ns

20

D

C_L= 100 pF

t_trCC D Output transition time output C_L= 25 pF V_DD= 5.0 V 10%, PAD3V5V = 0

pin²

SIUL.PCRx.SRC = 1

T

D

T

C_L= 50 pF

MEDIUM configuration

C_L= 100 pF

40

C_L= 25 pF V_DD= 3.3 V 10%, PAD3V5V = 1

12

SIUL.PCRx.SRC = 1

C_L= 50 pF

25

D

C_L= 100 pF

40

t_trCC D Output transition time output C_L= 25 pF V_DD= 5.0 V 10%, PAD3V5V = 0

4

6

ns

pin²

C_L= 50 pF

FAST configuration

C_L= 100 pF

12

4

C_L= 25 pF V_DD= 3.3 V 10%, PAD3V5V = 1

C_L= 50 pF

7

C_L= 100 pF

12

1

2

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= −40 to 125 °C, unless otherwise specified

C_Lincludes device and package capacitances (C_PKG< 5 pF).

2.15.5 I/O pad current specification

The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a

V

/V supply pair as described in Table 21.

DD SS

Table 21. I/O supply segment

Supply segment

Package

1

2

3

4

5

6

208 MAPBGA¹

144 LQFP

100 LQFP

64 LQFP

Equivalent to 144 LQFP segment pad distribution

pin20–pin49 pin51–pin99 pin100–pin122 pin 123–pin19

MCKO

—

MDOn/MSEO

—

pin16–pin35

pin8–pin26

pin37–pin69

pin28–pin55

pin70–pin83

pin56–pin7

pin 84–pin15

—

MPC5604B/C Microcontroller Data Sheet, Rev. 14

42

NXP Semiconductors

Package pinouts and signal descriptions

1

208 MAPBGA available only as development package for Nexus2+

Table 22 provides I/O consumption figures.

In order to ensure device reliability, the average current of the I/O on a single segment should remain below

the I

maximum value.

AVGSEG

Table 22. I/O consumption

Conditions¹

Value

Symbol

C

Parameter

Unit

Min

Typ Max

,2

I_SWTSLWCC D Dynamic I/O current for C_L= 25 pF

SLOW configuration

V_DD= 5.0 V 10%,

PAD3V5V = 0

—

20

16

29

17

mA

V_DD= 3.3 V 10%,

PAD3V5V = 1

—

2

I_SWTMEDCC D Dynamic I/O current for C_L= 25 pF

V_DD= 5.0 V 10%,

PAD3V5V = 0

mA

MEDIUM configuration

V_DD= 3.3 V 10%,

PAD3V5V = 1

2

I_SWTFSTCC D Dynamic I/O current for C_L= 25 pF

V_DD= 5.0 V 10%,

PAD3V5V = 0

110 mA

50

FAST configuration

V_DD= 3.3 V 10%,

PAD3V5V = 1

I_RMSSLWCC D Root mean square I/O C_L= 25 pF, 2 MHz

V_DD= 5.0 V 10%,

PAD3V5V = 0

—

2.3 mA

3.2

current for SLOW

C_L= 25 pF, 4 MHz

configuration

C_L= 100 pF, 2 MHz

C_L= 25 pF, 2 MHz

C_L= 25 pF, 4 MHz

C_L= 100 pF, 2 MHz

6.6

V_DD= 3.3 V 10%,

PAD3V5V = 1

1.6

2.3

4.7

I_RMSMEDCC D Root mean square I/O C_L= 25 pF, 13 MHz V_DD= 5.0 V 10%,

6.6 mA

13.4

18.3

5

current for MEDIUM

configuration

PAD3V5V = 0

C_L= 25 pF, 40 MHz

C_L= 100 pF, 13 MHz

C_L= 25 pF, 13 MHz V_DD= 3.3 V 10%,

PAD3V5V = 1

C_L= 25 pF, 40 MHz

8.5

C_L= 100 pF, 13 MHz

11

I_RMSFSTCC D Root mean square I/O C_L= 25 pF, 40 MHz V_DD= 5.0 V 10%,

22

33

56

14

20

35

mA

current for FAST

configuration

PAD3V5V = 0

C_L= 25 pF, 64 MHz

C_L= 100 pF, 40 MHz

C_L= 25 pF, 40 MHz V_DD= 3.3 V 10%,

PAD3V5V = 1

C_L= 25 pF, 64 MHz

C_L= 100 pF, 40 MHz

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

43

Package pinouts and signal descriptions

Table 22. I/O consumption (continued)

Conditions¹

Value

Symbol

C

Parameter

Unit

Min

Typ Max

I_AVGSEGSR D Sum of all the static I/O V_DD= 5.0 V 10%, PAD3V5V = 0

current within a supply

segment

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= −40 to125 °C, unless otherwise specified

Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.

—

70

65

mA

V

_DD= 3.3 V 10%, PAD3V5V = 1

1

2

Table 23 provides the weight of concurrent switching I/Os.

Due to the dynamic current limitations, the sum of the weight of concurrent switching I/Os on a single

segment must not exceed 100% to ensure device functionality.

1

Table 23. I/O weight

144/100 LQFP

Weight 5 V Weight 3.3 V

SRC³= 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1

64 LQFP

Supply segment

Weight 5 V

Weight 3.3 V

Pad

144

100

64

LQFP LQFP LQFP²

4

3

PB[3]

PC[9]

PC[14]

PC[15]

PG[5]

PG[4]

PG[3]

PG[2]

PA[2]

10%

9%

8%

7%

6%

5%

—

12%

11%

10%

9%

—

10%

—

8%

—

12%

—

7%

—

3

—

13%

—

12%

—

4

—

12%

—

11%

—

4

12%

—

10%

—

8%

—

9%

—

3

PE[0]

PA[1]

—

9%

—

9%

—

7%

—

9%

—

3

PE[1]

PE[8]

PE[9]

PE[10]

PA[0]

10%

9%

—

8%

9%

8%

—

8%

—

7%

—

7%

—

8%

—

6%

7%

—

5%

—

6%

—

PE[11]

6%

MPC5604B/C Microcontroller Data Sheet, Rev. 14

44

NXP Semiconductors

Package pinouts and signal descriptions

64 LQFP

1

Table 23. I/O weight (continued)

144/100 LQFP

Supply segment

Weight 5 V

Weight 3.3 V

Weight 5 V

Weight 3.3 V

Pad

144

100

64

SRC³= 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1

LQFP LQFP LQFP²

1

—

1

—

1

PG[9]

PG[8]

PC[11]

PC[10]

PG[7]

PG[6]

PB[0]

9%

—

10%

11%

12%

11%

10%

9%

—

9%

—

9%

13%

14%

—

12%

—

9%

—

13%

—

11%

—

12%

—

1

—

1

10%

9%

—

10%

—

14%

—

12%

—

12%

—

PB[1]

—

1

—

1

PF[9]

—

PF[8]

15%

—

13%

—

PF[12]

PC[6]

PC[7]

PF[10]

PF[11]

PA[15]

PF[13]

PA[14]

PA[4]

—

10%

—

12%

—

1

—

1

14%

—

12%

—

12%

—

11%

—

9%

—

12%

—

10%

—

11%

—

1

—

1

8%

11%

—

10%

—

8%

7%

11%

—

9%

8%

10%

—

8%

9%

PA[13]

PA[12]

7%

10%

—

9%

—

10%

—

9%

—

7%

8%

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

45

Package pinouts and signal descriptions

Supply segment

1

Table 23. I/O weight (continued)

144/100 LQFP

64 LQFP

Weight 3.3 V

SRC³= 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1

Weight 5 V

Weight 3.3 V

Weight 5 V

Pad

144

100

64

LQFP LQFP LQFP²

2

PB[9]

PB[8]

PB[10]

PF[0]

PF[1]

PF[2]

PF[3]

PF[4]

PF[5]

PF[6]

PF[7]

PD[0]

PD[1]

PD[2]

PD[3]

PD[4]

PD[5]

PD[6]

PD[7]

PD[8]

PB[4]

PB[5]

PB[6]

PB[7]

PD[9]

PD[10]

PD[11]

PB[11]

PD[12]

PB[12]

PD[13]

1%

6%

7%

8%

9%

1%

11%

10%

—

1%

7%

8%

9%

10%

1%

13%

12%

—

1%

6%

—

1%

7%

—

2

—

2

—

1%

—

1%

2%

—

2

—

17%

—

21%

—

2

18%

—

21%

—

MPC5604B/C Microcontroller Data Sheet, Rev. 14

46

NXP Semiconductors

Package pinouts and signal descriptions

64 LQFP

1

Table 23. I/O weight (continued)

144/100 LQFP

Supply segment

Weight 5 V

Weight 3.3 V

Weight 5 V

Weight 3.3 V

Pad

144

100

64

SRC³= 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1

LQFP LQFP LQFP²

2

—

2

PB[13]

PD[14]

PB[14]

PD[15]

PB[15]

PA[3]

10%

9%

5%

4%

3%

4%

5%

6%

7%

6%

—

12%

11%

10%

6%

5%

4%

5%

6%

7%

8%

7%

—

18%

—

9%

21%

—

8%

—

18%

—

21%

—

2

—

18%

—

21%

—

3

—

2

PG[13]

PG[12]

PH[0]

13%

12%

8%

7%

6%

—

11%

7%

6%

5%

—

PH[1]

—

PH[2]

—

PH[3]

—

PG[1]

PG[0]

PF[15]

PF[14]

PE[13]

PA[7]

—

4%

—

4%

—

3

—

5%

—

5%

—

16%

15%

14%

—

19%

18%

17%

—

PA[8]

—

PA[9]

—

PA[10]

PA[11]

PE[12]

PG[14]

PG[15]

PE[14]

PE[15]

PG[10]

PG[11]

PC[3]

—

2

—

3

—

10%

—

9%

—

9%

—

8%

—

9%

—

8%

—

7%

6%

9%

8%

PC[2]

8%

7%

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

47

Package pinouts and signal descriptions

Supply segment

1

Table 23. I/O weight (continued)

144/100 LQFP

64 LQFP

Weight 3.3 V

SRC³= 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1

Weight 5 V

Weight 3.3 V

Weight 5 V

Pad

144

100

64

LQFP LQFP LQFP²

3

4

3

4

2

PA[5]

PA[6]

5%

4%

5%

6%

7%

—

6%

—

6%

5%

6%

7

8%

—

7%

6%

5%

7%

8

7%

—

PH[10]

PC[1]

PC[0]

PH[9]

PE[2]

PE[3]

PC[5]

PC[4]

PE[4]

PE[5]

PH[4]

PH[5]

PH[6]

PH[7]

PH[8]

PE[6]

PE[7]

PC[12]

PC[13]

PC[8]

PB[2]

6%

5%

7%

—

6%

—

5%

—

3

9%

7%

8%

9%

7

8%

8

7

8

—

3

7%

10%

11%

12%

13%

—

9%

—

8%

9%

—

8%

9%

10%

11%

—

8%

—

11%

12%

—

9%

10%

—

10%

—

8%

10%

11%

12%

—

3

9%

—

4

9%

—

9%

—

9%

13%

14%

—

12%

13%

—

9%

—

10%

—

10%

—

12%

—

15%

13%

15%

13%

1

2

3

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= −40 to125 °C, unless otherwise specified

Segments shown apply to MPC560xB devices only

SRC: “Slew Rate Control” bit in SIU_PCR

2.16 RESET electrical characteristics

The device implements a dedicated bidirectional RESET pin.

MPC5604B/C Microcontroller Data Sheet, Rev. 14

48

NXP Semiconductors

Package pinouts and signal descriptions

V

DD

V

DDMIN

RESET

V

IH

V

IL

device reset forced by RESET

device start-up phase

Figure 8. Start-up reset requirements

V_RESET

hw_rst

‘1’

V

DD

V

IH

V

IL

‘0’

filtered by

lowpass filter

unknown reset

state

filtered by

hysteresis

filtered by

lowpass filter

device under hardware reset

W

FRST

W

NFRST

Figure 9. Noise filtering on reset signal

Table 24. Reset electrical characteristics

Value

Symbol

C

Parameter

Conditions¹

Unit

Min

Typ

Max

V_IH

SR P Input High Level CMOS

(Schmitt Trigger)

—

0.65V_DD

—

V_DD+0.4

V

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

49

Package pinouts and signal descriptions

Table 24. Reset electrical characteristics (continued)

Value

Symbol

C

Parameter

Conditions¹

Unit

Min

Typ

Max

V_ILSR P Input low Level CMOS

(Schmitt Trigger)

—

−0.4

—

0.35V_DD

V

V_HYSCC C Input hysteresis CMOS

(Schmitt Trigger)

0.1V_DD

—

V_OLCC P Output low level

Push Pull, I_OL= 2mA,

0.1V_DD

V_DD= 5.0 V 10%, PAD3V5V = 0

(recommended)

C

Push Pull, I_OL= 1mA,

—

0.1V_DD

0.5

V_DD= 5.0 V 10%, PAD3V5V = 1²

Push Pull, I_OL= 1mA,

V_DD= 3.3 V 10%, PAD3V5V = 1

(recommended)

t_tr

CC D Output transition time

output pin³

C_L= 25pF,

V_DD= 5.0 V 10%, PAD3V5V = 0

—

10

20

40

12

25

40

—

ns

C_L= 50pF,

V_DD= 5.0 V 10%, PAD3V5V = 0

C_L= 100pF,

V_DD= 5.0 V 10%, PAD3V5V = 0

—

C_L= 25pF,

V_DD= 3.3 V 10%, PAD3V5V = 1

—

C_L= 50pF,

V_DD= 3.3 V 10%, PAD3V5V = 1

—

C_L= 100pF,

V_DD= 3.3 V 10%, PAD3V5V = 1

—

W_FRSTSR P RESET input filtered

pulse

—

ns

µA

W_NFRSTSR P RESET input not filtered

pulse

—

1000

|I_WPU

|

CC P Weak pull-up current

V_DD= 3.3 V 10%, PAD3V5V = 1

V_DD= 5.0 V 10%, PAD3V5V = 0

V_DD= 5.0 V 10%, PAD3V5V = 1²

10

—

150

250

absolute value

D

P

1

2

3

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= −40 to 125 °C, unless otherwise specified

This transient configuration does not occurs when device is used in the V_DD= 3.3 V 10% range.

C_Lincludes device and package capacitance (C_PKG< 5 pF).

MPC5604B/C Microcontroller Data Sheet, Rev. 14

50

NXP Semiconductors

Package pinouts and signal descriptions

2.17 Power management electrical characteristics

2.17.1 Voltage regulator electrical characteristics

The device implements an internal voltage regulator to generate the low voltage core supply V

from

DD_LV

the high voltage ballast supply V

. The regulator itself is supplied by the common I/O supply V

.

DD_BV

DD

The following supplies are involved:

•

HV—High voltage external power supply for voltage regulator module. This must be provided

externally through VDD_HV power pin.

BV—High voltage external power supply for internal ballast module. This must be provided

externally through VDD_BV power pin. Voltage values should be aligned with V

.

DD

LV—Low voltage internal power supply for core, FMPLL and flash digital logic. This is generated

by the internal voltage regulator but provided outside to connect stability capacitor. It is further

split into four main domains to ensure noise isolation between critical LV modules within the

device:

— LV_COR—Low voltage supply for the core. It is also used to provide supply for FMPLL

through double bonding.

— LV_CFLA—Low voltage supply for code flash module. It is supplied with dedicated ballast

and shorted to LV_COR through double bonding.

— LV_DFLA—Low voltage supply for data flash module. It is supplied with dedicated ballast

and shorted to LV_COR through double bonding.

— LV_PLL—Low voltage supply for FMPLL. It is shorted to LV_COR through double bonding.

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

51

Package pinouts and signal descriptions

C

(LV_COR/LV_CFLA)

REG2

VDD_HV

VSS_LV

VDD_LV

VDD_BV

V

REF

Voltage Regulator

DEVICE

VDD_BV

VDD_LV

DEVICE

VDD_LVn

VSS_LVn

I

VSS_LV

VDD_LV

VSS_HV

VDD_HV

C

DEC2

REG3

(LV_COR/LV_PLL)

(supply/IO decoupling)

Figure 10. Voltage regulator capacitance connection

The internal voltage regulator requires external capacitance (C

) to be connected to the device in order

REGn

to provide a stable low voltage digital supply to the device. Capacitances should be placed on the board as

near as possible to the associated pins. Care should also be taken to limit the serial inductance of the board

to less than 5 nH.

Each decoupling capacitor must be placed between each of the three V

/V

supply pairs to

DD_LV SS_LV

ensure stable voltage (see 2.13, Recommended operating conditions).

The internal voltage regulator requires a controlled slew rate of both V

Figure 11.

and V

as described in

DD_HV

DD_BV

MPC5604B/C Microcontroller Data Sheet, Rev. 14

52

NXP Semiconductors

Package pinouts and signal descriptions

V

DD_HV

V

(MAX)

DD_HV

d

dt

VDD

V

(MIN)

DD_HV

POWER UP

FUNCTIONAL RANGE

POWER DOWN

Figure 11. V

and V

maximum slope

DD_BV

DD_HV

When STANDBY mode is used, further constraints are applied to the both V

and V

in order

DD_HV

DD_BV

to guarantee correct regulator function during STANDBY exit. This is described on Figure 12.

STANDBY regulator constraints should normally be guaranteed by implementing equivalent of CSTDBY

capacitance on application board (capacitance and ESR typical values), but would actually depend on

exact characteristics of application external regulator.

V

DD_HV

(MAX)

ΔVDD(STDBY)

V

(MIN)

DD_LV

DD_HV

d

dt

VDD(STDBY)

V

(NOMINAL)

DD_LV

0V

Figure 12. V

and V

supply constraints during STANDBY mode exit

DD_BV

DD_HV

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

53

Package pinouts and signal descriptions

Table 25. Voltage regulator electrical characteristics

Value

Symbol

C

Parameter

Conditions¹

Unit

Min Typ Max

C_REGn

R_REG

SR — Internal voltage regulator external

capacitance

—

200

—

500

0.2

—

nF

Ω

SR — Stability capacitor equivalent serial Range:

—

resistance

10 kHz to 20 MHz

C_DEC1

SR — Decoupling capacitance²ballast V_{DD_BV}/V_{SS_LV}pair:

100³470⁴

400

nF

V

_{DD_BV}= 4.5 V to 5.5 V

V

_{DD_BV}/V_{SS_LV}pair:

—

V_{DD_BV}= 3 V to 3.6 V

SR — Decoupling capacitance regulator V_DD/V_SSpair

C_DEC2

10

—

100

—

nF

supply

SR — Maximum slope on V_DD

250 mV/µs

d

VDD

dt

|Δ_VDD(STDBY)

|

SR — Maximum instant variation on V_DD

during standby exit

—

30

mV

SR — Maximum slope on V_DDduring

standby exit

15 mV/µs

d

dt

VDD(STDBY)

V_MREG

CC T Main regulator output voltage

P

Before exiting from

reset

—

1.32

—

V

After trimming

—

1.16 1.28

—

I_MREG

SR — Main regulator current provided to

V_{DD_LV}domain

—

150

mA

I_MREGINT

CC D Main regulator module current

consumption

I_MREG= 200 mA

I_MREG= 0 mA

After trimming

—

2

1

V_LPREG

I_LPREG

CC P Low power regulator output

voltage

1.16 1.28

—

V

SR — Low power regulator current

provided to V_{DD_LV}domain

—

5

15

600

—

mA

µA

—

I_LPREGINT

CC D Low power regulator module

current consumption

I_LPREG= 15 mA;

T_A= 55 °C

—

I_LPREG= 0 mA;

T_A= 55 °C

V_ULPREG

CC P Ultra low power regulator output

voltage

After trimming

1.16 1.28

—

V

MPC5604B/C Microcontroller Data Sheet, Rev. 14

54

NXP Semiconductors

Package pinouts and signal descriptions

Table 25. Voltage regulator electrical characteristics (continued)

Value

Symbol

C

Parameter

Conditions¹

Unit

Min Typ Max

I_ULPREG

I_ULPREGINT

SR — Ultra low power regulator current

provided to V_{DD_LV}domain

—

2

5

mA

µA

CC D Ultra low power regulator module I_ULPREG= 5 mA;

100

—

current consumption

T_A= 55 °C

I_ULPREG= 0 mA;

T_A= 55 °C

I_{DD_BV}

CC D In-rush average current on V_{DD_BV}

during power-up⁵

—

300⁶mA

1

2

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= −40 to 125 °C, unless otherwise specified

This capacitance value is driven by the constraints of the external voltage regulator supplying the V_{DD_BV}voltage.

A typical value is in the range of 470 nF.

3

4

This value is acceptable to guarantee operation from 4.5 V to 5.5 V

External regulator and capacitance circuitry must be capable of providing I_{DD_BV}while maintaining supply V_{DD_BV}

in operating range.

5

6

In-rush average current is seen only for short time (maximum 20 µs) during power-up and on standby exit. It is

dependant on the sum of the C_REGncapacitances.

The duration of the in-rush current depends on the capacitance placed on LV pins. BV decoupling capacitors must

be sized accordingly. Refer to I_MREGvalue for minimum amount of current to be provided in cc.

The |Δ

| and dVDD(STDBY)/dt system requirement can be used to define the component used

for the V supply generation. The following two examples describe how to calculate capacitance size:

VDD(STDBY)

DD

Example 1. No regulator (worst case)

The |Δ

| parameter can be seen as the V voltage drop through the ESR resistance of the

DD

VDD(STDBY)

regulator stability capacitor when the I

current required to load V

domain during the standby

DD_BV

DD_LV

exit. It is thus possible to define the maximum equivalent resistance ESR

(MAX) of the total

STDBY

capacitance on the V supply:

DD

1

ESR

(MAX) = |Δ

|/I

= (30 mV)/(300 mA) = 0.1Ω

STDBY

VDD(STDBY) DD_BV

The dVDD(STDBY)/dt parameter can be seen as the V voltage drop at the capacitance pin (excluding

DD

ESR drop) while providing the I

supply required to load V

domain during the standby exit. It

(MIN) of the total capacitance on

DD_BV

DD_LV

STDBY

is thus possible to define the minimum equivalent capacitance C

the V supply:

DD

C

(MIN) = I

/dVDD(STDBY)/dt = (300 mA)/(15 mV/µs) = 20 µF

STDBY

DD_BV

This configuration is a worst case, with the assumption no regulator is available.

1. Based on typical time for standby exit sequence of 20 µs, ESR(MIN) can actually be considered at ~50 kHz.

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

55

Package pinouts and signal descriptions

Example 2. Simplified regulator

The regulator should be able to provide significant amount of the current during the standby exit process.

For example, in case of an ideal voltage regulator providing 200 mA current, it is possible to recalculate

the equivalent ESR

(MAX) and C

(MIN) as follows:

STDBY

ESR

(MAX) = |Δ

|/(I

− 200 mA) = (30 mV)/(100 mA) = 0.3 Ω

STDBY

VDD(STDBY) DD_BV

C

(MIN) = (I

− 200 mA)/dVDD(STDBY)/dt = (300 mA − 200 mA)/(15 mV/µs) = 6.7 µF

DD_BV

STDBY

In case optimization is required, C

(MIN) and ESR

(MAX) should be calculated based on the

STDBY

regulator characteristics as well as the board V plane characteristics.

DD

2.17.2 Low voltage detector electrical characteristics

The device implements a Power-on Reset (POR) module to ensure correct power-up initialization, as well

as four low voltage detectors (LVDs) to monitor the V and the V

voltage while device is supplied:

DD

DD_LV

•

POR monitors V during the power-up phase to ensure device is maintained in a safe reset state

DD

(refer to RGM Destructive Event Status (RGM_DES) Register flag F_POR in device reference

manual)

•

LVDHV3 monitors V to ensure device reset below minimum functional supply (refer to RGM

Destructive Event Status (RGM_DES) Register flag F_LVD27 in device reference manual)

DD

LVDHV5 monitors V when application uses device in the 5.0 V ± 10% range (refer to RGM

DD

Functional Event Status (RGM_FES) Register flag F_LVD45 in device reference manual)

LVDLVCOR monitors power domain No. 1 (refer to RGM Destructive Event Status (RGM_DES)

Register flag F_LVD12_PD1 in device reference manual

LVDLVBKP monitors power domain No. 0 (refer to RGM Destructive Event Status (RGM_DES)

Register flag F_LVD12_PD0 in device reference manual)

NOTE

When enabled, power domain No. 2 is monitored through LVDLVBKP.

MPC5604B/C Microcontroller Data Sheet, Rev. 14

56

NXP Semiconductors

Package pinouts and signal descriptions

V

DD

V

LVDHVxH

LVDHVxL

RESET

Figure 13. Low voltage detector vs reset

NOTE

Figure 13 does not apply to LVDHV5 low voltage detector because

LVDHV5 is automatically disabled during reset and it must be enabled by

software again. Once the device is forced to reset by LVDHV5, the

LVDHV5 is disabled and reset is released as soon as internal reset sequence

is completed regardless of LVDHV5H threshold.

Table 26. Low voltage detector electrical characteristics

Value

Symbol

C

Parameter

Conditions¹

Unit

Min

Typ

Max

V_PORUP

V_PORH

SR P Supply for functional POR module

CC P Power-on reset threshold

—

1.0

1.5

—

5.5

2.6

V

T_A= 25 °C,

after trimming

T

—

1.5

—

2.6

2.95

2.9

V_LVDHV3HCC T LVDHV3 low voltage detector high threshold

V_LVDHV3LCC P LVDHV3 low voltage detector low threshold

V_LVDHV5HCC T LVDHV5 low voltage detector high threshold

V_LVDHV5LCC P LVDHV5 low voltage detector low threshold

V_LVDLVCORLCC P LVDLVCOR low voltage detector low threshold

V_LVDLVBKPLCC P LVDLVBKP low voltage detector low threshold

2.6

—

4.5

3.8

1.08

4.4

1.16

1

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= −40 to 125 °C, unless otherwise specified

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

57

Package pinouts and signal descriptions

2.18 Power consumption

Table 27 provides DC electrical characteristics for significant application modes. These values are

indicative values; actual consumption depends on the application.

Table 27. Power consumption on VDD_BV and VDD_HV

Value

Symbol

C

Parameter

Conditions¹

Unit

115 140³mA

Min Typ Max

2

I_DDMAX

CC D RUN mode maximum

average current

—

4

I_DDRUN

CC T RUNmodetypicalaverage f_CPU= 8 MHz

current⁵

—

7

—

mA

T

f_CPU= 16 MHz

18

29

40

51

8

T

f_CPU= 32 MHz

_CPU= 48 MHz

—

P

f

100

125

15

P

f_CPU= 64 MHz

I_DDHALT

CC C HALT mode current⁶

Slow internal RC oscillator T_A= 25 °C

mA

(128 kHz) running

P

T_A= 125 °C

14

25

I_DDSTOPCC P STOP mode current⁷

Slow internal RC oscillator T_A= 25 °C

180 700⁸µA

(128 kHz) running

D

P

T_A= 55 °C

500

1

—

6⁸

T_A= 85 °C

T_A= 105 °C

T_A= 125 °C

mA

µA

2

9⁸

4.5

30

75

180

12⁸

100

—

I_DDSTDBY2CC P STANDBY2 mode current⁹Slow internal RC oscillator T_A= 25 °C

(128 kHz) running

D

T_A= 55 °C

T_A= 85 °C

D

700

D

T_A= 105 °C

315 1000

560 1700

P

T_A= 125 °C

I_DDSTDBY1CC T STANDBY1 mode

Slow internal RC oscillator T_A= 25 °C

(128 kHz) running

20

45

60

—

µA

current¹⁰

D

T_A= 55 °C

D

T_A= 85 °C

T_A= 105 °C

T_A= 125 °C

100

165

280

350

500

900

1

2

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= −40 to 125 °C, unless otherwise specified

I_DDMAXis drawn only from the V_{DD_BV}pin. Running consumption does not include I/Os toggling which is highly

dependent on the application. The given value is thought to be a worst case value with all peripherals running, and

code fetched from code flash while modify operation ongoing on data flash. Notice that this value can be significantly

reduced by application: switch off not used peripherals (default), reduce peripheral frequency through internal

prescaler, fetch from RAM most used functions, use low power mode when possible.

3

4

Higher current may be sinked by device during power-up and standby exit. Please refer to in rush current on Table 25.

I_DDRUNis drawn only from the V_{DD_BV}pin. RUN current measured with typical application with accesses on both flash

and RAM.

MPC5604B/C Microcontroller Data Sheet, Rev. 14

58

NXP Semiconductors

Package pinouts and signal descriptions

5

6

Only for the “P” classification: Data and Code Flash in Normal Power. Code fetched from RAM: Serial IPs CAN and

LIN in loop back mode, DSPI as Master, PLL as system Clock (4 x Multiplier) peripherals on (eMIOS/CTU/ADC) and

running at max frequency, periodic SW/WDG timer reset enabled.

Data Flash Power Down. Code Flash in Low Power. SIRC (128 kHz) and FIRC (16 MHz) on. 10 MHz XTAL clock.

FlexCAN: instances: 0, 1, 2 ON (clocked but not reception or transmission), instances: 4, 5, 6 clock gated. LINFlex:

instances: 0, 1, 2 ON (clocked but not reception or transmission), instance: 3 clock gated. eMIOS: instance: 0 ON (16

channels on PA[0]–PA[11] and PC[12]–PC[15]) with PWM 20 kHz, instance: 1 clock gated. DSPI: instance: 0 (clocked

but no communication). RTC/API ON. PIT ON. STM ON. ADC ON but not conversion except 2 analog watchdog.

7

8

Only for the “P” classification: No clock, FIRC (16 MHz) off, SIRC (128 kHz) on, PLL off, HPvreg off,

ULPVreg/LPVreg on. All possible peripherals off and clock gated. Flash in power down mode.

When going from RUN to STOP mode and the core consumption is > 6 mA, it is normal operation for the main

regulator module to be kept on by the on-chip current monitoring circuit. This is most likely to occur with junction

temperatures exceeding 125 °C and under these circumstances, it is possible for the current to initially exceed the

maximum STOP specification by up to 2 mA. After entering stop, the application junction temperature will reduce to

the ambient level and the main regulator will be automatically switched off when the load current is below 6 mA.

9

Only for the “P” classification: ULPreg on, HP/LPVreg off, 32 KB RAM on, device configured for minimum

consumption, all possible modules switched off.

¹⁰ULPreg on, HP/LPVreg off, 8 KB RAM on, device configured for minimum consumption, all possible modules

switched off.

2.19 Flash memory electrical characteristics

2.19.1 Program/Erase characteristics

Table 28 shows the program and erase characteristics.

Table 28. Program and erase specifications

Value

Symbol

C

Parameter

Unit

Initial

max²

Min

Typ¹

Max³

T_dwprogramCC C Double word (64 bits) program time⁴

—

22

300

400

800

—

50

500

600

1300

30

500

5000

7500

30

µs

ms

µs

T_16Kpperase

T_32Kpperase

T_128Kpperase

T_esus

16 KB block preprogram and erase time

32 KB block preprogram and erase time

128 KB block preprogram and erase time

CC D Erase suspend latency

1

2

3

Typical program and erase times assume nominal supply values and operation at 25 °C.

Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.

The maximum program and erase times occur after the specified number of program/erase cycles. These maximum

values are characterized but not guaranteed.

4

Actual hardware programming times. This does not include software overhead.

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

59

Package pinouts and signal descriptions

Table 29. Flash module life

Conditions

Value

Symbol

C

Parameter

Unit

Min

Typ

Max

P/E

CC C Number of program/erase cycles 16 KB blocks

100,000

—

cycles

per block over the operating

temperature range (T_J)

32 KB blocks

10,000 100,000

1,000 100,000

128 KB blocks

Retention CC C Minimum data retention at 85 °C Blocks with

average ambient temperature¹

0–1,000 P/E cycles

20

10

5

—

years

Blocks with

1,001–10,000 P/E cycles

—

Blocks with

10,001–100,000 P/E cycles

1

Ambient temperature averaged over duration of application, not to exceed recommended product operating

temperature range.

ECC circuitry provides correction of single bit faults and is used to improve further automotive reliability

results. Some units will experience single bit corrections throughout the life of the product with no impact

to product reliability.

Table 30. Flash read access timing

Symbol

C

Parameter

Conditions¹

Max Unit

f_READCC P Maximum frequency for Flash reading

2 wait states

1 wait state

0 wait states

64

40

20

MHz

C

1

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= −40 to 125 °C, unless otherwise specified

2.19.2 Flash power supply DC characteristics

Table 31 shows the power supply DC characteristics on external supply.

Table 31. Flash memory power supply DC electrical characteristics

Value

Min Typ Max

Symbol

C

Parameter

Conditions¹

Unit

2

I_FREADCC D Sum of the current consumption on

Code flash memory module read

—

15

33 mA

VDD_HV and VDD_BV on read access f_CPU= 64 MHz³

Data flash memory module read

_CPU= 64 MHz³

—

15

33

f

MPC5604B/C Microcontroller Data Sheet, Rev. 14

60

NXP Semiconductors

Package pinouts and signal descriptions

Table 31. Flash memory power supply DC electrical characteristics

Value

Symbol

C

Parameter

Conditions¹

Unit

Min Typ Max

2

I_FMODCC D Sum of the current consumption on

VDD_HV and VDD_BV on matrix

Program/Erase ongoing while

reading code flash memory

registers f_CPU= 64 MHz³

—

15

33 mA

modification (program/erase)

Program/Erase ongoing while

reading data flash memory

registers f_CPU= 64 MHz³

—

15

33

I_FLPWCC D Sum of the current consumption on

VDD_HV and VDD_BV

During code flash memory

low-power mode

—

900 µA

900

During data flash memory

low-power mode

I_FPWDCC D Sum of the current consumption on

VDD_HV and VDD_BV

During code flash memory

power-down mode

150 µA

150

During data flash memory

power-down mode

1

2

3

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= −40 to 125 °C, unless otherwise specified

This value is only relative to the actual duration of the read cycle

f_CPU64 MHz can be achieved only at up to 105 °C

2.19.3 Start-up/Switch-off timings

Table 32. Start-up time/Switch-off time

Value

Typ

Symbol

C

Parameter

Conditions¹

Unit

Min

Max

125

T_FLARSTEXITCC T Delay for Flash module to exit reset mode

T

Code Flash

Data Flash

Code Flash

Data Flash

Code Flash

Data Flash

Code Flash

Data Flash

Code Flash

Data Flash

—

µs

125

0.5

30

T_FLALPEXIT

CC T Delay for Flash module to exit low-power

mode

T

T_FLAPDEXIT

CC T Delay for Flash module to exit power-down

mode

T

30

T_FLALPENTRYCC T Delay for Flash module to enter low-power

0.5

1.5

mode

T

T_FLAPDENTRYCC T

Delay for Flash module to enter power-down

mode

T

1

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= −40 to 125 °C, unless otherwise specified

2.20 Electromagnetic compatibility (EMC) characteristics

Susceptibility tests are performed on a sample basis during product characterization.

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

61

Package pinouts and signal descriptions

2.20.1 Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application

environment and simplified MCU software. It should be noted that good EMC performance is highly

dependent on the user application and the software in particular.

Therefore it is recommended that the user apply EMC software optimization and prequalification tests in

relation with the EMC level requested for his application.

•

Software recommendations: The software flowchart must include the management of runaway

conditions such as:

— Corrupted program counter

— Unexpected reset

— Critical data corruption (control registers...)

•

Prequalification trials: Most of the common failures (unexpected reset and program counter

corruption) can be reproduced by manually forcing a low state on the reset pin or the oscillator pins

for 1 second.

To complete these trials, ESD stress can be applied directly on the device. When unexpected

behavior is detected, the software can be hardened to prevent unrecoverable errors occurring.

2.20.2 Electromagnetic interference (EMI)

The product is monitored in terms of emission based on a typical application. This emission test conforms

to the IEC 61967-1 standard, which specifies the general conditions for EMI measurements.

1,2

Table 33. EMI radiated emission measurement

Value

Symbol

C

Parameter

Conditions

Unit

Min Typ Max

—

SR — Scan range

—

0.150

—

64

1000 MHz

f_CPUSR — Operating frequency

—

MHz

V

_{DD_LV}SR — LV operating voltages

—

1.28

—

S_EMICC T Peak level

V_DD= 5 V, T_A= 25 °C,

LQFP144 package

No PLL frequency

modulation

—

18 dBµV

Test conforming to IEC 61967-2,

f_OSC= 8 MHz/f_CPU= 64 MHz

2% PLL frequency

modulation

—

14 dBµV

1

2

EMI testing and I/O port waveforms per IEC 61967-1, -2, -4

For information on conducted emission and susceptibility measurement (norm IEC 61967-4), please contact your

local marketing representative.

2.20.3 Absolute maximum ratings (electrical sensitivity)

Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed

in order to determine its performance in terms of electrical sensitivity.

MPC5604B/C Microcontroller Data Sheet, Rev. 14

62

NXP Semiconductors

Package pinouts and signal descriptions

2.20.3.1 Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of

each sample according to each pin combination. The sample size depends on the number of supply pins in

the device (3 parts*(n+1) supply pin). This test conforms to the AEC-Q100-002/-003/-011 standard.

1 2

Table 34. ESD absolute maximum ratings

Symbol

C

Ratings

Conditions

T_A= 25 °C

Class Max value

Unit

V_ESD(HBM)CC T Electrostatic discharge voltage

(Human Body Model)

H1C

2000

V

conforming to AEC-Q100-002

V_ESD(MM)CC T Electrostatic discharge voltage

(Machine Model)

T_A= 25 °C

conforming to AEC-Q100-003

M2

200

V_ESD(CDM)CC T Electrostatic discharge voltage

(Charged Device Model)

T_A= 25 °C

conforming to AEC-Q100-011

C3A

500

750 (corners)

1

All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated

Circuits.

2

A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device

specification requirements. Complete DC parametric and functional testing shall be performed per applicable

device specification at room temperature followed by hot temperature, unless specified otherwise in the device

specification.

2.20.3.2 Static latch-up (LU)

Two complementary static tests are required on six parts to assess the latch-up performance:

•

A supply overvoltage is applied to each power supply pin.

A current injection is applied to each input, output and configurable I/O pin.

These tests are compliant with the EIA/JESD 78 IC latch-up standard.

Table 35. Latch-up results

Symbol

LU CC

C

Parameter

Conditions

Class

T Static latch-up class

T_A= 125 °C

conforming to JESD 78

II level A

2.21 Fast external crystal oscillator (4 to 16 MHz) electrical

characteristics

The device provides an oscillator/resonator driver. Figure 14 describes a simple model of the internal

oscillator driver and provides an example of a connection for an oscillator or a resonator.

Table 36 provides the parameter description of 4 MHz to 16 MHz crystals used for the design simulations.

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

63

Package pinouts and signal descriptions

EXTAL

C1

C2

EXTAL

XTAL

DEVICE

V

DD

I

R

EXTAL

XTAL

DEVICE

XTAL

DEVICE

Notes:

1. XTAL/EXTAL must not be directly used to drive external circuits

2. A series resistor may be required, according to crystal oscillator supplier recommendations.

Figure 14. Crystal oscillator and resonator connection scheme

Table 36. Crystal description

Shunt

Crystal

equivalent

series

resistance

ESR Ω

Crystal

motional

capacitance

(C_m) fF

Crystal

motional

inductance

(L_m) mH

Load on

xtalin/xtalout

C1 = C2

capacitance

between

xtalout

Nominal

frequency

(MHz)

NDK crystal

reference

(pF)¹

and xtalin

C0²(pF)

4

NX8045GB

NX5032GA

300

150

120

2.68

2.46

2.93

3.11

3.90

591.0

160.7

86.6

21

17

15

10

2.93

3.01

2.91

2.93

3.00

8

10

12

16

56.5

25.3

1

2

The values specified for C1 and C2 are the same as used in simulations. It should be ensured that the testing

includes all the parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them.

The value of C0 specified here includes 2 pF additional capacitance for parasitics (to be seen with bond-pads,

package, etc.).

MPC5604B/C Microcontroller Data Sheet, Rev. 14

64

NXP Semiconductors

Package pinouts and signal descriptions

S_MTRANS bit (ME_GS register)

‘1’

‘0’

V

XTAL

1/f

FXOSC

V

FXOSC

90%

10%

V

FXOSCOP

t

valid internal clock

FXOSCSU

Figure 15. Fast external crystal oscillator (4 to 16 MHz) timing diagram

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

65

Package pinouts and signal descriptions

Table 37. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics

Value

Symbol

C

Parameter

Conditions¹

Unit

Min

Typ

Max

f_FXOSCSR — Fast external crystal

oscillator frequency

—

4.0

—

16.0

MHz

g_mFXOSCCC C Fast external crystal

V_DD= 3.3 V 10%,

2.2

2.0

2.7

2.5

—

8.2

7.4

9.7

9.2

mA/V

oscillator transconductance PAD3V5V = 1

OSCILLATOR_MARGIN = 0

CC P

CC C

V_DD= 5.0 V 10%,

PAD3V5V = 0

OSCILLATOR_MARGIN = 0

V

_DD= 3.3 V 10%,

PAD3V5V = 1

OSCILLATOR_MARGIN = 1

V

_DD= 5.0 V 10%,

PAD3V5V = 0

OSCILLATOR_MARGIN = 1

V_FXOSCCC T Oscillation amplitude at

EXTAL

f_OSC= 4 MHz,

OSCILLATOR_MARGIN = 0

1.3

—

V

f

_OSC= 16 MHz,

OSCILLATOR_MARGIN = 1

V_FXOSCOPCC C Oscillation operating point

—

0.95

2

—

3

V

,2

I_FXOSC

CC T Fast external crystal

oscillator consumption

mA

t_FXOSCSUCC T Fast external crystal

oscillator start-up time

f_OSC= 4 MHz,

OSCILLATOR_MARGIN = 0

—

6

ms

f_OSC= 16 MHz,

OSCILLATOR_MARGIN = 1

1.8

V_IH

V_IL

SR P Input high level CMOS

(Schmitt Trigger)

Oscillator bypass mode

0.65V_DD

−0.4

V_DD+0.4

0.35V_DD

V

SR P Input low level CMOS

(Schmitt Trigger)

1

2

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= −40 to 125 °C, unless otherwise specified

Stated values take into account only analog module consumption but not the digital contributor (clock tree and

enabled peripherals)

2.22 Slow external crystal oscillator (32 kHz) electrical characteristics

The device provides a low power oscillator/resonator driver.

MPC5604B/C Microcontroller Data Sheet, Rev. 14

66

NXP Semiconductors

Package pinouts and signal descriptions

OSC32K_EXTAL

C1

C2

OSC32K_XTAL

DEVICE

Note: OSC32K_XTAL/OSC32K_EXTAL must not be directly used to drive external circuits.

Figure 16. Crystal oscillator and resonator connection scheme

C0

Crystal

R_m

L_m

C_m

C1

C2

C1

C2

Figure 17. Equivalent circuit of a quartz crystal

1

Table 38. Crystal motional characteristics

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

L_m

Motional inductance

Motional capacitance

—

18

11.796

—

28

KH

fF

C_m

2

C1/C2 Load capacitance at OSC32K_XTAL and

OSC32K_EXTAL with respect to ground²

—

pF

AC coupled @ C0 = 2.85 pF⁴

AC coupled @ C0 = 4.9 pF⁴

AC coupled @ C0 = 7.0 pF⁴

AC coupled @ C0 = 9.0 pF⁴

—

65

50

35

30

kΩ

3

R_m

Motional resistance

1

Crystal used: Epson Toyocom MC306

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

67

Package pinouts and signal descriptions

2

This is the recommended range of load capacitance at OSC32K_XTAL and OSC32K_EXTAL with respect to

ground. It includes all the parasitics due to board traces, crystal and package.

3

Maximum ESR (R_m) of the crystal is 50 kΩ

C0 includes a parasitic capacitance of 2.0 pF between OSC32K_XTAL and OSC32K_EXTAL pins

4

OSCON bit (OSC_CTL register)

1

0

V

OSC32K_XTAL

1/f

SXOSC

V

SXOSC

90%

10%

T

valid internal clock

SXOSCSU

Figure 18. Slow external crystal oscillator (32 kHz) timing diagram

Table 39. Slow external crystal oscillator (32 kHz) electrical characteristics

Value

Symbol

C

Parameter

Conditions¹

Unit

Min

Typ

Max

f_SXOSCSR — Slow external crystal oscillator frequency

V_SXOSCCC T Oscillation amplitude

—

32

—

32.768

2.1

40

—

8

kHz

V

I_SXOSCBIASCC T Oscillation bias current

2.5

µA

s

I_SXOSCCC T Slow external crystal oscillator consumption

T_SXOSCSUCC T Slow external crystal oscillator start-up time

—

2²

1

2

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= −40 to 125 °C, unless otherwise specified. Values are specified for no

neighbor GPIO pin activity. If oscillator is enabled (OSC32K_XTAL and OSC32K_EXTAL pins), neighboring pins

should not toggle.

Start-up time has been measured with EPSON TOYOCOM MC306 crystal. Variation may be seen with other crystal.

2.23 FMPLL electrical characteristics

The device provides a frequency-modulated phase-locked loop (FMPLL) module to generate a fast system

clock from the main oscillator driver.

MPC5604B/C Microcontroller Data Sheet, Rev. 14

68

NXP Semiconductors

Package pinouts and signal descriptions

Table 40. FMPLL electrical characteristics

Value

Typ

Symbol

C

Parameter

Conditions¹

Unit

Min

Max

f_PLLINSR — FMPLL reference clock²

—

4

—

64

60

MHz

%

Δ_PLLINSR — FMPLL reference clock duty

40

cycle²

f_PLLOUTCC D FMPLL output clock frequency

—

16

—

64

MHz

3

f_VCO

CC P VCO frequency without

frequency modulation

256

512 MHz

C VCO frequency with frequency

modulation

—

245

—

533

f_CPUSR — System clock frequency

f_FREECC P Free-running frequency

t_LOCKCC P FMPLL lock time

—

20

—

–4

—

40

—

64

MHz

—

150 MHz

Stable oscillator (f_PLLIN= 16 MHz)

f_sysmaximum

100

4

µs

%

Δt_STJITCC — FMPLL short term jitter⁴

Δt_LTJITCC — FMPLL long term jitter

f_PLLIN= 16 MHz (resonator),

f_PLLCLK@ 64 MHz, 4000 cycles

10

ns

I_PLL

CC C FMPLL consumption

T_A= 25 °C

—

4

mA

1

2

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= −40 to 125 °C, unless otherwise specified.

PLLIN clock retrieved directly from FXOSC clock. Input characteristics are granted when oscillator is used in

functional mode. When bypass mode is used, oscillator input clock should verify f_PLLINand Δ_PLLIN

Frequency modulation is considered 4%

.

3

4

Short term jitter is measured on the clock rising edge at cycle n and n+4.

2.24 Fast internal RC oscillator (16 MHz) electrical characteristics

The device provides a 16 MHz fast internal RC oscillator. This is used as the default clock at the power-up

of the device.

Table 41. Fast internal RC oscillator (16 MHz) electrical characteristics

Value

Symbol

f_FIRC

2,

C

Parameter

Conditions¹

Unit

Min

Typ

Max

CC P Fast internal RC oscillator high

T_A= 25 °C, trimmed

—

12

—

16

—

20

MHz

frequency

SR —

I_FIRCRUNCC T Fast internal RC oscillator high

frequency current in running mode

T_A= 25 °C, trimmed

—

200

µA

I_FIRCPWDCC D Fast internal RC oscillator high

frequency current in power down

mode

T_A= 125 °C

—

10

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

69

Package pinouts and signal descriptions

Table 41. Fast internal RC oscillator (16 MHz) electrical characteristics (continued)

Value

Typ

Symbol

C

Parameter

Conditions¹

Unit

Min

Max

I_FIRCSTOPCC T Fast internal RC oscillator high

frequency and system clock current

in stop mode

T_A= 25 °C sysclk = off

—

500

600

700

900

1250

1.1

—

2.0

µA

sysclk = 2 MHz

sysclk = 4 MHz

sysclk = 8 MHz

sysclk = 16 MHz

t_FIRCSUCC C Fast internal RC oscillator start-up V_DD= 5.0 V 10%

time

µs

%

Δ_FIRCPRECC T Fast internal RC oscillator precision T_A= 25 °C

−1

—

−5

—

1.6

—

+1

after software trimming of f_FIRC

Δ_FIRCTRIMCC T Fast internal RC oscillator trimming T_A= 25 °C

step

Δ_FIRCVARCC P Fast internal RC oscillator variation

in over temperature and supply with

respect to f_FIRCat T_A= 25 °C in

—

+5

high-frequency configuration

1

2

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= −40 to 125 °C, unless otherwise specified.

This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is

ON.

2.25 Slow internal RC oscillator (128 kHz) electrical characteristics

The device provides a 128 kHz slow internal RC oscillator. This can be used as the reference clock for the

RTC module.

Table 42. Slow internal RC oscillator (128 kHz) electrical characteristics

Value

Symbol

C

Parameter

Conditions¹

Unit

Min Typ Max

f_SIRC

CC P Slow internal RC oscillator low

T_A= 25 °C, trimmed

—

100

—

128

—

150

5

kHz

frequency

SR —

2,

I_SIRC

CC C Slow internal RC oscillator low

frequency current

T_A= 25 °C, trimmed

—

µA

µs

%

t_SIRCSU

CC P Slow internal RC oscillator start-up T_A= 25 °C, V_DD= 5.0 V 10%

time

—

−2

—

8

12

+2

—

Δ_SIRCPRECC C Slow internal RC oscillator precision T_A= 25 °C

—

after software trimming of f_SIRC

Δ_SIRCTRIMCC C Slow internal RC oscillator trimming

—

2.7

step

MPC5604B/C Microcontroller Data Sheet, Rev. 14

70

NXP Semiconductors

Package pinouts and signal descriptions

Table 42. Slow internal RC oscillator (128 kHz) electrical characteristics (continued)

Value

Symbol

C

Parameter

Conditions¹

Unit

Min Typ Max

Δ_SIRCVARCC C Slow internal RC oscillator variation High frequency configuration

in temperature and supply with

−10

—

+10

%

respect to f_SIRCat T_A= 55 °C in high

frequency configuration

1

2

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= −40 to 125 °C, unless otherwise specified.

This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is

ON.

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

71

Package pinouts and signal descriptions

2.26 ADC electrical characteristics

2.26.1 Introduction

The device provides a 10-bit Successive Approximation Register (SAR) analog-to-digital converter.

Offset error (E )

Gain error (E )

G

O

1023

1022

1021

1020

1019

1 LSB ideal = V

/ 1024

DD_ADC

1018

(2)

code out

7

(1)

6

5

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(5)

4

3

(3) Differential non-linearity error (DNL)

(4) Integral non-linearity error (INL)

(5) Center of a step of the actual transfer curve

(4)

(3)

2

1

1 LSB (ideal)

0

1

2

3

4

5

6

7

1017 1018 1019 1020 1021 1022 1023

(LSB

V

)

ideal

in(A)

Offset error (E )

O

Figure 19. ADC characteristic and error definitions

2.26.2 Input impedance and ADC accuracy

In the following analysis, the input circuit corresponding to the precise channels is considered.

To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC

impedance. Placing a capacitor with good high frequency characteristics at the input pin of the device can

MPC5604B/C Microcontroller Data Sheet, Rev. 14

72

NXP Semiconductors

Package pinouts and signal descriptions

be effective: the capacitor should be as large as possible, ideally infinite. This capacitor contributes to

attenuating the noise present on the input pin; furthermore, it sources charge during the sampling phase,

when the analog signal source is a high-impedance source.

A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple

RC filter). The RC filtering may be limited according to the value of source impedance of the transducer

or circuit supplying the analog signal to be measured. The filter at the input pins must be designed taking

into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input

impedance of the ADC itself.

In fact a current sink contributor is represented by the charge sharing effects with the sampling

capacitance: being C and C substantially two switched capacitances, with a frequency equal to the

S

p2

conversion rate of the ADC, it can be seen as a resistive path to ground. For instance, assuming a

conversion rate of 1 MHz, with C +C equal to 3 pF, a resistance of 330 kΩ is obtained (R = 1 /

S

p2

EQ

(f × (C +C )), where f represents the conversion rate at the considered channel). To minimize the error

c

S

p2

c

induced by the voltage partitioning between this resistance (sampled voltage on C +C ) and the sum of

S

p2

R + R , the external circuit must be designed to respect the Equation 4:

S

F

Eqn. 4

R + R

S

F

1

2

V • -------------------- < -- LSB

A

R

EQ

Equation 4 generates a constraint for external network design, in particular on a resistive path.

EXTERNAL CIRCUIT

INTERNAL CIRCUIT SCHEME

V

DD

Channel

Sampling

Selection

Source

Filter

Current Limiter

R

AD

S

F

L

SW1

V

C

S

A

F

P1

P2

R : Source impedance

S

R : Filter resistance

F

C : Filter capacitance

F

R : Current limiter resistance

L

R

: Channel selection switch impedance

: Sampling switch impedance

SW1

AD

C : Pin capacitance (two contributions, C and C )

P2

P

P1

C : Sampling capacitance

S

Figure 20. Input equivalent circuit (precise channels)

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

73

Package pinouts and signal descriptions

EXTERNAL CIRCUIT

INTERNAL CIRCUIT SCHEME

V

DD

Channel

Selection

Extended

Switch

Sampling

Source

R

Filter

Current Limiter

R

L

R

AD

SW2

S

F

SW1

C

S

C

V

C

P2

A

F

P1

P3

R : Source impedance

S

R : Filter resistance

F

C : Filter capacitance

F

R : Current limiter resistance

L

R

: Channel selection switch impedance (two contributions, R

: Sampling switch impedance

and R

)

SW1

SW2

AD

C : Pin capacitance (two contributions, C , C and C )

P3

P

P1

P2

C : Sampling capacitance

S

Figure 21. Input equivalent circuit (extended channels)

A second aspect involving the capacitance network shall be considered. Assuming the three capacitances

C , C and C are initially charged at the source voltage V (refer to the equivalent circuit in Figure 20):

F

P1

P2

A

A charge sharing phenomenon is installed when the sampling phase is started (A/D switch close).

Voltage transient on C_S

V

CS

V

A

ΔV < 0.5 LSB

V

A2

1

2

τ₁< (R_SW+ R_AD) C_S<< t_s

V

A1

τ₂= R_L(C_S+ C_P1+ C_P2)

t

s

Figure 22. Transient behavior during sampling phase

In particular two different transient periods can be distinguished:

MPC5604B/C Microcontroller Data Sheet, Rev. 14

74

NXP Semiconductors

Package pinouts and signal descriptions

1. A first and quick charge transfer from the internal capacitance C and C to the sampling

P1

P2

capacitance C occurs (C is supposed initially completely discharged): considering a worst case

S

(since the time constant in reality would be faster) in which C is reported in parallel to C (call

P2

P1

C = C + C ), the two capacitances C and C are in series, and the time constant is

P

P1

P2

P

S

Eqn. 5

C • C

P

S

τ

= (R

+ R

) • --------------------

AD

1

SW

C + C

P

S

Equation 5 can again be simplified considering only C as an additional worst condition. In reality,

S

the transient is faster, but the A/D converter circuitry has been designed to be robust also in the

very worst case: the sampling time t is always much longer than the internal time constant:

s

Eqn. 6

τ < (R

+ R

) • C « t

AD S s

1

SW

The charge of C and C is redistributed also on C , determining a new value of the voltage V

P1

P2

S

A1

on the capacitance according to Equation 7:

Eqn. 7

V

• (C + C + C ) = V • (C + C

P1 P2 P1

)

P2

A1

S

A

2. A second charge transfer involves also C (that is typically bigger than the on-chip capacitance)

F

through the resistance R : again considering the worst case in which C and C were in parallel

L

P2

S

to C (since the time constant in reality would be faster), the time constant is:

P1

Eqn. 8

τ < R • (C + C + C )

P1 P2

2

L

S

In this case, the time constant depends on the external circuit: in particular imposing that the

transient is completed well before the end of sampling time t , a constraints on R sizing is

s

L

obtained:

Eqn. 9

8.5 • τ = 8.5 • R • (C + C + C ) < t_s

2

L

S

P1

P2

Of course, R shall be sized also according to the current limitation constraints, in combination

L

with R (source impedance) and R (filter resistance). Being C definitively bigger than C , C

S

F

P1 P2

and C , then the final voltage V (at the end of the charge transfer transient) will be much higher

S

A2

than V . Equation 10 must be respected (charge balance assuming now C already charged at

A1

S

V ):

A1

Eqn. 10

V

• (C + C + C + C ) = V • C + V • (C + C + C )

P1 P2 A1 P1 P2

A2

S

F

A

F

S

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

75

Package pinouts and signal descriptions

The two transients above are not influenced by the voltage source that, due to the presence of the R C

F F

filter, is not able to provide the extra charge to compensate the voltage drop on C with respect to the ideal

S

source V ; the time constant R C of the filter is very high with respect to the sampling time (t ). The filter

A

F F

s

is typically designed to act as anti-aliasing.

Analog source bandwidth (V_A)

Noise

t_c< 2 R_FC_F(conversion rate vs. filter pole)

f_F= f₀(anti-aliasing filtering condition)

2 f₀< f_C(Nyquist)

f₀

f

Anti-aliasing filter (f_F= RC filter pole)

Sampled signal spectrum (f_C= conversion rate)

f_F

f₀

f_C

f

Figure 23. Spectral representation of input signal

Calling f the bandwidth of the source signal (and as a consequence the cut-off frequency of the

0

anti-aliasing filter, f ), according to the Nyquist theorem the conversion rate f must be at least 2f ; it

F

C

0

means that the constant time of the filter is greater than or at least equal to twice the conversion period (t ).

c

Again the conversion period t is longer than the sampling time t , which is just a portion of it, even when

c

s

fixed channel continuous conversion mode is selected (fastest conversion rate at a specific channel): in

conclusion it is evident that the time constant of the filter R C is definitively much higher than the

F F

sampling time t , so the charge level on C cannot be modified by the analog signal source during the time

s

S

in which the sampling switch is closed.

The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy

error due to the voltage drop on C ; from the two charge balance equations above, it is simple to derive

S

Equation 11 between the ideal and real sampled voltage on C :

S

Eqn. 11

V

C

+ C + C

P2

----------- = -------------------------------------------------------

A2

P1

F

V

C

+ C + C + C

A

P1

P2 S

F

From this formula, in the worst case (when V is maximum, that is for instance 5 V), assuming to accept

A

a maximum error of half a count, a constraint is evident on C value:

F

Eqn. 12

C

> 2048 • C

F

S

MPC5604B/C Microcontroller Data Sheet, Rev. 14

76

NXP Semiconductors

Package pinouts and signal descriptions

2.26.3 ADC electrical characteristics

Table 43. ADC input leakage current

Value

Unit

Symbol C

Parameter

Conditions

Min

Typ

Max

I_LKGCC D Input leakage current T_A= −40 °C No current injection on adjacent pin

—

1

70

nA

D

P

T_A= 25 °C

T_A= 85 °C

T_A= 105 °C

T_A= 125 °C

3

100

200

400

8

45

Table 44. ADC conversion characteristics

Value

Symbol

C

Parameter

Conditions¹

Unit

Min

Typ

Max

0.1

V_{SS_ADC}SR — Voltage on

VSS_HV_ADC (ADC

—

−0.1

—

V

reference) pin with

respect to ground

2

(V_SS

)

V_{DD_ADC}SR — Voltage on

VDD_HV_ADC pin

—

V_DD−0.1

—

V_DD+0.1

V

(ADC reference) with

respect to ground

(V_SS

)

V_AINxSR — Analog input voltage³

—

V_{SS_ADC}−0.1

—

V_{DD_ADC}+0.1

f_ADCSR — ADC analog frequency

6

32 + 4% MHz

Δ

_{ADC_SYS}SR — ADC digital clock duty ADCLKSEL = 1⁴

45

55

50

4

%

µA

mA

cycle (ipg_clk)

I_ADCPWDSR — ADC0 consumption in

power down mode

—

I_ADCRUNSR — ADC0 consumption in

running mode

t_{ADC_PU}SR — ADC power up delay

—

0.5

—

1.5

µs

t_s

CC

T

Sampling time⁵

f_ADC= 32 MHz, INPSAMP = 17

f_ADC= 6 MHz, INPSAMP = 255

f_ADC= 32 MHz, INPCMP = 2

—

42

t_c

CC

P

Conversion time⁶

0.625

—

µs

C_S

CC D ADC input sampling

capacitance

3

1

pF

C_P1

C_P2

CC D ADC input pin

capacitance 1

—

pF

CC D ADC input pin

capacitance 2

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

77

Package pinouts and signal descriptions

Table 44. ADC conversion characteristics (continued)

Value

Symbol

C

Parameter

Conditions¹

Unit

Min

Typ

Max

C_P3

CC D ADC input pin

capacitance 3

—

1

pF

kΩ

mA

R_SW1CC D Internal resistance of

analog source

—

−5

—

3

2

5

R_SW2CC D Internal resistance of

analog source

R_ADCC D Internal resistance of

analog source

I_INJ

SR — Input current Injection Current

V_DD=

injection on one 3.3 V 10%

ADC input,

V_DD

=

different from

the converted

one

5.0 V 10%

| INL | CC

| DNL | CC

T

Absolute value for

integral non-linearity

No overload

—

0.5

1.5

1.0

LSB

Absolute differential

non-linearity

No overload

| E_O

| E_G

|

CC

T

P

T

Absolute offset error

—

−2

−3

0.5

0.6

—

2

LSB

Absolute gain error

—

TUEp CC

Total unadjusted error⁷Without current injection

for precise channels,

With current injection

input only pins

3

TUEx CC

T

Total unadjusted error⁷Without current injection

−3

−4

1

3

4

LSB

for extended channel

With current injection

1

2

3

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= −40 to 125 °C, unless otherwise specified.

Analog and digital V_SSmust be common (to be tied together externally).

V_AINxmay exceed V_{SS_ADC}and V_{DD_ADC}limits, remaining on absolute maximum ratings, but the results of the

conversion will be clamped respectively to 0x000 or 0x3FF.

4

5

Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured

by internal divider by 2.

During the sampling time the input capacitance C_Scan be charged/discharged by the external source. The internal

resistance of the analog source must allow the capacitance to reach its final voltage level within t_s. After the end of

the sampling time t_s, changes of the analog input voltage have no effect on the conversion result. Values for the

sample clock t_sdepend on programming.

6

7

This parameter does not include the sampling time t_s, but only the time for determining the digital result and the time

to load the result’s register with the conversion result.

Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a

combination of Offset, Gain and Integral Linearity errors.

MPC5604B/C Microcontroller Data Sheet, Rev. 14

78

NXP Semiconductors

Package pinouts and signal descriptions

2.27 On-chip peripherals

2.27.1 Current consumption

1

Table 45. On-chip peripherals current consumption

Symbol

C

Parameter

Conditions

Typical value²Unit

I_{DD_BV(CAN)}

CC T CAN (FlexCAN) supply

current on VDD_BV

Bitrate:

500 Kbyte/s consumption:

Total (static + dynamic)

8 * f_periph+ 85

µA

• FlexCAN in loop-back

mode

• XTAL @ 8 MHz used as

CAN engine clock source

• Message sending period is

580 µs

Bitrate:

125 Kbyte/s

8 * f_periph+ 27

I_{DD_BV(eMIOS)}CC T eMIOS supply current on

VDD_BV

Static consumption:

• eMIOS channel OFF

• Global prescaler enabled

29 * f_periph

µA

Dynamic consumption:

3

• It does not change varying the frequency

(0.003 mA)

I_{DD_BV(SCI)}

CC T SCI (LINFlex) supply

current on VDD_BV

Total (static + dynamic) consumption:

• LIN mode

• Baudrate: 20 Kbyte/s

5 * f_periph+ 31

µA

I_{DD_BV(SPI)}

CC T SPI (DSPI) supply current Ballast static consumption (only clocked)

1

on VDD_BV

Ballast dynamic consumption (continuous

16 * f_periph

communication):

• Baudrate: 2 Mbit/s

• Transmission every 8 µs

• Frame: 16 bits

I_{DD_BV(ADC)}

CC T ADC supply current on

VDD_BV

V_DD= 5.5 V Ballast static consumption

(no conversion)

41 * f_periph

5 * f_periph

2 * f_periph

µA

Ballast dynamic consumption

(continuous conversion)³

I_{DD_HV_ADC(ADC)}CC T ADC supply current on

VDD_HV_ADC

V_DD= 5.5 V Analog static consumption

(no conversion)

Analog dynamic consumption 75 * f_periph+ 32

(continuous conversion)

I_{DD_HV(FLASH)}CC T Code Flash + Data Flash

supply current on VDD_HV

V_DD= 5.5 V

—

8.21

mA

µA

I_{DD_HV(PLL)}

CC T PLL supply current on

VDD_HV

—

30 * f_periph

1

2

3

Operating conditions: T_A= 25 °C, f_periph= 8 MHz to 64 MHz

f_periphis an absolute value.

During the conversion, the total current consumption is given from the sum of the static and dynamic consumption, i.e.,

(41 + 5) * f_periph

.

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

79

Package pinouts and signal descriptions

2.27.2 DSPI characteristics

1

Table 46. DSPI characteristics

DSPI0/DSPI1

DSPI2

No.

Symbol

C

Parameter

Unit

Min

Typ

Max

Min

Typ

Max

1

t_SCK

SR D SCK cycle time

Master mode

(MTFE = 0)

125

—

333

—

ns

D

Slave mode

(MTFE = 0)

125

83

—

333

125

—

Master mode

(MTFE = 1)

Slave mode

(MTFE = 1)

83

—

f_DSPI

SR D DSPI digital controller frequency

—

f_CPU

130²

—

f_CPU

15³

MHz

ns

Δt_CSCCC D Internal delay between pad Master mode

associated to SCK and pad

associated to CSn in

^{master mode for CSn1}→0

Δt_ASCCC D Internal delay between pad Master mode

associated to SCK and pad

—

130³

—

130³

ns

associated to CSn in

^{master mode for CSn1}→1

4

2

3

4

t_CSCextSR D CS to SCK delay

Slave mode

Master mode

Slave mode

32

—

32

—

ns

5

t_ASCextSR D After SCK delay

1/f_DSPI+ 5

—

t_SCK/2

—

1/f_DSPI+ 5

—

t_SDC

CC D SCK duty cycle

SR D

—

t_SCK/2

—

7

—

t_SCK/2

—

7

t_SCK/2

—

5

6

7

8

9

t_A

SR D Slave access time

—

1/f_DSPI+ 70

—

1/f_DSPI+ 130

ns

t_DI

SR D Slave SOUT disable time Slave mode

—

32

52

—

t_PCSCSR D PCSx to PCSS time

t_PASCSR D PCSS to PCSx time

0

—

0

—

0

—

0

—

t_SUI

SR D Data setup time for inputs Master mode

Slave mode

43

5

—

145

5

—

10

11

12

t_HI

SR D Data hold time for inputs

Master mode

Slave mode

0

—

0

—

ns

2⁶

—

0

—

2⁶

—

0

—

7

t_SUO

CC D Data valid after SCK edge Master mode

Slave mode

—

50

160

—

7

t_HO

CC D Data hold time for outputs Master mode

Slave mode

—

8

—

13

—

1

2

Operating conditions: C_L= 10 to 50 pF, Slew_IN= 3.5 to 15 ns.

Maximum value is reached when CSn pad is configured as SLOW pad while SCK pad is configured as MEDIUM. A positive value means that SCK

starts before CSn is asserted. DSPI2 has only SLOW SCK available.

MPC5604B/C Microcontroller Data Sheet, Rev. 14

80

NXP Semiconductors

Package pinouts and signal descriptions

3

4

5

Maximum value is reached when CSn pad is configured as MEDIUM pad while SCK pad is configured as SLOW. A positive value means that CSn is

deasserted before SCK. DSPI0 and DSPI1 have only MEDIUM SCK available.

The t_CSCdelay value is configurable through a register. When configuring t_CSC(using PCSSCK and CSSCK fields in DSPI_CTARx registers), delay

between internal CS and internal SCK must be higher than Δt_CSCto ensure positive t_CSCext

The t_ASCdelay value is configurable through a register. When configuring t_ASC(using PASC and ASC fields in DSPI_CTARx registers), delay between

internal CS and internal SCK must be higher than Δt_ASCto ensure positive t_ASCext

.

6

7

This delay value corresponds to SMPL_PT = 00b which is bit field 9 and 8 of the DSPI_MCR.

SCK and SOUT configured as MEDIUM pad

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

81

Package pinouts and signal descriptions

2

3

PCSx

1

4

SCK Output

(CPOL = 0)

4

SCK Output

(CPOL = 1)

10

9

Last Data

SIN

First Data

Data

12

11

Last Data

SOUT

Note: Numbers shown reference Table 46.

Figure 24. DSPI classic SPI timing – master, CPHA = 0

PCSx

SCK Output

(CPOL = 0)

10

SCK Output

(CPOL = 1)

9

Data

First Data

Last Data

SIN

12

11

SOUT

Last Data

First Data

Note: Numbers shown reference Table 46.

Figure 25. DSPI classic SPI timing – master, CPHA = 1

MPC5604B/C Microcontroller Data Sheet, Rev. 14

82

NXP Semiconductors

Package pinouts and signal descriptions

3

2

SS

1

4

SCK Input

(CPOL = 0)

4

SCK Input

(CPOL = 1)

5

11

12

Data

6

First Data

Last Data

SOUT

SIN

9

10

Data

Last Data

First Data

Note: Numbers shown reference Table 46.

Figure 26. DSPI classic SPI timing – slave, CPHA = 0

SS

SCK Input

(CPOL = 0)

SCK Input

(CPOL = 1)

11

5

6

12

Last Data

Data

SOUT

SIN

First Data

10

9

Last Data

First Data

Note: Numbers shown reference Table 46.

Figure 27. DSPI classic SPI timing – slave, CPHA = 1

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

83

Package pinouts and signal descriptions

3

PCSx

4

1

2

SCK Output

(CPOL = 0)

4

SCK Output

(CPOL = 1)

9

10

SIN

First Data

Last Data

Data

12

11

SOUT

First Data

Data

Note: Numbers shown reference Table 46.

Figure 28. DSPI modified transfer format timing – master, CPHA = 0

PCSx

SCK Output

(CPOL = 0)

SCK Output

(CPOL = 1)

10

9

SIN

Last Data

First Data

Data

12

Data

11

First Data

Last Data

SOUT

Note: Numbers shown reference Table 46.

Figure 29. DSPI modified transfer format timing – master, CPHA = 1

MPC5604B/C Microcontroller Data Sheet, Rev. 14

84

NXP Semiconductors

Package pinouts and signal descriptions

3

2

SS

1

SCK Input

(CPOL = 0)

4

SCK Input

(CPOL = 1)

12

11

6

5

First Data

9

Data

Last Data

10

SOUT

SIN

Last Data

First Data

Note: Numbers shown reference Table 46.

Figure 30. DSPI modified transfer format timing – slave, CPHA = 0

SS

SCK Input

(CPOL = 0)

SCK Input

(CPOL = 1)

11

5

6

12

Last Data

First Data

10

Data

SOUT

SIN

9

First Data

Last Data

Note: Numbers shown reference Table 46.

Figure 31. DSPI modified transfer format timing – slave, CPHA = 1

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

85

Package pinouts and signal descriptions

8

7

PCSS

PCSx

Note: Numbers shown reference Table 46.

Figure 32. DSPI PCS strobe (PCSS) timing

2.27.3 Nexus characteristics

Table 47. Nexus characteristics

Value

Typ

No.

Symbol

C

Parameter

Unit

Min

Max

1

2

t_TCYC

t_MCYC

t_MDOV

t_MSEOVCC D MCKO low to MSEO_b data valid

CC D TCK cycle time

64

32

—

15

5

—

8

ns

CC D MCKO cycle time

3

CC D MCKO low to MDO data valid

4

8

5

t_EVTOV

t_NTDIS

CC D MCKO low to EVTO data valid

CC D TDI data setup time

8

10

—

t_NTMSSCC D TMS data setup time

t_NTDIHCC D TDI data hold time

t_NTMSHCC D TMS data hold time

11

5

12

13

t_TDOV

t_TDOI

CC D TCK low to TDO data valid

CC D TCK low to TDO data invalid

35

6

MPC5604B/C Microcontroller Data Sheet, Rev. 14

86

NXP Semiconductors

Package pinouts and signal descriptions

TCK

10

11

TMS, TDI

12

TDO

Note: Numbers shown reference Table 47.

Figure 33. Nexus TDI, TMS, TDO timing

2.27.4 JTAG characteristics

Table 48. JTAG characteristics

Value

Typ

No.

Symbol

C

Parameter

Unit

Min

Max

1

2

3

4

5

6

7

t_JCYC

t_TDIS

CC D TCK cycle time

CC D TDI setup time

CC D TDI hold time

64

15

5

—

33

—

ns

t_TDIH

t_TMSS

t_TMSH

t_TDOV

t_TDOI

CC D TMS setup time

CC D TMS hold time

CC D TCK low to TDO valid

CC D TCK low to TDO invalid

15

5

—

6

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

87

Package characteristics

TCK

2/4

3/5

INPUT DATA VALID

DATA INPUTS

6

DATA OUTPUTS

OUTPUT DATA VALID

7

DATA OUTPUTS

Note: Numbers shown reference Table 48.

Figure 34. Timing diagram – JTAG boundary scan

3

Package characteristics

3.1

Package mechanical data

MPC5604B/C Microcontroller Data Sheet, Rev. 14

88

NXP Semiconductors

Package characteristics

3.1.1

64 LQFP

Figure 35. 64 LQFP package mechanical drawing (1 of 3)

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

89

Package characteristics

Figure 36. 64 LQFP package mechanical drawing (2 of 3)

MPC5604B/C Microcontroller Data Sheet, Rev. 14

90

NXP Semiconductors

Package characteristics

Figure 37. 64 LQFP package mechanical drawing (3 of 3)

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

91

Package characteristics

3.1.2

100 LQFP

Figure 38. 100 LQFP package mechanical drawing (1 of 3)

MPC5604B/C Microcontroller Data Sheet, Rev. 14

92

NXP Semiconductors

Package characteristics

Figure 39. 100 LQFP package mechanical drawing (2 of 3)

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

93

Package characteristics

Figure 40. 100 LQFP package mechanical drawing (3 of 3)

MPC5604B/C Microcontroller Data Sheet, Rev. 14

94

NXP Semiconductors

Package characteristics

3.1.3

144 LQFP

Figure 41. 144 LQFP package mechanical drawing (1 of 2)

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

95

Package characteristics

Figure 42. 144 LQFP package mechanical drawing (2 of 2)

MPC5604B/C Microcontroller Data Sheet, Rev. 14

96

NXP Semiconductors

Package characteristics

3.1.4

208 MAPBGA

Figure 43. 208 MAPBGA package mechanical drawing (1 of 2)

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

97

Package characteristics

Figure 44. 208 MAPBGA package mechanical drawing (2 of 2)

MPC5604B/C Microcontroller Data Sheet, Rev. 14

98

NXP Semiconductors

Ordering information

4

Ordering information

Figure 45. Commercial product code structure

Example code:

M

PC

56

0

4

B

F1

M

LL

4

R

Qualification Status

PowerPC Core

Automotive Platform

Core Version

Flash Size (core dependent)

Product

Fab and Mask Indicator

Temperature spec.

Package Code

Frequency

R = Tape & Reel (blank if Tray)

Qualification Status

Flash Size (z0 core)

2 = 256 KB

3 = 384 KB

Temperature spec.

C = −40 to 85 °C

V = −40 to 105 °C

M = −40 to 125 °C

M = MC status

S = Auto qualified

P = PC status

4 = 512 KB

Automotive Platform

56 = PPC in 90nm

Product

B = Body

Package Code

LH = 64 LQFP

C = Gateway

LL = 100 LQFP

LQ = 144 LQFP

MG = 208 MAPBGA

Core Version

0 = e200z0

1

Fab and Mask Indicator

F = ATMC Fab

K = TSMC Fab

1 = Maskset Revision

Frequency

4 = Up to 48 MHz

6 = Up to 64 MHz

Note: Not all options are available on all devices.

1

208 MAPBGA available only as development package for Nexus2+

5

Document revision history

Table 49 summarizes revisions to this document.

Table 49. Revision history

Revision

Date

Description of Changes

1

04-Apr-2008 Initial release.

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

99

Document revision history

Table 49. Revision history (continued)

Description of Changes

Revision

Date

2

06-Mar-2009 Made minor editing and formatting changes to improve readability

Harmonized oscillator naming throughout document

Features:

—Replaced 32 KB with 48 KB as max SRAM size

—Updated description of INTC

—Changed max number of GPIO pins from 121 to 123

Updated Section 1.2, Description

Updated Table 3

Added Section 2, Block diagram

Section 3, Package pinouts and signal descriptions: Removed signal descriptions (these

are found in the device reference manual)

Updated Figure 5:

—Replaced VPP with VSS_HV on pin 18

—Added MA[1] as AF3 for PC[10] (pin 28)

—Added MA[0] as AF2 for PC[3] (pin 116)

—Changed description for pin 120 to PH[10] / GPIO[122] / TMS

—Changed description for pin 127 to PH[9] / GPIO[121] / TCK

—Replaced NMI[0] with NMI on pin 11

Updated Figure 4:

—Replaced VPP with VSS_HV on pin 14

—Added MA[1] as AF3 for PC[10] (pin 22)

—Added MA[0] as AF2 for PC[3] (pin 77)

—Changed description for pin 81 to PH[10] / GPIO[122] / TMS

—Changed description for pin 88 to PH[9] / GPIO[121] / TCK

—Removed E1UC[19] from pin 76

—Replaced [11] with WKUP[11] for PB[3] (pin 1)

—Replaced NMI[0] with NMI on pin 7

Updated Figure 6:

—Changed description for ball B8 from TCK to PH[9]

—Changed description for ball B9 from TMS to PH[10]

—Updated descriptions for balls R9 and T9

Added 2.10, Parameter classification and tagged parameters in tables where appropriate

Added 2.11, NVUSRO register

Updated Table 11

2.13, Recommended operating conditions: Added note on RAM data retention to end of

section

Updated Table 12 and Table 13

Added 2.14.1, Package thermal characteristics

Updated 2.14.2, Power considerations

Updated Figure 7

MPC5604B/C Microcontroller Data Sheet, Rev. 14

100

NXP Semiconductors

Document revision history

Table 49. Revision history (continued)

Description of Changes

Revision

Date

2 (cont.) 06-Mar-2009 Updated Table 15, Table 16, Table 17, Table 18 and Table 19

Added 2.15.4, Output pin transition times

Updated Table 22

Updated Figure 8

Updated Table 24

2.17.1, Voltage regulator electrical characteristics: Amended description of LV_PLL

Figure 10: Exchanged position of symbols C_DEC1and C_DEC2

Updated Table 25

Added Figure 13

Updated Table 26 and Table 27

Updated 2.19, Flash memory electrical characteristics

Added 2.20, Electromagnetic compatibility (EMC) characteristics

Updated 2.21, Fast external crystal oscillator (4 to 16 MHz) electrical characteristics

Updated 2.22, Slow external crystal oscillator (32 kHz) electrical characteristics

Updated Table 40, Table 41 and Table 42

Added 2.27, On-chip peripherals

Added Table 43

Updated Table 44

Updated Table 47

Added Appendix A, Abbreviations

4

06-Aug-2009 Updated Figure 6

Table 11

• V_{DD_ADC}: changed min value for “relative to V_DD” condition

• V_IN: changed min value for “relative to V_DD” condition

• I_CORELV: added new row

Table 13

• T_{A C-Grade Part,}T_{J C-Grade Part,}T_{A V-Grade Part,}T_{J V-Grade Part,}T_{A M-Grade Part,}T_{J M-Grade Part}

:

added new rows

• Changed capacitance value in footnote

Table 20

• MEDIUM configuration: added condition for PAD3V5V = 0

Updated Figure 10

Table 25

• C_DEC1: changed min value

• I_MREG:changed max value

• I_{DD_BV}: added max value footnote

Table 26

• V_LVDHV3H: changed max value

• V_LVDHV3L: added max value

• V_LVDHV5H: changed max value

• V_LVDHV5L: added max value

Updated Table 27

Table 29

• Retention: deleted min value footnote for “Blocks with 100,000 P/E cycles“

Table 37

• I_FXOSC: added typ value

Table 39

• V_SXOSC: changed typ value

• T_SXOSCSU: added max value footnote

Table 40

• Δt_LTJIT: added max value

Updated Figure 38

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

101

Document revision history

Table 49. Revision history (continued)

Description of Changes

Revision

Date

5

02-Nov-2009 In the “MPC5604B/C series block summary” table, added a new row.

In the “Absolute maximum ratings” table, changed max value of V_{DD_BV}, V_{DD_ADC}, and

V_IN.

In the “Recommended operating conditions (3.3 V)” table, deleted min value of TV_DD

.

In the “Reset electrical characteristics” table, changed footnotes 3 and 5.

In the “Voltage regulator electrical characteristics” table:

• C_REGn: changed max value.

• C_DEC1: split into 2 rows.

• Updated voltage values in footnote 4

In the “Low voltage monitor electrical characteristics” table:

• Updated column Conditions.

• V_LVDLVCORL, V_LVDLVBKPL: changed min/max value.

In the “Program and erase specifications” table, added initial max value of T_dwprogram

In the “Flash module life” table, changed min value for blocks with 100K P/E cycles

In the “Flash power supply DC electrical characteristics” table:

• IFREAD, IFMOD: added typ value.

.

• Added footnote 1.

Added “NVUSRO[WATCHDOG_EN] field description” section.

Section 4.18: “ADC electrical characteristics” has been moved up in hierarchy (it was

Section 4.18.5).

In the “ADC conversion characteristics” table, changed initial max value of R_AD

.

In the “On-chip peripherals current consumption” table:

• Removed min/max from the heading.

• Changed unit of measurement and consequently rounded the values.

MPC5604B/C Microcontroller Data Sheet, Rev. 14

102

NXP Semiconductors

Document revision history

Table 49. Revision history (continued)

Description of Changes

Revision

Date

6

15-Mar-2010 In the “Introduction” section, relocated a note.

In the “MPC5604B/C device comparison” table, added footnote regarding SCI and CAN.

In the “Absolute maximum ratings” table, removed the min value of V_INrelative to V_DD

.

In the “Recommended operating conditions (3.3 V)” table:

• T_{A C-Grade Part,}T_{J C-Grade Part,}T_{A V-Grade Part,}T_{J V-Grade Part,}T_{A M-Grade Part,}T_{J M-Grade Part}

added new rows.

:

• TV_DD: made single row.

In the “LQFP thermal characteristics” table, added more rows.

Removed “208 MAPBGA thermal characteristics” table.

In the “I/O consumption” table:

• Removed I_DYNSEGrow.

• Added “I/O weight” table.

In the “Voltage regulator electrical characteristics” table:

• Updated the values.

• Removed I_VREGREFand I_VREDLVD12

• Added a note about I_{DD_BC}

.

In the “Low voltage monitor electrical characteristics” table:

• Updated V_PORHvalues.

• Updated V_LVDLVCORLvalue.

Entirely updated the “Low voltage power domain electrical characteristics” table.

In the “Program and erase specifications” table, inserted T_eslatrow.

Entirely updated the “Flash power supply DC electrical characteristics” table.

Entirely updated the “Start-up time/Switch-off time” table.

In the “Crystal oscillator and resonator connection scheme” figure, relocated a note.

In the “Slow external crystal oscillator (32 kHz) electrical characteristics” table:

• Removed g_mSXOSCrow.

• Inserted values of I_SXOSCBIAS

.

Entirely updated the “Fast internal RC oscillator (16 MHz) electrical characteristics” table.

In the “ADC conversion characteristics” table: updated the description of the conditions of

t_{ADC_PU}and t_{ADC_S.}

Entirely updated the “DSPI characteristics” table.

In the “Orderable part number summary” table, modified some orderable part number.

Updated the “Commercial product code structure” figure.

Removed the note about the condition from “Flash read access timing” table

Removed the notes that assert the values need to be confirmed before validation

Exchanged the order of “LQFP 100-pin configuration” and “LQFP 144-pin configuration”

Exchanged the order of “LQFP 100-pin package mechanical drawing” and “LQFP 144-pin

package mechanical drawing”

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

103

Document revision history

Table 49. Revision history (continued)

Description of Changes

Revision

Date

7

05-Jul-2010 Added 64 LQFP package information

Updated the “Features” section.

Figures “LQFP 100-pin configuration” and “LQFP 100-pin configuration”: removed

alternate function information

Added “Functional port pin descriptions” table

Added eDMA block in the “MPC5604B/C series block diagram” figure

Deleted the “NVUSRO[WATCHDOG_EN] field description” section

In the “Recommended operating conditions (3.3 V)” and “Recommended operating

conditions (5.0 V)” tables, deleted the conditions of T_{A C-Grade Part,}T_{A V-Grade Part,}T_{A M-Grade}

Part

In the “LQFP thermal characteristics” table, rounded the values.

In the “RESET electrical characteristics” section, replaced “nRSTIN” with “RESET”.

In the “I/O input DC electrical characteristics” table:

• W_FI: inserted a footnote

• W_NFI: inserted a footnote

In the “Low voltage monitor electrical characteristics” table:

• changed min value V_LVDHV3L, from 2.7 to 2.6

• Inserted max value of V_LVDLVCORL

In the “FMPLL electrical characteristics” table, rounded the values of f_VCO.

In the “DSPI characteristics” table:

• Added Δt_ASCrow

• Update values of t_A

In the “ADC conversion characteristics” table, added “I_ADCPWD” and “I_ADCRUN” rows

Removed “Orderable part number summary” table.

8

25-Nov-2010 Editorial changes and improvements.

In the “MPC5604B/C device comparison” table, changed the temperature value from 105

to 125 °C, in the footnote regarding “Execution speed”.

In the “Recommended operating conditions (3.3 V)” and “Recommended operating

conditions (5.0 V)” tables, restored the conditions of T_{A C-Grade Part,}T_{A V-Grade Part,}T_A

M-Grade Part

In the “LQFP thermal characteristics” table, added values concerning 64 LQFP package.

In the “MEDIUM configuration output buffer electrical characteristics” table: fixed a typo in

last row of conditions column, there was I_OHthat now is I_OL

.

In the “Reset electrical characteristics” table, changed the parameter classification tag for

V_OLand |I_WPU|.

In the “Low voltage monitor electrical characteristics” table, changed the max value of

V_LVDLVCORLfrom 1.5V to 1.15V.

In the “Program and erase specifications” table, replaced “T_eslat” with “T_esus”.

In the “FMPLL electrical characteristics” table, changed the parameter classification tag

for f_VCO

.

MPC5604B/C Microcontroller Data Sheet, Rev. 14

104

NXP Semiconductors

Document revision history

Table 49. Revision history (continued)

Description of Changes

Revision

Date

9

16 June 2011 Formatting and minor editorial changes throughout

Harmonized oscillator nomenclature

Removed all instances of note “All 64 LQFP information is indicative and must be

confirmed during silicon validation.”

Device comparison table: changed temperature value in footnote 2 from 105 °C to 125 °C

MPC560xB LQFP 64-pin configuration and MPC560xC LQFP 64-pin configuration:

renamed pin 6 from VPP_TEST to VSS_HV

Removed “Pin Muxing” section; added sections “Pad configuration during reset phases”,

“Voltage supply pins”, “Pad types”, “System pins,” “Functional ports”, and “Nexus 2+

pins”

Section “NVUSRO register”: edited content to separate configuration into electrical

parameters and digital functionality; updated footnote describing default value of ‘1’ in

field descriptions NVUSRO[PAD3V5V] and NVUSRO[OSCILLATOR_MARGIN]

Added section “NVUSRO[WATCHDOG_EN] field description”

Recommended operating conditions (3.3 V) and Recommended operating conditions

(5.0 V): updated conditions for ambient and junction temperature characteristics

I/O input DC electrical characteristics: updated I_LKGcharacteristics

Section “I/O pad current specification”: removed content referencing the I_DYNSEG

maximum value

I/O consumption: replaced instances of “Root medium square” with “Root mean square”

I/O weight: replaced instances of bit “SRE” with “SRC”; added pads PH[9] and PH[10];

added supply segments; removed weight values in 64-pin LQFP for pads that do not

exist in that package

Reset electrical characteristics: updated parameter classification for |I_WPU

|

Updated Voltage regulator electrical characteristics

Section “Low voltage detector electrical characteristics”: changed title (was “Voltage

monitor electrical characteristics”); added event status flag names found in RGM

chapter of device reference manual to POR module and LVD descriptions; replaced

instances of “Low voltage monitor” with “Low voltage detector”; updated values for

V_LVDLVBKPLand V_LVDLVCORL; replaced “LVD_DIGBKP” with “LVDLVBKP” in note

Updated section “Power consumption”

Fast external crystal oscillator (4 to 16 MHz) electrical characteristics: updated parameter

classification for V_FXOSCOP

Crystal oscillator and resonator connection scheme: added footnote about possibility of

adding a series resistor

Slow external crystal oscillator (32 kHz) electrical characteristics: updated footnote 1

FMPLL electrical characteristics: added short term jitter characteristics; inserted “—” in

empty min value cell of t_lockrow

Section “Input impedance and ADC accuracy”: changed “V_A/V_A2” to “V_A2/V_A” in

Equation 11

ADC input leakage current: updated I_LKGcharacteristics

ADC conversion characteristics: updated symbols

On-chip peripherals current consumption: changed “supply current on “V_{DD_HV_ADC”}to

“supply current on” V_{DD_HV}” in I_{DD_HV(FLASH)}row; updated I_{DD_HV(PLL)}value—was

3 * f_periph, is 30 * f_periph; updated footnotes

DSPI characteristics: added rows t_PCSCand t_PASC

Added DSPI PCS strobe (PCSS) timing diagram

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

105

Document revision history

Table 49. Revision history (continued)

Description of Changes

Revision

Date

10

15 Oct 2012 Table 2 (Bolero 512K device comparison), added footnote for MPC5603BxLH and

MPC5604BxLH about FlexCAN availability.

Table 2 (MPC5604B/C series block summary), replaced “System watchdog timer” with

“Software watchdog timer” and specified AUTOSAR (Automotive Open System

Architecture)

Table 5 (Functional port pin descriptions):

replaced footnote “Available only on MPC560xC versions and MPC5604B 208

MAPBGA devices” with “Available only on MPC560xC versions, MPC5603B 64 LQFP,

MPC5604B 64 LQFP and MPC5604B 208 MAPBGA devices”,

replaced VDD with VDD_HV

Figure 10 (Voltage regulator capacitance connection), updated pin name appearance

Renamed Figure 11 (V_{DD_HV}and V_{DD_BV}maximum slope) (was “VDD and VDD_BV

maximum slope”)

Renamed Figure 12 (V_{DD_HV}and V_{DD_BV}supply constraints during STANDBY mode exit)

(was “VDD and VDD_BV supply constraints during STANDBY mode exit”)

Table 12 (Recommended operating conditions (3.3 V)), added minimum value of T_VDD

and footnote about it.

Table 13 (Recommended operating conditions (5.0 V)), added minimum value of T_VDD

and footnote about it.

Section 2.17.1, “Voltage regulator electrical characteristics:

replaced “slew rate of V_DD/V_{DD_BV}” with “slew rate of both V_{DD_HV}and V_{DD_BV}

”

replaced “When STANDBY mode is used, further constraints apply to the V_DD/V_{DD_BV}

in order to guarantee correct regulator functionality during STANDBY exit.” with “When

STANDBY mode is used, further constraints are applied to the both V_{DD_HV}and

V_{DD_BV}in order to guarantee correct regulator function during STANDBY exit.”

Table 27 (Power consumption on VDD_BV and VDD_HV), updated footnotes of I_DDMAX

and I_DDRUNstating that both currents are drawn only from the V_{DD_BV}pin.

Table 31 (Flash memory power supply DC electrical characteristics), in the parameter

column replaced V_{DD_BV}and V_{DD_HV}respectively with VDD_BV and VDD_HV.

Table 45 (On-chip peripherals current consumption), in the parameter column replaced

V_{DD_BV}, V_{DD_HV}and V_{DD_HV_ADC}respectively with VDD_BV, VDD_HV and

VDD_HV_ADC

Updated Section 2.26.2, “Input impedance and ADC accuracy

Table 46 (DSPI characteristics), modified symbol for t_PCSCand t_PASC

11

14 Nov 2012 In the cover feature list:

added “and ECC” at the end of “Up to 512 KB on-chip code flash supported with the

flash controller”

added “with ECC” at the end of “Up to 48 KB on-chip SRAM”

Table 12 (Recommended operating conditions (3.3 V)), removed minimum value of T_VDD

and relative footnote.

Table 13 (Recommended operating conditions (5.0 V)), removed minimum value of T_VDD

and relative footnote.

12

19 Mar 2014 Added “K=TSMC Fab” against the Fab and mask indicator in Figure 45 (Commercial

product code structure).

MPC5604B/C Microcontroller Data Sheet, Rev. 14

106

NXP Semiconductors

Document revision history

Table 49. Revision history (continued)

Description of Changes

Revision

Date

13

19 Jan 2015 In Table 1 (MPC5604B/C device comparison):

• changed the MPC5604BxLH entry for CAN (FlexCAN) from 3⁷to 2⁶.

• updated tablenote 7.

In Table 13 (Recommended operating conditions (5.0 V)), updated tablenote 5 to: “1 µF

(electrolithic/tantalum) + 47 nF (ceramic) capacitance needs to be provided between

V_{DD_ADC}/V_{SS_ADC}pair. Another ceramic cap of 10nF with low inductance package can be

added”.

In Section 2.17.2, “Low voltage detector electrical characteristics, added a note on

LVHVD5 detector.

In Section 4, “Ordering information, added a note: “Not all options are available on all

devices”.

14

30 oct 2017 In Table 1 (MPC5604B/C device comparison) for MPC56 04BxLH changed the CAN from

2 to 3.

In Table 12 (Recommended operating conditions (3.3 V)) added Min value for TV_DD

In Table 13 (Recommended operating conditions (5.0 V)) added Min value for TV_DD

MPC5604B/C Microcontroller Data Sheet, Rev. 14

NXP Semiconductors

107

Abbreviations

Appendix A Abbreviations

Table A-1 lists abbreviations used but not defined elsewhere in this document.

Table A-1. Abbreviations

Abbreviation

Meaning

CMOS

CPHA

CPOL

CS

Complementary metal–oxide–semiconductor

Clock phase

Clock polarity

Peripheral chip select

Event out

EVTO

MCKO

MDO

MSEO

MTFE

SCK

Message clock out

Message data out

Message start/end out

Modified timing format enable

Serial communications clock

Serial data out

SOUT

TBD

To be defined

TCK

Test clock input

TDI

Test data input

TDO

Test data output

TMS

Test mode select

MPC5604B/C Microcontroller Data Sheet, Rev. 14

108

NXP Semiconductors

How to Reach Us:

Home Page:

nxp.com

Information in this document is provided solely to enable system and

software implementers to use NXP products. There are no express or

implied copyright licenses granted hereunder to design or fabricate any

integrated circuits based on the information in this document. NXP

reserves the right to make changes without further notice to any products

herein.

Web Support:

nxp.com/support

NXP makes no warranty, representation, or guarantee regarding the suit-

ability of its products for any particular purpose, nor does NXP assume

any liability arising out of the application or use of any product or circuit,

and specifically disclaims any and all liability, including without limita-

tion consequential or incidental damages. “Typical” parameters that may

be provided in NXP data sheets and/or specifications can and do vary in

different applications, and actual performance may vary over time. All

operating parameters, including “typicals,” must bevalidated for each

customer application by customer's technical experts. NXP does not con-

vey any license under its patent rights nor the rights of others. NXP sells

products pursuant to standard terms and conditions of sale, which can

befound at the following address: nxp.com/SalesTermsandConditions.

NXP, the NXP logo, NXP SECURE CONNECTIONS FOR A SMARTER

WORLD, COOLFLUX, EMBRACE, GREENCHIP, HITAG, I2C BUS, ICODE,

JCOP, LIFE VIBES, MIFARE, MIFARE CLASSIC, MIFARE DESFire, MIFARE

PLUS, MIFARE FLEX, MANTIS, MIFARE ULTRALIGHT, MIFARE4MOBILE,

MIGLO, NTAG, ROADLINK, SMARTLX, SMARTMX, STARPLUG, TOPFET,

TRENCHMOS, UCODE, Freescale, the Freescale logo, AltiVec, C.5, CodeTEST,

CodeWarrior, ColdFire, ColdFire+, C.Ware, the Energy Efficient Solutions logo,

Kinetis, Layerscape, MagniV, mobileGT, PEG, PowerQUICC, Processor Expert,

QorIQ, QorIQ Qonverge, Ready Play, SafeAssure, the SafeAssure logo, StarCore,

Symphony, VortiQa, Vybrid, Airfast, BeeKit, BeeStack, CoreNet, Flexis, MXC,

Platform in a Package, QUICC Engine, SMARTMOS, Tower, TurboLink, and

UMEMS are trademarks of NXP B.V. All other product or service names are the

property of their respective owners. Arm, AMBA, Arm Powered, Artisan, Cortex,

Jazelle, Keil, SecurCore, Thumb, TrustZone, and ÏVision are registered trademarks

of Arm Limited (or its subsidiaries) in the EU and/or elsewhere. Arm7, Arm9,

Arm11, big.LITTLE, CoreLink, CoreSight, DesignStart, Mali, Mbed, NEON,

POP, Sensinode, Socrates, ULINK and Versatile are trademarks of Arm Limited

Java are registered trademarks of Oracle and/or its affiliates. The Power Architec-

ture and Power.org word marks and the Power and Power.org logos and related

marks are trademarks and service marks licensed by Power.org.

Document Number: MPC5604BC

Rev. 14

11/2017


型号：	SPC5604CFMMG6R
厂家：	NXP
描述：	MPC5604B/C Microcontroller Data Sheet PC 微控制器
文件：	总109页 (文件大小：1086K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SPC5604CFMMG6R [NXP]

相关型号：

UL1042

ZXFV201

ZXFV201N14

ZXFV201N14TA

ZXFV201N14TC

ZXFV202E5

ZXFV202N8

ZXFV203N14

ZXFV301N16(1)

ZXFV302N16

ZXFV4089

ZXFV4089N8