SPC5604EEF2MLH [NXP]
MPC5604E Microcontroller;
| 型号： | SPC5604EEF2MLH |
| 厂家： | 
NXP |
| 描述： | MPC5604E Microcontroller PC 微控制器 |
| 文件： | 总76页 (文件大小：1018K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NXP Semiconductors
Data Sheet: Technical Data
Document Number: MPC5604E
Rev. 6, 11/2019
MPC5604E
100 LQFP
14 mm x 14 mm
MPC5604E Microcontroller
Data Sheet
64 LQFP
10 mm x 10 mm
— Quadrature decode with rotation direction flag
— Double buffer input capture and output compare
Communications interfaces
•
Single issue, 32-bit CPU core complex (e200z0h)
®
— Compliant with Power Architecture embedded
category
•
•
— Variable Length Encoding (VLE) only
Memory
— 2 LINFlex channels (1 × Master/Slave, 1 ×
Master Only)
•
— 3 DSPI controllers with automatic chip select
generation (up to 2/2/4 chip selects)
— 512 KB on-chip Code Flash with ECC and
erase/program controller
— 1 FlexCAN interface (2.0B Active) with 32
message buffers
— additional 64 (4 × 16) KB on-chip Data Flash
with ECC for EEPROM emulation
One 10-bit analog-to-digital converter (ADC)
— 7 input channels
— 96 KB on-chip SRAM with ECC
Fail-safe protection
•
–
–
4 channels routed to the pins
— Programmable watchdog timer
— Non-maskable interrupt
— Fault collection unit
3 internal connections: 1x temperature
sensor, 1x core voltage, 1x IO voltage
— Conversion time < 1 μ s including sampling
•
•
Nexus 2+ interface
time at full precision
Interrupts and events
— 4 analog watchdogs with interrupt capability
— 16-channel eDMA controller
— 16 priority level controller
•
On-chip CAN/UART bootstrap loader with Boot
Assist Module (BAM)
1
— Up to 32 external interrupts for 100-pin LQFP
•
•
On-chip TSENS
— Upto 22 external interrupts for 64-pin LQFP
— PIT implements four 32-bit timers
— 120 interrupts are routed via INTC
General purpose I/Os
100 MBit Fast Ethernet Controller (FEC)
— Supports precision timestamps
1
— MII on 100-pin LQFP package
•
•
— MII-lite on 64-pin LQFP package
JPEG/MJPEG 8/12bit Encoder
— Individually programmable as input, output or
special function
•
•
•
•
6 x stereo channels audio interface
— 39 on LQFP64
2
2x I C controller module
1
— 71 on LQFP100
CRC module
1 general purpose eTimer unit
— 6 timers each with up/down capabilities
— 16-bit resolution, cascadeable counters
1.The 100-pin package is not a production package.
It is used for software development only.
NXP reserves the right to change or discontinue this product without notice.
Table of Contents
1
2
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
3.14 Analog-to-Digital Converter (ADC) electrical characteristics
1.1 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Package pinouts and signal descriptions . . . . . . . . . . . . . . . . .6
2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2.2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.2.1 Power supply and reference voltage pins . . . . . .8
2.2.2 System pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.2.3 Pin muxing. . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.2 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . .21
3.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .22
3.4 Recommended operating conditions . . . . . . . . . . . . . .23
3.5 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .24
3.5.1 General notes for specifications at maximum
junction temperature . . . . . . . . . . . . . . . . . . . . .25
37
3.14.1 Input impedance and ADC accuracy . . . . . . . . 37
3.14.2 ADC conversion characteristics . . . . . . . . . . . . 41
3.15 Temperature sensor electrical characteristics . . . . . . . 42
3.16 Flash memory electrical characteristics . . . . . . . . . . . 42
3.17 NMI filter functional specification. . . . . . . . . . . . . . . . . 44
3.18 AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.18.1 Pad AC specifications. . . . . . . . . . . . . . . . . . . . 44
3.19 AC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . 47
3.19.1 Generic timing diagrams . . . . . . . . . . . . . . . . . 47
3.19.2 RESET pin characteristics . . . . . . . . . . . . . . . . 49
3.19.3 Nexus and JTAG timing . . . . . . . . . . . . . . . . . . 50
3.19.4 GPIO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.19.5 External interrupt timing (IRQ pin) . . . . . . . . . . 53
3.19.6 FlexCAN timing . . . . . . . . . . . . . . . . . . . . . . . . 53
3.19.7 LINFlex timing . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.19.8 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.19.9 Video interface timing. . . . . . . . . . . . . . . . . . . . 59
3.19.10Fast ethernet interface. . . . . . . . . . . . . . . . . . . 60
3.19.11I2C timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.19.12SAI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.1 100 LQFP mechanical outline drawing . . . . . . . . . . . . 66
4.2 64 LQFP mechanical outline drawing . . . . . . . . . . . . . 70
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3
3.6 Electromagnetic Interference (EMI) characteristics . . .26
3.7 Electrostatic Discharge (ESD) characteristics . . . . . . .27
3.8 Power management electrical characteristics. . . . . . . .27
3.8.1 Power Management Overview. . . . . . . . . . . . . .27
3.8.2 Voltage regulator electrical characteristics . . . .30
3.8.3 Voltage monitor electrical characteristics. . . . . .31
3.9 Power Up/Down reset sequencing . . . . . . . . . . . . . . . .31
3.10 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . .33
3.11 Main oscillator electrical characteristics . . . . . . . . . . . .34
3.12 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . .35
3.13 16 MHz RC oscillator electrical characteristics. . . . . . .36
4
5
6
MPC5604E Microcontroller Data Sheet, Rev. 6
2
NXP Semiconductors
Overview
1
Overview
This document provides electrical specifications, pin assignments, and package diagrams for the MPC5604E series of
microcontroller units (MCUs).
MPC5604E microcontrollers are members of a new family of next generation microcontrollers built on the Power Architecture.
This document describes the features of the family and options available within the family members, and highlights important
electrical and physical characteristics of the devices.
The MPC5604E microcontroller is a gateway system designed to move data from different sources via Ethernet to a receiving
system and vice versa. The supported data sources and sinks are:
•
•
•
•
Video data (with 8/10/12 bits per data word)
Audio data (6× stereo channels)
RADAR data (2 × 12 bit with <1μs per sample, digitized externally and read in via SPI)
Other serial communication interfaces including CAN, LIN, and SPI
The Ethernet module has a bandwidth of 10/100 Mbits/sec and supports precision time stamps (IEEE1588). Unshielded twisted
pair cables are used to transfer data (via Ethernet) in the car, resulting in a significant reduction of wiring costs by providing
inexpensive high bandwidth data links.
1.1
Device summary
The following table summarizes the MPC5604E device.
NOTE
The 100-pin package is not a production package. It is used for software development only.
Table 1. Device summary
MPC5604E
Feature
100-pin LQFP1
e200z0h, 64 MHz, VLE only, no SPE
64-pin LQFP
CPU
Flash with ECC
RAM with ECC
DMA
CFlash: 512 KB (LC) DFlash: 64 KB (LC, area optimized)
96 KB
16 channels
yes
PIT
SWT
yes
FCU
yes
Ethernet
100 Mbits MII
100 Mbits MII-Lite
Video Encoder
Audio Interface
ADC (10-bit)
Timer I/O (eTimer)
SCI (LINFlex)
SPI (DSPI)
8bpp/12bpp
6x Stereo (4x synchronous + 2x synchronous/asynchronous)
1× 4 channels + VDD_IO + VDDCore + TSens
1×6 channels
2×
DSPI_0: 2 chip selects
DSPI_1: 2 chip selects
DSPI_2: 4 chip selects
MPC5604E Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
3
Overview
Table 1. Device summary (continued)
MPC5604E
Feature
100-pin LQFP1
64-pin LQFP
CAN (FlexCAN)
IIC
1×
2×
Supply
3.3 V IO
1.2V Core with dedicated ballast source pin in two modes:
• internal ballast or
• external supply (using power on reset pin)
Phase Lock Loop (PLL)
Internal RC Oscillator
1× FMPLL
16 MHz
External crystal
Oscillator
4 MHz - 40 MHz
yes
CRC
Debug
JTAG, Nexus2+
JTAG
Ambient Temperature
–40 to 125 °C
1
The 100-pin package is not a production package. It is used for software development only.
1.2
Block diagram
Figure 1 shows a top-level block diagram of the MPC5604E MCU.
MPC5604E Microcontroller Data Sheet, Rev. 6
4
NXP Semiconductors
Overview
Internal and
External Ballast
e200z0 Core
32-bit
General
Purpose
Registers
1.2 V Regulator
Control
Integer
Execution
Unit
Special
Purpose
Registers
Exception
Handler
Interrupt
Controller
XOSC
16 MHz
RC Oscillator
Variable
Length
Encoded
Instructions
Instruction
Unit
FMPLL
(System)
Branch
Prediction
Unit
JTAG
Nexus2+
Load/Store
Unit
JTAG Port
Nexus2+
MII
eDMA
16 channels
Instruction Bus
(32-bit)
Data Bus
(32-bit)
FEC
PTP
Master
Master
Master
Master
Crossbar Switch (XBAR, AMBA 2.0 v6 AHB)
video_clk
Slave
Slave
Slave
Slave
512 KB
64 KB
Data
96 KB
SRAM
(ECC)
Code
Flash
Flash
(ECC)
(ECC)
Peripheral Bridge
ADC
10-bit
4+3 channels
ADC
BAM
CRC
DSPI
eDMA
Analog-to-Digital Converter
Boot Assist Module
Cylic Redundancy Check
Deserial Serial Peripheral Interface
Enhanced Direct Memory Access
CGM
PCU
RGM
Clock Generation Module
Power Control Unit
Reset Generation Module
TSENS Temperature sensor
MJPEG 12-bit Motion JPEG Encoder
eTimer Enhanced Timer
PDI
Parallel Data Interface (image sensor)
FCD
FCU
FEC
Fractional Clock Divider
Fault Collection Unit
Fast Ethernet Controller
PIT
PTP
Periodic Interrupt Timer
IEEE 1588 Precision Time Stamps
System Integration Unit
Static Random-Access Memory
System Status and Configuration Module
System Timer Module
SIUL
SRAM
SSCM
STM
SWT
FlexCAN Flexible Controller Area Network
FMPLL
I2C
Frequency-Modulated Phase-Locked Loop
Inter-Integrated Circuit serial interface
Serial Audio Interface 6xStereo
SAI
Software Watchdog Timer
LINFlex Serial Communication Interface (LIN support)
ME
Mode Entry Module
Figure 1. MPC5604E block diagram
MPC5604E Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
5
Package pinouts and signal descriptions
2
Package pinouts and signal descriptions
2.1
Package pinouts
The LQFP pinouts are shown in the following figures.
48 B[11]
47 VSS_HV
46 B[10]
45 B[9]
NMI
A[0]
A[1]
A[2]
A[3]
1
2
3
4
B[8]
TDO
TCK
TMS
TDI
B[7]
V
44
43
42
41
40
39
38
37
36
35
34
33
5
V
V
6
SS_LV
7
DD_LV
A[4]
8
A[5]
A[6]
9
64 LQFP
10
11
12
13
14
15
16
V
V
DD_HV
DD_HV
SS_HV
XTAL
EXTAL
RESET
A[7]
V
V
V
SS_HV
SS_LV
DD_LV
B[6]
B[5]
Note:
1. All VDD_HV and VSS_HV pins must be shorted on the board. The ADC supply (VDD_HV_ADC) and ground
(VSS_HV_ADC) should be managed independently from other high-voltage supplies, (it may still be supplied from the same
high-voltage source, but caution must be taken while routing it on the board.)
2. All VDD_LV and VSS_LV pins must be shorted on the board.
Figure 2. 64-pin LQFP pinout (top view)
MPC5604E Microcontroller Data Sheet, Rev. 6
6
NXP Semiconductors
Package pinouts and signal descriptions
75
74
73
72
71
70
69
68
67
66
B[11]
SS_HV
B[10]
D[3]
E[1]
B[9]
D[15]
E[0]
B[8]
TDO
NMI
A[0]
C[7]
A[1]
C[8]
A[2]
C[9]
A[3]
D[0]
D[8]
SS_LV
DD_LV
D[2]
D[1]
A[4]
A[5]
A[6]
DD_HV
SS_HV
XTAL
1
V
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
65 TCK
64 TMS
63 TDI
62 B[7]
V
V
100 LQFP
61
60
59
58
57
56
55
54
53
52
51
V
V
V
V
DD_HV
SS_HV
SS_LV
DD_LV
V
V
D[14]
B[6]
B[5]
EXTAL
RESET
A[7]
C[10]
C[11]
D[13]
D[12]
D[11]
D[10]
1. All VDD_HV and VSS_HV pins must be shorted on the board. The ADC supply (VDD_HV_ADC) and ground
(VSS_HV_ADC) should be managed independently from other high-voltage supplies, (it may still be supplied from the same
high-voltage source, but caution must be taken while routing it on the board.)
2. All VDD_LV and VSS_LV pins must be shorted on the board.
1
Figure 3. 100-pin LQFP pinout (top view)
1.The 100-pin package is not a production package. It is used for software development only.
MPC5604E Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
7
Package pinouts and signal descriptions
2.2
Signal descriptions
The following sections provide signal descriptions and related information about the functionality and configuration of the
MPC5604E devices.
2.2.1
Power supply and reference voltage pins
Table 2 lists the power supply and reference voltage for the MPC5604E devices.
Table 2. Supply pins
Supply
Pin
Multi-bonded Power
Supplies/Ground
Port Pin
Description
64-pin 100-pin1
VREG control and power supply pins. Pins available on 64-pin and 100-pin package.
VDD_HV_S_BALLAST0
VDD_HV_S_BALLAST1
Ballast Source/Supply Voltage
Ballast Source/Supply Voltage
VDD_HV_S_BALLAST
23
34
ADC0 reference and supply voltage. Pins available on 64-pin and 100-pin package.
ADC0 supply voltage with respect to ground
VDD_HV_ADC0
(VSS_HV_ADC
)
VDD_HV_ADC
21
22
30
31
ADC0 high reference voltage with respect
to ground (VSS_HV_ADC
VDD_HV_ADC0
VSS_HV_ADC0
VSS_HV_ADC0
)
ADC0 ground voltage with respect to
ground
VSS_HV_ADC
ADC0 low reference voltage with respect to
ground
Power supply pins (3.3 V). Pins available on 64-pin and 100-pin package.
VDD_HV_IO0_0
VDD_HV_OSC0
VDD_HV_IO0_2
VDD_HV_FLA1
VDD_HV_IO0_3
VDD_HV_FLA0
VDD_HV
Input/output ground voltage
11
38
18
61
Crystal oscillator amplifier supply voltage
3.3 V Input/Output Supply Voltage (supply)
Code and data flash supply voltage
3.3 V Input/Output Supply Voltage (supply)
Code and data flash supply voltage
HV Supply
VDD_HV
55
-
87
36
19
VSS_HV_IO0_0
VSS_HV_OSC0
VSS_HV_IO0_2
Vss_HV_FLA1
Vss_IO0_4
Input/output ground voltage
12
Crystal oscillator amplifier ground
Input/output ground voltage
37
60
VSS_HV
Code and data flash supply ground
Input/output ground voltage
35
88
74
56
47
Vss_HV_FLA0
VSS_HV
Code and data flash supply voltage
HV Ground
MPC5604E Microcontroller Data Sheet, Rev. 6
8
NXP Semiconductors
Package pinouts and signal descriptions
Table 2. Supply pins (continued)
Supply
Pin
Multi-bonded Power
Supplies/Ground
Port Pin
Description
64-pin 100-pin1
Power supply pins (1.2 V). Pins available on 64-pin and 100-pin package.
1.2 V supply pins for core logic and code
Flash. Decoupling capacitor must be
connected between these pins and the
VDD_LV_COR0_3
7
12
92
nearest VSS_LV_COR0_3 pin.
VDD_LV_PLL0
VDD_LV_COR0_2
VDD_LV_FLA0
1.2 V PLL supply voltage
1.2 V supply pins for core logic and code
Flash. Decoupling capacitor must be
connected between these pins and the
nearest VSS_LV_COR0_2 pin.
VDD_LV
58
Code and data flash supply voltage
1.2 V supply pins for core logic and code
Flash. Decoupling capacitor must be
connected between these pins and the
nearest VSS_LV_COR0_1 pin.
VDD_LV_COR0_1
35
-
58
33
11
VDD_LV_FLA1
VDD_LV
Code and data flash supply voltage
Core supply
1.2 V supply pins for core logic and code
Flash. Decoupling capacitor must be
connected betwee.n these pins and the
nearest VDD_LV_COR0_3 pin.
VSS_LV_COR0_3
6
VSS_LV_PLL0
PLL supply ground
1.2 V supply pins for core logic and code
Flash. Decoupling capacitor must be
connected betwee.n these pins and the
nearest VDD_LV_COR0_2 pin.
VSS_LV_COR0_2
59
93
VSS_LV
VSS_LV_FLA0
Code and data flash supply ground
1.2 V supply pins for core logic and data
Flash. Decoupling capacitor must be
connected between these pins and the
nearest VDD_LV_COR0_1 pin.
VSS_LV_COR0_1
36
-
59
32
VSS_LV_FLA1
VSS_LV
Code and data flash supply ground
Core ground
1
The 100-pin package is not a production package. It is used for software development only.
2.2.2
System pins
Table 3 and Table 4 contain information on pin functions for the MPC5604E devices. The pins listed in Table 3 are
single-function pins. The pins shown in Table 4 are multi-function pins, programmable via their respective Pad Configuration
Register (PCR) values.
MPC5604E Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
9
Package pinouts and signal descriptions
Table 3. System pins
Direction
Pad speed1
Pin
Symbol
Description
SRC = 0 SRC = 1
64-pin
100-pin2
Dedicated pins
Input only
NMI
Non-maskable Interrupt
Oscillator amplifier output
Slow
—
—
—
1
1
XTAL
Output only
13
20
Input for oscillator amplifier circuit and
internal clock generator
EXTAL
Input only
—
—
14
21
TDI3
TMS3
TCK3
TDO3
JTAG test data input
JTAG state machine control
JTAG clock
Input only
Input only
Input only
Output only
Slow
Slow
Slow
Slow
Medium
Medium
—
40
41
42
43
63
64
65
66
JTAG test data output
Medium
Reset pin
Bidirectional reset with Schmitt trigger
characteristics and noise filter
RESET
Bidirectional
Input only
Medium
—
—
—
15
31
22
45
POR_B Power-on reset
1
2
3
SRC values refer to the value assigned to the Slew Rate Control bits of the pad configuration register.
The 100-pin package is not a production package. It is used for software development only.
Additional board pull resistors are recommended when JTAG pins are not being used on the board or application.
2.2.3
Pin muxing
Table 4 defines the pin list and muxing for the MPC5604E devices.
Each row of Table 4 shows all the possible ways of configuring each pin, via “alternate functions”. The default function
assigned to each pin after reset is the ALT0 function.Pins marked as external interrupt capable can also be used to resume from
STOP and HALT mode.
MPC5604E devices provide four main I/O pad types depending of the associated functions:
•
•
Slow pads are the most common, providing a compromise between transition time and low electromagnetic emission.
Medium pads provide fast enough transition for serial communication channels with controlled current to reduce
electromagnetic emission.
•
Fast pads provide maximum speed. They are used for improved Nexus debugging capability.
Medium and Fast pads can be used in slow configuration to reduce the electromagnetic emissions, at the cost of reducing AC
performance.
MPC5604E Microcontroller Data Sheet, Rev. 6
10
NXP Semiconductors
Package pinouts and signal descriptions
Table 4. Pin muxing
Pad speed5
Pin6
Port
pin
PCR
Alternate
I/O
Functions
Peripheral3
register function1,2,8
direction4
SRC = 0 SRC = 1
64-pin 100-pin7
Port A (16-bit)
A[0]
PCR[0]
ALT0
ALT1
ALT2
ALT3
—
GPIO[0]
D[0]
—
—
D[11]
SIN
SIUL
SAI0
—
—
VID
I/O
I/O
—
—
I
Slow
Medium
2
2
—
—
DSPI 1
SIUL
I
I
EIRQ[0]
A[1]
A[2]
PCR[1]
PCR[2]
ALT0
ALT1
ALT2
ALT3
—
GPIO[1]
D[1]
SOUT
—
D[10]
EIRQ[1]
SIUL
SAI0
DSPI1
—
VID
SIUL
I/O
I/O
O
—
I
Slow
Slow
Medium
Medium
3
4
4
6
—
I
ALT0
ALT1
ALT2
ALT3
—
GPIO[2]
D[2]
SCK
D[0]
D[9]
SIUL
SAI0
DSPI1
SAI1
VID
I/O
I/O
I/O
I/O
I
—
—
ETC[5]
EIRQ[2]
ETIMER0
SIUL
I
I
A[3]
A[4]
A[5]
PCR[3]
PCR[4]
PCR[5]
ALT0
ALT1
ALT2
ALT3
—
GPIO[3]
D[3]
—
D[0]
D[8]
SIUL
SAI0
—
SAI2
VID
I/O
I/O
—
I/O
I
Slow
Medium
Medium
Fast
5
8
9
8
—
—
SIN
EIRQ[3]
DSPI2
SIUL
I
I
ALT0
ALT1
ALT2
ALT3
—
GPIO[4]
SYNC
SOUT
—
D[7]
ETC[3]
EIRQ[4]
SIUL
SAI0
DSPI2
—
VID
ETIMER0
SIUL
I/O
I/O
O
—
I
Slow
15
16
—
—
I
I
ALT0
ALT1
ALT2
ALT3
—
GPIO[5]
SYNC
SCK
D[0]
CLK
SIUL
SAI1
DSPI2
SAI1
VID
I/O
I/O
I/O
I/O
I
Medium
—
—
ETC[4]
EIRQ[5]
ETIMER0
SIUL
I
I
MPC5604E Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
11
Package pinouts and signal descriptions
Table 4. Pin muxing (continued)
I/O
Pad speed5
Pin6
Port
pin
PCR
Alternate
Functions
Peripheral3
register function1,2,8
direction4
SRC = 0 SRC = 1
64-pin 100-pin7
A[6]
PCR[6]
ALT0
ALT1
ALT2
ALT3
—
—
—
—
GPIO[6]
SYNC
CS0
—
VSYNC
D[0]
SIUL
SAI2
DSPI2
—
VID
VID
I/O
I/O
I/O
—
I
I
I
I
Slow
Slow
Slow
Medium
Medium
Medium
10
17
23
37
ETC[1]
EIRQ[6]
ETIMER0
SIUL
A[7]
PCR[7]
ALT0
ALT1
ALT2
ALT3
—
—
—
—
GPIO[7]
BCLK
CS1
—
HREF
D[1]
SIUL
SAI0
DSPI2
—
VID
VID
I/O
I/O
I/O
—
I
I
I
I
16
ETC[2]
EIRQ[7]
ETIMER0
SIUL
A[8]
PCR[8]
PCR[9]
ALT0
ALT1
ALT2
ALT3
—
GPIO[8]
BCLK
CS0
D[0]
D[6]
SIUL
SAI1
DSPI1
SAI2
VID
I/O
I/O
I/O
I/O
I
24
—
—
RX
EIRQ[8]
LIN1
SIUL
I
I
A[9]
ALT0
ALT1
ALT2
ALT3
—
GPIO[9]
BCLK
CS1
TX
D[5]
SIUL
SAI2
DSPI1
LIN1
VID
I/O
I/O
I/O
O
I
I
Slow
Slow
Medium
Medium
25
26
38
39
—
EIRQ[9]
SIUL
A[10]
PCR[10] ALT0
GPIO[10]
MCLK
ETC[5]
—
SIUL
SAI2
ETIMER0
—
I/O
I/O
I/O
—
I
ALT1
ALT2
ALT3
—
D[4]
VID
—
—
SIN
EIRQ[10]
DSPI0
SIUL
I
I
A[11]
PCR[11] ALT0
GPIO[11]
TX
CS1
CS0
D[3]
RX
SIUL
CAN0
DSPI0
DSPI1
VID
I/O
O
O
I/O
I
Slow
Medium
27
40
ALT1
ALT2
ALT3
—
—
LIN0
I
—
RX
LIN1
I
MPC5604E Microcontroller Data Sheet, Rev. 6
12
NXP Semiconductors
Package pinouts and signal descriptions
Table 4. Pin muxing (continued)
I/O
Pad speed5
Pin6
Port
pin
PCR
Alternate
Functions
Peripheral3
register function1,2,8
direction4
SRC = 0 SRC = 1
64-pin 100-pin7
A[12]
PCR[12] ALT0
GPIO[12]
TX
CS0
TX
D[2]
SIUL
LIN0
DSPI0
LIN1
VID
I/O
Slow
Medium
28
41
ALT1
ALT2
ALT3
—
O
I/O
O
I
—
—
RX
EIRQ[11]
CAN0
SIUL
I
I
A[13]
A[14]
PCR[13] ALT0
GPIO[13]
CLK
F[0]
CS0
EIRQ[12]
SIUL
IIC1
FCU0
DSPI0
SIUL
I/O
I/O
O
I/O
I
Slow
Slow
Medium
Medium
29
30
42
43
ALT1
ALT2
ALT3
—
PCR[14] ALT0
GPIO[14]
DATA
F[1]
CS1
SIN
SIUL
IIC1
FCU0
DSPI0
DSPI0
SIUL
I/O
I/O
O
O
I
ALT1
ALT2
ALT3
—
—
EIRQ[13]
I
A[15]
PCR[15] ALT0
GPIO[15]
SCK
PPS3
MCLK
SCK
ETC[0]
EIRQ[18]
SIUL
I/O
I/O
O
I/O
I
Slow
Medium
61
95
ALT1
ALT2
ALT3
—
—
—
DSPI0
CE_RTC
SAI1
DSPI1
ETIMER0
SIUL
I
I
Port B (16-bit)
B[0]
B[1]
PCR[16] ALT0
GPIO[16]
TX
ALARM2
BCLK
SIUL
CAN0
I/O
O
O
I/O
I
Slow
Slow
Medium
Medium
17
18
26
27
ALT1
ALT2
ALT3
—
CE_RTC
SAI1
AN[0]
ADC08
PCR[17] ALT0
GPIO[17]
—
—
D[0]
AN[1]
RX
SIUL
—
—
SAI1
ADC08
CAN0
CE_RTC
I/O
—
—
I/O
I
ALT1
ALT2
ALT3
—
—
—
I
I
TRIGGER2
B[2]
PCR[18] ALT0
GPIO[18]
TX
PPS2
ALARM1
AN[2]
TRIGGER1
SIUL
LIN0
CE_RTC
CE_RTC
ADC08
CE_RTC
I/O
O
O
O
I
Slow
Medium
19
28
ALT1
ALT2
ALT3
—
—
I
MPC5604E Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
13
Package pinouts and signal descriptions
Table 4. Pin muxing (continued)
I/O
Pad speed5
Pin6
Port
pin
PCR
Alternate
Functions
Peripheral3
register function1,2,8
direction4
SRC = 0 SRC = 1
64-pin 100-pin7
B[3]
PCR[19] ALT0
GPIO[19]
ETC[2]
SOUT
PPS1
AN[3]
RX
SIUL
I/O
I/O
I/O
O
I
Slow
Medium
20
29
ALT1
ALT2
ALT3
—
ETIMER0
DSPI0
CE_RTC
ADC08
LIN0
—
I
—
EIRQ[14]
SIUL
I
B[4]
PCR[20] ALT0
GPI[20]
—
—
—
RX_DV
SIUL
—
—
—
FEC
I
Slow
Medium
32
50
ALT1
ALT2
ALT3
—
—
—
—
I
B[5]
PCR[21] ALT0
ALT1
GPIO[21]
TX_D0
DEBUG[0]
—
SIUL
FEC
SSCM
—
I/O
O
I/O
—
Slow
Slow
Slow
Slow
Slow
Slow
Slow
Slow
Medium
Medium
Medium
Medium
Medium
Medium
Medium
Medium
33
34
39
44
45
46
48
49
55
56
62
67
70
73
75
76
ALT2
ALT3
B[6]
PCR[22] ALT0
ALT1
GPIO[22]
TX_D1
DEBUG[1]
—
SIUL
FEC
SSCM
—
I/O
O
I/O
—
ALT2
ALT3
B[7]
PCR[23] ALT0
ALT1
GPIO[23]
TX_D2
DEBUG[2]
—
SIUL
FEC
SSCM
—
I/O
O
I/O
—
ALT2
ALT3
B[8]
PCR[24] ALT0
ALT1
GPIO[24]
TX_D3
DEBUG[3]
—
SIUL
FEC
SSCM
—
I/O
O
I/O
—
ALT2
ALT3
B[9]
PCR[25] ALT0
ALT1
GPIO[25]
TX_EN
DEBUG[4]
—
SIUL
FEC
SSCM
—
I/O
O
I/O
—
ALT2
ALT3
B[10]
B[11]
B[12]
PCR[26] ALT0
ALT1
GPIO[26]
MDC
DEBUG[5]
—
SIUL
FEC
SSCM
—
I/O
O
I/O
—
ALT2
ALT3
PCR[27] ALT0
ALT1
GPIO[27]
MDIO
DEBUG[6]
—
SIUL
FEC
SSCM
—
I/O
I/O
I/O
—
ALT2
ALT3
PCR[28] ALT0
GPIO[28]
—
DEBUG[7]
—
SIUL
—
SSCM
—
I/O
—
I/O
—
I
ALT1
ALT2
ALT3
—
TX_CLK
FEC
MPC5604E Microcontroller Data Sheet, Rev. 6
14
NXP Semiconductors
Package pinouts and signal descriptions
Table 4. Pin muxing (continued)
I/O
Pad speed5
Pin6
Port
pin
PCR
Alternate
Functions
Peripheral3
register function1,2,8
direction4
SRC = 0 SRC = 1
64-pin 100-pin7
B[13]
B[14]
B[15]
PCR[29] ALT0
GPI[29]
—
—
—
RX_D0
SIUL
—
—
—
FEC
I
Slow
Slow
Slow
Medium
Medium
Medium
50
77
79
81
ALT1
ALT2
ALT3
—
—
—
—
I
PCR[30] ALT0
GPI[30]
—
—
—
RX_D1
SIUL
—
—
—
FEC
I
51
52
ALT1
ALT2
ALT3
—
—
—
—
I
PCR[31] ALT0
GPI[31]
—
—
—
RX_D2
SIUL
—
—
—
FEC
I
ALT1
ALT2
ALT3
—
—
—
—
I
Port C (64-pin: 7-bit; 100-pin: 16-bit)
C[0]
C[1]
PCR[32] ALT0
GPI[32]
—
—
—
RX_D3
SIUL
—
—
—
FEC
I
Slow
Medium
Medium
53
54
82
83
ALT1
ALT2
ALT3
—
—
—
—
I
PCR[33] ALT0
GPI[33]
—
—
SIUL
—
—
—
FEC
SIUL
I
Slow
ALT1
ALT2
ALT3
—
—
—
—
I
—
RX_CLK
EIRQ[15]
—
I
C[2]
C[3]
PCR[34] ALT0
GPIO[34]
ETC[0]
TX
PPS1
D[0]
SIUL
I/O
I/O
O
O
I
Slow
Slow
Medium
Medium
57
60
91
94
ALT1
ALT2
ALT3
—
—
—
ETIMER0
CAN0
CE_RTC
VID
LIN0
SIUL
RX
EIRQ[16]
I
I
PCR[35] ALT0
GPIO[35]
ETC[1]
TX
SYNC
D[1]
SIUL
ETIMER0
LIN0
SAI1
VID
I/O
I/O
O
I/O
I
ALT1
ALT2
ALT3
—
—
—
RX
EIRQ[17]
CAN0
SIUL
I
I
MPC5604E Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
15
Package pinouts and signal descriptions
Table 4. Pin muxing (continued)
I/O
Pad speed5
Pin6
Port
pin
PCR
Alternate
Functions
Peripheral3
register function1,2,8
direction4
SRC = 0 SRC = 1
64-pin 100-pin7
C[4]
PCR[36] ALT0
GPIO[36]
CLK_OUT
ETC[4]
MCLK
TRIGGER1
ABS[0]
SIUL
I/O
O
I/O
I/O
I
I
I
Medium
Fast
62
96
ALT1
ALT2
ALT3
—
—
—
MC_CGL
ETIMER0
SAI0
CE_RTC
MC_RGM
SIUL
EIRQ[19]
C[5]
C[6]
PCR[37] ALT0
GPIO[37]
CLK
ETC[3]
CS2
ABS[2]
EIRQ[20]
SIUL
IIC0
ETIMER0
DSPI2
MC_RGM
SIUL
I/O
—
I/O
O
I
Slow
Slow
Medium
Medium
63
64
99
ALT1
ALT2
ALT3
—
—
I
PCR[38] ALT0
GPIO[38]
DATA
CS0
CS3
FAB
SIUL
IIC0
DSPI1
DSPI2
MC_RGM
SIUL
I/O
—
I/O
O
I
100
ALT1
ALT2
ALT3
—
—
EIRQ[21]
I
C[7]
C[8]
PCR[39] ALT0
GPIO[39]
TXD
—
—
RXD
SIUL
LIN0
—
—
LIN1
I/O
O
—
—
I
Slow
Slow
Medium
Medium
—
—
3
5
ALT1
ALT2
ALT3
—
PCR[40] ALT0
GPIO[40]
TXD
—
—
RXD
SIUL
LIN1
—
—
LIN0
SIUL
I/O
O
—
—
I
ALT1
ALT2
ALT3
—
—
EIRQ[22]
I
C[9]
PCR[41] ALT0
GPI[41]
—
—
—
SIN
SIUL
—
—
—
DSPI0
SIUL
I
Slow
Slow
Slow
Medium
Medium
Medium
—
—
—
7
ALT1
ALT2
ALT3
—
—
—
—
I
—
EIRQ[23]
I
C[10]
C[11]
PCR[42] ALT0
GPIO[42]
ETC[5]
ETC[4]
—
SIN
EIRQ[24]
SIUL
I/O
I/O
I/O
—
I
24
25
ALT1
ALT2
ALT3
—
ETIMER0
ETIMER0
—
DSPI1
SIUL
—
I
PCR[43] ALT0
ALT1
GPIO[43]
ETC[2]
ETC[1]
ETC[3]
SIUL
I/O
I/O
I/O
I/O
ETIMER0
ETIMER0
ETIMER0
ALT2
ALT3
MPC5604E Microcontroller Data Sheet, Rev. 6
16
NXP Semiconductors
Package pinouts and signal descriptions
Table 4. Pin muxing (continued)
I/O
Pad speed5
Pin6
Port
pin
PCR
Alternate
Functions
Peripheral3
register function1,2,8
direction4
SRC = 0 SRC = 1
64-pin 100-pin7
C[12]
PCR[44] ALT0
GPIO[44]
PPS1
PPS2
ALARM1
TRIGGER1
TRIGGER2
EIRQ[25]
SIUL
I/O
Slow
Medium
—
44
ALT1
ALT2
ALT3
—
—
—
CE_RTC
CE_RTC
CE_RTC
CE_RTC
CE_RTC
SIUL
O
O
O
I
I
I
C[13]
C[14]
C[15]
PCR[45] ALT0
GPIO[45]
—
—
—
D[1]
SIUL
—
—
—
VID
SIUL
I/O
—
—
—
I
Slow
Slow
Slow
Medium
Medium
Medium
—
—
—
46
47
48
ALT1
ALT2
ALT3
—
—
EIRQ[26]
I
PCR[46] ALT0
GPIO[46]
—
—
—
D[0]
SIUL
—
—
—
VID
SIUL
I/O
—
—
—
I
ALT1
ALT2
ALT3
—
—
EIRQ[27]
I
PCR[47] ALT0
GPI[47]
—
—
—
COL
SIUL
—
—
—
FEC
I
ALT1
ALT2
ALT3
—
—
—
—
I
Port D (100-pin package: 16-bit)
D[0]
D[1]
D[2]
D[3]
D[4]
PCR[48] ALT0
ALT1
GPIO[48]
MDO0
—
SIUL
NEXUS
—
I/O
O
—
—
Slow
Slow
Slow
Slow
Slow
Medium
Medium
Medium
Medium
Medium
—
—
—
—
—
9
ALT2
ALT3
—
—
PCR[49] ALT0
ALT1
GPIO[49]
MCK0
—
SIUL
NEXUS
—
I/O
O
—
—
14
13
72
78
ALT2
ALT3
—
—
PCR[50] ALT0
ALT1
GPIO[50]
EVTO
—
SIUL
NEXUS
—
I/O
O
—
—
ALT2
ALT3
—
—
PCR[51] ALT0
ALT1
GPIO[51]
MSEO1
—
SIUL
NEXUS
—
I/O
O
—
—
ALT2
ALT3
—
—
PCR[52] ALT0
ALT1
GPIO[52]
MSEO0
—
SIUL
NEXUS
—
I/O
O
—
—
ALT2
ALT3
—
—
MPC5604E Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
17
Package pinouts and signal descriptions
Table 4. Pin muxing (continued)
I/O
Pad speed5
Pin6
Port
pin
PCR
Alternate
Functions
Peripheral3
register function1,2,8
direction4
SRC = 0 SRC = 1
64-pin 100-pin7
D[5]
PCR[53] ALT0
ALT1
GPIO[53]
MDO3
—
SIUL
NEXUS
—
I/O
O
—
—
Slow
Slow
Slow
Slow
Medium
Medium
Medium
Medium
—
80
84
98
10
ALT2
ALT3
—
—
D[6]
D[7]
D[8]
PCR[54] ALT0
ALT1
GPIO[54]
MDO2
—
SIUL
NEXUS
—
I/O
O
—
—
—
—
—
ALT2
ALT3
—
—
PCR[55] ALT0
ALT1
GPIO[55]
MDO1
—
SIUL
NEXUS
—
I/O
—
—
—
ALT2
ALT3
—
—
PCR[56] ALT0
GPI[56]
—
—
—
EVTI
SIUL
—
—
—
NEXUS
I
ALT1
ALT2
ALT3
—
—
—
—
I
D[9]
PCR[57] ALT0
GPIO[57]
ETC[3]
ETC[2]
—
RXD
EIRQ[28]
SIUL
I/O
I/O
I/O
—
I
Slow
Medium
—
49
ALT1
ALT2
ALT3
—
ETIMER0
ETIMER0
—
CAN0
SIUL
—
I
D[10]
D[11]
D[12]
PCR[58] ALT0
ALT1
GPIO[58]
TXD
—
SIUL
CAN0
—
I/O
O
—
—
Slow
Slow
Slow
Medium
Medium
Medium
—
—
—
51
52
53
ALT2
ALT3
—
—
PCR[59] ALT0
ALT1
GPIO[59]
ETC[0]
ETC[5]
ETC[4]
SIUL
I/O
I/O
I/O
I/O
ETIMER0
ETIMER0
ETIMER0
ALT2
ALT3
PCR[60] ALT0
GPIO[60]
ETC[1]
ETC[0]
—
SIUL
I/O
I/O
I/O
—
I
ALT1
ALT2
ALT3
—
ETIMER0
ETIMER0
—
SIN
DSPI0
D[13]
PCR[61] ALT0
GPI[61]
—
—
SIUL
—
—
—
FEC
SIUL
I
Slow
Medium
—
54
ALT1
ALT2
ALT3
—
—
—
—
I
—
CRS
EIRQ[29]
—
I
MPC5604E Microcontroller Data Sheet, Rev. 6
18
NXP Semiconductors
Package pinouts and signal descriptions
Table 4. Pin muxing (continued)
I/O
Pad speed5
Pin6
Port
pin
PCR
Alternate
Functions
Peripheral3
register function1,2,8
direction4
SRC = 0 SRC = 1
64-pin 100-pin7
D[14]
PCR[62] ALT0
GPI[62]
—
—
SIUL
—
—
—
FEC
SIUL
I
Slow
Medium
—
57
ALT1
ALT2
ALT3
—
—
—
—
I
—
RX_ER
EIRQ[30]
—
I
D[15]
PCR[63] ALT0
ALT1
GPIO[63]
F[0]
—
SIUL
FCU0
—
I/O
O
—
—
Slow
Medium
—
69
ALT2
ALT3
—
—
Port E (100-pin package: 7-bit)
E[0]
E[1]
E[2]
PCR[64] ALT0
ALT1
GPIO[64]
F[1]
—
SIUL
FCU0
—
I/O
O
—
—
Slow
Slow
Slow
Medium
Medium
Medium
—
—
—
68
71
85
ALT2
ALT3
—
—
PCR[65] ALT0
ALT1
GPIO[65]
TX_ER
—
SIUL
FEC
—
I/O
O
—
—
ALT2
ALT3
—
—
PCR[66] ALT0
GPI[66]
—
—
SIUL
—
—
—
LIN1
SIUL
I
ALT1
ALT2
ALT3
—
—
—
—
I
—
RXD
EIRQ[31]
—
I
E[3]
E[4]
E[5]
E[6]
PCR[67] ALT0
ALT1
GPIO[67]
TXD
—
SIUL
LIN1
—
I/O
O
—
—
Slow
Slow
Slow
Slow
Medium
Medium
Medium
Medium
—
—
—
—
86
89
90
97
ALT2
ALT3
—
—
PCR[68] ALT0
ALT1
GPIO[68]
CS0
CS0
SIUL
I/O
I/O
I/O
I/O
DSPI0
DSPI1
DSPI2
ALT2
ALT3
CS0
PCR[69] ALT0
ALT1
GPIO[69]
SCK
SCK
SIUL
I/O
I/O
I/O
I/O
DSPI0
DSPI1
DSPI2
ALT2
ALT3
SCK
PCR[70] ALT0
GPIO[70]
SOUT
SOUT
SOUT
SIN
SIUL
I/O
O
O
O
I
ALT1
ALT2
ALT3
—
—
—
DSPI0
DSPI1
DSPI2
DSPI0
DSPI2
DSPI2
SIN
SIN
I
I
1
ALT0 is the primary (default) function for each port after reset.
MPC5604E Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
19
Package pinouts and signal descriptions
2
Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIU module. PCR.PA = 00 → ALT0;
PCR.PA = 01 → ALT1; PCR.PA = 10 → ALT2; PCR.PA = 11 → ALT3. This is intended to select the output functions; to use
one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless of the values selected in the PCR.PA bitfields.
For this reason, the value corresponding to an input only function is reported as “—”.
3
Module included on the MCU.
4
Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by setting the
values of the PSMIO.PADSELx bitfields inside the SIUL module.
5
Programmable via the SRC (Slew Rate Control) bits in the respective Pad Configuration Register.
6
Additional board pull resistors are recommended when JTAG pins are not being used on the board or application.
7
The 100-pin package is not a production package. It is used for software development only.
8
Do not use ALT multiplexing when ADC channels are used.
MPC5604E Microcontroller Data Sheet, Rev. 6
20
NXP Semiconductors
Electrical characteristics
3
Electrical characteristics
3.1
Introduction
This section contains electrical characteristics of the device as well as temperature and power considerations.
This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take
precautions to avoid application of any voltage higher than the specified maximum rated voltages.
To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (V or V ). This can be done by the
DD
SS
internal pull-up or pull-down, which is provided by the product for most general purpose pins.
The parameters listed in the following tables represent the characteristics of the device and its demands on the system.
In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller
Characteristics is included in the Symbol column.
In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol
“SR” for System Requirement is included in the Symbol column.
CAUTION
All of the following figures are indicative and must be confirmed during either silicon validation, silicon characterization or
silicon reliability trial.
3.2
Parameter classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding, the classifications listed in Table 5 are used and the parameters are tagged accordingly in the tables where
appropriate.
Table 5. Parameter classifications
Classification tag
Tag description
P
Those parameters are guaranteed during production testing on each individual device.
Those parameters are achieved by the design characterization by measuring a statistically
relevant sample size across process variations.
C
Those parameters are achieved by design characterization on a small sample size from typical
devices under typical conditions unless otherwise noted. All values shown in the typical column
are within this category.
T
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
MPC5604E Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
21
Electrical characteristics
3.3
Absolute maximum ratings
1
Table 6. Absolute Maximum Ratings
Symbol
Parameter
SR Device ground
Conditions
Min
Max2
Unit
VSS
—
VSS
VSS
V
SR 3.3 V Input/Output Supply Voltage
(supply).
VDD_HV_IO
—
—
VSS _ 0.3
VSS _ 0.1
VSS + 6.0
V
V
Code Flash supply with VDD_HV_IO3
and Data Flash with VDD_HV_IO2
SR 3.3 VInput/Output Supply Voltage
(ground).
VSS + 0.1
VSS_HV_IO
Code Flash ground with VSS_HV_IO3
and Data Flash with VSS_HV_IO2
SR 3.3 V Crystal Oscillator Amplifier
Supply voltage (supply)
The oscillator and flash supply segments are
double-bounded with the VDD_HV_IO segments. See
VDD_HV_OSC
VSS_HV_OSC
VDD_HV_ADC0
—
VDD_HV_IO and VSS_HV_IO specifications.
SR 3.3 V Crystal Oscillator Amplifier
Supply voltage (ground)
SR 3.3 V ADC_0 Supply and High
Reference voltage
VSS _ 0.3
3
—
—
—
—
—
—
—
—
—
V
SS + 6.0
V
V
SR 3.3 V ADC_0 Ground and Low
Reference voltage
VSS_HV_ADC0
VDD_HV_REG
TVDD
VSS _ 0.1
VSS _ 0.3
VSS + 0.1
SR 3.3 V Voltage Regulator Supply
voltage
VSS + 6.0
V
SR Slope characteristics on all VDD
during power up4
—
0.1
V/us
V
SR 1.2 V supply pins for core logic
(supply)
VSS _ 0.3
VDD_LV_COR
VSS_LV_COR
VIN
VSS + 1.4
VSS + 0.1
DD_HV_IO +0.5
10
SR 1.2 V supply pins for core logic
(ground)
VSS _ 0.1
V
SR Voltage on any pin with respect to
V
SS_HV_IO _ 0.3
V
V
ground (VSS_HV_IO
)
SR Input current on any pin during
overload condition
IINJPAD
–10
–50
mA
mA
SR Absolute sum of all input currents
during overload condition
IINJSUM
50
TSTORAGE
TJ
SR Storage temperature
—
—
–55
–40
–40
150
150
125
°C
°C
°C
SR Junction temperature under bias
SR Ambient temperature under bias
fCPU<64 MHz
fCPU<64 MHz
Video use
case with
TA
–40
105
°C
internal supply
1
Functional operating conditions are given in the DC electrical characteristics. Absolute maximum ratings are stress
ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect
device reliability or cause permanent damage to the device.
MPC5604E Microcontroller Data Sheet, Rev. 6
22
NXP Semiconductors
Electrical characteristics
Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device
2
3
4
stress have not yet been determined.
MPC5604E’s I/O, flash, and oscillator circuit supplies are interconnected. The ADC supply managed independently
from other supplies.
Guaranteed by device validation.
3.4
Recommended operating conditions
Table 7. Recommended operating conditions
Symbol
Parameter
Conditions
Min
Max1
Unit
VSS
SR Device ground
—
—
—
VSS
3.0
0
VSS
3.6
0
V
V
V
VDD_HV_IO
VSS_HV_IO
SR 3.3 V input/output supply voltage
SR Input/output ground voltage
SR 3.3 V Crystal Oscillator Amplifier Supply
voltage (supply)
The oscillator and flash supply segments
are double-bounded with the VDD_HV_IOx
segments. See VDD_HV_IOx and
VSS_HV_IOx specifications.
VDD_HV_OSC
VSS_HV_OSC
—
SR 3.3 V Crystal Oscillator Amplifier Supply
voltage (ground)
SR 3.3 V ADC_0 Supply and High Reference
voltage
2
VDD_HV_ADC0
—
3.0
3.6
V
VDD_HV_REG
SR 3.3 V voltage regulator supply voltage
—
—
—
—
—
—
—
3.0
1.15
—
3.6
1.32
—
V
V
VDD_LV_EXTCOR SR Externally supplied core voltage
VDD_LV_REGCOR SR Internal supply voltage
VSS_LV_REGCOR SR Internal reference voltage
V
0
0
V
VDD_LV_COR
VSS_LV_COR
VSS_HV_ADC0
TJ
SR Internal supply voltage
—
—
V
SR Internal reference voltage
0
0
V
SR Ground and Low Reference voltage
SR Junction temperature under bias
SR Ambient temperature under bias
0
0
V
–40
–40
150
125
°C
°C
fCPU<64 MHz
f
CPU<64 MHz
TA
Video use case
with internal
supply
–40
105
°C
1
2
Full functionality cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical characteristics
and I/Os DC electrical specification may not be guaranteed.
MPC5604E’s I/O, flash, and oscillator circuit supplies are interconnected. The ADC supply managed independently
from other supplies.
MPC5604E Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
23
Electrical characteristics
3.5
Thermal characteristics
1
Table 8. Thermal characteristics for 100-pin LQFP
Typical
value
Symbol
Parameter
Conditions
Unit
Thermal resistance junction-to-ambient,
natural convection2
Single layer board—1s
Four layer board—2s2p
51
38
°C/W
°C/W
RθJA
Thermal resistance junction-to-ambient2
@ 200 ft./min.3, single layer
board—1s
41
32
°C/W
°C/W
RθJMA
@ 200 ft./min.3, four layer
board—2s2p
RθJB
Thermal resistance junction to board4
—
—
—
23
11
2
°C/W
°C/W
°C/W
RθJCtop Thermal resistance junction to case (top)5
ΨJT
Junction to package top natural convection6
1
2
Thermal characteristics are targets based on simulation that are subject to change per device
characterization.
Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test
board meets JEDEC specification for this package.
3
4
Flow rate of forced air flow.
Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package.
5
6
Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the interface
layer.
Thermal characterization parameter indicating the temperature difference between the package top and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal
characterization parameter is written as Psi-JT.
1
Table 9. Thermal characteristics for 64-pin LQFP
Typical
value
Symbol
Parameter
Conditions
Unit
Thermal resistance junction-to-ambient,
natural convection2
Single layer board—1s
Four layer board—2s2p
64
45
°C/W
°C/W
RθJA
Thermal resistance junction-to-ambient2
@ 200 ft./min.3, single layer
board—1s
52
39
°C/W
°C/W
RθJMA
@ 200 ft./min.3, four layer
board—2s2p
RθJB
Thermal resistance junction to board4
—
—
—
28
14
3
°C/W
°C/W
°C/W
RθJCtop Thermal resistance junction to case (top)5
ΨJT
Junction to package top natural convection6
1
2
Thermal characteristics are targets based on simulation that are subject to change per device
characterization.
Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test
board meets JEDEC specification for this package.
MPC5604E Microcontroller Data Sheet, Rev. 6
24
NXP Semiconductors
Electrical characteristics
3
4
Flow rate of forced air flow.
Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package.
5
6
Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the interface
layer.
Thermal characterization parameter indicating the temperature difference between the package top and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal
characterization parameter is written as Psi-JT.
3.5.1
General notes for specifications at maximum junction temperature
An estimation of the chip junction temperature, T , can be obtained from Equation 1:
J
T = T + (R
* P )
Eqn. 1
J
A
θJA
D
where:
T
= ambient temperature for the package (°C)
A
R
= junction to ambient thermal resistance (°C/W)
= power dissipation in the package (W)
θJA
P
D
The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal
performance. There are two values in common usage: the value determined on a single layer board and the value obtained on a
board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is closer
to the application depends on the power dissipated by other components on the board. The value obtained on a single layer board
is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually
appropriate if the board has low power dissipation and the components are well separated.
When a heat sink is used, the thermal resistance is expressed in Equation 2 as the sum of a junction to case thermal resistance
and a case to ambient thermal resistance:
R
= R
+ R
θCA
Eqn. 2
θJA
θJC
where:
R
R
R
= junction to ambient thermal resistance (°C/W)
= junction to case thermal resistance (°C/W)
= case to ambient thermal resistance (°C/W)
θJA
θJC
θCA
R
is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to
θJC
ambient thermal resistance, R
. For instance, the user can change the size of the heat sink, the air flow around the device, the
θCA
interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit
board surrounding the device.
To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal
Characterization Parameter (Ψ ) can be used to determine the junction temperature with a measurement of the temperature at
JT
the top center of the package case using Equation 3:
T = T + (Ψ x P )
Eqn. 3
J
T
JT
D
where:
T
= thermocouple temperature on top of the package (°C)
= thermal characterization parameter (°C/W)
= power dissipation in the package (W)
T
Ψ
JT
P
D
MPC5604E Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
25
Electrical characteristics
The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied
to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the
package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the
junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects
of the thermocouple wire.
References:
Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134
(408) 943-6900
U.S.A.
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or
303-397-7956.
JEDEC specifications are available on the WEB at http://www.jedec.org.
1. C.E. Triplett and B. Joiner, An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller
Module, Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.
2. G. Kromann, S. Shidore, and S. Addison, Thermal Modeling of a PBGA for Air-Cooled Applications, Electronic
Packaging and Production, pp. 53-58, March 1998.
3. B. Joiner and V. Adams, Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in
Thermal Modeling, Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.
3.6
Electromagnetic Interference (EMI) characteristics
1
Table 10. EMI Testing Specifications
Frequency
Range
Level
(Typ)
Symbol
Parameter
Conditions
VDD = 3.3 V
Clocks
Unit
Radiated
emissions
VEME
Oscillator Frequency = 8 150 kHz–50 MHz
2
14
11
7
TA = +25 °C
MHz;
50–150 MHz
System Bus Frequency =
dBμV
Device
64 MHz;
150–500 MHz
500–1000 MHz
Configuration, test
conditions and EM
testing per standard
IEC61967-2.
CPU Freq = 64MHZ
No PLL Frequency
Modulation
IEC Level
M
ExternalOscillatorFreq= 150 kHz–50 MHz
1
11
7
8 MHz
System Bus Freq = 64
50–150 MHz
dBμV
MHz
150–500 MHz
500–1000 MHz
CPU Freq = 64MHZ
1
2% PLL Freq Modulation
IEC Level
N
1
EMI testing and I/O port waveforms per standard IEC61967-2.
MPC5604E Microcontroller Data Sheet, Rev. 6
26
NXP Semiconductors
Electrical characteristics
3.7
Electrostatic Discharge (ESD) characteristics
1,2
Table 11. ESD ratings
Symbol
Parameter
Conditions
Value
Unit
VESD(HBM)
SR Electrostatic discharge (Human Body Model)
—
2000
V
Electrostatic discharge (Charged Device Model)
SR
750 (corners)
500 (other)
VESD(CDM)
—
V
1
2
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated
Circuits.
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification requirements. Complete DC parametric and functional testing shall be performed per applicable
device specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification
3.8
Power management electrical characteristics
Power Management Overview
3.8.1
The device supports the following power modes:
•
•
Internal voltage regulation mode
External voltage regulation mode
3.8.1.1
Internal voltage regulation mode
In this mode, the following supplies are involved:
•
V
(3.3V) — This is the main supply provided externally.
DD_HV_IO
MPC5604E Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
27
Electrical characteristics
(1.2V) — This is the core logic supply. In the internal regulation mode, the core supply is derived from
•
V
DD_LV_COR
the main supply via an on-chip linear regulator driving an internal PMOS ballast transistor. The PMOS ballast
transistors are located in the pad ring and their source connectors are directly bonded to a dedicated pin. See Figure 4.
Pads Pins
Vss_HV_IO0_X
3.3V
Vdd_HV_IO0_X
Vdd_HV_S_Ballast0/1
POR_B
Vreg
LVD
Vdd_LV_REGCOR0
1.2V
Vdd_LV_COR0_X
(3 supply pairs)
Vss_LV_COR0_X
Figure 4. Internal Regulation Mode
The core supply can also be provided externally. Table 12 shows how to connect V
external core supply mode.
pin for internal and
DD_HV_S_BALLAST
NOTE
V
pin is the supply pin, which carries the entire core logic current in the
DD_HV_S_BALLAST
internal regulation mode, while in external regulation mode it is used as a signal to bypass
the regulator.
Table 12. Core Supply Select
Mode
VDD_HV_S_Ballast
VDD_HV_IO (3.3V)
Internal supply mode (via internal PMOS ballast
transistors)
External supply mode (e.g., via external switched
regulator)
VDD_LV_COR (1.2V)
MPC5604E Microcontroller Data Sheet, Rev. 6
28
NXP Semiconductors
Electrical characteristics
3.8.1.2
External voltage regulation mode
In the external regulation mode, the core supply is provided externally using a switched regulator. This saves on-chip power
consumption by avoiding the voltage drop over the ballast transistor. The external supply mode is selected via a board level
supply change at the V
pin.
DD_HV_S_BALLAST
Pads Pins
Vss_HV_IO0_X
Vdd_HV_IO0_X
3.3V
Power
Vdd_HV_S_Ballast0/1
1.2V
Supply, e.g.,
switched or
linear
(1.15V-1.32V)
POR_B
Vreg
relaxed
LVD
Vdd_LV_REGCOR0
1.2V
Vdd_LV_COR0_X
(3 supply pairs)
Vss_LV_COR0_X
Figure 5. External Regulation Mode
NOTE
"In external regulation mode, POR_B pin should be used to control the power on RESET for
the device. POR_B should be kept low (asserted) as long as the input supplies are unstable
or below the specified operating range. Failure to do so may lead to unexpected device
operation and erratic reset recovery"
1
3.8.1.3
Recommended power supply sequencing
For MPC5604E, the external supplies need to be maintained as per the following relations:
•
•
•
V
V
V
should be always greater or equal to V
DD_HV_IO
DD_HV_IO
DD_HV_IO
DD_HV_S_Ballast
DD_LV_COR0_X
DD_HV_ADC
should be always greater than V
should be always greater than V
1.Investigations are in process to relax power supply sequencing recommendation.
MPC5604E Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
29
Electrical characteristics
3.8.2
Voltage regulator electrical characteristics
\
C
(LV_COR/LV_CFLA)
600 nF
REG2
GND
V
DD_HV_IO
V
V
V
DD_LV_COR0_2
SS_LV_COR0_2
DD_HV_S_BALLAST0
-
V
REF
V
DD_HV_S_BALLAST1
+
V
DD_LV_COR0_3
DEVICE
V
DD_LV_COR0_0
Voltage Regulator
I
V
SS_HV_IO
GND
DEVICE
V
V
C
V
SS_LV_COR0_0
V
SS_HV_IO
SS_LV_COR0_1
600 nF
DD_HV_IO
V
DD_LV_COR0_1
GND
GND
C
(supply/IO decoupling)
(LV_COR/LV_PLL)
DEC2
REG3
Figure 6. Voltage regulator capacitance connection
Table 13. Voltage regulator electrical characteristics
Value
Typ
Symbol
C
Parameter
Conditions1
Unit
Min
Max
Internal voltage regulator external
capacitance
2
CREGn
SR —
SR —
—
—
200
—
—
600
nF
Stability capacitor equivalent serial
resistance
RREG
CDEC1
CDEC2
0.05
0.2
Ω
Decoupling capacitance3 ballast
—
—
1004
400
—
—
SR —
SR —
4705
nF
—
Decoupling capacitance regulator
supply
1 μF
—
100 nF
—
Main regulator output voltage
Before exiting from
reset
T
—
1.15
—
1.32
1.28
—
—
VMREG
CC
V
P
After trimming
—
1.32
150
Main regulator current provided to
VDD_LV domain
IMREG
SR —
mA
MPC5604E Microcontroller Data Sheet, Rev. 6
30
NXP Semiconductors
Electrical characteristics
Table 13. Voltage regulator electrical characteristics (continued)
Value
Typ
Symbol
C
Parameter
Conditions1
Unit
Min
Max
Main regulator module current
consumption
IMREG = 200 mA
IMREG = 0 mA
—
—
—
—
2
1
IMREGINT CC D
mA
mA
In-rush current on VDD_BV during
power-up6
IDD_BV
CC D
—
—
—
407
1
2
3
VDD = 3.3 V 10%, TA = −40 to 125 °C, unless otherwise specified
It is required by the device in internal voltage regulation mode only.
This capacitance value is driven by the constraints of the external voltage regulator that supplies the VDD_BV
voltage. A typical value is in the range of 470 nF. This capacitance should be placed close to the device pin.
4
5
This value is acceptable to guarantee operation from 3.0 V to 3.6 V
External regulator and capacitance circuitry must be capable of providing IDD_BV while maintaining supply VDD_BV
in operating range.
6
7
In-rush current is seen only for short time during power-up and on standby exit (max 20 µs, depending on external
LV capacitances to be load)
The duration of the in-rush current depends on the capacitance placed on LV pins. BV decaps must be sized
accordingly. Refer to IMREG value for minimum amount of current to be provided in cc.
3.8.3
Voltage monitor electrical characteristics
The device implements a POR module to ensure correct power-up initialization, as well as three low voltage detectors to
monitor the V and the V voltage while device is supplied:
DD_HV
DD_LV
•
•
•
POR monitors V
during the power-up phase to ensure device is maintained in a safe reset state
DD_HV
LVDHV3 monitors V
to ensure device reset below minimum functional supply
DD_HV
LVDLVCOR monitors low voltage digital power domain
Table 14. Low voltage monitor electrical characteristics
Value
Symbol
Parameter
Conditions1
Unit
Min
Max
VPORH
T
D
P
P
P
P
Power-on reset threshold
—
1.5
1.0
2.7
—
V
V
V
V
V
V
VPORUP
Supply for functional POR module
TA = 25°C
VDDHVLVDMOK_H
VDDHVLVDMOK_L
VMLVDDOK_H
VMLVDDOK_L
VDD_HV low voltage detector high threshold
VDD_HV low voltage detector low threshold
Digital supply low voltage detector high
Digital supply low voltage detector low
—
—
—
—
—
2.95
—
2.6
—
1.135
—
1.095
1
VDD_HV = 3.3V 10% TA = –40 °C to TA MAX, unless otherwise specified
3.9
Power Up/Down reset sequencing
The MPC5604E implements a precise sequence to ensure each module is started only when all conditions for switching it ON
are available. This prevents overstress event or miss-functionality within and outside the device:
MPC5604E Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
31
Electrical characteristics
•
A POR module working on voltage regulator supply is controlling the correct start-up of the regulator. This is a key
module ensuring safe configuration for all Voltage regulator functionality when supply is below 1.5 V. Associated POR
(or POR) signal is active low.
•
•
Several Low Voltage Detectors, working on voltage regulator supply are monitoring the voltage of the critical modules
(Voltage regulator, I/Os, Flash and Low voltage domain). LVDs are gated low when POWER_ON is active.
A POWER_OK signal is generated when all critical supplies monitored by the LVD are available. This signal is active
high and released to all modules including I/Os, Flash and RC16 oscillator needed during power-up phase and reset
phase. When POWER_OK is low the associated module are set into a safe state.
VLVDHV3H
VPORH
3.3V
VDD_HV_REG
VPOR_UP
0V
3.3V
POWER_ON
LVDM (HV)
0V
3.3V
0V
VMLVDOK_H
VDD_LV_REGCOR
1.2V
0V
3.3V
LVDD (LV)
0V
3.3V
POWER_OK
0V
RC16MHz Oscillator
1.2V
0V
~1us
1.2V
0V
Internal Reset Generation Module
FSM
P0
P1
Figure 7. Power-up typical sequence
VLVDHV3L
3.3V
VPORH
VDD_HV_REG
0V
3.3V
LVDM (HV)
POWER_ON
0V
3.3V
0V
1.2V
0V
VDD_LV_REGCOR
LVDD (LV)
3.3V
0V
3.3V
POWER_OK
0V
RC16MHz Oscillator
1.2V
0V
Internal Reset Generation Module
FSM
1.2V
0V
IDLE
P0
Figure 8. Power-down typical sequence
MPC5604E Microcontroller Data Sheet, Rev. 6
32
NXP Semiconductors
Electrical characteristics
3.10 DC electrical characteristics
Table 15 gives the DC electrical characteristics at 3.3 V (3.0 V < V
< 3.6 V).
DD_HV_IO
1
Table 15. DC electrical characteristics (3.3 V)
Symbol
Parameter
Conditions
Min
Max
Unit
VIL
VIL
VIH
D
P
P
Minimum low level input voltage
Maximum low level input voltage
Minimum high level input voltage
—
—
—
–0.42
—
—
0.35 VDD_HV_IO
—
V
V
V
0.65 VDD_HV_IO
—
Maximum high level input
voltage
VIH
D
—
V
DD_HV_IO + 0.42
V
VHYS
VOL_S
VOH_S
VOL_M
T
P
P
P
Schmitt trigger hysteresis
—
0.1 VDD_HV_IO
—
V
V
V
V
Slow, low level output voltage
Slow, high level output voltage
Medium, low level output voltage
IOL = 2 mA
IOH = –2 mA
IOL = 2 mA
—
0.8VDD_HV_IO
—
0.1VDD_HV_IO
—
0.1VDD_HV_IO
Medium, high level output
voltage
VOH_M
P
IOH = –3 mA
0.8VDD_HV_IO
—
V
VOL_F
VOH_F
IPU
P
P
P
P
Fast, high level output voltage
Fast, high level output voltage
Equivalent pull-up current
IOL = 11 mA
IOH = –11 mA
VIN = VIL
—
0.8VDD_HV_IO
–95
0.1VDD_HV_IO
V
V
—
—
95
µA
IPD
Equivalent pull-down current
VIN = VIH
—
Input leakage current
(all bidirectional ports)
TA = –40 to
125 °C
IIL
P
P
D
P
P
D
—
1
µA
µA
V
Input leakage current
(all ADC input-only ports)
TA = –40 to
125 °C
IIL
—
0.5
Minimum RESET, low level input
voltage
VILR
VILR
VIHR
VIHR
—
—
—
—
—
–0.42
—
—
Maximum RESET, low level
input voltage
0.35 VDD_HV_IO
V
Minimum RESET, high level
input voltage
0.65 VDD_HV_IO
—
—
VDD_HV_IO + 0.42
—
V
Maximum RESET, high level
input voltage
V
RESET, Schmitt trigger
hysteresis
VHYSR
VOLR
IPU
CIN
D
D
0.1 VDD_HV_IO
V
V
RESET, low level output voltage IOL = 0.5 mA
—
–130
—
0.1VDD_HV_IO
RESET, equivalent pull-up
current
VIN = VIL
VIN = VIH
—
—
–10
10
D
µA
pF
D
Input capacitance
—
1
2
These specifications are design targets and subject to change per device characterization.
“SR” parameter values must not exceed the absolute maximum ratings shown in Table 6.
MPC5604E Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
33
Electrical characteristics
Symbol
Table 16. Supply current
Conditions
Value1
Typ
Parameter
Unit
Min
Max
I
RUN Mode, I/O currents not included,
worst case over temperature for
system clock
DD_LV_CORE
C
P
—
75
120
HALT Mode2
V
DD_LV_CORx
—
—
4
4
25
25
externally forced at 1.3 V
V
STOP Mode3
DD_LV_CORx
P
externally forced at 1.3 V
IDD_FLASH
Code Flash
FLASH supply current
during read
VDD_HV_IO at 3.3 V
—
—
4
9
7
FLASH supply current
during erase operation
on 1 Flash module
VDD_HV_IO at 3.3 V
Supply
current
14
mA
C
Data Flash
DD_HV_IO at 3.3 V
FLASH supply current
during read
V
—
—
3.5
7.5
6
FLASH supply current
during erase operation
on 1 Flash module
VDD_HV_IO at 3.3 V
12
IDD_ADC
ADC supply current
VDD_HV_ADC0 at 3.3 V
ADC Freq = 16MHz
C
—
—
1.8
3
4
I
OSC supply current
VDD_HV_OSC at 3.3 V
16 MHz
DD_OSC
C
0.74
1
All values to be confirmed after characterization/data collection.
2
Halt mode configurations: Code fetched from SRAM, Code Flash and Data Flash in low power mode, OSC/PLL0 are OFF, Core
clock frozen, all peripherals are disabled.
3
STOP "P" mode DUT configuration: Code fetched from SRAM, Code Flash and Data Flash off, OSC/PLL0 are OFF, Core clock
frozen, all peripherals are disabled.
3.11 Main oscillator electrical characteristics
The MPC5604E provides an oscillator/resonator driver.
Table 17. Main oscillator electrical characteristics
Symbol
fOSC SR Oscillator frequency
gm
VOSC
tOSCSU
Parameter
Min
Max
Unit
4
4
40
MHz
P
T
T
Transconductance
15.846 mA/V
Oscillation amplitude on XTAL pin
Start-up time1,2
1.3
—
2.25
5
V
ms
MPC5604E Microcontroller Data Sheet, Rev. 6
34
NXP Semiconductors
Electrical characteristics
1
2
The start-up time is dependent upon crystal characteristics, board leakage, etc., high ESR and excessive capacitive
loads can cause long start-up time.
Value captured when amplitude reaches 90% of XTAL
Table 18. Input clock characteristics
Symbol
fOSC SR Oscillator frequency
Parameter
Min
Typ
Max
Unit
4
—
—
—
—
50
40
100
1
MHz
MHz
ns
fCLK
trCLK
tDC
SR Frequency in bypass
SR Rise/fall time in bypass
SR Duty cycle
—
47.5
52.5
%
3.12 FMPLL electrical characteristics
1
Table 19. PLLMRFM electrical specifications
(V
= 3.0 V to 3.6 V, V = V
= 0 V, T = T to T )
DDPLL
SS
SSPLL
A
L
H
Value
Symbol
Parameter
Conditions
Unit
Min
Max
fref_crystal
fref_ext
PLL reference frequency range2
Crystal reference
—
D
D
D
D
4
40
MHz
MHz
MHz
MHz
Phase detector input frequency range
(after pre-divider)
fpll_in
4
4
4
16
fFMPLL_0
Clock frequency range in normal
mode
—
—
128
256
PCS
fFMPLL_0
PLL output frequency
_CLK
fVCO
fsys
P
D
D
VCO frequency
—
—
—
—
256
16
512
64
MHz
MHz
ns
On-chip PLL frequency2
System clock period
tCYC
1 / fsys
Self-clocked mode frequency
fSCM
D
20
-500
-6
150
500
6
MHz
ps
(VCO free running frequency)3,4
CLKOUT
period
Peak-to-peak (clock
edge to clock edge)
fSYS Maximum
CLKOU
TJITTER
T
jitter5,6,7,8
Long-term jitter (avg.
over 2 ms interval)
ns
tlpll
tdc
D
D
D
PLL lock time 9, 10
—
—
—
—
40
–6
200
60
6
μs
Duty cycle of reference
Frequency LOCK range
%
fLCK
% fsys
MPC5604E Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
35
Electrical characteristics
1
Table 19. PLLMRFM electrical specifications
(V
= 3.0 V to 3.6 V, V = V
= 0 V, T = T to T ) (continued)
DDPLL
SS
SSPLL
A
Conditions
—
L
H
Value
Symbol
Parameter
Unit
Min
Max
fUL
D
D
D
Frequency un-LOCK range
Modulation Depth
–18
0.25
–0.5
—
18
% fsys
%fsys
kHz
Center spread
Down Spread
—
4.011
–8.0
100
fCS
fDS
fMOD
Modulation frequency12
1
2
3
4
5
6
All values given are initial design targets and subject to change.
Considering operation with PLL not bypassed.
Self clocked mode frequency is the frequency that the PLL operates at when the PLL reference frequency falls.
fscm represents PLL0 VCO frequency in free running (when the PLL reference clock is disconnected).
This value is determined by the crystal manufacturer and board design.
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum
fSYS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock
signal. Noise injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency
increase the CJITTER percentage for a given interval.
7
8
Proper PC board layout procedures must be followed to achieve specifications.
Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of CJITTER and
either fCS or fDS (depending on whether center spread or down spread modulation is enabled).
9
This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for
this PLL, load capacitors should not exceed these limits.
10 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits
in the synthesizer control register (SYNCR).
11 This value is true when operating at frequencies above 60 MHz, otherwise fCS is 2% (above 64 MHz).
12 Modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50 kHz.
3.13 16 MHz RC oscillator electrical characteristics
Table 20. 16 MHz RC oscillator electrical characteristics
Symbol
Parameter
Conditions
Min
Typ
Max Unit
fRC
C
P
RC oscillator frequency
TA = 25 °C
8.5
16
24
MHz
Fast internal RC oscillator variation in
temperature and supply with respect to
fRC at TA = 55 °C in high-frequency
configuration
ΔRCMVAR
ΔRCMTRIM
—
–5
—
5
%
Post Trim Accuracy: The variation of the
PTF1 from the 16 MHz oscillator
T
TA = 25 °C
–2
—
2
%
1
PTF = Post Trimming Frequency: The frequency of the output clock after trimming at typical supply voltage and
temperature
MPC5604E Microcontroller Data Sheet, Rev. 6
36
NXP Semiconductors
Electrical characteristics
3.14 Analog-to-Digital Converter (ADC) electrical characteristics
The device provides a 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter.
Offset Error OSE
Gain Error GE
1023
1022
1021
1020
1019
1 LSB ideal = V
/ 1024
DD_ADC
1018
(2)
code out
7
(1)
6
5
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(5)
(3) Differential non-linearity error (DNL)
(4) Integral non-linearity error (INL)
(5) Center of a step of the actual transfer curve
4
3
(4)
(3)
2
1
1 LSB (ideal)
0
1
2
3
4
5
6
7
1017 1018 1019 1020 1021 1022 1023
(LSB
V
)
ideal
in(A)
Offset Error OSE
Figure 9. ADC characteristics and error definitions
3.14.1 Input impedance and ADC accuracy
To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor
with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as
possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; further, it sources charge
during the sampling phase, when the analog signal source is a high-impedance source.
A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC
filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to
MPC5604E Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
37
Electrical characteristics
be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal
(bandwidth) and the equivalent input impedance of the ADC itself.
In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: C being
S
substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path
to ground. For instance, assuming a conversion rate of 1 MHz, with C equal to 3 pF, a resistance of 330 kΩ is obtained (R
S
EQ
= 1 / (fc×C ), where fc represents the conversion rate at the considered channel). To minimize the error induced by the voltage
S
partitioning between this resistance (sampled voltage on C ) and the sum of R + R + R + R + R , the external circuit
S
S
F
L
SW
AD
must be designed to respect the Equation 4:
R + R + R + R
+ R
S
F
L
SW
AD
1
2
--------------------------------------------------------------------------
V •
< -- LSB
Eqn. 4
A
R
EQ
Equation 4 generates a constraint for external network design, in particular on resistive path. Internal switch resistances (R
SW
and R ) can be neglected with respect to external resistances.
AD
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
V
DD
Channel
Sampling
Selection
Source
Filter
Current Limiter
R
R
R
R
R
AD
S
F
L
SW1
V
C
C
C
P2
A
F
P1
R
Source Impedance
Filter Resistance
Filter Capacitance
Current Limiter Resistance
Channel Selection Switch Impedance
Sampling Switch Impedance
Pin Capacitance (two contributions, C and C
P1
Sampling Capacitance
S
F
F
L
R
C
R
R
R
C
C
SW1
AD
P
)
P2
S
Figure 10. Input equivalent circuit
A second aspect involving the capacitance network shall be considered. Assuming the three capacitances C , C and C are
F
P1
P2
initially charged at the source voltage V (refer to the equivalent circuit reported in Figure 10): A charge sharing phenomenon
A
is installed when the sampling phase is started (A/D switch close).
MPC5604E Microcontroller Data Sheet, Rev. 6
38
NXP Semiconductors
Electrical characteristics
Voltage Transient on CS
V
CS
V
A
ΔV < 0.5 LSB
V
A2
1
2
τ1 < (RSW + RAD) CS << TS
V
A1
τ2 = RL (CS + CP1 + CP2)
T
t
S
Figure 11. Transient behavior during sampling phase
In particular two different transient periods can be distinguished:
•
A first and quick charge transfer from the internal capacitance C and C to the sampling capacitance C occurs (C
P1 P2 S S
is supposed initially completely discharged): considering a worst case (since the time constant in reality would be
faster) in which C is reported in parallel to C (call C = C + C ), the two capacitances C and C are in series,
P2
P1
P
P1
P2
P
S
and the time constant is
C • C
P
S
--------------------
τ
= (R
+ R
) •
Eqn. 5
1
SW
AD
C + C
P
S
Equation 5 can again be simplified considering only C as an additional worst condition. In reality, the transient is
S
faster, but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time T
is always much longer than the internal time constant:
S
τ
< (R
+ R
) • C « T
S
Eqn. 6
1
SW
AD
S
The charge of C and C is redistributed also on C , determining a new value of the voltage V on the capacitance
P1
P2
S
A1
according to Equation 7:
V
• (C + C + C ) = V • (C + C )
P2
Eqn. 7
A1
S
P1
P2
A
P1
•
A second charge transfer involves also C (that is typically bigger than the on-chip capacitance) through the resistance
F
R : again considering the worst case in which C and C were in parallel to C (since the time constant in reality
L
P2
S
P1
would be faster), the time constant is:
τ
< R • (C + C + C )
P1 P2
Eqn. 8
2
L
S
In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed
well before the end of sampling time T , a constraints on R sizing is obtained:
S
L
10 • τ = 10 • R • (C + C + C ) < T
P1 P2 S
Eqn. 9
2
L
S
MPC5604E Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
39
Electrical characteristics
Of course, R shall be sized also according to the current limitation constraints, in combination with R (source
L
S
impedance) and R (filter resistance). Being C definitively bigger than C , C and C , then the final voltage V
F
F
P1 P2
S
A2
(at the end of the charge transfer transient) will be much higher than V . Equation 10 must be respected (charge
A1
balance assuming now C already charged at V ):
S
A1
V
• (C + C + C + C ) = V • C + V • (C + C + C )
P1 P2 A1 P1 P2
Eqn. 10
A2
S
F
A
F
S
The two transients above are not influenced by the voltage source that, due to the presence of the R C filter, is not able to
F
F
provide the extra charge to compensate the voltage drop on C with respect to the ideal source V ; the time constant R C of
S
A
F F
the filter is very high with respect to the sampling time (T ). The filter is typically designed to act as anti-aliasing.
S
Analog Source Bandwidth (V )
A
T
f
≤ 2 R C (Conversion Rate vs. Filter Pole)
F F
C
Noise
= f (Anti-aliasing Filtering Condition)
F
0
2 f ≤ f (Nyquist)
0
C
f
0
f
Anti-Aliasing Filter (f = RC Filter pole)
Sampled Signal Spectrum (f = conversion Rate)
C
F
f
f
f
C
F
0
f
f
Figure 12. Spectral representation of input signal
Calling f the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, f ),
0
F
according to the Nyquist theorem the conversion rate f must be at least 2f ; it means that the constant time of the filter is greater
C
0
than or at least equal to twice the conversion period (T ). Again the conversion period T is longer than the sampling time T ,
C
C
S
which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a
specific channel): in conclusion it is evident that the time constant of the filter R C is definitively much higher than the
F
F
sampling time T , so the charge level on C cannot be modified by the analog signal source during the time in which the
S
S
sampling switch is closed.
The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage
drop on C ; from the two charge balance equations above, it is simple to derive Equation 11 between the ideal and real sampled
S
voltage on C :
S
V
C
+ C + C
P2
----------- = -------------------------------------------------------
A
P1
F
Eqn. 11
V
C
+ C + C + C
A2
P1
P2 S
F
From this formula, in the worst case (when V is maximum, that is for instance 5 V), assuming to accept a maximum error of
A
half a count, a constraint is evident on C value:
F
C
> 2048 • C
Eqn. 12
F
S
MPC5604E Microcontroller Data Sheet, Rev. 6
40
NXP Semiconductors
Electrical characteristics
3.14.2 ADC conversion characteristics
Table 21. ADC conversion characteristics
Value
Symbol
Parameter
Conditions1
Unit
Min
Typ
Max
ADC clock frequency
(depends on ADC
fCK
SR configuration)
—
—
1
—
64
MHz
(The duty cycle depends on
ADCClk2 frequency)
fs
SR Sampling frequency
Sample time3
—
—
—
1.53
—
MHz
ns
fADC = 20 MHz,
500
ADC_conf_sample_input = 17
tADC_S
D
fADC = 9 MHz,
—
500
—
—
—
—
28.2
—
µs
ns
pF
INPSAMP = 255
Conversion time4
P
fADC = 20 MHz5,
ADC_conf_comp = 3
tADC_C
ADC input sampling
capacitance
6
CS
D
—
2.5
6
CP1
D
D
ADC input pin capacitance 1
ADC input pin capacitance 2
—
—
—
—
—
—
0.87
1
pF
pF
6
CP2
Internal resistance of analog
source
6
RSW1
D
D
—
—
—
—
—
—
0.6
2
kΩ
kΩ
Internal resistance of analog
source
6
RAD
Input current injection
Current injection on one ADC input,
different from the converted one.
Remains within TUE specification
IINJ
T
–5
—
5
mA
INL
DNL
OFS
GNE
P
P
T
T
Integral Non Linearity
Differential Non Linearity
Offset error
No overload
–1.5
–1.0
—
—
—
1
1.5
1.0
—
LSB
LSB
LSB
LSB
No overload
—
—
Gain error
—
1
—
Total unadjusted error
without current injection
TUE
P
—
—
–3
–3
—
—
3
3
LSB
LSB
Total unadjusted error with
current injection
TUE
TUE
T
P
Total unadjusted error
—
–3
-2
—
—
3
2
LSB
LSB
Total Unadjusted Error for
precise channels, input only
pins
No overload
TUEP CC
TUEX CC
overload conditions on adjacent
channel
—
-3
—
—
—
—
—
3
LSB
LSB
LSB
Total Unadjusted Error for
extended channel,
No overload
overload conditions on adjacent
channel
—
MPC5604E Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
41
Electrical characteristics
1
VDD = 3.3 V to 3.6 V, TA = –40 to +125 °C, unless otherwise specified and analog input voltage from VAGND to VAREF
.
2
3
ADCClk clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC.
During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC_S. After the
end of the sample time tADC_S, changes of the analog input voltage have no effect on the conversion result. Values
for the sample clock tADC_S depend on programming.
4
This parameter does not include the sample time tADC_S, but only the time for determining the digital result and the
time to load the result register with the conversion result.
5
6
7
20 MHz ADC clock. Specific prescaler is programmed on MC_PLL_CLK to provide 20 MHz clock to the ADC.
See Figure 10.
Does not include packaging and bonding capacitances
3.15 Temperature sensor electrical characteristics
Table 22. Temperature sensor electrical characteristics
Value
Symbol
C
Parameter
Conditions
Unit
min
typical
max
Temperature
monitoring range
—
CC
C
—
—
–40
—
150
°C
—
—
—
CC C Sensitivity
CC C Accuracy
—
5.14
—
—
10
10
mV/°C
°C
TJ = –40 to 25 °C
TJ = –25 to 125 °C
–10
–10
CC
C
—
°C
3.16 Flash memory electrical characteristics
1
Table 23. Code flash program and erase specifications
Initial
Typical
Value2
(0 Cycles)
Max4
(100000 Unit
Cycles)
Max3
(100
Symbol
Parameter
Min Value
Cycles)
TDWPRG
TBKPRG
TER8K
Double Word Program5
—
—
—
—
—
—
—
—
—
—
22
1.45
0.2
0.3
0.3
0.6
0.8
4.8
—
50
1.65
0.4
0.5
0.6
0.9
1.3
7.6
10
500
33
μs
s
Bank Program (512 KB)5, 6
Sector Erase (8KB)
5.0
5.0
5.0
5.0
7.5
55
s
TER16K
TER32K
TER64K
TER128K
TER512K
TPABT
Sector Erase (16KB)
Sector Erase (32KB)
Sector Erase (64KB)
Sector Erase (128KB)
Bank Erase (512KB)
Program Abort Latency
Erase Abort Latency
s
s
s
s
s
10
μs
μs
TEABT
—
30
30
MPC5604E Microcontroller Data Sheet, Rev. 6
42
NXP Semiconductors
Electrical characteristics
1
Table 23. Code flash program and erase specifications
Initial
Max3
(100
Typical
Value2
(0 Cycles)
Max4
(100000 Unit
Cycles)
Symbol
Parameter
Min Value
Cycles)
TEABT
TEABT
Erase Suspend Latency
—
—
—
30
—
30
—
μs
Erase Suspend Request Rate
10
ms
Endurance (8KB, 16KB sectors)
Endurance (32KB, 64KB sectors)
Endurance (128KB sectors)
100
10
1
NER
TDR
—
—
—
—
—
—
Kcycles
Years
Data Retention at 1K cycles
Data Retention at 10K cycles
Data Retention at 100K cycles
20
10
5
1
2
TBC = To be confirmed
Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to
change pending device characterization.
3
4
Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
The maximum program & erase times occur after the specified number of program/erase cycles. These maximum
values are characterized but not guaranteed.
5
6
Actual hardware programming times. This does not include software overhead.
Typical Bank programming time assumes that all cells are programmed in a single pulse. In reality some cells will
require more than one pulse, adding a small overhead to total bank programming time (see Initial Max column).
1
Table 24. Data flash program and erase specifications
Initial
Typical
Value2
(0 Cycles)
Max4
(100000 Unit
Cycles)
Max3
(100
Symbol
Parameter
Min Value
Cycles)
TDWPRG
TBKPRG
TER16K
TER512K
TPABT
Word Program5
—
—
30
0.49
0.7
1.9
—
TBC
TBC
TBC
TBC
12
TBC
TBC
TBC
TBC
12
μs
Bank Program (64 KB)5, 6
s
Sector Erase (16KB)
—
s
s
Bank Erase (64KB)
—
Program Abort Latency
Erase Abort Latency
—
μs
TEABT
TEABT
TEABT
NER
—
—
30
30
μs
Erase Suspend Latency
Erase Suspend Request Rate
Endurance (16KB sectors)
—
—
30
30
μs
10
100
—
—
—
ms
—
—
—
K cycles
Data Retention at 1K cycles
Data Retention at 10K cycles
Data Retention at 100K cycles
20
10
1
Years
@85C
TDR
—
—
—
1
2
TBC = To be confirmed
Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to
change pending device characterization.
MPC5604E Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
43
Electrical characteristics
3
Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
4
The maximum program & erase times occur after the specified number of program/erase cycles. These maximum
values are characterized but not guaranteed.
5
6
Actual hardware programming times. This does not include software overhead.
Typical Bank programming time assumes that all cells are programmed in a single pulse. In reality some cells will
require more than one pulse, adding a small overhead to total bank programming time (see Initial Max column).
Table 25. Flash read access timing
Symbol
C
Parameter
Conditions1
Max Unit
Maximum working frequency for Code Flash at
given number of WS in worst conditions
2 wait states
0 wait states
66
Fmax
C
MHz
18
Maximum working frequency for Data Flash at
given number of WS in worst conditions
Fmax
C
8 wait states
66
MHz
1
VDD_HV = 3.3 V 10%, TA = –40 to 125 °C, unless otherwise specified
3.17 NMI filter functional specification
Table 26. NMI filter functional specification
Pulse Width
Value
Units
Maximum pulse width
that is rejected
40
ns
Minimum pulse width
that is accepted
205
ns
The pulses shorter than “Maximum pulse width that is rejected” are blocked. The Pulses wider than “Minimum pulse width that
is passed” are allowed. When the pulses lengths are between they may be blocked or passed. This is due to tolerance of analog
circuit.
3.18 AC specifications
3.18.1 Pad AC specifications
Table 27 gives the AC electrical characteristics at 3.3 V (3.0 V < V
< 3.6 V) operation.
DD_HV_IO
MPC5604E Microcontroller Data Sheet, Rev. 6
44
NXP Semiconductors
Electrical characteristics
Table 27. Pad AC specifications (3.3 V, INVUSRO[PAD3V5V] = 1)
Rise/Fall1
(ns)
Load
drive
(pF)
Symbol
Parameter
Unit
Pad
Min
Typ
Max
25
50
3
3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
40
40
40
40
40
50
75
100
4
ns
ns
Propagation delay from
vdd/2 of internal signal
to Pchannel / Nchannel
switch on condition
Tswitchon
100
200
25
3
ns
3
ns
4
ns
50
6
ns
tr/tf
Slope at rising/falling
edge
100
200
25
10
14
—
—
—
—
0.01
0.01
0.01
0.01
1
ns
Slow
ns
MHz
MHz
MHz
MHz
mA/ns
mA/ns
mA/ns
mA/ns
ns
Frequency
of
Operation
50
2
Freq
100
200
25
2
2
2
Current
Slew
50
2
Slew rate at rising edge
of current
100
200
25
2
2
15
15
15
15
12
25
40
70
40
20
13
7
Propagation delay from
vdd/2 of internal signal
to Pchannel / Nchannel
switch on condition
50
1
ns
Tswitchon
100
200
25
1
ns
1
ns
2
ns
50
4
ns
tr/tf
Slope at rising/falling
edge
100
200
25
8
ns
Medium
14
—
—
—
—
2.5
2.5
2.5
2.5
ns
MHz
MHz
MHz
MHz
mA/ns
mA/ns
mA/ns
mA/ns
Frequency
of
Operation
50
Freq
100
200
25
7
Current
Slew
50
7
Slew rate at rising edge
of current
100
200
7
7
MPC5604E Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
45
Electrical characteristics
Table 27. Pad AC specifications (3.3 V, INVUSRO[PAD3V5V] = 1)
Rise/Fall1
Load
drive
(pF)
Symbol
Parameter
Unit
(ns)
Pad
Min
Typ
Max
25
50
1
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
6
6
ns
ns
Propagation delay from
vdd/2 of internal signal
to Pchannel / Nchannel
switch on condition
Tswitchon
100
200
25
1
6
ns
1
6
ns
1
4
ns
50
1.5
3
7
ns
tr/tf
Slope at rising/falling
edge
100
200
25
12
18
72
55
40
25
40
40
40
ns
Fast
5
ns
—
—
—
—
3
MHz
MHz
MHz
MHz
mA/ns
mA/ns
mA/ns
Frequency
of
Operation
50
Freq
100
200
25
50
3
Current
Slew
Slew rate at rising edge
of current
100
3
200
3
40
mA/ns
Propagation delay from
vdd/2 of internal signal
to Pchannel / Nchannel
switch on condition
Tswitchon
25
1
—
8
ns
tr/tf
Slope at rising/falling
edge
25
25
25
1
3
—
—
—
5
12
1
ns
ns
ns
TRise/TFall
Delay at rising/falling
edge
Symmetric
|TRise - TFall Delay between rising and
falling edge
0.05
Frequency
Freq
of
25
25
—
3
—
—
50
25
MHz
Operation
Current
Slew
Slew rate at rising edge
of current
mA/ns
1
Slope at rising/falling edge
MPC5604E Microcontroller Data Sheet, Rev. 6
46
NXP Semiconductors
Electrical characteristics
VDD_HV_IO/2
Pad
Data Input
Rising
Edge
Falling
Edge
Output
Delay
Output
Delay
VOH
VOL
Pad
Output
Figure 13. Pad output delay
3.19 AC timing characteristics
3.19.1 Generic timing diagrams
The generic timing diagrams in Figure 14 and Figure 15 apply to all I/O pins with pad types fast, slow and medium. See
Section 2.2, “Signal descriptions” for the pad type for each pin.
CLKOUT
VDD_HV_IOx/2
A
B
I/O OUTPUTS
VDD_HV_IOx/2
A—Maximum output delay time
B—Minimum output hold time
Figure 14. Generic output delay/hold timing
MPC5604E Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
47
Electrical characteristics
CLKOUT
VDD_HV_IOx/2
B
A
I/O INPUTS
VDD_HV_IOx/2
A—Minimum input setup time
B—Minimum input hold time
Figure 15. Generic Input setup/hold timing
MPC5604E Microcontroller Data Sheet, Rev. 6
48
NXP Semiconductors
Electrical characteristics
3.19.2 RESET pin characteristics
The MPC5604E implements a dedicated bidirectional RESET pin.
Figure 16. Start-up reset requirements
V
DD
V
DDMIN
RESET
V
IH
V
IL
device reset forced by RESET
device start-up phase
Figure 17. Noise filtering on reset signal
VRESET
hw_rst
‘1’
V
DD
V
IH
V
IL
‘0’
filtered by
lowpass filter
unknown reset
state
filtered by
hysteresis
filtered by
lowpass filter
device under hardware reset
W
W
FRST
FRST
W
NFRST
MPC5604E Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
49
Electrical characteristics
Table 28. RESET electrical characteristics
Value2
Typ
Symbol
C
Parameter
Conditions1
Unit
Min
Max
Input High Level CMOS
(Schmitt Trigger)
VIH
VIL
SR P
SR P
—
—
—
0.65VDD
—
—
VDD+0.4
V
V
Input low Level CMOS
(Schmitt Trigger)
−0.4
0.35VDD
Input hysteresis CMOS
(Schmitt Trigger)
VHYS CC C
0.1VDD
—
—
—
—
—
0.1VDD
12
V
V
VOL CC P Output low level
Push Pull, IOL = 3 mA,
CL = 25 pF,
Output transition time
—
output pin3
VDD = 3.3 V 10%
MEDIUM configuration
CL = 50 pF,
Ttr
CC D
—
—
—
—
—
—
—
25
40
ns
VDD = 3.3 V 10%
CL = 100 pF,
VDD = 3.3 V 10%
RESET input filtered
pulse
WFRST SR P
WNFRST SR P
—
—
40
ns
ns
µA
RESET input not filtered
pulse
—
500
10
—
Weak pull-up current
absolute value
VDD = 3.3 V 10%
|IWPU
|
CC P
150
1
2
3
VDD = 3.3 V 10% / 5.0 V 10%, TA = −40 to 125 °C, unless otherwise specified
All values need to be confirmed during device validation.
CL includes device and package capacitance (CPKG < 5 pF).
3.19.3 Nexus and JTAG timing
1
Table 29. Nexus debug port timing
Value
No.
Symbol
C
Parameter
Unit
Min
Typ
Max
1
tMCYC
CC D MCKO Cycle Time
2
—
—
—
8
tCYC
ns
2A
tMCYCP CC D MCKO cycle period
MCKO duty cycle
15
—
2B
tMDC
CC
D
48
52
%
3
4
5
6
7
tMDOV
CC D MCKO low to MDO data valid2
–0.1
–0.1
–0.1
50
—
—
—
—
—
0.22
0.22
0.22
—
tMCYC
tMCYC
tMCYC
ns
tMSEOV CC D MCKO low to MSEO data valid2
tEVTOV
tTCYC
tTDC
CC D MCKO low to EVTO data valid2
CC D TCK cycle time
CC D TCK Duty Cycle
40
60
%
MPC5604E Microcontroller Data Sheet, Rev. 6
50
NXP Semiconductors
Electrical characteristics
1
Table 29. Nexus debug port timing (continued)
Value
Typ
No.
Symbol
C
Parameter
Min
Unit
Max
tNTDIS
tNTMSS CC D TMS data setup time
tNTDIH CC D TDI data hold time
tNTMSH CC D TMS data hold time
CC D TDI data setup time
0.2
0.2
0.1
0.1
—
—
—
—
—
—
—
—
—
—
—
25
—
tTCYC
tTCYC
tTCYC
tTCYC
ns
8
9
10
11
tTDOV
tTDOV
CC D TCK low to TDO data valid
CC D TCK low to TDO data invalid
0.1
tTCYC
1
2
All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal.
MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.
2 A
2B
MCKO
3
4
5
MDO
MSEO
EVTO
Output Data Valid
Figure 18. Nexus output timing
7
TCK
6
Figure 19. Nexus event trigger and test clock timings
MPC5604E Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
51
Electrical characteristics
TCK
8
9
TMS, TDI
10
11
TDO
Figure 20. Nexus TDI, TMS, TDO Timing
3.19.4 GPIO timing
The GPIO specifications for setup time and output valid relative to CLKOUT are the same for all pins on the device regardless
of the primary pin function.
Table 30. GPIO Timing
No. Symbol
Characteristic
Min. Max. Unit
GPIO Read Time
GPIO Write Time
tCYC
1
2
tREAD
5
6
—
—
tCYC
tWRITE
MPC5604E Microcontroller Data Sheet, Rev. 6
52
NXP Semiconductors
Electrical characteristics
3.19.5 External interrupt timing (IRQ pin)
1
Table 31. External interrupt timing
Parameter
IRQ pulse width low
No.
Symbol
C
Conditions
Min Max Unit
1
2
3
tIPWL
tIPWH
tICYC
CC
CC
CC
D
D
D
—
—
—
4
4
—
—
—
tCYC
tCYC
tCYC
IRQ pulse width high
IRQ edge to edge time2
4+N3
1
2
3
IRQ timing specified at fSYS = 64 MHz and VDD_HV_IOx = 3.0 V, TA = TL to TH, and CL = 200 pF with SRC = 0b00.
Applies when IRQ pins are configured for rising edge or falling edge events, but not both.
N = ISR time to clear the flag
IRQ
1
2
3
Figure 21. External interrupt timing
3.19.6 FlexCAN timing
1
Table 32. FlexCAN timing
Num
Characteristic
Symbol Min. Value Max. Value
Unit
1
2
CTNX Output Valid after CLKOUT Rising Edge (Output Delay)
CNRX Input Valid to CLKOUT Rising Edge (Setup Time)
tCANOV
tCANSU
—
—
26.0
9.8
ns
ns
1
FlexCAN timing specified at fSYS = 64 MHz, VDD = 1.35 V to 1.65 V, VDDEH = 3.0 V to 5.5 V, VRC33 and
VDDPLL = 3.0 V to 3.6 V, TA = TL to TH, and CL = 50 pF with SRC = 0b00.
3.19.7 LINFlex timing
Minimum design target for interface frequency is 2 MBit/s.
MPC5604E Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
53
Electrical characteristics
3.19.8 DSPI timing
Table 33. DSPI timing
Conditions
No. Symbol
C
Parameter
Min
Max
Unit
Master (MTFE = 0)
62.5
128
31.25
16
—
—
—
—
—
1
tSCK CC
D
DSPI cycle time
Slave (MTFE = 0)
ns
Master (MTFE = 1,CPHA=1)
2
3
4
5
tCSC CC
tASC CC
tSDC CC
D
D
D
D
CS to SCK delay
After SCK delay
SCK duty cycle
Slave access time
—
ns
ns
—
—
16
0.4 * tSCK 0.6 * tSCK ns
tA
CC
SS active to SOUT valid
—
—
40
10
ns
ns
SS inactive to SOUT High-Z or
invalid
6
tDIS CC
D
Slave SOUT disable time
7
8
tPCSC CC
tPASC CC
D
D
PCSx to PCSS time
PCSS to PCSx time
—
—
13
13
12
2
—
—
—
—
ns
ns
Master (MTFE = 0)
Slave
9
tSUI CC
D
D
D
D
Data setup time for inputs
Data hold time for inputs
Data valid (after SCK edge)
Data hold time for outputs
ns
ns
ns
ns
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
Master (MTFE = 0)
Slave
NA1
NA1
NA1
NA1
12
–5
4
—
—
—
10
tHI
CC
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
Master (MTFE = 0)
Slave
–5
—
—
—
4
33
11 tSUO CC
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
Master (MTFE = 0)
Slave
—
–2
6
11
—
—
12 tHO CC
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
–2
—
1
This mode is not feasible at 32 MHz.
MPC5604E Microcontroller Data Sheet, Rev. 6
54
NXP Semiconductors
Electrical characteristics
2
3
PCSx
1
4
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
10
9
Last Data
SIN
First Data
Data
Data
12
11
First Data
Last Data
SOUT
Figure 22. DSPI classic SPI timing — Master, CPHA = 0
PCSx
SCK Output
(CPOL=0)
10
SCK Output
(CPOL=1)
9
First Data
Data
Data
Last Data
SIN
12
11
SOUT
Last Data
First Data
Figure 23. DSPI classic SPI timing — Master, CPHA = 1
MPC5604E Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
55
Electrical characteristics
3
2
SS
1
4
SCK Input
(CPOL=0)
4
SCK Input
(CPOL=1)
5
11
12
Data
6
First Data
Last Data
SOUT
9
10
Data
Last Data
First Data
SIN
Figure 24. DSPI classic SPI timing — Slave, CPHA = 0
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
6
12
Last Data
Data
Data
SOUT
SIN
First Data
10
9
Last Data
First Data
Figure 25. DSPI classic SPI timing — Slave, CPHA = 1
MPC5604E Microcontroller Data Sheet, Rev. 6
56
NXP Semiconductors
Electrical characteristics
3
PCSx
4
1
2
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
9
10
SIN
First Data
Last Data
Last Data
Data
12
11
SOUT
First Data
Data
Figure 26. DSPI modified transfer format timing — Master, CPHA = 0
PCSx
SCK Output
(CPOL=0)
SCK Output
(CPOL=1)
10
9
SIN
Last Data
First Data
Data
12
Data
11
First Data
Last Data
SOUT
Figure 27. DSPI modified transfer format timing — Master, CPHA = 1
MPC5604E Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
57
Electrical characteristics
3
2
SS
1
SCK Input
(CPOL=0)
4
4
SCK Input
(CPOL=1)
12
11
6
5
First Data
9
Data
Data
Last Data
10
SOUT
Last Data
First Data
SIN
Figure 28. DSPI modified transfer format timing — Slave, CPHA = 0
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
6
12
Last Data
First Data
10
Data
Data
SOUT
SIN
9
First Data
Last Data
Figure 29. DSPI modified transfer format timing — Slave, CPHA = 1
MPC5604E Microcontroller Data Sheet, Rev. 6
58
NXP Semiconductors
Electrical characteristics
8
7
PCSS
PCSx
Figure 30. DSPI PCS Strobe (PCSS) timing
3.19.9 Video interface timing
Table 34 details the MPC5604E’s video encoder block’s pixel input clocking requirement.
Table 34. Input pixel clock characteristics
No.
Parameter
Min
Max
Unit
PDI Clock Period
10
50
2
—
50
—
—
2
ns
%
1
2
PDI Clock Duty Cycle
Input setup time
3
4
5
ns
ns
ns
Input Hold Time
2
Input Pixel Clock Slew Rate
—
VCLKIN
1
3
4
VID_DATA[15:0]
VID_LINE_V
Input Data Valid
VID_FRAME_V
Figure 31. Video interface timing
MPC5604E Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
59
Electrical characteristics
3.19.10 Fast ethernet interface
MII signals use CMOS signal levels compatible with devices operating at either 5.0 V or 3.3 V. Signals are not TTL compatible.
They follow the CMOS electrical characteristics.
3.19.10.1 MII receive signal timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK)
The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency
requirement. In addition, the system clock frequency must exceed four times the RX_CLK frequency.
Table 35. MII receive signal timing
No.
Parameter
Min
Max
Unit
1
2
3
4
Rx Clock Period
40
5
—
—
—
60
ns
ns
ns
%
RXD[3:0], RX_DV, RX_ER to RX_CLK setup
RX_CLK to RXD[3:0], RX_DV, RX_ER hold
Rx Clock Duty Cycle
5
40
4
RX_CLK (input)
1
RXD[3:0] (inputs)
RX_DV
RX_ER
2
3
Figure 32. MII receive signal timing diagram
3.19.10.2 MII transmit signal timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)
The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency
requirement. In addition, the system clock frequency must exceed four times the TX_CLK frequency.
The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from either the rising or falling edge of
TX_CLK, and the timing is the same in either case. This options allows the use of non-compliant MII PHYs.
Refer to the Ethernet chapter for details of this option and how to enable it.
1
Table 36. MII transmit signal timing
No.
Parameter
Min
Max
Unit
5
6
7
8
TX Clock Period
40
5
—
—
25
60
ns
ns
ns
%
TX_CLK to TXD[3:0], TX_EN, TX_ER invalid
TX_CLK to TXD[3:0], TX_EN, TX_ER valid
TX Clock Duty Cycle
—
40
1
Output pads configured with SRC = 0b11.
MPC5604E Microcontroller Data Sheet, Rev. 6
60
NXP Semiconductors
Electrical characteristics
TX_CLK (input)
6
TXD[3:0] (outputs)
TX_EN
TX_ER
7
Figure 33. MII transmit signal timing diagram
3.19.10.3 MII async inputs signal timing (CRS and COL)
1
Table 37. MII async inputs signal timing
No.
Parameter
CRS, COL minimum pulse width
Min
Max
Unit
9
1.5
—
TX_CLK period
1
Output pads configured with SRC = 0b11.
CRS, COL
9
Figure 34. MII async inputs timing diagram
3.19.10.4 MII serial management channel timing (MDIO and MDC)
The FEC functions correctly with a maximum MDC frequency of 5 MHz.
Table 38. MII serial management channel timing (MDIO and MDC)
No.
Parameter
MDIO Input delay setup
Min
Max
Unit
1
2
3
4
5
6
28
0
—
—
25
—
—
60
ns
ns
ns
ns
ns
%
MDIO Input delay hold
MDIO Output delay valid
MDIO Output delay Invalid
MDC clock period
—
0
100
40
MDC Duty Cycle
MPC5604E Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
61
Electrical characteristics
3.19.11 I2C timing
2
Table 39. I C SCL and SDA input timing specifications
Value
No.
Symbol
Parameter
Unit
Min Max
1
2
4
6
7
8
9
—
—
—
—
—
—
—
D Start condition hold time
D Clock low time
2
8
—
—
—
—
—
—
—
IP bus cycle1
IP bus cycle1
ns
D Data hold time
0.0
4
D Clock high time
D Data setup time
IP bus cycle1
0.0
2
ns
D Start condition setup time (for repeated start condition only)
D Stop condition setup time
IP bus cycle1
IP bus cycle1
2
1
Inter Peripheral Clock is the clock at which the I2C peripheral is working in the device. It is equal to the system clock
(Sys_clk).
2
Table 40. I C SCL and SDA output timing specifications
Value
No.
Symbol
Parameter
Unit
Min Max
11
21
33
41
51
61
71
81
91
—
—
—
—
—
—
—
—
—
D Start condition hold time
D Clock low time
6
—
—
IP bus cycle2
IP bus cycle1
ns
10
—
7
D SCL/SDA rise time
D Data hold time
99.6
—
IP bus cycle1
D SCL/SDA fall time
D Clock high time
—
10
2
99.5
—
ns
IP bus cycle1
IP bus cycle1
IP bus cycle1
IP bus cycle1
D Data setup time
—
D Start condition setup time (for repeated start condition only)
D Stop condition setup time
20
10
—
—
1
Programming IBFD (I2C bus Frequency Divider) with the maximum frequency results in the minimum output timings
listed. The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period.
The actual position is affected by the prescale and division values programmed in IFDR.
2
3
Inter Peripheral Clock is the clock at which the I2C peripheral is working in the device.
Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL
or SDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.
MPC5604E Microcontroller Data Sheet, Rev. 6
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NXP Semiconductors
Electrical characteristics
2
6
5
SCL
3
1
8
4
7
9
SDA
2
Figure 35. I C input/output timing
3.19.12 SAI timing
All timing requirements are specified relative to the clock period or to the minimum allowed clock period of a device.
Table 41. Master Mode SAI Timing
Value
No.
Parameter
Unit
Min
Max
Operating voltage
2.7
3.6
V
S1
SAI_MCLK cycle time
31.25
45%
62.5
—
ns
S2
S3
SAI_MCLK pulse width high/low
SAI_BCLK cycle time
55%
—
MCLK period
ns
S4
S5
SAI_BCLK pulse width high/low
SAI_BCLK to SAI_FS output valid
45%
—
55%
15
BCLK period
ns
ns
ns
S6
S7
SAI_BCLK to SAI_FS output invalid
SAI_BCLK to SAI_TXD valid
0
—
—
15
S8
S9
SAI_BCLK to SAI_TXD invalid
0
—
—
—
ns
ns
ns
SAI_RXD/SAI_FS input setup before SAI_BCLK 28
S10 SAI_RXD/SAI_FS input hold after SAI_BCLK
0
MPC5604E Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
63
Electrical characteristics
Figure 36. SAI timing master modes
Table 42. Slave Mode SAI Timing
Value
No.
Parameter
Unit
Min
Max
Operating voltage
2.7
80
45%
10
2
3.6
V
S11 SAI_BCLK cycle time (input)
—
ns
S12 SAI_BCLK pulse width high/low (input)
S13 SAI_FS input setup before SAI_BCLK
S14 SAI_FS input hold after SAI_BCLK
S15 SAI_BCLK to SAI_TXD/SAI_FS output valid
S16 SAI_BCLK to SAI_TXD/SAI_FS output invalid
S17 SAI_RXD setup before SAI_BCLK
S18 SAI_RXD hold after SAI_BCLK
55%
—
BCLK period
ns
ns
ns
ns
—
—
0
28
—
10
2
—
ns
ns
—
MPC5604E Microcontroller Data Sheet, Rev. 6
64
NXP Semiconductors
Electrical characteristics
Figure 37. SAI timing slave modes
MPC5604E Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
65
Package mechanical data
4
Package mechanical data
4.1
100 LQFP mechanical outline drawing
MPC5604E Microcontroller Data Sheet, Rev. 6
66
NXP Semiconductors
Package mechanical data
Figure 38. 100 LQFP package mechanical drawing (part 1)
MPC5604E Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
67
Package mechanical data
Figure 39. 100 LQFP package mechanical drawing (part 2)
MPC5604E Microcontroller Data Sheet, Rev. 6
68
NXP Semiconductors
Package mechanical data
Figure 40. 100 LQFP package mechanical drawing (part 3)
MPC5604E Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
69
Package mechanical data
4.2
64 LQFP mechanical outline drawing
Figure 41. 64 LQFP package mechanical drawing (part 1)
MPC5604E Microcontroller Data Sheet, Rev. 6
70
NXP Semiconductors
Package mechanical data
Figure 42. 64LQFP package mechanical drawing (part 2)
MPC5604E Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
71
Package mechanical data
Figure 43. 64LQFP package mechanical drawing (part 3)
MPC5604E Microcontroller Data Sheet, Rev. 6
72
NXP Semiconductors
Ordering information
5
Ordering information
0
MPC
E
E F1
LH
M
R
56
4
Qualification status
Automotive platform (56 = Power architecture in 90 nm)
Core version (0 = e200z0h)
Config
Product (E = Family)
EEPROM (E = Data Flash)
Optional fields
Temperature spec
Package code (LH = 64LQFP)
Tape and Reel (R = Tape and reel)
Optional fields
Qualification status
M = MC status
Config
4 = SAI + ENET + MJPEG
3 = SAI + ENET
F = ATMC
1 = Maskset revision 1
S = Auto qualified
P = PC status
2 = Maskset revision 2
Tempearture spec
C = - 40 to 85 oC
V = - 40 to 105 oC
M = - 40 to 125 oC
Figure 44. Commercial product code structure
Table 43. Orderable part number summary
Part number1
Flash/SRAM Package
Speed
64 MHz
Key Features
SPC5604EEF2MLH and SPC5604EEF2MLHR
SPC5603EEF2MLH and SPC5603EEF2MLHR
SAI + ENET + MJPEG
SAI + ENET
512K / 96K 64 LQFP
1
All packaged devices are PPC, rather than MPC or SPC, until product qualifications are complete.
The unpackaged device prefix is PCC, rather than SCC, until product qualification is complete.
MPC5604E Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
73
Document revision history
6
Document revision history
Table 44. Revision history
Substantive changes
Revision
Date
1
15 Feb 2011 Initial Release
• In the Recommended operating conditions table, changed the external supply voltage changed
from 1.14 V to 1.15 V
• Added a footnote in the Device Summary table
2
13 June 2011
• Changed the description of VDD_HV_S_BALLAST0 in the Supply pins table
• Editorial changes and improvements
• In the Low voltage monitor electrical characteristics table, changed the marking of VPORUP from
P to D
• In the DC electrical characteristics table, changed the IOL of the Medium, low level output
voltage to 2 mA. From the same table, removed VOL_SYM and VOH_SYM. Revised the IPU and IPD
• In the Main oscillator electrical characteristics table, changed the minimum value of
transconductance to 4 mA/V
• In the 16 MHz RC oscillator electrical characteristics table, changed the marking of fRC from P
to C and revised its minimum and value.
• In the ADC conversion characteristics table, changed the minimum and maximum value of TUE
from TBD to -3 and 3
3
1 Nov 2011
• In the Pin muxing table, C5 port ABS[2] assignment changed from SIUL to MC_RGM
• IRevised the 64-pin and 100-pin package pinouts and added a footnote.
• In the Supply pins table, revised the description of ADC0 pins
• In the Supply pins table, added a column Port Pin and renamed the Symbol column
• IRemoved Power Supply segment table
• In the Pin Muxing table, clarified the peripherals in the following port pins: C5, A3, A8, A10, A12,
A15, C3, C4, C5, C6, C12
• In the Low voltage monitor electrical characteristics table, changed the maximum value of
VMLVDDOK_H
• In the ADC conversion characteristics, changed the ADC sampling time to 500 ns
• Inserted values for TBDs in the table EMI Testing Specifications
• From Supply Pins table, removed VVD_HV_ADV0
• In the PLLMRFM electrical specifications table, added the value of Self-clocked mode frequency
• In the ADC conversion characteristics table, added the value of INJ
3.1
4
2 Dec 2011
23 Jan 2012
• System Pin table, swapped the description of XTAL and EXTAL
On the first page:
• added 32 external interrupts for 100-pin LQFP and updated 22 external interrupts for 64-pin
LQFP.
• changed "8 input channels" to "7 input channels".
• changed "4 internal connection..." to "3 internal connection...".
• Removed “1 x VGate Current”.
• In Table 1., “Device summary”, removed VGate current from the equation for ADC (10-bit).
• In Figure 1., “MPC5604E block diagram”: changed "4+4 channels" to "4+3 channels".
• Updated Table 2., “Supply pins”.
5
03 Feb 2015
• In Table 4., “Pin muxing”, function of port pins B4, B13, B14, B15, C0, C1, C9, C15, D8, D13,
D14, and E2 changed from GPIO to GPI.
• Added new section - Section 5, “Ordering information”.
• In Figure 2., “64-pin LQFP pinout (top view)”, changed VSS (pin 47) to VSS_HV.
• In Figure 3., “100-pin LQFP pinout (top view)”, changed VSS (pin 74) to VSS_HV.
• Updated “optional fields” entries in Figure 44., “Commercial product code structure”.
MPC5604E Microcontroller Data Sheet, Rev. 6
74
NXP Semiconductors
Document revision history
Table 44. Revision history (continued)
Substantive changes
Revision
Date
• Changed the DS document from Advanced Information to Technical Data
• Updated Figure 44., “Commercial product code structure” and Table 43., “Orderable part
number summary”.
5.1
27 Jan 2016
• In Table 14., “Low voltage monitor electrical characteristics”, changed the max value of
VMLVDDOK_H from 1.235 V to 1.135 V
• In Table 41., “Master Mode SAI Timing”
•
•
•
•
For SAI_MCLK changed the Min cycle time from 40 to 31.25.
Changed the minimal value of SAI_BCLK cycle time from 80 to 62.5.
Updated unit of SAI_BCLK cycle time from BCLK period to ns.
Updated unit of SAI_BCLK pulse width high/low from ns to BCLK period.
• In Table 19., “PLLMRFM electrical specifications (VDDPLL = 3.0 V to 3.6 V, VSS = VSSPLL = 0 V,
TA = TL to TH)” changed the following:
•
•
•
Changed the name from fFMPLLOUT to fFMPLL_0PCS changed the Max value to 128
Added PLL output frequecy parameter row
Changed the frequency of fVCO Min range from 20 MHz to 256 MHz and Max range from
150 MHz to 512 MHz
16 October
2019
6
•
•
Changed the Min value of System clock period parameter to 1/fsys
Changed the name of Self-clocked mode frequency to Self-clocked mode
frequency(VCO free running frequency)
•
Updated the row for CJITTER
• In section 3.8.1.2, “External voltage regulation mode”, under Figure 5., “External Regulation
Mode”, added the following note:
•
In external regulation mode, POR_B pin should be used to control the power on RESET
for the device. POR_B should be kept low (asserted) as long as the input supplies are
unstable or below the specified operating range. Failure to do so may lead to unexpected
device operation and erratic reset recovery.
• Added section 3.17, “NMI filter functional specification”
• In Section Table 43., “Orderable part number summary”, changed the part number to
““SPC5604EEF2MLH and SPC5604EEF2MLHR” and “SPC5603EEF2MLH and
SPC5603EEF2MLHR”.
MPC5604E Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
75
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© 2019 NXP B.V.
Document Number: MPC5604E
Rev. 6
11/2019
相关型号：
SPC5604PEF1MLQ6
Freescale 32-bit MCU, Power Arch core, 512KB Flash, 64MHz, -40/+125degC, Automotive Grade, QFP 144
NXP
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