SPC5644AF0MMG3R [NXP]
Freescale 32-bit MCU, Power Arch, 4MB Flash, 80MHz, -40/+125degC, Automotive Grade, MAPBGA 208;
| 型号： | SPC5644AF0MMG3R |
| 厂家： | 
NXP |
| 描述： | Freescale 32-bit MCU, Power Arch, 4MB Flash, 80MHz, -40/+125degC, Automotive Grade, MAPBGA 208 |
| 文件： | 总142页 (文件大小：1662K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MPC5644A
Rev. 7.1, 12/2014
Freescale Semiconductor
MPC5644A Microcontroller
Datasheet
This is the MPC5644A Datasheet set consisting of the following files:
•
•
MPC5644A Datasheet Addendum (MPC5644A_AD), Rev. 1
MPC5644A Datasheet (MPC5644A), Rev. 7
© Freescale Semiconductor, Inc., 2014. All rights reserved.
MPC5644A_AD
Rev. 1, 12/2014
Freescale Semiconductor
Datasheet Addendum
MPC5644A Microcontroller
Datasheet Addendum
Table of Contents
Addendum List for Revision 7. . . . . . . . . . . . . . . . 2
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . 2
This addendum describes corrections to the MPC5644A
Microcontroller Datasheet, order number MPC5644A.
For convenience, the addenda items are grouped by
revision. Please check our website at
1
2
http://www.freescale.com/powerarchitecture for the
latest updates.
The current version available of the MPC5644A
Microcontroller Datasheet is Revision 7.
© Freescale Semiconductor, Inc., 2014. All rights reserved.
1 Addendum List for Revision 7
4
Table 1. MPC5644A Rev 7 Addendum
Location
Description
Section 3.11, “Temperature In “Temperature Sensor Electrical Characteristics” table, update the Min and Max value of
Sensor Electrical
Characteristics”,
Page 90
“Accuracy” parameter to -20oC and +20oC, respectively.
2 Revision History
Table 2 provides a revision history for this datasheet addendum document.
Table 2. Revision History Table
Rev. Number
Substantive Changes
Date of Release
1.0
Initial release.
12/2014
MPC5644A_AD, Rev. 1
2
Freescale Semiconductor
Information in this document is provided solely to enable system and software
implementers to use Freescale products. There are no express or implied copyright
licenses granted hereunder to design or fabricate any integrated circuits based on the
information in this document.
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© 2014 Freescale Semiconductor, Inc.
Document Number: MPC5644A_AD
Rev. 1
12/2014
Freescale Semiconductor
Data Sheet: Advance Information
Document Number: MPC5644A
Rev. 7, Jan 2012
MPC5644A
MPC5644A Microcontroller
Data Sheet
208 (17 x 17 mm)
324 (23 x 23 mm)
176 (24 x 24 mm)
•
2 enhanced queued analog-to-digital converters
(eQADCs)
•
150 MHz e200z4 Power Architecture core
—
—
—
—
Variable length instruction encoding (VLE)
—
Forty 12-bit input channels (multiplexed on 2 ADCs);
expandable to 56 channels with external multiplexers
6 command queues
Trigger and DMA support
688 ns minimum conversion time
Superscalar architecture with 2 execution units
Up to 2 integer or floating point instructions per cycle
Up to 4 multiply and accumulate operations per cycle
—
—
—
•
Memory organization
—
—
—
4 MB on-chip flash memory with ECC and Read
While Write (RWW)
192 KB on-chip SRAM with standby functionality
(32 KB) and ECC
8 KB instruction cache (with line locking),
configurable as 2- or 4-way
•
•
On-chip CAN/SCI/FlexRay Bootstrap loader with Boot
Assist Module (BAM)
Nexus
—
—
Class 3+ for the e200z4 core
Class 1 for the eTPU
•
•
JTAG (5-pin)
Development Trigger Semaphore (DTS)
—
—
—
—
14 + 3 KB eTPU code and data RAM
5 4 crossbar switch (XBAR)
24-entry MMU
External Bus Interface (EBI) with slave and master
port
—
Register of semaphores (32-bits) and an identification
register
—
—
Used as part of a triggered data acquisition protocol
EVTO pin is used to communicate to the external tool
•
Fail Safe Protection
•
•
Clock generation
—
—
—
Interrupts
—
—
Serial channels
—
—
16-entry Memory Protection Unit (MPU)
CRC unit with 3 sub-modules
Junction temperature sensor
—
—
On-chip 4–40 MHz main oscillator
On-chipFMPLL(frequency-modulatedphase-locked
loop)
•
•
Up to 120 general purpose I/O lines
Configurable interrupt controller (with NMI)
64-channel DMA
—
Individually programmable as input, output or special
function
—
Programmable threshold (hysteresis)
3 eSCI
•
•
Power reduction mode: slow, stop and stand-by modes
Flexible supply scheme
3 DSPI (2 of which support downstream Micro
Second Channel [MSC])
3 FlexCAN with 64 messages each
1 FlexRay module (V2.1) up to 10 Mbit/s with dual
or single channel and 128 message objects and ECC
—
—
5 V single supply with external ballast
Multiple external supply: 5 V, 3.3 V and 1.2 V
—
—
•
Packages
—
—
—
176 LQFP
208 MAPBGA
324 TEPBGA
•
•
1 eMIOS:
1 eTPU2 (second generation eTPU)
24 unified channels
—
—
32 standard channels
1 reaction module (6 channels with three outputs
per channel)
496-pin CSP (calibration tool only)
This document contains information on a product under development. Freescale reserves
the right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2009–2012. All rights reserved.
Table of Contents
1
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
3.3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 67
3.3.1 General notes for specifications at maximum
1.1 Document Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.3 Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.4 Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.4.1 e200z4 core. . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.4.2 Crossbar Switch (XBAR) . . . . . . . . . . . . . . . . . . .6
1.4.3 eDMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.4.4 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . .7
1.4.5 Memory protection unit (MPU). . . . . . . . . . . . . . .8
1.4.6 FMPLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
1.4.7 SIU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
1.4.8 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . .9
1.4.9 BAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
1.4.10 eMIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
1.4.11 eTPU2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
1.4.12 Reaction module . . . . . . . . . . . . . . . . . . . . . . . .13
1.4.13 eQADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
1.4.14 DSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
1.4.15 eSCI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.4.16 FlexCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.4.17 FlexRay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.4.18 System timers . . . . . . . . . . . . . . . . . . . . . . . . . .17
1.4.19 Software watchdog timer (SWT) . . . . . . . . . . . .17
1.4.20 Cyclic redundancy check (CRC) module. . . . . .18
1.4.21 Error correction status module (ECSM). . . . . . .18
1.4.22 External bus interface (EBI). . . . . . . . . . . . . . . .18
1.4.23 Calibration EBI. . . . . . . . . . . . . . . . . . . . . . . . . .19
1.4.24 Power management controller (PMC) . . . . . . . .19
1.4.25 Nexus port controller . . . . . . . . . . . . . . . . . . . . .19
1.4.26 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.4.27 Development Trigger Semaphore (DTS). . . . . .20
1.5 MPC5644A series architecture . . . . . . . . . . . . . . . . . . .20
1.5.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.5.2 Block summary . . . . . . . . . . . . . . . . . . . . . . . . .22
Pinout and signal description . . . . . . . . . . . . . . . . . . . . . . . . .24
2.1 176 LQFP pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.2 208 MAP BGA ballmap. . . . . . . . . . . . . . . . . . . . . . . . .26
2.3 324 TEPBGA ballmap. . . . . . . . . . . . . . . . . . . . . . . . . .27
2.4 Signal summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.5 Signal details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
3.1 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . .65
3.2 Maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.4 EMI (electromagnetic interference) characteristics . . . 71
3.5 Electrostatic discharge (ESD) characteristics . . . . . . . 71
3.6 Power management control (PMC) and power on reset
(POR) electrical specifications . . . . . . . . . . . . . . . . . . . . . . . 72
3.6.1 Voltage regulator controller (VRC)
electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 75
3.6.2 Regulator Example. . . . . . . . . . . . . . . . . . . . . . 76
3.6.3 Recommended power transistors . . . . . . . . . . 77
3.7 Power up/down sequencing . . . . . . . . . . . . . . . . . . . . 77
3.8 DC electrical specifications . . . . . . . . . . . . . . . . . . . . . 78
3.9 I/O pad current specifications . . . . . . . . . . . . . . . . . . . 85
3.9.1 I/O pad VRC33 current specifications . . . . . . . . 86
3.9.2 LVDS pad specifications. . . . . . . . . . . . . . . . . . 87
3.10 Oscillator and PLLMRFM electrical characteristics . . . 88
3.11 Temperature sensor electrical characteristics . . . . . . . 90
3.12 eQADC electrical characteristics. . . . . . . . . . . . . . . . . 90
3.13 Configuring SRAM wait states. . . . . . . . . . . . . . . . . . . 93
3.14 Platform flash controller electrical characteristics . . . . 93
3.15 Flash memory electrical characteristics. . . . . . . . . . . . 93
3.16 AC specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
3.16.1 Pad AC specifications . . . . . . . . . . . . . . . . . . . 95
3.17 AC timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
3.17.1 Reset and configuration pin timing. . . . . . . . . . 98
3.17.2 IEEE 1149.1 interface timing . . . . . . . . . . . . . . 99
3.17.3 Nexus timing . . . . . . . . . . . . . . . . . . . . . . . . . 102
3.17.4 External Bus Interface (EBI) and calibration
bus interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . 106
3.17.5 External interrupt timing (IRQ pin) . . . . . . . . . 110
3.17.6 eTPU timing . . . . . . . . . . . . . . . . . . . . . . . . . . 110
3.17.7 eMIOS timing . . . . . . . . . . . . . . . . . . . . . . . . . .111
3.17.8 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . .111
3.17.9 eQADC SSI timing . . . . . . . . . . . . . . . . . . . . . 118
3.17.10FlexCAN system clock source. . . . . . . . . . . . 119
Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . 120
4.1.1 176 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.1.2 208 MAPBGA. . . . . . . . . . . . . . . . . . . . . . . . . 123
4.1.3 324 TEPBGA . . . . . . . . . . . . . . . . . . . . . . . . . 125
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . 128
2
3
4
5
6
MPC5644A Microcontroller Data Sheet, Rev. 7
2
Freescale Semiconductor
1
Introduction
1.1
Document Overview
This document provides electrical specifications, pin assignments, and package diagrams for the MPC5644A series of
microcontroller units (MCUs). For functional characteristics, refer to the MPC5644A Microcontroller Reference Manual.
1.2
Description
®
The microcontroller’s e200z4 host processor core is built on Power Architecture technology and designed specifically for
embedded applications. In addition to the Power Architecture technology, this core supports instructions for digital signal
processing (DSP).
The MPC5644A has two levels of memory hierarchy consisting of 8 KB of instruction cache, backed by 192 KB on-chip SRAM
and 4 MB of internal flash memory. The MPC5644A includes an external bus interface, and also a calibration bus that is only
accessible when using the Freescale VertiCal Calibration System.
This document describes the features of the MPC5644A and highlights important electrical and physical characteristics of the
device.
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
3
1.3
Device comparison
Table 1 summarizes the MPC5644A and compares it to the MPC5634M.
Table 1. MPC5644A, MPC5634M and MPC5642A comparison
Feature
MPC5644A
MPC5634M
MPC5642A
Process
Core
90 nm
e200z4
e200z3
e200z4
SIMD
Yes
VLE
Yes
Cache
8 KB instruction
No
NMI & Critical Interrupt
16 entry
No
8 KB instruction
Non-Maskable Interrupt (NMI)
MMU
MPU
24 entry
16 entry
5 4
24 entry
16 entry
4 4
Crossbar switch
Core performance
Windowing software watchdog
Core Nexus
SRAM
3 4
0–150 MHz
0–80 MHz
Yes
0–150 MHz
Class 3+
192 KB
Class 2+
94 KB
Class 3+
128 KB
2 MB
Flash
4 MB
1.5 MB
Flash fetch accelerator
External bus
Calibration bus
DMA
4 256-bit
4 128-bit
None
16-bit (incl 32-bit muxed)
16-bit (incl 32-bit muxed)
64 ch.
16-bit
16-bit (incl 32-bit muxed)
64 ch.
32 ch.
DMA Nexus
Serial
None
3
2
3
eSCI_A
Yes (MSC Uplink)
eSCI_B
Yes (MSC Uplink)
eSCI_C
Yes
3
No
2
Yes
3
CAN
CAN_A
64 buf
No
CAN_B
64 buf
64 buf
3
64 buf
64 buf
3
CAN_C
32 buf
2
SPI
MPC5644A Microcontroller Data Sheet, Rev. 7
4
Freescale Semiconductor
Table 1. MPC5644A, MPC5634M and MPC5642A comparison (continued)
Feature
MPC5644A
MPC5634M
MPC5642A
Micro Second Channel (MSC) bus
downlink
Yes
DSPI_A
DSPI_B
DSPI_C
DSPI_D
No
Yes (with LVDS)
Yes (with LVDS)
No
Yes
Yes
Yes
Yes
FlexRay
No
System timers
5 PIT channels
4 STM channels
1 Software Watchdog
eMIOS
eTPU
24 ch.
16 ch.
32 ch. eTPU2
14 KB
3 KB
24 ch.
Code memory
Data memory
Interrupt controller
ADC
486 ch.1
40 ch.
307 ch.
34 ch.
Yes
486 ch.1
40 ch.
ADC_A
ADC_B
Yes
Temp sensor
Yes
Variable gain amp.
Yes
Decimation filter
2
1
2
Sensor diagnostics
Yes
CRC
Yes
No
Yes
FMPLL
Yes
VRC
Yes
Supplies
5 V, 3.3 V2
5 V, 3.3 V3
5 V, 3.3 V2
Low-power modes
Stop Mode
Slow Mode
Packages
176 LQFP4
208 MAPBGA4,5
324 TEPBGA3246
496-pin CSP7
144 LQFP
176 LQFP
176 LQFP4
208 MAPBGA4,5
324 TEPBGA3246
496-pin CSP7
208 MAPBGA
496-pin CSP7
1
199 interrupt vectors are reserved.
5 V single supply only for 176 LQFP.
5 V single supply only for 144 LQFP.
2
3
4
5
6
Pinout compatible with Freescale’s MPC5634M devices.
Pinout compatible with Freescale’s MPC5534.
Ballmap upwardly compatible with the standardized package ballmap used for various Freescale MPC5xxx family members, including
MPC5554, MPC5567 and MPC5666.
7
For Freescale VertiCal Calibration System only.
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
5
1.4
Feature details
e200z4 core
1.4.1
MPC5644A devices have a high performance e200z448n3 core processor:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Dual issue, 32-bit Power Architecture embedded category CPU
Variable Length Encoding Enhancements
8 KB instruction cache: 2- or 4- way set associative instruction cache
Thirty-two 64-bit general purpose registers (GPRs)
Memory management unit (MMU) with 24-entry fully-associative translation look-aside buffer (TLB)
Harvard Architecture: Separate instruction bus and load/store bus
Vectored interrupt support
Non-maskable interrupt input
Critical Interrupt input
New ‘Wait for Interrupt’ instruction, to be used with new low power modes
Reservation instructions for implementing read-modify-write accesses
Signal processing extension (SPE) APU
Single Precision Floating point (scalar and vector)
Nexus Class 3+ debug
Process ID manipulation for the MMU using an external tool
1.4.2
Crossbar Switch (XBAR)
The XBAR multiport crossbar switch supports simultaneous connections between five master ports and four slave ports. The
crossbar supports a 32-bit address bus width and a 64-bit data bus width.
The crossbar allows three concurrent transactions to occur from the master ports to any slave port but each master must access
a different slave. If a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher
priority master and grants it ownership of the slave port. All other masters requesting that slave port are stalled until the higher
priority master completes its transactions. Requesting masters are treated with equal priority and are granted access to a slave
port in round-robin fashion, based upon the ID of the last master to be granted access. The crossbar provides the following
features:
•
5 master ports
— CPU instruction bus
— CPU data bus
— eDMA
— FlexRay
— External Bus Interface
4 slave ports
•
•
— Flash
— Calibration and EBI bus
— SRAM
— Peripheral bridge
32-bit internal address, 64-bit internal data paths
MPC5644A Microcontroller Data Sheet, Rev. 7
6
Freescale Semiconductor
1.4.3
eDMA
The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data
movements via 64 programmable channels, with minimal intervention from the host processor. The hardware
micro-architecture includes a DMA engine which performs source and destination address calculations, and the actual data
movement operations, along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels.
This implementation is utilized to minimize the overall block size. The eDMA module provides the following features:
•
•
•
•
•
•
All data movement via dual-address transfers: read from source, write to destination
Programmable source and destination addresses, transfer size, plus support for enhanced addressing modes
Transfer control descriptor organized to support two-deep, nested transfer operations
An inner data transfer loop defined by a “minor” byte transfer count
An outer data transfer loop defined by a “major” iteration count
Channel activation via one of three methods:
— Explicit software initiation
— Initiation via a channel-to-channel linking mechanism for continuous transfers
— Peripheral-paced hardware requests (one per channel)
•
•
•
•
•
•
Support for fixed-priority and round-robin channel arbitration
Channel completion reported via optional interrupt requests
One interrupt per channel, optionally asserted at completion of major iteration count
Error termination interrupts optionally enabled
Support for scatter/gather DMA processing
Ability to suspend channel transfers by a higher priority channel
1.4.4
Interrupt controller
The INTC (interrupt controller) provides priority-based preemptive scheduling of interrupt requests, suitable for statically
scheduled hard real-time systems.
For high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor
is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt
request source for quick determination of which ISR needs to be executed. It also provides an ample number of priorities so that
lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of
interrupt request, the priority of each interrupt request is software configurable.
When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC supports the priority
ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can be raised temporarily so that
all tasks which share the resource cannot preempt each other.
The INTC provides the following features:
•
•
•
•
•
•
•
•
•
9-bit vector addresses
Unique vector for each interrupt request source
Hardware connection to processor or read from register
Each interrupt source can assigned a specific priority by software
Preemptive prioritized interrupt requests to processor
ISR at a higher priority preempts executing ISRs or tasks at lower priorities
Automatic pushing or popping of preempted priority to or from a LIFO
Ability to modify the ISR or task priority to implement the priority ceiling protocol for accessing shared resources
Low latency—three clocks from receipt of interrupt request from peripheral to interrupt request to processor
This device also includes a non-maskable interrupt (NMI) pin that bypasses the INTC and multiplexing logic.
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
7
1.4.5
Memory protection unit (MPU)
The Memory Protection Unit (MPU) provides hardware access control for all memory references generated in a device. Using
preprogrammed region descriptors, which define memory spaces and their associated access rights, the MPU concurrently
monitors all system bus transactions and evaluates the appropriateness of each transfer. Memory references with sufficient
access control rights are allowed to complete; references that are not mapped to any region descriptor or have insufficient rights
are terminated with a protection error response.
The MPU has these major features:
•
Support for 16 memory region descriptors, each 128 bits in size
— Specification of start and end addresses provide granularity for region sizes from 32 bytes to 4 GB
— MPU is invalid at reset, thus no access restrictions are enforced
— Two types of access control definitions: processor core bus master supports the traditional {read, write, execute}
permissions with independent definitions for supervisor and user mode accesses; the remaining non-core bus
1
masters (eDMA, FlexRay, and EBI ) support {read, write} attributes
— Automatic hardware maintenance of the region descriptor valid bit removes issues associated with maintaining a
coherent image of the descriptor
— Alternate memory view of the access control word for each descriptor provides an efficient mechanism to
1
dynamically alter the access rights of a descriptor only
— For overlapping region descriptors, priority is given to permission granting over access denying as this approach
provides more flexibility to system software
•
Support for two XBAR slave port connections (SRAM and PBRIDGE)
— For each connected XBAR slave port (SRAM and PBRIDGE), MPU hardware monitors every port access using
the pre-programmed memory region descriptors
— An access protection error is detected if a memory reference does not hit in any memory region or the reference
is flagged as illegal in all memory regions where it does hit. In the event of an access error, the XBAR reference
is terminated with an error response and the MPU inhibits the bus cycle being sent to the targeted slave device
— 64-bit error registers, one for each XBAR slave port, capture the last faulting address, attributes, and detail
information
1.4.6
FMPLL
The FMPLL allows the user to generate high speed system clocks from a 4 MHz to 40 MHz crystal oscillator or external clock
generator. Further, the FMPLL supports programmable frequency modulation of the system clock. The PLL multiplication
factor, output clock divider ratio are all software configurable. The PLL has the following major features:
•
•
•
Input clock frequency from 4 MHz to 40 MHz
Reduced frequency divider (RFD) for reduced frequency operation without forcing the PLL to relock
Three modes of operation
— Bypass mode with PLL off
— Bypass mode with PLL running (default mode out of reset)
— PLL normal mode
•
•
Each of the three modes may be run with a crystal oscillator or an external clock reference
Programmable frequency modulation
— Modulation enabled/disabled through software
— Triangle wave modulation up to 100 kHz modulation frequency
— Programmable modulation depth (0% to 2% modulation depth)
— Programmable modulation frequency dependent on reference frequency
1. EBI not available on all packages and is not available, as a master, for customer.
MPC5644A Microcontroller Data Sheet, Rev. 7
8
Freescale Semiconductor
•
•
Lock detect circuitry reports when the PLL has achieved frequency lock and continuously monitors lock status to
report loss of lock conditions
Clock Quality Module
— Detects the quality of the crystal clock and causes interrupt request or system reset if error is detected
— Detects the quality of the PLL output clock; if error detected, causes system reset or switches system clock to
crystal clock and causes interrupt request
•
•
Programmable interrupt request or system reset on loss of lock
Self-clocked mode (SCM) operation
1.4.7
SIU
The MPC5644A SIU controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O (GPIO),
internal peripheral multiplexing, and the system reset operation. The reset configuration block contains the external pin boot
configuration logic. The pad configuration block controls the static electrical characteristics of I/O pins. The GPIO block
provides uniform and discrete input/output control of the I/O pins of the MCU. The reset controller performs reset monitoring
of internal and external reset sources, and drives the RSTOUT pin. Communication between the SIU and the e200z4 CPU core
is via the crossbar switch. The SIU provides the following features:
•
System configuration
— MCU reset configuration via external pins
— Pad configuration control for each pad
— Pad configuration control for virtual I/O via DSPI serialization
System reset monitoring and generation
•
— Power-on reset support
— Reset status register provides last reset source to software
— Glitch detection on reset input
— Software controlled reset assertion
•
External interrupt
— Rising or falling edge event detection
— Programmable digital filter for glitch rejection
— Critical Interrupt request
— Non-Maskable Interrupt request
•
•
GPIO
— Centralized control of I/O and bus pins
— Virtual GPIO via DSPI serialization (requires external deserialization device)
— Dedicated input and output registers for setting each GPIO and Virtual GPIO pin
Internal multiplexing
— Allows serial and parallel chaining of DSPIs
— Allows flexible selection of eQADC trigger inputs
— Allows selection of interrupt requests between external pins and DSPI
1.4.8
Flash memory
The MPC5644A provides up to 4 MB of programmable, non-volatile, flash memory. The non-volatile memory (NVM) can be
used to store instructions or data, or both. The flash module includes a Fetch Accelerator that optimizes the performance of the
flash array to match the CPU architecture. The flash module interfaces the system bus to a dedicated flash memory array
controller. For CPU ‘loads’, DMA transfers and CPU instruction fetch, it supports a 64-bit data bus width at the system bus port,
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
9
and 128- and 256-bit read data interfaces to flash memory. The module contains a prefetch controller which prefetches
sequential lines of data from the flash array into the buffers. Prefetch buffer hits allow no-wait responses.
The flash memory provides the following features:
•
Supports a 64-bit data bus for instruction fetch, CPU loads and DMA access. Byte, halfword, word and doubleword
reads are supported. Only aligned word and doubleword writes are supported.
•
Fetch Accelerator
— Architected to optimize the performance of the flash
— Configurable read buffering and line prefetch support
— Four-entry 256-bit wide line read buffer
— Prefetch controller
•
•
Hardware and software configurable read and write access protections on a per-master basis
Interface to the flash array controller pipelined with a depth of one, allowing overlapped accesses to proceed in parallel
for interleaved or pipelined flash array designs
•
•
Configurable access timing usable in a wide range of system frequencies
Multiple-mapping support and mapping-based block access timing (0-31 additional cycles) usable for emulation of
other memory types
•
•
•
•
•
•
•
•
•
•
•
Software programmable block program/erase restriction control
Erase of selected block(s)
Read page size of 128 bits (four words)
ECC with single-bit correction, double-bit detection
Program page size of 128 bits (four words) to accelerate programming
ECC single-bit error corrections are visible to software
Minimum program size is two consecutive 32-bit words, aligned on a 0-modulo-8 byte address, due to ECC
Embedded hardware program and erase algorithm
Erase suspend, program suspend and erase-suspended program
Shadow information stored in non-volatile shadow block
Independent program/erase of the shadow block
1.4.9
BAM
The BAM (Boot Assist Module) is a block of read-only memory that is programmed once by Freescale and is identical for all
MPC5644A MCUs. The BAM program is executed every time the MCU is powered-on or reset in normal mode. The BAM
supports different modes of booting. They are:
•
•
•
Booting from internal flash memory
Serial boot loading (A program is downloaded into RAM via eSCI or the FlexCAN and then executed)
Booting from external memory on external bus
The BAM also reads the reset configuration half word (RCHW) from internal flash memory and configures the MPC5644A
hardware accordingly. The BAM provides the following features:
•
Sets up MMU to cover all resources and mapping of all physical addresses to logical addresses with minimum address
translation
•
Sets up MMU to allow user boot code to execute as either Power Architecture embedded category (default) or as
Freescale VLE code
•
•
•
•
Location and detection of user boot code
Automatic switch to serial boot mode if internal flash is blank or invalid
Supports user programmable 64-bit password protection for serial boot mode
Supports serial bootloading via FlexCAN bus and eSCI using Freescale protocol
MPC5644A Microcontroller Data Sheet, Rev. 7
10
Freescale Semiconductor
•
•
•
•
•
•
Supports serial bootloading via FlexCAN bus and eSCI with auto baud rate sensing
Supports serial bootloading of either Power Architecture code (default) or Freescale VLE code
Supports booting from calibration bus interface
Supports censorship protection for internal flash memory
Provides an option to enable the core watchdog timer
Provides an option to disable the system watchdog timer
1.4.10 eMIOS
The eMIOS timer module provides the capability to generate or measure events in hardware.
The eMIOS module features include:
•
•
•
•
•
Twenty-four 24-bit wide channels
3 channels’ internal timebases can be shared between channels
1 Timebase from eTPU2 can be imported and used by the channels
Global enable feature for all eMIOS and eTPU timebases
Dedicated pin for each channel (not available on all package types)
Each channel (0–23) supports the following functions:
•
•
•
•
•
•
•
•
•
General-purpose input/output (GPIO)
Single-action input capture (SAIC)
Single-action output compare (SAOC)
Output pulse-width modulation buffered (OPWMB)
Input period measurement (IPM)
Input pulse-width measurement (IPWM)
Double-action output compare (DAOC)
Modulus counter buffered (MCB)
Output pulse width and frequency modulation buffered (OPWFMB)
1.4.11 eTPU2
The eTPU2 is an enhanced co-processor designed for timing control. Operating in parallel with the host CPU, the eTPU2
processes instructions and real-time input events, performs output waveform generation, and accesses shared data without host
intervention. Consequently, for each timer event, the host CPU setup and service times are minimized or eliminated. A powerful
timer subsystem is formed by combining the eTPU2 with its own instruction and data RAM. High-level assembler/compiler
and documentation allows customers to develop their own functions on the eTPU2.
MPC5644A devices feature the second generation of the eTPU, called eTPU2. Enhancements of the eTPU2 over the standard
eTPU include:
•
•
•
•
The Timer Counter (TCR1), channel logic and digital filters (both channel and the external timer clock input
[TCRCLK]) now have an option to run at full system clock speed or system clock / 2.
Channels support unordered transitions: transition 2 can now be detected before transition 1. Related to this
enhancement, the transition detection latches (TDL1 and TDL2) can now be independently negated by microcode.
A new User Programmable Channel Mode has been added: the blocking, enabling, service request and capture
characteristics of this channel mode can be programmed via microcode.
Microinstructions now provide an option to issue Interrupt and Data Transfer requests selected by channel. They can
also be requested simultaneously at the same instruction.
•
•
Channel Flags 0 and 1 can now be tested for branching, in addition to selecting the entry point.
Channel digital filters can be bypassed.
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
11
The eTPU2 includes these distinctive features:
•
32 channels; each channel associated with one input and one output signal
— Enhanced input digital filters on the input pins for improved noise immunity
— Identical, orthogonal channels: each channel can perform any time function. Each time function can be assigned
to more than one channel at a given time, so each signal can have any functionality.
— Each channel has an event mechanism which supports single and double action functionality in various
combinations. It includes two 24-bit capture registers, two 24-bit match registers, 24-bit greater-equal and
equal-only comparators.
— Input and output signal states visible from the host
•
•
2 independent 24-bit time bases for channel synchronization:
— First time base clocked by system clock with programmable prescale division from 2 to 512 (in steps of 2), or by
output of second time base prescaler
— Second time base counter can work as a continuous angle counter, enabling angle based applications to match
angle instead of time
— Both time bases can be exported to the eMIOS timer module
— Both time bases visible from the host
Event-triggered microengine:
— Fixed-length instruction execution in two-system-clock microcycle
— 14 KB of code memory (SCM)
— 3 KB of parameter (data) RAM (SPRAM)
— Parallel execution of data memory, ALU, channel control and flow control sub-instructions in selected
combinations
— 32-bit microengine registers and 24-bit wide ALU, with 1 microcycle addition and subtraction, absolute value,
bitwise logical operations on 24-bit, 16-bit, or byte operands, single-bit manipulation, shift operations, sign
extension and conditional execution
— Additional 24-bit Multiply/MAC/Divide unit which supports all signed/unsigned Multiply/MAC combinations,
and unsigned 24-bit divide. The MAC/Divide unit works in parallel with the regular microcode commands.
•
Resource sharing features support channel use of common channel registers, memory and microengine time:
— Hardware scheduler works as a “task management” unit, dispatching event service routines by predefined,
host-configured priority
— Automatic channel context switch when a “task switch” occurs, that is, one function thread ends and another
begins to service a request from other channel: channel-specific registers, flags and parameter base address are
automatically loaded for the next serviced channel
— SPRAM shared between host CPU and eTPU2, supporting communication either between channels and host or
inter-channel
— Hardware implementation of four semaphores support coherent parameter sharing between both eTPU engines
— Dual-parameter coherency hardware support allows atomic access to two parameters by host
Test and development support features:
•
— Nexus Class 1 debug, supporting single-step execution, arbitrary microinstruction execution, hardware
breakpoints and watchpoints on several conditions
— Software breakpoints
— SCM continuous signature-check built-in self test (MISC - multiple input signature calculator), runs concurrently
with eTPU2 normal operation
MPC5644A Microcontroller Data Sheet, Rev. 7
12
Freescale Semiconductor
1.4.12 Reaction module
The reaction module provides the ability to modulate output signals to manage closed loop control without CPU assistance. It
works in conjunction with the eQADC and eTPU2 to increase system performance by removing the CPU from the current
control loop.
The reaction module has the following features:
•
•
•
Six reaction channels
Each channel output is a bus of three signals, providing ability to control 3 inputs.
Each channel can implement a peak and hold waveform, making it possible to implement up to six independent peak
and hold control channels
Target applications include solenoid control for direct injection systems and valve control in automatic transmissions
1.4.13 eQADC
The enhanced queued analog to digital converter (eQADC) block provides accurate and fast conversions for a wide range of
applications. The eQADC provides a parallel interface to two on-chip analog to digital converters (ADC), and a single master
to single slave serial interface to an off-chip external device. Both on-chip ADCs have access to all the analog channels.
The eQADC prioritizes and transfers commands from six command conversion command ‘queues’ to the on-chip ADCs or to
the external device. The block can also receive data from the on-chip ADCs or from an off-chip external device into the six
result queues, in parallel, independently of the command queues. The six command queues are prioritized with Queue_0 having
the highest priority and Queue_5 the lowest. Queue_0 also has the added ability to bypass all buffering and queuing and abort
a currently running conversion on either ADC and start a Queue_0 conversion. This means that Queue_0 will always have a
deterministic time from trigger to start of conversion, irrespective of what tasks the ADCs were performing when the trigger
occurred. The eQADC supports software and external hardware triggers from other blocks to initiate transfers of commands
from the queues to the on-chip ADCs or to the external device. It also monitors the fullness of command queues and result
queues, and accordingly generates DMA or interrupt requests to control data movement between the queues and the system
memory, which is external to the eQADC.
The ADCs also support features designed to allow the direct connection of high impedance acoustic sensors that might be used
in a system for detecting engine knock. These features include differential inputs; integrated variable gain amplifiers for
increasing the dynamic range; programmable pull-up and pull-down resistors for biasing and sensor diagnostics.
The eQADC also integrates a programmable decimation filter capable of taking in ADC conversion results at a high rate,
passing them through a hardware low pass filter, then down-sampling the output of the filter and feeding the lower sample rate
results to the result FIFOs. This allows the ADCs to sample the sensor at a rate high enough to avoid aliasing of out-of-band
noise; while providing a reduced sample rate output to minimize the amount DSP processing bandwidth required to fully
process the digitized waveform.
The eQADC provides the following features:
•
Dual on-chip ADCs
— 2 12-bit ADC resolution
— Programmable resolution for increased conversion speed (12-bit, 10-bit, 8-bit)
–
–
–
12-bit conversion time: 938 ns (1 M sample/sec)
10-bit conversion time: 813 ns (1.2 M sample/second)
8-bit conversion time: 688 ns (1.4 M sample/second)
— Up to 10-bit accuracy at 500 KSample/s and 8-bit accuracy at 1 MSample/s
— Differential conversions
— Single-ended signal range from 0 to 5 V
— Variable gain amplifiers on differential inputs (1, 2, 4)
— Sample times of 2 (default), 8, 64 or 128 ADC clock cycles
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
13
— Provides time stamp information when requested
— Allows time stamp information relative to eTPU clock sources, such as an angle clock
— Parallel interface to eQADC CFIFOs and RFIFOs
— Supports both right-justified unsigned and signed formats for conversion results
•
40 single-ended input channels, expandable to 56 channels with external multiplexers (supports four external 8-to-1
muxes)
•
•
•
8 channels can be used as 4 pairs of differential analog input channels
Differential channels include variable gain amplifier for improved dynamic range
Differential channels include programmable pull-up and pull-down resistors for biasing and sensor diagnostics
(200 k100 k5 k
•
Additional internal channels for monitoring voltages (such as core voltage, I/O voltage, LVI voltages, etc.) inside the
device
•
•
An internal bandgap reference to allow absolute voltage measurements
Silicon die temperature sensor
— Provides temperature of silicon as an analog value
— Read using an internal ADC analog channel
— May be read with either ADC
•
2 Decimation Filters
— Programmable decimation factor (1 to 16)
— Selectable IIR or FIR filter
— Up to 4th order IIR or 8th order FIR
— Programmable coefficients
— Saturated or non-saturated modes
— Programmable Rounding (Convergent; Two’s Complement; Truncated)
— Prefill mode to precondition the filter before the sample window opens
— Supports Multiple Cascading Decimation Filters to implement more complex filter designs
— Optional Absolute Integrators on the output of Decimation Filters
Full duplex synchronous serial interface to an external device
— Free-running clock for use by an external device
— Supports a 26-bit message length
•
•
Priority based queues
— Supports six queues with fixed priority. When commands of distinct queues are bound for the same ADC, the
higher priority queue is always served first
— Queue_0 can bypass all prioritization, buffering and abort current conversions to start a Queue_0 conversion a
deterministic time after the queue trigger
— Supports software and hardware trigger modes to arm a particular queue
— Generates interrupt when command coherency is not achieved
External hardware triggers
•
— Supports rising edge, falling edge, high level and low level triggers
— Supports configurable digital filter
1.4.14 DSPI
The deserial serial peripheral interface (DSPI) block provides a synchronous serial interface for communication between the
MPC5644A MCU and external devices. The DSPI supports pin count reduction through serialization and deserialization of
eTPU and eMIOS channels and memory-mapped registers. The channels and register content are transmitted using a SPI-like
protocol. This SPI-like protocol is completely configurable for baud rate, polarity and phase, frame length, chip select assertion,
MPC5644A Microcontroller Data Sheet, Rev. 7
14
Freescale Semiconductor
etc. Each bit in the frame may be configured to serialize either eTPU channels, eMIOS channels or GPIO signals. The DSPI
can be configured to serialize data to an external device that implements the Microsecond Bus protocol. There are three identical
DSPI blocks on the MPC5644A MCU. The DSPI pins support 5 V logic levels or Low Voltage Differential Signalling (LVDS)
to improve high speed operation.
DSPI module features include:
•
•
•
Selectable LVDS pads working at 40 MHZ for SOUT and SCK pins for DSPI_B and DSPI_C
3 sources of serialized data: eTPU_A, eMIOS output channels and memory-mapped register in the DSPI
4 destinations for deserialized data: eTPU_A and eMIOS input channels, SIU external Interrupt input request,
memory-mapped register in the DSPI
•
•
32-bit DSI and TSB modes require 32 PCR registers, 32 GPO and GPI registers in the SIU to select either GPIO, eTPU
or eMIOS bits for serialization
The DSPI Module can generate and check parity in a serial frame
1.4.15 eSCI
Three enhanced serial communications interface (eSCI) modules provide asynchronous serial communications with peripheral
devices and other MCUs, and include support to interface to Local Interconnect Network (LIN) slave devices. Each eSCI block
provides the following features:
•
•
•
•
•
Full-duplex operation
Standard mark/space non-return-to-zero (NRZ) format
13-bit baud rate selection
Programmable 8-bit or 9-bit, data format
Programmable 12-bit or 13-bit data format for Timed Serial Bus (TSB) configuration to support the Microsecond bus
standard
•
•
Automatic parity generation
LIN support
— Autonomous transmission of entire frames
— Configurable to support all revisions of the LIN standard
— Automatic parity bit generation
— Double stop bit after bit error
— 10- or 13-bit break support
•
•
•
Separately enabled transmitter and receiver
Programmable transmitter output parity
2 receiver wake-up methods:
— Idle line wake-up
— Address mark wake-up
•
•
•
•
•
Interrupt-driven operation with flags
Receiver framing error detection
Hardware parity checking
1/16 bit-time noise detection
DMA support for both transmit and receive data
— Global error bit stored with receive data in system RAM to allow post processing of errors
1.4.16 FlexCAN
The MPC5644A MCU includes three controller area network (FlexCAN) blocks. The FlexCAN module is a communication
controller implementing the CAN protocol according to Bosch Specification version 2.0B. The CAN protocol was designed to
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
15
be used primarily as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable
operation in the EMI environment of a vehicle, cost-effectiveness and required bandwidth. Each FlexCAN module contains 64
message buffers.
The FlexCAN modules provide the following features:
•
•
Based on and including all existing features of the Freescale TouCAN module
Full Implementation of the CAN protocol specification, Version 2.0B
— Standard data and remote frames
— Extended data and remote frames
— Zero to eight bytes data length
— Programmable bit rate up to 1 Mbit/s
•
•
•
•
•
•
•
•
Content-related addressing
64 message buffers of zero to eight bytes data length
Individual Rx Mask Register per message buffer
Each message buffer configurable as Rx or Tx, all supporting standard and extended messages
Includes 1088 bytes of embedded memory for message buffer storage
Includes 256-byte memory for storing individual Rx mask registers
Full featured Rx FIFO with storage capacity for six frames and internal pointer handling
Powerful Rx FIFO ID filtering, capable of matching incoming IDs against 8 extended, 16 standard or 32 partial (8 bits)
IDs, with individual masking capability
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Selectable backwards compatibility with previous FlexCAN versions
Programmable clock source to the CAN Protocol Interface, either system clock or oscillator clock
Listen only mode capability
Programmable loop-back mode supporting self-test operation
3 programmable Mask Registers
Programmable transmit-first scheme: lowest ID, lowest buffer number or highest priority
Time Stamp based on 16-bit free-running timer
Global network time, synchronized by a specific message
Maskable interrupts
Warning interrupts when the Rx and Tx Error Counters reach 96
Independent of the transmission medium (an external transceiver is assumed)
Multi-master concept
High immunity to EMI
Short latency time due to an arbitration scheme for high-priority messages
Low power mode, with programmable wake-up on bus activity
1.4.17 FlexRay
The MPC5644A includes one dual-channel FlexRay module that implements the FlexRay Communications System Protocol
Specification, Version 2.1 Rev A. Features include:
•
•
•
Single channel support
FlexRay bus data rates of 10 Mbit/s, 8 Mbit/s, 5 Mbit/s, and 2.5 Mbit/s supported
128 message buffers, each configurable as:
— Receive message buffer
— Single buffered transmit message buffer
— Double buffered transmit message buffer (combines two single buffered message buffer)
2 independent receive FIFOs
•
MPC5644A Microcontroller Data Sheet, Rev. 7
16
Freescale Semiconductor
— 1 receive FIFO per channel
— Up to 255 entries for each FIFO
ECC support
•
1.4.18 System timers
The system timers include two distinct types of system timer:
•
•
Periodic interrupts/triggers using the Periodic Interrupt Timer (PIT)
Operating system task monitors using the System Timer Module (STM)
1.4.18.1 Periodic interrupt timer (PIT)
The PIT provides five independent timer channels, capable of producing periodic interrupts and periodic triggers. The PIT has
no external input or output pins and is intended to provide system ‘tick’ signals to the operating system, as well as periodic
triggers for eQADC queues. Of the five channels in the PIT, four are clocked by the system clock and one is clocked by the
crystal clock. This one channel is also referred to as Real-Time Interrupt (RTI) and is used to wake up the device from low power
stop mode.
The following features are implemented in the PIT:
•
•
•
•
•
5 independent timer channels
Each channel includes 32-bit wide down counter with automatic reload
4 channels clocked from system clock
1 channel clocked from crystal clock (wake-up timer)
Wake-up timer remains active when System STOP mode is entered; used to restart system clock after predefined
time-out period
•
Each channel optionally able to generate an interrupt request or a trigger event (to trigger eQADC queues) when timer
reaches zero
1.4.18.2 System timer module (STM)
1
The System Timer Module (STM) is designed to implement the software task monitor as defined by AUTOSAR . It consists
of a single 32-bit counter, clocked by the system clock, and four independent timer comparators. These comparators produce a
CPU interrupt when the timer exceeds the programmed value.
The following features are implemented in the STM:
•
•
•
•
One 32-bit up counter with 8-bit prescaler
Four 32-bit compare channels
Independent interrupt source for each channel
Counter can be stopped in debug mode
1.4.19 Software watchdog timer (SWT)
The Software Watchdog Timer (SWT) is a second watchdog module to complement the standard Power Architecture watchdog
integrated in the CPU core. The SWT is a 32-bit modulus counter, clocked by the system clock or the crystal clock, that can
provide a system reset or interrupt request when the correct software key is not written within the required time window.
The following features are implemented:
•
•
32-bit modulus counter
Clocked by system clock or crystal clock
1.AUTOSAR: AUTomotive Open System ARchitecture (see http://www.autosar.org)
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
17
•
•
•
•
•
Optional programmable watchdog window mode
Can optionally cause system reset or interrupt request on timeout
Reset by writing a software key to memory mapped register
Enabled out of reset
Configuration is protected by a software key or a write-once register
1.4.20 Cyclic redundancy check (CRC) module
The CRC computing unit is dedicated to the computation of CRC off-loading the CPU. The CRC features:
•
•
•
Support for CRC-16-CCITT (x25 protocol):
16
12
5
— X + X + X + 1
Support for CRC-32 (Ethernet protocol):
32
26
23
22
16
12
11
10
8
7
5
4
2
— X + X + X + X + X + X + X + X + X + X + X + X + X + X + 1
Zero wait states for each write/read operations to the CRC_CFG and CRC_INP registers at the maximum frequency
1.4.21 Error correction status module (ECSM)
The ECSM provides a myriad of miscellaneous control functions regarding program-visible information about the platform
configuration and revision levels, a reset status register, a software watchdog timer, wakeup control for exiting sleep modes,
and information on platform memory errors reported by error-correcting codes and/or generic access error information for
certain processor cores.
The Error Correction Status Module supports a number of miscellaneous control functions for the platform. The ECSM includes
these features:
•
•
Registers for capturing information on platform memory errors if error-correcting codes (ECC) are implemented
For test purposes, optional registers to specify the generation of double-bit memory errors are enabled on the
MPC5644A.
The sources of the ECC errors are:
•
•
•
Flash
SRAM
Peripheral RAM (FlexRay, CAN, eTPU2 Parameter RAM)
1.4.22 External bus interface (EBI)
The MPC5644A device features an external bus interface that is available in 324 TEPBGA and calibration packages.
The EBI supports operation at frequencies of system clock /1, /2 and /4, with a maximum frequency support of 80 MHz.
Customers running the device at 120 MHz or 132 MHz will use the /2 divider, giving an EBI frequency of 60 MHz or 66 MHz.
Customers running the device at 80 MHz will be able to use the /1 divider to have the EBI run at the full 80 MHz frequency.
Features include:
•
•
•
•
•
•
•
•
1.8 V to 3.3 V ± 10% I/O (1.6 V to 3.6 V)
Memory controller with support for various memory types
16-bit data bus, up to 22-bit address bus
Pin muxing included to support 32-bit muxed bus
Selectable drive strength
Configurable bus speed modes
Bus monitor
Configurable wait states
MPC5644A Microcontroller Data Sheet, Rev. 7
18
Freescale Semiconductor
1.4.23 Calibration EBI
The Calibration EBI controls data transfer across the crossbar switch to/from memories or peripherals attached to the VertiCal
connector in the calibration address space. The Calibration EBI is only available in the VertiCal Calibration System.
Features include:
•
•
•
•
•
•
•
•
1.8 V to 3.3 V ± 10% I/O (1.6 V to 3.6 V)
Memory controller supports various memory types
16-bit data bus, up to 22-bit address bus
Pin muxing supports 32-bit muxed bus
Selectable drive strength
Configurable bus speed modes
Bus monitor
Configurable wait states
1.4.24 Power management controller (PMC)
The power management controller contains circuitry to generate the internal 3.3 V supply and to control the regulation of 1.2 V
supply with an external NPN ballast transistor. It also contains low voltage inhibit (LVI) and power-on reset (POR) circuits for
the 1.2 V supply, the 3.3 V supply, the 3.3 V/5 V supply of the closest I/O segment (VDDEH1) and the 5 V supply of the
regulators (VDDREG).
1.4.25 Nexus port controller
The NPC (Nexus Port Controller) block provides real-time Nexus Class3+ development support capabilities for the MPC5644A
Power Architecture-based MCU in compliance with the IEEE-ISTO 5001-2003 and 2010 standards. MDO port widths of 4 pins
and 12 pins are available in all packages.
1.4.26 JTAG
The JTAGC (JTAG Controller) block provides the means to test chip functionality and connectivity while remaining transparent
to system logic when not in test mode. Testing is performed via a boundary scan technique, as defined in the IEEE 1149.1-2001
standard. All data input to and output from the JTAGC block is communicated in serial format. The JTAGC block is compliant
with the IEEE 1149.1-2001 standard and supports the following features:
•
•
IEEE 1149.1-2001 Test Access Port (TAP) interface 4 pins (TDI, TMS, TCK, and TDO)
A 5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions:
— BYPASS, IDCODE, EXTEST, SAMPLE, SAMPLE/PRELOAD, HIGHZ, CLAMP
A 5-bit instruction register that supports the additional following public instructions:
— ACCESS_AUX_TAP_NPC
•
•
— ACCESS_AUX_TAP_ONCE
— ACCESS_AUX_TAP_eTPU
— ACCESS_CENSOR
3 test data registers to support JTAG Boundary Scan mode
— Bypass register
— Boundary scan register
— Device identification register
•
•
A TAP controller state machine that controls the operation of the data registers, instruction register and associated
circuitry
Censorship Inhibit Register
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
19
— 64-bit Censorship password register
— If the external tool writes a 64-bit password that matches the Serial Boot password stored in the internal flash
shadow row, Censorship is disabled until the next system reset.
1.4.27 Development Trigger Semaphore (DTS)
MPC5644A devices include a system development feature, the Development Trigger Semaphore (DTS) module, that enables
software to signal an external tool by driving a persistent (affected only by reset or an external tool) signal on an external device
pin. There is a variety of ways this module can be used, including as a component of an external real-time data acquisition
system
1.5
MPC5644A series architecture
Block diagram
1.5.1
Figure 1 shows a top-level block diagram of the MPC5644A series.
MPC5644A Microcontroller Data Sheet, Rev. 7
20
Freescale Semiconductor
Power ArchitectureTM
e200z4
Interrupt
Controller
JTAG
Nexus Class 3+
SPE
Nexus
IEEE-ISTO
5001-2003/2010
VLE
MMU
eDMA
64 Channel
8 KB I-cache
FlexRay
M4
M0
M1
M6
M7
Crossbar Switch
S0
S1
MPU
S2
S7
Analog PLL
4 MB
Flash
192 KB
SRAM
Voltage Regulator
RCOSC
XOSC
Standby
Regulator
with Switch
ECSM
I/O Bridge
3 KB Data eTPU2
ADCi DEC
x2
eMIOS
24
Channel
32
RAM
Channel
14 KB Code
Nexus
VGA
AMux
RAM
Class 1
LEGEND
ADC
ADCi
– Analog to Digital Converter
– ADC interface
JTAG
MMU
MPU
PMC
PIT
– IEEE 1149.1 test controller
– Memory Management Unit
– Memory Protection Unit
– Power Management Controller
– Periodic Interrupt Timer
AMux – Analog Multiplexer
BAM
CRC
DEC
DTS
DSPI
EBI
– Boot Assist Module
– Cyclic Redundancy Check unit
– Decimation Filter
– Development Trigger Semaphore
– Deserial/Serial Peripheral Interface
– External Bus Interface
RCOSC – low-speed RC oscillator
REACM – Reaction module
SIU
– System Integration Unit
– Signal Processing Extension
SPE
ECSM – Error Correction Status Module
eDMA – Enhanced Direct Memory Access
eMIOS – Enhanced Modular Input Output System
SRAM – Static RAM
STM
SWT
VGA
– System Timer Module
– Software Watchdog Timer
– Variable Gain Amplifier
eSCI
– Enhanced Serial Communications Interface
eTPU2 – Second gen. Enhanced Time Processing Unit VLE
– Variable Length (instruction) Encoding
FlexCAN– Controller Area Network (FlexCAN)
XOSC – XTAL Oscillator
FMPLL – Frequency-Modulated Phase Locked Loop
Figure 1. MPC5644A series block diagram
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
21
1.5.2
Block summary
Table 2 summarizes the functions of the blocks present on the MPC5644A series microcontrollers.
Table 2. MPC5644A series block summary
Block
Function
Boot assist module (BAM)
Block of read-only memory containing executable code that searches
for user-supplied boot code and, if none is found, executes the BAM
boot code resident in device ROM.
Calibration Bus interface
Transfers data across the crossbar switch to/from peripherals attached
to the calibration system connector.
Controller area network (FlexCAN)
Crossbar switch (XBAR)
Supports the standard CAN communications protocol.
Internal busmaster.
Cyclic redundancy check (CRC)
Deserial serial peripheral interface (DSPI)
CRC checksum generator.
Provides a synchronous serial interface for communication with
external devices.
e200z4 core
Executes programs and interrupt handlers.
Enhanced direct memory access (eDMA)
Performs complex data movements with minimal intervention from the
core.
Enhanced modular input-output system
(eMIOS)
Provides the functionality to generate or measure events.
Enhanced queued analog-to-digital
converter (eQADC)
Provides accurate and fast conversions for a wide range of
applications.
Enhanced serial communication interface
(eSCI)
Provides asynchronous serial communication capability with
peripheral devices and other microcontroller units.
Enhanced time processor unit (eTPU2)
Second-generation co-processor processes real-time input events,
performs output waveform generation, and accesses shared data
without host intervention.
Error Correction Status Module (ECSM)
The Error Correction Status Module supports a number of
miscellaneous control functions for the platform, and includes registers
for capturing information on platform memory errors if error-correcting
codes (ECC) are implemented
External bus interface (EBI)
Enables expansion of internal bus to enable connection of external
memory or peripherals.
Flash memory
FlexRay
Provides storage for program code, constants, and variables.
Provides high-speed distributed control for advanced automotive
applications.
Interrupt controller (INTC)
JTAG controller
Provides priority-based preemptive scheduling of interrupt requests.
Provides the means to test chip functionality and connectivity while
remaining transparent to system logic when not in test mode.
Memory protection unit (MPU)
Nexus port controller (NPC)
Provides hardware access control for all memory references
generated.
Provides real-time development support capabilities in compliance
with the IEEE-ISTO 5001-2003 standard.
MPC5644A Microcontroller Data Sheet, Rev. 7
22
Freescale Semiconductor
Table 2. MPC5644A series block summary (continued)
Function
Block
Reaction Module (REACM)
Works in conjunction with the eQADC and eTPU2 to increase system
performance by removing the CPU from the current control loop.
System Integration Unit (SIU)
Controls MCU reset configuration, pad configuration, external
interrupt, general purpose I/O (GPIO), internal peripheral multiplexing,
and the system reset operation.
Static random-access memory (SRAM)
System timers
Provides storage for program code, constants, and variables.
Includes periodic interrupt timer with real-time interrupt; output
compare timer and system watchdog timer.
Temperature sensor
Provides the temperature of the device as an analog value.
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
23
2
Pinout and signal description
This section contains the pinouts for all production packages for the MPC5644A family of devices.
CAUTION
Any pins labeled “NC” are to be left unconnected. Any connection to an external circuit or
voltage may cause unpredictable device behavior or damage.
MPC5644A Microcontroller Data Sheet, Rev. 7
24
Freescale Semiconductor
2.1
176 LQFP pinout
AN[18]
1
VDD
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
AN[17]
2
TMS
AN[16]
3
TDI
AN[11] / ANZ
4
MDO5 / ETPUA4_O / GPIO[76]
AN[9] / ANX
5
TCK
VSS
VDDA
6
VSSA
7
MDO4 / ETPUA2_O / GPIO[75]
AN[39]
8
VDDEH7A
AN[8] / ANW
9
MDO11 / ETPUA29_O / GPIO[82]
VDDREG
10
TDO
VRCCTL
11
GPIO[219]
VSTBY
12
JCOMP
VRC33
13
EVTO
MCKO
14
NC
176-Pin
LQFP
VSS
15
MSEO[0]
NC
16
MSEO[1]
MDO[0]
17
EVTI
MDO[1]
18
VSS
signal details:
MDO[2]
19
DSPI_B_PCS[3] / DSPI_C_SIN / GPIO[108]
MDO[3]
DSPI_B_SOUT / DSPI_C_PCS[5] / GPIO[104]
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
pin 21: ETPUA31 / DSPI_C_PCS[4] / ETPUA13_O / GPIO[145]
pin 22: ETPUA30 / DSPI_C_PCS[3] / ETPUA11_O / GPIO[144]
pin 23: ETPUA29 / DSPI_C_PCS[2] / RCH5_C / GPIO[143]
pin 24: ETPUA28 / DSPI_C_PCS[1] / RCH5_B / GPIO[142]
pin 25: ETPUA27 / IRQ[15] / DSPI_C_SOUT_LVDS+ / SOUTB / GPIO[141]
pin 26: ETPUA26 / IRQ[14] / DSPI_C_SOUT_LVDS- / GPIO[140]
pin 27: ETPUA25 / IRQ[13] / DSPI_C_SCK_LVDS+ / GPIO[139]
pin 28: ETPUA24 / IRQ[12] / DSPI_C_SCK_LVDS- / GPIO[138]
pin 30: ETPUA23 / IRQ[11] / ETPUA21_O / FR_A_TX_EN / GPIO[137]
pin 32: ETPUA22 / IRQ[10] / ETPUA17_O / GPIO[136]
pin 34: ETPUA21 / IRQ[9] / RCH0_C / FR_A_RX / GPIO[135]
pin 35: ETPUA20 / IRQ[8] / RCH0_B / FR_A_TX / GPIO[134]
pin 36: ETPUA19 / DSPI_D_PCS[4] / RCH5_A / GPIO[133]
pin 37: ETPUA18 / DSPI_D_PCS[3] / RCH4_A / GPIO[132]
pin 38: ETPUA17 / DSPI_D_PCS[2] / RCH3_A / GPIO[131]
pin 39: ETPUA16 / DSPI_D_PCS[1] / RCH2_A / GPIO[130]
pin 40: ETPUA15 / DSPI_B_PCS[5] / RCH1_A / GPIO[129]
pin 42: ETPUA14 / DSPI_B_PCS[4] / ETPUA9_O / RCH0_A / GPIO[128]
(see signal details, pin 21)
(see signal details, pin 22)
(see signal details, pin 23)
(see signal details, pin 24)
(see signal details, pin 25)
(see signal details, pin 26)
(see signal details, pin 27)
(see signal details, pin 28)
VSS
DSPI_B_SIN / DSPI_C_PCS[2] / GPIO[103]
DSPI_B_PCS[0] / DSPI_D_PCS[2] / GPIO[105]
VDDEH6B
DSPI_B_PCS[1] / DSPI_D_PCS[0] / GPIO[106]
VSS
DSPI_B_PCS[2] / DSPI_C_SOUT / GPIO[107]
DSPI_B_SCK / DSPI_C_PCS[1] / GPIO[102]
DSPI_B_PCS[4] / DSPI_C_SCK / GPIO[109]
DSPI_B_PCS[5] / DSPI_C_PCS[0] / GPIO[110]
(see signal details, pin 30)
VDDEH1A
(see signal details, pin 32)
VDD
(see signal details, pin 34)
(see signal details, pin 35)
(see signal details, pin 36)
(see signal details, pin 37)
(see signal details, pin 38)
(see signal details, pin 39)
(see signal details, pin 40)
VDDEH1B
VDD
RSTOUT
CAN_C_TX / DSPI_D_PCS3 / GPIO[87]
SCI_A_TX / EMIOS13 / GPIO[89]
SCI_A_RX / EMIOS15 / GPIO[90]
CAN_C_RX / DSPI_D_PCS4 / GPIO[88]
98
RESET
97
VSS
96
VDDEH6A
95
VSS
XTAL
94
93
EXTAL / EXTCLK
92
(see signal details, pin 42)
VSS
VDDPLL
VSS
91
90
NIC
CAN_B_RX / DSPI_C_PCS[4] / SCI_C_RX / GPIO[86]
89
Note: Pin 96 (VSS) should be tied low.
Figure 2. 176-pin LQFP pinout (top view)
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
25
2.2
208 MAP BGA ballmap
1
2
3
4
VDDA1
AN21
5
6
7
AN5
8
9
10
11
12
13
MDO2
14
MDO0
MDO1
VSS
15
16
VSS
VSS
AN9
VSS
VDD
AN39
AN11
VSSA1
AN0
AN1
AN4
AN16
AN2
VRH
AN22
AN7
AN24
VRL
AN27
AN28
AN32
AN31
VSSA0
VDDA0
AN33
AN12-SDS
AN13-SDO
AN14-SDI
VDDEH7
VRC33
VSS
A
B
C
D
A
B
C
D
E
F
VDD
AN8
REFBYPC
AN3
AN25
AN23
AN30
MDO3
VDD
VSTBY
VRC33
VSS
AN17
AN34
AN18
AN15-FCK
VSS
MSEO0
EVTO
EVTI
TCK
VDD
VSS
AN6
AN35
TMS
TDI
NC
ETPUA30 ETPUA31
ETPUA28 ETPUA29
ETPUA24 ETPUA27
ETPUA23 ETPUA22
ETPUA20 ETPUA19
ETPUA16 ETPUA15
AN37
VDD
NC
MSEO1
JCOMP
E
F
ETPUA26
ETPUA25
ETPUA17
ETPUA14
ETPUA7
ETPUA6
ETPUA1
ETPUA0
VSS
AN36
VDDEH6AB
TDO
MCKO
DSPI_B_
SOUT
DSPI_B_
PCS3
DSPI_B_
SIN
DSPI_B_
PCS0
ETPUA21
ETPUA18
ETPUA13
VDDEH1AB
TCRCLKA
ETPUA5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
G
H
J
G
H
J
DSPI_B_
PCS4
DSPI_B_
PCS2
DSPI_B_
PCS1
GPIO99
DSPI_B_
PCS5
DSPI_B_
SCK
SCI_A_TX
GPIO98
RSTOUT
WKPCFG
BOOTCFG1
NC
CAN_C_TX SCI_A_RX
VDDREG
RESET
VSS
K
L
K
L
CAN_C_
ETPUA12
ETPUA10
ETPUA8
ETPUA3
NC
ETPUA11
ETPUA9
ETPUA4
ETPUA2
VSS
SCI_B_TX
RX
SCI_B_RX
PLLREF
VRCCTL
VSS
M
N
P
R
T
M
N
P
R
T
MDO7_
ETPUA19_O
1
VDD
GPIO207
EMIOS4
EMIOS1
5
VRC33
NC
EMIOS2
EMIOS6
EMIOS9
EMIOS10
EMIOS8
EMIOS11
EMIOS13
8
VDDEH4AB
MDO11_
EMIOS12
MDO4_
VRC33
VSS
EXTAL
XTAL
MDO8_
VDD
CAN_A_TX
VDD
NC
ETPUA29_O ETPUA2_O ETPUA21_O
MDO10_
VDD
GPIO206
EMIOS0
4
EMIOS3
GPIO219
6
EMIOS14
EMIOS15
9
EMIOS23
MDO6_
CAN_A_RX CAN_B_RX
VDD
VSS
VDDPLL
VSS
ETPUA27_O
MDO5_
MDO9_
ETPUA25_O
VSS
VDD
NC
CAN_B_TX
12
VDDE5
13
ENGCLK
14
VDD
ETPUA4_O ETPUA13_O
1
2
3
7
10 11
15
16
1
This pin (N13) should be tied low.
Figure 3. 208-pin MAPBGA package ballmap (viewed from above)
2.3
324 TEPBGA ballmap
1
2
3
4
5
6
7
8
9
10
VRH
11
A
B
C
VSS
VDD
VSS
AN16
VDD
VSS
AN17
AN18
VDD
AN37
AN36
AN20
VDDA1
AN21
AN0
VSSA1
AN4
AN23
AN5
AN6
AN25
AN24
AN7
VRL
VRC33
AN11
REFBYPC
AN27
AN30
AN29
AN9
ANX
AN1
AN10
ANY
D
AN39
AN38
VSS
VDD
AN19
AN2
AN3
AN22
AN26
AN28
AN8
ANW
E
F
G
H
J
VSSA0
VRCCTL
MDO1
CS2
VDDA0
MDO0
MDO2
OE
VSTBY
VDDREG
MDO3
MCKO
CS0
CS1
CS3
WE1
WE0
BDIP
RD_WR
VDDEH1AB
ETPUA30
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K
L
ETPUA31
ETPUA27
TA
TS
ETPUA26
ETPUA29
Figure 4. 324-pin TEPBGA package ballmap (northwest, viewed from above)
M
N
ETPUA23
ADDR13
ADDR14
ADDR18
ADDR21
ADDR25
ADDR29
ETPUA20
ETPUA17
ETPUA15
VSS
ETPUA24
ADDR12
ADDR15
ADDR19
ADDR22
ADDR26
VDDE-EH
ETPUA19
ETPUA16
ETPUA14
ETPUA13
2
ETPUA25
ETPUA22
ADDR16
VDDE-EH
ADDR23
ADDR27
ADDR30
ETPUA18
VSS
ETPUA28
ETPUA21
ADDR17
ADDR20
ADDR24
ADDR28
ADDR31
VSS
VDDE2
VSS
VDDE2
VSS
VSS
VDDE5
VRC33
P
VSS
VSS
R
T
U
V
W
Y
VDDE5
DATA0
DATA1
DATA2
5
DATA6
DATA5
DATA4
DATA3
6
DATA10
DATA9
DATA8
DATA7
7
VDDE5
DATA13
DATA12
DATA11
8
DATA14
DATA15
ETPUA9
CLKOUT
9
ENGCLK
ETPUA8
ETPUA7
ETPUA6
10
ETPUA4
ETPUA3
ETPUA2
ETPUA5
11
VDD
AA
AB
VDD
ETPUA10
ETPUA11
4
ETPUA12
3
1
Figure 5. 324-pin TEPBGA package ballmap (southwest, viewed from above)
12
13
14
15
16
17
18
19
20
21
VDD
22
VSS
DSPI_A_
PCS5
DSPI_A_
SOUT
MDO8_
ETPUA21_O ETPUA27_O
MDO10_
AN34
AN33
AN32
AN31
AN14-SDI
AN13-SDO
AN12-SDS
AN35
AN15-FCK
GPIO207
GPIO206
GPIO204
GPIO203
GPIO99
GPIO98
VDDEH7
VDD
A
B
C
DSPI_A_
PCS4
MDO7_
ETPUA19_O ETPUA2_O
MDO4_
MDO5_
ETPUA4_O
DSPI_A_SIN
DSPI_A_SCK
VSS
VSS
VDDEH7
VDD
DSPI_A_
PCS1
MDO6_
ETPUA13_O ETPUA29_O
MDO11_
VSS
VDDEH7
DSPI_A_
PCS0
MDO9_
VSS
VDDEH7
TMS
TCK
TDO
TDI
NC
D
E
F
G
H
J
ETPUA25_O
VDDEH7
VDDEH7
RDY
JCOMP
EVTO
EVTI
VSS
NC
MSEO0
VSS
MSEO1
DSPI_B_SIN
VDDEH7
DSPI_B_
SOUT
DSPI_B_
PCS3
DSPI_B_
PCS0
DSPI_B_
PCS1
VSS
VSS
VSS
VSS
VSS
VSS
VDDEH7
VSS
DSPI_B_
PCS4
DSPI_B_
PCS2
NC
DSPI_B_SCK
VSS
K
L
DSPI_B_
PCS5
VSS
NC
NC
Figure 6. 324-pin TEPBGA package ballmap (northeast, viewed from above)
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VRC33
NC
NC
SCI_A_TX
SCI_A_RX
NC
NC
VSS
VDDEH6AB
NC
M
N
CAN_C_TX
NC
RSTOUT
NC
RSTCFG
RESET
VSS
P
R
1
VSS
BOOTCFG0
PLLCFG1
CAN_C_RX
VDD
VSS
T
VDDEH6AB
SCI_C_RX
SCI_C_TX
CAN_A_RX
VDDEH4AB
CAN_A_TX
19
BOOTCFG1
PLLREF
CAN_B_RX
VDD
EXTAL
XTAL
U
V
ETPUA1
ETPUA0
EMIOS0
TCRCLKA
12
EMIOS1
EMIOS2
EMIOS3
EMIOS4
13
VDDEH4AB
EMIOS5
EMIOS6
EMIOS7
14
EMIOS8
EMIOS9
EMIOS10
EMIOS11
15
EMIOS15
EMIOS14
EMIOS13
EMIOS12
16
EMIOS16
EMIOS17
EMIOS18
EMIOS19
17
EMIOS23
EMIOS22
EMIOS21
EMIOS20
18
VDDPLL
CAN_B_TX
VDD
W
Y
VSS
WKPCFG
SCI_B_RX
20
VSS
AA
AB
SCI_B_TX
21
VSS
22
1
This pin (T21) should be tied low.
Figure 7. 324-pin TEPBGA package ballmap (southeast, viewed from above)
2.4
Signal summary
Table 3. MPC5644A signal properties
Status7
Package pin #
P
A
PCR
I/O
Voltage5 /
Name
Function1
PA PCR4
Type Pad Type6
After
Reset
G2 Field3
During Reset
176
208
324
GPIO
EMIOS148
GPIO[203]
eMIOS channel
GPIO
P
G
01
00
203
204
206
207
O
I/O
VDDEH7
Slow
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
—/ Up
— / Up
— / Up
— / Up
—
—
—
—
A15
D14
C14
B14
EMIOS158
GPIO[204]
eMIOS channel
GPIO
P
G
01
00
O
I/O
VDDEH7
Slow
GPIO[206] ETRIG0 GPIO / eQADC Trigger Input
G
G
G
00
00
—
I/O9
I/O9
VDDEH7
Slow10
143 R4
144 P5
122 T6
GPIO[207] ETRIG1 GPIO / eQADC Trigger Input
VDDEH7
Slow
GPIO[219]
GPIO
21911 I/O
VDDEH7
MultiV12
—
Reset / Configuration
RESET
External Reset Input
External Reset Output
P
P
P
—
01
—
I
VDDEH6
Slow
RESET / Up
RESET / Up
97
L16
R22
P21
V21
RSTOUT
230
208
O
VDDEH6
Slow
RSTOUT /
Down
RSTOUT / Down 102 K15
PLLREF
IRQ[4]
ETRIG2
GPIO[208]
FMPLL Mode Selection
External Interrupt Request
eQADC Trigger Input
GPIO
001
I
I
I
VDDEH6
Slow
— / Up
PLLREF / Up
— / Up
—
83
M14
A1 010
A2 100
G
000
I/O
PLLCFG113
IRQ[5]
DSPI_D_SOUT
GPIO[209]
—
—
—
209
—
I
O
VDDEH6
Medium
— / Up
—
—
U20
External interrupt request
DSPI D data output
GPIO
A1 010
A2 100
G
000
I/O
RSTCFG
GPIO[210]
RSTCFG
GPIO
P
G
01
00
210
211
I
VDDEH6
Slow
— / Down
— / Down
—
—
—
—
P22
T20
I/O
BOOTCFG[0]
IRQ[2]
GPIO[211]
Boot Config. Input
External Interrupt Request
GPIO
P
A1
G
01
10
00
I
I
VDDEH6
Slow
BOOTCFG[0] /
Down
I/O
Table 3. MPC5644A signal properties (continued)
Status7
Package pin #
P
A
PCR
I/O
Type Pad Type6
Voltage5 /
Name
Function1
PA PCR4
After
Reset
G2 Field3
During Reset
176
208
M15
324
BOOTCFG[1]
IRQ[3]
ETRIG3
Boot Config. Input
P
001
212
213
I
I
I
VDDEH6
Slow
— / Down
BOOTCFG[1] / 85
Down
U21
External Interrupt Request
eQADC Trigger Input
GPIO
A1 010
A2 100
G
GPIO[212]
000
I/O
WKPCFG
NMI
DSPI_B_SOUT
GPIO[213]
Weak Pull Config. Input
Non-Maskable Interrupt
DSPI D data output
GPIO
P
001
I
I
VDDEH6
Medium
— / Up
WKPCFG / Up 86
L15
AA20
A1 010
A2 100
G
O
I/O
000
External Bus Interface
CS[0]
ADDR[8]
GPIO[0]
External chip selects
External address bus
GPIO
P
A1
G
01
10
00
0
1
2
O
I/O
I/O
VDDE2
Fast
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
—
—
G1
H1
H2
CS[1]
ADDR9
GPIO[1]
External chip selects
External address bus
GPIO
P
A1
G
01
10
00
O
I/O
I/O
VDDE2
Fast
—
—
—
—
CS[2]
ADDR10
WE[2]/BE[2]
External chip selects
External address bus
Write/byte enable
P
0001
O
I/O
O
VDDE2
Fast
A1 0010
A2 0100
A3 1000
CAL_WE[2]/BE[2] Cal. bus write/byte enable
O
GPIO[2]
GPIO
G
0000
I/O
CS[3]
ADDR11
WE[3]/BE[3]
External chip selects
External address bus
Write/byte enable
P
0001
3
O
I/O
O
VDDE2
Fast
— / Up
— / Up
—
—
H4
A1 0010
A2 0100
A3 1000
CAL_WE[3]/BE[3] Cal bus write/byte enable
O
GPIO[3]
GPIO
G
0000
I/O
ADDR12
GPIO[8]
External address bus
GPIO
P
G
01
00
8
9
I/O
I/O
VDDE3
Fast
— / Up
— / Up
— / Up
— / Up
—
—
—
—
N2
N1
ADDR13
WE[2]
GPIO[9]
External address bus
Write/byte enable
GPIO
P
001
I/O
O
I/O
VDDE3
Fast
A2 100
G
000
ADDR14
WE[3]
GPIO[10]
External address bus
Write/byte enables
GPIO
P
001
10
11
I/O
O
I/O
VDDE3
Fast
— / Up
— / Up
— / Up
— / Up
—
—
—
—
P1
P2
A2 100
G
000
ADDR15
GPIO[11]
External address bus
GPIO
P
G
01
00
I/O
I/O
VDDE3
Fast
Table 3. MPC5644A signal properties (continued)
Status7
Package pin #
P
A
PCR
I/O
Type Pad Type6
Voltage5 /
Name
Function1
PA PCR4
After
Reset
G2 Field3
During Reset
176
208
324
ADDR16
FR_A_TX
DATA16
External address bus
Flexray TX data channel A
External data bus
GPIO
P
001
12
13
14
15
16
17
I/O
O
I/O
I/O
VDDE-EH
Medium
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
—
—
P3
P4
R1
R2
R4
T1
A1 010
A2 100
G
GPIO[12]
000
ADDR17
FR_A_TX_EN
DATA17
External address bus
FlexRay ch. A TX data enable
External data bus
GPIO
P
001
I/O
O
I/O
I/O
VDDE-EH
Medium
—
—
—
—
—
—
—
—
—
—
A1 010
A2 100
G
GPIO[13]
000
ADDR18
FR_A_RX
DATA18
External address bus
Flexray RX data ch. A
External data bus
GPIO
P
001
I/O
I
I/O
I/O
VDDE-EH
Medium
A1 010
A2 100
G
GPIO[14]
000
ADDR19
FR_B_TX
DATA19
External address bus
Flexray TX data ch. B
External data bus
GPIO
P
001
I/O
O
I/O
I/O
VDDE-EH
Medium
A1 010
A2 100
G
GPIO[15]
000
ADDR20
FR_B_TX_EN
DATA20
External address bus
Flexray TX data enable for ch. B A1 010
External data bus
GPIO
P
001
I/O
O
I/O
I/O
VDDE-EH
Medium
A2 100
G
GPIO[16]
000
ADDR21
FR_B_RX
DATA21
External address bus
Flexray RX data channel B
External data bus
GPIO
P
001
I/O
I
I/O
I/O
VDDE-EH
Medium
A1 010
A2 100
G
GPIO[17]
000
ADDR22
DATA22
GPIO[18]
External address bus
External data bus
GPIO
P
001
18
19
20
21
I/O
I/O
I/O
VDDE-EH
Medium
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
—
—
—
—
—
—
—
—
T2
T3
T4
U1
A2 100
G
000
ADDR23
DATA23
GPIO[19]
External address bus
External data bus
GPIO
P
001
I/O
I/O
I/O
VDDE-EH
Medium
A2 100
G
000
ADDR24
DATA24
GPIO[20]
External address bus
External data bus
GPIO
P
001
I/O
I/O
I/O
VDDE-EH
Medium
A2 100
G
000
ADDR25
DATA25
GPIO[21]
External address bus
External data bus
GPIO
P
001
I/O
I/O
I/O
VDDE-EH
Medium
A2 100
000
G
Table 3. MPC5644A signal properties (continued)
Status7
Package pin #
P
A
PCR
I/O
Type Pad Type6
Voltage5 /
Name
Function1
PA PCR4
After
Reset
G2 Field3
During Reset
176
208
324
ADDR26
DATA26
GPIO[22]
External address bus
External data bus
GPIO
P
001
22
23
24
25
26
I/O
I/O
I/O
VDDE-EH
Medium
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
—
—
U2
U3
U4
V1
V3
A2 100
G
P
000
001
ADDR27
DATA27
GPIO[23]
External address bus
External data bus
GPIO
I/O
I/O
I/O
VDDE-EH
Medium
—
—
—
—
—
—
—
—
A2 100
G
000
ADDR28
DATA28
GPIO[24]
External address bus
External data bus
GPIO
P
001
I/O
I/O
I/O
VDDE-EH
Medium
A2 100
G
000
ADDR29
DATA29
GPIO[25]
External address bus
External data bus
GPIO
P
001
I/O
I/O
I/O
VDDE-EH
Medium
A2 100
G
000
ADDR30
ADDR68
DATA30
GPIO[26]
External address bus
External address bus
External data bus
GPIO
P
001
I/O
O
I/O
I/O
VDDE-EH
Medium
A1 010
A2 100
G
000
ADDR31
ADDR78
DATA31
GPIO[27]
External address bus
External address bus
External data bus
GPIO
P
001
27
I/O
O
I/O
I/O
VDDE-EH
Medium
— / Up
— / Up
—
—
V4
A1 010
A2 100
G
000
DATA0
ADDR16
GPIO[28]
External data bus
External address bus
GPIO
P
001
28
29
30
31
32
I/O
I/O
I/O
VDDE5
Fast
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
—
—
—
—
—
—
—
—
—
—
Y5
A1 010
G
000
DATA1
ADDR17
GPIO[29]
External data bus
External address bus
GPIO
P
001
I/O
I/O
I/O
VDDE5
Fast
AA5
AB5
AB6
AA6
A1 010
G
000
DATA2
ADDR18
GPIO[30]
External data bus
External address bus
GPIO
P
001
I/O
I/O
I/O
VDDE5
Fast
A1 010
G
000
DATA3
ADDR19
GPIO[31]
External data bus
External address bus
GPIO
P
001
I/O
I/O
I/O
VDDE5
Fast
A1 010
G
000
DATA4
ADDR20
GPIO[32]
External data bus
External address bus
GPIO
P
001
I/O
I/O
I/O
VDDE5
Fast
A1 010
000
G
Table 3. MPC5644A signal properties (continued)
Status7
Package pin #
P
A
PCR
I/O
Type Pad Type6
Voltage5 /
Name
Function1
PA PCR4
After
Reset
G2 Field3
During Reset
176
208
324
DATA5
ADDR21
GPIO[33]
External data bus
External address bus
GPIO
P
001
33
34
35
36
37
38
39
40
41
42
43
62
I/O
I/O
I/O
VDDE5
Fast
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
—
—
Y6
A1 010
G
P
000
001
DATA6
ADDR22
GPIO[34]
External data bus
External address bus
GPIO
I/O
I/O
I/O
VDDE5
Fast
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
W6
AB7
AA7
Y7
A1 010
G
000
DATA7
ADDR23
GPIO[35]
External data bus
External address bus
GPIO
P
001
I/O
I/O
I/O
VDDE5
Fast
A1 010
G
000
DATA8
ADDR24
GPIO[36]
External data bus
External address bus
GPIO
P
001
I/O
I/O
I/O
VDDE5
Fast
A1 010
G
000
DATA9
ADDR25
GPIO[37]
External data bus
External address bus
GPIO
P
001
I/O
I/O
I/O
VDDE5
Fast
A1 010
G
000
DATA10
ADDR26
GPIO[38]
External data bus
External address bus
GPIO
P
001
I/O
I/O
I/O
VDDE5
Fast
W7
AB8
AA8
Y8
A1 010
G
000
DATA11
ADDR27
GPIO[39]
External data bus
External address bus
GPIO
P
001
I/O
I/O
I/O
VDDE5
Fast
A1 010
G
000
DATA12
ADDR28
GPIO[40]
External data bus
External address bus
GPIO
P
001
I/O
I/O
I/O
VDDE5
Fast
A1 010
G
000
DATA13
ADDR29
GPIO[41]
External data bus
External address bus
GPIO
P
001
I/O
I/O
I/O
VDDE5
Fast
A1 010
G
000
DATA14
ADDR30
GPIO[42]
External data bus
External address bus
GPIO
P
001
I/O
I/O
I/O
VDDE5
Fast
W9
Y9
A1 010
G
000
DATA15
ADDR31
GPIO[43]
External data bus
External address bus
GPIO
P
001
I/O
I/O
I/O
VDDE5
Fast
A1 010
G
000
RD_WR
GPIO[62]
External read/write
GPIO
P
G
01
00
I/O
I/O
VDDE2
Fast
J4
Table 3. MPC5644A signal properties (continued)
Status7
Package pin #
P
A
PCR
I/O
Type Pad Type6
Voltage5 /
Name
Function1
PA PCR4
After
Reset
G2 Field3
During Reset
176
208
324
BDIP
GPIO[63]
External burst data in progress
GPIO
P
G
01
00
63
64
65
68
69
O
I/O
VDDE2
Fast
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
—
—
J3
J2
J1
H3
K3
WE[0]/BE[0]
GPIO[64]
External write/byte enable
GPIO
P
G
01
00
O
I/O
VDDE2
Fast
—
—
—
—
—
—
—
—
WE[1]/BE[1]
GPIO[65]
External write/byte enable
GPIO
P
G
01
00
O
I/O
VDDE2
Fast
OE
GPIO[68]
External output enable
GPIO
P
G
01
00
O
I/O
VDDE2
Fast
TS
ALE
GPIO[69]
External transfer start
Address latch enable
GPIO[69]
P
001
I/O
O
I/O
VDDE2
Fast
A1 010
G
000
TA
External transfer acknowledge
External transfer start
GPIO
P
001
70
I/O
O
I/O
VDDE2
Fast
— / Up
— / Up
—
—
K2
TS8
A1 010
G
GPIO[70]
000
Calibration Bus
CAL_CS0
Calibration chip select
P
01
336
338
O
VDDE12
Fast
— / —
— / —
—
—
—
—
—
—
CAL_CS2
CAL_ADDR[10]
CAL_WE[2]/BE[2] Calibration write/byte enable
Calibration chip select
Calibration address bus
P
A
001
010
O
I/O
O
VDDE12
Fast
A2 100
CAL_CS3
CAL_ADDR[11]
CAL_WE[3]/BE[3] Calibration write/byte enable
Calibration chip select
Calibration address bus
P
A
001
010
339
O
I/O
O
VDDE12
Fast
— / —
—
—
—
A2 100
CAL_ADDR[12] Calibration address bus
P
A
01
10
340
340
340
340
345
I/O
O
VDDE12
Fast
— / —
— / —
— / —
— / —
— / —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CAL_WE[2]/BE[2] Calibration write/byte enable
CAL_ADDR[13] Calibration address bus
P
A
01
10
I/O
O
VDDE12
Fast
CAL_WE[3]/BE[3] Calibration write/byte enable
CAL_ADDR[14]
CAL_DATA[31]
Calibration address bus
Calibration data bus
P
A
01
10
I/O
I/O
VDDE12
Fast
CAL_ADDR[15]
CAL_ALE
Calibration address bus
Calibration address latch enable A1
P
01
10
I/O
O
VDDE12
Fast
CAL_ADDR[16]
CAL_DATA[16]
Calibration address bus
Calibration data bus
P
A
01
10
I/O
I/O
VDDE12
Fast
Table 3. MPC5644A signal properties (continued)
Status7
Package pin #
P
A
PCR
I/O
Type Pad Type6
Voltage5 /
Name
Function1
PA PCR4
After
Reset
G2 Field3
During Reset
176
208
324
CAL_ADDR[17]
CAL_DATA[17]
Calibration address bus
Calibration data bus
P
A
01
10
345
345
345
345
345
345
345
345
345
345
345
345
345
345
341
341
I/O
I/O
VDDE12
Fast
— / —
— / —
— / —
— / —
— / —
— / —
— / —
— / —
— / —
— / —
— / —
— / —
— / —
— / —
— / Up
— / Up
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CAL_ADDR[18]
CAL_DATA[18]
Calibration address bus
Calibration data bus
P
A
01
10
I/O
I/O
VDDE12
Fast
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CAL_ADDR[19]
CAL_DATA[19]
Calibration address bus
Calibration data bus
P
A
01
10
I/O
I/O
VDDE12
Fast
CAL_ADDR[20]
CAL_DATA[20]
Calibration address bus
Calibration data bus
P
A
01
10
I/O
I/O
VDDE12
Fast
CAL_ADDR[21]
CAL_DATA[21]
Calibration address bus
Calibration data bus
P
A
01
10
I/O
I/O
VDDE12
Fast
CAL_ADDR[22]
CAL_DATA[22]
Calibration address bus
Calibration data bus
P
A
01
10
I/O
I/O
VDDE12
Fast
CAL_ADDR[23]
CAL_DATA[23]
Calibration address bus
Calibration data bus
P
A
01
10
I/O
I/O
VDDE12
Fast
CAL_ADDR[24]
CAL_DATA[24]
Calibration address bus
Calibration data bus
P
A
01
10
I/O
I/O
VDDE12
Fast
CAL_ADDR[25]
CAL_DATA[25]
Calibration address bus
Calibration data bus
P
A
01
10
I/O
I/O
VDDE12
Fast
CAL_ADDR[26]
CAL_DATA[26]
Calibration address bus
Calibration data bus
P
A
01
10
I/O
I/O
VDDE12
Fast
CAL_ADDR[27]
CAL_DATA[27]
Calibration address bus
Calibration data bus
P
A
01
10
I/O
I/O
VDDE12
Fast
CAL_ADDR[28]
CAL_DATA[28]
Calibration address bus
Calibration data bus
P
A
01
10
I/O
I/O
VDDE12
Fast
CAL_ADDR[29]
CAL_DATA[29]
Calibration address bus
Calibration data bus
P
A
01
10
I/O
I/O
VDDE12
Fast
CAL_ADDR[30]
CAL_DATA[30]
Calibration address bus
Calibration data bus
P
A
01
10
I/O
I/O
VDDE12
Fast
CAL_DATA[0]
Calibration data bus
P
01
I/O
VDDE12
Fast
— / Up
— / Up
CAL_DATA[1]
Calibration data bus
P
01
I/O
VDDE12
Fast
Table 3. MPC5644A signal properties (continued)
Status7
Package pin #
P
A
PCR
I/O
Type Pad Type6
Voltage5 /
Name
Function1
PA PCR4
After
Reset
G2 Field3
During Reset
176
208
324
CAL_DATA[2]
CAL_DATA[3]
CAL_DATA[4]
CAL_DATA[5]
CAL_DATA[6]
CAL_DATA[7]
CAL_DATA[8]
CAL_DATA[9]
CAL_DATA[10]
CAL_DATA[11]
CAL_DATA[12]
CAL_DATA[13]
CAL_DATA[14]
CAL_DATA[15]
CAL_RD_WR
Calibration data bus
Calibration data bus
Calibration data bus
Calibration data bus
Calibration data bus
Calibration data bus
Calibration data bus
Calibration data bus
Calibration data bus
Calibration data bus
Calibration data bus
Calibration data bus
Calibration data bus
Calibration data bus
Calibration read/write enable
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
341
341
341
341
341
341
341
341
341
341
341
341
341
341
342
342
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
VDDE12
Fast
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / —
— / —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDDE12
Fast
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDDE12
Fast
VDDE12
Fast
VDDE12
Fast
VDDE12
Fast
VDDE12
Fast
VDDE12
Fast
VDDE12
Fast
VDDE12
Fast
VDDE12
Fast
VDDE12
Fast
VDDE12
Fast
VDDE12
Fast
VDDE12
Fast
CAL_WE[0]/BE[0] Calibration write/byte enable
O
VDDE12
Fast
Table 3. MPC5644A signal properties (continued)
Status7
Package pin #
P
A
PCR
I/O
Type Pad Type6
Voltage5 /
Name
Function1
PA PCR4
After
Reset
G2 Field3
During Reset
176
208
324
CAL_WE[1]/BE[1] Calibration write/byte enable
P
P
01
01
342
342
343
—
O
O
VDDE12
Fast
— / —
— / —
— / —
—
—
—
—
—
—
—
—
—
—
—
—
—
CAL_OE
Calibration output enable
VDDE12
Fast
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CAL_TS
CAL_ALE
Calibration transfer start
Address Latch Enable
P
A
01
10
O
O
VDDE12
Fast
CAL_MDO[4]
CAL_MDO[5]
CAL_MDO[6]
CAL_MDO[7]
CAL_MDO[8]
CAL_MDO[9]
CAL_MDO[10]
CAL_MDO[11]
Calibration Nexus Message
Data Out
P
P
P
P
P
P
P
P
01
01
01
01
01
01
01
01
O
O
O
O
O
O
O
O
VDDE12
Fast
—
—
—
—
—
—
—
—
CAL_MDO[4] / —
CAL_MDO[5] / —
CAL_MDO[6] / —
CAL_MDO[7] / —
CAL_MDO[8] / —
CAL_MDO[9] / —
Calibration Nexus Message
Data Out
—
VDDE12
Fast
Calibration Nexus Message
Data Out
—
VDDE12
Fast
Calibration Nexus Message
Data Out
—
VDDE12
Fast
Calibration Nexus Message
Data Out
—
VDDE12
Fast
Calibration Nexus Message
Data Out
—
VDDE12
Fast
Calibration Nexus Message
Data Out
—
VDDE12
Fast
CAL_MDO[10] /
—
Calibration Nexus Message
Data Out
—
VDDE12
Fast
CAL_MDO[11] /
—
NEXUS
EVTI
Nexus event in
P
P
P
P
P
01
01
—
01
01
231
227
I
VDDEH7
— / Up
—
EVTI / Up
EVTO / —
MCKO / —
MDO[0] / —
MDO[1] / —
116 E15
120 D15
H20
G20
F1
MultiV12,14
EVTO
Nexus event out
O
O
O
O
VDDEH7
MultiV12,14,15
MCKO
MDO016
MDO116
Nexus message clock out
Nexus message data out
Nexus message data out
21911
220
VRC33
Fast
—
14
17
18
F15
A14
B14
VRC33
Fast
—
F3
221
VRC33
Fast
—
G2
Table 3. MPC5644A signal properties (continued)
Status7
Package pin #
P
A
PCR
I/O
Type Pad Type6
Voltage5 /
Name
Function1
PA PCR4
After
Reset
G2 Field3
During Reset
176
19
208
A13
324
MDO216
Nexus message data out
Nexus message data out
P
P
01
01
222
223
75
O
O
VRC33
Fast
—
MDO[2] / —
MDO[3] / —
— / —
G3
MDO316
VRC33
Fast
—
—
20
B13
G4
MDO416
Nexus message data out
eTPU A channel (output only)
GPIO[
P
A1
G
01
10
00
O
O
VDDEH7
126 P10
129 T10
135 T11
136 N11
137 P11
139 T7
B19
ETPUA2_O8
GPIO[75]
MultiV12,14
I/O
MDO516
Nexus message data out
eTPU A channel (output only)
GPIO
P
A1
G
01
10
00
76
77
78
79
80
81
82
O
O
VDDEH7
—
—
—
—
—
—
—
— / —
— / —
— / —
— / —
— / —
— / —
— / —
B20
C18
B18
A18
D18
A19
C19
ETPUA4_O8
GPIO[76]
MultiV12,14
I/O
MDO616
Nexus message data out
eTPU A channel (output only)
GPIO
P
A1
G
01
10
00
O
O
VDDEH7
ETPUA13_O8
GPIO[77]
MultiV12,14
I/O
MDO716
Nexus message data out
eTPU A channel (output only)
GPIO
P
A1
G
01
10
00
O
O
VDDEH7
ETPUA19_O8
GPIO[78]
MultiV12,14
I/O
MDO816
Nexus message data out
eTPU A channel (output only)
GPIO
P
A1
G
01
10
00
O
O
VDDEH7
ETPUA21_O8
GPIO[79]
MultiV12,14
I/O
MDO916
Nexus message data out
eTPU A channel (output only)
GPIO
P
A1
G
01
10
00
O
O
VDDEH7
ETPUA25_O8
GPIO[80]
MultiV12,14
I/O
MDO1016
Nexus message data out
eTPU A channel (output only)
GPIO
P
A1
G
01
10
00
O
O
VDDEH7
134 R10
124 P9
ETPUA27_O8
GPIO[81]
MultiV12,14
I/O
MDO1116
Nexus message data out
eTPU A channel (output only)
GPIO[82]
P
A1
G
01
10
00
O
O
VDDEH7
ETPUA29_O8
GPIO[82]
MultiV12,14
I/O
MSEO[0]16
MSEO[1]16
RDY
Nexus message start/end out
Nexus message start/end out
Nexus ready output
P
P
P
01
01
01
224
225
226
O
O
O
VDDEH7
—
—
—
MSEO[0] / —
MSEO[1] / —
—
118 C15
117 E16
G21
G22
G19
MultiV12,14
VDDEH7
MultiV12,14
VDDEH7
—
—
MultiV12,14
JTAG
Table 3. MPC5644A signal properties (continued)
Status7
Package pin #
P
A
PCR
I/O
Type Pad Type6
Voltage5 /
Name
Function1
PA PCR4
After
Reset
G2 Field3
During Reset
176
208
324
TCK
TDI
JTAG test clock input
P
P
P
P
P
01
01
01
01
01
—
232
228
—
I
I
VDDEH7
MultiV12
TCK / Down
TCK / Down
TDI / Up
128 C16
130 E14
123 F14
131 D14
D21
D22
E21
E20
F20
JTAG test data input
VDDEH7
MultiV12
TDI / Up
TDO / Up
TMS / Up
TDO
TMS
JTAG test data output
JTAG test mode select input
JTAG TAP controller enable
O
I
VDDEH7
MultiV12
TDO / Up
TMS / Up
VDDEH7
MultiV12
JCOMP
—
I
VDDEH7
MultiV12
JCOMP / Down JCOMP / Down 121 F16
FlexCAN
CAN_A_TX
SCI_A_TX
GPIO[83]
FlexCAN A TX
eSCI A TX
GPIO
P
A1
G
01
10
00
83
84
85
O
O
I/O
VDDEH6
Slow
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
81
82
88
P12
R12
T12
AB19
Y19
CAN_A_RX
SCI_A_RX
GPIO[84]
FlexCAN A RX
eSCI A RX
GPIO
P
A1
G
01
10
00
I
I
VDDEH6
Slow
I/O
CAN_B_TX
DSPI_C_PCS[3]
SCI_C_TX
FlexCAN B TX
DSPI C peripheral chip select
eSCI C TX
P
001
O
O
O
VDDEH6
Slow
Y22
A1 010
A2 100
GPIO[85]
GPIO
G
000
I/O
CAN_B_RX
DSPI_C_PCS[4]
SCI_C_RX
FlexCAN B RX
DSPI C peripheral chip select
eSCI C RX
P
001
86
I
O
I
VDDEH6
Slow
— / Up
— / Up
89
R13
W21
A1 010
A2 100
GPIO[86]
GPIO
G
000
I/O
CAN_C_TX
DSPI_D_PCS[3]
GPIO[87]
FlexCAN C TX
DSPI D peripheral chip select
GPIO
P
A1
G
01
10
00
87
88
O
O
I/O
VDDEH6
Medium
— / Up
— / Up
— / Up
— / Up
101 K13
P19
V20
CAN_C_RX
DSPI_D_PCS[4]
GPIO[88]
FlexCAN C RX
DSPI D peripheral chip select
GPIO
P
A1
G
01
10
00
I
O
I/O
VDDEH6
Slow
98
L14
eSCI
Table 3. MPC5644A signal properties (continued)
Status7
Package pin #
P
A
PCR
I/O
Type Pad Type6
Voltage5 /
Name
Function1
PA PCR4
After
Reset
G2 Field3
During Reset
176
208
324
SCI_A_TX
eSCI A TX
eMIOS channel
GPIO
P
A1
G
01
10
00
89
90
91
92
O
O
I/O
VDDEH6
Medium
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
100 J14
N20
EMIOS138
GPIO[89]
SCI_A_RX
EMIOS158
GPIO[90]
eSCI A RX
eMIOS channel
GPIO
P
A1
G
01
10
00
I
O
I/O
VDDEH6
Medium
99
87
84
K14
L13
M13
P20
SCI_B_TX
DSPI_D_PCS[1]
GPIO[91]
eSCI B TX
DSPI D peripheral chip select
GPIO
P
A1
G
01
10
00
O
O
I/O
VDDEH6
Medium
AB21
AB20
SCI_B_RX
DSPI_D_PCS[5]
GPIO[92]
eSCI B RX
DSPI D peripheral chip select
GPIO
P
A1
G
01
10
00
I
O
I/O
VDDEH6
Medium
SCI_C_TX
GPIO[244]
eSCI C TX
GPIO
P
G
01
00
244
245
O
I/O
VDDEH6
Medium
— / Up
— / Up
— / Up
— / Up
—
—
W19
V19
SCI_C_RX
GPIO[245]
eSCI C RX
GPIO
P
G
01
00
I
VDDEH6
Medium
—
—
I/O
DSPI
DSPI_A_SCK17
DSPI_C_PCS[1]
GPIO[93]
—
—
A1
G
—
10
00
93
94
95
96
97
98
—
O
I/O
VDDEH7
Medium
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
—
—
—
—
—
—
—
—
—
—
C17
B17
A17
D16
C16
C15
DSPI C peripheral chip select
GPIO
DSPI_A_SIN17
DSPI_C_PCS[2]
GPIO[94]
—
—
A1
G
—
10
00
—
O
I/O
VDDEH7
Medium
DSPI C peripheral chip select
GPIO
DSPI_A_SOUT17
DSPI_C_PCS[5]
GPIO[95]
—
—
A1
G
—
10
00
—
O
I/O
VDDEH7
Medium
DSPI C peripheral chip select
GPIO
DSPI_A_PCS[0]17
DSPI_D_PCS[2]
GPIO[96]
—
—
A1
G
—
10
00
—
O
I/O
VDDEH7
Medium
DSPI D peripheral chip select
GPIO
DSPI_A_PCS[1]17
DSPI_B_PCS[2]
GPIO[97]
—
—
A1
G
—
10
00
—
O
I/O
VDDEH7
Medium
DSPI B peripheral chip select
GPIO
CS[2]
DSPI_D_SCK
GPIO[98]
—
—
A1
G
—
10
00
—
I/O
I/O
VDDEH7
Medium
141 J15
SPI clock pin for DSPI module
GPIO
Table 3. MPC5644A signal properties (continued)
Status7
Package pin #
P
A
PCR
I/O
Type Pad Type6
Voltage5 /
Name
Function1
PA PCR4
After
Reset
G2 Field3
During Reset
176
208
324
CS[3]
DSPI_D_SIN
GPIO[99]
—
—
A1
G
—
10
00
99
—
I
I/O
VDDEH7
Medium
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
142 H13
B15
B16
A16
K21
H22
J19
J21
J22
K22
J20
K20
L19
DSPI D data input
GPIO
DSPI_A_PCS[4]17
DSPI_D_SOUT
GPIO[100]
—
—
A1
G
—
10
00
100
101
102
103
104
105
106
107
108
109
110
O
I/O
VDDEH7
Medium
—
—
—
DSPI D data output
GPIO
DSPI_A_PCS[5]17
DSPI_B_PCS[3]
GPIO[101]
—
—
A1
G
—
10
00
O
I/O
VDDEH7
Medium
—
DSPI B peripheral chip select
GPIO
DSPI_B_SCK
DSPI_C_PCS[1]
GPIO[102]
SPI clock pin for DSPI module
DSPI C peripheral chip select
GPIO
P
A1
G
01
10
00
I/O
O
I/O
VDDEH6
Medium
106 J16
112 G15
113 G13
DSPI_B_SIN
DSPI_C_PCS[2]
GPIO[103]
DSPI B data input
DSPI C peripheral chip select
GPIO
P
A1
G
01
10
00
I
O
I/O
VDDEH6
Medium
DSPI_B_SOUT
DSPI_C_PCS[5]
GPIO[104]
DSPI B data output
DSPI C peripheral chip select
GPIO
P
A1
G
01
10
00
O
O
I/O
VDDEH6
Medium
DSPI_B_PCS[0]
DSPI_D_PCS[2]
GPIO[105]
DSPI B peripheral chip select
DSPI D peripheral chip select
GPIO
P
A1
G
01
10
00
I/O
O
I/O
VDDEH6
Medium
111
G16
DSPI_B_PCS[1]
DSPI_D_PCS[0]
GPIO[106]
DSPI B peripheral chip select
DSPI D peripheral chip select
GPIO
P
A1
G
01
10
00
O
I/O
I/O
VDDEH6
Medium
109 H16
107 H15
114 G14
105 H14
104 J13
DSPI_B_PCS[2]
DSPI_C_SOUT
GPIO[107]
DSPI B peripheral chip select
DSPI C data output
GPIO
P
A1
G
01
10
00
O
O
I/O
VDDEH6
Medium
DSPI_B_PCS[3]
DSPI_C_SIN
GPIO[108]
DSPI B peripheral chip select
DSPI C data input
GPIO
P
A1
G
01
10
00
O
I
I/O
VDDEH6
Medium
DSPI_B_PCS[4]
DSPI_C_SCK
GPIO[109]
DSPI B peripheral chip select
SPI clock pin for DSPI module
GPIO
P
A1
G
01
10
00
O
I/O
I/O
VDDEH6
Medium
DSPI_B_PCS[5]
DSPI_C_PCS[0]
GPIO[110]
DSPI B peripheral chip select
DSPI C peripheral chip select
GPIO
P
A1
G
01
10
00
O
I/O
I/O
VDDEH6
Medium
Table 3. MPC5644A signal properties (continued)
Status7
Package pin #
P
A
PCR
I/O
Voltage5 /
Name
Function1
PA PCR4
Type Pad Type6
After
Reset
G2 Field3
During Reset
176
208
324
eQADC
AN018
DAN0+
Single Ended Analog Input
Positive Terminal Diff. Input
P
P
P
P
P
P
P
P
P
P
—
—
—
—
—
—
—
—
01
01
—
—
—
—
—
—
—
—
—
—
I
I
VDDA
Analog
I / —
I / —
I / —
I / —
I / —
I / —
I / —
I / —
I / —
I / —
AN[0] / —
AN[1] / —
AN[2] / —
AN[3] / —
AN[4] / —
AN[5] / —
AN[6] / —
AN[7] / —
AN[8] / —
AN[9] / —
172 B5
171 A6
170 D6
169 C7
168 B6
167 A7
166 D7
165 C8
C6
C7
D7
D8
B7
B8
C8
C9
E1
C2
AN118
DAN0-
Single Ended Analog Input
Negative Terminal Diff. Input
I
I
VDDA
Analog
AN218
DAN1+
Single Ended Analog Input
Positive Terminal Diff. Input
I
I
VDDA
Analog
AN318
DAN1-
Single Ended Analog Input
Negative Terminal Diff. Input
I
I
VDDA
Analog
AN418
DAN2+
Single Ended Analog Input
Positive Terminal Diff. Input
I
I
VDDA
Analog
AN518
DAN2-
Single Ended Analog Input
Negative Terminal Diff. Input
I
I
VDDA
Analog
AN618
DAN3+
Single Ended Analog Input
Positive Terminal Diff. Input
I
I
VDDA
Analog
AN718
DAN3-
Single Ended Analog Input
Negative Terminal Diff. Input
I
I
VDDA
Analog
AN8
ANW
Single-ended Analog Input
Multiplexed Analog Input
I
VDDA
Analog
9
5
B3
A2
AN9
ANX
Single-ended Analog Input
External Multiplexed Analog
Input
I
I
VDDA
Analog
AN10
ANY
Single-ended Analog Input
Multiplexed Analog Input
P
P
P
01
01
—
—
I
I
VDDA
Analog
I / —
I / —
I / —
AN[10] / —
AN[11] / —
AN[12] / —
—
—
D1
AN11
ANZ
Single-ended Analog Input
Multiplexed Analog Input
VDDA
Analog
4
A3
C1
AN12 - SDS
MA0
Single-ended Analog Input
MUX Address 0
eTPU A channel (output only)
eQADC Serial Data Select
001
215
I
O
O
I/O
VDDEH719
Medium
148 A12
C13
A1 010
A2 100
G
ETPUA19_O8
SDS
000
AN13 - SDO
MA1
Single-ended Analog Input
MUX Address 1
eTPU A channel (output only)
eQADC Serial Data Out
P
001
216
I
VDDEH719
Medium
I / —
AN[13] / —
147 B12
B13
A1 010
A2 100
G
O
O
O
ETPUA21_O8
SDO
000
Table 3. MPC5644A signal properties (continued)
Status7
Package pin #
P
A
PCR
I/O
Type Pad Type6
Voltage5 /
Name
Function1
PA PCR4
After
Reset
G2 Field3
During Reset
176
208
324
AN14 - SDI
MA2
Single-ended Analog Input
MUX Address 2
eTPU A channel (output only)
eQADC Serial Data In
P
001
217
218
I
VDDEH719
Medium
I / —
AN[14] / —
146 C12
A13
A14
A1 010
A2 100
G
O
O
I
ETPUA27_O8
SDI
000
AN15 - FCK
FCK
Single-ended Analog Input
eQADC Free Running Clock
eTPU A channel (output only)
P
001
I
O
O
VDDEH719
Medium
I / —
AN[15] / —
145 C13
A1 010
A2 100
ETPUA29_O8
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
Single-ended Analog Input
Single-ended Analog Input
Single-ended Analog Input
Single-ended Analog Input
Single-ended Analog Input
Single-ended Analog Input
Single-ended Analog Input
Single-ended Analog Input
Single-ended Analog Input
Single-ended Analog Input
Single-ended Analog Input
Single-ended Analog Input
Single-ended Analog Input
P
P
P
P
P
P
P
P
P
P
P
P
P
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I
I
I
I
I
I
I
I
I
I
I
I
I
VDDA
Analog
I / —
I / —
I / —
I / —
I / —
I / —
I / —
I / —
I / —
I / —
I / —
I / —
I / —
AN[16] / —
AN[17] / —
AN[18] / —
AN[19] / —
AN[20] / —
AN[21] / —
AN[22] / —
AN[23] / —
AN[24] / —
AN[25] / —
AN[26] / —
AN[27] / —
AN[28] / —
3
2
1
C6
C4
D5
A3
VDDA
Analog
A4
VDDA
Analog
B4
VDDA
Analog
—
—
—
—
D6
C5
B6
VDDA
Analog
VDDA
Analog
173 B4
161 B8
160 C9
159 D8
158 B9
—
VDDA
Analog
D9
A8
VDDA
Analog
VDDA
Analog
B9
VDDA
Analog
A9
VDDA
Analog
—
D10
C10
D11
VDDA
Analog
157 A10
156 B10
VDDA
Analog
Table 3. MPC5644A signal properties (continued)
Status7
Package pin #
P
A
PCR
I/O
Type Pad Type6
Voltage5 /
Name
Function1
PA PCR4
After
Reset
G2 Field3
During Reset
176
208
324
AN29
AN30
AN31
AN32
AN33
AN34
AN35
AN36
AN37
AN38
AN39
VRH
Single-ended Analog Input
Single-ended Analog Input
Single-ended Analog Input
Single-ended Analog Input
Single-ended Analog Input
Single-ended Analog Input
Single-ended Analog Input
Single-ended Analog Input
Single-ended Analog Input
Single-ended Analog Input
Single-ended Analog Input
Voltage Reference High
Voltage Reference Low
P
P
P
P
P
P
P
P
P
P
P
P
P
P
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I
I
I
I
I
I
I
I
I
I
I
I
I
I
VDDA
Analog
I / —
AN[29] / —
AN[30] / —
AN[31] / —
AN[32] / —
AN[33] / —
AN[34] / —
AN[35] / —
AN[36] / —
AN[37] / —
AN[38] / —
AN[39] / —
VRH
—
—
C11
B11
D12
C12
B12
A12
D13
B5
VDDA
Analog
I / —
I / —
I / —
I / —
I / —
I / —
I / —
I / —
I / —
I / —
I / —
I / —
I / —
155 D9
154 D10
153 C10
152 C11
151 C5
150 D11
174 F4
175 E3
VDDA
Analog
VDDA
Analog
VDDA
Analog
VDDA
Analog
VDDA
Analog
VDDA
Analog
VDDA
Analog
A5
VDDA
Analog
—
8
—
D3
VDDA
Analog
D2
D2
VDDA
—
163 A8
162 A9
164 B7
A10
A11
B10
VRL
VDDA
—
VRL
REFBYBC
Reference Bypass Capacitor
Input
VDDA
Analog
REFBYPC
eTPU2
TCRCLKA
IRQ[7]
GPIO[113]
eTPU A TCR clock
External interrupt request
GPIO
P
A1
G
01
10
00
113
I
I
VDDEH4
Slow
— / Up
— / Up
—
L4
AB12
I/O
Table 3. MPC5644A signal properties (continued)
Status7
Package pin #
P
A
PCR
I/O
Type Pad Type6
Voltage5 /
Name
Function1
PA PCR4
After
Reset
G2 Field3
During Reset
176
61
208
N3
324
ETPUA0
eTPU A channel
P
001
114
I/O
O
VDDEH4
Slow
— /
WKPCFG
— /
Y12
ETPUA12_O8
ETPUA19_O8
GPIO[114]
eTPU A channel (output only)
eTPU A channel (output only)
GPIO
A1 010
A2 100
WKPCFG
O
G
000
I/O
ETPUA1
eTPU A channel
eTPU A channel (output only)
GPIO
P
A1
G
01
10
00
115
116
117
I/O
O
I/O
VDDEH4
Slow
— /
WKPCFG
— /
WKPCFG
60
59
M3
P2
P1
N2
W12
AA11
Y11
ETPUA13_O8
GPIO[115]
ETPUA2
eTPU A channel
eTPU A channel (output only)
GPIO
P
A1
G
01
10
00
I/O
O
I/O
VDDEH4
Slow
— /
WKPCFG
— /
WKPCFG
ETPUA14_O8
GPIO[116]
ETPUA3
eTPU A channel
eTPU A channel (output only)
GPIO
P
A1
G
01
10
00
I/O
O
I/O
VDDEH4
Slow
— / WKPCFG GPIO / WKPCFG 58
ETPUA15_O8
GPIO[117]
ETPUA4
eTPU A channel
P
0001 118
I/O
O
O
VDDEH4
Slow
— /
WKPCFG
— /
WKPCFG
56
54
W11
ETPUA16_O8
FR_B_TX
GPIO[118]
eTPU A channel (output only)
Flexray TX data channel B
GPIO
A1 0010
A3 1000
G
0000
I/O
ETPUA5
eTPU A channel
eTPU A channel (output only)
P
0001 119
I/O
O
O
O
I/O
VDDEH4
Slow +
LVDS
— /
WKPCFG
— /
WKPCFG
M4
L3
AB11
AB10
AA10
ETPUA17_O8
A1 0010
A2 0100
DSPI_B_SCK_LV LVDS negative DSPI clock
DS-
FR_B_TX_EN
GPIO[119]
Flexray TX data enable for ch. B A3 1000
GPIO
G
0000
ETPUA6
eTPU A channel
eTPU A channel (output only)
P
0001 120
I/O
O
O
VDDEH4
Medium +
LVDS
— /
WKPCFG
— /
WKPCFG
53
52
ETPUA18_O8
A1 0010
A2 0100
A3 1000
DSPI_B_SCK_LV LVDS positive DSPI clock
DS+
FR_B_RX
GPIO[120]
Flexray RX data channel B
GPIO
I
G
0000
I/O
ETPUA7
eTPU A channel
eTPU A channel (output only)
P
0001 121
I/O
O
O
O
I/O
VDDEH4
Slow +
LVDS
— /
WKPCFG
— /
WKPCFG
K3
ETPUA19_O8
A1 0010
A2 0100
A3 1000
DSPI_B_SOUT_L LVDS negative DSPI data out
VDS-
eTPU A channel (output only)
GPIO
ETPUA6_O8
GPIO[121]
G
0000
Table 3. MPC5644A signal properties (continued)
Status7
Package pin #
P
A
PCR
I/O
Type Pad Type6
Voltage5 /
Name
Function1
PA PCR4
After
Reset
G2 Field3
During Reset
176
51
208
N1
324
ETPUA8
ETPUA20_O8
DSPI_B_SOUT_L LVDS positive DSPI data out
eTPU A channel
P
001
122
I/O
O
VDDEH4
Slow +
LVDS
— /
WKPCFG
— /
Y10
eTPU A channel (output only)
A1 010
A2 100
WKPCFG
O
VDS+
GPIO
G
000
I/O
GPIO[122]
ETPUA9
eTPU A channel
P
001
123
124
125
126
127
I/O
O
O
VDDEH4
Slow
— /
WKPCFG
— /
WKPCFG
50
49
48
47
M2
M1
L2
AA9
AA4
AB4
AB3
ETPUA21_O8
RCH1_B
eTPU A channel (output only)
Reaction channel 1B
GPIO
A1 010
A2 100
G
GPIO[123]
000
I/O
ETPUA10
ETPUA22_O8
RCH1_C
eTPU A channel
P
001
I/O
O
O
VDDEH1
Slow
— /
WKPCFG
— /
WKPCFG
eTPU A channel (output only)
Reaction channel 1C
GPIO
A1 010
A2 100
G
GPIO[124]
000
I/O
ETPUA11
eTPU A channel
P
001
I/O
O
O
VDDEH1
Slow
— /
WKPCFG
— /
WKPCFG
ETPUA23_O8
RCH4_B
eTPU A channel (output only)
Reaction channel 4B
GPIO
A1 010
A2 100
G
GPIO[125]
000
I/O
ETPUA12
DSPI_B_PCS[1]
RCH4_C
eTPU A channel
P
001
I/O
O
O
VDDEH1
Medium
— /
WKPCFG
— /
WKPCFG
L1
DSPI B peripheral chip select
Reaction channel 4C
GPIO
A1 010
A2 100
G
GPIO[126]
000
I/O
ETPUA13
DSPI_B_PCS[3]
GPIO[127]
eTPU A channel
DSPI B peripheral chip select
GPIO
P
A1
G
01
10
00
I/O
O
I/O
VDDEH1
Medium
— /
WKPCFG
— /
WKPCFG
46
42
J4
J3
AB2
AA2
ETPUA14
eTPU A channel
P
0001 128
I/O
O
O
O
I/O
VDDEH1
Medium
— /
WKPCFG
— /
WKPCFG
DSPI_B_PCS[4]
ETPUA9_O8
RCH0_A
DSPI B peripheral chip select
eTPU A channel (output only)
Reaction channel 0A
GPIO
A1 0010
A2 0100
A3 1000
GPIO[128]
G
0000
ETPUA15
DSPI_B_PCS[5]
RCH1_A
eTPU A channel
DSPI B peripheral chip select
Reaction channel 1A
GPIO
P
001
129
130
I/O
O
O
VDDEH1
Medium
— /
WKPCFG
— /
WKPCFG
40
39
K2
K1
AA1
Y2
A1 010
A2 100
G
GPIO[129]
000
I/O
ETPUA16
DSPI_D_PCS[1]
RCH2_A
eTPU A channel
P
001
I/O
O
O
VDDEH1
Slow
— /
WKPCFG
— /
WKPCFG
DSPI D peripheral chip select
Reaction channel 2A
GPIO
A1 010
A2 100
G
GPIO[130]
000
I/O
Table 3. MPC5644A signal properties (continued)
Status7
Package pin #
P
A
PCR
I/O
Type Pad Type6
Voltage5 /
Name
Function1
PA PCR4
After
Reset
G2 Field3
During Reset
176
38
208
H3
324
ETPUA17
eTPU A channel
P
001
131
132
133
I/O
O
VDDEH1
Slow
— /
WKPCFG
— /
Y1
DSPI_D_PCS[2]
RCH3_A
GPIO[131]
DSPI D peripheral chip select
Reaction channel 3A
GPIO
A1 010
A2 100
G
WKPCFG
O
I/O
000
ETPUA18
eTPU A channel
P
001
I/O
O
VDDEH1
Slow
— /
WKPCFG
— /
37
36
35
H4
J2
J1
W3
W2
W1
DSPI_D_PCS[3]
RCH4_A
GPIO[132]
DSPI D peripheral chip select
Reaction channel 4A
GPIO
A1 010
A2 100
G
WKPCFG
O
I/O
000
ETPUA19
eTPU A channel
P
001
I/O
O
VDDEH1
Slow
— /
WKPCFG
— /
DSPI_D_PCS[4]
RCH5_A
GPIO[133]
DSPI D peripheral chip select
Reaction channel 5A
GPIO
A1 010
A2 100
G
WKPCFG
O
I/O
000
ETPUA20
IRQ[8]
RCH0_B
FR_A_TX
GPIO[134]
eTPU A channel
P
0001 134
I/O
I
VDDEH1
Slow
— /
WKPCFG
— /
External interrupt request
Reaction channel 0B
Flexray TX data channel A
GPIO
A1 0010
A2 0100
A3 1000
WKPCFG
O
O
G
0000
I/O
ETPUA21
IRQ[9]
RCH0_C
FR_A_RX
GPIO[135]
eTPU A channel
External interrupt request
Reaction channel 0C
Flexray RX channel A
GPIO
P
0001 135
I/O
I
O
I
VDDEH1
Slow
— /
WKPCFG
— /
WKPCFG
34
G4
N4
A1 0010
A2 0100
A3 1000
G
0000
I/O
ETPUA22
IRQ[10]
eTPU A channel
P
001
136
I/O
I
O
VDDEH1
Slow
— /
WKPCFG
— /
WKPCFG
32
30
H2
H1
N3
M1
External interrupt request
eTPU A channel (output only)
GPIO
A1 010
A2 100
G
ETPUA17_O8
GPIO[136]
000
I/O
ETPUA23
IRQ[11]
eTPU A channel
P
0001 137
I/O
I
O
O
I/O
VDDEH1
Slow
— /
WKPCFG
— /
WKPCFG
External interrupt request
eTPU A channel (output only)
Flexray ch. A TX enable
GPIO
A1 0010
A2 0100
A3 1000
ETPUA21_O8
FR_A_TX_EN
GPIO[137]
G
0000
ETPUA24
IRQ[12]
eTPU A channel
External interrupt request
P
001
138
I/O
I
O
VDDEH1
Slow +
LVDS
— /
WKPCFG
— /
WKPCFG
28
G1
M2
A1 010
A2 100
DSPI_C_SCK_LV LVDS negative DSPI clock
DS-
GPIO
G
000
I/O
GPIO[138]
Table 3. MPC5644A signal properties (continued)
Status7
Package pin #
P
A
PCR
I/O
Type Pad Type6
Voltage5 /
Name
Function1
PA PCR4
After
Reset
G2 Field3
During Reset
176
27
208
G3
324
ETPUA25
IRQ[13]
DSPI_C_SCK_LV LVDS positive DSPI clock
eTPU A channel
P
001
139
140
I/O
I
O
VDDEH1
Medium +
LVDS
— /
WKPCFG
— /
M3
L2
L1
External interrupt request
A1 010
A2 100
G
WKPCFG
DS+
GPIO
000
I/O
GPIO[139]
ETPUA26
IRQ[14]
eTPU A channel
External interrupt request
P
001
I/O
I
O
VDDEH1
Slow +
LVDS
— /
WKPCFG
— /
26
25
F3
A1 010
A2 100
G
WKPCFG
DSPI_C_SOUT_L LVDS negative DSPI data out
VDS-
GPIO
000
I/O
GPIO[140]
ETPUA27
IRQ[15]
eTPU A channel
External interrupt request
P
0001 141
I/O
I
O
VDDEH1
Slow +
LVDS
— /
WKPCFG
— /
G2
A1 0010
A2 0100
A3 1000
WKPCFG
DSPI_C_SOUT_L LVDS positive DSPI data out
VDS+
DSPI_B_SOUT
GPIO[141]
DSPI data out
GPIO
O
G
0000
I/O
ETPUA28
DSPI_C_PCS[1]
RCH5_B
eTPU A channel
P
001
142
143
144
145
I/O
O
O
VDDEH1
Medium
— /
WKPCFG
— /
WKPCFG
24
23
22
21
F1
F2
E1
E2
M4
L3
L4
K1
DSPI C peripheral chip select
Reaction channel 5B
GPIO
A1 010
A2 100
G
GPIO[142]
000
I/O
ETPUA29
DSPI_C_PCS[2]
RCH5_C
eTPU A channel
P
001
I/O
O
O
VDDEH1
Medium
— /
WKPCFG
— /
WKPCFG
DSPI C peripheral chip select
Reaction channel 5C
GPIO
A1 010
A2 100
G
GPIO[143]
000
I/O
ETPUA30
eTPU A channel
P
001
I/O
O
O
VDDEH1
Medium
— /
WKPCFG
— /
WKPCFG
DSPI_C_PCS[3]
ETPUA11_O8
GPIO[144]
DSPI C peripheral chip select
eTPU A channel (output only)
GPIO
A1 010
A2 100
G
000
I/O
ETPUA31
eTPU A channel
P
001
I/O
O
O
VDDEH1
Medium
— /
WKPCFG
— /
WKPCFG
DSPI_C_PCS[4]
ETPUA13_O8
GPIO[145]
DSPI C peripheral chip select
eTPU A channel (output only)
GPIO
A1 010
A2 100
G
000
I/O
eMIOS
EMIOS0
eMIOS channel
P
001
179
I/O
O
O
VDDEH4
Slow
— / Up
— / Up
63
T4
AA12
ETPUA0_O8
ETPUA25_O8
GPIO[179]
eTPU A channel (output only)
eTPU A channel (output only)
GPIO
A1 010
A2 100
G
000
I/O
Table 3. MPC5644A signal properties (continued)
Status7
Package pin #
P
A
PCR
I/O
Type Pad Type6
Voltage5 /
Name
Function1
PA PCR4
After
Reset
G2 Field3
During Reset
176
64
208
T5
324
EMIOS1
eMIOS channel
eTPU A channel (output only)
GPIO
P
A1
G
01
10
00
180
181
I/O
O
VDDEH4
Slow
— / Up
— / Up
— / Up
— / Up
W13
Y13
ETPUA1_O8
GPIO[180]
I/O
EMIOS2
eMIOS channel
P
001
I/O
O
VDDEH4
Slow
65
N7
ETPUA2_O8
RCH2_B
eTPU A channel (output only)
Reaction channel 2B
GPIO
A1 010
A2 100
O
GPIO[181]
G
000
I/O
EMIOS3
eMIOS channel
eTPU A channel (output only)
GPIO
P
A1
G
01
10
00
182
183
I/O
O
I/O
VDDEH4
Slow
— /
WKPCFG
— /
WKPCFG
66
67
R6
R5
AA13
AB13
ETPUA3_O8
GPIO[182]
EMIOS4
eMIOS channel
P
001
I/O
O
O
VDDEH4
Slow
— /
WKPCFG
— /
WKPCFG
ETPUA4_O8
RCH2_C
eTPU A channel (output only)
Reaction channel 2C
GPIO
A1 010
A2 100
G
GPIO[183]
000
I/O
EMIOS5
eMIOS channel
eTPU A channel (output only)
GPIO
P
A1
G
01
10
00
184
185
186
187
I/O
O
I/O
VDDEH4
Slow
— /
WKPCFG
— /
WKPCFG
—
—
—
Y14
ETPUA5_O8
GPIO[184]
EMIOS6
eMIOS channel
eTPU A channel (output only)
GPIO
P
A1
G
01
10
00
I/O
O
I/O
VDDEH4
Slow
— / Down
— / Down
— / Up
— / Down
— / Down
— / Up
68
69
70
P7
AA14
AB14
W15
ETPUA6_O8
GPIO[185]
EMIOS7
eMIOS channel
eTPU A channel (output only)
GPIO
P
A1
G
01
10
00
I/O
O
I/O
VDDEH4
Slow
ETPUA7_O8
GPIO[186]
EMIOS8
eMIOS channel
eTPU A channel (output only)
eSCI B TX
P
001
I/O
O
O
VDDEH4
Slow
P8
R7
N8
ETPUA8_O8
SCI_B_TX
GPIO[187]
A1 010
A2 100
G
GPIO
000
I/O
EMIOS9
eMIOS channel
eTPU A channel (output only)
eSCI B RX
P
001
188
189
I/O
O
I
VDDEH4
Slow
— / Up
— / Up
71
73
Y15
ETPUA9_O8
SCI_B_RX
GPIO[188]
A1 010
A2 100
G
GPIO
000
I/O
EMIOS10
DSPI_D_PCS[3]
RCH3_B
eMIOS channel
P
001
I/O
O
O
VDDEH4
Medium
— /
WKPCFG
— /
WKPCFG
AA15
DSPI D peripheral chip select
Reaction channel 3B
GPIO
A1 010
A2 100
G
GPIO[189]
000
I/O
Table 3. MPC5644A signal properties (continued)
Status7
Package pin #
P
A
PCR
I/O
Type Pad Type6
Voltage5 /
Name
Function1
PA PCR4
After
Reset
G2 Field3
During Reset
176
75
208
R8
324
EMIOS11
eMIOS channel
P
001
190
191
I/O
O
VDDEH4
Medium
— /
WKPCFG
— /
AB15
DSPI_D_PCS[4]
RCH3_C
GPIO[190]
DSPI D peripheral chip select
Reaction channel 3C
GPIO
A1 010
A2 100
G
WKPCFG
O
I/O
000
EMIOS12
eMIOS channel
P
001
I/O
O
VDDEH4
Medium
— /
WKPCFG
— /
76
N10
AB16
DSPI_C_SOUT
ETPUA27_O8
GPIO[191]
DSPI C data output
eTPU A channel (output only)
GPIO
A1 010
A2 100
WKPCFG
O
G
000
I/O
EMIOS13
DSPI_D_SOUT
GPIO[192]
eMIOS channel
DSPI D data output
GPIO
P
A1
G
01
10
00
192
193
I/O
O
I/O
VDDEH4
Medium
— /
WKPCFG
— /
WKPCFG
77
78
T8
R9
AA16
Y16
EMIOS14
IRQ[0]
eMIOS channel
P
001
I/O
I
O
VDDEH4
Slow
— / Down
— / Down
— / Down
— / Down
External interrupt request
eTPU A channel (output only)
GPIO
A1 010
A2 100
G
ETPUA29_O8
GPIO[193]
000
I/O
EMIOS15
IRQ[1]
GPIO[194]
eMIOS channel
External interrupt request
GPIO
P
A1
G
01
10
00
194
I/O
I
I/O
VDDEH4
Slow
79
T9
W16
EMIOS16
GPIO[195]
eMIOS channel
GPIO
P
G
01
00
195
196
197
198
199
200
201
202
I/O
I/O
VDDEH4
Slow
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
—
—
W17
Y17
EMIOS17
GPIO[196]
eMIOS channel
GPIO
P
G
01
00
I/O
I/O
VDDEH4
Slow
—
—
—
—
—
—
—
—
—
—
—
—
EMIOS18
GPIO[197]
eMIOS channel
GPIO
P
G
01
00
I/O
I/O
VDDEH4
Slow
AA17
AB17
AB18
AA18
Y18
EMIOS19
GPIO[198]
eMIOS channel
GPIO
P
G
01
00
I/O
I/O
VDDEH4
Slow
— /
WKPCFG
— /
WKPCFG
EMIOS20
GPIO[199]
eMIOS channel
GPIO
P
G
01
00
I/O
I/O
VDDEH4
Slow
— /
WKPCFG
— /
WKPCFG
EMIOS21
GPIO[200]
eMIOS channel
GPIO
P
G
01
00
I/O
I/O
VDDEH4
Slow
— /
WKPCFG
— /
WKPCFG
EMIOS22
GPIO[201]
eMIOS channel
GPIO
P
G
01
00
I/O
I/O
VDDEH4
Slow
— / Down
— / Down
EMIOS23
GPIO[202]
eMIOS channel
GPIO
P
G
01
00
I/O
I/O
VDDEH4
Slow
— / Down
— / Down
80
R11
W18
Clock Synthesizer
Table 3. MPC5644A signal properties (continued)
Status7
Package pin #
P
A
PCR
I/O
Type Pad Type6
Voltage5 /
Name
Function1
PA PCR4
After
Reset
G2 Field3
During Reset
176
93
208
P16
324
XTAL
Crystal oscillator output
P
01
—
—
O
I
VDDEH6
Analog
—
—
—
—
—
V22
U22
AB9
W10
EXTAL
EXTCLK
Crystal oscillator input
External clock input
P
A
01
10
VDDEH6
Analog
—
92
N16
CLKOUT
ENGCLK
System clock output
P
01
229
214
O
O
VDDE5
Fast
CLKOUT
ENGCLK
—
—
Engineering clock output
P
01
VDDE5
Fast
—
T14
Power / Ground
VDDREG
VRCCTL
Voltage Regulator Supply
—
—
—
—
I
5 V
—
I / —
VDDREG
VRCCTL
10
K16
N14
F4
F2
Voltage Regulator Control
Output
O
O / —
11
VRC3320
Internal regulator output
—
—
—
—
—
—
—
—
O
3.3 V
3.3 V
5 V
I/O / —
VRC33
13
A15,D1, B1,
N6, N12 M19, P11
Input for external 3.3 V supply
eQADC high reference voltage
VDDA
VSSA
I
I
I / —
I / —
VDDA
VSSA
6
7
—
—
—
—
eQADC ground/low reference
voltage
—
VDDA021
VSSA022
eQADC high reference voltage
—
—
—
—
I
I
5 V
—
I / —
I / —
VDDA0
VSSA0
—
B11
E3
E2
eQADC ground/low reference
voltage
—
A11
VDDA121
VSSA122
eQADC high reference voltage
—
—
—
—
I
I
5 V
—
I / —
I / —
VDDA1
VSSA1
—
—
A4
A5
A6
A7
eQADC ground/low reference
voltage
VDDPLL
VSTBY
VDD
FMPLL Supply Voltage
—
—
—
—
—
—
I
I
I
1.2
I / —
I / —
I / —
VDDPLL
VSTBY
VDD
91
R16
C1
W22
E4
Power Supply for Standby RAM
0.9 V - 6 V
1.2 V
12
Core supply for input or
decoupling
33,
45,
62,
B1, B16, A2, A20, A21,
C2, D3, B3, C4, C22,
E4, N5, D5, W20, Y4,
103, P4, P13, Y21, AA3,
132, R3,R14, AA22
149, T2, T15
176
Table 3. MPC5644A signal properties (continued)
Status7
Package pin #
P
A
PCR
I/O
Type Pad Type6
Voltage5 /
Name
Function1
PA PCR4
After
Reset
G2 Field3
During Reset
176
208
324
VDDE12
External supply input for
calibration bus interfaces
—
—
—
—
I
I
I
1.8 V - 3.3 V
1.8 V - 3.3 V
1.8 V - 3.3 V
I / —
I / —
I / —
VDDE12
VDDE224
VDDE5
—
—
—
VDDE223
VDDE5
External supply input for EBI
interfaces
—
—
—
—
—
M9, M10
External supply input for
ENGCLK, CLKOUT and EBI
signals DATA[0:15]
T13
N11, W5, W8
VDDE-EH
External supply for EBI
interfaces
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I
I
I
I
I
I
I
I
I
I
I
I
3.0 V - 5 V
3.3 V - 5.0 V
3.3 V - 5.0 V
3.3 V - 5.0 V
3.3 V - 5.0 V
3.3 V - 5.0 V
3.3 V - 5.0 V
3.3 V - 5.0 V
3.3 V - 5.0 V
3.3 V - 5.0 V
3.3 V - 5.0 V
3.3 V - 5.0 V
I / —
I / —
I / —
I / —
I / —
I / —
I / —
I / —
I / —
I / —
I / —
I / —
VDDE-EH
VDDEH1A25
VDDEH1B25
VDDEH1AB25
VDDEH426
—
—
—
—
R3, V2
VDDEH1A25
VDDEH1B25
VDDEH1AB25
VDDEH426
I/O Supply Input
I/O Supply Input
I/O Supply Input
I/O Supply Input
I/O Supply Input
I/O Supply Input
I/O Supply Input
I/O Supply Input
I/O Supply Input
I/O Supply Input
I/O Supply Input
31
41
—
—
55
74
—
—
—
K4
K4
—
—
—
—
VDDEH4A26
VDDEH4B26
VDDEH4AB26
VDDEH627
VDDEH4A26
VDDEH4B26
VDDEH4AB26
VDDEH627
—
—
W14, AA19
—
N9
—
—
—
—
VDDEH6A27
VDDEH6B27
VDDEH6AB27
VDDEH6A27
VDDEH6B27
VDDEH6AB27
95
—
110
—
—
F13
M22, U19
Table 3. MPC5644A signal properties (continued)
Status7
Package pin #
P
A
PCR
I/O
Type Pad Type6
Voltage5 /
Name
Function1
PA PCR4
After
Reset
G2 Field3
During Reset
176
208
D12
324
VDDEH7
I/O Supply Input
—
—
I
3.3 V - 5.0 V
I / —
VDDEH7
—
B22, C21,
D15, D20,
E19, F19,
H19, J14
VDDEH7A
VDDEH7B
VSS
I/O Supply Input
I/O Supply Input
Ground
—
—
—
—
—
—
I
I
I
3.3 V - 5.0 V
3.3 V - 5.0 V
—
I / —
I / —
I / —
VDDEH7A
VDDEH7B
VSS
125
138
—
—
—
—
15,
29,
43,
57,
72,
90,
94,
96,
A1, A16, A1, A22, B2,
B2, B15, B21, C3, C20,
C3,C14, D4, D17, D19,
D4, D13, F21, H21, J9,
G7, G8, J10, J11, J12,
G9,
G10,
J13, K9, K10,
K11, K12,
H7, H8, K13, K14, L9,
108, H9, H10, L10, L11, L12,
115, J7, J8, L13, L14, L21,
127, J9, J10, M11, M12,
133, K7,
M13, M14,
140 K8, K9, N9, N10, N12,
K10,
M16,
N13, N14,
N21, P9, P10,
N4,N13, P12, P13,
P3, P14, P14, T19,
R2,R15, T21, T22, W4,
T1, T16 Y3, Y20,
AA21, AB1,
AB22
1
2
For each pin in the table, each line in the Function column is a separate function of the pin. For all I/O pins the selection of primary pin function or
secondary function or GPIO is done in the SIU except where explicitly noted. See the Signal details table for a description of each signal.
The P/A/G column indicates the position a signal occupies in the muxing order for a pin—Primary, Alternate 1, Alternate 2, Alternate 3, or GPIO.
Signals are selected by setting the PA field value in the appropriate PCR register in the SIU module. The PA field values are as follows: P - 0b0001,
A1 - 0b0010, A2 - 0b0100, A3 - 0b1000, or G - 0b0000. Depending on the register, the PA field size can vary in length. For PA fields having fewer
than four bits, remove the appropriate number of leading zeroes from these values.
3
4
The Pad Configuration Register (PCR) PA field is used by software to select pin function.
Values in the PCR No. column refer to registers in the System Integration Unit (SIU). The actual register name is “SIU_PCR” suffixed by the PCR
number. For example, PCR[190] refers to the SIU register named SIU_PCR190.
5
The VDDE and VDDEH supply inputs are broken into segments. Each segment of slow I/O pins (VDDEH) may have a separate supply in the 3.3
V to 5.0 V range (-10%/+5%). Each segment of fast I/O (VDDE) may have a separate supply in the 1.8 V to 3.3 V range (+/- 10%).
6
7
See Table 4 for details on pad types.
The Status During Reset pin is sampled after the internal POR is negated. Prior to exiting POR, the signal has a high impedance. Terminology is
O - output, I - input, Up - weak pull up enabled, Down - weak pull down enabled, Low - output driven low, High - output driven high. A dash for the
function in this column denotes that both the input and output buffer are turned off. The signal name to the left or right of the slash indicates the
pin is enabled.
8
9
Output only.
When used as ETRIG, this pin must be configured as an input. For GPIO it can be configured either as an input or output.
10 Maximum frequency is 50 kHz.
11 The SIU_PCR219 register is unusual in that it controls pads for two separate device pins: GPIO[219] and MCKO. See the MPC5644A
Microcontroller Reference Manual (SIU chapter) for details.
12 Multivoltage pads are automatically configured in low swing mode when a JTAG or Nexus function is selected, otherwise they are high swing.
13 On 176 LQFP and 208 MAPBGA packages, this pin is tied low internally.
14 Nexus multivoltage pads default to 5 V operation until the Nexus module is enabled.
15 EVTO should be clamped to 3.3 V to prevent possible damage to external tools that only support 3.3 V.
16 Do not connect pin directly to a power supply or ground.
17 This signal name is used to support legacy naming.
18 During and just after POR negates, internal pull resistors can be enabled, resulting in as much as 4 mA of current draw. The pull resistors are
disabled when the system clock propagates through the device.
19 For pins AN12-AN15, if the analog features are used the VDDEH7 input pins should be tied to VDDA because that segment must meet the VDDA
specification to support analog input function.
20 Do not use VRC33 to drive external circuits.
21 VDDA0 and VDDA1 are shorted together internally in BGA packages. In the QFP package the two pads are double bonded on one pin called
VDDA.
22 VSSA0 and VSSA1 are shorted together internally in BGA packages. In the QFP package the two pads are double bonded on one pin called VSSA.
23
VDDE2 and VDDE3 are shorted together in all production packages.
24
VDDE2 and VDDE3 are shorted together in all production packages.
25 VDDEH1A, VDDEH1B, and VDDEH1AB are shorted together in all production packages. The separation of the signal names is present to support
legacy naming, however they should be considered as the same signal in this document.
26 VDDEH4, VDDEH4A, VDDEH4B, and VDDEH4AB are shorted together in all production packages. The separation of the signal names is present
to support legacy naming, however they should be considered as the same signal in this document.
27 VDDEH6, VDDEH6A, VDDEH6B, and VDDEH6AB are shorted together in all production packages. The separation of the signal names is present
to support legacy naming, however they should be considered as the same signal in this document.
Table 4. Pad types
Pad Type
Name
I/O Voltage Range
Slow
Medium
Fast
pad_ssr_hv
pad_msr_hv
pad_fc
3.0V - 5.5 V
3.0 V - 5.5 V
3.0 V - 3.6 V
MultiV1,2
pad_multv_hv
3.0 V - 5.5 V (high swing mode)
3.0 V - 3.6 V (low swing mode)
Analog
LVDS
pad_ae_hv
pad_lo_lv
0.0 - 5.5 V
—
1
2
Multivoltage pads are automatically configured in low swing mode when a JTAG or Nexus function
is selected, otherwise they are high swing.
VDDEH7 supply cannot be below 4.5 V when in low-swing mode.
2.5
Signal details
Table 5. Signal details
Signal
Module or Function
Description
CLKOUT
ENGCLK
EXTAL
Clock Generation
Clock Generation
Clock Generation
MPC5644A clock output for the external/calibration bus interface
Clock for external ASIC devices
Input pin for an external crystal oscillator or an external clock
source based on the value driven on the PLLREF pin at reset.
PLLREF
Clock Generation
Reset/Configuration
PLLREF is used to select whether the oscillator operates in xtal
mode or external reference mode from reset. PLLREF=0 selects
external reference mode. On the 324BGA package, PLLREF is
bonded to the ball used for PLLCFG[0] for compatibility with
MPC55xx devices .
For the 176-pin QFP and 208-ball BGA packages:
0: External reference clock is selected.
1: XTAL oscillator mode is selected
For the 324 ball BGA package:
If RSTCFG is 0:
0: External reference clock is selected.
1: XTAL oscillator mode is selected.
If RSTCFG is 1, XTAL oscillator mode is selected.
Crystal oscillator input
XTAL
Clock Generation
DSPI
DSPI_B_SCK_LVDS-
DSPI_B_SCK_LVDS+
LVDS pair used for DSPI_B TSB mode transmission
DSPI_B_SOUT_LVDS- DSPI
DSPI_B_SOUT_LVDS+
LVDS pair used for DSPI_B TSB mode transmission
LVDS pair used for DSPI_C TSB mode transmission
DSPI_C_SCK_LVDS-
DSPI_C_SCK_LVDS+
DSPI
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
57
Table 5. Signal details (continued)
Module or Function Description
Signal
DSPI_C_SOUT_LVDS- DSPI
DSPI_C_SOUT_LVDS+
LVDS pair used for DSPI_C TSB mode transmission
PCS_B[0]
PCS_C[0]
PCS_D[0]
DSPI_B - DSPI_D
Peripheral chip select when device is in master mode—slave
select when used in slave mode
PCS_B[1:5]
PCS_C[1:5]
PCS_D[1:5]
DSPI_B - DSPI_D
DSPI_B - DSPI_D
DSPI_B - DSPI_D
DSPI_B - DSPI_D
EBI
Peripheral chip select when device is in master mode—not used
in slave mode
SCK_B
SCK_C
SCK_D
DSPI clock—output when device is in master mode; input when
in slave mode
SIN_B
SIN_C
SIN_D
DSPI data in
SOUT_B
SOUT_C
SOUT_D
DSPI data out
ADDR[10:31]
The ADDR[10:31] signals specify the physical address of the
bus transaction.
The 26 address lines correspond to bits 3-31 of the EBI’s 32-bit
internal address bus.
ADDR[15:31] can be used as Address and Data signals when
configured appropriately for a multiplexed external bus. This
allows 32-bit data operations, or 16-bit data operations without
using DATA[0:15] signals.
ALE
EBI
The Address Latch Enable (ALE) signal is used to demultiplex
the address from the data bus. It is asserted while the least
significant 16 bits of the address are present in the multiplexed
address/data bus.
BDIP
EBI
EBI
BDIP is asserted to indicate that the master is requesting
another data beat following the current one.
CS[0:3]
CSx is asserted by the master to indicate that this transaction is
targeted for a particular memory bank on the Primary external
bus.
DATA[0:31]
OE
EBI
EBI
The DATA[0:31] signals contain the data to be transferred for the
current transaction.
OE is used to indicate when an external memory is permitted to
drive back read data. External memories must have their data
output buffers off when OE is negated. OE is only asserted for
chip-select accesses.
RD_WR
EBI
RD_WR indicates whether the current transaction is a read
access or a write access.
MPC5644A Microcontroller Data Sheet, Rev. 7
58
Freescale Semiconductor
Table 5. Signal details (continued)
Signal
Module or Function
EBI
Description
TA
TA is asserted to indicate that the slave has received the data
(and completed the access) for a write cycle, or returned data for
a read cycle. If the transaction is a burst read, TA is asserted for
each one of the transaction beats. For write transactions, TA is
only asserted once at access completion, even if more than one
write data beat is transferred.
TS
EBI
EBI
EBI
The Transfer Start signal (TS) is asserted by the MPC5644A to
indicate the start of a transfer.
WE[2:3]
Write enables are used to enable program operations to a
particular memory. WE[2:3] are only asserted for write accesses
WE[0:3]/BE[0:3]
Write enables are used to enable program operations to a
particular memory. These signals can also be used as byte
enables for read and write operation by setting the WEBS bit in
the appropriate EBI Base Register (EBI_BRn). WE[0:3] are only
asserted for write accesses. BE[0:3] are asserted for both read
and write accesses
eMIOS[0:23]
AN[0:39]
FCK
eMIOS
eQADC
eQADC
eQADC
eMIOS I/O channels
Single-ended analog inputs for analog-to-digital converter
eQADC free running clock for eQADC SSI.
MA[0:2]
These three control bits are output to enable the selection for an
external Analog Mux for expansion channels.
REFBYPC
SDI
eQADC
Bypass capacitor input
Serial data in
eQADC
SDO
eQADC
Serial data out
SDS
eQADC
Serial data select
VRH
eQADC
Voltage reference high input
Voltage reference low input
eSCI receive
VRL
eQADC
SCI_A_RX
SCI_B_RX
SCI_C_RX
eSCI_A - eSCI_C
SCI_A_TX
SCI_B_TX
SCI_C_TX
eSCI_A - eSCI_C
eTPU
eSCI transmit
ETPU_A[0:31]
eTPU I/O channel
RCH0_[A:C]
RCH1_[A:C]
RCH2_[A:C]
RCH3_[A:C]
RCH4_[A:C]
RCH5_[A:C]
eTPU2
Reaction Module
eTPU2 reaction channels. Used to control external actuators,
e.g., solenoid control for direct injection systems and valve
control in automatic transmissions
TCRCLKA
eTPU2
Input clock for TCR time base
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
59
Table 5. Signal details (continued)
Module or Function Description
Signal
CAN_A_TX
CAN_B_TX
CAN_C_TX
FlexCan_A -
FlexCAN_C
FlexCAN transmit
CAN_A_RX
CAN_B_RX
CAN_C_RX
FlexCAN_A -
FlexCAN_C
FlexCAN receive
FR_A_RX
FR_B_RX
FlexRay
FlexRay
FlexRay
FlexRay receive (Channels A, B)
FlexRay transmit enable (Channels A, B)
Flexray transmit (Channels A, B)
FR_A_TX_EN
FR_B_TX_EN
FR_A_TX
FR_B_TX
JCOMP
TCK
JTAG
JTAG
JTAG
JTAG
JTAG
Nexus
Enables the JTAG TAP controller.
Clock input for the on-chip test logic.
TDI
Serial test instruction and data input for the on-chip test logic.
Serial test data output for the on-chip test logic.
Controls test mode operations for the on-chip test logic.
TDO
TMS
EVTI
EVTI is an input that is read on the negation of RESET to enable
or disable the Nexus Debug port. After reset, the EVTI pin is
used to initiate program synchronization messages or generate
a breakpoint.
EVTO
Nexus
Nexus
Nexus
Output that provides timing to a development tool for a single
watchpoint or breakpoint occurrence.
MCKO
MCKO is a free running clock output to the development tools
which is used for timing of the MDO and MSEO signals.
MDO[0:11]1
Trace message output to development tools. This pin also
indicates the status of the crystal oscillator clock following a
power-on reset, when MDO[0] is driven high until the crystal
oscillator clock achieves stability and is then negated.
MSEO[0:1]1
RDY
Nexus
Nexus
Output pin—Indicates the start or end of the variable length
message on the MDO pins
Nexus Ready Output (RDY) is an output that indicates to the
development tools the data is ready to be read from or written to
the Nexus read/write access registers.
MPC5644A Microcontroller Data Sheet, Rev. 7
60
Freescale Semiconductor
Table 5. Signal details (continued)
Signal
Module or Function
SIU - Configuration
Description
BOOTCFG[0:1]
Two BOOTCFG signals are implemented in MPC5644A MCUs.
The BAM program uses the BOOTCFG0 bit to determine where
to read the reset configuration word, and whether to initiate a
FlexCAN or eSCI boot.
The BOOTCFG1 pin is sampled during the assertion of the
RSTOUT signal, and the value is used to update the RSR and
the BAM boot mode
See the MPC5644A Microcontroller Reference Manual for more
information.
The following values are for BOOTCFG[0:1}:
00:Boot from internal flash memory
01:FlexCAN/eSCI boot
10:Boot from external memory using EBI
11:Reserved
Note: For the 176-pin QFP and 208-ball BGA packages
BOOTCFG[0] is always 0 since the EBI interface is not available.
WKPCFG
SIU - Configuration
The WKPCFG pin is applied at the assertion of the internal reset
signal (assertion of RSTOUT), and is sampled 4 clock cycles
before the negation of the RSTOUT pin.
The value is used to configure whether the eTPU and eMIOS
pins are connected to internal weak pull up or weak pull down
devices after reset. The value latched on the WKPCFG pin at
reset is stored in the Reset Status Register (RSR), and is
updated for all reset sources except the Debug Port Reset and
Software External Reset.
0: Weak pulldown applied to eTPU and eMIOS pins at reset
1: Weak pullup applied to eTPU and eMIOS pins at reset.
ETRIG[2:3]
SIU - eQADC Triggers External signal eTRIGx triggers eQADC CFIFOx
SIU - eQADC Triggers External signal eTRIGx triggers eQADC CFIFOx
GPIO[206] ETRIG0
(Input)
GPIO[207] ETRIG1
(Input)
SIU - eQADC Triggers External signal eTRIGx triggers eQADC CFIFOx
IRQ[0:5]
SIU - External Interrupts The IRQ[0:15] pins connect to the SIU IRQ inputs. IMUX Select
IRQ[7:15]
Register 1 is used to select the IRQ[0:15] pins as inputs to the
IRQs.
See the MPC5644A Microcontroller Reference Manual for more
information.
NMI
SIU - External Interrupts Non-Maskable Interrupt
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
61
Table 5. Signal details (continued)
Signal
GPIO[0:3]
Module or Function
Description
SIU - GPIO
SIU - Reset
SIU - Reset
SIU - Reset
Configurable general purpose I/O pins. Each GPIO input and
output is separately controlled by an 8-bit input (GPDI) or output
(GPDO) register. Additionally, each GPIO pins is configured
using a dedicated SIU_PCR register.
GPIO[8:43]
GPIO[62:65]
GPIO[68:70]
GPIO[75:145]
GPIO[179:204]
GPIO[208:213]
GPIO[219]
The GPIO pins are generally multiplexed with other I/O pin
functions.
GPIO[244:245]
See The MPC5644A Microcontroller Reference Manual for more
information.
•
RESET
The RESET pin is an active low input. The RESET pin is
asserted by an external device during a power-on or external
reset. The internal reset signal asserts only if the RESET pin
asserts for 10 clock cycles. Assertion of the RESET pin while the
device is in reset causes the reset cycle to start over.
The RESET pin has a glitch detector which detects spikes
greater than two clock cycles in duration that fall below the
switch point of the input buffer logic of the VDDEH input pins.
The switch point lies between the maximum VIL and minimum
VIH specifications for the VDDEH input pins.
RSTCFG
Used to enable or disable the PLLREF and the BOOTCFG[0:1]
configuration signals.
0: Get configuration information from BOOTCFG[0:1] and
PLLREF
1: Use default configuration of booting from internal flash with
crystal clock source
Note: For the 176-pin QFP and 208-ball BGA packages
RSTCFG is always 0, so PLLREF and BOOTCFG signals
are used.
RSTOUT
The RSTOUT pin is an active low output that uses a push/pull
configuration. The RSTOUT pin is driven to the low state by the
MCU for all internal and external reset sources. There is a delay
between initiation of the reset and the assertion of the RSTOUT
pin.
1
Do not connect pin directly to a power supply or ground.
MPC5644A Microcontroller Data Sheet, Rev. 7
62
Freescale Semiconductor
Table 6. Power/ground segmentation
Power Segment
Voltage
I/O Pins Powered by Segment
VDDE2
VDDE3
VDDE5
1.8 V - 3.3 V
1.8 V - 3.3 V
1.8 V - 3.3 V
CS0, CS1, CS2, CS3,RD_WR, BDIP, WE0, WE1, OE, TS, TA
ADDR12, ADDR13, ADDR14, ADDR15
DATA0, DATA1, DATA2, DATA3, DATA4, DATA5, DATA6,
DATA7, DATA8, DATA9, DATA10, DATA11, DATA12, DATA13,
DATA14, DATA15, CLKOUT, ENGCLK
VDDE12
1.8 V - 3.3 V
CAL_CS0, CAL_CS2, CAL_CS3 CAL_ADDR12,
CAL_ADDR13, CAL_ADDR14, CAL_ADDR15,
CAL_ADDR16, CAL_ADDR17, CAL_ADDR18,
CAL_ADDR19, CAL_ADDR20, CAL_ADDR21,
CAL_ADDR22, CAL_ADDR23, CAL_ADDR24,
CAL_ADDR25, CAL_ADDR26, CAL_ADDR27,
CAL_ADDR28, CAL_ADDR29, CAL_ADDR30, CAL_DATA0,
CAL_DATA1, CAL_DATA2, CAL_DATA3, CAL_DATA4,
CAL_DATA5, CAL_DATA6, CAL_DATA7, CAL_DATA8,
CAL_DATA9, CAL_DATA10, CAL_DATA11, CAL_DATA12,
CAL_DATA13, CAL_DATA14, CAL_DATA15, CAL_RD_WR,
CAL_WE0, CAL_WE1, CAL_OE, CAL_TS
VDDE-EH
VDDEH1
3.0 V - 5 V
ADDR16, ADDR17, ADDR18, ADDR19, ADDR20, ADDR21,
ADDR22, ADDR23, ADDR24, ADDR25, ADDR26, ADDR27,
ADDR28, ADDR29, ADDR30, ADDR31
3.3 V - 5.0 V
ETPUA10, ETPUA11, ETPUA12, ETPUA13, ETPUA14,
ETPUA15, ETPUA16, ETPUA17, ETPUA18, ETPUA19,
ETPUA20, ETPUA21, ETPUA22, ETPUA23, ETPUA24,
ETPUA25, ETPUA26, ETPUA27, ETPUA28, ETPUA29,
ETPUA30, ETPUA31
VDDEH4
VDDEH6
3.3 V - 5.0 V
EMIOS0, EMIOS1, EMIOS2, EMIOS3, EMIOS4, EMIOS5,
EMIOS6, EMIOS7, EMIOS8, EMIOS9, EMIOS10, EMIOS11,
EMIOS12, EMIOS13, EMIOS14, EMIOS15, EMIOS16,
EMIOS17, EMIOS18, EMIOS19, EMIOS20, EMIOS21,
EMIOS22, EMIOS23, TCRCLKA, ETPUA0, ETPUA1,
ETPUA2, ETPUA3, ETPUA4, ETPUA5, ETPUA6, ETPUA7,
ETPUA8, ETPUA9, ETPUA0
3.3 V - 5.0 V
RESET, RSTOUT, PLLREF, PLLCFG1, RSTCFG,
BOOTCFG0, BOOTCFG1, WKPCFG, CAN_A_TX,
CAN_A_RX, CAN_B_TX, CAN_B_RX, CAN_C_TX,
CAN_C_RX, SCI_A_TX, SCI_A_RX, SCI_B_TX, SCI_C_RX,
DSPI_B_SCK, DSPI_B_SIN, DSPI_B_SOUT,
DSPI_B_PCS[0], DSPI_B_PCS[1], DSPI_B_PCS[2],
DSPI_B_PCS[3], DSPI_B_PCS[4], DSPI_B_PCS[5],
SCI_B_RX, SCI_C_TX, EXTAL, XTAL
VDDEH7
3.3 V - 5.0 V
EMIOS14, EMIOS 15, GPIO98, GPIO99, GPIO203, GPIO204,
GPIO206, GPIO207, GPIO219, EVTI, EVTO, MDO4, MDO5,
MDO6, MDO7, MDO8, MDO9, MDO10, MDO11, MSEO0,
MSEO1, RDY, TCK, TDI, TDO, TMS, JCOMP, DSPI_A_SCK,
DSPI_A_SIN, DSPI_A_SOUT, DSPI_A_PCS[0],
DSPI_A_PCS[1], DSPI_A_PCS[4], DSPI_A_PCS[5],
AN12-SDS, AN13-SDO, AN14-SDI, AN15-FCK
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
63
Table 6. Power/ground segmentation
Voltage I/O Pins Powered by Segment
Power Segment
VDDA
5 V
AN0, AN1, AN2, AN3, AN4, AN5, AN6, AN7, AN8, AN9, AN10,
AN11, AN16, AN17, AN18, AN19, AN20, AN21, AN22, AN23,
AN24, AN25, AN26, AN27, AN28, AN29, AN30, AN31, AN32,
AN33, AN34, AN35, AN36, AN37, AN38, AN39, VRH, VRL,
REFBYBC
VRC331
3.3 V
MCKO, MDO0, MDO1, MDO2, MDO3
Other Power Segments
VDDREG
VRCCTL
VDDPLL
VSTBY
5 V
—
—
—
—
—
1.2 V
0.95–1.2 V
(unregulated mode)
2.0–5.5 V
(regulated mode)
—
—
VSS
—
1
Do not use VRC33 to drive external circuits.
MPC5644A Microcontroller Data Sheet, Rev. 7
64
Freescale Semiconductor
3
Electrical characteristics
This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing
specifications for the MPC5644A series of MCUs.
The electrical specifications are preliminary and are from previous designs, design simulations, or initial evaluation. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however for production silicon
these specifications will be met. Finalized specifications will be published after complete characterization and device
qualifications have been completed.
In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller
Characteristics is included in the Symbol column.
In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol
“SR” for System Requirement is included in the Symbol column.
3.1
Parameter classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding, the classifications listed in Table 7 are used and the parameters are tagged accordingly in the tables where
appropriate.
Table 7. Parameter classifications
Classification tag
Tag description
P
C
Those parameters are guaranteed during production testing on each individual device.
Those parameters are achieved by the design characterization by measuring a statistically
relevant sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical
devices under typical conditions unless otherwise noted. All values shown in the typical column
are within this category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
3.2
Maximum ratings
1
Table 8. Absolute maximum ratings
Value
Symbol
Parameter
Conditions
Unit
min
max
VDD
SR 1.2 V core supply voltage2
SR Flash core voltage3,4
–0.3
–0.3
–0.3
–0.3
–0.3
1.32
3.6
6
V
V
V
V
V
VFLASH
VSTBY
VDDPLL
VRC33
SR SRAM standby voltage5
SR Clock synthesizer voltage
1.32
3.6
SR Voltage regulator control
input voltage4
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
65
1
Table 8. Absolute maximum ratings (continued)
Value
max
Symbol
Parameter
Conditions
Unit
min
VDDA
SR Analog supply voltage5
SR I/O supply voltage4,6
SR I/O supply voltage5
SR DC input voltage7
Reference to VSSA
–0.3
–0.3
–0.3
–1.08
5.5
3.6
5.5
V
V
V
V
VDDE
VDDEH
VIN
VDDEH powered I/O pads
VDDEH
+ 0.3 V9
VDDE powered I/O pads
–1.010
VDDE
+
0.3 V10
VDDA powered I/O pads
Reference to VRL
–1.0
–0.3
5.5
VDDREG
SR Voltage regulator supply
voltage
5.5
V
V
VRH
SR Analog reference high
voltage
–0.3
5.5
V
SS – VSSA
SR VSS differential voltage
SR VREF differential voltage
–0.1
–0.3
–0.3
0.1
5.5
0.3
V
V
V
V
RH – VRL
VRL – VSSA
SR VRL to VSSA differential
voltage
V
SSPLL – VSS SR VSSPLL to VSS differential
–0.1
–3
0.1
3
V
voltage
IMAXD
IMAXA
TJ
SR Maximum DC digital input
current11
Per pin, applies to all
digital pins
mA
mA
oC
SR Maximum DC analog input
current12
Per pin, applies to all
analog pins
—
5
SR Maximum operating
temperature range - die
junction temperature
–40.0
150.0
TSTG
TSDR
SR Storage temperature range
–55.0
—
150.0
260.0
oC
oC
SR Maximum solder
temperature13
MSL
SR Moisture sensitivity level14
—
3
1
Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are
stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima
may affect device reliability or cause permanent damage to the device.
2
3
Allowed 2 V for 10 hours cumulative time, remaining time at 1.2 V +10%.
The VFLASH supply is connected to VRC33 in the package substrate. This specification applies to calibration
package devices only.
4
5
Allowed 5.3 V for 10 hours cumulative time, remaining time at 3.3 V +10%.
Allowed 5.9 V for 10 hours cumulative time, remaining time at 5 V +10%.
MPC5644A Microcontroller Data Sheet, Rev. 7
66
Freescale Semiconductor
6
7
All functional non-supply I/O pins are clamped to VSS and VDDE, or VDDEH
.
AC signal overshoot and undershoot of up to 2.0 V of the input voltages is permitted for an accumulative
duration of 60 hours over the complete lifetime of the device (injection current not limited for this duration).
8
9
Internal structures hold the voltage greater than –1.0 V if the injection current limit of 2 mA is met.
Internal structures hold the input voltage less than the maximum voltage on all pads powered by VDDEH
supplies, if the maximum injection current specification is met (2 mA for all pins) and VDDEH is within the
operating voltage specifications.
10 Internal structures hold the input voltage less than the maximum voltage on all pads powered by VDDE supplies,
if the maximum injection current specification is met (2 mA for all pins) and VDDE is within the operating voltage
specifications.
11 Total injection current for all pins (including both digital and analog) must not exceed 25 mA.
12 Total injection current for all analog input pins must not exceed 15 mA.
13 Solder profile per IPC/JEDEC J-STD-020D.
14 Moisture sensitivity per JEDEC test method A112.
3.3
Thermal characteristics
1
Table 9. Thermal characteristics for 176-pin QFP
Symbol
RJA
C
Parameter
Conditions
Value
Unit
CC D Junction-to-Ambient, Natural Convection2
CC D Junction-to-Ambient, Natural Convection2
CC D Junction-to-Moving-Air, Ambient2
Single layer board - 1s
Four layer board - 2s2p
38
31
30
°C/W
°C/W
°C/W
RJA
RJMA
200 ft./min., single layer
board - 1s
RJMA
CC D Junction-to-Moving-Air, Ambient2
at 200 ft./min., four layer
board - 2s2p
25
°C/W
RJB
RJCtop
JT
CC D Junction-to-Board3
CC D Junction-to-Case4
20
5
°C/W
°C/W
°C/W
CC D Junction-to-Package Top, Natural
Convection5
2
1
2
Thermal characteristics are targets based on simulation that are subject to change per device characterization.
Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board
meets JEDEC specification for this package.
3
4
5
Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package.
Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.
Thermal characterization parameter indicating the temperature difference between the package top and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization
parameter is written as Psi-JT.
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
67
1
Table 10. Thermal characteristics for 208-pin MAPBGA
Symbol
RJA
C
Parameter
CC D Junction-to-Ambient, Natural Convection2,3 One layer board - 1s
CC D Junction-to-Ambient, Natural Convection2,4 Four layer board - 2s2p
Conditions
Value
Unit
39
24
31
°C/W
°C/W
°C/W
RJA
RJMA
CC D Junction-to-Moving-Air, Ambient2,4
at 200 ft./min., one layer
board
RJMA
CC D Junction-to-Moving-Air, Ambient2,4
at 200 ft./min., four layer
board 2s2p
20
°C/W
RJB
RJC
JT
CC D Junction-to-board5
Four layer board - 2s2p
13
6
°C/W
°C/W
°C/W
CC D Junction-to-case6
CC D Junction-to-package top natural convection7
2
1
2
Thermal characteristics are targets based on simulation that are subject to change per device characterization.
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
3
4
5
Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
6
7
Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate
method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature.
Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter
is written as Psi-JT.
1
Table 11. Thermal characteristics for 324-pin TEPBGA
Symbol
RJA
C
Parameter
Conditions
Value
Unit
CC D Junction-to-Ambient, Natural Convection2
CC D Junction-to-Ambient, Natural Convection2
CC D Junction-to-Moving-Air, Ambient2
Single layer board - 1s
Four layer board - 2s2p
29
19
23
°C/W
°C/W
°C/W
RJA
RJMA
at 200 ft./min., single layer
board
RJMA
CC D Junction-to-Moving-Air, Ambient2
at 200 ft./min., four layer
board 2s2p
16
°C/W
RJB
RJCtop
JT
CC D Junction-to-Board3
CC D Junction-to-Case4
10
7
°C/W
°C/W
°C/W
CC D Junction-to-Package Top, Natural
Convection5
2
1
2
Thermal characteristics are targets based on simulation that are subject to change per device characterization.
Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board
meets JEDEC specification for this package.
3
4
Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package.
Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.
MPC5644A Microcontroller Data Sheet, Rev. 7
68
Freescale Semiconductor
5
Thermal characterization parameter indicating the temperature difference between the package top and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization
parameter is written as Psi-JT.
3.3.1
General notes for specifications at maximum junction temperature
An estimation of the chip junction temperature, T , can be obtained from the equation:
J
T = T + (R
* P )
Eqn. 1
J
A
JA
D
where:
o
T = ambient temperature for the package ( C)
A
o
R
= junction-to-ambient thermal resistance ( C/W)
JA
P = power dissipation in the package (W)
D
The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide consistent values for
estimations and comparisons. The difference between the values determined for the single-layer (1s) board compared to a
four-layer board that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal resistance
is not a constant. The thermal resistance depends on the:
•
•
•
•
Construction of the application board (number of planes)
Effective size of the board which cools the component
Quality of the thermal and electrical connections to the planes
Power dissipated by adjacent components
Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package
to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance
between the vias leave the planes virtually disconnected, the thermal performance is also greatly reduced.
As a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit
board. The value obtained on a board with the internal planes is usually within the normal range if the application board has:
•
•
•
One oz. (35 micron nominal thickness) internal planes
Components are well separated
2
Overall power dissipation on the board is less than 0.02 W/cm
The thermal performance of any component depends on the power dissipation of the surrounding components. In addition, the
ambient temperature varies widely within the application. For many natural convection and especially closed box applications,
the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the
device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the
local ambient conditions that determine the temperature of the device.
At a known board temperature, the junction temperature is estimated using the following equation:
T = T + (R
* P )
Eqn. 2
J
B
JB
D
where:
o
T = board temperature for the package perimeter ( C)
B
o
R
= junction-to-board thermal resistance ( C/W) per JESD51-8S
JB
P = power dissipation in the package (W)
D
When the heat loss from the package case to the air does not factor into the calculation, an acceptable value for the junction
temperature is predictable. Ensure the application board is similar to the thermal test condition, with the component soldered to
a board with internal planes.
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
69
The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-ambient thermal
resistance:
R
= R
+ R
CA
Eqn. 3
JA
JC
where:
o
R
R
R
= junction-to-ambient thermal resistance ( C/W)
JA
JC
CA
o
= junction-to-case thermal resistance ( C/W)
o
= case to ambient thermal resistance ( C/W)
R
is device related and is not affected by other factors. The thermal environment can be controlled to change the
JC
case-to-ambient thermal resistance, R
. For example, change the air flow around the device, add a heat sink, change the
CA
mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding
the device. This description is most useful for packages with heat sinks where 90% of the heat flow is through the case to heat
sink to ambient. For most packages, a better model is required.
A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal resistance and the
junction-to-case thermal resistance. The junction-to-case thermal resistance describes when using a heat sink or where a
substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the
thermal performance when most of the heat is conducted to the printed circuit board. This model can be used to generate simple
estimations and for computational fluid dynamics (CFD) thermal models.
To determine the junction temperature of the device in the application on a prototype board, use the thermal characterization
parameter ( ) to determine the junction temperature by measuring the temperature at the top center of the package case using
JT
the following equation:
T = T + ( x P )
Eqn. 4
J
T
JT
D
where:
o
T = thermocouple temperature on top of the package ( C)
T
o
= thermal characterization parameter ( C/W)
JT
P = power dissipation in the package (W)
D
The thermal characterization parameter is measured in compliance with the JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top center of the package case. Position the thermocouple so that the thermocouple junction rests
on the package. Place a small amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from
the junction. Place the thermocouple wire flat against the package case to avoid measurement errors caused by the cooling
effects of the thermocouple wire.
References:
Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134
USA
(408) 943-6900
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or
303-397-7956.
JEDEC specifications are available on the WEB at http://www.jedec.org.
•
C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine
Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.
•
G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled Applications”, Electronic
Packaging and Production, pp. 53-58, March 1998.
MPC5644A Microcontroller Data Sheet, Rev. 7
70
Freescale Semiconductor
•
B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application
in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.
3.4
EMI (electromagnetic interference) characteristics
1
Table 12. EMI Testing Specifications
Frequency
Range
Level
(Max)
Symbol
Radiated
emissions,
electric field
Parameter
Conditions
Clocks
Unit
VRE_TEM
VDDREG = 5.25 V;
TA = 25 °C
16 MHz crystal 150 kHz – 50 MHz
20
20
26
26
K
dBV
40 MHz bus
No PLL frequency
50 – 150 MHz
150 kHz – 30 MHz
RBW 9 kHz, Step
Size 5 kHz
modulation
150 – 500 MHz
500 – 1000 MHz
IEC Level
—
—
30 MHz – 1 GHz -
RBW 120 kHz, Step
Size 80 kHz
SAE Level
3
16 MHz crystal 150 kHz– 50 MHz
40 MHz bus
50 – 150 MHz
±2% PLL
13
13
11
13
L
dBV
frequency
modulation
150 – 500 MHz
500 – 1000 MHz
IEC Level
—
—
SAE Level
2
1
EMI testing and I/O port waveforms per SAE J1752/3 issued 1995-03 and IEC 61967-2.
3.5
Electrostatic discharge (ESD) characteristics
1,2
Table 13. ESD ratings
Symbol
Parameter
Conditions
Value
Unit
—
SR
SR
SR
SR
ESD for Human Body Model (HBM)
HBM circuit description
—
—
—
2000
1500
100
500
750
1
V
R1
C
pF
V
—
ESD for field induced charge Model
(FDCM)
All pins
Corner pins
—
SR
Number of pulses per pin
Positive pulses (HBM)
Negative pulses (HBM)
—
—
—
—
1
—
SR
Number of pulses
1
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated
Circuits.
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
71
2
Device failure is defined as: “If after exposure to ESD pulses, the device does not meet the device specification
requirements, which includes the complete DC parametric and functional testing at room temperature and hot
temperature.”
3.6
Power management control (PMC) and power on reset (POR)
electrical specifications
Table 14. PMC Operating Conditions and External Regulators Supply Voltage
ID
Name
Parameter
Min
Typ
Max
Unit
1
2
3
Jtemp SR — Junction temperature
–40
4.75
1.262
27
5
150
5.25
1.32
°C
V
Vddreg
Vdd
SR — PMC 5 V supply voltage VDDREG
SR — Core supply voltage 1.2 V VDD when external
regulator is used without disabling the internal
regulator (PMC unit turned on, LVI monitor
active)1
1.3
V
3a
—
SR — Core supply voltage 1.2 V VDD when external
regulator is used with a disabled internal
regulator (PMC unit turned-off, LVI monitor
disabled)
1.14
1.2
1.32
V
4
5
Ivdd
SR — Voltage regulator core supply maximum
required DC output current
400
3.3
—
—
mA
V
Vdd33
SR — Regulated 3.3 V supply voltage when external
regulator is used without disabling the internal
regulator (PMC unit turned-on, internal 3.3V
regulator enabled, LVI
3.45
3.6
monitor active)3
5a
6
—
—
SR — Regulated 3.3 V supply voltage when external
regulator is used with a disabled internal
regulator (PMC unit turned-off, LVI monitor
disabled)
3
3.3
—
3.6
—
V
SR — Voltage regulator 3.3 V supply maximum
required DC output current
80
mA
1
2
3
An internal regulator controller can be used to regulate core supply.
The minimum supply required for the part to exit reset and enter in normal run mode is 1.28 V.
An internal regulator can be used to regulate 3.3 V supply.
MPC5644A Microcontroller Data Sheet, Rev. 7
72
Freescale Semiconductor
Table 15. PMC Electrical Characteristics
ID
Name
VBG
Parameter
Min
Typ
Max
Unit
Notes
1
CC C Nominal bandgap voltage
reference
—
1.219
—
V
1a
1b
—
—
CC
CC
P
Untrimmed bandgap
reference voltage
VBG - 7%
VBG
VBG
Vbg + 6%
V
V
P
Trimmed bandgap
reference voltage (5 V,
27 °C)
VBG
-10mV
VBG +
10mV
1c
1d
2
—
—
CC C Bandgap reference
temperature variation
—
—
—
100
3000
1.28
—
—
—
ppm
/°C
CC C Bandgap reference supply
voltage variation
ppm
/V
Vdd
CC C Nominal VDD core supply
internal regulator target DC
output voltage1
V
2a
2b
—
—
CC
P
Nominal VDD core supply
internal regulator target DC
output voltage variation at
power-on reset
Vdd - 6%
Vdd
Vdd
Vdd + 10%
Vdd + 3%
V
CC
P
Nominal VDD core supply
internal regulator target DC
output voltage variation
after power-on reset
Vdd - 10%2
V
2c
2d
—
CC C Trimming step Vdd
—
20
—
—
—
mV
mA
Ivrcctl
CC C Voltage regulator controller
for core supply maximum
DC output current
20
3
Lvi1p2
—
CC C Nominal LVI for rising core
supply3
—
1.160
1.200
—
V
V
3a
CC C Variation of LVI for rising
core supply at power-on
reset
1.120
1.280
See note 4
See note 4
3b
3c
—
—
CC C Variation of LVI for rising
core supply after power-on
reset
Lvi1p2 -
3%
Lvi1p2
20
Lvi1p2 +
3%
V
CC C Trimming step LVI core
supply
—
—
mV
3d
4
Lvi1p2_h CC C LVI core supply hysteresis
Por1.2V_r CC C POR 1.2 V rising
—
—
40
—
—
mV
V
0.709
4a
—
CC C POR 1.2 V rising variation Por1.2V_r- Por1.2V_r Por1.2V_r
V
35%
+ 35%
4b Por1.2V_f CC C POR 1.2 V falling
4c
—
0.638
—
V
V
—
CC C POR 1.2 V falling variation Por1.2V_f- Por1.2V_f Por1.2V_f+
35%
35%
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
73
Table 15. PMC Electrical Characteristics (continued)
ID
Name
Vdd33
Parameter
Min
Typ
Max
Unit
Notes
5
CC C Nominal 3.3 V supply
internal regulator DC output
voltage
—
3.39
—
V
5a
5b
—
—
CC
P
Nominal 3.3 V supply
internal regulator DC output
voltage variation at
power-on reset
Vdd33 -
8.5%
Vdd33
Vdd33
Vdd3 + 7% V
See note 5
CC
P
Nominal 3.3 V supply
internal regulator DC output
voltage variation power-on
reset
Vdd33 -
7.5%
Vdd33 +
7%
V
With internal
load up
to Idd3p3
5c
5d
—
CC D Voltage regulator 3.3 V
output impedance at
—
—
—
2
maximum DC load
Idd3p3
CC
P
Voltage regulator 3.3 V
maximum DC output
current (internal regulator
enabled)6
807
—
mA
5e Vdd33 ILim CC C Voltage regulator 3.3 V DC
current limit
—
—
130
—
—
mA
V
6
Lvi3p3
CC C Nominal LVI for rising 3.3 V
supply
3.090
The Lvi3p3
specs are also
valid for the
Vddeh LVI
6a
6b
—
—
—
CC C Variation of LVI for rising
3.3 V supply at power-on
reset
Lvi3p3 -
6%
Lvi3p3
Lvi3p3
Lvi3p3 +
6%
V
V
See note 8
CC C Variation of LVI for rising
3.3 V supply after power-on
reset
Lvi3p3 -
3%
Lvi3p3 +
3%
See note 8
6c
6d
7
CC C Trimming step LVI 3.3 V
—
—
—
20
60
—
—
—
mV
mV
V
Lvi3p3_h CC C LVI 3.3 V hysteresis
Por3.3V_r CC C Nominal POR for rising
3.3 V supply
2.07
The 3.3V POR
specs are also
valid for the
VDDEH POR
7a
—
CC C Variation of POR for rising Por3.3V_r- Por3.3V_r Por3.3V_r
V
V
V
V
3.3 V supply
35%
+ 35%
7b Por3.3V_f CC C Nominal POR for falling
3.3 V supply
—
1.95
—
7c
—
CC C Variation of POR for falling Por3.3V_f- Por3.3V_f Por3.3V_f+
3.3 V supply
35%
35%
8
Lvi5p0
CC C Nominal LVI for rising 5 V
—
4.290
—
VDDREG supply
MPC5644A Microcontroller Data Sheet, Rev. 7
74
Freescale Semiconductor
Table 15. PMC Electrical Characteristics (continued)
ID
Name
Parameter
Min
Typ
Max
Unit
Notes
8a
—
—
—
CC C Variation of LVI for rising
5 V VDDREG supply at
power-on reset
Lvi5p0 -
6%
Lvi5p0
Lvi5p0 +
6%
V
8b
CC C Variation of LVI for rising
5 V VDDREG supply
Lvi5p0 -
3%
Lvi5p0
Lvi5p0 +
3%
V
power-on reset
8c
8d
9
CC C Trimming step LVI 5 V
—
—
—
20
60
—
—
—
mV
mV
V
Lvi5p0_h CC C LVI 5 V hysteresis
Por5V_r CC C Nominal POR for rising 5 V
2.67
VDDREG supply
9a
9b
9c
—
CC C Variation of POR for rising
5 V VDDREG supply
Por5V_r
- 35%
Por5V_r
2.47
Por5V_r
+ 50%
V
V
V
Por5V_f CC C Nominal POR for falling 5 V
VDDREG supply
—
—
—
CC C Variation of POR for falling
5 V VDDREG supply
Por5V_f
- 35%
Por5V_f
Por5V_f
+ 50%
1
2
3
4
Using external ballast transistor.
Min range is extended to 10% since Lvi1p2 is reprogrammed from 1.2 V to 1.16 V after power-on reset.
LVI for falling supply is calculated as LVI rising – LVI hysteresis.
Lvi1p2 tracks DC target variation of internal Vdd regulator. Minimum and maximum Lvi1p2 correspond to minimum
and maximum Vdd DC target respectively.
5
Minimum loading (<10 mA) for reading trim values from flash, powering internal RC oscillator, and IO consumption
during POR.
6
7
No external load is allowed, except for use as a reference for an external tool.
This value is valid only when the internal regulator is bypassed. When the internal regulator is enabled, the
maximum external load allowed on the Nexus pads is 30 pF at 40 MHz.
8
Lvi3p3 tracks DC target variation of internal Vdd33 regulator. Minimum and maximum Lvi3p3 correspond to
minimum and maximum Vdd33 DC target respectively.
3.6.1
Voltage regulator controller (VRC) electrical specifications
Table 16. VRC electrical specifications
Symbol
Parameter
Min.
Max.
Units
Current can be sourced by VRCCTL at Tj:
25 oC
150 oC
– 40 oC
25 oC
TBD
TBD
TBD
—
—
—
—
mA
mA
—
1
IVRCCTL
Required gain at Tj:
1,3,4
IDD IVRCCTL (fsys = fMAX
)
BETA 2
TBD
TBD
—
150 oC
TBD
—
1
IVRCCTL is measured at the following conditions: VDD = 1.35 V, VRC33 = 3.1 V, VVRCCTL = 2.2 V.
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
75
2
BETA represents the worst-case external transistor. It is measured on a per-part basis and calculated as
(IDD IVRCCTL).
Refer to Table 52 for the maximum operating frequency.
3
4
Values are based on IDD from high-use applications as explained in the IDD Electrical Specification.
3.6.2
Regulator Example
In designs where the MPC5644A microcontroller’s internal regulators are used, a ballast is required for generation of the 1.2 V
internal supply. No ballast is required when an external 1.2 V supply is used.
The resistor may or may not be
required. This depends on the
VDDREG
allowable power dissipation of
the npn bypass transistor
device. The resistor may be
Creg
Rc
used to limit the in-rush current
at power on.
The bypass transistor
MUST be operated out
of saturation region.
Cc
VRCCTL
MCU
Rb
Keep parasitic inductance
under 20nH
Re
VDD
Mandatory decoupling
capacitor network
Cb
VSS
Ce
Cd
VRCCTL capacitor and resistor is required
Figure 8. Core voltage regulator controller external components preferred configuration
Table 17. MPC5644A External network specification
External Network
Min
Typ
Max
Comment
Parameter
T1
NJD2873 or BCP68
only
Cb
Ce
1.1 F
3*2.35F+5F
2.2F
2.97F
3*6.35F+13.5F
50m
X7R,-50%/+35%
X7R, -50%/+35%
3*4.7F+10F
Equivalent ESR of 5m
Ce capacitors
Cd
Rb
4*50nF
9
4*100nF
4*135nF
X7R, -50%/+35%
+/-10%
10
11
MPC5644A Microcontroller Data Sheet, Rev. 7
76
Freescale Semiconductor
Table 17. MPC5644A External network specification
External Network
Parameter
Min
Typ
Max
Comment
Re
0.252
0.280
10F
0.308
+/-10%
Creg
It depends on
external Vreg.
Cc
Rc
5F
10F
13.5F
5.6
X7R, -50%/+35%
1.1
May or may not be
required. It depends
on the allowable
power dissipation of
T1.
3.6.3
Recommended power transistors
TM
The following NPN transistors are recommended for use with the on-chip voltage regulator controller: ON Semiconductor
BCP68T1 or NJD2873 as well as Philips Semiconductor BCP68. The collector of the external transistor is preferably
TM
connected to the same voltage supply source as the output stage of the regulator.
Table 18. Recommended operating characteristics
Symbol
FE () DC current gain (Beta)
PD Absolute minimum power dissipation
Parameter
Value
Unit
h
60 – 550
—
W
>1.0
(1.5 preferred)
ICMaxDC Minimum peak collector current
1.0
A
mV
V
VCESAT Collector-to-emitter saturation voltage
200 – 6001
VBE
Base-to-emitter voltage
0.4 – 1.0
1
Adjust resistor at bipolar transistor collector for 3.3 V/5.0 V to avoid VCE < VCESAT
.
3.7
Power up/down sequencing
There is no power sequencing required among power sources during power up and power down, in order to operate within
specification.
Although there are no power up/down sequencing requirements to prevent issues such as latch-up or excessive current spikes
the state of the I/O pins during power up/down varies according to Table 19 for all pins with fast pads, and Table 20 for all pins
with medium, slow, and multi-voltage pads.
Table 19. Power sequence pin states (fast pads)
VDDE
VRC33
VDD
Pad State
LOW
VDDE
VDDE
VDDE
X
X
X
LOW
HIGH
LOW
VRC33
VRC33
LOW
VDD
HIGH IMPEDANCE
FUNCTIONAL
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
77
Table 20. Power sequence pin states (medium, slow, and multi-voltage pads)
VDDEH
VDD
Pad State
LOW
VDDEH
VDDEH
X
LOW
LOW
VDD
HIGH IMPEDANCE
FUNCTIONAL
3.8
DC electrical specifications
Table 21. DC electrical specifications
Value
typ
Symbol
C
Parameter
Conditions
Unit
min
max
VDD
SR
SR
SR
SR
SR
—
—
—
—
—
Core supply voltage
I/O supply voltage
I/O supply voltage
I/O supply voltage
—
—
—
—
—
1.14
1.62
3.0
1.32
3.6
V
V
V
V
V
VDDE
VDDEH
VDDE-EH
VRC33
5.25
5.25
3.6
3.0
3.3 V regulated
voltage1
3.0
—
VDDA
VINDC
SR
SR
SR
—
—
—
Analog supply voltage
Analog input voltage
—
—
—
4.752
VSSA-0.3
–100
—
—
—
5.25
VDDA+0.3
100
V
V
VSS – VSSA
VSS differential
voltage
mV
VRL
SR
SR
SR
SR
SR
—
—
—
—
—
Analog reference low
voltage
—
—
—
—
—
—
VSSA
–100
—
—
—
—
—
VSSA+0.1
100
V
mV
V
V
RL – VSSA
VRL differential
voltage
VRH
Analog reference high
voltage
VDDA-0.1
4.75
VDDA
5.25
V
RH – VRL
VREF differential
voltage
V
VDDF
Flash operating
voltage3
1.14
1.32
V
4
VFLASH
SR
SR
—
—
Flash read voltage
3.0
—
—
3.6
1.2
V
V
VSTBY
SRAM standby
voltage
Unregulated
mode
0.95
Regulated
mode
2.0
—
5.5
Keep-out Range:
1.2V–2V
MPC5644A Microcontroller Data Sheet, Rev. 7
78
Freescale Semiconductor
Table 21. DC electrical specifications (continued)
Value
Symbol
C
Parameter
Conditions
Unit
min
typ
max
VDDREG
SR
SR
SR
CC
—
—
—
C
P
Voltage regulator
supply voltage
—
—
—
4.75
—
5.25
V
V
VDDPLL
Clock synthesizer
operating voltage
1.14
–100
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.32
VSSPLL
VSS
–
VSSPLL to VSS
differential voltage
100
mV
V
VIL_S
Slow/medium I/O pad
input low voltage
Hysteresis
enabled
VSS-0.3
0.35*VDDEH
0.40*VDDEH
0.35*VDDE
0.40*VDDE
0.8
Hysteresis
disabled
VSS-0.3
VIL_F
CC
CC
CC
CC
CC
CC
CC
C
P
Fast pad I/O input low
voltage
Hysteresis
enabled
VSS-0.3
V
V
V
V
V
V
V
Hysteresis
disabled
V
V
V
SS-0.3
SS-0.3
SS-0.3
VIL_LS
VIL_HS
VIH_S
VIH_F
C
P
Multi-voltage I/O pad
input low voltage in
Hysteresis
enabled
Low-swing-mode5,6,7,
8
Hysteresis
disabled
1.1
C
P
Multi-voltage pad I/O
input low voltage in
high-swing-mode
Hysteresis
enabled
VSS-0.3
0.35 VDDEH
0.4 VDDEH
VDDEH+0.3
VDDEH+0.3
VDDE+0.3
VDDE+0.3
VDDEH+0.3
Hysteresis
disabled
VSS-0.3
C
P
Slow/medium pad I/O
input high voltage9
Hysteresis
enabled
0.65 VDDEH
0.55 VDDEH
0.65 VDDE
0.58 VDDE
2.5
Hysteresis
disabled
C
P
Fast I/O input high
voltage
Hysteresis
enabled
Hysteresis
disabled
VIH_LS
C
P
Multi-voltage pad I/O
input high voltage in
low-swing-mode5,6,7,8
Hysteresis
enabled
Hysteresis
disabled
2.2
VDDEH+0.3
VIH_HS
C
P
Multi-voltage I/O input
high voltage in
high-swing-mode
Hysteresis
enabled
0.65 VDDEH
0.55 VDDEH
VDDEH+0.3
VDDEH+0.3
Hysteresis
disabled
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
79
Table 21. DC electrical specifications (continued)
Value
Symbol
C
Parameter
Conditions
Unit
min
typ
max
VOL_S
CC
CC
CC
P
P
P
Slow/medium pad I/O
output low voltage9
—
—
0.2*VDDEH
V
V
V
VOL_F
Fast I/O output low
voltage9
—
—
—
—
0.2*VDDE
0.6
VOL_LS
Multi-voltage pad I/O
output low voltage in
low-swing
mode5,6,7,8,9
VOL_HS
CC
P
Multi-voltage pad I/O
output low voltage in
high-swing mode9
—
—
0.2*VDDEH
V
VOH_S
VOH_F
VOH_LS
CC
CC
CC
P
P
P
Slow/medium pad I/O
output high voltage9
0.8 VDDEH
0.8 VDDE
2.1
—
—
—
—
V
V
V
Fast pad I/O output
high voltage9
Multi-voltage pad I/O
output high voltage in
low-swing mode5,6,7,8
IOH_LS
0.5 mA
=
3.1
3.7
VOH_HS
CC
CC
P
C
Multi-voltage pad I/O
output high voltage in
high-swing mode9
0.8 VDDEH
—
—
—
—
V
V
VHYS_S
Slow/medium/multi-vo
ltage I/O input
hysteresis
—
0.1 * VDDEH
VHYS_F
CC
CC
C
C
Fast I/O input
hysteresis
—
0.1 * VDDE
0.25
—
—
—
—
V
v
VHYS_LS
Low-Swing-Mode
hysteresis
Multi-VoltageI/OInput enabled
Hysteresis
IDD+IDDPLL
CC
P
P
P
Operating current
1.2 V supplies
VDD at
1.32 Vat 80
MHz
—
—
—
380
400
400
mA
mA
mA
VDD at
1.32V
at 120 MHz
VDD at
1.32V
at 150 MHz
MPC5644A Microcontroller Data Sheet, Rev. 7
80
Freescale Semiconductor
Table 21. DC electrical specifications (continued)
Value
Symbol
C
Parameter
Conditions
Unit
min
typ
max
IDDSTBY
CC
CC
T
T
P
Operating current
0.95-1.2 V
VSTBY at
55 oC
—
35
100
A
A
A
Operating current
2–5.5 V
V
STBY at
—
45
25
110
90
55 oC
IDDSTBY27
Operating current
0.95-1.2 V
VSTBY 27 oC
P
Operating current
2-5.5 V
VSTBY 27 oC
35
100
A
IDDSTBY150
CC
P
P
P
Operating current
0.95-1.2 V
VSTBY
—
—
—
790
760
2000
2000
15
A
A
150 oC
Operating current
2–5.5 V
V
STBY at
150 oC
IDDPLL
CC
CC
Operating current
1.2 V supplies
VDDPLL
80 MHz,
VDD=1.2 V
,
mA
IDDSLOW
IDDSTOP
P
VDD low-power mode
operating current at
1.32 V
Slow
—
90
mA
mode10
P
C
Stop mode11
—
—
75
60
1 12
IDD33
CC
CC
Operating current
3.3 V supplies
VRC33
,
mA
mA
IDDA
IREF
IDDREG
P
P
Operating current
5.0 V supplies
VDDA
—
—
—
—
30.0
1.0
Analog
reference
supply
current
(transient)
C
D
D
D
D
D
D
D
VDDREG
VDDEH1
VDDEH4
VDDEH6
VDDEH7
VDDE7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
7013
IDDH1
IDDH4
IDDH6
IDDH7
IDD7
CC
Operating current
VDDE14 supplies
See note 14
mA
IDDH9
IDD12
VDDEH9
VDDE12
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
81
Table 21. DC electrical specifications (continued)
Value
Symbol
C
Parameter
Conditions
Unit
min
typ
max
IACT_S
CC
CC
C
P
D
D
D
C
Slow/medium I/O
weak pull up/down
current15
3.0 V –
3.6 V
15
—
95
A
4.75 V –
5.5 V
35
36
34
42
10
—
—
—
—
—
200
120
139
158
75
IACT_F
Fast I/O weak pull
up/down current15
1.62 V –
1.98 V
A
A
2.25 V –
2.75 V
3.0 V –
3.6 V
IACT_MV_PU
CC
Multi-voltage pad
weak pullup current
VDDE=
3.0–3.6 V5,
MultiV pad,
high swing
mode only
P
C
4.75 V –
5.25 V
25
10
—
—
200
60
IACT_MV_PD
CC
Multivoltage pad weak
pulldown current
VDDE
=
A
3.0–3.6 V5,
MultiV pad,
high swing
mode only
P
P
T
P
P
4.75 V –
5.25 V
25
—
—
—
—
—
200
2.5
IINACT_D
CC
SR
SR
I/O input leakage
current16
—
—
—
—
–2.5
–1.0
–250
–150
A
mA
nA
IIC
DC injection current
(per pin)
1.0
IINACT_A
Analog input current,
channel off, AN[0:7]17
250
150
Analog input current,
channel off, all other
analog pins17
MPC5644A Microcontroller Data Sheet, Rev. 7
82
Freescale Semiconductor
Table 21. DC electrical specifications (continued)
Value
typ
Symbol
C
Parameter
Conditions
Unit
min
max
CL
CC
D
D
D
D
D
D
D
Load capacitance
(fast I/O)18
DSC(PCR[8
:9]) = 0b00
—
10
pF
DSC(PCR[8
:9]) = 0b01
—
—
—
—
—
—
20
30
50
7
DSC(PCR[8
:9]) = 0b10
DSC(PCR[8
:9]) = 0b11
CIN
CC
CC
CC
Input capacitance
(digital pins)
—
—
—
pF
pF
pF
CIN_A
Input capacitance
(analog pins)
10
12
CIN_M
Input capacitance
(digital and analog
pins19
)
RPUPD200K
RPUPD100K
RPUPD5K
SR
SR
SR
CC
P
P
C
C
Weak Pull-Up/Down
Resistance20, 200 k
Option
—
—
130
65
—
—
—
—
280
140
7.5
2.5
k
k
k
%
Weak Pull-Up/Down
Resistance20, 100 k
Option
Weak Pull-Up/Down
5 V ± 5%
supply
1.4
Resistance20
,
5 k Option
RPUPDMTCH
Pull-up/Down
Resistance matching
ratios (100K/200K)
Pull-up and
pull-down
resistances
both
–2.5
enabled and
settings are
equal.
TA (TL to
TH)
SR
SR
—
—
Operating
temperature range -
ambient (packaged)
—
–40.0
—
125.0
25
C
—
Slew rate on power
supply pins
—
V/ms
1
2
These specifications apply when VRC33 is supplied externally, after disabling the internal regulator (VDDREG = 0).
ADC is functional with 4 V VDDA 4.75 V but with derated accuracy. This means the ADC will continue to function
at full speed with no undesirable behavior, but the accuracy will be degraded.
3
The VDDF supply is connected to VDD in the package substrate. This specification applies to calibration package
devices only.
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
83
4
5
6
7
8
9
VFLASH is only available in the calibration package.
Power supply for multi-voltage pads cannot be below 4.5 V when in low-swing mode.
The slew rate (SRC) setting must be 0b11 when in low-swing mode.
While in low-swing mode there are no restrictions in transitioning to high-swing mode.
Pin in low-swing mode can accept a 5 V input.
All VOL/VOH values 100% tested with ± 2 mA load except where noted.
10 Bypass mode, system clock at 1 MHz (using system clock divider), PLL shut down, CPU running simple executive
code, 4 x ADC conversion every 10 ms, 2 x PWM channels 1 kHz, all other modules stopped.
11 Bypass mode, system clock at 1 MHz (using system clock divider), CPU stopped, PIT running, all other modules
stopped.
12 This current will be consumed for external regulation and internal regulation, when 3.3V regulator is switched off by
shadow flash
13 If 1.2V and 3.3V internal regulators are on,then iddreg=70mA
If supply is external that is 3.3V internal regulator is off, then iddreg=15mA
14 Power requirements for each I/O segment are dependent on the frequency of operation and load of the I/O pins on a
particular I/O segment, and the voltage of the I/O segment. See Table 22 for values to calculate power dissipation for
specific operation. The total power consumption of an I/O segment is the sum of the individual power consumptions
for each pin on the segment.
15 Absolute value of current, measured at VIL and VIH.
16 Weak pull up/down inactive. Measured at VDDE = 3.6 V and VDDEH = 5.25 V. Applies to fast, slow, and medium pads.
17 Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half
for each 8 to 12 oC, in the ambient temperature range of 50 to 125 oC. Applies to analog pads.
18 Applies to CLKOUT, external bus pins, and Nexus pins.
19 Applies to the FCK, SDI, SDO, and SDS pins.
20 This programmable option applies only to eQADC differential input channels and is used for biasing and sensor
diagnostics.
MPC5644A Microcontroller Data Sheet, Rev. 7
84
Freescale Semiconductor
3.9
I/O pad current specifications
The power consumption of an I/O segment depends on the usage of the pins on a particular segment. The power consumption
is the sum of all output pin currents for a particular segment. The output pin current can be calculated from Table 22 based on
the voltage, frequency, and load on the pin. Use linear scaling to calculate pin currents for voltage, frequency, and load
parameters that fall outside the values given in Table 22.
1
Table 22. I/O pad average I
specifications
DDE
IDDE
RMS
(mA)
Pad
Type
Period
(ns)
Load2 VDDE
Drive/Slew
Rate Select
IDDE Avg
(mA)3
Symbol
C
(pF)
(V)
Slow
Medium
Fast
IDRV_SSR_HV
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
37
130
650
840
24
50
50
50
200
50
50
50
200
50
30
20
10
50
30
20
10
50
50
50
200
30
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
3.6
3.6
3.6
3.6
1.98
1.98
1.98
1.98
5.5
5.5
5.5
5.5
5.5
11
01
00
00
11
01
00
00
11
10
01
00
11
10
01
00
11
01
00
00
11
9
—
—
2.5
0.5
1.5
14
—
—
IDRV_MSR_HV
—
62
5.3
1.1
3
—
317
425
10
—
—
IDRV_FC
22.7
12.1
8.3
4.44
12.5
7.3
5.42
2.84
9
68.3
41.1
27.7
14.3
31
10
10
10
10
10
18.6
12.6
6.4
—
10
10
MultiV
(High
Swing
Mode)
IDRV_MULTV_
20
HV
30
6.1
2.3
5.8
3.4
—
117
212
30
—
—
MultiV
(Low
IDRV_MULTV_
—
HV
Swing
Mode)
1
2
3
Numbers from simulations at best case process, 150 °C.
All loads are lumped.
Average current is for pad configured as output only.
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
85
3.9.1
I/O pad VRC33 current specifications
The power consumption of the V
supply is dependent on the usage of the pins on all I/O segments. The power consumption
RC33
is the sum of all input and output pin V
currents for all I/O segments. The output pin V
current can be calculated from
RC33
RC33
Table 23 based on the voltage, frequency, and load on all fast pad pins. The input pin V
current can be calculated from
RC33
Table 23 based on the voltage, frequency, and load on all medium-speed pads. Use linear scaling to calculate pin currents for
voltage, frequency, and load parameters that fall outside the values given in Table 23.
1
Table 23. I/O pad V
average I
specifications
Drive Select
RC33
DDE
Period
Load2
(pF)
IDD33 Avg
(µA)
IDD33 RMS
(µA)
Pad Type
Symbol
C
(ns)
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
D
D
D
D
D
D
D
D
D
D
D
D
D
100
200
800
800
40
50
50
11
01
00
00
11
01
00
00
11
01
00
00
11
0.8
0.04
0.06
0.009
2.75
0.11
0.02
0.01
33.4
33.4
33.4
33.4
33.4
235.7
87.4
47.4
47
Slow
IDRV_SSR_HV
50
200
50
258
100
500
500
20
50
76.5
56.2
56.2
35.4
34.8
33.8
33.7
34.9
Medium
IDRV_MSR_HV
50
200
50
30
50
MultiV3 (High
Swing Mode)
IDRV_MULTV_HV
117
212
30
50
200
30
MultiV4 (Low
Swing Mode)
IDRV_MULTV_HV
1
2
3
4
These are typical values that are estimated from simulation and not tested. Currents apply to output pins only.
All loads are lumped.
Average current is for pad configured as output only.
In low swing mode, multi-voltage pads must operate in highest slew rate setting.
MPC5644A Microcontroller Data Sheet, Rev. 7
86
Freescale Semiconductor
1
Table 24. V
pad average DC current
RC33
Pad
Type
Period
(ns)
Load2
(pF)
VRC33
(V)
VDDE
(V)
Drive
Select
IDD33 Avg IDD33 RMS
Symbol
C
(µA)
(µA)
CC
CC
CC
CC
CC
CC
CC
CC
D
D
D
D
D
D
D
D
10
10
10
10
10
10
10
10
50
30
20
10
50
30
20
10
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
11
10
01
00
11
10
01
00
2.35
1.75
1.41
1.06
1.75
1.32
1.14
0.95
6.12
4.3
3.6
3.43
2.9
3.6
Fast
IDRV_FC
1.98
1.98
1.98
1.98
4.56
3.44
2.95
2.62
1
2
These are typical values that are estimated from simulation and not tested. Currents apply to output pins only.
All loads are lumped.
3.9.2
LVDS pad specifications
LVDS pads are implemented to support the MSC (Microsecond Channel) protocol which is an enhanced feature of the DSPI
module. The LVDS pads are compliant with LVDS specifications and support data rates up to 50 MHz.
Table 25. DSPI LVDS pad specification
Min.
Value
Typ.
Value
Max.
Value
#
Characteristic
Symbol
C
Condition
Unit
Data Rate
4
5
Data Frequency
fLVDSCLK
CC
D
—
50
MHz
mV
Driver Specs
Differential output voltage
VOD
CC
P
SRC=0b00
or 0b11
150
400
CC
CC
CC
P
P
P
SRC=0b01
SRC=0b10
90
320
480
1.39
160
1.06
6
Common mode voltage
(LVDS), VOS
VOD
1.2
V
7
8
Rise/Fall time
TR/TF
TPLH
CC
CC
D
D
—
—
2
4
ns
ns
Propagation delay (Low to
High)
9
Propagation delay (High to
Low)
TPHL
CC
CC
D
D
4
4
ns
ns
10 Delay (H/L), sync Mode
tPDSYNC
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
87
Table 25. DSPI LVDS pad specification (continued)
11 Delay, Z to Normal
(High/Low)
TDZ
CC
D
—
500
100
ns
ns
12 Diff Skew Itphla-tplhbI or
Itplhb-tphlaI
TSKEW
CC
D
—
0.5
Termination
13 Trans. Line (differential Zo)
14 Temperature
CC
CC
D
D
—
95
105
150
–40
C
3.10 Oscillator and PLLMRFM electrical characteristics
Table 26. PLLMRFM electrical specifications
(VDDPLL = 1.08 V to 3.6 V, VSS = VSSPLL = 0 V, TA = TL to TH)
Value
Symbol
C
Parameter
Conditions
Unit
min
max
fref_crystal CC
fref_ext
D
C
P
PLL reference frequency range1
Crystal
reference
4
40
MHz
External
reference
4
4
80
16
fpll_in
CC
Phase detector input frequency range
(after pre-divider)
—
MHz
fvco
fsys
fsys
CC
CC
CC
P
C
T
VCO frequency range
—
—
256
16
4
512
150
40
MHz
MHz
MHz
On-chip PLL frequency2
System frequency in bypass mode2
Crystal
reference
P
External
0
80
reference
tCYC
CC
CC
D
D
D
P
T
System clock period
—
Lower limit
Upper limit
—
—
1.6
24
1 / fsys
3.7
ns
fLORL
fLORH
Loss of reference frequency window3
MHz
56
fSCM
CC
CC
Self-clocked mode frequency 4,5
1.2
–5
72.25
5
MHz
CJITTER
CLKOUT
period
Peak-to-peak (clock fSYS maximum
edge to clock edge)
% fCLKOUT
jitter6,7,8,9
T
T
Long-term jitter
(avg. over 2 ms
interval)
–6
—
6
ns
tcst
CC
Crystal start-up time 10, 11
—
10
ms
MPC5644A Microcontroller Data Sheet, Rev. 7
88
Freescale Semiconductor
Table 26. PLLMRFM electrical specifications
(VDDPLL = 1.08 V to 3.6 V, VSS = VSSPLL = 0 V, TA = TL to TH) (continued)
Value
Symbol
C
Parameter
Conditions
Unit
min
max
VIHEXT
CC
CC
CC
T
T
EXTAL input high voltage
Crystal Mode12
Vxtal
+ 0.4
—
V
External
VRC33
/2 +
0.4
VRC33
Reference12, 13
VILEXT
T
T
EXTAL input low voltage
XTAL load capacitance10
Crystal Mode12
—
Vxtal -
0.4
V
External
0
VRC33
/2 -
0.4
Reference12, 13
—
T
4 MHz
8 MHz
12 MHz
16 MHz
20 MHz
40 MHz
—
5
5
30
26
pF
5
23
5
19
5
16
5
8
tlpll
tdc
fLCK
fUL
fCS
CC
CC
CC
CC
CC
P
T
T
T
D
D
D
PLL lock time 10, 14
—
200
60
s
Duty cycle of reference
Frequency LOCK range
Frequency un-LOCK range
Modulation Depth
—
40
–6
–18
±0.25
–0.5
—
%
—
6
% fsys
% fsys
% fsys
—
18
Center spread
Down Spread
—
±4.0
–8.0
100
fDS
fMOD
CC
Modulation frequency15
kHz
1
2
3
Considering operation with PLL not bypassed.
All internal registers retain data at 0 Hz.
“Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self clocked
mode.
4
5
Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside
the fLOR window.
fVCO self clock range is 20–150 MHz. fSCM represents fSYS after PLL output divider (ERFD) of 2 through 16 in
enhanced mode.
6
7
This value is determined by the crystal manufacturer and board design.
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum
fSYS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock
signal. Noise injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency
increase the CJITTER percentage for a given interval.
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
89
8
9
Proper PC board layout procedures must be followed to achieve specifications.
Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of CJITTER and
either fCS or fDS (depending on whether center spread or down spread modulation is enabled).
10 This value is determined by the crystal manufacturer and board design. For 4 MHz to 40 MHz crystals specified for
this PLL, load capacitors should not exceed these limits.
11 Proper PC board layout procedures must be followed to achieve specifications.
12 This parameter is guaranteed by design rather than 100% tested.
13
V
cannot exceed VRC33 in external reference mode.
IHEXT
14 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits
in the synthesizer control register (SYNCR).
15 Modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50 kHz.
3.11 Temperature sensor electrical characteristics
Table 27. Temperature sensor electrical characteristics
Value
Symbol
C
Parameter
Conditions
Unit
min
typical
max
—
CC C Temperature
monitoring range
–40
—
150
°C
—
—
CC C Sensitivity
CC Accuracy
—
6.3
—
—
mV/°C
°C
P
TJ = –40 to 150 °C
–10
10
3.12 eQADC electrical characteristics
Table 28. eQADC conversion specifications (operating)
Value
Unit
Symbol
C
Parameter
min
max
fADCLK
SR
CC
CC
SR
—
D
ADC clock (ADCLK) frequency
Conversion cycles
2
2+13
—
16
128+14
10
MHz
CC
TSR
ADCLK cycles
C
Stop mode recovery time1
s
fADCLK
—
ADC clock (ADCLK) frequency
2
16
mV
1
Stop mode recovery time is the time from the setting of either of the enable bits in the ADC Control Register to
the time that the ADC is ready to perform conversions.Delay from power up to full accuracy = 8 ms.
MPC5644A Microcontroller Data Sheet, Rev. 7
90
Freescale Semiconductor
Table 29. eQADC single ended conversion specifications (operating)
Value
Symbol
C
Parameter
Unit
min
max
OFFNC
CC
CC
CC
C
C
C
C
T
Offset error without calibration
0
–4
160
4
Counts
Counts
Counts
Counts
mA
OFFWC
GAINNC
Offset error with calibration
Full scale gain error without calibration
Full scale gain error with calibration
Disruptive input injection current 1, 2, 3, 4
Incremental error due to injection current5,6
Total unadjusted error (TUE) at 8 MHz
Total unadjusted error at 16 MHz
–160
–4
0
GAINWC CC
4
IINJ
EINJ
CC
CC
CC
CC
–3
3
T
–4
4
Counts
Counts
Counts
TUE8
TUE16
C
C
–4
46
–8
8
1
Below disruptive current conditions, the channel being stressed has conversion values of 0x3FF for analog
inputs greater then VRH and 0x0 for values less then VRL. Other channels are not affected by non-disruptive
conditions.
2
3
Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions
within the limit do not affect device reliability or cause permanent damage.
Input must be current limited to the value specified. To determine the value of the required current-limiting
resistor, calculate resistance values using VPOSCLAMP = VDDA + 0.5 V and VNEGCLAMP = – 0.3 V, then use
the larger of the calculated values.
4
5
6
Condition applies to two adjacent pins at injection limits.
Performance expected with production silicon.
All channels have same 10 k < Rs < 100 k; Channel under test has Rs=10 k; IINJ=IINJMAX,IINJMIN
Table 30. eQADC differential ended conversion specifications (operating)
Value
Symbol
GAINVGA11
C
Parameter
Unit
min
max
CC
CC
–
Variable gain amplifier accuracy (gain=1)2
C
INL
8 MHz
ADC
–4
–8
4
8
Counts
3
CC
CC
CC
C
C
C
16 MHz
ADC
Counts
Counts
Counts
DNL
8 MHz
ADC
–34
–34
34
34
16 MHz
ADC
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
91
Table 30. eQADC differential ended conversion specifications (operating) (continued)
Value
Symbol
C
Parameter
Unit
min
max
GAINVGA21
CC
CC
–
Variable gain amplifier accuracy (gain=2)2
D
INL
8 MHz
ADC
–5
–8
–3
–3
5
8
3
3
Counts
Counts
Counts
Counts
CC
CC
CC
D
D
D
16 MHz
ADC
DNL
8 MHz
ADC
16 MHz
ADC
GAINVGA41
CC
CC
–
Variable gain amplifier accuracy (gain=4)2
D
INL
8 MHz
ADC
–7
–8
–4
–4
—
7
Counts
Counts
Counts
Counts
V
CC
CC
CC
CC
D
D
D
C
16 MHz
ADC
8
DNL
8 MHz
ADC
4
16 MHz
ADC
4
DIFFmax
DIFFmax2
DIFFmax4
DIFFcmv
Maximum
PREGAIN
differential voltage set to 1X
(VRH - VRL)/2
(DANx+ - DANx-) or
setting
(DANx- - DANx+)5
CC
CC
CC
C
C
C
PREGAIN
set to 2X
setting
—
—
(VRH - VRL)/4
(VRH - VRL)/8
V
V
V
PREGAIN
set to 4X
setting
Differential input
Common mode
voltage (DANx- +
DANx+)/25
—
(VRH + VRL)/2 - 5% (VRH + VRL)/2 + 5%
1
2
Applies only to differential channels.
Variable gain is controlled by setting the PRE_GAIN bits in the ADC_ACR1-8 registers to select a gain factor of 1, 2, or 4.
Settings are for differential input only. Tested at 1 gain. Values for other settings are guaranteed by as indicated.
3
4
5
At VRH – VRL = 5.12 V, one LSB = 1.25 mV.
Guaranteed 10-bit mono tonicity.
Voltages between VRL and VRH will not cause damage to the pins. However, they may not be converted accurately if the
differential voltage is above the maximum differential voltage. In addition, conversion errors may occur if the common mode
voltage of the differential signal violates the Differential Input common mode voltage specification.
MPC5644A Microcontroller Data Sheet, Rev. 7
92
Freescale Semiconductor
3.13 Configuring SRAM wait states
Use the SWSC field in the ECSM_MUDCR register to specify an additional wait state for the device SRAM. By default, no
wait state is added.
Table 31. Cutoff frequency for additional SRAM wait state
1
SWSC Value
98
0
1
153
1
Max frequencies including 2% PLL FM.
Please see the device reference manual for details.
3.14 Platform flash controller electrical characteristics
1,2
Table 32. APC, RWSC, WWSC settings vs. frequency of operation
Max. Flash Operating
APC4
RWSC4
WWSC
Frequency (MHz)3
20 MHz
61 MHz
90 MHz
123 MHz
153 MHz
0b000
0b001
0b010
0b011
0b100
0b000
0b001
0b010
0b011
0b100
0b11
0b11
0b11
0b11
0b11
1
APC, RWSC and WWSC are fields in the flash memory BIUCR register used to
specify wait states for address pipelining and read/write accesses. Illegal
combinations exist—all entries must be taken from the same row.
2
3
4
TBD: To Be Defined.
Max frequencies including 2% PLL FM.
APC must be equal to RWSC.
3.15 Flash memory electrical characteristics
1
Table 33. Flash program and erase specifications
Min. Typical Initial
Value Value
#
Symbol
C
Parameter
Max3 Unit
Max2
1
2
3
Tdwprogram CC
Tpprogram CC
T16kpperase CC
P
P
P
Double Word (64 bits) Program Time
Page Program Time
—
—
—
38
45
—
500
500
s
s
1604
16 KB Block Pre-program and Erase
Time
270
1000
5000
ms
5
T64kpperase CC
P
64 KB Block Pre-program and Erase
Time
—
800
1800
5000
ms
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
93
1
Table 33. Flash program and erase specifications
Min. Typical Initial
Value Value
#
Symbol
C
Parameter
Max3 Unit
7500 ms
Max2
6
T128kpperase CC
P
128 KB Block Pre-program and Erase
Time
—
1500
3000
—
2600
7
T256kpperase CC
P
256 KB Block Pre-program and Erase
Time
—
5200 15000 ms
8
9
Tpsrt
Tesrt
SR
SR
—
—
Program suspend request rate5
Erase suspend request rate 6
100
10
—
—
s
ms
1
2
3
Typical program and erase times assume nominal supply values and operation at 25 oC. All times are subject to
change pending device characterization.
Initial factory condition: < 100 program/erase cycles, 25 oC, typical supply voltage, 80 MHz minimum system
frequency.
The maximum erase time occurs after the specified number of program/erase cycles. This maximum value is
characterized but not guaranteed.
4
5
6
Page size is 128 bits (4 words).
Time between program suspend resume and the next program suspend request.
Time between erase suspend resume and the next erase suspend request.
Table 34. Flash module life
Value
Symbol
C
Parameter
Conditions
Unit
min
typ
P/E
CC
CC
CC
C
Number of program/erase
cycles per block for 16 KB,
48 KB, and 64 Kbyte
blocks over the operating
temperature range (TJ)
—
—
100,000
—
P/E
cycles
P/E
C
C
Number of program/erase
cycles per block for
128 Kbyte and 256 Kbyte
blocks over the operating
temperature range (TJ)
1,000
100,000
P/E
cycles
Data
Retention
Minimum data retention at
85 C average ambient
temperature1
Blocks with 0 – 1,000
P/E cycles
20
10
5
—
—
—
years
years
years
Blocks with 1,001 –
10,000 P/E cycles
Blocks with 10,001 –
100,000 P/E cycles
1
Ambient temperature averaged over duration of application, not to exceed product operating temperature range.
MPC5644A Microcontroller Data Sheet, Rev. 7
94
Freescale Semiconductor
3.16 AC specifications
3.16.1 Pad AC specifications
1
Table 35. Pad AC specifications (5.0 V)
Output Delay (ns)2,3
Low-to-High /
Rise/Fall Edge (ns)3,4
SRC/DSC
MSB,LSB
Drive Load
(pF)
Name
C
High-to-Low
Min
Max
Min
Max
Medium5,6,7
CC
D
4.6/3.7
12/12
2.2/2.2
7/7
50
118
109
01
N/A
CC
CC
CC
D
D
D
12/13
69/71
28/34
152/165
19/18
5.6/6
34/35
4.4/4.3
15/15
74/74
14/14
50
50
50
00
Slow7,10
7.3/5.7
118
109
01
N/A
CC
CC
CC
D
D
D
26/27
137/142
4.1/3.6
61/69
13/13
72/74
34/34
164/164
8/8
50
50
50
320/330
10.3/8.9
00
MultiV11
(High Swing Mode)
3.28/2.98
N/A
118
109
01
CC
CC
CC
D
D
D
8.38/6.11
16/12.9
5.48/4.81
11/11
63/63
50
50
30
61.7/10.4 92.2/24.3 42.0/12.2
2.31/2.34 7.62/6.33 1.26/1.67
00
MultiV
6.5/4.4
118
(Low Swing Mode)
Fast12
pad_i_hv13
pull_hv
N/A
CC
CC
D
D
0.5/0.5
NA
1.9/1.9
6000
0.3/0.3
±1.5/1.5
0.5
50
N/A
N/A
5000/5000
1
These are worst case values that are estimated from simulation and not tested. The values in the table are
simulated at VDD = 1.14 V to 1.32 V, VDDEH = 4.5 V to 5.5 V, TA = TL to TH
2
3
4
5
This parameter is supplied for reference and is not guaranteed by design and not tested.
Delay and rise/fall are measured to 20% or 80% of the respective signal.
This parameter is guaranteed by characterization before qualification rather than 100% tested.
In high swing mode, high/low swing pad Vol and Voh values are the same as those of the slew controlled output
pads
6
7
Medium Slew-Rate Controlled Output buffer. Contains an input buffer and weak pullup/pulldown.
Output delay is shown in Figure 9. Add a maximum of one system clock to the output delay for delay with respect
to system clock.
8
9
Can be used on the tester.
This drive select value is not supported. If selected, it will be approximately equal to 11.
10 Slow Slew-Rate Controlled Output buffer. Contains an input buffer and weak pullup/pulldown.
11 Selectable high/low swing IO pad with selectable slew in high swing mode only.
12 Fast pads are 3.3 V pads.
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
95
13 Stand alone input buffer. Also has weak pull-up/pull-down.
Table 36. Pad AC specifications (V
1
= 3.3 V)
DDE
Output Delay (ns)2,3
Low-to-High /
Rise/Fall Edge (ns)3,4
SRC/DSC
Drive Load
(pF)
Pad Type
C
High-to-Low
Min
Max
Min
Max
MSB,LSB
Medium5,6,7
CC
CC
D
D
5.8/4.4
16/13
18/17
46/49
2.7/2.1
10/10
34/34
50
118
11.2/8.6
200
N/A
109
01
CC
CC
CC
CC
CC
CC
D
D
D
D
D
D
14/16
27/27
37/45
69/82
6.5/6.7
15/13
38/38
53/46
5.5/4.1
21/16
19/19
43/43
50
200
50
83/86
200/210
270/285
27/28
86/86
00
11
113/109
9.2/6.9
30/23
120/120
20/20
200
50
Slow7,10
81/87
63/63
200
N/A
109
01
CC
CC
CC
CC
CC
CC
D
D
D
D
D
D
31/31
58/52
80/90
144/155
415/415
533/540
3.7/3.1
46/49
15.4/15.4
32/26
42/42
82/85
50
200
50
162/168
216/205
80/82
190/190
250/250
10/10
00
106/95
200
30
MultiV7,11
(High Swing Mode)
118
37/37
200
N/A
109
01
CC
CC
CC
CC
D
D
D
D
32
72
15/15
46/46
50
200
50
210
295
100/100
134/134
00
200
MultiV
Not a valid operational mode
(Low Swing Mode)
Fast
CC
CC
CC
CC
CC
CC
D
D
D
D
D
D
2.5/2.5
1.2/1.2
1.2/1.2
10
20
30
50
0.5
50
00
01
2.5/2.5
2.5/2.5
2.5/2.5
3/3
1.2/1.2
10
1.2/1.2
118
N/A
N/A
pad_i_hv12
pull_hv
0.5/0.5
NA
0.4/0.4
±1.5/1.5
5000/5000
6000
1
These are worst case values that are estimated from simulation and not tested. The values in the table are
simulated at VDD = 1.14 V to 1.32 V, VDDE = 3 V to 3.6 V, VDDEH = 3 V to 3.6 V, TA = TL to TH.
MPC5644A Microcontroller Data Sheet, Rev. 7
96
Freescale Semiconductor
2
3
4
5
This parameter is supplied for reference and is not guaranteed by design and not tested.
Delay and rise/fall are measured to 20% or 80% of the respective signal.
This parameter is guaranteed by characterization before qualification rather than 100% tested.
In high swing mode, high/low swing pad Vol and Voh values are the same as those of the slew controlled output
pads
6
7
Medium Slew-Rate Controlled Output buffer. Contains an input buffer and weak pullup/pulldown.
Output delay is shown in Figure 9. Add a maximum of one system clock to the output delay for delay with respect
to system clock.
8
9
Can be used on the tester.
This drive select value is not supported. If selected, it will be approximately equal to 11.
10 Slow Slew-Rate Controlled Output buffer. Contains an input buffer and weak pullup/pulldown.
11 Selectable high/low swing IO pad with selectable slew in high swing mode only.
12 Stand alone input buffer. Also has weak pull-up/pull-down.
VDDE/2
Pad
Data Input
Rising
Edge
Output
Delay
Falling
Edge
Output
Delay
V
OH
Pad
Output
V
OL
Figure 9. Pad output delay
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
97
3.17 AC timing
3.17.1 Reset and configuration pin timing
1
Table 37. Reset and Configuration Pin Timing
#
Characteristic
Symbol
Min
Max
Unit
1
2
3
4
RESET Pulse Width2
tRPW
tGPW
tRCSU
tRCH
10
2
—
—
—
—
tcyc
tcyc
tcyc
tcyc
RESET Glitch Detect Pulse Width
PLLREF, BOOTCFG, WKPCFG Setup Time to RSTOUT Valid
PLLREF, BOOTCFG, WKPCFG Hold Time to RSTOUT Valid
10
0
1
2
Reset timing specified at: VDDEH = 3.0 V to 5.25 V, VDD = 1.14 V to 1.32 V, TA = TL to TH.
RESET pulse width is measured from 50% of the falling edge to 50% of the rising edge.
2
RESET
1
RSTOUT
3
BOOTCFG
WKPCFG
4
Figure 10. Reset and Configuration Pin Timing
MPC5644A Microcontroller Data Sheet, Rev. 7
98
Freescale Semiconductor
3.17.2 IEEE 1149.1 interface timing
1
Table 38. JTAG pin AC electrical characteristics
Min.
Value
Max.
Value
#
Symbol
tJCYC
C
Characteristic
TCK Cycle Time
Unit
1
2
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
D
D
D
D
D
D
D
D
D
D
D
D
100
40
—
5
—
60
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tJDC
TCK Clock Pulse Width
3
tTCKRISE
TCK Rise and Fall Times (40% - 70%)
TMS, TDI Data Setup Time
TMS, TDI Data Hold Time
4
tTMSS, TDIS
TMSH, tTDIH
tTDOV
tTDOI
t
—
—
222
—
22
—
—
50
50
5
t
25
—
0
6
TCK Low to TDO Data Valid
TCK Low to TDO Data Invalid
TCK Low to TDO High Impedance
JCOMP Assertion Time
7
8
tTDOHZ
tJCMPPW
tJCMPS
tBSDV
—
100
40
—
—
9
10
11
12
JCOMP Setup Time to TCK Low
TCK Falling Edge to Output Valid
tBSDVZ
TCK Falling Edge to Output Valid out
of High Impedance
13
14
15
tBSDHZ
tBSDST
tBSDHT
CC
CC
CC
D
D
D
TCK Falling Edge to Output High
Impedance
—
50
—
—
ns
ns
ns
Boundary Scan Input Valid to TCK
Rising Edge
253
253
TCK Rising Edge to Boundary Scan
Input Invalid
1
JTAG timing specified at VDD = 1.14 V to 1.32 V, VDDEH = 4.5 V to 5.5 V with multi-voltage pads programmed to
Low-Swing mode, TA = TL to TH, and CL = 30 pF with DSC = 0b10, SRC = 0b11. These specifications apply to JTAG
boundary scan only. See Table 39 for functional specifications.
2
3
Pad delay is 8–10 ns. Remainder includes TCK pad delay, clock tree delay logic delay and TDO output pad delay.
For 20 MHz TCK.
NOTE
The Nexus/JTAG Read/Write Access Control/Status Register (RWCS) write (to begin a
read access) or the write to the Read/Write Access Data Register (RWD) (to begin a write
access) does not actually begin its action until 1 JTAG clock (TCK) after leaving the JTAG
Update-DR state. This prevents the access from being performed and therefore will not
signal its completion via the READY (RDY) output unless the JTAG controller receives an
additional TCK. In addition, EVTI is not latched into the device unless there are clock
transitions on TCK.
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
99
The tool/debugger must provide at least one TCK clock for the EVTI signal to be
recognized by the MCU. When using the RDY signal to indicate the end of a Nexus
read/write access, ensure that TCK continues to run for at least 1 TCK after leaving the
Update-DR state. This can be just a TCK with TMS low while in the Run-Test/Idle state or
by continuing with the next Nexus/JTAG command. Expect the affect of EVTI and RDY
to be delayed by edges of TCK. Note: RDY is not available in all packages of all devices.
TCK
2
3
2
1
3
Figure 11. JTAG test clock input timing
MPC5644A Microcontroller Data Sheet, Rev. 7
100
Freescale Semiconductor
TCK
4
5
TMS, TDI
6
8
7
TDO
Figure 12. JTAG test access port timing
TCK
10
JCOMP
9
Figure 13. JTAG JCOMP timing
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
101
TCK
11
13
Output
Signals
12
Output
Signals
14
15
Input
Signals
Figure 14. JTAG boundary scan timing
3.17.3 Nexus timing
1
Table 39. Nexus debug port timing
#
Symbol
tMCYC
tMCYC
tMDC
C
Characteristic
MCKO Cycle Time
Min. Value Max. Value
Unit
1
1a
2
CC
CC
CC
CC
CC
CC
CC
D
D
D
D
D
D
D
D
D
D
D
22,3
254
40
8
—
tCYC
ns
Absolute Minimum MCKO Cycle Time
MCKO Duty Cycle
60
%
3
tMDOV
tMSEOV
tEVTOV
tEVTIPW
MCKO Low to MDO Data Valid5
MCKO Low to MSEO Data Valid5
MCKO Low to EVTO Data Valid5
EVTI Pulse Width
- 0.1
- 0.1
- 0.1
4.0
0.35
0.35
0.35
—
tMCYC
tMCYC
tMCYC
tTCYC
tMCYC
tCYC
ns
4
6
7
8
tEVTOPW CC
EVTO Pulse Width
1
—
9
tTCYC
tTCYC
tTDC
CC
CC
CC
TCK Cycle Time
46,7
1008
40
—
9a
10
Absolute Minimum TCK Cycle Time
TCK Duty Cycle
—
60
%
MPC5644A Microcontroller Data Sheet, Rev. 7
102
Freescale Semiconductor
1
Table 39. Nexus debug port timing (continued)
Characteristic Min. Value Max. Value
TDI Data Setup Time
#
Symbol
tNTDIS
C
Unit
11
12
13
14
15
CC
CC
CC
CC
CC
D
D
D
D
D
5
—
—
ns
ns
ns
ns
ns
tNTDIH
tNTMSS
tNTMSH
—
TDI Data Hold Time
TMS Data Setup Time
TMS Data Hold Time
25
5
—
25
—
—
TDO propagation delay from falling
edge of TCK
19.5
16
—
CC
D
TDO hold time with respect to TCK
falling edge (minimum TDO
propagation delay)
5.25
—
ns
1
All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. Nexus timing
specified at VDD = 1.14 V to 1.32 V, VDDEH = 4.5 V to 5.5 V with multi-voltage pads programmed to Low-Swing
mode, TA = TL to TH, and CL = 30 pF with DSC = 0b10.
2
3
4
Achieving the absolute minimum MCKO cycle time may require setting the MCKO divider to more than its minimum
setting (NPC_PCR[MCKO_DIV] depending on the actual system frequency being used.
This is a functionally allowable feature. However, this may be limited by the maximum frequency specified by the
Absolute minimum MCKO period specification.
This may require setting the MCO divider to more than its minimum setting (NPC_PCR[MCKO_DIV]) depending on
the actual system frequency being used.
5
6
MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.
Achieving the absolute minimum TCK cycle time may require a maximum clock speed (system frequency / 8) that
is less than the maximum functional capability of the design (system frequency / 4) depending on the actual system
frequency being used.
7
8
This is a functionally allowable feature. However, this may be limited by the maximum frequency specified by the
Absolute minimum TCK period specification.
This may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability
of the design (system frequency / 4) depending on the actual system frequency being used.
1
2
MCKO
3
4
6
MDO
MSEO
EVTO
Output Data Valid
Figure 15. Nexus output timing
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
103
TCK
EVTI
EVTO
7
8
7
8
9
Figure 16. Nexus event trigger and test clock timings
TCK
11
13
12
14
TMS, TDI
15
16
TDO
Figure 17. Nexus TDI, TMS, TDO timing
MPC5644A Microcontroller Data Sheet, Rev. 7
104
Freescale Semiconductor
N
Table 40. Nexus debug port operating frequency
Nexus Pin Usage
Max. Operating
Frequency
Package Nexus Width Nexus Routing
CAL_MDO[4:1
1]
MDO[0:3]
MDO[4:11]
176 LQFP Reduced port Route to MDO2 Nexus Data Out
GPIO
GPIO
GPIO
GPIO
GPIO
40 MHz3
40 MHz5,6
40 MHz3
40 MHz5,6
40 MHz3
208 BGA mode1
[0:3]
324 BGA
Full port
Route to MDO2 Nexus Data Out Nexus Data Out
mode4
[0:3]
[4:11]
GPIO
496 CSP Reduced port Route to MDO2 Nexus Data Out
mode1
[0:3]
Full port
mode4
Route to MDO2 Nexus Data Out Nexus Data Out
[0:3]
[4:11]
GPIO
Route to
Cal Nexus Data
Out [0:3]
Cal Nexus Data
Out [4:11]
CAL_MDO7
1
2
3
NPC_PCR[FPM] = 0
NPC_PCR[NEXCFG] = 0
The Nexus AUX port runs up to 40 MHz. Set NPC_PCR[MCKO_DIV] to divide-by-two if the system frequency is
greater than 40 MHz.
4
5
NPC_PCR[FPM] = 1
Set the NPC_PCR[MCKO_DIV] to divide by two if the system frequency is between 40 MHz and 80 MHz inclusive.
Set the NPC_PCR[MCKO_DIV] to divide by four if the system frequency is greater than 80 MHz.
6
7
Pad restrictions limit the Maximum Operation Frequency in these configurations
NPC_PCR[NEXCFG] = 1
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
105
3.17.4 External Bus Interface (EBI) and calibration bus interface timing
Table 41. External Bus Interface maximum operating frequency
Port
Width
Multiplexed
Mode
ADDR[12:15]
Pin Usage
ADDR[16:31]
Pin Usage
DATA[0:15]
Pin Usage
Max. Operating
Frequency
16-bit
Yes
ADDR[12:15]
GPIO
ADDR[16:31]
DATA[0:15]
66 MHz1
16-bit
32-bit
No
ADDR[12:15]
ADDR[12:15]
ADDR[16:31]
DATA[0:15]
DATA[0:15]
33 MHz2,3
33 MHz2,3
Yes
ADDR[16:31]
DATA[16:31]
1
2
3
Set SIU_ECCR[EBDF] to divide by two or divide by four if the system frequency is greater than 66 MHz.
System Frequency must be 132 MHz and SIU_ECCR[EBDF] set to divide by four.
Pad restrictions limit the maximum operating frequency.
Table 42. Calibration bus interface maximum operating frequency
Port
Width
Multiplexed CAL_ADDR[12:15] CAL_ADDR[16:30] CAL_DATA[0:15]
Max. Operating
Frequency
Mode
Pin Usage
Pin Usage
Pin Usage
16-bit
Yes
GPIO
GPIO
CAL_ADDR[12:30]
CAL_DATA[0:15]
66 MHz1
16-bit
32-bit
No
CAL_ADDR[12:15] CAL_ADDR[16:30]
CAL_DATA[0:15]
66 MHz1
66 MHz1
Yes
CAL_WE[2:3]
CAL_ADDR[16:30]
CAL_DATA[16:30]
CAL_ADDR[0:15]
CAL_DATA[0:15]
CAL_DATA[31]
1
Set SIU_ECCR[EBDF] to divide by two or divide by four if the system frequency is greater than 66 MHz
1
Table 43. External bus interface (EBI) and calibration bus operation timing
66 MHz (ext. bus)2
#
Symbol
C
Characteristic
CLKOUT Period
Unit
Notes
Min
Max
1
TC
CC
P
15.2
—
ns Signals are
measured at 50%
VDDE
.
2
3
4
5
tCDC CC
tCRT CC
tCFT CC
tCOH CC
D
D
D
D
CLKOUT duty cycle
CLKOUT rise time
CLKOUT fall time
45%
—
55%
3
TC
ns
ns
ns
3
—
CLKOUT Posedge to Output Signal
Invalid or High Z(Hold Time)
1.3
—
• ADDR[8:31]
• CS[0:3]
• DATA[0:31]
• OE
• RD_WR
• TS
• WE[0:3]/BE[0:3]
MPC5644A Microcontroller Data Sheet, Rev. 7
106
Freescale Semiconductor
1
Table 43. External bus interface (EBI) and calibration bus operation timing (continued)
66 MHz (ext. bus)2
#
Symbol
C
Characteristic
Unit
Notes
Min
Max
6
tCOV CC
D
CLKOUT Posedge to Output Signal Valid
(Output Delay)
—
9
ns
ADDR[8:31]
CS[0:3]
DATA[0:31]
OE
RD_WR
TS
WE[0:3]/BE[0:3]
7
8
9
tCIS CC
tCIH CC
tAPW CC
D
D
Input Signal Valid to CLKOUT Posedge
(Setup Time)
6.0
1.0
—
—
ns
ns
DATA[0:31]
CLKOUT Posedge to Input Signal Invalid
(Hold Time)
DATA[0:31]
ALE Pulse Width4
ALE Negated to Address Invalid4
D
D
6.5
1.55
—
—
ns
ns
10 tAAI CC
1
External Bus and Calibration bus timing specified at fSYS = 150 MHz and 100 MHz, VDD = 1.14 V to 1.32 V,
VDDE = 3 V to 3.6 V (unless stated otherwise), TA = TL to TH, and CL = 30 pF with DSC = 0b10.
2
The external bus is limited to half the speed of the internal bus. The maximum external bus frequency is 66 MHz
for 16-bit muxed mode and 33 MHz for non-muxed mode. For The EBI division factor should be set accordingly
based on the internal frequency being used.
3
4
5
Refer to Fast Pad timing in Table 35 and Table 36 (different values for 1.8 V vs. 3.3 V).
Measured at 50% of ALE.
When CAL_TS pad is used for CAL_ALE function the hold time is 1 ns instead of 1.5 ns.
Voh_f
VDDE/2
Vol_f
CLKOUT
2
3
2
4
1
Figure 18. CLKOUT timing
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
107
VDDE/2
CLKOUT
6
5
VDDE/2
5
OUTPUT
BUS
VDDE/2
6
5
5
OUTPUT
SIGNAL
VDDE/2
6
OUTPUT
SIGNAL
VDDE/2
Figure 19. Synchronous output timing
MPC5644A Microcontroller Data Sheet, Rev. 7
108
Freescale Semiconductor
CLKOUT
VDDE/2
7
8
INPUT
BUS
VDDE/2
7
8
INPUT
SIGNAL
VDDE/2
Figure 20. Synchronous input timing
System Clock
CLKOUT
ALE
TS
A/D
DATA
ADDR
9
10
Figure 21. ALE signal timing
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
109
3.17.5 External interrupt timing (IRQ pin)
1
Table 44. External interrupt timing
#
Characteristic
IRQ Pulse Width Low
Symbol
Min
Max
Unit
1
2
3
tIPWL
tIPWH
tICYC
3
3
6
—
—
—
tcyc
tcyc
tcyc
IRQ Pulse Width High
IRQ Edge to Edge Time2
1
2
IRQ timing specified at VDD = 1.14 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL
to TH.
Applies when IRQ pins are configured for rising edge or falling edge events, but not both.
IRQ
2
1
3
Figure 22. External Interrupt Timing
3.17.6 eTPU timing
1
Table 45. eTPU timing
#
Characteristic
eTPU Input Channel Pulse Width
eTPU Output Channel Pulse Width
Symbol
Min
Max
Unit
1
2
tICPW
4
22
—
—
tcyc
tcyc
tOCPW
1
2
eTPU timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V,
TA = TL to TH, and CL = 200 pF with SRC = 0b00.
This specification does not include the rise and fall times. When calculating the minimum eTPU pulse width, include
the rise and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).
MPC5644A Microcontroller Data Sheet, Rev. 7
110
Freescale Semiconductor
3.17.7 eMIOS timing
1
Table 46. eMIOS timing
Characteristic
Min.
Value
Max.
Value
#
Symbol
C
Unit
1
2
tMIPW
CC
CC
D
D
eMIOS Input Pulse Width
eMIOS Output Pulse Width
4
1
—
—
tCYC
tCYC
tMOPW
1
eMIOS timing specified at fSYS = 80 MHz, VDD = 1.14 V to 1.32 V, VDDEH = 4.5 V to 5.5 V, TA = TL to TH, and CL =
50 pF with SRC = 0b00.
3.17.8 DSPI timing
DSPI channel frequency support for the MPC5644A MCU is shown in Table 47. Timing specifications are in Table 48.
Table 47. DSPI channel frequency support
Max. Usable
Frequency
(MHz)
SystemClock
(MHz)
DSPI Use
Mode
Notes
150
120
LVDS
Non-LVDS
LVDS
37.5
18.75
40
Use sysclock /4 divide ratio.
Use sysclock /8 divide ratio.
Use sysclock /3 divide ratio. Gives 33/66 duty cycle. Use DSPI
configuration DBR=0b1 (double baud rate), BR=0b0000 (scaler
value 2) and PBR=0b01 (prescaler value 3).
Non-LVDS
LVDS
20
40
20
Use sysclock /6 divide ratio.
Use sysclock /2 divide ratio.
Use sysclock /4 divide ratio.
80
Non-LVDS
1,2
Table 48. DSPI timing
Characteristic
#
Symbol
C
Condition
Min.
Max.
Unit
1
2
3
4
5
tSCK
tCSC
tASC
tSDC
tA
CC
CC
CC
CC
CC
D
D
D
D
D
SCK Cycle Time3,4,5
PCS to SCK Delay6
After SCK Delay8
SCK Duty Cycle
24.4 ns
227
2.9 ms
—
—
ns
ns
ns
ns
219
—
(½tSC)–2 (½tSC)+2
Slave Access Time
—
25
(SS active to SOUT driven)
6
tDIS
CC
D
Slave SOUT Disable Time
(SS inactive to SOUT High-Z or
invalid)
—
25
ns
7
8
tPCSC CC
tPASC CC
D
D
PCSx to PCSS time
PCSS to PCSx time
410
511
—
—
ns
ns
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
111
1,2
Table 48. DSPI timing (continued)
#
Symbol
tSUI CC
C
Characteristic
Condition
Min.
Max.
Unit
9
Data Setup Time for Inputs
VDDEH=4.5–5.5 V
D
D
D
D
D
D
Master (MTFE = 0)
20
23.5
2
—
—
—
—
—
—
ns
VDDEH=3–3.6 V
Slave
Master (MTFE = 1, CPHA = 0)12
Master (MTFE = 1, CPHA = 1)
8
VDDEH=4.5–5.5 V
VDDEH=3–3.6 V
20
23.5
10
tHI
CC
Data Hold Time for Inputs
D
D
D
D
Master (MTFE = 0)
Slave
-4
7
—
—
—
—
ns
Master (MTFE = 1, CPHA = 0)12
Master (MTFE = 1, CPHA = 1)
21
-4
11
tSUO
CC
Data Valid (after SCK edge)
D
D
D
D
D
D
D
Master (MTFE = 0)
Slave
VDDEH=4.5–5.5 V
VDDEH=3–3.6 V
VDDEH=4.5–5.5 V
VDDEH=3–3.6 V
—
—
—
—
—
—
—
5
ns
6.3
25
27
21
5
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
VDDEH=4.5–5.5 V
VDDEH=3–3.6 V
6.3
12
tHO
CC
Data Hold Time for Outputs
VDDEH=4.5–5.5 V
D
D
D
D
D
D
Master (MTFE = 0)
Slave
–5
–7.5
5.5
3
—
—
—
—
—
—
ns
VDDEH=3 –3.6 V
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
VDDEH=4.5–5.5 V
VDDEH=3–3.6 V
–5
–7.5
1
All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on medium-speed pads. DSPI signals using
slow pads have an additional delay based on the slew rate. DSPI timing is specified at VDDEH = 3 to 3.6 V and
VDDEH = 4.5 to 5.5 V, TA = TL to TH, and CL = 50 pF with SRC = 0b11.
2
3
Data is verified at fSYS = 102 MHz and 153 MHz (100 MHz and 150 MHz + 2% frequency modulation).
The minimum DSPI Cycle Time restricts the baud rate selection for given system clock rate. These numbers are
calculated based on two MPC5644A devices communicating over a DSPI link.
MPC5644A Microcontroller Data Sheet, Rev. 7
112
Freescale Semiconductor
4
5
The actual minimum SCK cycle time is limited by pad performance.
For DSPI channels using LVDS output operation, up to 40 MHz SCK cycle time is supported. For non-LVDS output,
maximum SCK frequency is 20 MHz. Appropriate clock division must be applied.
6
7
8
9
The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK].
Timing met when pcssck = 3(01), and cssck =2 (0000).
The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC].
Timing met when ASC = 2 (0000), and PASC = 3 (01).
10 Timing met when pcssck = 3.
11 Timing met when ASC = 3.
12 This number is calculated assuming the SMPL_PT bitfield in DSPI_MCR is set to 0b10.
2
3
PCSx
1
4
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
10
9
Last Data
SIN
First Data
First Data
Data
Data
12
11
Last Data
SOUT
Note: Refer to Table 48 for the numbers.
Figure 23. DSPI classic SPI timing — master, CPHA = 0
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
113
PCSx
SCK Output
(CPOL=0)
10
SCK Output
(CPOL=1)
9
Data
Data
First Data
Last Data
SIN
12
11
SOUT
Last Data
First Data
Note: Refer to Table 48 for the numbers.
Figure 24. DSPI classic SPI timing — master, CPHA = 1
3
2
SS
1
4
SCK Input
(CPOL=0)
4
SCK Input
(CPOL=1)
5
11
12
Data
6
First Data
Last Data
SOUT
SIN
9
10
Data
Last Data
First Data
Note: Refer to Table 48 for the numbers.
Figure 25. DSPI classic SPI timing — slave, CPHA = 0
MPC5644A Microcontroller Data Sheet, Rev. 7
114
Freescale Semiconductor
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
6
12
Last Data
Data
Data
SOUT
SIN
First Data
10
9
Last Data
First Data
Note: Refer to Table 48 for the numbers.
Figure 26. DSPI classic SPI timing — slave, CPHA = 1
3
PCSx
4
1
2
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
9
10
SIN
First Data
12
Last Data
Last Data
Data
11
SOUT
First Data
Data
Note: Refer to Table 48 for the numbers.
Figure 27. DSPI modified transfer format timing — master, CPHA = 0
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
115
PCSx
SCK Output
(CPOL=0)
SCK Output
(CPOL=1)
10
9
SIN
Last Data
First Data
Data
12
Data
11
First Data
Last Data
SOUT
Note: Refer to Table 48 for the numbers.
Figure 28. DSPI modified transfer format timing — master, CPHA = 1
3
2
SS
1
SCK Input
(CPOL=0)
4
4
SCK Input
(CPOL=1)
12
11
6
5
First Data
9
Data
Data
Last Data
10
SOUT
SIN
Last Data
First Data
Note: Refer to Table 48 for the numbers.
Figure 29. DSPI modified transfer format timing — slave, CPHA =0
MPC5644A Microcontroller Data Sheet, Rev. 7
116
Freescale Semiconductor
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
6
12
Last Data
First Data
10
Data
Data
SOUT
SIN
9
First Data
Last Data
Note: Refer to Table 48 for the numbers.
Figure 30. DSPI modified transfer format timing — slave, CPHA =1
8
7
PCSS
PCSx
Note: Refer to Table 48 for the numbers.
Figure 31. DSPI PCS strobe (PCSS) timing
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
117
3.17.9 eQADC SSI timing
1
Table 49. eQADC SSI timing characteristics (pads at 3.3 V or at 5.0 V)
CLOAD = 25 pF on all outputs. Pad drive strength set to maximum.
#
Symbol
C
Rating
Min
Typ
Max
Unit
1
1
2
3
4
5
6
fFCK CC
tFCK CC
tFCKHT CC
tFCKLT CC
tSDS_LL CC
tSDO_LL CC
tDVFE CC
D
D
D
D
D
D
D
FCK Frequency 2, 3
1/17
12
fSYS_CLK
tSYS_CLK
ns
FCK Period (tFCK = 1/ fFCK
Clock (FCK) High Time
Clock (FCK) Low Time
SDS Lead/Lag Time
SDO Lead/Lag Time
)
2
17
9* tSYS_CLK 6.5
8* tSYS_CLK 6.5
7.5
tSYS_CLK 6.5
tSYS_CLK 6.5
ns
-7.5
-7.5
1
ns
7.5
ns
Data Valid from FCK Falling Edge
(tFCKLT+tSDO_LL
ns
)
7
8
tEQ SU CC
D
D
eQADC Data Setup Time (Inputs)
eQADC Data Hold Time (Inputs)
22
1
ns
ns
_
tEQ_HO CC
1
SS timing specified at fSYS = 80 MHz, VDD = 1.14 V to 1.32 V, VDDEH = 4.5 V to 5.5 V, TA = TL to TH, and CL = 50 pF with
SRC = 0b00.
2
3
Maximum operating frequency is highly dependent on track delays, master pad delays, and slave pad delays.
FCK duty is not 50% when it is generated through the division of the system clock by an odd number.
1
2
3
FCK
SDS
4
5
4
5
25th
6
1st (MSB)
2nd
26th
SDO
External Device Data Sample at
FCK Falling Edge
8
7
1st (MSB)
2nd
25th
26th
SDI
eQADC Data Sample at
FCK Rising Edge
Figure 32. eQADC SSI timing
MPC5644A Microcontroller Data Sheet, Rev. 7
118
Freescale Semiconductor
3.17.10 FlexCAN system clock source
Table 50. FlexCAN engine system clock divider threshold
#
Symbol
Characteristic
Value
Unit
1
FCAN_TH
FlexCAN engine system clock threshold
100
MHz
Table 51. FlexCAN engine system clock divider
System Frequency
Required SIU_SYSDIV[CAN_SRC] Value
<= FCAN_TH
> FCAN_TH
01,2
12,3
1
Divides system clock source for FlexCAN engine by 1.
2
3
System clock is only selected for FlexCAN when CAN_CR[CLK_SRC] = 1.
Divides system clock source for FlexCAN engine by 2.
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
119
4
Packages
4.1
4.1.1
Package mechanical data
176 LQFP
MPC5644A Microcontroller Data Sheet, Rev. 7
120
Freescale Semiconductor
Figure 33. 176 LQFP package mechanical drawing (part 1)
Figure 34. 176 LQFP package mechanical drawing (part 2)
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
121
Figure 35. 176 LQFP package mechanical drawing (part 3)
MPC5644A Microcontroller Data Sheet, Rev. 7
122
Freescale Semiconductor
4.1.2
208 MAPBGA
Figure 36. 208 MAPBGA package mechanical drawing (part 1)
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
123
Figure 37. 208 MAPBGA package mechanical drawing (part 2)
MPC5644A Microcontroller Data Sheet, Rev. 7
124
Freescale Semiconductor
4.1.3
324 TEPBGA
Figure 38. 324 BGA package mechanical drawing (part 1)
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
125
Figure 39. 324 BGA package mechanical drawing (part 2)
MPC5644A Microcontroller Data Sheet, Rev. 7
126
Freescale Semiconductor
5
Ordering information
Table 52 shows the orderable part numbers for the MPC5644A series.
Table 52. Orderable part number summary
Speed
(MHz)
Part number
SPC5643AF0MLU3
Flash/SRAM
Package
3 MB/192 KB
3 MB/192 KB
3 MB/192 KB
3 MB/192 KB
3 MB/192 KB
3 MB/192 KB
3 MB/192 KB
3 MB/192 KB
3 MB/192 KB
4 MB/192 KB
4 MB/192 KB
4 MB/192 KB
4 MB/192 KB
4 MB/192 KB
4 MB/192 KB
4 MB/192 KB
4 MB/192 KB
4 MB/192 KB
176LQFP (Pb free)
208MAPBGA(Pb free)
324PBGA (Pb free)
176LQFP (Pb free)
80
80
SPC5643AF0MMG3
SPC5643AF0MVZ3
SPC5643AF0MLU2
SPC5643AF0MMG2
SPC5643AF0MVZ2
SPC5643AF0MLU1
SPC5643AF0MMG1
SPC5643AF0MVZ1
SPC5644AF0MLU3
SPC5644AF0MMG3
SPC5644AF0MVZ3
SPC5644AF0MLU2
SPC5644AF0MMG2
SPC5644AF0MVZ2
SPC5644AF0MLU1
SPC5644AF0MMG1
SPC5644AF0MVZ1
80
120
120
120
150
150
150
80
208MAPBGA (Pb free)
324PBGA (Pb free)
176LQFP (Pb free)
208MAPBGA (Pb free)
324PBGA (Pb free)
176 LQFP (Pb free)
208 MAPBGA (Pb free)
324 TEPBGA (Pb free)
176 LQFP (Pb free)
208 MAPBGA (Pb free)
324 TEPBGA (Pb free)
176 LQFP (Pb free)
208 MAPBGA (Pb free)
324 TEPBGA (Pb free)
80
80
120
120
120
150
150
150
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
127
Figure 40. Product code structure
Example code:
SPC
5644A
F0
M
VZ
1
Qualification Status
Product Family
ATMC Fab and Mask Revision
Temperature Range
Package
Maximum Frequency
Qualification Status
MPC = Industrial qualified
SPC = Automotive qualified
PC = Prototype
Fab and Mask Revision
F = ATMC
0 = Revision
Package Code
LU = 176 LQFP
MG = 208 MAPBGA
VZ = 324 TEPBGA
Temperature spec.
Product
5644A= MPC5644A family
M = –40 °C to 125 °C
Maximum Frequency
1 = 150 MHz
2 = 120 MHz
3 = 80 MHz
6
Document revision history
Table 53 summarizes revisions to this document.
Table 53. Revision history
Substantive changes
Revision
Date
Rev. 1
4/2008
Initial release
MPC5644A Microcontroller Data Sheet, Rev. 7
128
Freescale Semiconductor
Table 53. Revision history (continued)
Revision
Date
Substantive changes
Rev. 2
11/2009
Maximum device speed is 145 MHz (was 150 MHz)
16-entry Memory Protection Unit (MPU). Was incorrectly listed as 8-entry.
Feature details section added
Changes to signal summary table:
• Added ANY function to AN[10]
• Added ANW function to AN[8]
Changes to 208 ball BGA ballmap:
• A12 is AN12-SDS (was AN12)
• A15 is VRC33 (was VDD33)
• B12 is AN13-SDO (was AN13)
• C12 is AN14SDI (was AN14)
• C13 is AN15-FCK (was AN15)
• D1 is VRC33 (was VDD33)
• F13 is VDDEH6AB (was VDDEH6)
• H13 is GPIO99 (was PCSA3)
• J15 is GPIO98 (was PCSA2)
• K4 is now VDDEH1AB (was VDDEH1)
• N6 is now VRC33 (was VDD33)
• N9 is VDDEH4AB (was VDDEH4)
• N12 is now VRC33 (was VDD33)
• P6 is now NC
• T13 is VDDE5 (was NC)
Rev. 2
11/2009
(cont.)
Recommended operating characteristics for power transistor updated
Pad current specifications updated
LVDS pad specifications updated. SRC does not apply to common mode voltage.
Temperature sensor electrical characteristics added
eQADC electrical characteristics updated with VGA gain specs
Pad AC specifications updated
Definition for RDY signal added to signal details
VSTBY maximum is 5.5 V (was listed incorrectly as 6.0 V)
I
MAXA maximum is 5 mA (was TBD)
Analog differential input functions added to AN0–AN7 in signal summary
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
129
Table 53. Revision history (continued)
Substantive changes
Revision
Date
Rev. 3
04/2010
Changes to Signal Properties table (changes apply to Revision 2 and later devices:
EBI changes:
• WE_BE[2] (A2) and CAL_WE_BE[2] (A3) signals added to CS[2] (PCR 2)
• WE_BE[3] (A2) and CAL_WE_BE[3] (A3) signals added to CS[3] (PCR 3)
Calibration bus changes:
• CAL_WE[2]/BE[2] (A2) signal added to CAL_CS[2] (PCR 338)
• CAL_WE[3]/BE[3] (A2) signal added to CAL_CS[3] (PCR 339)
• CAL_ALE (A1) added to CAL_ADDR[15] (PCR 340)
eQADC changes:
• AN[8] and AN[38] pins swapped. AN[8] Is now on pins 9 (176-pin), B3 (208-ball) and
E1 (324-ball). AN[8] was on D3 (324-ball) on previous devices. AN[38] Is now on D3
(324-ball). AN[38] was on pins 9 (176-pin), B3 (208-ball) and E1 (324-ball) on previous
devices.
• ANZ function added to AN11 pin
Reaction channels added to eTPU2:
• RCH0_A (A3) added to ETPU_A[14] (PCR 128)
• RCH0_B (A2) added to ETPU_A[20] (PCR 134)
• RCH0_C (A2) added to ETPU_A[21] (PCR 135)
• RCH1_A (A2) added to ETPU_A[15] (PCR 129)
• RCH1_B (A2) added to ETPU_A[9] (PCR 123)
• RCH1_C (A2) added to ETPU_A[10] (PCR 124)
• RCH2_A (A2) added to ETPU_A[16] (PCR 130)
• RCH3_A (A2) added to ETPU_A[17] (PCR 131
• RCH4_A (A2) added to ETPU_A[18] (PCR 132))
• RCH4_B (A2) added to ETPU_A[11] (PCR 125)
• RCH4_C (A2) added to ETPU_A[12] (PCR 126)
• RCH5_A (A2) added to ETPU_A[19] (PCR 133)
• RCH5_B (A2) added to ETPU_A[28] (PCR 142)
• RCH5_C (A2) added to ETPU_A[29] (PCR 143)
Reaction channels added to eMIOS:
• RCH2_B (A2) added to EMIOS[2] (PCR 181)
• RCH2_C (A2) added to EMIOS[4] (PCR 183)
• RCH3_B (A2) added to EMIOS[10] (PCR 189)
• RCH3_C (A2) added to EMIOS[11] (PCR 190)
Pad changes:
• ETPUA16 (PCR 130) has Medium (was Slow) pad
• ETPUA17 (PCR 131) has Medium (was Slow) pad
• ETPUA18 (PCR 132) has Medium (was Slow) pad
• ETPUA19 (PCR 133) has Medium (was Slow) pad
• ETPUA25 (PCR 139) has Slow+LVDS (was Medium+LVDS) pads
Signal Details table updated:
• Added eTPU2 reaction channels
• Changed IRQ[0:15] to two ranges, excluding IRQ6, which does not exist on this device
• Changed TCR_A to TCRCLKA (TCR_A is the pin name, not the signal name)
• Changed WE_BE[0:1] to WE_BE[0:3] (2 new signals added to Rev. 2). Also changed
notation from “WE_BE[n]” to “WE[n]/BE[n]” to be consistent.
MPC5644A Microcontroller Data Sheet, Rev. 7
130
Freescale Semiconductor
Table 53. Revision history (continued)
Substantive changes
Revision
Date
Rev. 3
(cont)
04/2010
Changes to Power/ground segmentation table:
• ADDR[20:21] removed from VDDE2 segment; they are in VDDE-EH
• CAL_CS1 removed from VDDE12 segment (there is no CAL_CS1 on this device)
• CAL_EVTO and CAL_MCKO removed from VDDE12 segment. Those pins do not
exist
• VDDE-VDDEH renamed to VDDE-EH
• EMIOS24 removed from VDDEH segment. That pin does not exist.
• ETPUA[0:9] added to VDDEH4 segment
• Renamed TCR_A in VDDEH4 segment to TCRCLKA.
• EXTAL and XTAL added to VDDEH6 segment
• AN15-FCK added to VDDEH7 segment
• GPIO98, GPIO99, GPIO206, GPIO207 and GPIO219 added to VDDEH7 segment.
• MSEO1 added to VDDEH7 segment
• Power segment VDDEH1A renamed to VDDEH1
Changes to 176-pin package pinout:
• Changed pin 9 from AN38 to AN8.
• Added note that pin 96 (VSS) should be tied low.
Changes to 208-ball package ballmap:
• Changed ball B3 from AN38 to AN8.
• Added note that ball N13 (VSS) should be tied low.
324-ball package ballmap updated for Rev. 2 silicon:
• AN8 was on ball D3; it is now on E1
• AN38 was on ball E1; it is now on D3
Changes to features list:
• Correction: there are 6 reaction channels (was noted as 5)
• Development Trigger Semaphore (DTS) added to features list and feature details
• FlexRay module now has 128 message buffers (was 64) and ECC support
Added note after JTAG pin AC electrical characteristics table detailing JTAG EVTI and
RDY signal clocking with TCK. This affects debuggers.
Part numbers and part number decoder updated.
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
131
Table 53. Revision history (continued)
Substantive changes
Revision
Date
Rev. 3
(cont)
04/2010
Added information to AC timings section:
• New section added: Reset and configuration pin timing
• New section added: External interrupt timing (IRQ pin)
• New section added: eTPU timing
• Added Nexus debug port operating frequency table to Nexus timings section
• Added external bus interface maximum operating frequency table and calibration bus
interface maximum operation frequency table
• Added FlexCAN system clock source section
Changes to Power management control (PMC) and power on reset (POR) electrical
specifications:
• Max value for parameter 2 (vddreg) is 5.25 V (was 5.5 V)
Updated “Core voltage regulator controller external components preferred configuration”
diagram.
Changes to DC electrical specifications table:
• Slew rate on power supply pins (system requirement) changed to 25 V/ms (was
50 V/ms)
Throughout the document the maximum frequency is now 150 MHz (was 145 MHz)
Changes to DC electrical specifications:
• Parameter classifications added
• VDDREG max value changed to 5.25 V (was 5.5 V)
• VOH_LS min value changed to 2.0 V (was 2.7 V) with a load current of 0.5 mA
• VOL_LS max value changed to 0.6 V (was 0.2*VDDEH) with load current of 2 mA
• VINDC min value changed to VSSA-0.3 (was VSSA-1.0)
• VINDC max value changed to VDDA+0.3 (was VDDA+1.0)
Added new section: Configuring SRAM wait states
VRCCTL external circuit updated.
MPC5644A Microcontroller Data Sheet, Rev. 7
132
Freescale Semiconductor
Table 53. Revision history (continued)
Substantive changes
Revision
Date
Rev. 4
08/2010
Updates to Nexus timings:
• tMDOV max value changed to 0.35 (was 0.2)
• tMSEOV max value changed to 0.35 (was 0.2)
• tEVTOV max value changed to 0.35 (was 0.2)
Updates to DC electrical specifications:
• VSTBY min value changed to 0.95 V (was 0.9 V)
• VSTBY has two ranges—for regulated mode and unregulated mode
Correction to PLLMRFM electrical specifications:
• VDDPLL range is from 1.08 V to 3.6 V (was 3.0 V to 3.6 V.
Updates to pad AC specifications:
• Specs with drive load = 200 pF deleted. DSC (drive strength control) values range from
10 – 50 pF.
• I/O pad average IDDE specifications updated (fast pad specs only)
• I/O pad VRC33 average IDDE specifications (fast pad specs only)
Updates to Reset and configuration pin timings:
• Footnote added: RESET pulse width is measured from 50% of the falling edge to 50%
of the rising edge.
• Timings are specified at VDD = 1.14 V to 1.32 V (was 1.08 V to 1.32 V).
Updates to EBI timings:
• Note added to tAAI: When CAL_TS is used as CAL_ALE the hold time is 1 ns instead
of 1.5 ns.
• Correction: maximum calibration bus interface operating frequency is 66 MHz for all
port configurations.
• VDDE range in footnote 1 corrected to read, “External Bus and Calibration bus timing
specified at fSYS = 150 MHz and 100 MHz, VDD = 1.14 V to 1.32 V, VDDE = 3 V to 3.6
V (unless stated otherwise)” (VDDE range was 1.62 V to 3.6 V)
Correction to IEEE 1149.1 timings:
• SRC value in footnote 1 corrected to read, “JTAG timing specified at VDD = 1.14 V to
1.32 V, VDDEH = 4.5 V to 5.5 V with multi-voltage pads programmed to Low-Swing
mode, TA = TL to TH, and CL = 30 pF with DSC = 0b10, SRC = 0b11.” (SRC value was
0b00)
Correction to External interrupt timing (IRQ pin) timings:
• Timings are specified at VDD = 1.14 V to 1.32 V (was 1.08 V to 1.32 V).
Update to DSPI timings:
• Some of the timing parameters can vary depending on the value of VDDE. For these
parameters, ranges are now defined for two ranges of VDDE
.
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
133
Table 53. Revision history (continued)
Revision
Date
Substantive changes
Rev. 4
(cont)
08/2010
Change in signal name notation for DSPI, CAN and SCI signals:
DSPI:
PCS_x[n] is now DSPI_x_PCS[n]
SOUT_x is now DSPI_x_SOUT
SIN_x is now DSPI_x_SIN
SCK_x is now DSPI_x_SCK
CAN:
CNTXx is now CAN_x_TX
CNRXx is now CAN_x_RX
SCI:
RXDx is now SCI_x_RX
TXDx is now SCI_x_TX
Updates to DC electrical specifications:
• Slew rate on power supply pins specification changed to 25 V/ms (was 50 V/ms)
VOH_LS min spec changed to 2.0 V at 0.5 mA (was 2.7 V at 0.5 mA)
Updated I/O pad current specifications
Updated I/O pad VRC33 current specifications
Corrections to Nexus timing:
• Maximum Nexus debug port operating frequency is 40 MHz in all configurations
• To route Nexus to MDO, clear NPC_PCR[NEXCFG] (formerly this was documented as
NPC_PCR[CAL]
• To route Nexus to CAL_MDO, set NPC_PCR[NEXCFG]=1 (formerly this was
documented as NPC_PCR[CAL]
MPC5644A Microcontroller Data Sheet, Rev. 7
134
Freescale Semiconductor
Table 53. Revision history (continued)
Substantive changes
Revision
Date
Rev. 5
2/2011
• Minor editorial updates.
• Re-organized the first few subsections of the “Overview” section.
• Added ECSM to the block diagram.
• Added information on the REACM, SIU, and ECS modules to the “Block summary”
section.
• Added DATA[0:15] to VDDE5 in the “signal properties” table.
• Updated VSTBY parameters in the “Power/ground segmentation” table.
• Updated the parameter symbols and classifications throughout the document.
• Updated footnote instances in the “Absolute maximum ratings” table.
• Removed IMAXA footnote in the “Absolute Maximum Ratings” table.
• Updated the format of the “EMI (electromagnetic interference) characteristics” table.
• Removed the footnote on VDDREG in the “Power management control (PMC) and
power on reset (POR) electrical specifications” table.
• Updated values for Vbg, Idd3p3, Por3.3V_r, Por3.3V_f, Por5V_r, and Por5V_f in the
“PMC electrical characteristics” table.
• Updated “Bandgap reference supply voltage variation” in the “PMC Electrical
Characteristics” table.
• Updated VCESAT and VBEin the “Recommended power transistors” operating
characteristics” table.
• Updated VIH_LS in the “DC electrical specifications” table.
• Updated the VOH_LS min value in the “DC electrical specifications” table.
• Updated IDDSTBY and IDDSTBY150 in the “DC electrical specifications” table.
• Updated the IDDA/IREF/IDDREG max value in the “DC electrical specifications” table.
• Updated IACT_F, IACT_MV_PU, IACT_MV_PD, RPUPD5K, RPUPDMTCH, and footnotes in the
“DC electrical specifications” table.
• Updated Medium pad type IDD33 values in the “I/O pad VRC33 average IDDE
specifications” table.
• Updated values for VOD in the “DSPI LVDS pad specification” table.
• Removed the footnotes from the “DSPI LVDS pad specifications” table.
• Removed the redundant “XTAL Load Capacitance” parameter instance from the
“PLLMRFM electrical specifications” table.
• Updated footnotes in the “PLLMRFM electrical specifications” table.
• Updated values for OFFNC and GAINNC in the “eQADC conversion specifications
(operating)” table.
• Added DIFFmax, DIFFmax2, DIFFmax4, and DIFFcmv parameters to the “eQADC
conversion specifications (operating)” table.
• Added the maximum operating frequency values in the “Cutoff frequency for additional
SRAM wait state” table.
• Updated multiple entries in the “APC, RWSC, WWSC settings vs. frequency of
operation” table.
• Removed footnote in the “APC, RWSC, WWSC settings vs. frequency of operation”
table.
• Changed the voltage in the “Pad AC specifications” table title from 4.5 V to 5.0 V.
• Added the maximum LH/HL output delay values for pad type MultiV in the “Pad AC
specifications (VDDE = 3.3 V)” table.
Rev. 6
—
• Rev. 6 not published.
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
135
Table 53. Revision history (continued)
Substantive changes
Revision
Date
Rev. 7
01/2012
• Minor editorial changes.
• In MPC5644A feature list, moved “24 unified channels” after “1 x eMIOS”.
• In Table 3MPC5644A signal properties/Column “Name” updated the following rows:
DSPI_D_SCK /GPIO [98] -Changed “-” to CS[2]
DSPI_D_SIN /GPIO[99] -Changed “-” to CS[3].
• In Table 11Thermal characteristics for 324-pin TEPBGA/ Column “Value” added
conditional text.
• In Table 21DC electrical specifications made the following changes:
-For the value “VOL_S” parameter changed from “Slow/ medium/multi-voltage pad I/O
output low voltage” to “Slow/medium pad I/O output low voltage”.
-Added a new row for “IDDSTBY27”.
-For row “IDDSTBY(operating current 0.95 -1.2V)” added max value “100” and changed
typ value from “125” to “35”.
-For row “IDDSTBY (operating current 2 - 5.5V)” added max value “110” and changed typ
value from “135” to “45”.
-For symbol “IDDSTBY 150(operating current 0.95 -1.2V)” added max value “2000”,
changed typ value from “1050” to “790”,C cell changed from “T” to “P” and for symbol
“IDDSTBY (operating current 2 - 5.5V)” added max value “2000”, changed typ value from
“1050” to “760”, C cell changed from “T” to “P”.
-Removed note 9 and note 10 (Characterization based capability) from symbol
“VOL_HS .
”
• Splitted Table 28eQADC conversion specifications (operating)into Table 29eQADC
single ended conversion specifications (operating) and Table 30eQADC differential
ended conversion specifications (operating).
• In Table 30 eQADC differential ended conversion specifications (operating)made the
following changes:
-Added the note of DIFFcmv on all of the DIFF specs.
-Min value changed from (VRH-VRL)/2-5% to (VRH+VRL)/2-5 % and max value
changed from (VRH-VRL)/2+5 % to (VRH+VRL)/2+5 %for DIFFcmv.
• In Table 31 Cutoff frequency for additional SRAM wait statemade the following
changes:
-Added note “Max frequencies including 2% PLL FM”.
-Max operating frequency changed from “96” to “98” and “150” to “153”.
• In Section 3.13, “Configuring SRAM wait states, changed text from “MPC5644A
Microcontroller Reference Manual “ to “device reference manual”.
• In Table 32APC, RWSC, WWSC settings vs. frequency of operation,
- Added note for “Max Flash Operating Frequency(MHz).
- Changed values from 30, 60,120, 150 to 20,61,123, 153 respectively in Max Flash
Operating Frequency (MHz).
• In Table 33,aFlash program and erase specificationsdded two parameter “Tpsrt” and
“Tesrt”.
• In Table 41External Bus Interface maximum operating frequency, replacedthe <=
symbol in notes with
• Added note “Refer to table DSPI timing for the numbers” in all the figures under
Section 3.17.8, “DSPI timing .
• In Table 52Orderable part number summary, changed LBGA208 to MAPBGA and
changed all packages to 123XXXX format.
MPC5644A Microcontroller Data Sheet, Rev. 7
136
Freescale Semiconductor
Table 53. Revision history (continued)
Substantive changes
Revision
Date
Rev. 7
(cont.)
01/12
• Added Table 17MPC5644A External network specification.
• Updated Figure 8.
• Changed External Network Parameter Ce min value to “3*2.35 F+5 F” from
“2*2.35 F+5 F” in Table 17MPC5644A External network specification.
• Changed Trans. Line (differential Zo) unit to from W in Table 25DSPI LVDS
pad specification.
MPC5644A Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
137
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Document Number: MPC5644A
Rev. 7
Jan 2012
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