SSTUA32S865 [NXP]
1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-667 RDIMM applications; 1.8 V 28位1 ： 2注册奇偶校验的DDR2-667 RDIMM应用程序的缓冲区
| 型号： | SSTUA32S865 |
| 厂家： | 
NXP |
| 描述： | 1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-667 RDIMM applications |
| 文件： | 总29页 (文件大小：153K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SSTUA32S865
1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-667
RDIMM applications
Rev. 02 — 16 March 2007
Product data sheet
1. General description
The SSTUA32S865 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two
rank by four (2R × 4) and similar high-density Double Data Rate 2 (DDR2) memory
modules. It is similar in function to the JEDEC-standard 14-bit DDR2 register, but
integrates the functionality of the normally required two registers in a single package,
thereby freeing up board real-estate and facilitating routing to accommodate high-density
Dual In-line Memory Module (DIMM) designs.
The SSTUA32S865 also integrates a parity function, which accepts a parity bit from the
memory controller, compares it with the data received on the D-inputs and indicates
whether a parity error has occurred on its open-drain PTYERR pin (active LOW).
The SSTUA32S865 is packaged in a 160-ball, 12 × 18 grid, 0.65 mm ball pitch, thin profile
fine-pitch ball grid array (TFBGA) package, which (while requiring a minimum
9 mm × 13 mm of board space) allows for adequate signal routing and escape using
conventional card technology.
2. Features
I 28-bit data register supporting DDR2
I Fully compliant to JEDEC standard for SSTUA32S865
I Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two
JEDEC-standard DDR2 registers (that is, 2 × SSTUA32864 or 2 × SSTUA32866)
I Parity checking function across 22 input data bits
I Parity out signal
I Controlled output impedance drivers enable optimal signal integrity and speed
I Exceeds JESD82-9 speed performance (1.8 ns max. single-bit switching propagation
delay, 2.0 ns max. mass-switching)
I Supports up to 450 MHz clock frequency of operation
I Optimized pinout for high-density DDR2 module design
I Chip-selects minimize power consumption by gating data outputs from changing state
I Supports Stub Series Terminated Logic SSTL_18 data inputs
I Differential clock (CK and CK) inputs
I Supports Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS)
switching levels on the control and RESET inputs
I Single 1.8 V supply operation (1.7 V to 2.0 V)
I Available in 160-ball 9 mm × 13 mm, 0.65 mm ball pitch TFBGA package
SSTUA32S865
NXP Semiconductors
1.8 V DDR2-667 registered buffer with parity
3. Applications
I 400 MT/s to 667 MT/s high-density (for example, 2 rank by 4) DDR2 registered DIMMs
I DDR2 Registered DIMMs (RDIMM) desiring parity checking functionality
4. Ordering information
Table 1.
Ordering information
Solder process
Type number
Package
Name
Description
Version
SSTUA32S865ET/G Pb-free (SnAgCu solder ball TFBGA160 plastic thin fine-pitch ball grid array package; SOT802-1
compound) 160 balls; body 9 × 13 × 0.8 mm
SSTUA32S865ET
SnPb solder ball compound TFBGA160 plastic thin fine-pitch ball grid array package; SOT802-1
160 balls; body 9 × 13 × 0.8 mm
SSTUA32S865_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 16 March 2007
2 of 29
SSTUA32S865
NXP Semiconductors
1.8 V DDR2-667 registered buffer with parity
5. Functional diagram
(CS ACTIVE)
VREF
SSTUA32S865
PARITY
D
Q
Q
Q
Q
Q
Q
Q
GENERATOR
AND
CHECKER
PARIN
22
PTYERR
R
Q0A
Q0B
D
R
D0
Q21A
Q21B
D
R
D21
QCS0A
QCS0B
DCS0
D
R
CSGATEEN
DCS1
QCS1A
QCS1B
D
R
QCKE0A,
QCKE1A
DCKE0,
2
DCKE1
2
2
D
R
QCKE0B,
QCKE1B
QODT0A,
QODT1A
DODT0,
2
DODT1
D
R
QODT0B,
QODT1B
RESET
002aab386
CK
CK
Fig 1. Functional diagram of SSTUA32S865
SSTUA32S865_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 16 March 2007
3 of 29
SSTUA32S865
NXP Semiconductors
1.8 V DDR2-667 registered buffer with parity
6. Pinning information
6.1 Pinning
SSTUA32S865ET/G
SSTUA32S865ET
ball A1
index area
2
4
6
8
10 12
9 11
1
3
5
7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
002aab387
Transparent top view
Fig 2. Pin configuration for TFBGA160
SSTUA32S865_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 16 March 2007
4 of 29
SSTUA32S865
NXP Semiconductors
1.8 V DDR2-667 registered buffer with parity
1
VREF
D1
2
n.c.
3
4
5
6
7
8
9
10
11
12
A
B
C
D
E
F
PARIN
n.c.
n.c.
n.c.
n.c.
n.c.
QCKE1A QCKE0A
QCKE1B QCKE0B
Q21A
Q21B
Q19A
Q19B
Q18A
Q18B
Q17B
Q17A
D2
QODT0B QODT0A
QODT1B QODT1A
D3
D4
D6
D5
VDDL
VDDL
VDDL
VDDL
VDDL
GND
GND
GND
GND
GND
GND
GND
VDDL
GND
GND
VDDL
VDDL
VDDL
n.c.
n.c.
GND
GND
GND
GND
Q20B
Q16B
Q1B
Q20A
Q16A
Q1A
D7
D8
VDDL
VDDR
D11
D9
VDDR
VDDR
GND
VDDR
VDDR
GND
D18
D12
D15
DCS0
DCS1
D14
D10
D16
D21
D20
DODT0
DCKE1
MCL
Q2B
Q2A
G
H
J
CSGATEEN
CK
Q5B
Q5A
VDDR
GND
VDDR
GND
QCS0B
QCS1B
Q6B
QCS0A
QCS1A
Q6A
CK
VDDL
GND
K
L
RESET
D0
VDDR
GND
VDDR
GND
GND
Q10B
Q9B
Q10A
Q9A
M
N
P
R
T
D17
VDDL
GND
VDDR
VDDR
GND
VDDR
GND
D19
VDDL
VDDL
VDDR
GND
Q11B
Q15B
Q14B
Q0B
Q11A
Q15A
Q14A
Q8B
D13
GND
GND
DODT1
DCKE0
VREF
MCL
MCL
PTYERR
n.c.
MCH
MCH
Q3B
Q3A
Q12B
Q12A
Q7B
Q7A
Q4B
Q4A
Q13B
Q13A
U
V
Q0A
Q8A
002aab011
160-ball, 12 × 18 grid; top view.
An empty cell indicates no ball is populated at that grid point.
n.c. denotes a no-connect (ball present but not connected to the die).
MCL denotes a pin that must be connected LOW.
MCH denotes a pin that must be connected HIGH.
Fig 3. Ball mapping
SSTUA32S865_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 16 March 2007
5 of 29
SSTUA32S865
NXP Semiconductors
1.8 V DDR2-667 registered buffer with parity
6.2 Pin description
Table 2.
Pin description
Symbol
Pin
Type
Description
Ungated inputs
DCKE0, DCKE1
DODT0, DODT1
U1, U2
T2, T1
SSTL_18
DRAM function pins not associated with Chip Select.
DRAM inputs, re-driven only when Chip Select is LOW.
Chip Select gated inputs
D0 to D21
M1, B1, B2, C1, C2, D2, D1, SSTL_18
E1, E2, F2, M2, F1, G2, R1,
L2, H2, N2, N1, G1, P1, R2,
P2
Chip Select inputs
DCS0, DCS1
J2, K2
SSTL_18
DRAM Chip Select signals. These pins initiate DRAM
address/command decodes, and as such at least one will
be LOW when a valid address/command is present. The
register can be programmed to re-drive all D-inputs only
(CSGATEEN = HIGH) when at least one Chip Select
input is LOW.
Re-driven outputs
Q0A to Q21A
V11, F12, G12, V6, V9, H12, SSTL_18
L12, V8, V12, N12, M12,
P12, V7, V10, T12, R12,
Outputs of the register, valid after the specified clock
count and immediately following a rising edge of the
clock.
E12, A12, A10, A9, D12, A8
Q0B to Q21B
U11, F11, G11, U6, U9,
H11, L11, U8, U12, N11,
M11, P11, U7, U10, T11,
R11, E11, A11, B10, B9,
D11, B8
QCS0A, QDS1A,
QCS0B, QCS1B
J12, K12, J11, K11
QCKE0A, QCKE1A, A7, A6, B7, B6
QCKE0B, QCKE1B
QODT0A, QODT1A, B12, C12, B11, C11
QODT0B, QODT1B
Parity input
PARIN
A3
U4
SSTL_18
Parity input for the D0 to D21 inputs. Arrives one clock
cycle after the corresponding data input.
Parity error
PTYERR
open drain When LOW, this output indicates that a parity error was
identified associated with the address and/or command
inputs. PTYERR will be active for two clock cycles, and
delayed by an additional clock cycle for compatibility with
final parity out timing on the industry-standard DDR2
register with parity (in JEDEC definition).
Program inputs
CSGATEEN
H1
1.8 V
LVCMOS
Chip Select Gate Enable. When HIGH, the D0 to D21
inputs will be latched only when at least one Chip Select
input is LOW during the rising edge of the clock. When
LOW, the D0 to D21 inputs will be latched and redriven
on every rising edge of the clock.
SSTUA32S865_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 16 March 2007
6 of 29
SSTUA32S865
NXP Semiconductors
1.8 V DDR2-667 registered buffer with parity
Table 2.
Pin description …continued
Symbol
Pin
Type
Description
Clock inputs
CK, CK
J1, K1
SSTL_18
Differential master clock input pair to the register. The
register operation is triggered by a rising edge on the
positive clock input (CK).
Miscellaneous inputs
MCL
U3, V2, V3
U5, V5
L1
Must be connected to a logic LOW.
Must be connected to a logic HIGH.
MCH
RESET
1.8 V
LVCMOS
Asynchronous reset input. When LOW, it causes a reset
of the internal latches, thereby forcing the outputs LOW.
RESET also resets the PTYERR signal.
VREF
VDDL
VDDR
GND
A1, V1
0.9 V
nominal
Input reference voltage for the SSTL_18 inputs. Two pins
(internally tied together) are used for increased reliability.
D4, E4, E6, F4, G4, H4, K4,
K5, N4, N5, P5, P6, R5, R6
Power supply voltage.
Power supply voltage.
Ground.
E7, F8, F9, G8, G9, J8, J9,
L8, L9, N8, N9, P7, P8
D5, D8, D9, E5, E8, E9, F5,
G5, H5, H8, H9, J4, J5, K8,
K9, L4, L5, M4, M5, M8, M9,
P4, P9, R4, R7, R8, R9
n.c.
A2, A4, A5, B3, B4, B5, D6,
D7, V4
Ball present but not connected to die.
SSTUA32S865_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 16 March 2007
7 of 29
SSTUA32S865
NXP Semiconductors
1.8 V DDR2-667 registered buffer with parity
7. Functional description
7.1 Function table
Table 3.
RESET
Function table (each flip-flop)
Inputs
Outputs[1]
DCS0
DCS1
CSGATEEN
CK
CK
Dn, DODTn,
DCKEn
Qn
QCS0 QCS1 QODTn,
QCKEn
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
X
↑
↓
L
L
H
L
L
L
L
L
H
X
↑
↓
H
L
L
X
L or H
L or H
X
Q0
L
Q0
L
Q0
H
Q0
L
L
H
H
H
L
X
↑
↓
L
L
X
↑
↓
H
H
L
H
H
L
X
L or H
L or H
X
Q0
L
Q0
H
Q0
L
Q0
L
H
H
H
H
H
H
H
H
H
X
↑
↓
L
L
X
↑
↓
H
H
H
L
H
L
X
L or H
L or H
X
Q0
L
Q0
H
Q0
H
Q0
L
H
H
H
H
H
H
L
↑
↓
L
L
↑
L or H
↑
↓
L or H
↓
H
H
H
H
H
L
X
Q0
Q0
Q0
Q0
L
Q0
H
Q0
H
Q0
L
H
L
H
H
↑
↓
H
X
H
H
H
L or H
L or H
Q0
L
Q0
L
Q0
L
X or
X or
X or floating
X or
X or
X or floating
floating
floating
floating
floating
[1] Q0 is the previous state of the associated output.
Table 4.
RESET
Parity and standby function table
Inputs
Output
PTYERR[2][3]
DCS0
DCS1
CK
CK
∑ of inputs = H
PARIN[1]
(D0 to D21)
H
H
H
H
H
H
H
H
H
H
L
L
L
H
H
H
H
L
↑
↓
even
odd
L
H
↑
↓
L
L
L
↑
↓
even
odd
H
L
L
↑
↓
H
H
H
H
H
H
H
X
↑
↓
even
odd
L
H
L
↑
↓
L
L
L
↑
↓
even
odd
H
L
L
↑
↑
↓
↓
H
H
H
X
X
X
X
PTYERR0
PTYERR0
H
L or H
L or H
X
X or floating X or floating X or floating X or floating
X or floating
X or floating
[1] PARIN arrives one clock cycle after the data to which it applies. All Dn inputs must be driven to a known state for parity to be calculated
correctly.
SSTUA32S865_2
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Product data sheet
Rev. 02 — 16 March 2007
8 of 29
SSTUA32S865
NXP Semiconductors
1.8 V DDR2-667 registered buffer with parity
[2] This condition assumes PTYERR is HIGH at the crossing of CK going HIGH and CK going LOW. If PTYERR is LOW, it stays latched
LOW for two clock cycles or until RESET is driven LOW.
CSGATEEN is ‘don’t care’ for PTYERR.
[3] PTYERR0 is the previous state of output PTYERR.
7.2 Functional information
This 28-bit 1 : 2 registered buffer with parity is designed for 1.7 V to 2.0 V VDD operation.
All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The
control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized
to drive the DDR2 DIMM load.
The SSTUA32S865 operates from a differential clock (CK and CK). Data are registered at
the crossing of CK going HIGH, and CK going LOW.
The device supports low-power standby operation. When the reset input (RESET) is LOW,
the differential input receivers are disabled, and undriven (floating) data, clock and
reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW all
registers are reset, and all outputs except PTYERR are forced LOW. The LVCMOS
RESET input must always be held at a valid logic HIGH or LOW level.
To ensure defined outputs from the register before a stable clock has been supplied,
RESET must be held in the LOW state during power-up.
In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with
respect to CK and CK. Therefore, no timing relationship can be guaranteed between the
two. When entering reset, the register will be cleared and the data outputs will be driven
LOW quickly, relative to the time to disable the differential input receivers. However, when
coming out of reset, the register will become active quickly, relative to the time to enable
the differential input receivers. As long as the data inputs are LOW, and the clock is stable
during the time from the LOW-to-HIGH transition of RESET until the input receivers are
fully enabled, the design of the SSTUA32S865 ensures that the outputs remain LOW, thus
ensuring no glitches on the output.
The device monitors both DCS0 and DCS1 inputs and will gate the Qn outputs from
changing states when both DCS0 and DCS1 are HIGH. If either DCS0 or DCS1 input is
LOW, the Qn outputs will function normally. The RESET input has priority over the DCS0
and DCS1 control and will force the Qn outputs LOW and the PTYERR output HIGH. If the
DCSn-control functionality is not desired, then the CSGATEEN input can be hardwired to
ground, in which case, the setup-time requirement for DCSn would be the same as for the
other Dn data inputs.
The SSTUA32S865 includes a parity checking function. The SSTUA32S865 accepts a
parity bit from the memory controller at its input pin PARIN, compares it with the data
received on the Dn inputs (with either DCS0 or DCS1 active) and indicates whether a
parity error has occurred on its open-drain PTYERR pin (active LOW).
SSTUA32S865_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 16 March 2007
9 of 29
SSTUA32S865
NXP Semiconductors
1.8 V DDR2-667 registered buffer with parity
7.3 Functional differences to SSTU32864
The SSTUA32S865 for its basic register functionality, signal definition and performance is
based upon the industry-standard SSTU32864, but provides key operational features
which differ (at least in part) from the industry-standard register in the following aspects:
7.3.1 Chip Select (CS) gating of key inputs (DCS0, DCS1, CSGATEEN)
As a means to reduce device power, the internal latches will only be updated when one or
both of the CS inputs are active (LOW) and CSGATEEN HIGH at the rising edge of the
clock. The 22 ‘Chip-Select-gated’ input signals associated with this function include
addresses (ADDR0 to ADDR15, BA0 to BA2), and RAS, CAS, WE, with the remaining
signals (CS, CKE, ODT) continuously re-driven at the rising edge of every clock as they
are independent of CS. The CS gating function can be disabled by tying CSGATEEN
LOW, enabling all internal latches to be updated on every rising edge of the clock.
Table 5.
Mode
Chip Select gating mode
Signal name
CSGATEEN
HIGH
Description
Gating
Registers only re-drive signals to the DRAMs when
Chip Select inputs are LOW.
Non-gating
CSGATEEN
LOW
Registers always re-drive signals on every clock cycle,
independent of the state of the Chip Select inputs.
7.3.2 Parity error checking and reporting
The SSTUA32S865 incorporates a parity function, whereby the signal received on input
pin PARIN is received as parity to the register, one clock cycle later than the CS-gated
inputs. The received parity bit is then compared to the parity calculated across these
same inputs by the register parity logic to verify that the information has not been
corrupted. The 22 CS-gated input signals will be latched and re-driven on the first clock,
and any error will be reported one clock cycle later via the PTYERR output pin (driven
LOW for two consecutive clock cycles). PTYERR is an open-drain output, allowing
multiple modules to share a common signal pin for reporting the occurrence of a parity
error during a valid command cycle (coincident with the re-driven signals). This output is
driven LOW for two consecutive clock cycles to allow the memory controller sufficient time
to sense and capture the error even. A LOW state on PTYERR indicates that a parity error
has occurred.
7.3.3 Reset (RESET)
Similar to the RESET pin on the industry-standard SSTU32864, this pin is used to clear all
internal latches and all outputs will be driven LOW quickly except the PTYERR output,
which will be floated (and will normally default HIGH by their external pull-up).
7.3.4 Power-up sequence
The reset function for the SSTUA32S865 is similar to that of the SSTU32864 except that
the PTYERR signal is also cleared and will be held clear (HIGH) for three consecutive
clock cycles.
SSTUA32S865_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 16 March 2007
10 of 29
SSTUA32S865
NXP Semiconductors
1.8 V DDR2-667 registered buffer with parity
RESET
DCSn
CK
m
m + 1
m + 2
m + 3
m + 4
CK
t
ACT
t
t
h
su
(1)
Dn
t
, t
PDM PDMSS
CK to Q
Qn
t
t
h
su
PARIN
t
t
, t
PHL PLH
PHL
CK to PTYERR
CK to PTYERR
PTYERR
002aaa983
HIGH, LOW, or Don't care
HIGH or LOW
(1) After RESET is switched from LOW to HIGH, all data and PARIN input signals must be set and held LOW for a minimum
time of tACT(max) to avoid false error.
Fig 4. RESET switches from LOW to HIGH
SSTUA32S865_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 16 March 2007
11 of 29
SSTUA32S865
NXP Semiconductors
1.8 V DDR2-667 registered buffer with parity
RESET
DCSn
CK
m
m + 1
m + 2
m + 3
m + 4
CK
t
t
h
su
(1)
Dn
t
, t
PDM PDMSS
CK to Q
Qn
t
su
t
h
PARIN
t
, t
PHL PLH
CK to PTYERR
PTYERR
002aaa984
Output signal is dependent
on the prior unknown event
Unknown input event
HIGH or LOW
Fig 5. RESET being held HIGH
SSTUA32S865_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 16 March 2007
12 of 29
SSTUA32S865
NXP Semiconductors
1.8 V DDR2-667 registered buffer with parity
RESET
DCSn
t
INACT
(1)
CK
(1)
CK
(1)
Dn
t
PHL
RESET to Q
Qn
(1)
PARIN
t
PLH
RESET to PTYERR
PTYERR
002aaa985
HIGH, LOW, or Don't care
HIGH or LOW
(1) After RESET is switched from HIGH to LOW, all data and clock input signals must be set and held at valid logic levels (not
floating) for a minimum time of tINACT(max)
.
Fig 6. RESET switches from HIGH to LOW
SSTUA32S865_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 16 March 2007
13 of 29
SSTUA32S865
NXP Semiconductors
1.8 V DDR2-667 registered buffer with parity
22
22
Dn
QnA
QnB
D
Q
D
D
PTYERR
D
LATCHING AND
RESET FUNCTION
(1)
PARIN
CLOCK
002aaa417
(1) This function holds the error for two cycles. For details, see Section 7 “Functional description” and Figure 4 “RESET
switches from LOW to HIGH”.
Fig 7. Parity logic diagram
SSTUA32S865_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 16 March 2007
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SSTUA32S865
NXP Semiconductors
1.8 V DDR2-667 registered buffer with parity
8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDD
VI
Parameter
Conditions
Min
Max
Unit
V
supply voltage
−0.5
+2.5
[1]
[1]
input voltage
receiver
−0.5
+2.5
V
VO
output voltage
driver
−0.5
VDD + 0.5
−50
V
IIK
input clamping current
output clamping current
output current
VI < 0 V or VI > VDD
VO < 0 V or VO > VDD
continuous; 0 V < VO < VDD
-
-
-
-
mA
mA
mA
mA
IOK
±50
IO
±50
ICCC
continuous current through
each VDD or GND pin
±100
Tstg
storage temperature
−65
2
+150
°C
kV
V
Vesd
electrostatic discharge
voltage
Human Body Model (HBM); 1.5 kΩ; 100 pF
Machine Model (MM); 0 Ω; 200 pF
-
-
200
[1] The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
9. Recommended operating conditions
Table 7.
Symbol
VDD
Recommended operating conditions
Parameter
Conditions
Min
Typ
Max
Unit
supply voltage
1.7
-
2.0
V
Vref
reference voltage
0.49 × VDD
0.50 × VDD 0.51 × VDD
V
VT
termination voltage
Vref − 0.040 Vref
Vref + 0.040
V
VI
input voltage
0
-
-
-
-
-
-
-
-
-
-
-
-
VDD
-
V
[1]
[1]
[1]
[1]
[2]
[2]
VIH(AC)
VIL(AC)
VIH(DC)
VIL(DC)
VIH
AC HIGH-level input voltage
AC LOW-level input voltage
DC HIGH-level input voltage
DC LOW-level input voltage
HIGH-level input voltage
LOW-level input voltage
common mode input voltage range
differential input voltage
HIGH-level output current
LOW-level output current
ambient temperature
data inputs (Dn)
data inputs (Dn)
data inputs (Dn)
data inputs (Dn)
RESET
Vref + 0.250
V
-
Vref − 0.250
V
Vref + 0.125
-
V
-
Vref − 0.125
-
V
0.65 × VDD
V
VIL
RESET
-
0.35 × VDD
V
VICR
VID
CK, CK
0.675
1.125
-
V
CK, CK
600
mV
mA
mA
°C
IOH
-
−8
IOL
-
8
Tamb
operating in
free air
0
+70
[1] The differential inputs must not be floating, unless RESET is LOW.
[2] The RESET input of the device must be held at valid logic levels (not floating) to ensure proper device operation.
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10. Characteristics
Table 8.
Characteristics
Over recommended operating conditions, unless otherwise noted.
Symbol
VOH
VOL
II
Parameter
Conditions
Min
Typ
Max
-
Unit
V
HIGH-level output voltage
LOW-level output voltage
input current
IOH = −6 mA; VDD = 1.7 V
IOL = 6 mA; VDD = 1.7 V
1.2
-
-
-
-
-
-
-
0.5
±5
2
V
all inputs; VI = VDD or GND; VDD = 2.0 V
µA
mA
IDD
supply current
static standby; RESET = GND;
V
DD = 2.0 V
static operating; RESET = VDD
DD = 2.0 V; VI = VIH(AC) or VIL(AC)
clock only; RESET = VDD
VI = VIH(AC) or VIL(AC)
;
-
-
-
40
-
mA
V
IDDD
dynamic operating current
per MHz
;
16
µA
;
CK and CK switching at 50 % duty cycle.
IO = 0 mA; VDD = 1.8 V
per each data input; RESET = VDD
VI = VIH(AC) or VIL(AC)
;
-
19
-
µA
;
CK and CK switching at 50 % duty cycle.
One data input switching at half clock
frequency, 50 % duty cycle.
IO = 0 mA; VDD = 1.8 V
Ci
input capacitance
data inputs; VI = Vref ± 250 mV;
2.5
2
-
-
-
3.5
3
pF
pF
pF
V
DD = 1.8 V
CK and CK; VICR = 0.9 V; VID = 600 mV;
DD = 1.8 V
V
RESET; VI = VDD or GND; VDD = 1.8 V
3
5
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Table 9.
Timing requirements
Over recommended operating conditions, unless otherwise noted.
Symbol
fclock
tW
Parameter
Conditions
Min
Typ
Max
450
-
Unit
MHz
ns
clock frequency
-
-
-
-
-
-
pulse width
CK, CK HIGH or LOW
1
[1][2]
[1][3]
tACT
differential inputs active time
differential inputs inactive time
set-up time
-
10
15
-
ns
tINACT
tsu
-
ns
Chip Select; DCS0, DCS1
valid before clock
switching
0.7
ns
Data; Dn valid before
clock switching
0.5
-
-
ns
PARIN before CK and CK
0.5
0.5
-
-
-
-
ns
ns
th
hold time
input to remain valid after
clock switching
PARIN after CK and CK
0.5
-
-
ns
[1] This parameter is not necessarily production tested.
[2] Data inputs must be active below a minimum time of tACT(max) after RESET is taken HIGH.
[3] Data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT(max) after RESET is taken LOW.
Table 10. Switching characteristics
Over recommended operating conditions, unless otherwise noted.
Symbol
fmax
Parameter
Conditions
Min
450
1.25
1.2
1
Typ
Max
-
Unit
MHz
ns
maximum input clock frequency
peak propagation delay
LOW-to-HIGH delay
-
-
-
-
-
-
[1]
tPDM
tLH
CK and CK to output
CK and CK to PTYERR
CK and CK to PTYERR
from RESET to PTYERR
CK and CK to output
1.8
3
ns
tHL
HIGH-to-LOW delay
3
ns
tPLH
LOW-to-HIGH propagation delay
-
3
ns
[1][2]
tPDMSS
simultaneous switching peak
propagation delay
-
2.0
ns
tPHL
HIGH-to-LOW propagation delay
RESET to output
-
-
3
ns
[1] Includes 350 ps of test-load transmission line delay.
[2] This parameter is not necessarily production tested.
Table 11. Output edge rates
Over recommended operating conditions, unless otherwise noted.
Symbol
dV/dt_r
dV/dt_f
dV/dt_∆
Parameter
Conditions
Min
Typ
Max
Unit
V/ns
V/ns
V/ns
rising edge slew rate
falling edge slew rate
1
1
-
-
-
-
4
4
1
absolute difference between dV/dt_r
and dV/dt_f
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11. Test information
11.1 Test circuit
All input pulses are supplied by generators having the following characteristics:
Pulse Repetition Rate (PRR) ≤ 10 MHz; Z0 = 50 Ω; input slew rate = 1 V/ns ± 20 %,
unless otherwise specified.
The outputs are measured one at a time with one transition per measurement.
V
DD
DUT
delay = 350 ps
= 50 Ω
R
= 1000 Ω
= 1000 Ω
L
50 Ω
Z
o
CK
CK
CK inputs
OUT
(1)
= 30 pF
C
L
R
L
test point
R
L
= 100 Ω
test point
002aaa371
(1) CL includes probe and jig capacitance.
Fig 8. Load circuit
LVCMOS
V
DD
0.5V
0.5V
RESET
DD
DD
0 V
t
t
ACT
INACT
90 %
(1)
DD
I
10 %
002aaa372
(1) IDD tested with clock and data inputs held at VDD or GND, and IO = 0 mA.
Fig 9. Voltage and current waveforms; inputs active and inactive times
t
W
V
V
IH
IL
V
input
V
V
ICR
ID
ICR
002aaa373
VID = 600 mV.
VIH = Vref + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs.
VIL = Vref − 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 10. Voltage waveforms; pulse duration
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CK
CK
V
V
ICR
ID
t
t
h
su
V
V
IH
IL
input
V
ref
V
ref
002aaa374
VID = 600 mV.
Vref = 0.5VDD
.
VIH = Vref + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs.
VIL = Vref − 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 11. Voltage waveforms; setup and hold times
CK
V
V
V
i(p-p)
ICR
ICR
CK
t
t
PHL
PLH
V
V
OH
OL
V
output
T
002aaa375
tPLH and tPHL are the same as tPD
.
Fig 12. Voltage waveforms; propagation delay times (clock to output)
LVCMOS
V
V
V
V
IH
RESET
0.5V
DD
IL
t
PHL
OH
OL
output
V
T
002aaa376
tPLH and tPHL are the same as tPD
.
VIH = Vref + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs.
VIL = Vref − 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 13. Voltage waveforms; propagation delay times (reset to output)
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11.2 Output slew rate measurement
VDD = 1.8 V ± 0.1 V.
All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz; Z0 = 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise specified.
V
DD
R
DUT
= 50 Ω
L
OUT
test point
002aaa377
(1)
= 10 pF
C
L
(1) CL includes probe and jig capacitance.
Fig 14. Load circuit, HIGH-to-LOW slew measurement
output
V
OH
80 %
dv_f
20 %
V
OL
dt_f
002aaa378
Fig 15. Voltage waveforms, HIGH-to-LOW slew rate measurement
DUT
OUT
test point
(1)
= 10 pF
C
L
R
L
= 50 Ω
002aaa379
(1) CL includes probe and jig capacitance.
Fig 16. Load circuit, LOW-to-HIGH slew measurement
dt_r
V
V
OH
80 %
dv_r
20 %
output
OL
002aaa380
Fig 17. Voltage waveforms, LOW-to-HIGH slew rate measurement
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Product data sheet
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1.8 V DDR2-667 registered buffer with parity
11.3 Error output load circuit and voltage measurement
VDD = 1.8 V ± 0.1 V.
All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz; Z0 = 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise specified.
V
DD
R
DUT
= 1 kΩ
L
OUT
test point
002aaa500
(1)
= 10 pF
C
L
(1) CL includes probe and jig capacitance.
Fig 18. Load circuit, error output measurements
LVCMOS
V
DD
RESET
0.5V
DD
0 V
t
PLH
V
OH
output
waveform 2
0.15 V
0 V
002aaa501
Fig 19. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to
RESET input
timing
inputs
V
i(p-p)
V
V
ICR
ICR
t
HL
V
V
DD
OL
output
waveform 1
0.5V
DD
002aaa502
Fig 20. Voltage waveforms, open-drain output HIGH-to-LOW transition time with respect
to clock inputs
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Product data sheet
Rev. 02 — 16 March 2007
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1.8 V DDR2-667 registered buffer with parity
timing
inputs
V
V
i(p-p)
V
ICR
ICR
t
LH
V
OH
output
waveform 2
0.15 V
0 V
002aaa503
Fig 21. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to
clock inputs
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Product data sheet
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1.8 V DDR2-667 registered buffer with parity
12. Package outline
TFBGA160: plastic thin fine-pitch ball grid array package; 160 balls; body 9 x 13 x 0.8 mm
SOT802-1
D
B
A
ball A1
index area
A
A
2
E
1
A
detail X
C
e
1
v M
w M
C
C
A
B
e
b
y
y
C
1
1/2e
V
U
T
P
R
N
e
M
K
H
L
J
e
2
1/2e
G
E
C
A
F
D
B
ball A1
index area
1
3
5
7
9
11
2
4
6
8
10
12
X
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
A
b
D
E
e
e
e
v
w
y
y
1
1
2
1
2
max.
0.35 0.85 0.45
0.25 0.75 0.35
9.1
8.9
13.1
12.9
mm
1.2
0.65 7.15 11.05 0.15 0.08
0.1
0.1
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
03-01-29
SOT802-1
- - -
- - -
- - -
Fig 22. Package outline SOT802-1 (TFBGA160)
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1.8 V DDR2-667 registered buffer with parity
13. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus PbSn soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
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13.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 23) than a PbSn process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 12 and 13
Table 12. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
235
≥ 350
220
< 2.5
≥ 2.5
220
220
Table 13. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 23.
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Product data sheet
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maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 23. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
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14. Revision history
Table 14. Revision history
Document ID
SSTUA32S865_2
Modifications:
Release date
Data sheet status
Change notice
Supersedes
20070316
Product data sheet
-
SSTUA32S865_1
• The format of this data sheet has been redesigned to comply with the new identity guidelines of
NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Figure 6 “RESET switches from HIGH to LOW”: changed “tRPHL” to “tPHL”; changed “tRPLH” to
“tPLH
”
• Table 6 “Limiting values”:
–
–
–
changed Parameter for VI to “input voltage”; moved “receiver” to Conditions
changed Parameter for VO to “output voltage”; moved “driver” to Conditions
changed Parameter for IO to “output current”; moved “continuous” to Conditions
• Table 7 “Recommended operating conditions”: changed symbol “VTT” to “VT”
• Table 8 “Characteristics”:
–
Symbol IDD: changed Parameter to “supply current”; moved “static standby” and “static
operating” to Conditions
–
–
IDD, supply current, static standby: changed Max value from “100 µA” to “2 mA”
Symbol IDDD: changed Parameter to “dynamic operating current per MHz”; moved “clock only”
and “per each data input” to Conditions
–
Symbol Ci: changed Parameter to “input capacitance”; moved “data inputs”, “CK and CK”, and
“RESET” to Conditions
• Table 9 “Timing requirements”, Symbol tW: changed Parameter to “pulse width”; moved “CK, CK
HIGH or LOW” to Conditions
• Table 10 “Switching characteristics”:
–
–
–
–
changed Symbol “fMAX” to “fmax”
changed Parameter for tPDM to “peak propagation delay”
changed Parameter for tPDMSS to “simultaneous switching peak propagation delay”
changed Parameter for tPHL to “HIGH-to-LOW propagation delay”
SSTUA32S865_1
(9397 750 14758)
20050525
Product data sheet
-
-
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15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of a NXP Semiconductors product can reasonably be expected to
15.2 Definitions
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
16. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
SSTUA32S865_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 16 March 2007
28 of 29
SSTUA32S865
NXP Semiconductors
1.8 V DDR2-667 registered buffer with parity
17. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
7
Functional description . . . . . . . . . . . . . . . . . . . 8
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional information . . . . . . . . . . . . . . . . . . . 9
Functional differences to SSTU32864 . . . . . . 10
Chip Select (CS) gating of key inputs
7.1
7.2
7.3
7.3.1
(DCS0, DCS1, CSGATEEN). . . . . . . . . . . . . . 10
Parity error checking and reporting. . . . . . . . . 10
Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . 10
Power-up sequence . . . . . . . . . . . . . . . . . . . . 10
7.3.2
7.3.3
7.3.4
8
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 15
Recommended operating conditions. . . . . . . 15
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 16
9
10
11
Test information. . . . . . . . . . . . . . . . . . . . . . . . 18
Test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Output slew rate measurement. . . . . . . . . . . . 20
Error output load circuit and voltage
11.1
11.2
11.3
measurement . . . . . . . . . . . . . . . . . . . . . . . . . 21
12
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23
13
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Introduction to soldering . . . . . . . . . . . . . . . . . 24
Wave and reflow soldering . . . . . . . . . . . . . . . 24
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 24
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 25
13.1
13.2
13.3
13.4
14
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 27
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 28
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 28
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 28
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 28
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 16 March 2007
Document identifier: SSTUA32S865_2
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