SSTUG32866EC/S,518_技术文档

SSTUG32866

1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 conﬁgurable registered buffer

with parity for DDR2-1G RDIMM applications

Rev. 01 — 29 June 2007

Product data sheet

1. General description

The SSTUG32866 is a 1.8 V conﬁgurable register speciﬁcally designed for use on DDR2

memory modules requiring a parity checking function. It is deﬁned in accordance with the

JEDEC standard for the SSTUG32866 registered buffer. The register is conﬁgurable

(using conﬁguration pins C0 and C1) to two topologies: 25-bit 1 : 1 or 14-bit 1 : 2, and in

the latter conﬁguration can be designated as Register A or Register B on the DIMM.

The SSTUG32866 accepts a parity bit from the memory controller on its parity bit

(PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs

and indicates whether a parity error has occurred on its open-drain QERR pin

(active LOW). The convention is even parity, that is, valid parity is deﬁned as an even

number of ones across the DIMM-independent data inputs combined with the parity input

bit.

The SSTUG32866 is packaged in a 96-ball, 6 × 16 grid, 0.8 mm ball pitch LFBGA

package (13.5 mm × 5.5 mm).

2. Features

I Conﬁgurable register supporting DDR2 up to 800 MT/s Registered DIMM applications

I Conﬁgurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode

I Controlled output impedance drivers enable optimal signal integrity and speed

I Meets or exceeds SSTUG32866 JEDEC standard speed performance

I Supports up to 550 MHz clock frequency of operation

I Optimized pinout for high-density DDR2 module design

I Chip-selects minimize power consumption by gating data outputs from changing state

I Supports SSTL_18 data inputs

I Checks parity on the DIMM-independent data inputs

I Partial parity output and input allows cascading of two SSTUG32866s for correct parity

error processing

I Differential clock (CK and CK) inputs

I Supports LVCMOS switching levels on the control and RESET inputs

I Single 1.8 V supply operation (1.7 V to 2.0 V)

I Available in 96-ball, 13.5 mm × 5.5 mm, 0.8 mm ball pitch LFBGA package

3. Applications

I 400 MT/s to 800 MT/s and higher DDR2 registered DIMMs desiring parity checking

functionality

SSTUG32866

NXP Semiconductors

1.8 V DDR2-1G conﬁgurable registered buffer with parity

4. Ordering information

Table 1.

Ordering information

Solder process

Type number

Package

Name

Description

Version

SSTUG32866EC/G Pb-free (SnAgCu solder LFBGA96 plastic low proﬁle ﬁne-pitch ball grid array package; SOT536-1

ball compound) 96 balls; body 13.5 × 5.5 × 1.05 mm

SSTUG32866EC/S Pb-free (SnAgCu solder LFBGA96 plastic low proﬁle ﬁne-pitch ball grid array package; SOT536-1

ball compound)

96 balls; body 13.5 × 5.5 × 1.05 mm

4.1 Ordering options

Table 2.

Ordering options

Type number

SSTUG32866EC/G

SSTUG32866EC/S

Temperature range

T_amb= 0 °C to +70 °C

T_amb= 0 °C to +85 °C

SSTUG32866_1

Product data sheet

Rev. 01 — 29 June 2007

2 of 28

SSTUG32866

NXP Semiconductors

1.8 V DDR2-1G conﬁgurable registered buffer with parity

5. Functional diagram

RESET

CK

SSTUG32866

VREF

DCKE

1D

C1

QCKEA

QCKEB

(1)

R

DODT

DCS

CSR

D2

1D

QODTA

QODTB

C1

R

1D

QCSA

C1

(1)

QCSB

R

0

1

1D

Q2A

C1

(1)

Q2B

R

to 10 other channels

(D3, D5, D6, D8 to D14)

002aad081

(1) Disabled in 1 : 1 conﬁguration.

Fig 1. Functional diagram of SSTUG32866; 1 : 2 Register A conﬁguration with C0 = 0 and

C1 = 1 (positive logic)

SSTUG32866_1

Product data sheet

Rev. 01 — 29 June 2007

3 of 28

SSTUG32866

NXP Semiconductors

1.8 V DDR2-1G conﬁgurable registered buffer with parity

RESET

CK

LPS0

(internal node)

Q2A, Q3A,

Q5A, Q6A,

Q8A to Q14A

D2, D3, D5, D6,

11

CE

D

D8 to D14

VREF

11

D2, D3, D5, D6,

D8 to D14

11

CLK

R

11

Q2B, Q3B,

Q5B, Q6B,

Q8B to Q14B

D2, D3, D5, D6,

D8 to D14

11

PARITY

CHECK

C1

1

0

1

PPO

D

CLK

R

CLK

R

CLK

R

CE

PAR_IN

QERR

C0

CLK

2-BIT

COUNTER

R

0

1

LPS1

(internal node)

D

CLK

R

002aaa650

Fig 2. Parity logic diagram for 1 : 2 Register A conﬁguration (positive logic); C0 = 0, C1 = 1

SSTUG32866_1

Product data sheet

Rev. 01 — 29 June 2007

4 of 28

SSTUG32866

NXP Semiconductors

1.8 V DDR2-1G conﬁgurable registered buffer with parity

6. Pinning information

6.1 Pinning

SSTUG32866EC/G

SSTUG32866EC/S

ball A1

index area

1 2 3 4 5 6

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

002aad082

Transparent top view

Fig 3. Pin conﬁguration for LFBGA96

1

DCKE

D2

2

3

4

5

QCKE

Q2

6

A

B

C

D

E

F

PPO

D15

D16

QERR

D17

D18

VREF

GND

V

DNU

Q15

Q16

DNU

Q17

Q18

C0

DD

GND

D3

V

Q3

DD

DODT

D5

GND

QODT

Q5

V

DD

D6

GND

Q6

G

H

J

PAR_IN RESET

V

C1

DD

CK

DCS

CSR

D19

D20

D21

D22

D23

D24

D25

GND

QCS

n.c.

Q8

DNU

n.c.

V

DD

K

L

D8

GND

Q19

Q20

Q21

Q22

Q23

Q24

D9

V

Q9

DD

M

N

P

R

T

D10

D11

D12

D13

D14

GND

Q10

Q11

Q12

Q13

Q14

V

DD

GND

V

DD

VREF

Q25

002aab108

Fig 4. Ball mapping, 1 : 1 register (C0 = 0, C1 = 0)

Rev. 01 — 29 June 2007

SSTUG32866_1

Product data sheet

5 of 28

SSTUG32866

NXP Semiconductors

1.8 V DDR2-1G conﬁgurable registered buffer with parity

1

DCKE

D2

2

3

4

5

6

A

B

C

D

E

F

PPO

DNU

QERR

n.c.

VREF

GND

V

QCKEA QCKEB

DD

GND

Q2A

Q3A

Q2B

Q3B

D3

V

DD

DODT

D5

GND

QODTA QODTB

V

Q5A

Q6A

Q5B

Q6B

DD

D6

n.c.

GND

G

H

J

PAR_IN RESET

V

C1

C0

DD

CK

DCS

CSR

DNU

GND

QCSA

n.c.

QCSB

n.c.

V

DD

K

L

D8

GND

Q8A

Q8B

D9

V

Q9A

Q9B

DD

M

N

P

R

T

D10

D11

D12

D13

D14

GND

Q10A

Q11A

Q12A

Q13A

Q14A

Q10B

Q11B

Q12B

Q13B

V

DD

GND

V

DD

VREF

Q14B

002aab109

Fig 5. Ball mapping, 1 : 2 Register A (C0 = 0, C1 = 1)

1

2

3

4

5

6

A

B

C

D

E

F

D1

D2

D3

D4

D5

D6

PPO

DNU

QERR

DNU

VREF

GND

V

Q1A

Q2A

Q3A

Q4A

Q5A

Q6A

C1

Q1B

Q2B

Q3B

Q4B

Q5B

Q6B

C0

DD

GND

V

DD

GND

V

DD

GND

G

H

J

PAR_IN RESET

V

DD

CK

DCS

CSR

DNU

GND

QCSA

n.c.

QCSB

n.c.

V

DD

K

L

D8

GND

Q8A

Q9A

Q10A

Q8B

Q9B

Q10B

D9

V

DD

M

N

P

R

T

D10

DODT

D12

D13

DCKE

GND

V

QODTA QODTB

DD

GND

Q12A

Q13A

Q12B

Q13B

V

DD

VREF

QCKEA QCKEB

002aab110

Fig 6. Ball mapping, 1 : 2 Register B (C0 = 1, C1 = 1)

Rev. 01 — 29 June 2007

SSTUG32866_1

Product data sheet

6 of 28

SSTUG32866

NXP Semiconductors

1.8 V DDR2-1G conﬁgurable registered buffer with parity

6.2 Pin description

Table 3.

Symbol

GND

Pin description

Type

Description

B3, B4, D3, D4, F3, F4, ground input

H3, H4, K3, K4, M3,

ground

M4, P3, P4

V_DD

A4, C3, C4, E3, E4,

G3, G4, J3, J4, L3, L4,

N3, N4, R3, R4, T4

1.8 V nominal

power supply voltage

VREF

CK

A3, T3

H1

0.9 V nominal

input reference voltage

differential input positive master clock input

differential input negative master clock input

CK

J1

C0

G6

LVCMOS inputs Conﬁguration control inputs; Register A or Register B and

1 : 1 mode or 1 : 2 mode select.

C1

G5

RESET

G2

LVCMOS input

SSTL_18 input

Asynchronous reset input (active LOW). Resets registers and

disables VREF data and clock.

Chip select inputs (active LOW). Disables D1 to D25^[1]

outputs switching when both inputs are HIGH.

CSR

J2

DCS

H2

[2]

D1 to D25

SSTL_18 input

Data input. Clocked in on the crossing of the rising edge of

CK and the falling edge of CK.

[2]

DODT

DCKE

PAR_IN

The outputs of this register bit will not be suspended by the

DCS and CSR control.

The outputs of this register bit will not be suspended by the

DCS and CSR control.

G1

Parity input. Arrives one clock cycle after the corresponding

data input.

[2]

Q1 to Q25,

Q1A to Q14A,

Q1B to Q14B

1.8 V CMOS

outputs

Data outputs that are suspended by the DCS and CSR

control.^[3]

PPO

A2

1.8 V CMOS

output

Partial parity out. Indicates odd parity of inputs D1 to D25.^[1]

[2]

QCS, QCSA,

QCSB

1.8 V CMOS

output

Data output that will not be suspended by the DCS and CSR

control.

[2]

QODT, QODTA,

QODTB

1.8 V CMOS

output

Data output that will not be suspended by the DCS and CSR

control.

QCKE,

QCKEA,

QCKEB

1.8 V CMOS

output

Data output that will not be suspended by the DCS and CSR

control.

QERR

D2

open-drain

output

Output error bit (active LOW). Generated one clock cycle

after the corresponding data output.

[2]

n.c.

-

Not connected. Ball present but no internal connection to the

die.

[2]

DNU

-

Do not use. Inputs are in standby-equivalent mode and

outputs are driven LOW.

[1] Data inputs = D2, D3, D5, D6, D8 to D25 when C0 = 0 and C1 = 0.

Data inputs = D2, D3, D5, D6, D8 to D14 when C0 = 0 and C1 = 1.

Data inputs = D1 to D6, D8 to D10, D12, D13 when C0 = 1 and C1 = 1.

[2] Depends on conﬁguration. See Figure 4, Figure 5, and Figure 6 for ball number.

SSTUG32866_1

Product data sheet

Rev. 01 — 29 June 2007

7 of 28

SSTUG32866

NXP Semiconductors

1.8 V DDR2-1G conﬁgurable registered buffer with parity

[3] Data outputs = Q2, Q3, Q5, Q6, Q8 to Q25 when C0 = 0 and C1 = 0.

Data outputs = Q2, Q3, Q5, Q6, Q8 to Q14 when C0 = 0 and C1 = 1.

Data outputs = Q1 to Q6, Q8 to Q10, Q12, Q13 when C0 = 1 and C1 = 1.

7. Functional description

The SSTUG32866 is a 25-bit 1 : 1 or 14-bit 1 : 2 conﬁgurable registered buffer with parity,

designed for 1.7 V to 2.0 V V_DDoperation.

All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The

control and reset (RESET) inputs are LVCMOS. All data outputs are 1.8 V CMOS drivers

that have been optimized to drive the DDR2 DIMM load, and meet SSTL_18

speciﬁcations. The error (QERR) output is 1.8 V open-drain driver.

The SSTUG32866 operates from a differential clock (CK and CK). Data are registered at

the crossing of CK going HIGH, and CK going LOW.

The C0 input controls the pinout conﬁguration for the 1 : 2 pinout from A conﬁguration

(when LOW) to B conﬁguration (when HIGH). The C1 input controls the pinout

conﬁguration from 25-bit 1 : 1 (when LOW) to 14-bit 1 : 2 (when HIGH).

The SSTUG32866 accepts a parity bit from the memory controller on its parity bit

(PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs

and indicates whether a parity error has occurred on its open-drain QERR pin

(active LOW). The convention is even parity, that is, valid parity is deﬁned as an even

number of ones across the DIMM-independent data inputs combined with the parity input

bit.

When used as a single device, the C0 and C1 inputs are tied LOW. In this conﬁguration,

parity is checked on the PAR_IN input which arrives one cycle after the input data to which

it applies. The Partial-Parity-Out (PPO) and QERR signals are produced three cycles after

the corresponding data inputs.

When used in pairs, the C0 input of the ﬁrst register is tied LOW and the C0 input of the

second register is tied HIGH. The C1 input of both registers are tied HIGH. Parity, which

arrives one cycle after the data input to which it applies, is checked on the PAR_IN input of

the ﬁrst device. The PPO and QERR signals are produced on the second device three

clock cycles after the corresponding data inputs. The PPO output of the ﬁrst register is

cascaded to the PAR_IN of the second register. The QERR output of the ﬁrst register is

left ﬂoating and the valid error information is latched on the QERR output of the second

register.

If an error occurs and the QERR output is driven LOW, it stays latched LOW for two clock

cycles or until RESET is driven LOW. The DIMM-dependent signals (DCKE, DCS, DODT,

and CSR) are not included in the parity check computation.

The device supports low-power standby operation. When RESET is LOW, the differential

input receivers are disabled, and undriven (ﬂoating) data, clock and reference voltage

(VREF) inputs are allowed. In addition, when RESET is LOW all registers are reset, and

all outputs are forced LOW. The LVCMOS RESET input must always be held at a valid

logic HIGH or LOW level.

SSTUG32866_1

Product data sheet

Rev. 01 — 29 June 2007

8 of 28

SSTUG32866

NXP Semiconductors

1.8 V DDR2-1G conﬁgurable registered buffer with parity

The device also supports low-power active operation by monitoring both system chip

select (DCS and CSR) inputs and will gate the Qn and PPO outputs from changing states

when both DCS and CSR inputs are HIGH. If either DCS or CSR input is LOW, the Qn

and PPO outputs will function normally. The RESET input has priority over the DCS and

CSR control and when driven LOW will force the Qn and PPO outputs LOW, and the

QERR output HIGH. If the DCS control functionality is not desired, then the CSR input can

be hard-wired to ground, in which case, the setup time requirement for DCS would be the

same as for the other Dn data inputs. To control the low-power mode with DCS only, then

the CSR input should be pulled up to V_DDthrough a pull-up resistor.

To ensure deﬁned outputs from the register before a stable clock has been supplied,

RESET must be held in the LOW state during power-up.

In the DDR2 RDIMM application, RESET is speciﬁed to be completely asynchronous with

respect to CK and CK. Therefore, no timing relationship can be guaranteed between the

two. When entering reset, the register will be cleared and the Qn outputs will be driven

LOW quickly, relative to the time to disable the differential input receivers. However, when

coming out of reset, the register will become active quickly, relative to the time to enable

the differential input receivers. As long as the data inputs are LOW, and the clock is stable

during the time from the LOW-to-HIGH transition of RESET until the input receivers are

fully enabled, the design of the SSTUG32866 must ensure that the outputs will remain

LOW, thus ensuring no glitches on the output.

7.1 Function table

Table 4.

Function table (each ﬂip-ﬂop)

L = LOW voltage level; H = HIGH voltage level; X = don’t care; ↑ = LOW-to-HIGH transition; ↓ = HIGH-to-LOW transition.

Inputs

Outputs^[1]

RESET

DCS

CSR

CK

Dn, DODTn,

DCKEn

Qn

QCS

QODT,

QCKE

H

L

↑

↓

L

H

X

L

H

L

H

↓

L

L or H

Q₀

L

Q₀

L

Q₀

L

H

L

↑

↓

L

↑

↓

H

X

L

H

L

H

L

L or H

Q₀

L

Q₀

H

Q₀

L

H

↑

↓

L

↑

L or H

↑

↓

L or H

↓

H

X

L

H

L

Q₀

L

Q₀

H

Q₀

L

H

↑

↓

H

X

H

L or H

Q₀

L

Q₀

L

X or ﬂoating X or ﬂoating X or ﬂoating X or ﬂoating X or ﬂoating

[1] Q₀is the previous state of the associated output.

SSTUG32866_1

Product data sheet

Rev. 01 — 29 June 2007

9 of 28

SSTUG32866

NXP Semiconductors

1.8 V DDR2-1G conﬁgurable registered buffer with parity

Table 5.

Parity and standby function table

L = LOW voltage level; H = HIGH voltage level; X = don’t care; ↑ = LOW-to-HIGH transition; ↓ = HIGH-to-LOW transition.

Inputs

Outputs^[1]

CK

RESET

DCS

CSR

CK

∑ of inputs = H PAR_IN^[2]

PPO^[3]

QERR^[4]

(D1 to D25)

H

L

X

L

↑

↓

even

odd

L

H

↑

↓

L

H

L

↑

↓

even

odd

H

L

↑

↓

H

L

H

X

↑

↓

even

odd

L

H

L

↑

↓

L

↑

↓

even

odd

H

L

H

L

↑

↓

H

L

H

X

PPO₀

L

QERR₀

H

L or H

X

X or ﬂoating X or ﬂoating X or ﬂoating X or ﬂoating

X or ﬂoating

[1] PPO₀is the previous state of output PPO; QERR₀is the previous state of output QERR.

[2] Data inputs = D2, D3, D5, D6, D8 to D25 when C0 = 0 and C1 = 0.

Data inputs = D2, D3, D5, D6, D8 to D14 when C0 = 0 and C1 = 1.

Data inputs = D1 to D6, D8 to D10, D12, D13 when C0 = 1 and C1 = 1.

[3] PAR_IN arrives one clock cycle (C0 = 0), or two clock cycles (C0 = 1), after the data to which it applies.

[4] This condition assumes QERR is HIGH at the crossing of CK going HIGH and CK going LOW. If QERR is LOW, it stays latched LOW for

two clock cycles or until RESET is driven LOW.

8. Limiting values

Table 6.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DD

V_I

Parameter

Conditions

Min

Max

Unit

V

supply voltage

−0.5

−0.5^[1]

+2.5

input voltage

receiver

+2.5^[2]

V_DD+ 0.5^[2]

−50

V

V_O

output voltage

driver

V

I_IK

input clamping current

output clamping current

output current

V_I< 0 V or V_I> V_DD

V_O< 0 V or V_O> V_DD

continuous; 0 V < V_O< V_DD

-

mA

I_OK

±50

I_O

±50

I_DDC

continuous current through

each V_DDor GND pin

±100

T_stg

storage temperature

−65

2

+150

°C

kV

V

V_esd

electrostatic discharge

voltage

Human Body Model (HBM); 1.5 kΩ; 100 pF

Machine Model (MM); 0 Ω; 200 pF

-

200

[1] The input and output negative voltage ratings may be exceeded if the input and output clamping current ratings are observed.

[2] This value is limited to 2.5 V maximum.

SSTUG32866_1

Product data sheet

Rev. 01 — 29 June 2007

10 of 28

SSTUG32866

NXP Semiconductors

1.8 V DDR2-1G conﬁgurable registered buffer with parity

9. Recommended operating conditions

Table 7.

Recommended operating conditions

Symbol Parameter

Conditions

Min

Typ

Max

Unit

V

V_DD

V_ref

V_T

supply voltage

1.7

-

2.0

reference voltage

termination voltage

input voltage

0.49 × V_DD

0.50 × V_DD0.51 × V_DD

V

0

_ref− 0.040

V_ref

V_ref+ 0.040

V

V_I

-

V_DD

-

V

V_IH(AC)

AC HIGH-level input voltage

data (Dn), CSR, and

PAR_IN inputs

V_ref+ 0.250

V

V_IL(AC)

V_IH(DC)

V_IL(DC)

AC LOW-level input voltage

DC HIGH-level input voltage

DC LOW-level input voltage

data (Dn), CSR, and

PAR_IN inputs

-

V

-

_ref− 0.250

V

data (Dn), CSR, and

PAR_IN inputs

V_ref+ 0.125

-

data (Dn), CSR, and

PAR_IN inputs

V

-

_ref− 0.125

[1]

[2]

V_IH

V_IL

HIGH-level input voltage

LOW-level input voltage

RESET, Cn

CK, CK

0.65 × V_DD

-

V

-

0.35 × V_DD

V_ICR

common mode input voltage

range

0.675

1.125

[2]

V_ID

I_OH

I_OL

differential input voltage

HIGH-level output current

LOW-level output current

ambient temperature

CK, CK

600

-

mV

mA

-

−8

8

T_amb

operating in free air

SSTUG32866EC/G

SSTUG32866EC/S

0

-

70

85

°C

[1] The RESET and Cn inputs of the device must be held at valid levels (not ﬂoating) to ensure proper device operation.

[2] The differential inputs must not be ﬂoating, unless RESET is LOW.

SSTUG32866_1

Product data sheet

Rev. 01 — 29 June 2007

11 of 28

SSTUG32866

NXP Semiconductors

1.8 V DDR2-1G conﬁgurable registered buffer with parity

10. Characteristics

Table 8.

Characteristics

At recommended operating conditions (see Table 7); unless otherwise speciﬁed.

Symbol

V_OH

V_OL

I_I

Parameter

Conditions

Min

Typ

Max

-

Unit

V

HIGH-level output voltage

LOW-level output voltage

input current

I_OH= −6 mA; V_DD= 1.7 V

I_OL= 6 mA; V_DD= 1.7 V

all inputs; V_I= V_DDor GND; V_DD= 2.0 V

1.2

-

0.5

±5

2

V

µA

mA

I_DD

supply current

static Standby mode; RESET = GND;

I_O= 0 mA; V_DD= 2.0 V

static Operating mode; RESET = V_DD

I_O= 0 mA; V_DD= 2.0 V;

V_I= V_IH(AC)or V_IL(AC)

;

-

40

-

mA

I_DDD

dynamic operating current per clock only; RESET = V_DD

;

16

µA

MHz

V_I= V_IH(AC)or V_IL(AC); CK and CK

switching at 50 % duty cycle; I_O= 0 mA;

_DD= 1.8 V

V

per each data input, 1 : 1 mode;

RESET = V_DD; V_I= V_IH(AC)or V_IL(AC)

CK and CK switching at 50 % duty

cycle; one data input switching at half

clock frequency, 50 % duty cycle;

I_O= 0 mA; V_DD= 1.8 V

-

11

19

-

µA

;

per each data input, 1 : 2 mode;

RESET = V_DD; V_I= V_IH(AC)or V_IL(AC)

;

CK and CK switching at 50 % duty

cycle; one data input switching at half

clock frequency, 50 % duty cycle;

I_O= 0 mA; V_DD= 1.8 V

C_i

input capacitance

output impedance

data and CSR inputs;

V_I= V_ref± 250 mV; V_DD= 1.8 V

2.5

2

-

3.5

3

pF

CK and CK inputs; V_ICR= 0.9 V;

V

_i(p-p)= 600 mV; V_DD= 1.8 V

RESET input; V_I= V_DDor GND;

_DD= 1.8 V

3

4

V

[1]

Z_o

instantaneous

steady-state

-

15

53

-

Ω

[1] Instantaneous is deﬁned as within < 2 ns following the output data transition edge.

SSTUG32866_1

Product data sheet

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SSTUG32866

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1.8 V DDR2-1G conﬁgurable registered buffer with parity

Table 9.

Timing requirements

At recommended operating conditions (see Table 7), unless otherwise speciﬁed. See Section 11.1.

Symbol Parameter

f_clockclock frequency

t_W

Conditions

Min

Typ

Max

550

-

Unit

MHz

ns

-

pulse width

CK, CK HIGH or LOW

1

[1][2]

[1][3]

t_ACT

t_INACT

t_su

differential inputs active time

differential inputs inactive time

setup time

-

10

15

-

ns

-

ns

DCS before CK↑, CK↓, CSR HIGH;

CSR before CK↑, CK↓, DCS HIGH

0.6

ns

DCS before CK↑, CK↓, CSR LOW

0.5

-

ns

DODT, DCKE and data (Dn) before CK↑,

CK↓

PAR_IN before CK↑, CK↓

0.5

0.4

-

ns

t_h

hold time

DCS, DODT, DCKE and data (Dn) after

CK↑, CK↓

PAR_IN after CK↑, CK↓

0.4

-

ns

[1] This parameter is not necessarily production tested.

[2] VREF must be held at a valid input voltage level and data inputs must be held LOW for a minimum time of t_ACT(max)after RESET is taken

HIGH.

[3] VREF, data and clock inputs must be held at valid levels (not ﬂoating) a minimum time of t_INACT(max)after RESET is taken LOW.

Table 10. Switching characteristics

At recommended operating conditions (see Table 7), unless otherwise speciﬁed. See Section 11.1.

Symbol Parameter

Conditions

Min

550

1.0

Typ

Max

-

Unit

MHz

ns

f_max

maximum input clock frequency

-

[1]

t_PDM

peak propagation delay

single bit switching;

1.4

from CK↑ and CK↓ to Qn

t_PD

propagation delay

LOW-to-HIGH delay

HIGH-to-LOW delay

from CK↑ and CK↓ to PPO

from CK↑ and CK↓ to QERR

from CK↑ and CK↓ to Qn

0.5

1.2

1

-

1.7

3

ns

t_LH

t_HL

2.4

1.5

[1][2]

t_PDMSS

simultaneous switching peak

propagation delay

-

t_PHL

HIGH-to-LOW propagation delay

from RESET↓ to Qn↓

from RESET↓ to PPO↓

from RESET↓ to QERR↑

-

3

ns

t_PLH

LOW-to-HIGH propagation delay

[1] Includes 350 ps of test load transmission line delay.

[2] This parameter is not necessarily production tested.

Table 11. Data output edge rates

At recommended operating conditions (see Table 7), unless otherwise speciﬁed. See Section 11.2.

Symbol

dV/dt_r

dV/dt_f

dV/dt_∆

Parameter

Conditions

Min

Typ

Max

Unit

rising edge slew rate

falling edge slew rate

from 20 % to 80 %

from 80 % to 20 %

1

-

4

1

V/ns

absolute difference between dV/dt_r from 20 % or 80 %

and dV/dt_f

to 80 % or 20 %

SSTUG32866_1

Product data sheet

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13 of 28

SSTUG32866

NXP Semiconductors

1.8 V DDR2-1G conﬁgurable registered buffer with parity

10.1 Timing diagrams

RESET

DCS

CSR

CK

m

m + 1

m + 2

m + 3

m + 4

CK

t

h

su

D1

to

D25

t

PD

CK to Q

Q1

to

Q25

t

h

su

PAR_IN

PPO

t

PD

CK to PPO

t

PD

CK to QERR

QERR

002aaa655

Fig 7. Timing diagram for SSTUG32866 used as a single device; C0 = 0, C1 = 0

SSTUG32866_1

Product data sheet

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14 of 28

SSTUG32866

NXP Semiconductors

1.8 V DDR2-1G conﬁgurable registered buffer with parity

RESET

DCS

CSR

CK

m

m + 1

m + 2

m + 3

m + 4

CK

t

h

su

D1

to

D14

t

PD

CK to Q

Q1

to

Q14

t

h

su

PAR_IN

PPO

t

PD

CK to PPO

t

PD

CK to QERR

QERR

(not used)

002aaa656

Fig 8. Timing diagram for the ﬁrst SSTUG32866 (1 : 2 Register A conﬁguration) device used in pair; C0 = 0,

C1 = 1

SSTUG32866_1

Product data sheet

Rev. 01 — 29 June 2007

15 of 28

SSTUG32866

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1.8 V DDR2-1G conﬁgurable registered buffer with parity

RESET

DCS

CSR

CK

m

m + 1

m + 2

m + 3

m + 4

CK

t

h

su

D1

to

D14

t

PD

CK to Q

Q1

to

Q14

t

h

su

(1)

PAR_IN

t

PD

CK to PPO

PPO

(not used)

t

PD

CK to QERR

QERR

002aaa657

(1) PAR_IN is driven from PPO of the ﬁrst SSTUG32866 device.

Fig 9. Timing diagram for the second SSTUG32866 (1 : 2 Register B conﬁguration) device used in pair;

C0 = 1, C1 = 1

SSTUG32866_1

Product data sheet

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SSTUG32866

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1.8 V DDR2-1G conﬁgurable registered buffer with parity

11. Test information

11.1 Parameter measurement information for data output load circuit

V_DD= 1.8 V ± 0.1 V.

All input pulses are supplied by generators having the following characteristics:

PRR ≤ 10 MHz; Z_o= 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise speciﬁed.

The outputs are measured one at a time with one transition per measurement.

V

DD

DUT

delay = 350 ps

= 50 Ω

R

= 1000 Ω

L

50 Ω

Z

o

CK

CK inputs

OUT

(1)

= 30 pF

C

L

R

L

test point

R

L

= 100 Ω

test point

002aaa371

(1) C_Lincludes probe and jig capacitance.

Fig 10. Load circuit, data output measurements

LVCMOS

V

DD

0.5V

RESET

DD

0 V

t

ACT

INACT

90 %

(1)

DD

I

10 %

002aaa372

(1) I_DDtested with clock and data inputs held at V_DDor GND, and I_O= 0 mA.

Fig 11. Voltage and current waveforms; inputs active and inactive times

t

W

V

IH

IL

V

input

V

ICR

ID

ICR

002aaa373

V_ID= 600 mV.

V_IH= V_ref+ 250 mV (AC voltage levels) for differential inputs. V_IH= V_DDfor LVCMOS inputs.

V_IL= V_ref− 250 mV (AC voltage levels) for differential inputs. V_IL= GND for LVCMOS inputs.

Fig 12. Voltage waveforms; pulse duration

SSTUG32866_1

Product data sheet

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SSTUG32866

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1.8 V DDR2-1G conﬁgurable registered buffer with parity

CK

V

ICR

ID

CK

t

h

su

V

IH

IL

input

V

ref

V

ref

002aaa374

V_ID= 600 mV.

V_ref= 0.5V_DD

.

V_IH= V_ref+ 250 mV (AC voltage levels) for differential inputs. V_IH= V_DDfor LVCMOS inputs.

V_IL= V_ref− 250 mV (AC voltage levels) for differential inputs. V_IL= GND for LVCMOS inputs.

Fig 13. Voltage waveforms; setup and hold times

CK

V

i(p-p)

ICR

CK

t

PHL

PLH

V

OH

OL

V

output

T

002aaa375

t_PLHand t_PHLare the same as t_PD

.

Fig 14. Voltage waveforms; propagation delay times (clock to output)

LVCMOS

V

IH

RESET

0.5V

DD

IL

t

PHL

OH

OL

output

V

T

002aaa376

t_PLHand t_PHLare the same as t_PD

.

V_IH= V_ref+ 250 mV (AC voltage levels) for differential inputs. V_IH= V_DDfor LVCMOS inputs.

V_IL= V_ref− 250 mV (AC voltage levels) for differential inputs. V_IL= GND for LVCMOS inputs.

Fig 15. Voltage waveforms; propagation delay times (reset to output)

SSTUG32866_1

Product data sheet

Rev. 01 — 29 June 2007

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SSTUG32866

NXP Semiconductors

1.8 V DDR2-1G conﬁgurable registered buffer with parity

11.2 Data output slew rate measurement information

V_DD= 1.8 V ± 0.1 V.

All input pulses are supplied by generators having the following characteristics:

PRR ≤ 10 MHz; Z_o= 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise speciﬁed.

V

DD

R

DUT

= 50 Ω

L

OUT

test point

002aaa377

(1)

= 10 pF

C

L

(1) C_Lincludes probe and jig capacitance.

Fig 16. Load circuit, HIGH-to-LOW slew measurement

output

V

OH

80 %

dv_f

20 %

V

OL

dt_f

002aaa378

Fig 17. Voltage waveforms, HIGH-to-LOW slew rate measurement

DUT

OUT

test point

(1)

= 10 pF

C

L

R

L

= 50 Ω

002aaa379

(1) C_Lincludes probe and jig capacitance.

Fig 18. Load circuit, LOW-to-HIGH slew measurement

dt_r

V

OH

80 %

dv_r

20 %

output

OL

002aaa380

Fig 19. Voltage waveforms, LOW-to-HIGH slew rate measurement

SSTUG32866_1

Product data sheet

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19 of 28

SSTUG32866

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1.8 V DDR2-1G conﬁgurable registered buffer with parity

11.3 Error output load circuit and voltage measurement information

V_DD= 1.8 V ± 0.1 V.

All input pulses are supplied by generators having the following characteristics:

PRR ≤ 10 MHz; Z_o= 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise speciﬁed.

V

DD

R

DUT

= 1 kΩ

L

OUT

test point

002aaa500

(1)

= 10 pF

C

L

(1) C_Lincludes probe and jig capacitance.

Fig 20. Load circuit, error output measurements

LVCMOS

V

DD

RESET

0.5V

DD

0 V

t

PLH

V

OH

output

waveform 2

0.15 V

0 V

002aaa501

Fig 21. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to

RESET input.

timing

inputs

V

i(p-p)

V

ICR

t

HL

V

DD

OL

output

waveform 1

0.5V

DD

002aaa502

Fig 22. Voltage waveforms, open-drain output HIGH-to-LOW transition time with respect

to clock inputs

SSTUG32866_1

Product data sheet

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20 of 28

SSTUG32866

NXP Semiconductors

1.8 V DDR2-1G conﬁgurable registered buffer with parity

timing

inputs

V

i(p-p)

V

ICR

t

LH

V

OH

output

waveform 2

0.15 V

0 V

002aaa503

Fig 23. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to

clock inputs

11.4 Partial parity out load circuit and voltage measurement information

V_DD= 1.8 V ± 0.1 V.

All input pulses are supplied by generators having the following characteristics:

PRR ≤ 10 MHz; Z_o= 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise speciﬁed.

DUT

OUT

test point

(1)

= 5 pF

C

L

R

L

= 1 kΩ

002aaa654

(1) C_Lincludes probe and jig capacitance.

Fig 24. Partial parity out load circuit

CK

V

i(p-p)

ICR

CK

t

PHL

PLH

V

OH

OL

V

output

T

002aaa375

V_T= 0.5V_DD

.

t_PLHand t_PHLare the same as t_PD

.

V_i(p-p)= 600 mV.

Fig 25. Partial parity out voltage waveforms; propagation delay times with respect to clock

inputs

SSTUG32866_1

Product data sheet

Rev. 01 — 29 June 2007

21 of 28

SSTUG32866

NXP Semiconductors

1.8 V DDR2-1G conﬁgurable registered buffer with parity

LVCMOS

V

IH

RESET

output

0.5V

DD

IL

t

PHL

OH

OL

V

T

002aaa376

V_T= 0.5V_DD

.

t_PLHand t_PHLare the same as t_PD

.

V_IH= V_ref+ 250 mV (AC voltage levels) for differential inputs. V_IH= V_DDfor LVCMOS inputs.

V_IL= V_ref− 250 mV (AC voltage levels) for differential inputs. V_IL= GND for LVCMOS inputs.

Fig 26. Partial parity out voltage waveforms; propagation delay times with respect to

RESET input

SSTUG32866_1

Product data sheet

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22 of 28

SSTUG32866

NXP Semiconductors

1.8 V DDR2-1G conﬁgurable registered buffer with parity

12. Package outline

LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm SOT536-1

B

A

D

ball A1

index area

A

2

A

E

A

1

detail X

e

1

C

1/2 e

y

v M

w M

C

A B

C

1

e

b

T

R

P

N

e

M

L

K

J

H

G

F

e

2

1/2 e

E

D

C

B

A

ball A1

index area

1

2

3

4

5

6

X

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

b

e

v

w

y

1

D

E

1

2

1

2

max.

0.41

0.31

1.2

0.9

0.51

0.41

5.6

5.4

13.6

13.4

mm

1.5

4

12

0.1

0.2

0.8

0.15

0.1

REFERENCES

JEDEC JEITA

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

00-03-04

03-02-05

SOT536-1

Fig 27. Package outline SOT536-1 (LFBGA96)

SSTUG32866_1

Product data sheet

Rev. 01 — 29 June 2007

23 of 28

SSTUG32866

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1.8 V DDR2-1G conﬁgurable registered buffer with parity

13. Soldering

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

13.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

13.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus PbSn soldering

13.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

SSTUG32866_1

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24 of 28

SSTUG32866

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1.8 V DDR2-1G conﬁgurable registered buffer with parity

13.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 28) than a PbSn process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 12 and 13

Table 12. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 13. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 28.

SSTUG32866_1

Product data sheet

Rev. 01 — 29 June 2007

25 of 28

SSTUG32866

NXP Semiconductors

1.8 V DDR2-1G conﬁgurable registered buffer with parity

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 28. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

14. Abbreviations

Table 14. Abbreviations

Acronym

CMOS

DDR

Description

Complementary Metal Oxide Semiconductor

Double Data Rate

DIMM

LVCMOS

PPO

Dual In-line Memory Module

Low Voltage Complementary Metal Oxide Semiconductor

Partial-Parity-Out

PRR

Pulse Repetition Rate

RDIMM

SSTL

Registered Dual In-line Memory Module

Stub Series Terminated Logic

15. Revision history

Table 15. Revision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

SSTUG32866_1

20070629

Product data sheet

-

SSTUG32866_1

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16. Legal information

16.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of a NXP Semiconductors product can reasonably be expected to

16.2 Deﬁnitions

result in personal injury, death or severe property or environmental damage.

NXP Semiconductors accepts no liability for inclusion and/or use of NXP

Semiconductors products in such equipment or applications and therefore

such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

16.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

17. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

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SSTUG32866

NXP Semiconductors

1.8 V DDR2-1G conﬁgurable registered buffer with parity

18. Contents

1

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2

3

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3

4

4.1

5

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7

7

7.1

8

Functional description . . . . . . . . . . . . . . . . . . . 8

Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 10

Recommended operating conditions. . . . . . . 11

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 12

Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 14

9

10

10.1

11

11.1

Test information. . . . . . . . . . . . . . . . . . . . . . . . 17

Parameter measurement information for

data output load circuit . . . . . . . . . . . . . . . . . . 17

Data output slew rate measurement

information . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Error output load circuit and voltage

measurement information. . . . . . . . . . . . . . . . 20

Partial parity out load circuit and voltage

11.2

11.3

11.4

measurement information. . . . . . . . . . . . . . . . 21

12

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23

13

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Introduction to soldering . . . . . . . . . . . . . . . . . 24

Wave and reﬂow soldering . . . . . . . . . . . . . . . 24

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 24

Reﬂow soldering . . . . . . . . . . . . . . . . . . . . . . . 25

13.1

13.2

13.3

13.4

14

15

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 26

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 26

16

Legal information. . . . . . . . . . . . . . . . . . . . . . . 27

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 27

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 27

16.1

16.2

16.3

16.4

17

18

Contact information. . . . . . . . . . . . . . . . . . . . . 27

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 29 June 2007

Document identifier: SSTUG32866_1


型号：	SSTUG32866EC/S,518
厂家：	NXP
描述：	SSTUG32866 - 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applications BGA 96-Pin 双倍数据速率逻辑集成电路触发器
文件：	总28页 (文件大小：151K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SSTUG32866EC/S,518 [NXP]

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