SSTUM32865ES_技术文档

SSTUM32865

1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-800

RDIMM applications

Rev. 01 — 19 September 2007

Product data sheet

1. General description

The SSTUM32865 is a 1.8 V 28-bit 1 : 2 register speciﬁcally designed for use on two rank

by four (2R × 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It

is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the

functionality of the normally required two registers in a single package, thereby freeing up

board real-estate and facilitating routing to accommodate high-density Dual In-line

Memory Module (DIMM) designs.

The SSTUM32865 also integrates a parity function, which accepts a parity bit from the

memory controller, compares it with the data received on the D-inputs and indicates

whether a parity error has occurred on its open-drain PTYERR pin (active LOW).

It further offers added features over the JEDEC standard register in that it is permanently

conﬁgured for high output drive strength. This allows use in high density designs with

heavier than normal net loading conditions. Furthermore, the SSTUM32865 features two

additional chip select inputs, which allow more versatile enabling and disabling in densely

populated memory modules. Both added features (drive strength and chip selects) are

fully backward compatible to the JEDEC standard register.

The SSTUM32865 is packaged in a 160-ball, 12 × 18 grid, 0.65 mm ball pitch, thin proﬁle

ﬁne-pitch ball grid array (TFBGA) package, which, while requiring a minimum

9 mm × 13 mm of board space, allows for adequate signal routing and escape using

conventional card technology.

2. Features

I 28-bit data register supporting DDR2

I Fully compliant to JEDEC standard for SSTUB32865

I Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two

JEDEC-standard DDR2 registers (that is, 2 × SSTUB32864 or 2 × SSTUB32866)

I Parity checking function across 22 input data bits

I Parity out signal

I Controlled multi-impedance output impedance drivers enable optimal signal integrity

and speed

I Meets or exceeds SSTUB32865 JEDEC standard speed performance

I Supports up to 450 MHz clock frequency of operation

I Permanently conﬁgured for high output drive

I Optimized pinout for high-density DDR2 module design

I Chip-selects minimize power consumption by gating data outputs from changing state

I Two additional chip select inputs allow optional ﬂexible enabling and disabling

SSTUM32865

NXP Semiconductors

1.8 V DDR2-800 registered buffer with parity

I Supports Stub Series Terminated Logic SSTL_18 data inputs

I Differential clock (CK and CK) inputs

I Supports LVCMOS switching levels on the control and RESET inputs

I Single 1.8 V supply operation (1.7 V to 2.0 V)

I Available in 160-ball 9 mm × 13 mm, 0.65 mm ball pitch TFBGA package

3. Applications

I 400 MT/s to 800 MT/s high-density (for example, 2 rank by 4) DDR2 registered DIMMs

I DDR2 Registered DIMMs (RDIMM) desiring parity checking functionality

4. Ordering information

Table 1.

Ordering information

Solder process

Type number

Package

Name

Description

Version

SSTUM32865ET/G Pb-free (SnAgCu solder ball TFBGA160 plastic thin ﬁne-pitch ball grid array package; SOT802-2

compound) 160 balls; body 9 × 13 × 0.7 mm

SSTUM32865ET/S Pb-free (SnAgCu solder ball TFBGA160 plastic thin ﬁne-pitch ball grid array package; SOT802-2

compound)

160 balls; body 9 × 13 × 0.7 mm

4.1 Ordering options

Table 2.

Ordering options

Type number

SSTUM32865ET/G

SSTUM32865ET/S

Topside mark

Temperature range

SSTUM32865ET

SSTUM32865ETS

T_amb= 0 °C to +70 °C

T_amb= 0 °C to +85 °C

SSTUM32865_1

Product data sheet

Rev. 01 — 19 September 2007

2 of 28

SSTUM32865

NXP Semiconductors

1.8 V DDR2-800 registered buffer with parity

5. Functional diagram

(CS ACTIVE)

VREF

SSTUM32865

PARITY

GENERATOR

AND

CHECKER

D

Q

PARIN

22

PTYERR

R

Q0A

D

R

D0

Q0B

Q21A

Q21B

D

R

D21

QCS0A

QCS0B

DCS0

D

R

CSGATEEN

DCS1

QCS1A

QCS1B

D

R

DCS2

DCS3

QCKE0A,

QCKE1A

DCKE0,

2

D

R

Q

DCKE1

QCKE0B,

QCKE1B

QODT0A,

QODT1A

DODT0,

2

DODT1

D

R

QODT0B,

QODT1B

RESET

CK

002aac647

Fig 1. Functional diagram of SSTUM32865

SSTUM32865_1

Product data sheet

Rev. 01 — 19 September 2007

3 of 28

SSTUM32865

NXP Semiconductors

1.8 V DDR2-800 registered buffer with parity

6. Pinning information

6.1 Pinning

SSTUM32865ET/G

SSTUM32865ET/S

ball A1

index area

2

4

6

8

10 12

9 11

1

3

5

7

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

002aac648

Transparent top view

Fig 2. Pin conﬁguration for TFBGA160

SSTUM32865_1

Product data sheet

Rev. 01 — 19 September 2007

4 of 28

SSTUM32865

NXP Semiconductors

1.8 V DDR2-800 registered buffer with parity

1

VREF

D1

2

n.c.

3

4

5

6

7

8

9

10

11

12

A

B

C

D

E

F

PARIN

n.c.

QCKE1A QCKE0A

QCKE1B QCKE0B

Q21A

Q21B

Q19A

Q19B

Q18A

Q18B

Q17B

Q17A

D2

QODT0B QODT0A

QODT1B QODT1A

D3

D4

D6

D5

VDDL

DCS2

GND

VDDL

GND

VDDL

n.c.

GND

Q20B

Q16B

Q1B

Q20A

Q16A

Q1A

D7

D8

VDDL

VDDR

D11

D9

VDDR

GND

VDDR

GND

D18

D12

D15

DCS0

DCS1

D14

D10

D16

D21

D20

DODT0

DCKE1

MCL

Q2B

Q2A

G

H

J

CSGATEEN

CK

Q5B

Q5A

VDDR

GND

VDDR

GND

QCS0B

QCS1B

Q6B

QCS0A

QCS1A

Q6A

CK

DCS3

GND

K

L

RESET

D0

VDDR

GND

VDDR

GND

Q10B

Q9B

Q10A

Q9A

M

N

P

R

T

D17

VDDL

GND

VDDR

GND

VDDR

GND

D19

VDDL

VDDR

GND

Q11B

Q15B

Q14B

Q0B

Q11A

Q15A

Q14A

Q8B

D13

GND

DODT1

DCKE0

VREF

MCL

PTYERR

n.c.

MCH

Q3B

Q3A

Q12B

Q12A

Q7B

Q7A

Q4B

Q4A

Q13B

Q13A

U

V

Q0A

Q8A

002aac650

160-ball, 12 × 18 grid; top view.

An empty cell indicates no ball is populated at that grid point.

n.c. denotes a no-connect (ball present but not connected to the die).

MCL denotes a pin that must be connected LOW.

MCH denotes a pin that must be connected HIGH.

Fig 3. Ball mapping

SSTUM32865_1

Product data sheet

Rev. 01 — 19 September 2007

5 of 28

SSTUM32865

NXP Semiconductors

1.8 V DDR2-800 registered buffer with parity

6.2 Pin description

Table 3.

Pin description

Symbol

Type

Description

Ungated inputs

DCKE0, DCKE1

DODT0, DODT1

U1, U2

T2, T1

SSTL_18

DRAM function pins not associated with Chip Select.

DRAM inputs, re-driven only when Chip Select is LOW.

Chip Select gated inputs

D0 to D21

M1, B1, B2, C1, C2, D2, D1, SSTL_18

E1, E2, F2, M2, F1, G2, R1,

L2, H2, N2, N1, G1, P1, R2,

P2

Chip Select inputs

DCS0, DCS1,

DCS2, DCS3^[1]

J2, K2, H4, K4

SSTL_18

DRAM Chip Select signals. These pins initiate DRAM

address/command decodes, and as such at least one will

be LOW when a valid address/command is present. The

register can be programmed to re-drive all D-inputs only

(CSGATEEN = HIGH) when at least one Chip Select

input is LOW. DCS2 and DCS3 are not re-driven and can

be left open-circuit to default HIGH by means of its

internal pull-up resistors.

Re-driven outputs

Q0A to Q21A

V11, F12, G12, V6, V9, H12, SSTL_18

L12, V8, V12, N12, M12,

P12, V7, V10, T12, R12,

Outputs of the register, valid after the speciﬁed clock

count and immediately following a rising edge of the

clock.

E12, A12, A10, A9, D12, A8

Q0B to Q21B

U11, F11, G11, U6, U9,

H11, L11, U8, U12, N11,

M11, P11, U7, U10, T11,

R11, E11, A11, B10, B9,

D11, B8

QCS0A, QDS1A,

QCS0B, QCS1B

J12, K12, J11, K11

QCKE0A, QCKE1A, A7, A6, B7, B6

QCKE0B, QCKE1B

QODT0A, QODT1A, B12, C12, B11, C11

QODT0B, QODT1B

Parity input

PARIN

A3

U4

SSTL_18

Parity input for the D0 to D21 inputs. Arrives one clock

cycle after the corresponding data input.

Parity error

PTYERR

open-drain When LOW, this output indicates that a parity error was

identiﬁed associated with the address and/or command

inputs. PTYERR will be active for two clock cycles, and

delayed by an additional clock cycle for compatibility with

ﬁnal parity out timing on the industry-standard DDR2

register with parity (in JEDEC deﬁnition).

SSTUM32865_1

Product data sheet

Rev. 01 — 19 September 2007

6 of 28

SSTUM32865

NXP Semiconductors

1.8 V DDR2-800 registered buffer with parity

Table 3.

Pin description …continued

Symbol

Type

Description

Program inputs

CSGATEEN

H1

1.8 V

LVCMOS

Chip Select Gate Enable. When HIGH, the D0 to D21

inputs will be latched only when at least one Chip Select

with weak input is LOW during the rising edge of the clock. When

pull-up

LOW, the D0 to D21 inputs will be latched and redriven

on every rising edge of the clock.

Clock inputs

CK, CK

J1, K1

SSTL_18

Differential master clock input pair to the register. The

register operation is triggered by a rising edge on the

positive clock input (CK).

Miscellaneous inputs

MCL

U3, V2, V3

U5, V5

L1

Must be connected to a logic LOW.

Must be connected to a logic HIGH.

MCH

RESET

1.8 V

LVCMOS

Asynchronous reset input. When LOW, it causes a reset

of the internal latches, thereby forcing the outputs LOW.

with weak RESET also resets the PTYERR signal.

pull-up

VREF

VDDL

VDDR

GND

A1, V1

0.9 V

nominal

Input reference voltage for the SSTL_18 inputs. Two pins

(internally tied together) are used for increased reliability.

D4, E4, E6, F4, G4, K5, N4,

N5, P5, P6, R5, R6

Power supply voltage.

Ground.

E7, F8, F9, G8, G9, J8, J9,

L8, L9, N8, N9, P7, P8

D5, D8, D9, E5, E8, E9, F5,

G5, H5, H8, H9, J4, J5, K8,

K9, L4, L5, M4, M5, M8, M9,

P4, P9, R4, R7, R8, R9

n.c.

A2, A4, A5, B3, B4, B5, D6,

D7, V4

Ball present but not connected to die.

[1] If application does not require DCS2 and DCS3, it is allowed to connect H4 and K4 to V_DD

.

SSTUM32865_1

Product data sheet

Rev. 01 — 19 September 2007

7 of 28

SSTUM32865

NXP Semiconductors

1.8 V DDR2-800 registered buffer with parity

7. Functional description

7.1 Function table

Table 4.

Function table (each ﬂip-ﬂop)

Inputs

RESET DCS0^[2]DCS1^[2]CSGATEEN

Outputs^[1]

CK

Dn, DODTn, DCKEn Qn QCS0 QCS1 QODTn,

QCKEn

H

L

X

↑

↓

L

H

L

H

X

↑

↓

H

L

X

L or H

X

Q₀

L

Q₀

L

Q₀

H

Q₀

L

H

L

X

↑

↓

L

X

↑

↓

H

L

H

L

X

L or H

X

Q₀

L

Q₀

H

Q₀

L

Q₀

L

H

X or

X

↑

↓

L

X

↑

L or H

↑

↓

L or H

↓

H

L

H

L

X

Q₀

L

Q₀

H

Q₀

H

Q₀

L

H

X or

L

↑

↓

H

L

L or H

↑

L or H

↓

X

Q₀

L

Q₀

H

Q₀

H

Q₀

L

H

L

H

↑

↓

H

X

H

L or H

X or

L or H

X or

Q₀

L

Q₀

L

Q₀

L

X or ﬂoating

ﬂoating ﬂoating

[1] Q₀is the previous state of the associated output.

[2] DCS2 and DCS3 operate identically to DCS0 and DCS1, except they do not have corresponding re-driven (QCS) outputs.

Table 5.

RESET

Parity and standby function table

Inputs

CK

Output

PTYERR^[3][4]

DCS0^[1]

DCS1^[1]

CK

∑ of inputs = H

PARIN^[2]

(D0 to D21)

H

L

H

L

↑

↓

even

odd

L

H

↑

↓

L

↑

↓

even

odd

H

L

↑

↓

H

X

↑

↓

even

odd

L

H

L

↑

↓

L

↑

↓

even

odd

H

L

↑

↓

H

X

PTYERR₀

H

L or H

X

X or ﬂoating X or ﬂoating X or ﬂoating X or ﬂoating

X or ﬂoating

SSTUM32865_1

Product data sheet

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SSTUM32865

NXP Semiconductors

1.8 V DDR2-800 registered buffer with parity

[1] DCS2 and DCS3 operate identically to DCS0 and DCS1 with regard to the parity function.

[2] PARIN arrives one clock cycle after the data to which it applies. All Dn inputs must be driven to a known state for parity to be calculated

correctly.

[3] This condition assumes PTYERR is HIGH at the crossing of CK going HIGH and CK going LOW. If PTYERR is LOW, it stays latched

LOW for two clock cycles or until RESET is driven LOW. CSGATEEN is ‘don’t care’ for PTYERR.

[4] PTYERR₀is the previous state of output PTYERR.

7.2 Functional information

This 28-bit 1 : 2 registered buffer with parity is designed for 1.7 V to 2.0 V V_DDoperation.

All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The

control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized

to drive the DDR2 DIMM load.

The SSTUM32865 operates from a differential clock (CK and CK). Data are registered at

the crossing of CK going HIGH, and CK going LOW.

The device supports low-power standby operation. When the reset input (RESET) is LOW,

the differential input receivers are disabled, and undriven (ﬂoating) data, clock and

reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW all

registers are reset, and all outputs except PTYERR are forced LOW. The LVCMOS

RESET input must always be held at a valid logic HIGH or LOW level.

To ensure deﬁned outputs from the register before a stable clock has been supplied,

RESET must be held in the LOW state during power-up.

In the DDR2 RDIMM application, RESET is speciﬁed to be completely asynchronous with

respect to CK and CK. Therefore, no timing relationship can be guaranteed between the

two. When entering reset, the register will be cleared and the data outputs will be driven

LOW quickly, relative to the time to disable the differential input receivers. However, when

coming out of reset, the register will become active quickly, relative to the time to enable

the differential input receivers. As long as the data inputs are LOW, and the clock is stable

during the time from the LOW-to-HIGH transition of RESET until the input receivers are

fully enabled, the design of the SSTUM32865 ensures that the outputs remain LOW, thus

ensuring no glitches on the output.

The device monitors DCS0, DCS1, DCS2 and DCS3 inputs and will gate the Qn outputs

from changing states when all DCSn inputs are HIGH. If DCSn input is LOW, the Qn

outputs will function normally. The RESET input has priority over the DCSn control and

will force the Qn outputs LOW and the PTYERR output HIGH. If the DCSn-control

functionality is not desired, then the CSGATEEN input can be hardwired to ground, in

which case, the set-up time requirement for DCSn would be the same as for the other Dn

data inputs.

The SSTUM32865 includes a parity checking function. The SSTUM32865 accepts a

parity bit from the memory controller at its input pin PARIN, compares it with the data

received on the Dn inputs (with either DCSn inputs active) and indicates whether a parity

error has occurred on its open-drain PTYERR pin (active LOW).

SSTUM32865_1

Product data sheet

Rev. 01 — 19 September 2007

9 of 28

SSTUM32865

NXP Semiconductors

1.8 V DDR2-800 registered buffer with parity

7.3 Functional differences to SSTU32864

The SSTUM32865 for its basic register functionality, signal deﬁnition and performance is

based upon the industry-standard SSTU32864, but provides key operational features

which differ (at least in part) from the industry-standard register in the following aspects:

7.3.1 Chip Select (CS) gating of key inputs (DCS0, DCS1, DCS2, DCS3,

CSGATEEN)

As a means to reduce device power, the internal latches will only be updated when one or

more of the CS inputs are active (LOW) and CSGATEEN HIGH at the rising edge of the

clock. The 22 ‘Chip-Select-gated’ input signals associated with this function include

addresses (ADDR0 to ADDR15, BA0 to BA2), and RAS, CAS, WE, with the remaining

signals (CS, CKE, ODT) continuously re-driven at the rising edge of every clock as they

are independent of CS. The CS gating function can be disabled by tying CSGATEEN

LOW, enabling all internal latches to be updated on every rising edge of the clock.

Table 6.

Mode

Chip Select gating mode

Signal name

CSGATEEN

HIGH

Description

Gating

Registers only re-drive signals to the DRAMs when

Chip Select inputs are LOW.

Non-gating

CSGATEEN

LOW

Registers always re-drive signals on every clock cycle,

independent of the state of the Chip Select inputs.

7.3.2 Parity error checking and reporting

The SSTUM32865 incorporates a parity function, whereby the signal received on input pin

PARIN is received as parity to the register, one clock cycle later than the CS-gated inputs.

The received parity bit is then compared to the parity calculated across these same inputs

by the register parity logic to verify that the information has not been corrupted. The 22

CS-gated input signals will be latched and re-driven on the ﬁrst clock, and any error will be

reported one clock cycle later via the PTYERR output pin (driven LOW for two consecutive

clock cycles). PTYERR is an open-drain output, allowing multiple modules to share a

common signal pin for reporting the occurrence of a parity error during a valid command

cycle (coincident with the re-driven signals). This output is driven LOW for two consecutive

clock cycles to allow the memory controller sufﬁcient time to sense and capture the error

even. A LOW state on PTYERR indicates that a parity error has occurred.

7.3.3 Reset (RESET)

Similar to the RESET pin on the industry-standard SSTU32864, this pin is used to clear all

internal latches and all outputs will be driven LOW quickly except the PTYERR output,

which will be ﬂoated (and will normally default HIGH by their external pull-up).

7.3.4 Power-up sequence

The reset function for the SSTUM32865 is similar to that of the SSTU32864 except that

the PTYERR signal is also cleared and will be held clear (HIGH) for three consecutive

clock cycles.

SSTUM32865_1

Product data sheet

Rev. 01 — 19 September 2007

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SSTUM32865

NXP Semiconductors

1.8 V DDR2-800 registered buffer with parity

RESET

DCSn

CK

m

m + 1

m + 2

m + 3

m + 4

CK

t

ACT

t

h

su

(1)

Dn

t

, t

PDM PDMSS

CK to Q

Qn

t

h

su

PARIN

t

, t

PHL PLH

PHL

CK to PTYERR

PTYERR

002aaa983

HIGH, LOW, or Don't care

HIGH or LOW

(1) After RESET is switched from LOW to HIGH, all data and PARIN input signals must be set and held LOW for a minimum

time of t_ACT(max)to avoid false error.

Fig 4. RESET switches from LOW to HIGH

SSTUM32865_1

Product data sheet

Rev. 01 — 19 September 2007

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SSTUM32865

NXP Semiconductors

1.8 V DDR2-800 registered buffer with parity

RESET

DCSn

CK

m

m + 1

m + 2

m + 3

m + 4

CK

t

h

su

(1)

Dn

t

, t

PDM PDMSS

CK to Q

Qn

t

su

t

h

PARIN

t

, t

PHL PLH

CK to PTYERR

PTYERR

002aaa984

Output signal is dependent

on the prior unknown event

Unknown input event

HIGH or LOW

Fig 5. RESET being held HIGH

SSTUM32865_1

Product data sheet

Rev. 01 — 19 September 2007

12 of 28

SSTUM32865

NXP Semiconductors

1.8 V DDR2-800 registered buffer with parity

RESET

DCSn

t

INACT

(1)

CK

(1)

CK

(1)

Dn

t

PHL

RESET to Q

Qn

(1)

PARIN

t

PLH

RESET to PTYERR

PTYERR

002aac649

HIGH, LOW, or Don't care

HIGH or LOW

(1) After RESET is switched from HIGH to LOW, all data and clock input signals must be set and held at valid logic levels (not

ﬂoating) for a minimum time of t_INACT(max)

.

Fig 6. RESET switches from HIGH to LOW

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Product data sheet

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SSTUM32865

NXP Semiconductors

1.8 V DDR2-800 registered buffer with parity

22

Dn

QnA

QnB

D

Q

D

PTYERR

D

LATCHING AND

RESET FUNCTION

(1)

PARIN

CLOCK

002aaa417

(1) This function holds the error for two cycles. For details, see Section 7 “Functional description” and Figure 4 “RESET

switches from LOW to HIGH”.

Fig 7. Parity logic diagram

SSTUM32865_1

Product data sheet

Rev. 01 — 19 September 2007

14 of 28

SSTUM32865

NXP Semiconductors

1.8 V DDR2-800 registered buffer with parity

8. Limiting values

Table 7.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DD

V_I

Parameter

Conditions

Min

Max

Unit

V

supply voltage

−0.5

+2.5

[1]

input voltage

receiver

−0.5

+2.5

V

V_O

output voltage

driver

−0.5

V_DD+ 0.5

−50

V

I_IK

input clamping current

output clamping current

output current

V_I< 0 V or V_I> V_DD

V_O< 0 V or V_O> V_DD

continuous; 0 V < V_O< V_DD

-

mA

I_OK

±50

I_O

±50

I_DDC

continuous current through

each V_DD^[2]or GND pin

±100

T_stg

storage temperature

−65

2

+150

°C

kV

V

V_esd

electrostatic discharge

voltage

Human Body Model (HBM); 1.5 kΩ; 100 pF

Machine Model (MM); 0 Ω; 200 pF

-

150

[1] The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

[2] Pins VDDL or VDDR.

9. Recommended operating conditions

Table 8.

Recommended operating conditions

Symbol Parameter

Conditions

Min

Typ

Max

Unit

V_DD

supply voltage

1.7

-

2.0

V

V_ref

reference voltage

0.49 × V_DD

0.50 × V_DD0.51 × V_DD

V_T

termination voltage

V

_ref− 0.040 V_ref

V_ref+ 0.040

V_I

input voltage

0

-

V_DD

-

[1]

[2]

V_IH(AC)

V_IL(AC)

V_IH(DC)

V_IL(DC)

V_IH

AC HIGH-level input voltage

AC LOW-level input voltage

DC HIGH-level input voltage

DC LOW-level input voltage

HIGH-level input voltage

LOW-level input voltage

data inputs (Dn)

RESET

V_ref+ 0.250

-

V_ref− 0.250

V_ref+ 0.125

-

V_ref− 0.125

-

0.65 × V_DD

V_IL

RESET

-

0.35 × V_DD

V_ICR

common mode input voltage

range

CK, CK

0.675

1.125

V_ID

I_OH

I_OL

differential input voltage

HIGH-level output current

LOW-level output current

ambient temperature

CK, CK

600

-

mV

mA

-

−8

8

T_amb

operating in free air

SSTUM32865ET/G

SSTUM32865ET/S

0

-

+70

+85

°C

[1] The differential inputs must not be ﬂoating, unless RESET is LOW.

[2] The RESET input of the device must be held at valid logic levels (not ﬂoating) to ensure proper device operation.

SSTUM32865_1

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1.8 V DDR2-800 registered buffer with parity

10. Characteristics

Table 9.

Characteristics

Over recommended operating conditions, unless otherwise noted.

Symbol

V_OH

V_OL

Parameter

Conditions

Min

Typ

Max

-

Unit

V

HIGH-level output voltage

LOW-level output voltage

input current

I_OH= −6 mA; V_DD= 1.7 V

I_OL= 6 mA; V_DD= 1.7 V

all inputs; V_I= V_DDor GND;

1.2

-

0.5

±5

V

I_I

µA

V_DD= 2.0 V

I_DD

supply current

static standby current;

RESET = GND; V_DD= 2.0 V

-

2

mA

static operating current;

RESET = V_DD; V_DD= 2.0 V;

V_I= V_IH(AC)or V_IL(AC)

40

I_DDD

dynamic operating current per MHz

clock only; RESET = V_DD

;

-

16

19

-

µA

V_I= V_IH(AC)or V_IL(AC); CK and CK

switching at 50 % duty cycle.

I_O= 0 mA; V_DD= 1.8 V

per each data input;

RESET = V_DD

;

V_I= V_IH(AC)or V_IL(AC); CK and CK

switching at 50 % duty cycle. One

data input switching at half clock

frequency, 50 % duty cycle.

I_O= 0 mA; V_DD= 1.8 V

C_i

input capacitance

output impedance

data inputs; V_I= V_ref± 250 mV;

2.5

2

-

3.5

3

pF

V

_DD= 1.8 V

CK and CK; V_ICR= 0.9 V;

_ID= 600 mV; V_DD= 1.8 V

RESET; V_I= V_DDor GND;

_DD= 1.8 V

V

3

5

V

[1]

Z_o

instantaneous

steady-state

-

7

-

Ω

53

[1] Instantaneous is deﬁned as within < 2 ns following the output data transition edge.

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SSTUM32865

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1.8 V DDR2-800 registered buffer with parity

Table 10. Timing requirements

Over recommended operating conditions, unless otherwise noted.

Symbol

f_clock

t_W

Parameter

Conditions

Min

Typ

Max

450

-

Unit

MHz

ns

clock frequency

-

pulse width

CK, CK HIGH or LOW

1

[1][2]

[1][3]

t_ACT

differential inputs active time

differential inputs inactive time

set-up time

-

10

15

-

ns

t_INACT

t_su

-

ns

Chip Select; DCS0, DCS1

valid before clock

switching

0.6

ns

Data; Dn valid before

clock switching

0.5

0.4

-

ns

PARIN; PARIN before CK

and CK

t_h

hold time

input to remain valid after

clock switching

PARIN after CK and CK

[1] This parameter is not necessarily production tested.

[2] Data inputs must be active below a minimum time of t_ACT(max)after RESET is taken HIGH.

[3] Data and clock inputs must be held at valid levels (not ﬂoating) a minimum time of t_INACT(max)after RESET is taken LOW.

Table 11. Switching characteristics

Over recommended operating conditions, unless otherwise noted.

Symbol

f_max

Parameter

Conditions

Min

450

1.0

1.2

1

Typ

Max

-

Unit

MHz

ns

maximum input clock frequency

peak propagation delay

LOW to HIGH delay time

HIGH to LOW delay time

LOW-to-HIGH propagation delay

-

[1]

t_PDM

t_LH

CK and CK to output

CK and CK to PTYERR

from RESET to PTYERR

CK and CK to output

1.4

3

ns

t_HL

3

ns

t_PLH

-

3

ns

[1][2]

t_PDMSS

simultaneous switching peak

propagation delay

-

1.5

ns

t_PHL

HIGH-to-LOW propagation delay

RESET to output

-

3

ns

[1] Includes 350 ps of test-load transmission line delay.

[2] This parameter is not necessarily production tested.

Table 12. Output edge rates

Over recommended operating conditions, unless otherwise noted.

Symbol

dV/dt_r

dV/dt_f

dV/dt_∆

Parameter

Conditions

Min

Typ

Max

Unit

V/ns

rising edge slew rate

falling edge slew rate

1

-

4

1

absolute difference between dV/dt_r

and dV/dt_f

SSTUM32865_1

Product data sheet

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SSTUM32865

NXP Semiconductors

1.8 V DDR2-800 registered buffer with parity

11. Test information

11.1 Test circuit

All input pulses are supplied by generators having the following characteristics:

Pulse Repetition Rate (PRR) ≤ 10 MHz; Z₀= 50 Ω; input slew rate = 1 V/ns ± 20 %,

unless otherwise speciﬁed.

The outputs are measured one at a time with one transition per measurement.

V

DD

DUT

delay = 350 ps

= 50 Ω

R

= 1000 Ω

L

50 Ω

Z

o

CK

CK inputs

OUT

(1)

= 30 pF

C

L

R

L

test point

R

L

= 100 Ω

test point

002aaa371

(1) C_Lincludes probe and jig capacitance.

Fig 8. Load circuit

LVCMOS

V

DD

0.5V

RESET

DD

0 V

t

ACT

INACT

90 %

(1)

DD

I

10 %

002aaa372

(1) I_DDtested with clock and data inputs held at V_DDor GND, and I_O= 0 mA.

Fig 9. Voltage and current waveforms; inputs active and inactive times

t

W

V

IH

IL

V

input

V

ICR

ID

ICR

002aaa373

V_ID= 600 mV.

V_IH= V_ref+ 250 mV (AC voltage levels) for differential inputs. V_IH= V_DDfor LVCMOS inputs.

V_IL= V_ref− 250 mV (AC voltage levels) for differential inputs. V_IL= GND for LVCMOS inputs.

Fig 10. Voltage waveforms; pulse duration

SSTUM32865_1

Product data sheet

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SSTUM32865

NXP Semiconductors

1.8 V DDR2-800 registered buffer with parity

CK

V

ICR

ID

t

h

su

V

IH

IL

input

V

ref

V

ref

002aaa374

V_ID= 600 mV.

V_ref= 0.5V_DD

.

V_IH= V_ref+ 250 mV (AC voltage levels) for differential inputs. V_IH= V_DDfor LVCMOS inputs.

V_IL= V_ref− 250 mV (AC voltage levels) for differential inputs. V_IL= GND for LVCMOS inputs.

Fig 11. Voltage waveforms; set-up and hold times

CK

V

i(p-p)

ICR

CK

t

PHL

PLH

V

OH

OL

V

output

T

002aaa375

t_PLHand t_PHLare the same as t_PD

.

Fig 12. Voltage waveforms; propagation delay times (clock to output)

LVCMOS

V

IH

RESET

0.5V

DD

IL

t

PHL

OH

OL

output

V

T

002aaa376

t_PLHand t_PHLare the same as t_PD

.

V_IH= V_ref+ 250 mV (AC voltage levels) for differential inputs. V_IH= V_DDfor LVCMOS inputs.

V_IL= V_ref− 250 mV (AC voltage levels) for differential inputs. V_IL= GND for LVCMOS inputs.

Fig 13. Voltage waveforms; propagation delay times (reset to output)

SSTUM32865_1

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SSTUM32865

NXP Semiconductors

1.8 V DDR2-800 registered buffer with parity

11.2 Output slew rate measurement

V_DD= 1.8 V ± 0.1 V.

All input pulses are supplied by generators having the following characteristics:

PRR ≤ 10 MHz; Z_o= 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise speciﬁed.

V

DD

R

DUT

= 50 Ω

L

OUT

test point

002aaa377

(1)

= 10 pF

C

L

(1) C_Lincludes probe and jig capacitance.

Fig 14. Load circuit, HIGH-to-LOW slew measurement

output

V

OH

80 %

dv_f

20 %

V

OL

dt_f

002aaa378

Fig 15. Voltage waveforms, HIGH-to-LOW slew rate measurement

DUT

OUT

test point

(1)

= 10 pF

C

L

R

L

= 50 Ω

002aaa379

(1) C_Lincludes probe and jig capacitance.

Fig 16. Load circuit, LOW-to-HIGH slew measurement

dt_r

V

OH

80 %

dv_r

20 %

output

OL

002aaa380

Fig 17. Voltage waveforms, LOW-to-HIGH slew rate measurement

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SSTUM32865

NXP Semiconductors

1.8 V DDR2-800 registered buffer with parity

11.3 Error output load circuit and voltage measurement

V_DD= 1.8 V ± 0.1 V.

All input pulses are supplied by generators having the following characteristics:

PRR ≤ 10 MHz; Z_o= 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise speciﬁed.

V

DD

R

DUT

= 1 kΩ

L

OUT

test point

002aaa500

(1)

= 10 pF

C

L

(1) C_Lincludes probe and jig capacitance.

Fig 18. Load circuit, error output measurements

LVCMOS

V

DD

RESET

0.5V

DD

0 V

t

PLH

V

OH

output

waveform 2

0.15 V

0 V

002aaa501

Fig 19. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to

RESET input

timing

inputs

V

i(p-p)

V

ICR

t

HL

V

DD

OL

output

waveform 1

0.5V

DD

002aaa502

Fig 20. Voltage waveforms, open-drain output HIGH-to-LOW transition time with respect

to clock inputs

SSTUM32865_1

Product data sheet

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NXP Semiconductors

1.8 V DDR2-800 registered buffer with parity

timing

inputs

V

i(p-p)

V

ICR

t

LH

V

OH

output

waveform 2

0.15 V

0 V

002aaa503

Fig 21. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to

clock inputs

SSTUM32865_1

Product data sheet

Rev. 01 — 19 September 2007

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1.8 V DDR2-800 registered buffer with parity

12. Package outline

TFBGA160: plastic thin fine-pitch ball grid array package; 160 balls; body 9 x 13 x 0.7 mm

SOT802-2

D

B

A

ball A1

index area

A

2

E

A

1

detail X

e

1

C

1/2 e

y

C

1

y

M

v

C

A

B

e

b

M

w

V

U

T

R

P

N

M

L

e

K

J

e

2

H

G

F

1/2 e

E

D

C

B

A

ball A1

index area

1

3

5

7

9

11

2

4

6

8

10 12

X

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

1

A

2

b

D

E

e

1

e

v

w

y

1

2

max

0.35 0.80 0.45

0.25 0.65 0.35

9.1

8.9

13.1

12.9

mm

1.15

0.65 7.15 11.05 0.15 0.08

0.1

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

- - -

JEITA

05-06-21

05-07-13

- - -

SOT802-2

Fig 22. Package outline SOT802-2 (TFBGA160)

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1.8 V DDR2-800 registered buffer with parity

13. Soldering

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

13.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

13.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus PbSn soldering

13.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

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SSTUM32865

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1.8 V DDR2-800 registered buffer with parity

13.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 23) than a PbSn process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 13 and 14

Table 13. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 14. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 23.

SSTUM32865_1

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Rev. 01 — 19 September 2007

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SSTUM32865

NXP Semiconductors

1.8 V DDR2-800 registered buffer with parity

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 23. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

14. Abbreviations

Table 15. Abbreviations

Acronym

CMOS

DDR2

Description

Complementary Metal Oxide Semiconductor

Double Data Rate 2

DIMM

Dual In-line Memory Module

DRAM

LVCMOS

MT/s

Dynamic Random Access Memory

Low Voltage Complementary Metal Oxide Semiconductor

Mega Transfers per second

RDIMM

SSTL

Registered Dual In-line Memory Module

Stub Series Terminated Logic

SSTL_18

Stub Series Terminated Logic for 1.8 V

15. Revision history

Table 16. Revision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

SSTUM32865_1

20070919

Product data sheet

-

SSTUM32865_1

Product data sheet

Rev. 01 — 19 September 2007

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SSTUM32865

NXP Semiconductors

1.8 V DDR2-800 registered buffer with parity

16. Legal information

16.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of a NXP Semiconductors product can reasonably be expected to

16.2 Deﬁnitions

result in personal injury, death or severe property or environmental damage.

NXP Semiconductors accepts no liability for inclusion and/or use of NXP

Semiconductors products in such equipment or applications and therefore

such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

16.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

17. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

SSTUM32865_1

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18. Contents

1

General description . . . . . . . . . . . . . . . . . . . . . . 1

2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3

3

4

4.1

5

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

7

Functional description . . . . . . . . . . . . . . . . . . . 8

Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Functional information . . . . . . . . . . . . . . . . . . . 9

Functional differences to SSTU32864 . . . . . . 10

Chip Select (CS) gating of key inputs (DCS0,

DCS1, DCS2, DCS3, CSGATEEN) . . . . . . . . 10

Parity error checking and reporting. . . . . . . . . 10

Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . 10

Power-up sequence . . . . . . . . . . . . . . . . . . . . 10

7.1

7.2

7.3

7.3.1

7.3.2

7.3.3

7.3.4

8

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 15

Recommended operating conditions. . . . . . . 15

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 16

9

10

11

Test information. . . . . . . . . . . . . . . . . . . . . . . . 18

Test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Output slew rate measurement. . . . . . . . . . . . 20

Error output load circuit and voltage

11.1

11.2

11.3

measurement . . . . . . . . . . . . . . . . . . . . . . . . . 21

12

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23

13

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Introduction to soldering . . . . . . . . . . . . . . . . . 24

Wave and reﬂow soldering . . . . . . . . . . . . . . . 24

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 24

Reﬂow soldering . . . . . . . . . . . . . . . . . . . . . . . 25

13.1

13.2

13.3

13.4

14

15

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 26

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 26

16

Legal information. . . . . . . . . . . . . . . . . . . . . . . 27

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 27

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 27

16.1

16.2

16.3

16.4

17

18

Contact information. . . . . . . . . . . . . . . . . . . . . 27

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 19 September 2007

Document identifier: SSTUM32865_1


型号：	SSTUM32865ES
厂家：	NXP
描述：	1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-800 RDIMM applications 1.8 V 28位1 ： 2注册奇偶校验的DDR2-800 RDIMM应用程序的缓冲区双倍数据速率
文件：	总28页 (文件大小：153K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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