SSTVN16859BS,151 [NXP]
IC SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PQCC56, 8 X 8 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-684-1, HVQFN-56, FF/Latch;
| 型号： | SSTVN16859BS,151 |
| 厂家： | 
NXP |
| 描述： | IC SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PQCC56, 8 X 8 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-684-1, HVQFN-56, FF/Latch 输出元件 逻辑集成电路 触发器 电视 |
| 文件： | 总23页 (文件大小：120K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SSTVF16859
13-bit 1 : 2 SSTL_2 registered buffer for DDR
Rev. 02 — 19 July 2005
Product data sheet
1. General description
The SSTVF16859 is a 13-bit to 26-bit SSTL_2 registered driver with differential clock
inputs, designed to operate between 2.3 V and 2.7 V for PC1600-PC2700 applications or
between 2.5 V and 2.7 V for PC3200 applications. All inputs are compatible with the
JEDEC standard for SSTL_2 with Vref normally at 0.5 × VDD, except the LVCMOS reset
(RESET) input. All outputs are SSTL_2, Class II compatible, which can be used for
standard stub-series applications or capacitive loads. Master reset (RESET)
asynchronously resets all registers to zero.
The SSTVF16859 is intended to be incorporated into standard DIMM (Dual In-Line
Memory Module) designs defined by JEDEC, such as DDR (Double Data Rate) SDRAM
and SDRAM II Memory Modules. Different from traditional SDRAM, DDR SDRAM
transfers data on both clock edges (rising and falling), thus doubling the peak bus
bandwidth. A DDR DRAM rated at 133 MHz will have a burst rate of 266 MHz.
The device data inputs consist of different receivers. One differential input is tied to the
input pin while the other is tied to a reference input pad, which is shared by all inputs.
The clock input is fully differential (CK and CK) to be compatible with DRAM devices that
are installed on the DIMM. Data are registered at the crossing of CK going HIGH, and CK
going LOW. However, since the control inputs to the SDRAM change at only half the data
rate, the device must only change state on the positive transition of the CK signal. In order
to be able to provide defined outputs from the device even before a stable clock has been
supplied, the device has an asynchronous input pin (RESET), which when held to the
LOW state, resets all registers and all outputs to the LOW state.
The device supports low-power standby operation. When RESET is LOW, the differential
input receivers are disabled, and un-driven (floating) data, clock, and reference voltage
(VREF) inputs are allowed. In addition, when RESET is LOW, all registers are reset, and
all outputs are forced LOW. The LVCMOS RESET input must always be held at a valid
logic HIGH or LOW level.
To ensure defined outputs from the register before a stable clock has been supplied,
RESET must be held in the LOW state during power-up.
In the DDR DIMM application, RESET is specified to be completely asynchronous with
respect to CK and CK. Therefore, no timing relationship can be guaranteed between the
two. When entering RESET, the register will be cleared and the outputs will be driven
LOW. As long as the data inputs are LOW, and the clock is stable during the time from the
LOW-to-HIGH transition of RESET until the input receivers are fully enabled, the outputs
will remain LOW.
SSTVF16859
Philips Semiconductors
13-bit 1 : 2 SSTL_2 registered buffer for DDR
2. Features
■ Stub-series terminated logic for 2.5 V VDD (SSTL_2)
■ Designed for PC1600-PC2700 (at 2.5 V) and PC3200 (at 2.6 V) applications
■ Pin and function compatible with JEDEC standard SSTV16859
■ Supports SSTL_2 signal inputs as per JESD 8-9
■ Flow-through architecture optimizes printed-circuit board layout
■ ESD classification testing is done to JEDEC Standard JESD22. Protection exceeds
2000 V to HBM per method A114.
■ Latch-up testing is done to JEDEC Standard JESD78, which exceeds 100 mA
■ Supports efficient low power standby operation
■ Full DDR solution when used with PCKVF857
■ Available in TSSOP64, LFBGA96 and HVQFN56 packages
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tPHL/tPLH
propagation delay,
CK/CK to Qn
CL = 30 pF;
-
1.7
-
ns
VDD = 2.5 V
[1]
Ci
input capacitance
VDD = 2.5 V
-
2.8
-
pF
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VDD2 × fi + Σ (CL × VDD2 × fo) where:
fi = input frequency in MHz;
CL = output load capacitance in pF;
fo = output frequency in MHz;
VDD = supply voltage in V;
Σ (CL × VDD2 × fo) = sum of the outputs.
4. Ordering information
Table 2:
Ordering information
Tamb = 0 °C to +70 °C
Type number
Package
Name
Description
Version
SSTVF16859BS
HVQFN56 plastic thermal enhanced very thin quad flat package; SOT684-1
no leads; 56 terminals; body 8 × 8 × 0.85 mm
SSTVF16859DGG TSSOP64 plastic thin shrink small outline package; 64 leads;
body width 6.1 mm
SOT646-1
SOT536-1
SSTVF16859EC
LFBGA96 plastic low profile fine-pitch ball grid array package;
96 balls; body 13.5 × 5.5 × 1.05 mm
9397 750 15157
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 19 July 2005
2 of 23
SSTVF16859
Philips Semiconductors
13-bit 1 : 2 SSTL_2 registered buffer for DDR
5. Functional diagram
SSTVF16859
RESET
1D
C1
Q1A
Q1B
CK
CK
R
D1
VREF
002aab621
to 12 other channels
Fig 1. Logic diagram of SSTVF16859
6. Pinning information
6.1 Pinning
terminal 1
index area
1
2
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Q7A
Q6A
Q5A
Q4A
Q3A
Q2A
Q1A
Q13B
D10
D9
3
D8
4
D7
5
RESET
GND
CK
6
7
SSTVF16859BS
8
CK
9
V
V
V
DDQ
DDQ
DD
10
11
12
13
14
Q12B
Q11B
Q10B
Q9B
VREF
D6
D5
Q8B
D4
002aab618
Transparent top view
Fig 2. Pin configuration for HVQFN56
9397 750 15157
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 19 July 2005
3 of 23
SSTVF16859
Philips Semiconductors
13-bit 1 : 2 SSTL_2 registered buffer for DDR
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Q13A
Q12A
Q11A
Q10A
Q9A
V
DD
2
GND
D14
D12
3
4
5
V
V
DD
DD
6
V
DD
7
GND
Q8A
Q7A
Q6A
Q5A
Q4A
Q3A
Q2A
GND
Q1A
Q13B
GND
D11
D10
D9
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
GND
D8
D7
RESET
GND
CK
SSTVF16859DGG
CK
V
DD
V
V
DD
DD
Q12B
Q11B
Q10B
Q9B
VREF
D6
GND
D5
Q8B
Q7B
D4
Q6B
D3
GND
GND
V
DD
V
V
DD
DD
Q5B
Q4B
Q3B
Q2B
Q1B
D2
D1
GND
V
DD
002aab617
Fig 3. Pin configuration for TSSOP64
9397 750 15157
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 19 July 2005
4 of 23
SSTVF16859
Philips Semiconductors
13-bit 1 : 2 SSTL_2 registered buffer for DDR
ball A1
index area
SSTVF16859EC
1 2 3 4 5 6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
002aab619
Transparent top view
Fig 4. Pin configuration for LFBGA96
1
2
3
4
5
6
n.c.
n.c.
n.c.
D12
D10
D8
A
B
C
D
E
F
n.c.
n.c.
Q13A
Q11A
Q9A
Q7A
Q5A
Q3A
Q13B
Q11B
Q9B
Q7B
Q5B
Q3B
Q1B
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
D13
D11
D9
Q12A
Q10A
Q8A
Q6A
Q4A
Q2A
Q1A
Q12B
Q10B
Q8B
Q6B
Q4B
Q2B
n.c.
GND
GND
GND
GND
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
GND
GND
GND
GND
GND
D7
RESET
CK
G
H
J
n.c.
n.c.
n.c.
D5
VREF
CK
V
V
n.c.
D6
K
L
DDQ
DDQ
DDQ
DDQ
V
V
V
DDQ
V
D3
D4
M
N
P
R
T
DDQ
GND
GND
n.c.
GND
GND
n.c.
D1
D2
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
002aab620
All VDD and VDDQ are tied internally.
Fig 5. Ball mapping for LFBGA96
9397 750 15157
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 19 July 2005
5 of 23
SSTVF16859
Philips Semiconductors
13-bit 1 : 2 SSTL_2 registered buffer for DDR
6.2 Pin description
Table 3:
Symbol
Pin description
Pin
Description
TSSOP64
HVQFN56
LFBGA96
H1
G1
G2
F1
Q1A
Q2A
Q3A
Q4A
Q5A
Q6A
Q7A
Q8A
Q9A
Q10A
Q11A
Q12A
Q13A
Q1B
Q2B
Q3B
Q4B
Q5B
Q6B
Q7B
Q8B
Q9B
Q10B
Q11B
Q12B
Q13B
VDD
16
14
13
12
11
10
9
7
data output
6
5
4
3
F2
2
E1
E2
D1
D2
C1
C2
B1
B2
P2
P1
N2
N1
M2
M1
L2
1
8
56
54
53
52
51
50
22
21
20
19
18
16
15
14
13
12
11
10
8
5
4
3
2
1
32
31
30
29
28
25
24
23
22
21
20
19
17
37, 46, 60
data output
L1
K2
K1
J2
J1
H2
-
26, 33, 45
power supply voltage
output supply voltage
VDDQ
6, 18, 27, 33, 38, 9, 17, 23, 27, 34, D3, D4, E3, E4,
47, 59, 64
44, 49, 55
F3, F4, K3, K4,
L3, L4, M3, M4,
GND
7, 15, 26, 34, 39, 37, 48
43, 50, 54, 58, 63
B3, B4, C3, C4,
G3, G4, H3, H4,
J3, N3, N4, P3,
P4
ground
9397 750 15157
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 19 July 2005
6 of 23
SSTVF16859
Philips Semiconductors
13-bit 1 : 2 SSTL_2 registered buffer for DDR
Table 3:
Symbol
Pin description …continued
Pin
Description
TSSOP64
35
HVQFN56
LFBGA96
N5
D1
24
25
28
29
30
31
39
40
41
42
43
46
47
32
35
36
38
Data input. Clocked in on the crossing of the rising
edge of CK and the falling edge of CK.
D2
36
N6
D3
40
M5
M6
L5
D4
41
D5
42
D6
44
L6
D7
52
G5
F6
D8
53
D9
55
F5
D10
D11
D12
D13
VREF
CK
56
E6
57
E5
61
D6
62
D5
45
J4
input reference voltage
48
J6
positive master clock input
negative master clock input
CK
49
H6
RESET
51
G6
Asynchronous reset input. Resets registers and
disables data and clock differential input receivers.
n.c.
-
-
A1, A2, A3, A4,
A5, A6, B5, B6,
C5, C6, H5, J5,
K5, K6, P5, P6,
R1, R2, R3, R4,
R5, R6, T1, T2,
T3, T4, T5, T6
not connected
7. Functional description
Refer to Figure 1 “Logic diagram of SSTVF16859”.
7.1 Function table
Table 4:
Function selection (each flip-flop)
H = HIGH voltage level; L = LOW voltage level; ↓ = HIGH-to-LOW transition;
↑ = LOW-to-HIGH transition; X = Don’t care
Inputs
Output
RESET
CK
CK
Dn
Qn
L
H
H
H
L
↑
↓
L
↑
↓
H
H
[1]
L or H
L or H
X
Q0
X or floating
X or floating
X or floating
L
[1] Q0 is the previous state of output Qn.
9397 750 15157
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 19 July 2005
7 of 23
SSTVF16859
Philips Semiconductors
13-bit 1 : 2 SSTL_2 registered buffer for DDR
8. Limiting values
Table 5:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDD
VI
Parameter
Conditions
Min
Max
Unit
V
supply voltage
−0.5
−0.5[1]
−0.5[1]
+3.6
input voltage
VDD + 0.5[2]
VDD + 0.5[2]
±50
V
VO
output voltage
V
IIK
input clamp current
output clamp current
continuous output current
continuous current through each
VI < 0 V or VI > VDD
VO < 0 V or VO > VDD
VO = 0 V to VDD
-
-
-
-
mA
mA
mA
mA
IOK
±50
IO
±50
ICCC
±100
VDD or GND
[3]
Tstg
storage temperature
−65
+150
°C
[1] The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
[2] This value is limited to 3.6 V maximum.
[3] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures that are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.
9. Recommended operating conditions
Table 6:
Symbol
VDD
Recommended operating conditions[1]
Parameter
Conditions
Min
VDD
1.15
1.25
Typ
Max
Unit
V
supply voltage
-
2.7
Vref
reference voltage (Vref = VDD/2) PC1600-PC2700
1.25
1.35
V
PC3200
termination voltage
1.3
1.35
V
VTT
V
ref − 0.040
Vref
Vref + 0.040
V
VI
input voltage
0
-
-
-
-
-
-
-
-
VDD
-
V
VIH(AC)
VIL(AC)
VIH(DC)
VIL(DC)
VIH
AC HIGH-level input voltage
AC LOW-level input voltage
DC HIGH-level input voltage
DC LOW-level input voltage
HIGH-level input voltage
LOW-level input voltage
data inputs
data inputs
data inputs
data inputs
RESET
Vref + 0.310
V
-
V
-
ref − 0.310
V
Vref + 0.150
V
-
V
ref − 0.150
V
1.7
0
VDD
0.7
V
VIL
V
VICR
common-mode input voltage
range
CK, CK
CK, CK
0.97
1.53
V
VID
IOH
IOL
differential input voltage
HIGH-level output current
LOW-level output current
ambient temperature
360
-
-
-
-
-
mV
mA
mA
°C
-
−16
16
+70
-
Tamb
operating in free air
0
[1] The RESET input of the device must be held at VDD or GND to ensure proper device operation. The differential inputs must not be
floating, unless RESET is LOW.
9397 750 15157
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 19 July 2005
8 of 23
SSTVF16859
Philips Semiconductors
13-bit 1 : 2 SSTL_2 registered buffer for DDR
10. Static characteristics
Table 7:
Static characteristics (PC1600-PC2700)
Tamb = 0 °C to +70 °C; over recommended operating conditions; voltages are referenced to GND (ground = 0 V);
unless otherwise specified.
Symbol Parameter
Conditions
II = −18 mA; VDD = 2.3 V
Min
Typ
Max
−1.2
-
Unit
V
VIK
input clamping voltage
-
-
-
-
-
-
-
VOH
HIGH-level output voltage IOH = −100 µA; VDD = 2.3 V to 2.7 V
IOH = −16 mA; VDD = 2.3 V
VDD − 0.2
V
1.95
-
V
VOL
LOW-level output voltage IOL = 100 µA; VDD = 2.3 V to 2.7 V
IOL = 16 mA; VDD = 2.3 V
-
-
-
0.2
0.35
±5
V
V
II
input current (all inputs)
supply current
VI = VDD or GND; VDD = 2.7 V
IO = 0 mA; VDD = 2.7 V
µA
IDD
static standby; RESET = GND
-
-
-
-
0.01
45
mA
mA
static operating; RESET = VDD
;
VI = VIH(AC) or VIL(AC)
IDDD
dynamic operating current IO = 0 mA; VDD = 2.7 V; RESET = VDD
;
-
-
15
9
-
-
µA
µA
per MHz, clock only
VI = VIH(AC) or VIL(AC); CK and CK
switching 50 % duty cycle
dynamic operating current IO = 0 mA; VDD = 2.7 V; RESET = VDD
;
per MHz, per each data
input
VI = VIH(AC) or VIL(AC); CK and CK
switching 50 % duty cycle; one data
input switching at half clock frequency,
50 % duty cycle
Ci
input capacitance
data inputs; VI = Vref ± 310 mV;
2.5
2.5
-
2.8
3.2
2.4
3.5
3.5
3.5
pF
pF
pF
V
DD = 2.5 V
CK and CK; VICR = 1.25 V;
I(p-p) = 360 mV; VDD = 2.5 V
V
RESET; VI = VDD or GND; VDD = 2.5 V
9397 750 15157
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 19 July 2005
9 of 23
SSTVF16859
Philips Semiconductors
13-bit 1 : 2 SSTL_2 registered buffer for DDR
Table 8:
Static characteristics (PC3200)
At recommended operating conditions; Tamb = 0 °C to +70 °C; voltages are referenced to GND (ground = 0 V);
unless otherwise specified.
Symbol Parameter
Conditions
II = −18 mA; VDD = 2.5 V
Min
Typ
Max
−1.2
-
Unit
V
VIK
input clamping voltage
-
-
-
-
-
-
-
VOH
HIGH-level output voltage IOH = −100 µA; VDD = 2.5 V to 2.7 V
IOH = −16 mA; VDD = 2.5 V
VDD − 0.2
V
1.95
-
V
VOL
LOW-level output voltage IOL = 100 µA; VDD = 2.5 V to 2.7 V
IOL = 16 mA; VDD = 2.5 V
-
-
-
0.2
0.35
±5
V
V
II
input current (all inputs)
supply current
VI = VDD or GND; VDD = 2.7 V
IO = 0 mA; VDD = 2.7 V
µA
IDD
static standby; RESET = GND
-
-
-
-
0.01
45
mA
mA
static operating; RESET = VDD
;
VI = VIH(AC) or VIL(AC)
IDDD
dynamic operating current IO = 0 mA; VDD = 2.7 V; RESET = VDD
;
-
-
15
9
-
-
µA
µA
per MHz, clock only
VI = VIH(AC) or VIL(AC); CK and CK
switching 50 % duty cycle
dynamic operating current IO = 0 mA; VDD = 2.7 V; RESET = VDD
;
per MHz, per each data
input
VI = VIH(AC) or VIL(AC); CK and CK
switching 50 % duty cycle; one data
input switching at half clock frequency,
50 % duty cycle
Ci
input capacitance,
data inputs
VI = Vref ± 310 mV; VDD = 2.6 V
2.5
2.5
-
2.8
3.2
2.4
3.5
3.5
3.5
pF
pF
pF
input capacitance,
CK and CK
VICR = 1.25 V; VI(p-p) = 360 mV;
V
DD = 2.6 V
input capacitance,
RESET
VI = VDD or GND; VDD = 2.6 V
9397 750 15157
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 19 July 2005
10 of 23
SSTVF16859
Philips Semiconductors
13-bit 1 : 2 SSTL_2 registered buffer for DDR
11. Dynamic characteristics
Table 9:
Timing requirements (PC1600-PC2700)
At recommended operating conditions; VDD = 2.5 V ± 0.2 V; Tamb = 0 °C to +70 °C; unless otherwise specified.
See Figure 11.
Symbol
fclock
Parameter
Conditions
Min
-
Typ
Max
200
-
Unit
MHz
ns
clock frequency
-
-
tW
pulse duration, CK, CK, HIGH or
LOW
2.5
[1] [2]
[1] [3]
[4] [6]
[5] [6]
[4] [6]
[5] [6]
tACT
tINACT
tsu
differential inputs active time
differential inputs inactive time
setup time, fast slew rate
setup time, slow slew rate
hold time, fast slew rate
-
-
-
-
-
-
-
22
22
-
ns
ns
ns
ns
ns
ns
-
data before CK↑, CK↓
data before CK↑, CK↓
data after CK↑, CK↓
data after CK↑, CK↓
0.65
0.75
0.75
0.9
-
th
-
hold time, slow slew rate
-
[1] This parameter is not necessarily production tested.
[2] Data inputs must be below a minimum time to tACT(max), after RESET is taken HIGH.
[3] Data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT(max), after RESET is taken LOW.
[4] For data signal input slew rate ≥ 1 V/ns.
[5] For data signal input slew rate ≥ 0.5 V/ns and < 1 V/ns.
[6] CK, CK signals input slew rates are ≥ 1 V/ns.
Table 10: Timing requirements (PC3200)
At recommended operating conditions; VDD = 2.6 V ± 0.1 V; Tamb = 0 °C to +70 °C; unless otherwise specified.
See Figure 11.
Symbol
fclock
Parameter
Conditions
Min
-
Typ
Max
210
-
Unit
MHz
ns
clock frequency
-
-
tW
pulse duration, CK, CK, HIGH or
LOW
2.5
[1] [2]
[1] [3]
[4] [6]
[5] [6]
[4] [6]
[5] [6]
tACT
tINACT
tsu
differential inputs active time
differential inputs inactive time
setup time, fast slew rate
setup time, slow slew rate
hold time, fast slew rate
-
-
-
-
-
-
-
22
22
-
ns
ns
ns
ns
ns
ns
-
data before CK↑, CK↓
data before CK↑, CK↓
data after CK↑, CK↓
data after CK↑, CK↓
0.65
0.75
0.65
0.8
-
th
-
hold time, slow slew rate
-
[1] This parameter is not necessarily production tested.
[2] Data inputs must be below a minimum time to tACT(max), after RESET is taken HIGH.
[3] Data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT(max), after RESET is taken LOW.
[4] For data signal input slew rate ≥ 1 V/ns.
[5] For data signal input slew rate ≥ 0.5 V/ns and < 1 V/ns.
[6] CK, CK signals input slew rates are ≥ 1 V/ns.
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Table 11: Switching characteristics (PC1600-PC2700)
At recommended operating conditions; VDD = 2.5 V ± 0.2 V; Tamb = 0 °C to +70 °C; Class I; Vref = VTT = VDD × 0.5 and
CL = 10 pF; unless otherwise specified. See Figure 11.
Symbol
fMAX
Parameter
Conditions
Min
200
1.1
-
Typ
Max
-
Unit
MHz
ns
maximum input clock frequency
propagation delay
-
-
-
-
tPD
from CK, CK to Qn
2.5
2.9
5
tPDMSS
tPHL
propagation delay, simultaneous switching from CK, CK to Qn
HIGH-to-LOW transition time from RESET to Qn
ns
1.1
ns
Table 12: Switching characteristics (PC3200)
At recommended operating conditions; VDD = 2.6 V ± 0.1 V; Tamb = 0 °C to +70 °C; Class I; Vref = VTT = VDD × 0.5 and
CL = 10 pF; unless otherwise specified. See Figure 11.
Symbol
fMAX
Parameter
Conditions
Min
210
1.1
-
Typ
Max
-
Unit
MHz
ns
maximum input clock frequency
propagation delay
-
-
-
-
tPD
from CK, CK to Qn
2.2
2.48
5
tPDMSS
tPHL
propagation delay, simultaneous switching from CK, CK to Qn
ns
HIGH-to-LOW transition time
from RESET to Qn
1.1
ns
11.1 AC waveforms
All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz; Zo = 50 Ω; input slew rate = 1 V/ns ± 20 %; unless otherwise specified.
The outputs are measured one at a time with one transition per measurement.
LVCMOS
V
DD
RESET
V
/2
DD
V
/2
DD
0 V
t
t
ACT
INACT
90 %
(1)
DD
I
10 %
002aaa372
(1) IDD tested with clock and data inputs held at VDD or GND, and IO = 0 mA.
Fig 6. Inputs active and inactive times
t
W
V
V
IH
IL
V
input
V
V
ref
ID
ref
002aab623
VIH = Vref + 310 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input.
VIL = Vref − 310 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input.
Fig 7. Pulse duration
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CK
CK
V
V
V
ICR
ICR
i(p-p)
t
t
PHL
PLH
V
V
OH
OL
V
output
TT
002aab624
VTT = Vref = VDD/2
tPLH and tPHL are the same as tPD
.
Fig 8. Propagation delay times (clock to output)
LVCMOS
V
V
V
V
IH
RESET
output
V
/2
DD
IL
t
PHL
OH
OL
V
TT
002aaa376
VTT = Vref = VDD/2
tPLH and tPHL are the same as tPD
.
VIH = Vref + 310 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input.
VIL = Vref − 310 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input.
Fig 9. Propagation delay times (reset to output)
CK
V
V
ICR
i(p-p)
CK
t
t
h
su
V
V
IH
IL
input
V
ref
V
ref
002aab625
Vref = VDD/2
VIH = Vref + 310 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input.
VIL = Vref − 310 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input.
Fig 10. Setup and hold times
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12. Test information
R
L
= 50 Ω
m output under test
test point
002aab622
(1)
= 30 pF
C
L
(1) CL includes probe and jig capacitance.
Fig 11. Load circuit
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13. Package outline
TSSOP64: plastic thin shrink small outline package; 64 leads; body width 6.1 mm
SOT646-1
E
A
D
X
c
H
y
v M
A
E
Z
64
33
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
32
M
detail X
w
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions).
A
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
L
L
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
1.05
0.85
0.27
0.17
0.2
0.1
17.1
16.9
6.2
6.0
8.3
7.9
0.75
0.45
0.89
0.61
mm
1.2
0.5
1
0.2
0.25
0.08
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-08-21
03-02-18
SOT646-1
MO-153
Fig 12. Package outline SOT646-1 (TSSOP64)
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LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm SOT536-1
B
A
D
ball A1
index area
A
2
A
E
A
1
detail X
e
1
C
1/2 e
y
y
v M
w M
C
C
A B
C
1
e
b
T
R
P
N
e
M
L
K
J
H
G
F
e
2
1/2 e
E
D
C
B
A
ball A1
index area
1
2
3
4
5
6
X
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
A
b
e
e
e
v
w
y
y
1
D
E
1
2
1
2
max.
0.41
0.31
1.2
0.9
0.51
0.41
5.6
5.4
13.6
13.4
mm
1.5
4
12
0.1
0.2
0.8
0.15
0.1
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
00-03-04
03-02-05
SOT536-1
Fig 13. Package outline SOT536-1 (LFBGA96)
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HVQFN56: plastic thermal enhanced very thin quad flat package; no leads;
56 terminals; body 8 x 8 x 0.85 mm
SOT684-1
D
B
A
terminal 1
index area
A
E
A
1
c
detail X
C
e
1
y
y
e
1/2 e
b
v
M
M
C
C
A
B
C
1
w
15
28
L
29
14
e
e
E
h
2
1/2 e
1
42
terminal 1
index area
56
43
X
D
h
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
max.
(1)
(1)
E
UNIT
A
1
b
c
E
e
e
1
e
2
y
D
D
L
v
w
y
1
h
h
0.05 0.30
0.00 0.18
8.1
7.9
4.45
4.15
8.1
7.9
4.45
4.15
0.5
0.3
mm
0.2
0.5
6.5
6.5
0.05
0.1
1
0.1 0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
01-08-08
02-10-22
SOT684-1
- - -
MO-220
- - -
Fig 14. Package outline SOT684-1 (HVQFN56)
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14. Soldering
14.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of
soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface mount IC packages. Wave
soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is recommended.
14.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement. Driven by legislation and
environmental forces the worldwide use of lead-free solder pastes is increasing.
Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and cooling)
vary between 100 seconds and 200 seconds depending on heating method.
Typical reflow peak temperatures range from 215 °C to 270 °C depending on solder paste
material. The top-surface temperature of the packages should preferably be kept:
• below 225 °C (SnPb process) or below 245 °C (Pb-free process)
– for all BGA, HTSSON..T and SSOP..T packages
– for packages with a thickness ≥ 2.5 mm
– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called
thick/large packages.
• below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a
thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages.
Moisture sensitivity precautions, as indicated on packing, must be respected at all times.
14.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically
developed.
If wave soldering is used the following conditions must be observed for optimal results:
• Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be
parallel to the transport direction of the printed-circuit board;
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– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the
transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
• For packages with leads on four sides, the footprint must be placed at a 45° angle to
the transport direction of the printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C
or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.
A mildly-activated flux will eliminate the need for removal of corrosive residues in most
applications.
14.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage
(24 V or less) soldering iron applied to the flat part of the lead. Contact time must be
limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within
2 seconds to 5 seconds between 270 °C and 320 °C.
14.5 Package related soldering information
Table 13: Suitability of surface mount IC packages for wave and reflow soldering methods
Package [1]
Soldering method
Wave
Reflow[2]
BGA, HTSSON..T[3], LBGA, LFBGA, SQFP,
SSOP..T[3], TFBGA, VFBGA, XSON
not suitable
suitable
DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP,
HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,
HVSON, SMS
not suitable[4]
suitable
PLCC[5], SO, SOJ
suitable
suitable
LQFP, QFP, TQFP
not recommended[5] [6]
not recommended[7]
not suitable
suitable
SSOP, TSSOP, VSO, VSSOP
CWQCCN..L[8], PMFP[9], WQCCN..L[8]
suitable
not suitable
[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026);
order a copy from your Philips Semiconductors sales office.
[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal or
external package cracks may occur due to vaporization of the moisture in them (the so called popcorn
effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit
Packages; Section: Packing Methods.
[3] These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no
account be processed through more than one soldering cycle or subjected to infrared reflow soldering with
peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package
body peak temperature must be kept as low as possible.
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[4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the
solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink
on the top side, the solder might be deposited on the heatsink surface.
[5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave
direction. The package footprint must incorporate solder thieves downstream and at the side corners.
[6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
[7] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger
than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
[8] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered
pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by
using a hot bar soldering process. The appropriate soldering profile can be provided on request.
[9] Hot bar soldering or manual soldering is suitable for PMFP packages.
15. Abbreviations
Table 14: Abbreviations
Acronym
DDR
Description
Double Data Rate
DIMM
ESD
Dual In-line Memory Module
Electro Static Discharge
Human Body Model
HBM
PRR
Pulse Rate Repetition
Stub Series Terminated Logic
SSTL
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16. Revision history
Table 15: Revision history
Document ID
SSTVF16859_2
Modifications:
Release date Data sheet status
20050719 Product data sheet
Change notice
Doc. number
Supersedes
-
9397 750 15157 SSTVF16859_1
• The format of this data sheet has been redesigned to comply with the new presentation and
information standard of Philips Semiconductors.
• Table 1 “Quick reference data”:
–
parameter for tPHL/tPLH changed from ‘propagation delay; CLK to Qn’ to ‘propagation delay;
CK/CK to Qn’
–
Condition column for input capacitance changed from ‘VCC = 2.5 V’ to ‘VDD = 2.5 V’
• Section 6 “Pinning information”:
–
Figure 3 “Pin configuration for TSSOP64”: pins 6, 18, 27, 33, 38 47, 59 and 64 changed from
‘VDD’ to ‘VDDQ
pin description tables consolidated with columns for package-type
’
–
• Symbol ‘VREF’ changed to ‘VREF’ for pin name, and to ‘Vref’ for reference voltage
• Figure 2 “Pin configuration for HVQFN56” on page 3:
–
terminals 26, 33, 45 symbols changed from ‘VDDI’ to ‘VDD
’
–
terminal 56 symbol changed from ‘Q8B’ to ‘Q8A’
• Table 4 “Function selection (each flip-flop)” on page 7: moved definitions above table; added Table
note 1.
• Table 5 “Limiting values” on page 8:
–
deleted (old) Table note 1; this information is now placed in Section 18 “Definitions” on page 22.
–
Added symbol ‘ICCC’ to parameter ‘continuous current through each VDD or GND’
• Section 9 “Recommended operating conditions” on page 8: under Min and Max columns, values
previously expressed with unit ‘mV’ re-written as equivalent ‘V’ value.
• Table 7 “Static characteristics (PC1600-PC2700)” on page 9:
–
–
–
IDD(max) for ‘static operating’ condition changed from ‘25 mA’ to ‘45 mA’
IDDD(typ) for ‘clock only’ changed from ‘20 µA’ to ‘15 µA’
parameter for IDDD modified: added ‘per MHz’ to parameter, changed Unit to ‘µA’
• Table 8 “Static characteristics (PC3200)” on page 10: parameter for IDDD modified: added ‘per MHz’
to parameter, changed Unit to ‘µA’
• Added Section 14 “Soldering”, Section 15 “Abbreviations”, and Section 20 “Trademarks”.
SSTVF16859_1
20040712
Product data sheet
-
9397 750 13077
-
9397 750 15157
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17. Data sheet status
Level Data sheet status[1] Product status[2] [3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
18. Definitions
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
20. Trademarks
Notice — All referenced brands, product names, service names and
19. Disclaimers
trademarks are the property of their respective owners.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
21. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
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22. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
7
7.1
8
Functional description . . . . . . . . . . . . . . . . . . . 7
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8
Recommended operating conditions. . . . . . . . 8
Static characteristics. . . . . . . . . . . . . . . . . . . . . 9
Dynamic characteristics . . . . . . . . . . . . . . . . . 11
AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 12
Test information. . . . . . . . . . . . . . . . . . . . . . . . 14
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15
9
10
11
11.1
12
13
14
14.1
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Introduction to soldering surface mount
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 18
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 18
Manual soldering . . . . . . . . . . . . . . . . . . . . . . 19
Package related soldering information . . . . . . 19
14.2
14.3
14.4
14.5
15
16
17
18
19
20
21
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 21
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 22
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Contact information . . . . . . . . . . . . . . . . . . . . 22
© Koninklijke Philips Electronics N.V. 2005
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 19 July 2005
Document number: 9397 750 15157
Published in The Netherlands
相关型号：
SSTVN16859BS,157
IC SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PQCC56, 8 X 8 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-684-1, HVQFN-56, FF/Latch
NXP
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