TDA1310A [NXP]
Stereo Continuous Calibration DAC CC-DAC; 立体声连续校准DAC CC- DAC
| 型号： | TDA1310A |
| 厂家： | 
NXP |
| 描述： | Stereo Continuous Calibration DAC CC-DAC |
| 文件： | 总16页 (文件大小：116K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA1310A
Stereo Continuous Calibration DAC
(CC-DAC)
May 1994
Preliminary specification
Supersedes data of TDA1310; TDA1310T July 1993
File under Integrated Circuits, IC01
Philips Semiconductors
Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC
(CC-DAC)
TDA1310A
FEATURES
GENERAL DESCRIPTION
• Space saving package DIL8 or SO8
• Low power consumption
The TDA1310A is a device of a new generation of
Digital-to-Analog Converters (DACs) which embodies the
innovative technique of Continuous Calibration. The
largest bit-currents are repeatedly generated by one single
current reference source. This duplication is based upon
an internal charge storage principle having an accuracy
insensitive to ageing, temperature and process variations.
• Wide dynamic range (16-bit resolution)
• Continuous Calibration (CC) concept
• Easy application:
– Single 3 to 5 V supply rail
The TDA1310A is fabricated in a 1.0 µm CMOS process
and features an extremely low power dissipation, small
package size and easy application. Furthermore, the
accuracy of the intrinsic high coarse-current combined
with the implemented symmetrical offset decoding method
precludes zero-crossing distortion and ensures high
quality audio reproduction. Therefore, the CC-DAC is
eminently suitable for use in (portable) digital audio
equipment.
– Output current and bias current are proportional to
the supply voltage
• Fast settling time permits 2×, 4× and 8× oversampling
(serial input) or double speed operation at 4×
oversampling
• Internal bias current ensures maximum dynamic range
• Wide operating temperature range (-40 t +85 °C)
• Compatible with most current Japanese input formats:
– Time multiplexed
– Two’s complement
– TTL
• No zero-crossing distortion.
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
PINS
PIN POSITION
MATERIAL
CODE
TDA1310A
8
8
DIL8
SO8
plastic
plastic
SOT97DE
SOT96AG
TDA1310AT
May 1994
2
Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC
(CC-DAC)
TDA1310A
QUICK REFERENCE DATA
SYMBOL
VDD
IDD
IFS
PARAMETER
supply voltage
CONDITIONS
MIN.
TYP.
MAX.
5.5
UNIT
3
5.0
3.0
1.0
0.6
−65
V
supply current
VDD = 5 V at code 0000H
VDD = 5 V
−
4.0
1.1
−
mA
mA
mA
dB
%
full scale output current
0.9
−
V
DD = 3 V
(THD+N)/S
total harmonic distortion at 0 dB signal level
plus noise-to-signal ratio
−
−61
0.08
−
0.05
at −60 dB signal level
−
−
−
−
−
−30
3
−24
6
dB
%
at −60 dB signal level;
A-weighted
−33
2.2
1.7
−
dB
%
−
at −60 dB signal level;
A-weighted;
−
%
R3 = R4 = 11 kΩ;
(see Fig.1); IFS = 2 mA
S/N
tCS
signal-to-noise ratio at
bipolar zero
A-weighted at code 0000H
86
92
95
−
−
dB
dB
A-weighted; IFS = 2 mA;
R3 = R4 = 11 kΩ; see Fig.1
−
current settling time to
−
0.2
−
µs
±1 LSB
BR
fclk
input bit rate at data input
−
−
−
−
18.4
18.4
Mbits/s
MHz
clock frequency at clock
input BCK
TCFS
full scale temperature
coefficient at analog
−
±400 × 10−6
−
outputs (IOL; IOR
)
Tamb
Ptot
operating ambient
temperature
−40
−
+85
°C
total power dissipation
VDD = 5 V at code 0000H
VDD = 3 V at code 0000H
−
−
15
20
mW
mW
6.0
−
May 1994
3
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC
(CC-DAC)
TDA1310A
PINNING
SYMBOL
PIN
DESCRIPTION
bit clock input
BCK
WS
DATA
GND
VDD
IOL
1
2
3
4
5
6
7
8
word select input
data input
ground
supply voltage
left channel output
reference input
right channel output
Iref
IOR
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
The basic operation of the continuous calibration DAC is
illustrated in Fig.3. The figure shows the calibration and
operation cycle. During calibration of the MOS current
source (Fig.3a) transistor M1 is connected as a diode by
applying a reference current. The voltage Vgs on the
intrinsic gate-source capacitance Cgs of M1 is then
determined by the transistor characteristics. After
calibration of the drain current to the reference value Iref,
the switch S1 is opened and S2 is switched to the other
position (Fig.3b). The gate-to-source voltage Vgs of M1 is
not changed because the charge on Cgs is preserved.
Therefore, the drain current of M1 will still be equal to Iref
and this exact duplicate of Iref is now available at the OUT
terminal.
An internal bias current Ibias is added to the full scale
output current IFS in order to achieve the maximum
dynamic range at the outputs OP1 and OP2 in Fig.1.
The reference input current Iref controls with gain GFS, the
current IFS which is a sink current and with gain Gbias the
Ibias which is a source current(1).
The current Iref is proportional to VDD so the IFS and the Ibias
will be proportional to VDD as well(2) because GFS and Gbias
are constant.
The reference voltage Vref in Fig.1 is 2⁄3VDD. In this way
maximum dynamic range is achieved over the entire
power supply voltage range.
The 32 current sources and the spare current source of the
TDA1310A are continuously calibrated (see Fig.1). The
spare current source is included to allow continuous
converter operation. The output of one calibrated source is
connected to an 11-bit binary current divider consisting of
2048 transistors. A symmetrical offset decoding principle
is incorporated and arranges the bit switching in such a
way that the zero-crossing is performed only by switching
the LSB currents.
The tolerance of the reference input current in Fig.1
depends on the tolerance of the resistors R3, R4
(3)
and Rref
.
The TDA1310A (CC-DAC) accepts serial input data
formats of 16-bit word length. Left and right data words are
time multiplexed. The most significant bit (bit 1) must
always be first. The input data format is shown in
Figs 4 and 5.
(1) IFS = GFS x Iref and Ibias = Gbias x Iref
With a HIGH level on the word select input (WS), data is
placed in the left input register, with a LOW level on the
WS input, data is placed in the right input register
(see Fig.1). The data in the input registers are
simultaneously latched in the output registers which
control the bit switches.
VDD1
I FS1
I bias1
(2)
=
=
-------------
VDD2
----------
IFS2
-------------
Ibias2
VDD
-------------------------------------------------------------------------------------------------
R3 + ∆R3 + R4 + ∆R4 + Rref + ∆Rref
(3) ∆Iref = Iref
–
May 1994
5
Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC
(CC-DAC)
TDA1310A
Calibration principle
a.
b.
a. Calibration.
b. Operation.
Fig.3 Calibration principle.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VDD
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
supply voltage
−
6
V
Tstg
Txtal
Tamb
Ves
storage temperature
−55
−
+150
+150
+85
°C
°C
°C
V
maximum crystal temperature
operating ambient temperature
electrostatic handling
−40
note 1
note 2
−2000 +2000
−200 +200
V
Notes
1. Human body model; C = 100 pF; R = 1500 Ω; 3 zaps positive and negative.
2. Machine model; C = 200 pF; L = 0.5 µH; R = 10 Ω; 3 zaps positive and negative.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
PARAMETER
VALUE
UNIT
thermal resistance from junction to ambient in free air
DIL8
SO8
100
210
K/W
K/W
May 1994
6
Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC
(CC-DAC)
TDA1310A
CHARACTERISTICS
VDD = 5 V; Tamb = 25 °C; measured in Fig.1; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VDD
supply voltage
supply current
supply voltage ripple rejection note 1
3.0
5.0
3.0
30
5.5
V
IDD
at code 0000H
−
−
4.0
mA
dB
SVRR
−
Digital inputs; pins WS, BCK and DATA
|IIL|
|IIH|
fclk
input leakage current LOW
input leakage current HIGH
clock frequency
VI = 0 V
VI = 5 V
−
−
−
−
−
−
−
−
−
−
10
µA
10
µA
18.4
18.4
384
MHz
Mbits/s
kHz
BR
fWS
bit rate data input
word select input frequency
Timing (see Fig.4)
tr
rise time
−
−
−
−
−
−
−
−
−
−
12
12
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
tf
fall time
−
tCY
bit clock cycle time
bit clock pulse width HIGH
bit clock pulse width LOW
data set-up time
54
15
15
12
2
tBCKH
tBCKL
tSU;DAT
tHD:DAT
tHD:WS
tSU;WS
−
−
−
data hold time to bit clock
word select hold time
word select set-up time
−
2
−
12
−
Analog input; pin Iref
Rref
reference resistor
see Fig.1
7.4
11.0
14.6
16
kΩ
Analog outputs; pins IOL and IOR
RES
VDCC
IFS
resolution
−
−
bits
V
DC output voltage compliance
full-scale current
2.0
0.9
−
−
VDD − 1
1.0
±400 × 10−6
1.1
−
mA
TCFS
full-scale temperature
coefficient
Ibias
GFS
bias current
643
714
785
µA
reference input current to full
scale output current gain
11.9
13.2
14.5
Gbias
reference input current to bias
current gain
8.48
9.42
10.36
May 1994
7
Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC
(CC-DAC)
TDA1310A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
−61
UNIT
dB
(THD+N)/S total harmonic distortion plus at 0 dB signal level;
−
−
−
−
−
−
−
−65
noise-to-signal ratio
note 2
0.05
−30
3
0.08
−24
6
%
at −60 dB signal level;
note 2
dB
%
at −60 dB signal level;
A-weighted; note 2
−33
2.2
1.7
−
dB
%
−
at −60 dB signal level;
A-weighted; note 2;
R3 = R4 = 11 kΩ;
−
%
see Fig.1; IFS = 2 mA
at 0 dB signal level;
f = 20 Hz to 20 kHz
−
−
−
−65
0.05
0.2
95
−61
0.08
−
dB
%
tcs
current settling time to ±1 LSB
µs
dB
dB
αcs
|∆IO|
channel separation
86
−
unbalance between outputs
IOL and IOR
note 1
−
0.2
0.3
|td|
time delay between outputs
IOL and IOR
−
±0.2
92
−
−
−
µs
dB
dB
S/N
signal-to-noise ratio at bipolar A-weighted at code
zero
86
−
0000H
A-weighted; IFS = 2 mA;
R3 = R4 = 11 kΩ;
see Fig.1
95
Notes
1. Vripple = 1% of supply voltage; fripple = 100 Hz.
2. Measured with 1 kHz sine wave generated at sampling rate of 192 kHz.
May 1994
8
Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC
(CC-DAC)
TDA1310A
Fig.4 Timing and input signals.
Fig.5 Format of input signals.
May 1994
9
Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC
(CC-DAC)
TDA1310A
APPLICATION INFORMATION
Remark: the graphs are constructed from average measurement values of a small amount of engineering samples,
therefore no guarantee for typical values is implied.
Measured with a 1 kHz sinewave generated at a
sample frequency (fs) = 192 kHz.
(1) Measured within the specified operation supply voltage range
(3 to 5.5 V).
(2) Measured outside the specified operating supply voltage range
(2 to 3 V and 5.5 to 6 V).
Measured with a 1 kHz sinewave generated at a
sample frequency (fs) = 192 kHz.
Fig.6 Total harmonic distortion as a function
of supply voltage (4fs).
Fig.7 Total harmonic distortion as a function
of signal level (4fs).
May 1994
10
Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC
(CC-DAC)
TDA1310A
(1) Measured including all distortion plus noise at a signal level of −60 dB.
(2) Measured including all distortion plus noise at a signal level of 0 dB.
Fig.8 Total harmonic distortion as a function of frequency (4fs).
May 1994
11
Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC
(CC-DAC)
TDA1310A
PACKAGE OUTLINES
8.25
7.80
9.8
9.2
3.2
max
4.2
max
0.51
min
3.60
3.05
2.54
(3x)
0.254 M
0.38 max
1.15
max
0.53
max
7.62
1.73 max
10.0
8.3
MSA252 - 1
8
1
5
6.48
6.20
4
Dimensions in mm.
Fig.9 Plastic DIL, 8-pin (DIL8).
May 1994
12
Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC
(CC-DAC)
TDA1310A
4.0
3.8
5.0
4.8
a
A
6.2
5.8
S
0.1 S
0.7
0.3
8
1
5
4
0.7
0.6
1.45
1.25
1.75
1.35
0.25
0.19
1.0
0.5
0.25
0.10
o
0 to 8
pin 1
index
detail A
MBC180 - 1
1.27
0.49
0.36
0.25 M
(8x)
Dimensions in mm.
Fig.10 Plastic SO, 8-pin (SO8).
May 1994
13
Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC
(CC-DAC)
TDA1310A
A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.
SOLDERING
Plastic dual in-line packages
BY DIP OR WAVE
The maximum permissible temperature of the solder is
260 °C; this temperature must not be in contact with the
joint for more than 5 s. The total contact time of successive
solder waves must not exceed 5 s.
BY SOLDER PASTE REFLOW
Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be
applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified storage maximum. If the printed-circuit board has
been pre-heated, forced cooling may be necessary
immediately after soldering to keep the temperature within
the permissible limit.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250 °C.
REPAIRING SOLDERED JOINTS
Apply a low voltage soldering iron below the seating plane
(or not more than 2 mm above it). If its temperature is
below 300 °C, it must not be in contact for more than 10 s;
if between 300 and 400 °C, for not more than 5 s.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45 °C.
REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON OR PULSE-HEATED SOLDER TOOL)
Plastic small-outline packages
Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300 °C. When using proper tools, all other pins can be
soldered in one operation within 2 to 5 s at between 270
and 320 °C. (Pulse-heated soldering is not recommended
for SO packages.)
BY WAVE
During placement and before soldering, the component
must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150 °C within 6 s.
Typical dwell time is 4 s at 250 °C.
For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.
May 1994
14
Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC
(CC-DAC)
TDA1310A
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
May 1994
15
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Philips Semiconductors
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