TDA18218HN/C1,551 [NXP]

TDA18218HN - DVB-T Silicon Tuner IC QFN 48-Pin;


型号：	TDA18218HN/C1,551
厂家：	NXP
描述：	TDA18218HN - DVB-T Silicon Tuner IC QFN 48-Pin
文件：	总25页 (文件大小：127K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TDA18218HN

DVB-T Silicon Tuner IC

Rev. 01 — 8 July 2009

Product data sheet

1. General description

The TDA18218HN is a Silicon Tuner IC designed for digital terrestrial (DVB-T) TV

reception. The TDA18218HN integrates the overall tuning function, including selectivity

and provides a low-IF output signal.

The TDA18218HN uses integrated IF ﬁlters to support 6 MHz, 7 MHz or 8 MHz channel

bandwidths. The TDA18218HN requires only one single 16 MHz crystal for clock

generation. A clock signal is available on crystal oscillator output pins (XTO_P / XTO_N)

to synchronize the channel decoder.

The TDA18218HN is a low cost Silicon Tuner targeting digital terrestrial applications. The

TDA18218HN matches the performance of the conventional can tuners. Additionally, the

following beneﬁts can be stated:

• Easy on-board integration

• Drastically reduces:

– the size of the tuner function

– the power consumption

2. Features

I Fully integrated IF selectivity; eliminating the need for external SAW ﬁlters

I Fully integrated oscillators with no external components

I Integrated wideband gain control

I Alignment free

I RF loop-through for easy implementation in the Set-Top Box (STB)

I Integrated die thermal sensor

I Single 3.3 V power supply

I Low power consumption (750 mW)

I Crystal oscillator output buffer (16 MHz) for single crystal applications

I I²C-bus interface compatible with 3.3 V and 5 V microcontrollers

I Three Standby modes

I RoHS packaging

3. Applications

I DVB-T Set-Top Box (STB) and TV receiver

I System application optimization is described in the application note AN0814

I Driver application is described in the application note AN0822

TDA18218HN

NXP Semiconductors

DVB-T Silicon Tuner IC

4. Quick reference data

Table 1.

Quick reference data

T_amb= 25 °C; V_CC= 3.3 V; IF output level option = 2 V (p - p); IF output load = 1 kΩ on each terminal

Symbol Parameter

Conditions

Min Typ

Max Unit

f_RF

RF frequency

tuner noise ﬁgure

phase noise

center of channel

normal mode; maximum gain

worst case in the RF frequency range

10 kHz

174

864

MHz

NF_tun

ϕ_n

−85

−105

775

108

dBc/Hz

100 kHz

power dissipation

V_i(max)

α_image

S_dig

maximum input voltage 1 dB gain compression, one analog TV signal

dBµV

image rejection

digital sensitivity

normal mode

DVB-T (64 QAM 2/3); BER = 2 × 10⁻⁴

[1]

−82

dBm

[1] Measured with TDA10048 channel decoder.

5. Ordering information

Table 2.

Ordering information

Type number Package

Name

Description

Version

TDA18218HN HVQFN48 plastic thermal enhanced very thin quad ﬂat package; SOT619-1

no leads; 48 terminals; body 7 × 7 × 0.85 mm

6. Block diagram

AGC

SELECTIVITY

LPFc

AGC1

AGC2

FILTER

mixer

IFO_P

IFO_N

VIFAGC

RF_IN

LEVEL

CONTROL

TDA18218HN

ATTENUATOR

XTO_P

XTO_N

I C

CRYSTAL

OSCILATOR

SYNTHESIZER

INTERFACE

16 17

AS SCL

SDA

VTLO

CPLO XTAL_P

XTAL_N

001aaj012

Fig 1. Block diagram

TDA18218HN_1

Product data sheet

Rev. 01 — 8 July 2009

2 of 25

TDA18218HN

NXP Semiconductors

DVB-T Silicon Tuner IC

7. Pinning information

7.1 Pinning

terminal 1

index area

RF_IN

i.c.

SDA

SCL

i.c.

GND(DIG)

i.c.

GND(RF)

i.c.

VIFAGC

IFO_P

IFO_N

i.c.

TDA18218HN

GND(IF)

CC(IF)

i.c.

GND(IF)

REG28

REG18

VT_K

CAPREG_VCO

GND(VCO)

CC(PLL)

001aaj013

Transparent top view

Fig 2. Pin conﬁguration

7.2 Pin description

Table 3.

Pin description

Symbol

RF_IN

i.c.

Description

unbalanced RF input

internally connected; leave open

RF ground

i.c.

GND(RF)

i.c.

internally connected; leave open

IF ground

i.c

GND(IF)

V_CC(IF)

i.c.

IF supply voltage (3.3 V)

internally connected; leave open

VCO supply decoupling

VCO ground

CAPREG_VCO

GND(VCO)

V_CC(PLL)

GND(PLL)

VTLO

PLL supply voltage

PLL ground

local oscillator (LO) tuning voltage input

TDA18218HN_1

Product data sheet

Rev. 01 — 8 July 2009

3 of 25

TDA18218HN

NXP Semiconductors

DVB-T Silicon Tuner IC

Table 3.

Pin description …continued

Description

Symbol

CPLO

charge pump of the LO synthesizer

crystal oscillator input positive

XTAL_P

XTAL_N

i.c.

crystal oscillator input negative

internally connected; leave open

crystal oscillator output buffer positive

XTO_P

XTO_N

XTAL_MS

crystal oscillator output buffer negative

XTAL out mode

I²C-bus address selection input

IF ground

GND(IF)

CP_K

charge pump of the calibration synthesizer

tuning voltage of the calibration synthesizer

internal regulator decoupling

IF ground

VT_K

REG18

REG28

GND(IF)

V_CC(IF)

IFO_N

IFO_P

VIFAGC

i.c.

IF supply voltage (3.3 V)

IF output negative

IF output positive

IF gain control input

internally connected; leave open

GND(DIG)

SCL

digital ground

I²C-bus clock input

I²C-bus data input and output

SDA

CAPRFAGC

GND(RF)

i.c.

RF AGC ﬁltering

RF ground

internally connected; leave open

RF ground

GND(RF)

i.c.

RF ground

internally connected; leave open

RF ground

GND(RF)

V_CC(RF)

RF supply voltage

loop-through

V_CC(RF)

i.c.

RF supply voltage

internally connected; leave open

8. Functional description

The RF input signal is driven to a low-noise ampliﬁer. It is then ampliﬁed and fed to the

image rejection mixer. The mixer down-converts the RF signal to a low IF frequency, which

depends on channel bandwidth (standard IF ﬁlters are implemented for 6 MHz, 7 MHz

TDA18218HN_1

Product data sheet

Rev. 01 — 8 July 2009

4 of 25

TDA18218HN

NXP Semiconductors

DVB-T Silicon Tuner IC

and 8 MHz channel bandwidths). The TDA18218HN requires a single 16 MHz crystal for

clock generation, a 16 MHz differential sine wave clock reference is available to drive a

channel decoder.

8.1 AGC1 stage

The TDA18218HN embeds 2 different RF ampliﬁers with internal gain control.

The ﬁrst stage, AGC1, behaves like a LNA (Low noise ampliﬁer); its gain can take 4

different values (15 dB, 12 dB, 9 dB and 6 dB). Purpose of this ampliﬁer is to ensure a low

noise ﬁgure for the tuner.

In order to optimize noise and linearity performances an internal level detector selects the

appropriate gain:

• If the signal level at the tuner is low, the gain is set to the maximum value (15 dB).

• If the signal level at the tuner input is high, the gain is set to the minimum value (6 dB).

• In between the gain is set to an intermediate value 12 dB or 9 dB.

The strategy of the level detection is a proprietary algorithm from NXP, managed by the

driver.

It should be noted that:

1. The level detector measures the signal level within the complete RF frequency range,

i.e. from 50 MHz to 870 MHz. Consequently, AGC1 gain is adapted to the complete

RF power. If a strong signal is present at the tuner input, it will determine AGC1 gain

(even if it is not the wanted signal). This concept prevents the tuner from overloading.

2. The level control is always operating.

8.2 AGC2 stage

The second stage, AGC2, is also an ampliﬁer with a gain controlled thanks to a level

detector.

The gain is controlled between −12 dB and +16.4 dB, it is adapted by steps of 0.2 dB.

It should be noted that:

1. The level control is always operating. Consequently, this ampliﬁer is responsible for

adapting the daily level changes.

2. The level detector measures the signal level within the complete RF frequency range

(same as AGC1)

The strategy of the level detection is a proprietary algorithm from NXP, managed by the

driver.

8.3 IF AGC

Finally, in order to adapt the tuner output level, a last ampliﬁer is used (IF AGC). This

ampliﬁer delivers the appropriate level to the DVB-T channel decoder. The output level is

therefore controlled thanks to the DC voltage applied on VIFAGC pin. This voltage is

commonly delivered by the channel decoder.

TDA18218HN_1

Product data sheet

Rev. 01 — 8 July 2009

5 of 25

TDA18218HN

NXP Semiconductors

DVB-T Silicon Tuner IC

It should be noted that the level control is always operating.

The strategy of the level detection has to be adapted for each type of channel decoder. It

must be deﬁned to satisfy ADC sampling (minimum level, ADC headroom).

All AGC ampliﬁers are controlled independently.

8.4 Power-down mode

The TDA18218HN can be programmed in Standby mode. The following blocks are turned

off when programming a power-down:

• AGC2 and its level detector

• BP ﬁlter

• Mixer and VCO

• IF selectivity LPFc

• IF AGC

Remaining functions are:

• Loop-Through

• 16 MHz clock output (to drive a channel decoder)

• I²C-bus Core (to wake-up the IC later on)

9. Control interface

9.1 I²C-bus format, write and read mode

I²C-bus uses two pins (SDA and SCL) to transfer information between devices connected

to the bus. The SDA pin provides bidirectional data transfer. While the SCL pin provides

the timing sequences. Data can be read and written as follows:

Write mode:

• Any register can be written to using its subaddress

• Any following (contiguous) registers can be written using the subaddress of the ﬁrst

Read mode:

• The read after Restart mode is not allowed. In addition, registers cannot be read using

the subaddress of the register. However, registers can be read as follows:

– from 00h to 16h

– from 00h to 27h

– from 00h to 3Ah

– from 00h to any register subaddress, if MSB = 1 for the next register

TDA18218HN_1

Product data sheet

Rev. 01 — 8 July 2009

6 of 25

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Table 4.

I²C-bus register map

Sub

address

Bit

Initial POR

value (Hex)

(Hex)

7 (MSB)

0 (LSB)

Address byte 1

Address byte 2

ID byte

MA[1:0]

R/W

AD[5:0]

LT[1:0]

00h

01h

02h

03h

04h

05h

06h

07h

ID[6:0]

C0^[1]

Read byte 1

Read byte 2

Read byte 3

Read byte 4

Read byte 5

Read byte 6

LO_Lock

CAL_Lock

TM_D[3:0]

AGC2[7:0]

AGC1[2]

AGC1[1:0]

Main divider

byte 1

08h

09h

PSM byte 1

Main divider

byte 2

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

Main divider

byte 3

LO_Frac_0[31:24]

LO_Frac_1[23:16]

Main divider

byte 4

Main divider

byte 5

LO_Frac_2[15:12]

Main divider

byte 6

Main divider

byte 7

Main divider

byte 8

Freq_prog_

Start

Call divider

byte 1

Call divider

byte 2

Call divider

byte 3

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Table 4.

I²C-bus register map …continued

Sub

address

Bit

Initial POR

value (Hex)

(Hex)

7 (MSB)

0 (LSB)

13h

14h

15h

16h

17h

Call divider

byte 4

Call divider

byte 5

Call divider

byte 6

Call divider

byte 7

Power-down

byte 1

pdLT

pdAGC1b

PD_RFAGC

_Ifout

PD_LO_

Synthe

F0^[2]

B0^[3]

19^[2]

59^[3]

18h

Power-down

byte 2

RFSW_MTO

_LT_RFin

pdDETECT1

pdAGC2b

19h

1Ah

1Bh

1Ch

XTOUT byte

IF byte 1

XtOut[3:0]

BP_Filter[2:0]

LP_Fc[1:0]

IF_level[2:0]

IF byte 2

AGC2b byte

pulse_up_

auto

pulse_up_

width[1:0]

AGC_On

1Dh

PSM byte 2

TM_

TM_ON

Range

1Eh

1Fh

PSM byte 3

PSM byte 4

AGC1_Speed[1:0]

AGC1_

aud_sel

AGC1_au_ptr[1:0]

AGC1_aud[2:0]

20h

AGC1 byte 1

AGC2_RAM_sel[1:0]

AGC2_Speed[1:0]

AGC2_

Gup_sel

AGC1_

Gup_sel

Manual_LT

21h

22h

23h

24h

25h

AGC1 byte 2

AGC1 byte 3

AGC2 byte 1

AGC2 byte 2

AGC1_Gud[4:0]

AGC2_Gud[4:0]

Analog AGC

byte

IFAGC_Top[3:0]

26h

27h

RC byte

RSSI byte

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Table 4.

I²C-bus register map …continued

Sub

address

Bit

Initial POR

value (Hex)

(Hex)

7 (MSB)

0 (LSB)

28h

29h

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

35h

36h

IR CAL byte 1

IR CAL byte 2

IR CAL byte 3

IR CAL byte 4

RF CAL byte 1

RF CAL byte 2

RF CAL byte 3

RF CAL byte 4

RF CAL byte 5

RF CAL byte 6

RF CAL byte 7

RF CAL byte 8

RF CAL byte 9

RF CAL byte 10

RF CAL RAM

byte 1

37h

RF CAL RAM

byte 2

38h

39h

3Ah

Margin byte

Fmax byte 1

Fmax byte 2

[1] See Section 9.2.1 “Device type address ID”.

[2] Case TDA18218HN is a device without LT.

[3] Case TDA18218HN is a device with LT.

TDA18218HN

NXP Semiconductors

DVB-T Silicon Tuner IC

9.2 I²C-bus address selection

The programmable module address bits MA[1:0] allow up to four tuners to be addressed

in one system. Bits MA[1:0] are programmed by applying a speciﬁc voltage (V_AS) to pin

AS. The relationship between the status of bits MA[1:0] and the voltage applied to pin AS

is shown in Table 5.

Table 5.

Address byte 1 bit descriptions

Legend: * power-on reset value.

Bit

Symbol

Access

R/W

Value

Description

7 to 3

2 to 1

1 1000*

must be set to 1 1000

programmable address bit value set with V_AS

V_AS= 0 V to 0.1 × V_CC

V_AS= 0.2 × V_CCto 0.3 × V_CC

V_AS= 0.4 × V_CCto 0.6 × V_CC

V_AS= 0.9 × V_CCto V_CC

write mode

MA[1:0]

R/W

read mode

Example: MA[1:0] = 00, R/W = 0, full module address = 1100 0000 (C0h).

Table 6.

Address byte 2 bit descriptions

Legend: * power-on reset value.

Bit

Symbol

Access

R/W

Value

00*

Description

7 to 6

5 to 0

must be set to 00

AD[5:0]

R/W

programmable address bits of the ﬁrst

programming byte

9.2.1 Device type address ID

Table 7.

ID byte bit descriptions

Legend: * power-on reset value.

Address

Bit

Symbol

Access Value

Description

00h

ID byte

must be 1

6 to 0

ID[6:0]

100 0000*

TDA18218HN device type address

9.3 Crystal buffer output

TDA18218HN embeds a Xtal oscillator and a buffer to drive another IC. The buffer can be

conﬁgured through register XTOUT (I²C-bus sub address 19h). This buffer has been

designed to be AC coupled. This output can be used in differential or sinusoidal mode

(using XTO_N and XTO_P pins) or in asymmetrical or square mode (just leaving one pin

open).

It should be noted that TDA18218HN speciﬁcation refers to differential output with no

load.

TDA18218HN_1

Product data sheet

Rev. 01 — 8 July 2009

10 of 25

TDA18218HN

NXP Semiconductors

DVB-T Silicon Tuner IC

Table 8.

Address Register

19h XTOUT byte 3 to 0 XtOut[3:0] R/W

Crystal buffer output register bit descriptions

Bit Symbol Access Value

Description

crystal buffer output

XTAL off

XTOUT off

square wave 16 MHz

sine wave 200 mV

sine wave 400 mV

sine wave 800 mV

sine wave 1200 mV

not applicable

other

9.4 Temperature sensor

Table 9.

Temperature sensor bit descriptions

Address Register

Bit

Symbol

Access Value Description

temperature sensor on or off

1Dh

PSM byte 2

TM_ON

temperature sensor switched off

temperature sensor switched on

temperature range selection

60 °C to 90 °C

TM_Range R/W

92 °C to 122 °C

die temperature^[1]

01h

Read byte 1 3 to 0 TM_D[3:0]

[1] The die temperature can be read as shown in Table 10.

Table 10. Die temperature values

TM_D[3:0]

Temperature range selection (die temperature)

TM_RANGE = 0

60 °C

TM_RANGE = 1

92 °C

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

62 °C

94 °C

66 °C

98 °C

64 °C

96 °C

74 °C

106 °C

104 °C

100 °C

102 °C

122 °C

120 °C

116 °C

118 °C

108 °C

72 °C

68 °C

70 °C

90 °C

88 °C

84 °C

86 °C

76 °C

TDA18218HN_1

Product data sheet

Rev. 01 — 8 July 2009

11 of 25

TDA18218HN

NXP Semiconductors

DVB-T Silicon Tuner IC

Table 10. Die temperature values …continued

TM_D[3:0]

Temperature range selection (die temperature)

TM_RANGE = 0

78 °C

TM_RANGE = 1

110 °C

1101

1110

1111

82 °C

114 °C

80 °C

112 °C

9.5 Standby mode selection

Table 11. Standby mode selection

Mode

Power down byte 1 (address 17h)

SM (bit 0) pdAGC1b (bit 3) XTOUT

Device-off mode

see Table 8

Standby mode with loop-through and crystal

oscillator on (default at POR), XTOUT 1200 mV

Standby mode with only crystal oscillator on

see Table 8

9.6 IF level

Refer to Table 21 “General characteristics for TV reception (RF input to IF output)”.

9.7 AGC and band-pass ﬁlters

Table 12. AGC and band-pass ﬁlter bit descriptions

Address Register Bit Symbol Access Value Description

03h

Read byte 3

7 to 0 AGC2[7:0]

R/W

AGC2 gain = 0.2 × (AGC2[7:0]) − 12 (dB)

range = −12 dB to 16.4 dB

04h

Read byte 4

7 and AGC1[2:0]

1 to 0

R/W

AGC1 gain range = 6 dB to 15 dB

6 dB

9 dB

12 dB

15 dB

1Ah

IF byte 1

2 to 0 BP_Filter[2:0]

band-pass ﬁlters

ﬁlter 3 (174 MHz to 188 MHz)

ﬁlter 4 (188 MHz to 253 MHz)

ﬁlter 5 (253 MHz to 343 MHz)

ﬁlter 6 (343 MHz to 870 MHz; bypass)

1Bh

1Ch

IF byte 2

1 to 0 LP_Fc[1:0]

low-pass ﬁlter cut-off frequency

6 MHz

7 MHz

8 MHz

AGC2b byte

AGC_On

AGC1 and AGC2 clock on or off

off

TDA18218HN_1

Product data sheet

Rev. 01 — 8 July 2009

12 of 25

TDA18218HN

NXP Semiconductors

DVB-T Silicon Tuner IC

9.8 RFin to LT path

Table 13. RFin to LT path bit descriptions

Address Register

Bit

Symbol

Access Value Description

20h

AGC1 byte 1

Manual_LT

loop-through command

sets LT attenuation depending on state of pin

XTAL_MS; see Table 14

sets LT attenuation manually; see Table 15

sets LT gain in range: −6 dB to −15 dB; see Table 15

04h

Read byte 4

3 to 2 LT[1:0]

R/W

Table 14. RFin to LT gain control modes

Bit Manual_LT Pin XTAL_MS AGC1 and LT attenuator gain modes

LOW

HIGH

LOW

AGC1 gain ﬁxed at 6 dB; LT gain set by LT[1:0]; see Table 15

LT gain set automatically function of AGC1 gain; see Table 15

AGC1 gain ﬁxed at gain set by AGC1[2:0]; LT gain set by LT[1:0];

see Table 15

HIGH

AGC1 gain set automatically; LT gain set by LT[1:0]; see

Table 15

Table 15. Loop-through attenuator gain settings

LT[1]

LT[0]

Loop-through gain

−6 dB

−9 dB

−12 dB

−15 dB

9.9 PLL settings

Table 16. PLL bit descriptions

Address Register Bit

Symbol

Access Value Description

0Ah

0Bh

0Ch

01h

Main divider byte 3 7 to 0 LO_Frac_0[31:24] R

Main divider byte 4 7 to 0 LO_Frac_1[23:16]

Main divider byte 5 7 to 4 LO_Frac_2[15:12]

LO frequency setting (kHz); in automatic mode

Read byte 1

LO_Lock

LO lock ﬂag

PLL unlocked

PLL locked

CAL_Lock

calibration oscillator lock ﬂag

PLL unlocked

PLL locked

0Fh

Main divider byte 8 6

Freq_prog_Start

launch automatic mode of PLL calculation (LO

and calibration synthesizer); automatically

reset to logic 0 (internally) when LO and

calibration are completed

TDA18218HN_1

Product data sheet

Rev. 01 — 8 July 2009

13 of 25

TDA18218HN

NXP Semiconductors

DVB-T Silicon Tuner IC

9.10 Power-down and switches

Table 17. Power-down and switches bit descriptions

Address Register Bit Symbol

Acces Value Description

17h

Power-down byte 1

pdLT

R/W

loop-through output switch

closed

open

pdAGC1b

PD_RFAGC_Ifout

PD_LO_Synthe

AGC1 power-down^[1]

LNA on

LNA off

mixer and IF stages power-down

blocks on

blocks off

LO synthesizer power-down

PLL on

PLL off

Standby mode; I²C-bus interface, crystal

oscillator and AGC1 are turned on

normal

standby

18h

Power-down byte 2

RFSW_MTO_LT_RFin R/W

provides the RF signal to the

loop-through^[2]

switch is open

switch is closed

AGC1 detector power-down

detector on

pdDETECT1

pdAGC2b

detector off

AGC2 power-down^[1]

LNA on

LNA off

[1] This setting controls the status of the Low Noise Ampliﬁer (LNA).

[2] RFSW_MTO_LT_RFin = 0 in tuner applications with loop-through disabled.

RFSW_MTO_LT_RFin = 1 in tuner applications with loop-through enabled.

10. Limiting values

Table 18. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions

V_CCsupply voltage

Min

Max

Unit

−0.3

+3.60

TDA18218HN_1

Product data sheet

Rev. 01 — 8 July 2009

14 of 25

TDA18218HN

NXP Semiconductors

DVB-T Silicon Tuner IC

Table 18. Limiting values …continued

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter

Conditions

Min

Max

Unit

V_I

input voltage

pins SDA and SCL

all other pins

V_CC< 3.3 V

−0.3

+5.5

−0.3

−40

V_CC+ 0.3

+3.6

+150

+95

V_CC> 3.3 V

T_stg

T_j

storage temperature

°C

junction temperature

V_ESD

electrostatic discharge voltage

EIA/JESD22-A114

±2000

(human body model)

EIA/JESD22-C101-C

(FCDM) class III^[1]

±200

[1] Class III: 200 V to 1000 V.

11. Thermal characteristics

Table 19. Thermal characteristics

Symbol Parameter Conditions

thermal resistance from according to JEDEC speci-

Min

Typ

Max

Unit

R_th(j-a)

29.9

K/W

junction to ambient

ﬁcation 4L board with 16

thermal vias

T_amb

ambient temperature

+70

°C

12. Characteristics

Table 20. Loop-through characteristics (RF input to loop-through output)

T_amb= 25 °C, V_CC= 3.3 V; unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min Typ Max Unit

f_RF(lt)

loop-through RF frequency

center of channel

864 MHz

|s₁₁

|s₂₂

input return loss

75 Ω nominal impedance

75 Ω load

−8

dBc

output return loss

G_v(lt)

∆G_lt

loop-through voltage gain

loop-through gain variation

loop-through noise ﬁgure

−0.5 -

in the RF frequency range; 75 Ω load

maximum gain

NF_lt

[1]

CSO_lt

loop-through composite second-order

distortion

−51

CTB_lt

loop-through composite triple beat

bypass isolation

−55

dBc

α_isol(bp)

from loop-through output to RF input

[1] Channel loading assumptions: 129 channels at 75 dBµV.

TDA18218HN_1

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DVB-T Silicon Tuner IC

Table 21. General characteristics for TV reception (RF input to IF output)

T_amb= 25 °C, V_CC= 3.3 V, IF output level option 2 V (p - p), IF output load = 1 kΩ on each pin; unless otherwise speciﬁed.

Symbol

V_CC

Parameter

Conditions

Min Typ

Max Unit

supply voltage

supply current

3.13 3.30

3.47

[1]

I_CC

normal mode

235^[2]270^[3]mA

device-off mode

Standby mode with loop-through

and crystal oscillator on (default at

POR), XTOUT 1200 mV

Standby mode with only oscillator on

775

power dissipation

RF frequency

MHz

f_RF

center of channel

174

864

f_IF(nom)

nominal IF frequency

center of channel; for channel band-

width

6 MHz

MHz

7 MHz

3.5

8 MHz

G_v

voltage gain

normal mode

normal mode; maximum gain

∆G_AGC(tun)

NF_tun

tuner AGC gain range

tuner noise ﬁgure

V_{o(IF)dif(p-p)}

peak-to-peak differential IF output IF_level[2:0] = 000

voltage

IF_level[2:0] = 010

IF_level[2:0] = 111

0.5

100

Z_o(IF)

IF output impedance

IF AGC GAIN range

differential mode; magnitude value

Ω

∆G_AGC(IF)

2 V (peak-to-peak) IF output volt-

age selection

[4]

G_tlt

tilt gain

RF frequency range

6 MHz IF ﬁlter (1 MHz to 5.5 MHz)

7 MHz IF ﬁlter (1 MHz to 6.5 MHz)

8 MHz IF ﬁlter (1 MHz to 7.5 MHz)

f_IF(stpb)lp

low-pass stop-band IF frequency 60 dB attenuation

6 MHz IF ﬁlter (1 MHz to 5.5 MHz)

MHz

7 MHz IF ﬁlter (1 MHz to 6.5 MHz)

8 MHz IF ﬁlter (1 MHz to 7.5 MHz)

normal mode

α_image

image rejection

group delay time

t_d(grp)

normal mode

6 MHz IF ﬁlter (1 MHz to 5.5 MHz)

7 MHz IF ﬁlter (1 MHz to 6.5 MHz)

8 MHz IF ﬁlter (1 MHz to 7.5 MHz)

155

165

175

ϕ_n

phase noise

worst case in the RF frequency

range

10 kHz

100 kHz

−85

−105

dBc/Hz

t_startup(tun)

tuner start-up time

at power-up

TDA18218HN_1

Product data sheet

Rev. 01 — 8 July 2009

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TDA18218HN

NXP Semiconductors

DVB-T Silicon Tuner IC

Table 21. General characteristics for TV reception (RF input to IF output) …continued

T_amb= 25 °C, V_CC= 3.3 V, IF output level option 2 V (p - p), IF output load = 1 kΩ on each pin; unless otherwise speciﬁed.

Symbol

t_set

Parameter

Conditions

Min Typ

Max Unit

setting time

channel change

f_tun(step)

V_i(max)

tuner frequency (step size)

maximum input voltage

kHz

dBµV

1 dB gain compression, one analog

TV signal

108

[5]

S_dig

digital sensitivity

DVB-T (64 QAM 2/3);

BER = 2 × 10⁻⁴

−82

dBm

[1] XTAL buffer off.

[2] Measured at 3.3 V.

[3] Measured at 3.47 V.

[4] Difference deﬁned between maximum and minimum over the IF bandwidth.

[5] Measured with TDA10048 channel decoder.

Table 22. Pin characteristics

T_amb= 25 °C, V_CC= 3.3 V; unless otherwise speciﬁed

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

IF AGC input: pin VIFAGC

V_AGC

Z_i

AGC voltage

V_CC

[1]

input impedance

MΩ

dB/V

dG_AGC/dV rate of change of AGC gain

with voltage

Crystal oscillator

f_xtal

Z_i

crystal frequency

input impedance

MHz

magnitude value; crystal

speciﬁcation: R_s= 150 Ω max;

drive level < 100 µW

500

Ω

Crystal oscillator output buffer

Square mode: only on XTO_N (XtOut[3:0] = 2)

R_o

output resistance

16 MHz output frequency

Ω

V_o(p-p)

peak-to-peak output voltage 10 kΩ; 10 pF AC load; same load

0.6

on XTO_P and XTO_N

SR_r

SR_f

slew rate of rising signal

slew rate of falling signal

10 kΩ; 10 pF AC load

150

V/µs

Sinusoidal mode: on XTO_P and XTO_N (XtOut[3:0] = 8)

R_o

output resistance

16 MHz output frequency

480

0.4

Ω

V_o(p-p)

peak-to-peak output voltage 10 kΩ; 10 pF AC load; same load

on XTO_P and XTO_N

Digital levels I²C-bus^[2]

Pin SCL

V_IL

LOW-level input voltage

ﬁxed input levels

1.5

V_DDrelated input levels

ﬁxed input levels

0.3 × V_CC

V_IH

HIGH-level input voltage

V_DDrelated input levels

0.7 × V_CC

TDA18218HN_1

Product data sheet

Rev. 01 — 8 July 2009

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DVB-T Silicon Tuner IC

Table 22. Pin characteristics …continued

T_amb= 25 °C, V_CC= 3.3 V; unless otherwise speciﬁed

Symbol

f_SCL

Parameter

Conditions

Min

Typ

Max

Unit

SCL clock frequency

400

kHz

pin SDA

V_OH

HIGH-level output voltage

LOW-level input voltage

I_SDA= 3 mA (sink current)

ﬁxed input levels

0.4

V_IL

1.5

V_DDrelated input levels

ﬁxed input levels

0.3 × V_CC

V_IH

HIGH-level input voltage

V_DDrelated input levels

0.7 × V_CC

[1] Typical value is HIGH impedance input.

[2] Devices that use non-standard supply voltages, which do not conform to the intended I²C-bus system levels, must relate their input

levels to the supply voltage to which the pull-up resistors are connected.

TDA18218HN_1

Product data sheet

Rev. 01 — 8 July 2009

18 of 25

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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

13. Application information

1 nF

150 pF

+3V3_TUN

47 nF

+3V3_TUN

47 nF

1 µH

BLM18HK102SNI

BAV99W

470 pF

220 nF

+3V3_TUN

4.7 kΩ

48 47 46 45 44 43 42 41 40 39 38 37

1 nF

150 pF

RF_IN

SDA

RF_IN_OUT

i.c.

SCL

1 µH

BAV99W

GND(DIG)

i.c.

BLM18HK102SNI

V_IF_AGC

GND(RF)

i.c.

100 nF

VIFAGC

IFO_P

IFO_N

i.c.

IF OUT P

+3V3_TUN

100 nF

TDA18218HN

GND(IF)

IF OUT N

CC(IF)

i.c.

47 nF

470 pF

100 nF

+3V3_TUN

GND(IF)

REG28

REG18

VT_K

470 pF

47 nF

CAPREG_VCO

GND(VCO)

GND

CC(PLL)

10 nF

100 nF

13 14 15 16 17 18 19 20 21 22 23 24

220 nF

3.9 nF

6.8 nF

120 Ω

470 pF

U14

390 Ω

47 nF

+3V3_TUN

220 nF

0.75 pF

390 Ω

4.7 nF

18 pF

XTOUT

1 nF

6.8 nF

390 Ω

(1)

Cxtal

QZ3

16 MHz

18 pF

001aaj014

(1) Cxtal not connected for NDK; Cxtal = 1.5 pF for Siward.

Fig 3. Application diagram

TDA18218HN

NXP Semiconductors

DVB-T Silicon Tuner IC

14. Package outline

HVQFN48: plastic thermal enhanced very thin quad flat package; no leads;

48 terminals; body 7 x 7 x 0.85 mm

SOT619-1

terminal 1

index area

detail X

1/2 e

terminal 1

index area

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

UNIT

max.

0.05 0.30

0.00 0.18

7.1

6.9

5.25

4.95

7.1

6.9

5.25

4.95

0.5

0.3

0.05

0.1

0.2

0.5

5.5

0.1 0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

01-08-08

02-10-18

SOT619-1

- - -

MO-220

- - -

Fig 4. Package outline HVQFN48 - SOT619-1

TDA18218HN_1

Product data sheet

Rev. 01 — 8 July 2009

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DVB-T Silicon Tuner IC

15. Abbreviations

Table 23. Abbreviations

Acronym

ADC

AGC

BER

Description

Analog-to-Digital Converter

Automatic Gain Control

Bit Error Rate

Band-Pass

Cxtal

DVB-T

DVR

FCDM

crystal Capacitor

Digital Video Broadcasting – Terrestrial

Digital Video Recorder

Flow Control Decision Message

Integrated Circuit

Intermediate Frequency

Low Noise Ampliﬁer

Low Pass Frequency cut

Local Oscillator

LNA

LPFc

Loop-Through

MSB

PCB

PLL

Most Signiﬁcant Bit

Printed-Circuit Board

Phase-Locked Loop

Power-On Reset

POR

QAM

Quadrature Amplitude Modulation

Radio Frequency

RoHS

SAW

STB

TOP

VCO

XTAL

Restriction of Hazardous Substances

Surface Acoustic Wave

Set-Top Box

Take-Over Point

Voltage Controlled Oscillator

Crystal

TDA18218HN_1

Product data sheet

Rev. 01 — 8 July 2009

21 of 25

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DVB-T Silicon Tuner IC

16. Revision history

Table 24. Revision history

Document ID

Release date

20090708

Data sheet status

Change notice

Supersedes

TDA18218HN_1

Product data sheet

TDA18218HN_1

Product data sheet

Rev. 01 — 8 July 2009

22 of 25

TDA18218HN

NXP Semiconductors

DVB-T Silicon Tuner IC

17. Legal information

18. Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Applications — Applications that are described herein for any of these

18.1 Deﬁnitions

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

18.2 Disclaimers

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

18.3 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I²C-bus — logo is a trademark of NXP B.V.

Silicon Tuner — is a trademark of NXP B.V.

19. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

TDA18218HN_1

Product data sheet

Rev. 01 — 8 July 2009

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DVB-T Silicon Tuner IC

20. Tables

Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .2

Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .2

Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .3

Table 4. I²C-bus register map . . . . . . . . . . . . . . . . . . . . .7

Table 5. Address byte 1 bit descriptions . . . . . . . . . . . .10

Table 6. Address byte 2 bit descriptions . . . . . . . . . . . .10

Table 7. ID byte bit descriptions . . . . . . . . . . . . . . . . . .10

Table 8. Crystal buffer output register bit descriptions .11

Table 9. Temperature sensor bit descriptions . . . . . . . .11

Table 10. Die temperature values . . . . . . . . . . . . . . . . . .11

Table 11. Standby mode selection . . . . . . . . . . . . . . . . .12

Table 12. AGC and band-pass ﬁlter bit descriptions . . . .12

Table 13. RFin to LT path bit descriptions . . . . . . . . . . . .13

Table 14. RFin to LT gain control modes . . . . . . . . . . . . 13

Table 15. Loop-through attenuator gain settings . . . . . . 13

Table 16. PLL bit descriptions . . . . . . . . . . . . . . . . . . . . . 13

Table 17. Power-down and switches bit descriptions . . . 14

Table 18. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 19. Thermal characteristics . . . . . . . . . . . . . . . . . . 15

Table 20. Loop-through characteristics

(RF input to loop-through output) . . . . . . . . . . 15

Table 21. General characteristics for TV reception

(RF input to IF output) . . . . . . . . . . . . . . . . . . . 16

Table 22. Pin characteristics . . . . . . . . . . . . . . . . . . . . . . 17

Table 23. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 24. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 22

21. Figures

Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Fig 2. Pin conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . .3

Fig 3. Application diagram . . . . . . . . . . . . . . . . . . . . . . .19

Fig 4. Package outline HVQFN48 - SOT619-1 . . . . . . .20

TDA18218HN_1

Product data sheet

Rev. 01 — 8 July 2009

24 of 25

TDA18218HN

NXP Semiconductors

DVB-T Silicon Tuner IC

22. Contents

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Quick reference data . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2

7.1

7.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

Functional description . . . . . . . . . . . . . . . . . . . 4

AGC1 stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

AGC2 stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

IF AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Power-down mode . . . . . . . . . . . . . . . . . . . . . . 6

8.1

8.2

8.3

8.4

Control interface . . . . . . . . . . . . . . . . . . . . . . . . 6

I²C-bus format, write and read mode . . . . . . . . 6

I²C-bus address selection. . . . . . . . . . . . . . . . 10

Device type address ID. . . . . . . . . . . . . . . . . . 10

Crystal buffer output . . . . . . . . . . . . . . . . . . . . 10

Temperature sensor . . . . . . . . . . . . . . . . . . . . 11

Standby mode selection . . . . . . . . . . . . . . . . . 12

IF level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

AGC and band-pass ﬁlters . . . . . . . . . . . . . . . 12

RFin to LT path . . . . . . . . . . . . . . . . . . . . . . . . 13

PLL settings . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Power-down and switches . . . . . . . . . . . . . . . 14

9.1

9.2

9.2.1

9.3

9.4

9.5

9.6

9.7

9.8

9.9

9.10

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 14

Thermal characteristics. . . . . . . . . . . . . . . . . . 15

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 15

Application information. . . . . . . . . . . . . . . . . . 19

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 20

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 21

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 22

18.1

18.2

18.3

Legal information. . . . . . . . . . . . . . . . . . . . . . . 23

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Contact information. . . . . . . . . . . . . . . . . . . . . 23

Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 8 July 2009

Document identifier: TDA18218HN_1

TDA18218HN/C1,551 [NXP]

相关型号：

TDA18218HN/C1,557

TDA18219HN/C1

TDA18219HN/C1,518

TDA18219HN/C1,557

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TDA18250HN

TDA18250HN/C1

TDA18250HN/C1,551

TDA18250HN/C1/S1,5

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