TDA19997HL [NXP]
IC SPECIALTY CONSUMER CIRCUIT, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, 0.5 MM PITCH, LEAD FREE, PLASTIC, MS-026, SOT-407-1, LQFP-100, Consumer IC:Other;
| 型号： | TDA19997HL |
| 厂家： | 
NXP |
| 描述： | IC SPECIALTY CONSUMER CIRCUIT, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, 0.5 MM PITCH, LEAD FREE, PLASTIC, MS-026, SOT-407-1, LQFP-100, Consumer IC:Other 商用集成电路 |
| 文件： | 总26页 (文件大小：305K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TDA19997HL
Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer
Rev. 02 — 22 December 2009
Product data sheet
1. General description
The High-Definition Multimedia Interface (HDMI) switch enables connection of multiple
DVI/HDMI inputs to a receiver with at least one input. The TDA19997HL is a switch with
four HDMI 1.4 compliant DVI/HDMI inputs and one DVI/HDMI output. Each HDMI input
has its own dedicated embedded EDID memory. A fifth DDC-bus input is available for
VGA or second HDMI input of SoC. The built-in auto-adaptive equalizer improves signal
quality, allowing the use of cable lengths up to 30 m.
The TDA19997HL supports Deep Color mode in 10-bit and 12-bit per channel up to
1920 × 1080p at 50/60 Hz. The TDA19997HL supports DVI/HDMI streams with or without
High-bandwidth Digital Content Protection (HDCP 1.3) and all Data Island packets.
The TDA19997HL settings are controllable via the I2C-bus.
2. Features
Complies with the HDMI 1.4, DVI 1.0, EIA/CEA-861D and HDCP 1.3 standards
Four independent DVI/HDMI inputs, up to 2.25 gigasamples per second
Pin compatible with TDA9996/TDA9995
Robust auto-adaptive equalizer (up to 20 m AWG26 at 2.25 Gbit/s)
Robust auto-adaptive equalizer (up to 30 m AWG24 at 1.5 Gbit/s)
Integrated 50 Ω single-ended termination resistors
+5 V signal detection for each HDMI input
Supports color depth processing at 24-bit, 30-bit or 36-bit per pixel
Supports all Data Island packets
Activity detection on each input, manages output activity and power consumption
Extended mode: re-generate output TMDS waveform removing jitter and skew
Frequency measurement allowing direct reading of format/resolution
Automatic mode for main features:
Automatic Hot Plug Detect (HPD) generation and termination resistors
management
Automatic HPD generation with programmable duration
Automatic EDID load
Display Data Channel (DDC) bus:
5 V tolerant, DDC-bus inputs with bit rates up to 400 kbit/s
One DDC-bus output with the same latency as the HDMI stream pipeline delay
DDC-bus master switch functionality avoids bus corruption
TDA19997HL
NXP Semiconductors
Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer
DDC-bus level-shifting buffer with digital lock-up protection
A fifth DDC-bus input available for VGA or second HDMI input of SoC
I2C-bus controllable at bit rates up to 400 kbit/s
Non-volatile memory for switch management (Hot Plug Detect, Power-down)
Non-volatile storage for EDID’s allowing easy loading
Embedded Extended Display Identification Data (EDID) memory:
253-byte shared and 3-byte of dedicated EDID memory per HDMI input
Non-volatile memory for programming default EDID content
Supports sources without +5 V
5 embedded EDID memory supplied by +5 V from HDMI source
An extra 128-byte blocks for DVI or PC formats
EDID update by I2C-bus, example for AVR applications
Fail-safe output in Idle mode
Mute pin preventing from pop noise/image noise
ATC/Rx compliant for 36-bit Deep Color 1080p 60 Hz
ATC/Tx eye diagram compliant for 36-bit Deep color 1080p 60 Hz
Programmable slave address for easy cascade approach
Ready for HDMI Audio return Channel (HDMI 1.4 features refer to AN907)
3.3 V and 1.8 V power supplies
Additional ESD protection pin for CEC line
ESD protection:
HBM: class 2
MM: class B
FCDM: class IV
IEC 61000-4-2 class 3 for HDMI inputs
Power-down mode with dedicated pin
CMOS process
Lead (Pb) free LQFP100 14 × 14 × 1 mm package, pitch 0.5 mm
3. Applications
HDTV (plasma, Rear projection TV and LCD TV)
YCbCr or RGB Hi-Speed video digitizer
Projector
Home theater
AVR
Switch box
TDA19997HL_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 22 December 2009
2 of 26
TDA19997HL
NXP Semiconductors
Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer
4. Quick reference data
Table 1.
Symbol
Quick reference data
Parameter
Conditions
Min Typ Max
Unit
HDMI input pins: RXx_D0+, RXx_D0−, RXx_D1+, RXx_D1−, RXx_D2+, RXx_D2−, RXx_HPD, RXx_5V, RXy_DDC_DAT,
RXy_DDC_CLK, CEC[1][2]
VESD
electrostatic discharge voltage
IEC 61000-4-2 class 3 (contact
discharge)
7
-
-
kV
HDMI pins: OUT_D0−, OUT_D0+, OUT_D1−, OUT_D1+, OUT_D2−, OUT_D2+, RXx_D0+, RXx_D0−, RXx_D1+,
RXx_D1−, RXx_D2+, RXx_D2−[1]
fmax
maximum frequency
2.25
-
-
GHz
Supplies
VDDH(3V3)
VDDH(1V8)
VDDS(3V3)
HDMI supply voltage (3.3 V)
HDMI supply voltage (1.8 V)
supervisor supply voltage (3.3 V)
3.13 3.3 3.47
1.65 1.8 1.95
V
V
V
V
3.0
3.3 3.6
VDDDC(1V8) core digital supply voltage (1.8 V)
1.65 1.8 1.95
[1] x = A, B, C, D.
[2] y = A, B, C, D, E.
5. Ordering information
Table 2.
Ordering information
Type number
Maximum data rate
per channel
Package
Name
Description
Version
TDA19997HL
2.25 gigasamples per LQFP100
second
plastic low profile quad flat package; 100 leads;
body 14 × 14 × 1.4 mm
SOT407-1
TDA19997HL_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 22 December 2009
3 of 26
TDA19997HL
NXP Semiconductors
Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer
6. Block diagram
V
DDH(3V3)
TDA19997
V
DDH(1V8)
RXA_C+
RXA_C−
RXA_D0+
RXA_D0−
RXA_D1+
RXA_D1−
RXA_D2+
RXA_D2−
EQ
EQ
EQ
OUT_C+
OUT_C−
RXB_C+
RXB_C−
RXB_D0+
RXB_D0−
RXB_D1+
RXB_D1−
RXB_D2+
RXB_D2−
OUT_D0+
RT AND EQ
RT AND EQ
RT AND EQ
OUT_D0−
HDMI
SWITCH
RXC_C+
RXC_C−
RXC_D0+
RXC_D0−
RXC_D1+
RXC_D1−
RXC_D2+
RXC_D2−
OUT_D1+
OUT_D1−
RXD_C+
RXD_C−
RXD_D0+
RXD_D0−
RXD_D1+
RXD_D1−
RXD_D2+
RXD_D2−
OUT_D2+
OUT_D2−
I2C_SDA
I2C_SCL
2
I C-BUS
INTERRUPT
CONTROL
INT_N/MUTE
RXA_5V
RXA_HPD
HP_BIAS
EDID
RXA_DDC_DAT
RXA_DDC_CLK
RXB_5V
RXB_HPD
RXB_DDC_DAT
RXB_DDC_CLK
OSCILLATOR
HP_BIAS
HP_BIAS
HP_BIAS
RXC_5V
RXC_HPD
RXC_DDC_DAT
RXC_DDC_CLK
DDC
OUT_DDC_DAT
OUT_DDC_CLK
BUFFER
MASTER
SWITCH
OUT_DDC
RXD_5V
RXD_HPD
RXD_DDC_DAT
RXD_DDC_CLK
REGULATOR
AUX_5V
RXE_DDC_DAT
RXE_DDC_CLK
001aak370
Fig 1. Block diagram
TDA19997HL_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 22 December 2009
4 of 26
TDA19997HL
NXP Semiconductors
Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer
7. Pinning information
7.1 Pinning
1
75
TDA19997
25
51
001aak372
Fig 2. Pin configuration
7.2 Pin description
Table 3.
Pin description
Symbol
Pin
1
Type[1] Description
VSS
G
O
O
P
ground
OUT_C+
OUT_C−
VDDO(3V3)
OUT_DDC_CLK
OUT_DDC_DAT
VSS
2
HDMI output positive clock channel
HDMI output negative clock channel
output supply voltage; 3.3 V
3
4
5
O
I/O
G
P
DDC-bus clock output; open-drain; 5 V tolerant
DDC-bus data input/output; open-drain; 5 V tolerant
ground
6
7
VDDDC(1V8)
RXA_HPD
RXA_5V
8
digital core supply voltage; 1.8 V
HDMI output A Hot Plug Detect; 5 V tolerant
input A HDMI +5 V
9
O
I
10
RXA_DDC_DAT 11
I/O
HDMI input/output A DDC-bus serial data; open-drain; 5 V
tolerant
RXA_DDC_CLK 12
I
HDMI input A DDC-bus serial clock; open-drain; 5 V tolerant
HDMI input A negative clock channel
HDMI input A positive clock channel
HDMI input A supply voltage; 3.3 V
HDMI input A negative data channel 0
HDMI input A positive data channel 0
ground
RXA_C−
RXA_C+
VDDH(3V3)
RXA_D0−
RXA_D0+
VSS
13
14
15
16
17
18
19
20
21
22
I
I
P
I
I
G
I
RXA_D1−
RXA_D1+
VDDH(3V3)
RXA_D2−
HDMI input A negative data channel 1
HDMI input A positive data channel 1
HDMI input A supply voltage; 3.3 V
HDMI input A negative data channel 2
I
P
I
TDA19997HL_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 22 December 2009
5 of 26
TDA19997HL
NXP Semiconductors
Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer
Table 3.
Pin description …continued
Symbol
RXA_D2+
VDDH(1V8)
AUX_5V
VSS
Pin
23
24
25
26
27
28
29
Type[1] Description
I
HDMI input A positive data channel 2
P
I
HDMI core supply voltage; 1.8 V
auxiliary input; 5 V
G
I
ground
TEST1
reserved for test (connect to ground)
HDMI output B Hot Plug Detect; 5 V tolerant
input B HDMI +5 V
RXB_HPD
RXB_5V
O
I
RXB_DDC_DAT 30
I/O
HDMI input/output B DDC-bus serial data; open-drain; 5 V
tolerant
RXB_DDC_CLK 31
I
HDMI input B DDC-bus serial clock; open-drain; 5 V tolerant
HDMI input B negative clock channel
HDMI input B positive clock channel
HDMI input B supply voltage; 3.3 V
HDMI input B negative data channel 0
HDMI input B positive data channel 0
ground
RXB_C−
RXB_C+
VDDH(3V3)
RXB_D0−
RXB_D0+
VSS
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
I
I
P
I
I
G
I
RXB_D1−
RXB_D1+
VDDH(3V3)
RXB_D2−
RXB_D2+
VSS
HDMI input B negative data channel 1
HDMI input B positive data channel 1
HDMI input B supply voltage; 3.3 V
HDMI input B negative data channel 2
HDMI input B positive data channel 2
ground
I
P
I
I
G
CDEC_DDC
VDDDC(1V8)
VDDDC(3V3)
TEST2
internal supply voltage regulator decoupling capacitor; 1.8 V
digital core supply voltage; 1.8 V
digital core supply voltage; 3.3 V
reserved for test (connect to ground)
power-down control input; active HIGH
I2C-bus output serial data
P
P
I
PD
I
I2C_SDA
I2C_SCL
O
I
I2C-bus serial clock
RXE_DDC_CLK 51
RXE_DDC_DAT 52
I
Additional input DDC-bus serial clock; open-drain; 5 V tolerant
I/O
Additional input/output DDC-bus serial data; open-drain; 5 V
tolerant
INT_N/MUTE
53
O
interrupt request for I2C-bus mode or 5 V detection
MUTE output pin
CDEC_STBY
VDDS(3V3)
VSS
54
55
56
57
58
59
internal supply voltage regulator decoupling capacitor; 1.8 V
supervisor supply voltage; 3.3 V
ground
P
G
CEC
8 kV System level ESD protection
HDMI input C Hot Plug Detect; 5 V tolerant
input C HDMI +5 V
RXC_HPD
RXC_5V
I
I
RXC_DDC_DAT 60
I/O
HDMI input/output C DDC-bus serial data; open-drain; 5 V
tolerant
TDA19997HL_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 22 December 2009
6 of 26
TDA19997HL
NXP Semiconductors
Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer
Table 3.
Symbol
RXC_DDC_CLK 61
Pin description …continued
Pin
Type[1] Description
I
HDMI input C DDC-bus serial clock; open-drain; 5 V tolerant
RXC_C−
RXC_C+
VDDH(3V3)
RXC_D0−
RXC_D0+
VSS
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
I
HDMI input C negative clock channel
HDMI input C positive clock channel
HDMI input C supply voltage; 3.3 V
HDMI input C negative data channel 0
HDMI input C positive data channel 0
ground
I
P
I
I
G
I
RXC_D1−
RXC_D1+
VDDH(3V3)
RXC_D2−
RXC_D2+
VSS
HDMI input C negative data channel 1
HDMI input C positive data channel 1
HDMI input C supply voltage; 3.3 V
HDMI input C negative data channel 2
HDMI input C positive data channel 2
ground
I
P
I
I
G
I
R12K
termination resistor control
VDDH(1V8)
RXD_HPD
RXD_5V
P
O
I
HDMI core supply voltage; 1.8 V
HDMI output D Hot Plug Detect; 5 V tolerant
input D HDMI +5 V
RXD_DDC_DAT 78
I/O
HDMI input/output D DDC-bus serial data; open-drain; 5 V
tolerant
RXD_DDC_CLK 79
I
HDMI input D DDC-bus serial clock; open-drain; 5 V tolerant
HDMI input D negative clock channel
HDMI input D positive clock channel
HDMI input D supply voltage; 3.3 V
HDMI input D negative data channel 0
HDMI input D positive data channel 0
ground
RXD_C−
RXD_C+
VDDH(3V3)
RXD_D0−
RXD_D0+
VSS
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
I
I
P
I
I
G
I
RXD_D1−
RXD_D1+
VDDH(3V3)
RXD_D2−
RXD_D2+
VDDDC(1V8)
VSS
HDMI input D negative data channel 1
HDMI input D positive data channel 1
HDMI input D supply voltage; 3.3 V
HDMI input D negative data channel 2
HDMI input D positive data channel 2
digital core supply voltage; 1.8 V
ground
I
P
I
I
P
G
O
O
P
O
O
G
O
O
OUT_D2+
OUT_D2−
VDDO(1V8)
OUT_D1+
OUT_D1−
VSS
HDMI output positive data channel 2
HDMI output negative data channel 2
output supply voltage; 1.8 V
HDMI output positive data channel 1
HDMI output negative data channel 1
ground
OUT_D0+
OUT_D0−
HDMI output positive data channel 0
HDMI output negative data channel 0
TDA19997HL_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 22 December 2009
7 of 26
TDA19997HL
NXP Semiconductors
Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer
[1] P = power supply; G = ground; I = input and O = output; I/O = input/output.
8. Functional description
The TDA19997HL is a DVI/HDMI switch comprising four DVI/HDMI inputs and one output
optimized for Hi-Speed TMDS data. All inputs meet HDMI compliance tests and include a
built-in auto-adaptive input equalizer. The TDA19997HL includes an activity detection
module and Hot Plug Detect management.
In addition, the TDA19997HL stores the Extended Display Identification Data (EDID) for
each input in the built-in EDID memory. Full DDC-bus functionality is provided by the
TDA19997HL, including level-shifting.
8.1 HDMI input
The TDA19997HL supports bit rate inputs up to 2.25 Gbit/s enabling high frame rate
formats such as 1080p60, 1080i120 and 720p120 in 36-bit Deep Color mode.
The termination resistor control (R12K) needs an external resistor of 12 kΩ ± 1 %.
The termination resistor can be disconnected from the 3.3 V supply to remove the
common-mode voltage via the I2C-bus and/or when RXx_HPD is LOW.
8.2 Equalizer
The input equalizer is fully auto-adaptive, needing no external control. Signals from short
cables with very low TMDS clock frequencies (20 MHz) to long cables (up to 20 m) at high
TMDS clock frequencies (225 MHz) are easily managed by the TDA19997HL’s equalizer.
8.3 Activity detection
When activity is detected, the output is automatically activated. If no input activity is
detected, the output is disabled to avoid false detections by the HDMI receiver. The power
consumption is reduced accordingly. The detection range is fixed by I2C-bus. An interrupt
output can be used to indicate any activity change.
• In I2C-bus mode: the TMDS frequency can be read, however, the precision of the
value depends on internal oscillator accuracy.
8.4 Embedded EDID memory
The size of the EDID memory is 253-byte shared and 3-byte dedicated for each input. The
memory can be accessed by each input at the same time.
EDID content programming is performed using the non-volatile memory. The EDID
memory can be powered by +5 V from the source or directly from the PCB using the
dedicated AUX_5V pin. In Power-down mode, the EDID memory remains active and it is
possible to modify its content. Access from pins RXx_DDC_DAT and RXx_DDC_CLK is
independent of other supplies. Consequently, the source has access to the EDID memory
when TDA19997HL is not powered.
Content can be modified using the I2C-bus. However, data modified using the I2C-bus
must be powered by the 1.8 V supply from pin CDEC_DDC or the AUX_5V auxiliary
supply pin.
TDA19997HL_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 22 December 2009
8 of 26
TDA19997HL
NXP Semiconductors
Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer
EDID memory accesses are only acknowledged when EDID-only mode is enabled.
Remark: Embedded non-volatile memory content shall be programmed with all
termination resistors disconnected to ensure proper programming.
8.5 Display Data Channel (DDC)
The DDC-bus is 5 V tolerant and supports all direct connections from the HDMI source.
The TDA19997HL provides level-shifting and buffering for both OUT_DDC_DAT and
OUT_DDC_CLK pins. It allows level-shifting from 5 V on the source side to 3.3 V on the
receiver side.
To prevent a lock-up condition, a specific digital protection is implemented on the
DDC-bus.
Pins RXx_DDC_DAT, RXx_DDC_CLK, OUT_DDC_DAT and OUT_DDC_CLK are
compatible with the I2C-bus specification in Fast-mode (400 kHz):
• Pins RXx_DDC_DAT and RXx_DDC_CLK at VDD = 4.5 V to 5.5 V
• Pins OUT_DDC_DAT and OUT_DDC_CLK at VDD = 3.0 V to 3.6 V
When the TDA19997HL is not 1.8 V core supplied, pins OUT_DDC_DAT and
OUT_DDC_CLK are high-impedance. In addition, pins RXx_DDC_DAT and
RXx_DDC_CLK are high-impedance when the device is not 5 V supplied.
TDA19997HL acts as a DDC-bus master switch to prevent bus corruption. When the input
selection changes, the upstream DDC-bus communication (using RXx_DDC_DAT and
RXx_DDC_CLK) is disconnected and a stop bit is sent on the downstream DDC-bus
communication (using OUT_DDC_DAT and OUT_DDC_CLK). The DDC-bus is then
connected on the next upstream DDC during a free bus period to avoid bus corruption.
8.6 HDMI features
TDA19997HL does not decode Data Island or Deep Color information, it forwards these
packets including null packets.
8.7 +5 V signal detection
+5 V signal detection from source is used for activity control through I2C-bus by setting a
bit and an interrupt.
8.8 AUX_5V pin
This pin can be used to supply the built-in EDID memory and DDC-bus enabling access to
EDID memory using the DDC-bus without a +5 V signal from any of the input sources.
When pin AUX_5V is powered, the TDA19997HL provides support for HDMI cabled
sources without a +5 V signal. In addition, the AUX_5V supply ensures EDID data stored
in active memory is not lost when a +5 V signal is not available from the input sources.
Input signal detection (+5 V) is also available when AUX_5V pin is powered.
AUX_5V is necessary when using the fifth DDC-bus input (RXE_DDC_DAT,
RXE_DDC_CLK).
TDA19997HL_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 22 December 2009
9 of 26
TDA19997HL
NXP Semiconductors
Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer
8.9 HDMI output
The TDA19997HL HDMI output port is only activated when data is detected on the
selected input.
HDMI output can be switched off (high-impedance) using an I2C-bus bit or using pin PD.
• Idle mode: HDMI output is either fixed at a constant value (fail-safe protection) or
high-impedance. Configuration is performed using an I2C-bus bit. When output is
fixed at a constant value, it creates a voltage difference in the differential pairs and
stabilizes the receiver differential amplifier. The disadvantage of this protection
against noise is increased power consumption (current from switch and pull-up on
receiver side). If the two differential output pairs are high-impedance, the receiver
differential pair is common mode (receiver pull-up). The receiver differential amplifier
is not stable and does not need any additional power (no current from switch).
8.10 Power management
The following five power modes are available:
• Operating mode: the device is fully functional
• Power-off mode: no supplies are available
• EDID-only mode: only +5 V from the source available
• Power-down mode: all supplies are available and pin PD is HIGH.
• Idle mode: all supplies are available and there is no HDMI input. As a power saving
feature, Idle mode is automatically selected when there is no activity on the inputs.
When activity is detected, Operating mode wake-up is automatically selected
Table 4.
Power management
Mode
Functions
EDID-only
Power-down
Idle
Operating
+5 V signal detection
n/a
on
on
on
[1]
[4]
[4]
[4]
RXx_HPD (if 5 V)[2][3]
[4]
[4]
[4]
[4]
[4]
[4]
RXx_DDC_DAT; RXx_DDC_CLK (if 5 V)[5][3]
EDID DDC read (if 5 V)[3]
on
[1]
EDID I2C-bus write (If 5 V)[3]
OUT_DDC_DAT; OUT_DDC_CLK
INT_N management
off
off
off
off
off
off
off
off
off
off
off
on
off
on
off
off
off
off
off
on
on
off
on
on
[4]
[4]
on
on
[4]
[4]
Termination resistors
[4]
[4]
[1]
[4]
[4]
[4]
[1]
[4]
Activity detection
Equalizer (when active)
TMDS buffer extended mode
TMDS output (if active)
Configuration register read/write
Configuration nonvolatile memory download
Configuration nonvolatile memory write
on
on
on
on
on
on
[1] Nonvolatile memory.
[2] x = A, B, C or D.
TDA19997HL_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 22 December 2009
10 of 26
TDA19997HL
NXP Semiconductors
Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer
[3] When 5 V is indicated, a +5 V input signal is available on at least one HDMI input and/or pin AUX_5V is powered.
[4] Bit state dependent.
[5] x = A, B, C, D or E.
8.11 Power supplies
The termination supply voltage must be 3.3 V ± 5 % with a termination resistance of
50 Ω ± 10 % as defined in the HDMI 1.3a specification.
A dedicated 3.3 V ± 10 % supply (powering interrupt pin INT_N/MUTE) is kept for
compatibility with TDA9996. This pin shall be connected to the rest of 3.3 V supply line.
The 1.8 V supply must also be ± 10 %.
A double Power-On Reset (POR) is implemented to manage different delays between
both supply ramp-ups. POR is managed internally without a reset pin. All 1.8 V power
supply pins (VDDDC, VDDH, VDDO) could be connected together (i.e. these pins must be
shorted out).
+5 V from the HDMI connector and AUX_5V pin are used to supply the EDID memory and
the corresponding DDC-bus slave module. To maintain the EDID (volatile memory part)
contents modified by I2C-bus, it is necessary to have +5 V (from HDMI connector or
AUX_5V pin) constantly available.
8.12 I2C-bus
The TDA19997HL allows software programming of its internal registers using the I2C-bus.
The I2C-bus is a separate bus to the DDC-bus, ensuring that I2C-bus programming of the
TDA19997HL’s registers does not influence DDC-bus operation. The TDA19997HL
supports I2C-bus Fast-mode (400 kHz).
8.12.1 I2C-bus protocol
To access registers, the TDA19997HL uses the I2C-bus. The TDA19997HL acts as an
I2C-bus slave device. Pin I2C_SCL is used as the input pin. Both Fast-mode (400 kHz)
and Standard-mode (100 kHz) are supported by the TDA19997HL. The slave I2C-bus
address is shown in Table 5.
The I2C-bus slave address is 1100 A2 A1 A0 R/W. Address bit values are stored in the
non-volatile configuration memory and enable selection of the slave address. The default
slave address value is 1100 000x.
The I2C-bus slave address is identical to TDA9996.
Table 5.
Default slave address
Device type
Bit
A6
A5
A4
A3
A2
A1
A0
R/W
TDA19997HL
1
1
0
0
A2
A1
A0
1/0
I2C-bus access is explained in Figure 3. The I2C-bus master writes the TDA19997HL
address and the subaddress to access the specific register, then it writes the data.
TDA19997HL_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 22 December 2009
11 of 26
TDA19997HL
NXP Semiconductors
Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL
SDA
SLAVE ADDRESS
SUBADDRESS
DATA
STOP
001aaf292
Fig 3. I2C-bus access
8.12.2 Memory page management
The I2C-bus memory is split into several pages, selected using the common register
CURPAGE_ADR. It is only necessary to write in this register once to change the current
page. Multiple read or write operations in the same page must start by writing to register
CURPAGE_ADR once.
• Page 00h: general control
• Page 20h: EDID block0
• Page 21h: EDID block1 and control
• Page 22h: second EDID block0
• Page 30h: configuration
9. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDDx(3V3)
VDDx(1V8)
ΔVDD
Parameter
Conditions
Min
−0.5
−0.5
−0.5
−55
0
Max
+4.6
+2.5
+0.5
+150
+70
Unit
V
supply voltage on all 3.3 V pins
supply voltage on all 1.8 V pins
supply voltage difference
storage temperature
V
V
Tstg
°C
°C
°C
Tamb
ambient temperature
junction temperature
Tj
-
+125
HDMI input pins: RXx_D0+, RXx_D0−, RXx_D1+, RXx_D1−, RXx_D2+, RXx_D2−, RXx_HPD, RXx_5V, RXy_DDC_DAT,
RXy_DDC_CLK, CEC[1][2]
VESD
electrostatic discharge voltage
IEC 61000-4-2 class 3 (contact
discharge)
7
-
kV
HDMI output pins: OUT_D0−, OUT_D0+, OUT_D1−, OUT_D1+, OUT_D2−, OUT_D2+, OUT_DDC_DAT, OUT_DDC_CLK
VESD
electrostatic discharge voltage
IEC 61000-4-2 class 2 (contact
discharge)
5
-
kV
All pins
VESD
electrostatic discharge voltage
EIA/JESD22-A114-F (human body
model) class 2
−2500 +2500
V
V
V
EIA/JESD22-A115-A (machine
model) class B
−200
+200
-
EIA/JESD22-C101-D (FCDM)
class IV
1500
[1] x = A, B, C, D.
TDA19997HL_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 22 December 2009
12 of 26
TDA19997HL
NXP Semiconductors
Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer
[2] y = A, B, C, D, E.
10. Thermal characteristics
Table 7.
Symbol
Rth(j-a)
Thermal characteristics
Parameter
Conditions
Typ
49.5
18.9
Unit
K/W
K/W
thermal resistance from junction to ambient in free air
thermal resistance from junction to case
Rth(j-c)
11. Characteristics
Table 8.
Characteristics
VDDH(3V3) = 3.13 V to 3.47 V; VDDDC(3V3) = 3.0 V to 3.6 V; VDDH(1V8) = 1.65 V to 1.95 V; VDDDC(1V8) = 1.65 V to 1.95 V;
Tamb = 0 °C to +70 °C; typical values measured at VDDH(3V3) and VDDDC(3V3) = 3.3 V; VDDH(1V8) and VDDDC(1V8) = 1.8 V and
Tamb = 25 °C; fmax = 2.25 GHz; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supplies
VDDH(3V3)
VDDH(1V8)
VDDS(3V3)
VDDDC(3V3)
VDDDC(1V8)
VDDO(3V3)
VDDO(1V8)
IDDH(3V3)
HDMI supply voltage (3.3 V)
HDMI supply voltage (1.8 V)
supervisor supply voltage (3.3 V)
core digital supply voltage (3.3 V)
core digital supply voltage (1.8 V)
output supply voltage (3.3 V)
output supply voltage (1.8 V)
HDMI supply current (3.3 V)
HDMI supply current (1.8 V)
supervisor supply current (3.3 V)
core digital supply current (3.3 V)
core digital supply current (1.8 V)
3.13
3.3
1.8
3.3
3.3
1.8
3.3
1.8
22
13
2
3.47
1.95
3.6
3.6
1.95
3.6
1.95
29
V
1.65
V
3.0
V
3.0
V
1.65
V
3.0
V
1.65
V
[1][2]
-
-
-
-
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
°C
IDDH(1V8)
16
IDDS(3V3)
3
IDDDC(3V3)
IDDDC(1V8)
6
8
Pin 8
51
77
92
23
15
3
70
Pin 45
Pin 91
90
105
28
IDDO(3V3)
IDDO(1V8)
IAUX_5V
Tj(max)
output supply current (3.3 V)
output supply current (1.8 V)
current on pin AUX_5V
18
5
maximum junction temperature
Rth(j-a) = 49.5 K/W
-
124
TDA19997HL_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 22 December 2009
13 of 26
TDA19997HL
NXP Semiconductors
Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer
Table 8.
Characteristics …continued
VDDH(3V3) = 3.13 V to 3.47 V; VDDDC(3V3) = 3.0 V to 3.6 V; VDDH(1V8) = 1.65 V to 1.95 V; VDDDC(1V8) = 1.65 V to 1.95 V;
Tamb = 0 °C to +70 °C; typical values measured at VDDH(3V3) and VDDDC(3V3) = 3.3 V; VDDH(1V8) and VDDDC(1V8) = 1.8 V and
T
amb = 25 °C; fmax = 2.25 GHz; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Pcons
Power consumption
0 = Power-down; no 5 V
3.3 V
1.8 V
-
-
-
-
0
0
mW
mW
1 = EDID read only; using
+5 V (20 mW) from source
for EDID
3.3 V
1.8 V
-
-
-
-
0
0
mW
mW
2 = Idle mode; EDID +
I2C-bus + HDMI, No HDMI
activity on selected input,
20 mW from source
[3]
3.3 V
1.8 V
-
-
-
-
28
15
mW
mW
3 = Operating mode; all on,
with HDMI activity on
selected input
[3]
[3]
3.3 V
1.8 V
-
-
-
-
-
-
241
583
824
mW
mW
mW
total power consumption in
Operating mode
TDA19997HL_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 22 December 2009
14 of 26
TDA19997HL
NXP Semiconductors
Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer
Table 8.
Characteristics …continued
VDDH(3V3) = 3.13 V to 3.47 V; VDDDC(3V3) = 3.0 V to 3.6 V; VDDH(1V8) = 1.65 V to 1.95 V; VDDDC(1V8) = 1.65 V to 1.95 V;
Tamb = 0 °C to +70 °C; typical values measured at VDDH(3V3) and VDDDC(3V3) = 3.3 V; VDDH(1V8) and VDDDC(1V8) = 1.8 V and
T
amb = 25 °C; fmax = 2.25 GHz; unless otherwise specified.
Symbol Parameter Conditions
HDMI inputs: pins RXx_C+, RXx_C−, RXx_D0+, RXx_D0−, RXx_D1+, RXx_D1−, RXx_D2+ and RXx_D2−[4]
Min
Typ
Max
Unit
Vi(dif)
differential input voltage
R12K = 12 kΩ ± 1 %
150
-
-
1200 mV
VI(cm)
common-mode input voltage
2.735
3.475
V
HDMI output pins: OUT_D0−, OUT_D0+, OUT_D1−, OUT_D1+, OUT_D2− and OUT_D2+
Vo(p-p)
VOH
peak-to-peak output voltage
HIGH-level output voltage
LOW-level output voltage
with test load and operating
conditions as described in
the HDMI 1.3a specification
400
525
3.3
2.8
600
mV
V
3.125
2.535
3.475
3.065
VOL
V
HDMI pins: RXx_C+ and RXx_C−[4]
fclk(max) maximum clock frequency
225
-
-
MHz
GHz
HDMI pins: OUT_D0−, OUT_D0+, OUT_D1−, OUT_D1+, OUT_D2−, OUT_D2+, RXx_D0−, RXx_D0+, RXx_D1−,
RXx_D1+, RXx_D2− and RXx_D2+[4]
fmax
maximum frequency
2.25
-
-
Digital inputs[5]: pins PD
VIL
VIH
LOW-level input voltage
HIGH-level input voltage
-
-
-
0.8
-
V
V
2.0
Digital inputs[5]: pin RXx_HPD[4]
VIL
VIH
Ci
LOW-level input voltage
HIGH-level input voltage
input capacitance
-
-
-
-
0.8
-
V
2.0
-
V
2.8
pF
Digital outputs: pin INT_N/MUTE
VOH
HIGH-level output voltage
CL = 10 pF; lOH = 2 mA
CL = 10 pF; lOL = 2 mA
2.4
-
-
-
-
V
V
VOL
LOW-level output voltage
0.4
I2C-bus: pins I2C_SCL and I2C_SDA (Fast-mode)[5]
fSCL
Cb
SCL clock frequency
-
-
-
-
-
-
400
400
10
kHz
pF
capacitive load for each bus line
Ci
input capacitance
pF
DDC I2C-bus: pins RXx_DDC_DAT and RXx_DDC_CLK[6][5]
fSCL
SCL clock frequency
Standard-mode
Fast-mode
-
-
-
-
-
-
100
400
10
kHz
kHz
pF
Ci
input capacitance
DDC I2C-bus[5]: master bus; pins OUT_DDC_DAT and OUT_DDC_CLK
fSCL
SCL clock frequency
Standard-mode
Fast-mode
-
-
-
100
400
kHz
kHz
MTP endurance
Nendu(W)
write endurance
number of cycles at
1000
-
Tj = 125 °C
[1] Typical values: add 40 mA by connected link for regulator dimensioning.
[2] Maximum values: add 48 mA by connected link for regulator dimensioning.
[3] Maximum values: add 167 mW by connected link for regulator dimensioning (12 mA × 3.47 V = 167 mW).
TDA19997HL_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 22 December 2009
15 of 26
TDA19997HL
NXP Semiconductors
Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer
[4] x = A, B, C, D.
[5] 5 V tolerant.
[6] x = A, B, C, D, E.
12. Typical operating characteristics
001aak378
300
current
consumption
(mA)
V
DDx(1V8)
200
100
V
DDx(3V3)
0
0
50
100
150
200
TMDS
250
(MHz)
f
(1) VDDx(1V8) = sum of current from all VDD(1V8) supply pins.
(2) VDDx(3V3) = sum of current from all VDD(3V3) supply pins, excluding current from HDMI source.
Fig 4. Typical current consumption
TDA19997HL_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 22 December 2009
16 of 26
TDA19997HL
NXP Semiconductors
Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer
SOURCE
CABLE
TDA19997
TP1
TP2
TP3
(source output)
(cable output)
(switch output)
001aak373
a. Jitter measurement test bench
001aak366
001aak367
40
40
Jitter
Jitter
(% Tbit)
(% Tbit)
30
30
20
10
0
20
10
0
TP2
TP1
TP2
TP3
TP3
TP1
1 m
5 m
cable length
10 m
15 m
AWG26 AWG24
20 m
1 m
5 m
10 m
cable length
15 m
AWG26 AWG24
20 m
b. Typical jitter measurement in 480p60 24-bit deep
color video format
c. Typical jitter measurement in 720p60 24-bit deep
color video format
001aak368
001aak371
40
40
Jitter
Jitter
(% Tbit)
(% Tbit)
TP2
TP2
30
30
TP3
TP1
20
10
0
20
10
0
TP1
TP3
1 m
5 m
10 m
cable length
15 m
AWG26 AWG24
20 m
1 m
5 m
cable length
10 m
15 m
20 m
AWG26 AWG24
d. Typical jitter measurement in 1080p60 24-bit deep
color video format
e. Typical jitter measurement in 1080p60 36-bit deep
color video format
Fig 5. Typical jitter measurement
TDA19997HL_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 22 December 2009
17 of 26
TDA19997HL
NXP Semiconductors
Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer
001aak374
001aak375
875
875
(mV)
(mV)
525
525
175
175
−175
−525
−875
−175
−525
−875
0
1.48
2.96
4.44
5.92
7.40
0
0.538
1.076
1.614
2.152 2.690
t (ns)
t (ns)
a. Typical eye diagram in 480p60 24-bit deep color
video format
b. Typical eye diagram in 720p60 24-bit deep color
video format
001aak376
001aak377
875
875
(mV)
(mV)
525
175
525
175
−175
−525
−875
−175
−525
−875
0
270
540
810
1080
1350
0
179.6
359.2
538.8
718.4 898.0
t (ps)
t (ps)
c. Typical eye diagram in 1080p60 24-bit deep color
video format
d. Typical eye diagram in 1080p60 36-bit deep color
video format
Fig 6. Typical eye diagram measurement with Tx compliancy mask
TDA19997HL_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 22 December 2009
18 of 26
TDA19997HL
NXP Semiconductors
Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer
13. Application information
47 kΩ
(1)
100 nF
(2)
47 kΩ
100 nF
100 nF
100 nF
V
V
DDH(1V8)
SS
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
12 kΩ 1%
OUT_C+
OUT_C−
DDO(3V3)
R12K
V
2
DD(3V3)
V
SS
100 nF
3
V
RXC_D2+
4
22 kΩ
OUT_DDC_CLK
OUT_DDC_DAT
RXC_D2−
V
V
5
DD(3V3)
DD(3V3)
22 kΩ
V
DDH(3V3)
6
V
SS
RXC_D1+
7
V
(2)
100 nF
RXC_D1−
DDDC(1V8)
47 kΩ
8
V
RXA_HPD
RXA_5V
SS
9
RXC_D0+
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
RXA_DDC_DAT
RXA_DDC_CLK
RXA_C−
RXC_D0−
(1)
47 kΩ
V
100 nF
DDH(3V3)
RXC_C+
TDA19997
RXA_C+
RXC_C−
V
100 nF
RXC_DDC_CLK
RXC_DDC_DAT
RXC_5V
DDH(3V)
RXA_D0−
(1)
47 kΩ
RXA_D0+
V
SS
RXC_HPD
CEC
(2)
RXA_D1−
100 nF
100 nF
47 kΩ
V
RXA_D1+
SS
V
V
100 nF
DDH(3V3)
DDS(3V3)
RXA_D2−
CDEC_STBY
22 kΩ
RXA_D2+
INT_N/MUTE
V
DD(3V3)
V
100 nF
RXE_DDC_DAT
RXE_DDC_CLK
DDH(1V8)
AUX_5V
V5V_AUX
100 nF
2
I C-bus
100
nF
100 nF
(2)
47 kΩ
100 nF
47 kΩ
(1)
100 nF
100 nF
001aak369
(1) Mandatory.
(2) Recommended.
Fig 7. Application diagram
TDA19997HL_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 22 December 2009
19 of 26
TDA19997HL
NXP Semiconductors
Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer
14. Package outline
LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm
SOT407-1
y
X
A
51
75
50
26
(1)
76
Z
E
e
H
A
E
2
E
A
(A )
3
A
1
w M
p
θ
b
L
p
pin 1 index
L
detail X
100
1
25
Z
D
v
M
A
B
e
w M
b
p
D
B
H
v
M
5
D
0
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
p
v
w
y
Z
Z
θ
1
2
3
p
E
D
E
max.
7o
0o
0.15 1.45
0.05 1.35
0.27 0.20 14.1 14.1
0.17 0.09 13.9 13.9
16.25 16.25
15.75 15.75
0.75
0.45
1.15 1.15
0.85 0.85
mm
1.6
0.25
0.5
1
0.2 0.08 0.08
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-02-01
03-02-20
SOT407-1
136E20
MS-026
Fig 8. Package outline SOT407-1 (LQFP100)
TDA19997HL_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 22 December 2009
20 of 26
TDA19997HL
NXP Semiconductors
Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer
15. Abbreviations
Table 9.
Abbreviations
Description
Acronym
ATC
Authorized Test Center
Audio/Video Receiver
AVR
AWG
CDM
DDC
DVI
American Wire Gauge
Charged Device Model
Display Data Channel
Digital Video Input
EDID
ESD
EQ
Extended Display Identification Data
ElectroStatic Discharge
EQualizer
HBM
HDCP
HDMI
HDTV
HPD
I2C
Human Body Model
High-bandwidth Digital Content Protection
High-Definition Multimedia Interface
High-Definition TeleVision
Hot Plug Detect
Inter-Integrated Circuit
Liquid Crystal Display
LCD
MM
Machine Model
MTP
POR
RGB
RT
Multi-Time Programmable
Power-On Reset
Red/Green/Blue
Resistor Termination
SoC
System on a Chip
TMDS
VGA
YCbCr
Transition Minimized Differential Signaling
Video Graphic Array
Y = Luminance, Cb = Chroma blue, Cr = Chroma red
16. References
[1] HDMI 1.4 — High-Definition Multimedia Interface; Specification Version 1.4; 5 June
2009.
[2] CEA-861D — A DTV profile for Uncompressed High-Speed Digital Interfaces;
CEA-861rDv18; 5 August 2006.
[3] IEC-60958 — Digital audio interface - Part 1: General; Second edition; March 2004.
Digital audio interface - Part 3: Consumer applications; Second edition; January
2003.
[4] IEC-61937 — Digital audio interface - Interface for non-linear PCM encode audio bit
stream applying IEC-60958 - Part 1: General; First edition; May 2003.
[5] HDCP 1.3 — High-bandwidth Digital Content Protection; Revision 1.3; 21 December
2006.
TDA19997HL_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 22 December 2009
21 of 26
TDA19997HL
NXP Semiconductors
Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer
[6] E-DDC 1.1 — VESA Enhanced Display Data Channel Standard; Version 1.1; 24
March 2004.
[7] DVI 1.0 — DVI Digital Video Interface; Revision 1.0; 2 April 1999.
17. Revision history
Table 10. Revision history
Document ID
TDA19997HL_2
Modifications:
Release date
20091222
Data sheet status
Change notice
Supersedes
Product data sheet
-
TDA19997_1
• Section 2 “Features”: updated ESD part
• Table 1 “Quick reference data”: updated ESD part
• Table 6 “Limiting values”: updated ESD part
TDA19997_1
20090819
Objective data sheet
-
-
TDA19997HL_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 22 December 2009
22 of 26
TDA19997HL
NXP Semiconductors
Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer
18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Limiting values — Stress above one or more limiting values (as defined in
18.2 Definitions
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
18.3 Disclaimers
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
18.4 Licenses
Purchase of NXP ICs with HDMI technology
Use of an NXP IC with HDMI technology in equipment that complies with
the HDMI standard requires a license from HDMI Licensing LLC, 1060 E.
Arques Avenue Suite 100, Sunnyvale CA 94085, USA, e-mail:
admin@hdmi.org.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
18.5 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
I2C-bus — logo is a trademark of NXP B.V.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
TDA19997HL_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 22 December 2009
23 of 26
TDA19997HL
NXP Semiconductors
Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer
20. Tables
Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .3
Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .3
Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table 4. Power management . . . . . . . . . . . . . . . . . . . .10
Table 5. Default slave address . . . . . . . . . . . . . . . . . . .11
Table 6. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 7. Thermal characteristics . . . . . . . . . . . . . . . . . .13
Table 8. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 9. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 10. Revision history . . . . . . . . . . . . . . . . . . . . . . . .22
TDA19997HL_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 22 December 2009
24 of 26
TDA19997HL
NXP Semiconductors
Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer
21. Figures
Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Fig 2. Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . .5
Fig 3. I2C-bus access. . . . . . . . . . . . . . . . . . . . . . . . . . .12
Fig 4. Typical current consumption . . . . . . . . . . . . . . . .16
Fig 5. Typical jitter measurement. . . . . . . . . . . . . . . . . .17
Fig 6. Typical eye diagram measurement with
Tx compliancy mask . . . . . . . . . . . . . . . . . . . . . .18
Fig 7. Application diagram . . . . . . . . . . . . . . . . . . . . . . .19
Fig 8. Package outline SOT407-1 (LQFP100). . . . . . . .20
TDA19997HL_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 22 December 2009
25 of 26
TDA19997HL
NXP Semiconductors
Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer
22. Contents
1
2
3
4
5
6
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Quick reference data . . . . . . . . . . . . . . . . . . . . . 3
Ordering information. . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
8
8.1
8.2
8.3
8.4
8.5
8.6
8.7
Functional description . . . . . . . . . . . . . . . . . . . 8
HDMI input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Equalizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Activity detection. . . . . . . . . . . . . . . . . . . . . . . . 8
Embedded EDID memory. . . . . . . . . . . . . . . . . 8
Display Data Channel (DDC) . . . . . . . . . . . . . . 9
HDMI features . . . . . . . . . . . . . . . . . . . . . . . . . 9
+5 V signal detection . . . . . . . . . . . . . . . . . . . . 9
AUX_5V pin . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
HDMI output . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power management . . . . . . . . . . . . . . . . . . . . 10
Power supplies . . . . . . . . . . . . . . . . . . . . . . . . 11
I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 11
Memory page management . . . . . . . . . . . . . . 12
8.8
8.9
8.10
8.11
8.12
8.12.1
8.12.2
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 12
Thermal characteristics . . . . . . . . . . . . . . . . . 13
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 13
Typical operating characteristics. . . . . . . . . . 16
Application information. . . . . . . . . . . . . . . . . . 19
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 20
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 21
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 22
10
11
12
13
14
15
16
17
18
Legal information. . . . . . . . . . . . . . . . . . . . . . . 23
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 23
18.1
18.2
18.3
18.4
18.5
19
20
21
22
Contact information. . . . . . . . . . . . . . . . . . . . . 23
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 22 December 2009
Document identifier: TDA19997HL_2
相关型号：
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