TDA4686 [NXP]
Video processor with automatic cut-off control; 具有自动切断控制视频处理器
| 型号： | TDA4686 |
| 厂家： | 
NXP |
| 描述： | Video processor with automatic cut-off control |
| 文件： | 总28页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA4686
Video processor with automatic
cut-off control
1997 Jun 23
Product specification
Supersedes data of May 1993
File under Integrated Circuits, IC02
Philips Semiconductors
Product specification
Video processor with automatic cut-off control
TDA4686
FEATURES
• Intended for double line frequency application
(100/120 Hz)
• Operates from an 8 V DC supply
• Black level clamping of the colour difference, luminance
and RGB input signals with coupling-capacitor DC level
storage
The required input signals are:
• Two analog RGB inputs, selected either by fast switch
signals or via I2C-bus; brightness and contrast control of
both RGB inputs
• Luminance and negative colour difference signals
• 2 or 3-level sandcastle pulse for internal timing pulse
generation
• Saturation, contrast, brightness and white adjustment
via I2C-bus
• I2C-bus data and clock signals for microcontroller
control.
• Same RGB output black levels for Y/CD and RGB input
signals
Two sets of analog RGB colour signals can also be
inserted, e.g. one from a peritelevision connector and the
other from an on-screen display generator. The TDA4686
includes full I2C-bus control of all parameters and
functions with automatic cut-off control of the picture tube
cathode currents. It provides RGB output signals for the
video output stages.
• Timing pulse generation from either a 2 or 3-level
sandcastle pulse for clamping, vertical synchronization
and cut-off timing pulses
• Automatic cut-off control or clamped output selectable
via I2C-bus
• Automatic cut-off control with picture tube leakage
current compensation
The TDA4686 is a simplified, pin compatible (except for
pin 18) version of the TDA4680. The module address via
I2C-bus can be used for both ICs; where a function is not
included in the TDA4686 the I2C-bus command is not
executed. The differences with the TDA4680 are:
• Cut-off measurement pulses after end of the vertical
blanking pulse or end of an extra vertical flyback pulse
• Increased RGB signal bandwidths
• No automatic white level control; the white levels are
determined directly by the I2C-bus data
• Two switch-on delays to prevent discolouration before
steady-state operation
• RGB reference levels for automatic cut-off control are
• Average beam current and peak drive limiting
• PAL/SECAM or NTSC matrix selection via I2C-bus
not adjustable via I2C-bus
• No clamping delay
• Emitter-follower RGB output stages to drive the video
output stages
• I2C-bus controlled DC output e.g. for hue-adjust of
NTSC (multistandard) decoders
• Only contrast and brightness adjust for the RGB input
signals
• The measurement lines are triggered either by the
trailing edge of the vertical component of the sandcastle
pulse or by the trailing edge of an optional external
vertical flyback pulse (on pin 18), according to which
occurs first.
• No delay of clamping pulse
• Large luminance, colour difference and RGB bandwidth.
The TDA4685 is like TDA4686 but intended for normal line
frequency application.
GENERAL DESCRIPTION
The TDA4686 is a monolithic integrated circuit with a
luminance and a colour difference interface for video
processing in TV receivers. Its primary function is to
process the luminance and colour difference signals from
a colour decoder which is equipped e.g. with the
multistandard decoder TDA4655 or TDA9160 plus delay
line TDA4661 and the Picture Signal Improvement (PSI)
IC, TDA467X, or from a feature module.
1997 Jun 23
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Philips Semiconductors
Product specification
Video processor with automatic cut-off control
TDA4686
QUICK REFERENCE DATA
SYMBOL
VP
PARAMETER
MIN.
7.2
TYP.
8.0
MAX.
8.8
UNIT
supply voltage (pin 5)
supply current (pin 5)
V
IP
−
−
−
−
60
−
−
−
−
mA
V
V8(p-p)
V6(p-p)
V7(p-p)
V14
luminance input (peak-to-peak value)
0.45
1.33
1.05
−(B − Y) input (peak-to-peak value)
V
−(R − Y) input (peak-to-peak value)
V
3-level sandcastle pulse
H + V
−
−
−
2.5
4.5
8.0
−
−
−
V
V
V
H
BK
2-level sandcastle pulse
H + V
BK
−
−
−
2.5
4.5
0.7
−
−
−
V
V
V
Vi(p-p)
RGB input signals at pins 2, 3, 4, 10, 11 and 12
(peak-to-peak value)
Vo(b-w)
Tamb
RGB outputs at pins 24, 22 and 20 (black-to-white value)
operating ambient temperature
−
2.0
−
V
0
−
70
°C
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
SOT117-1
SOT261-2
TDA4686
DIP28
plastic dual in-line package; 28 leads (600 mil)
plastic leaded chip carrier; 28 leads
TDA4686WP
PLCC28
1997 Jun 23
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Philips Semiconductors
Product specification
Video processor with automatic cut-off control
TDA4686
BLOCK DIAGRAM
EM7D15
a n d b o o k , f u l l p a g e w i d t h
1997 Jun 23
4
Philips Semiconductors
Product specification
Video processor with automatic cut-off control
TDA4686
PINNING
SYMBOL PIN
DESCRIPTION
SYMBOL PIN
DESCRIPTION
fast switch 2 input
CPDL
16 storage capacitor for peak drive
limiting
FSW2
R2
1
2
3
4
5
6
7
8
9
red input 2
CL
17 storage capacitor for leakage current
18 vertical flyback pulse input
19 cut-off measurement input
20 blue output
G2
green input 2
VFB
CI
B2
blue input 2
VP
supply voltage
BO
−(B − Y)
−(R − Y)
Y
colour difference input −(B − Y)
colour difference input −(R − Y)
luminance input
ground
CB
21 blue cut-off storage capacitor
22 green output
GO
CG
23 green cut-off storage capacitor
24 red output
GND
R1
RO
10 red input 1
CR
25 red cut-off storage capacitor
26 hue control output
27 I2C-bus serial data input;
acknowledge output
G1
11 green input 1
HUE
SDA
B1
12 blue input 1
FSW1
SC
13 fast switch 1 input
14 sandcastle pulse input
15 average beam current limiting input
SCL
28 I2C-bus serial clock input
BCL
handbook, halfpage
FSW
R
1
2
28 SCL
27 SDA
26 HUE
2
2
2
2
G
3
B
4
25
24
23
22
21
20
C
R
C
R
O
G
V
5
6
25 C
R
P
V
5
P
−(B − Y)
−(R − Y)
Y
24 R
O
−(B − Y)
6
7
23 C
G
−(R − Y)
Y
7
G
C
O
TDA4686
8
22 G
21 C
TDA4686WP
O
8
B
GND
9
B
GND
9
B
O
R
1
10
11
20 B
O
R
1
10
11
12
19 CI
G
1
19 CI
VFB
G
1
18
17
16
B
1
C
C
L
MED717
FSW 13
1
PDL
SC 14
15 BCL
MED716
Fig.2 Pin configuration (DIP-version).
Fig.3 Pin configuration (PLCC-version).
1997 Jun 23
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Philips Semiconductors
Product specification
Video processor with automatic cut-off control
TDA4686
I2C-BUS PROTOCOL
Control
I2C-BUS RECEIVER (MICROCONTROLLER WRITE MODE)
Each transmission to the I2C-bus receiver consists of at
least three bytes following the START bit. Each byte is
acknowledged by an acknowledge bit immediately
following each byte. The first byte is the Module Address
(MAD) byte, also called slave address byte. This includes
the module address, 1000100 for the TDA4686.
The I2C-bus transmitter provides the data bytes to select
and adjust the following functions and parameters:
• Brightness adjust
• Saturation adjust
The TDA4686 is a slave receiver (R/W = 0), therefore the
module address byte is 10001000 (88H; see also Fig.4).
• Contrast adjust
• DC output e.g. for hue control
• RGB gain adjust
The length of a data transmission is unrestricted, but the
module address and the correct subaddress must be
transmitted before the data byte(s). The order of data
transmission is shown in Figs 5 and 6.
Without auto-increment (BREN = 0 or 1) the module
address (MAD) byte is followed by a SubAddress (SAD)
byte and one data byte only (see Fig.5).
• Peak drive limiting level adjust
• Selects either 3-level or 2-level (5 V) sandcastle pulse
• Enables cut-off control; enables output clamping
• Selects either PAL/SECAM or NTSC matrix
• Enables/disables synchronization of the execution of
I2C-bus commands with the vertical blanking interval
• Enables Y/CD, RGB1 or RGB2 input.
I2C-bus transmitter and data transfer
I2C-BUS SPECIFICATION
The I2C-bus is a bidirectional, two-wire, serial data bus for
intercommunication between ICs in an equipment.
The microcontroller transmits data to the I2C-bus receiver
in the TDA4686 over the serial data line SDA (pin 27)
synchronized by the serial clock line SCL (pin 28). Both
lines are normally connected to a positive voltage supply
through pull-up resistors. Data is transferred when the
SCL line is LOW. When SCL is HIGH the serial data line
SDA must be stable. A HIGH-to-LOW transition of the SDA
line when SCL is HIGH is defined as a START bit.
A LOW-to-HIGH transition of the SDA line when SCL is
HIGH is defined as a STOP bit.
Each transmission must start with a START bit and end
with a STOP bit. The bus is busy after a START bit and is
only free again after a STOP bit has been transmitted.
1997 Jun 23
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Philips Semiconductors
Product specification
Video processor with automatic cut-off control
TDA4686
MSB
1
LSB
0
0
0
0
1
0
0
ACK
module address
R/W
MED710
Fig.4 The module address byte.
STA MAD SAD
START
STO
MED697
STOP
condition
condition
data byte
Fig.5 Data transmission without auto-increment (BREN = 0 or 1).
STA MAD SAD
START
STO
MED698
STOP
condition
condition
data byte
data bytes
Fig.6 Data transmission with auto-increment (BREN = 0).
7
1997 Jun 23
Philips Semiconductors
Product specification
Video processor with automatic cut-off control
TDA4686
AUTO-INCREMENT
CONTROL REGISTER 2
The auto-increment format enables quick slave receiver
initialization by one transmission, when the I2C-bus control
bit BREN = 0 (see control register bits of Table 1).
If BREN = 1 auto-increment is not possible.
FSON2 (Fast Switch 2 ON).
FSDIS2 (Fast Switch 2 Disable).
FSON1 (Fast Switch 1 ON).
FSDIS1 (Fast Switch 1 Disable).
If the auto-increment format is selected, the MAD byte is
followed by a SAD byte and by the data bytes of
consecutive subaddresses (see Fig.6).
The RGB input signals are selected by FSON2 and
FSON1 or FSW2 and FSW1:
All subaddresses from 00H to 0FH are automatically
incremented, the subaddress counter wraps round from
0FH to 00H. Reserved subaddresses 07H, 08H, 09H,
0BH, 0EH and 0FH are treated as legal but have no effect.
Subaddresses outside the range 00H and 0FH are not
acknowledged by the device.
• FSON2 has priority over FSON1
• FSW2 has priority over FSW1
• FSDIS1 and FSDIS2 disable FSW1 and FSW2
(see Table 2).
BCOF (Black level Control Off):
Subaddresses are stored in the TDA4686 to address the
following parameters and functions (see Table 1):
0 = automatic cut-off control enabled
1 = automatic cut-off control disabled; RGB outputs are
clamped to fixed DC levels.
• Brightness adjust
• Saturation adjust
When the supply voltage has dropped below
approximately 6.0 V (usually occurs when the TV receiver
is switched on or the supply voltage is interrupted) all data
and function bits are set to 01H.
• Contrast adjust
• Hue control voltage
• RGB gain adjust
• Peak drive limiting adjust
• Control register functions.
The data bytes D7 to D0 (see Table 1) provide the data of
the parameters and functions for video processing.
CONTROL REGISTER 1
NMEN (NTSC Matrix Enable):
0 = PAL/SECAM matrix
1 = NTSC matrix.
BREN (Buffer Register Enable):
0 = new data is executed as soon as it is received
1 = data is stored in buffer registers and is transferred to
the data registers during the next vertical blanking
interval.
The I2C-bus receiver does not accept any new data until
this data is transferred into the data registers.
SC5 (SandCastle 5 V):
0 = 3-level sandcastle pulse
1 = 2-level (5 V) sandcastle pulse.
1997 Jun 23
8
Philips Semiconductors
Product specification
Video processor with automatic cut-off control
TDA4686
Table 1 Subaddress (SAD) and data bytes; note 1
MSB
SAD
LSB
FUNCTION
(HEX)
D7
D6
D5
D4
D3
D2
D1
D0
Brightness
Saturation
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
X
A05
A15
A25
A35
A45
A55
A65
X
A04
A14
A24
A34
A44
A54
A64
X
A03
A13
A23
A33
A43
A53
A63
X
A02
A12
A22
A32
A42
A52
A62
X
A01
A11
A21
A31
A41
A51
A61
X
A00
A10
A20
A30
A40
A50
A60
X
Contrast
0
Hue control voltage
Red gain
0
0
Green gain
Blue gain
0
0
Reserved
0
Reserved
0
X
X
X
X
X
X
Reserved
0
X
X
X
X
X
X
Peak drive limit
Reserved
0
AA5
X
AA4
X
AA3
X
AA2
X
AA1
X
AA0
X
X
SC5
X
X
X
Control register 1
Control register 2
Reserved
BREN
X
X
NMEN
X
X
X
BCOF FSDIS2 FSON2 FSDIS1 FSON1
X
X
X
X
X
X
X
X
X
X
X
Reserved
X
Note
1. X = don’t care, but for software compatibility with other or future video ICs it is recommended to set all X to logic 0.
1997 Jun 23
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Philips Semiconductors
Product specification
Video processor with automatic cut-off control
TDA4686
Table 2 Signal input selection by the fast source switches; notes 1 to 4
I2C-BUS CONTROL BITS
ANALOG SWITCH SIGNALS
INPUT SELECTED
FSW2
(PIN 1)
FSW1
(PIN 13)
FSON2 FSDIS2 FSON1 FSDIS1
RGB2
RGB1
Y/CD
L
L
L
L
L
L
L
H
X
X
X
X
X
L
ON
ON
H
L
ON
ON
ON
L
L
L
L
L
L
H
L
H
X
L
ON
H
L
ON
H
X
X
X
X
X
H
ON
ON
H
X
X
X
ON
ON
L
L
H
H
X
L
H
X
H
X
X
H
ON
Notes
1. H: logic HIGH implies that the voltage >0.9 V.
2. L: logic LOW implies that the voltage <0.4 V.
3. X = don’t care.
4. ON indicates the selected input signal.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER
MIN.
MAX.
UNIT
VP
Vi
supply voltage (pin 5)
−
8.8
V
input voltage (pins 1 to 8, 10 to 13, 16, 21, 23 and 25)
input voltage (pins 15, 18 and 19)
input voltage (pins 27 and 28)
sandcastle pulse voltage
average current (pins 20, 22 and 24)
peak current (pins 20, 22 and 24)
output current
−0.1
−0.7
−0.1
−0.7
−10
−20
−8
+VP
V
V
V
V
VP + 0.7
+8.8
VP + 5.8
+4
V14
Iav
mA
mA
mA
°C
IM
+4
I26
+0.6
+150
70
Tstg
Tamb
Ptot
storage temperature
−20
0
operating ambient temperature
total power dissipation
°C
SOT117-1
−
−
1.2
1.0
W
W
SOT261-2
1997 Jun 23
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Philips Semiconductors
Product specification
Video processor with automatic cut-off control
TDA4686
CHARACTERISTICS
All voltages are measured in test circuit of Fig.10 with respect to GND (pin 9); VP = 8.0 V; Tamb = 25 °C; nominal signal
amplitudes (black-to-white) at output pins 24, 22 and 20; nominal settings of brightness, contrast, saturation and white
level control; without beam current or peak drive limiting; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply (pin 5)
VP
IP
supply voltage
supply current
7.2
8.0
8.8
V
−
60
−
mA
Colour difference inputs [−(B − Y): pin 6; −(R − Y): pin 7]
V6(p-p)
V7(p-p)
V6,7
−(B − Y) input (peak-to-peak value)
−(R − Y) input (peak-to-peak value)
internal DC bias voltage
notes 1 and 2
−
−
−
−
1.33
1.05
4.1
−
−
V
notes 1 and 2
−
V
at black level clamping
during line scan
−
V
I6,7
input current
0.1
−
µA
µA
MΩ
at black level clamping 100
10
−
R6,7
input resistance
−
−
Luminance/sync (VBS; Y: pin 8)
Vi(p-p)
luminance input voltage at pin 8
note 2
−
0.45
−
V
(peak-to-peak value)
internal DC bias voltage
input current
V8(bias)
I8
at black level clamping
during line scan
−
−
4.1
−
−
V
0.1
−
µA
µA
MΩ
at black level clamping 100
10
−
R8
input resistance
−
−
RGB input 1 (R1: pin 10; G1: pin 11; B1: pin 12)
Vi(p-p)
input voltage at pins 10, 11 and 12
(peak-to-peak value)
note 2
−
0.7
−
V
V10/11/12(bias) internal DC bias voltage
at black level clamping
during line scan
−
−
5.7
−
−
V
I10/11/12
input current
0.1
−
µA
µA
MΩ
at black level clamping 100
10
−
R10/11/12
input resistance
−
−
RGB input 2 (R2: pin 2, G2: pin 3, B2: pin 4)
Vi(p-p)
input voltage at pins 2, 3 and 4
(peak-to-peak value)
note 2
−
0.7
−
V
V2/3/4
I2/3/4
internal DC bias voltage
input current
at black level clamping
during line scan
−
−
5.7
−
−
V
0.1
−
µA
µA
MΩ
at black level clamping 100
10
−
R2/3/4
input resistance
−
−
1997 Jun 23
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Philips Semiconductors
Product specification
Video processor with automatic cut-off control
TDA4686
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Fast signal switch FSW1 (pin 13) to select Y, CD or R1, G1, B1 inputs (control bits: see Table 2)
V13
voltage to select Y and CD
voltage to select R1, G1, B1
internal resistance to ground
−
−
0.4
V
0.9
−
−
5.0
−
V
R13
4.0
−
kΩ
ns
∆t
difference between transit times for
signal switching and signal insertion
−
10
Fast signal switch FSW2 (pin 1) to select Y, CD/R1, G1, B1 or R2, G2, B2 inputs (control bits: see Table 2)
V1
voltage to select Y, CD/R1, G1, B1
voltage to select R2, G2, B2
internal resistance to ground
−
−
0.4
5.0
−
V
0.9
−
−
V
R1
4.0
−
kΩ
ns
∆t
difference between transit times for
signal switching and signal insertion
−
10
Saturation adjust [acts on −(R − Y) and −(B − Y) signals under I2C-bus control; subaddress 01H (bit resolution
1.5% of maximum saturation); data byte 3FH for maximum saturation, data byte 23H for nominal saturation
and data byte 00H for minimum saturation]
ds
saturation below maximum
at 23H
−
−
5
−
−
dB
dB
at 00H; f = 100 kHz
50
Contrast adjust [acts on internal RGB signals under I2C-bus control; subaddress 02H (bit resolution 1.5% of
maximum contrast); data byte 3FH for maximum contrast, data byte 22H for nominal contrast and data byte
00H for minimum contrast]
dc
contrast below maximum
at 22H
at 00H
−
−
5
−
−
dB
dB
22
Brightness adjust [acts on internal RGB signals under I2C-bus control; subaddress 00H (bit resolution 1.5%
of maximum brightness); data byte 3FH for maximum brightness, data byte 26H for nominal brightness and
data byte 00H for minimum brightness]
dbr
black level shift of nominal signal
amplitude referred to cut-off
measurement level
at 3FH
at 00H
−
−
30
−
−
%
%
−50
White potentiometers [under I2C-bus control; subaddresses 04H (red), 05H (green) and 06H (blue); data byte
3FH for maximum gain; data byte 19H for nominal gain and data byte 00H for minimum gain]; note 3
∆Gv
relative to nominal gain
increase of gain
at 3FH
at 00H
−
−
50
50
−
−
%
%
decrease of gain
1997 Jun 23
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Philips Semiconductors
Product specification
Video processor with automatic cut-off control
TDA4686
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
RGB outputs (pins 24, 22 and 20; positive going output signals; peak drive limiter set = 3FH); note 4
Vo(b-w)
nominal output signals
(black-to-white value)
−
2.0
−
−
V
maximum output signals
(black-to-white value)
3.0
−
V
∆Vo
spread between RGB output signals
minimum output voltages
−
−
10
0.8
−
%
V
V
V
Vo
−
−
maximum output voltages
6.8
2.3
−
V24,22,20
voltage of cut-off measurement line
equivalent to voltage during
ultra-black
output clamping;
BCOF = 1
2.5
2.7
Iint
Ro
internal current sources
output resistance
−
−
5.0
20
−
−
mA
Ω
Frequency response (measured with 10 MΩ, 30 pF external load)
fres
frequency response of Y path
(from pin 8 to pins 24, 22 and 20)
f = 14 MHz
f = 12 MHz
f = 22 MHz
−
−
−
−
−
−
3
3
3
dB
dB
dB
frequency response of CD path
(from pins 7 to 24 and 6 to 20)
frequency response of RGB1 path
(from pins 10 to 24, 11 to 22 and
12 to 20)
frequency response of RGB2 path
(from pins 2 to 24, 3 to 22 and
4 to 20)
f = 22 MHz
−
−
3
dB
Sandcastle pulse detector (pin 14)
CONTROL BIT SC5 = 0; 3-LEVEL; notes 5 and 6
V14
sandcastle pulse voltage
for horizontal and vertical blanking
pulses
2.0
2.5
3.0
5.0
V
V
for horizontal pulses (line count)
for burst key pulses (clamping)
4.0
7.6
4.5
−
VP + 5.8 V
CONTROL BIT SC5 = 1; 2-LEVEL; notes 5 and 6
V14
sandcastle pulse voltage
for horizontal and vertical blanking
pulses
2.0
4.0
2.5
4.5
3.0
V
for burst key pulses
VP + 5.8 V
GENERAL
I14
td
output current
V14 = 0 V
−
−
−
−100
µA
µs
leading edge delay of the clamping
pulse
0
−
1997 Jun 23
13
Philips Semiconductors
Product specification
Video processor with automatic cut-off control
TDA4686
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Vertical flyback (pin 18); note 6
V18
vertical flyback pulse
for LOW
−
−
−
2.5
V
for HIGH
4.5
−
−
V
V
internal voltage
input current
pin 18 open-circuit;
note 7
−
5.0
I18
−
−
5
µA
Average beam current limiting (pin 15); note 8
Vc(15)
contrast reduction starting voltage
−
−
4.0
−
−
V
V
∆Vc(15)
voltage difference for full contrast
reduction
−2.0
Vbr(15)
brightness reduction starting voltage
−
−
2.5
−
−
V
V
∆Vbr(15)
voltage difference for full brightness
reduction
−1.6
Peak drive limiting voltage [pin 16; internal peak drive limiting level (Vpdl) acts on RGB outputs under I2C-bus
control; subaddress 0AH]; note 9
V20,22,24
minimum RGB output voltages
maximum RGB output voltages
charge current
at 00H
at 3FH
−
−
3.0
−
V
7.0
−
−
V
I16
−1
5
−
µA
mA
V
discharge current
during peak white
−
−
V16
internal voltage limitation
contrast reduction starting voltage
4.5
−
−
−
Vc(16)
∆Vc(16)
4.0
−2.0
−
V
voltage difference for full contrast
reduction
−
−
V
Vbr(16)
brightness reduction starting voltage
−
−
2.5
−
−
V
V
∆Vbr(16)
voltage difference for full brightness
reduction
−1.6
Automatic cut-off control (pin 19); notes 6 and 10 to 12; see Fig.8
V19
I19
external voltage
output current
−
−
VP − 1.4 V
−
−
−60
−
µA
input current
150
−
−
µA
mA
V
additional input current
switch-on delay 1
0.5
−
V24,22,20
V19(th)
Vref
monitor pulse amplitude (under
I2C-bus control; subaddress 0AH)
switch-on delay 1;
note 11
−
V
pdl − 1.0 −
voltage threshold for picture tube
cathode warming up
switch-on delay 1
−
−
−
4.5
2.7
1.0
−
−
−
V
V
V
internally controlled voltage
during leakage
measurement period
∆V19
difference between VMEAS (cut-off
measurement voltage) and Vref
1997 Jun 23
14
Philips Semiconductors
Product specification
Video processor with automatic cut-off control
TDA4686
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Cut-off storage (pins 25, 23 and 21)
I21,23,25
charge and discharge currents
input currents of storage inputs
during cut-off
measurement lines
−
−
0.3
−
mA
outside measurement
time
−
0.1
µA
Storage of leakage information (pin 17)
I17
charge and discharge currents
during leakage
measurement period
−
−
−
0.4
−
−
mA
µA
V
leakage current
outside measurement
time
0.1
−
V17
threshold voltage for reset to
switch-on state
2.5
Hue control (under I2C-bus control; subaddress 03H; data byte 3FH for maximum voltage; data byte 20H for
nominal voltage and data byte 00H for minimum voltage); note 13
V26
output voltage
at 3FH
at 20H
at 00H
4.8
−
−
−
V
3.0
−
−
V
−
1.2
−
V
Iint
current of the internal current source
at pin 26
500
−
µA
I2C-bus receiver clock SCL (pin 28)
fSCL
VIL
VIH
IIL
IIH
tL
input frequency range
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
HIGH-level input current
clock pulse LOW
0
−
−
−
−
−
−
−
−
−
100
1.5
6.0
−10
10
kHz
V
−
3.0
−
V
µA
µA
µs
µs
µs
µs
−
4.7
4.0
−
−
tH
clock pulse HIGH
rise time
−
tr
1.0
0.3
tf
fall time
−
I2C-bus receiver data input/output SDA (pin 27)
VIL
VIH
IIL
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
HIGH-level input current
LOW-level output current
rise time
−
−
−
−
−
−
−
−
−
1.5
6.0
−10
10
−
V
3.0
−
V
µA
µA
mA
µs
µs
µs
IIH
−
IOL
tr
3.0
−
1.0
0.3
−
tf
fall time
−
tSU;DAT
data set-up time
0.25
1997 Jun 23
15
Philips Semiconductors
Product specification
Video processor with automatic cut-off control
TDA4686
Notes to the characteristics
1. The values of the −(B − Y) and −(R − Y) colour difference input signals are for a 75% colour-bar signal.
2. The pins are capacitively coupled to a low ohmic source, with a recommended maximum output impedance of 600 Ω.
3. The white potentiometers affect the amplitudes of the RGB output signals.
4. The RGB outputs at pins 24, 22 and 20 are emitter followers with current sources.
5. Sandcastle pulses are compared with internal threshold voltages independent of VP. The threshold voltages
separate the components of the sandcastle pulse. The particular component is generated when the voltage on pin 14
exceeds the defined internal threshold voltage.
The internal threshold voltages (control bit SC5 = 0) are:
1.5 V for horizontal and vertical blanking pulses
3.5 V for horizontal pulses
6.5 V for the burst key pulse.
The internal threshold voltages (control bit SC5 = 1) are:
1.5 V for horizontal and vertical blanking pulses
3.5 V for the burst key pulse.
6. Vertical signal blanking is determined by the vertical component of the sandcastle pulse. The leakage and the RGB
cut-off measurement lines are positioned in the first four complete lines after the end of the vertical component.
In this case, the RGB output signals are blanked until the end of the last measurement line; see Fig.8a. If an extra
vertical flyback pulse VFB is applied to pin 18, the four measurement lines start in the first complete line after the end
of the VFB pulse; see Fig.8b. In this case, the output signals are blanked either until the end of the last measurement
line or until the end of the vertical component of the sandcastle pulse, according to which occurs last.
7. If no VFB pulse is applied, pin 18 can be left open-circuit or connected to VP. If pin 18 is always LOW neither
automatic cut-off control nor output clamping can happen.
8. Average beam current limiting reduces the contrast, at minimum contrast it reduces the brightness.
9. Peak drive limiting reduces the RGB outputs by reducing the contrast, at minimum contrast it reduces the brightness.
The maximum RGB outputs are determined via the I2C-bus under subaddress 0AH. When an RGB output exceeds
the maximum voltage, peak drive limiting is delayed by one horizontal line.
10. During leakage current measurement, the RGB channels are blanked to ultra-black level. During cut-off
measurement one channel is set to the measurement pulse level, the other channels are blanked to ultra-black.
Since the brightness adjust shifts the colour signal relative to the black level, the brightness adjust is disabled during
the vertical blanking interval (see Figs 7 and 8).
11. During picture cathode warming up (first switch-on delay) the RGB outputs (pins 24, 22 and 20) are blanked to the
ultra-black level during line scan. During the vertical blanking interval a white-level monitor pulse is fed out on the
RGB outputs and the cathode currents are measured. When the voltage threshold on pin 19 is greater than 4.5 V,
the monitor pulse is switched off and cut-off control is activated (second switch-on delay). As soon as cut-off control
stabilizes, RGB output blanking is removed.
12. Range of cut-off measurement level at the RGB outputs is 1 to 5 V. The recommended value is 3 V.
13. The hue control output at pin 26 is an emitter follower with current source.
1997 Jun 23
16
Philips Semiconductors
Product specification
Video processor with automatic cut-off control
TDA4686
Table 3 Demodulator axes and amplification factors
PARAMETER
NTSC
PAL
(B − Y)* demodulator axis
(R − Y)* demodulator axis
(R − Y)* amplification factor
(B − Y)* amplification factor
0°
0°
115°
1.97
2.03
90°
1.14
2.03
Table 4 PAL/SECAM and NTSC matrix; note 1
MATRIX
NMEN
PAL/SECAM
NTSC
0
1
Note
1. PAL/SECAM signals are matrixed by the equation: VG − Y = −0.51VR − Y − 0.19VB − Y
NTSC signals are matrixed by the equations (hue phase shift of −5 degrees):
VR − Y* = 1.57VR − Y − 0.41VB − Y; VG − Y* = −0.43VR − Y − 0.11VB − Y; VB − Y* = VB − Y
In the matrix equations: VR − Y and VB − Y are conventional PAL demodulation axes and amplitudes at the output of
the NTSC demodulator. VG − Y*, VR − Y* and VB − Y* are the NTSC modified colour difference signals; this is equivalent
to the demodulator axes and amplification factors shown in Table 3. VG − Y* = −0.27VR − Y* − 0.22VB − Y*
.
MHA697
(1)
(2)
cut-off measurement line
for red signal
ultra-black
(1) Maximum brightness.
(2) Nominal brightness.
Fig.7 Cut-off measurement pulse.
1997 Jun 23
17
Philips Semiconductors
Product specification
Video processor with automatic cut-off control
TDA4686
sandcastle pulse
with vertical
component
R channel
G channel
B channel
LM
LM
MR
MG
LM
MB
MHA698
a. Timing controlled by sandcastle pulse.
vertical flyback
pulse (VFB)
R channel
LM
LM
MR
G channel
B channel
MG
LM
MB
MHA699
b. Timing controlled by additional vertical flyback pulse (VFB).
LM = leakage current measurement time.
MR, MG, MB = R, G, B cut-off measurement pulses.
Fig.8 Leakage and cut-off current measurement timing diagram.
1997 Jun 23
18
Philips Semiconductors
Product specification
Video processor with automatic cut-off control
TDA4686
INTERNAL PIN CONFIGURATION
EM7D18
a n d b o o k , f u l l p a g e w
1997 Jun 23
19
Philips Semiconductors
Product specification
Video processor with automatic cut-off control
TDA4686
TEST AND APPLICATION INFORMATION
EM7D19
bnok,lfuapgedwith
1997 Jun 23
20
Philips Semiconductors
Product specification
Video processor with automatic cut-off control
TDA4686
PACKAGE OUTLINES
handbook, full pagewidth
DIP28: plastic dual in-line package; 28 leads (600 mil)
SOT117-1
D
M
E
A
2
A
L
A
1
c
e
w M
Z
b
1
(e )
1
b
M
H
28
15
pin 1 index
E
1
14
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
max.
A
A
Z
(1)
(1)
1
2
UNIT
mm
b
b
c
D
E
e
e
L
M
M
w
1
1
E
H
min.
max.
max.
1.7
1.3
0.53
0.38
0.32
0.23
36.0
35.0
14.1
13.7
3.9
3.4
15.80
15.24
17.15
15.90
5.1
0.51
4.0
2.54
0.10
15.24
0.60
0.25
0.01
1.7
0.013
0.009
0.066
0.051
0.020
0.014
1.41
1.34
0.56
0.54
0.15
0.13
0.62
0.60
0.68
0.63
inches
0.20
0.020
0.16
0.067
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-01-14
SOT117-1
051G05
MO-015AH
1997 Jun 23
21
Philips Semiconductors
Product specification
Video processor with automatic cut-off control
TDA4686
PLCC28: plastic leaded chip carrier; 28 leads
SOT261-2
e
e
E
E
y
X
A
E
b
p
25
19
b
1
Z
E
18
26
w
M
28
1
H
E
pin 1 index
e
A
A
1
A
4
12
4
k
1
β
(A )
3
k
5
11
L
p
v
M
A
Z
e
D
detail X
D
H
B
v
M
B
D
0
5
10 mm
scale
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
(1)
(1)
A
min.
A
max.
k
1
max.
Z
Z
E
(1)
(1)
1
4
D
UNIT
mm
A
A
b
D
E
e
e
e
H
H
k
L
p
v
w
y
β
b
D
E
D
E
3
p
1
max. max.
4.57
4.19
0.81 11.58 11.58
0.66 11.43 11.43
10.92 10.92 12.57 12.57 1.22
9.91 9.91 12.32 12.32 1.07
1.44
1.02
0.53
0.33
0.51
0.51 0.25 3.05
0.020 0.01 0.12
1.27
0.05
0.18 0.18 0.10 2.16 2.16
0.007 0.007 0.004 0.085 0.085
o
45
0.180
0.165
0.032 0.456 0.456
0.026 0.450 0.450
0.430 0.430 0.495 0.495 0.048
0.390 0.390 0.485 0.485 0.042
0.057
0.040
0.021
0.013
inches
0.020
Note
1. Plastic or metal protrusions of 0.01 inches maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-02-25
SOT261-2
1997 Jun 23
22
Philips Semiconductors
Product specification
Video processor with automatic cut-off control
TDA4686
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
WAVE SOLDERING
DIP
Wave soldering techniques can be used for all PLCC
packages if the following conditions are observed:
SOLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
• The package footprint must incorporate solder thieves at
the downstream corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
REPAIRING SOLDERED JOINTS
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
PLCC
REPAIRING SOLDERED JOINTS
REFLOW SOLDERING
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Reflow soldering techniques are suitable for all PLCC
packages.
The choice of heating method may be influenced by larger
PLCC packages (44 leads, or more). If infrared or vapour
phase heating is used and the large packages are not
absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9397 750 00192).
1997 Jun 23
23
Philips Semiconductors
Product specification
Video processor with automatic cut-off control
TDA4686
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1997 Jun 23
24
Philips Semiconductors
Product specification
Video processor with automatic cut-off control
TDA4686
NOTES
1997 Jun 23
25
Philips Semiconductors
Product specification
Video processor with automatic cut-off control
TDA4686
NOTES
1997 Jun 23
26
Philips Semiconductors
Product specification
Video processor with automatic cut-off control
TDA4686
NOTES
1997 Jun 23
27
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Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
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Middle East: see Italy
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Internet: http://www.semiconductors.philips.com
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1997
SCA54
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Date of release: 1997 Jun 23
Document order number: 9397 750 02046
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