TDA6651TT/C3_技术文档

TDA6650TT; TDA6651TT

5 V mixer/oscillator and low noise PLL synthesizer for hybrid

terrestrial tuner (digital and analog)

Rev. 05 — 10 January 2007

Product data sheet

1. General description

The TDA6650TT; TDA6651TT is a programmable 3-band mixer/oscillator and low phase

noise PLL synthesizer intended for pure 3-band tuner concepts applied to hybrid (digital

and analog) or digital only terrestrial and cable TV reception.

Table 1.

Different versions are available depending on the target application^[1]

Application

Type version

hybrid (analog and digital)

TDA6650TT/C3

TDA6651TT/C3

TDA6650TT/C3/S2

TDA6651TT/C3/S2

TDA6651TT/C3/S3

digital only

[1] See Table 22 “Characteristics” for differences between TDA6651TT/C3/S2 and TDA6651TT/C3/S3.

The device includes three double balanced mixers for low, mid and high bands, three

oscillators for the corresponding bands, a switchable IF ampliﬁer, a wideband AGC

detector and a low noise PLL synthesizer. The frequencies of the three bands are shown

in Table 2. Two pins are available between the mixer output and the IF ampliﬁer input to

enable IF ﬁltering for improved signal handling and to improve the adjacent channel

rejection.

Table 2.

Band

Recommended band limits in MHz

RF input

Oscillator

Min

Max

PAL and DVB-T tuners for hybrid application^[1]

Low

Mid

44.25

157.25

443.25

863.25

83.15

196.15

482.15

902.15

157.25

196.15

482.15

High

443.25

DVB-T tuners for digital only application^[2]

Low

Mid

47.00

160.00

446.00

866.00

83.15

196.15

482.15

902.15

160.00

446.00

196.15

482.15

High

[1] RF input frequency is the frequency of the corresponding picture carrier for analog standard.

[2] RF input frequency is the frequency of the center of DVB-T channel.

The IF ampliﬁer is switchable in order to drive both symmetrical and asymmetrical

outputs. When it is used as an asymmetrical ampliﬁer, the IFOUTB pin needs to be

connected to the supply voltage V_CCA

.

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

Five open-drain PMOS ports are included on the IC. Two of them, BS1 and BS2, are also

dedicated to the selection of the low, mid and high bands. PMOS port BS5 pin is shared

with the ADC.

The AGC detector provides a control that can be used in a tuner to set the gain of the

RF stage. Six AGC take-over points are available by software. Two programmable AGC

time constants are available for search tuning and normal tuner operation.

The local oscillator signal is fed to the fractional-N divider. The divided frequency is

compared to the comparison frequency into the fast phase detector which drives the

charge pump. The loop ampliﬁer is also on-chip, including the high-voltage transistor to

drive directly the 33 V tuning voltage without the need to add an external transistor.

The comparison frequency is obtained from an on-chip crystal oscillator. The crystal

frequency can be output to the XTOUT pin to drive the clock input of a digital

demodulation IC.

Control data is entered via the I²C-bus; six serial bytes are required to address the device,

select the Local Oscillator (LO) frequency, select the step frequency, program the output

ports and set the charge pump current or select the ALBC mode, enable or disable the

crystal output buffer, select the AGC take-over point and time constant and/or select a

speciﬁc test mode. A status byte concerning the AGC level detector and the ADC voltage

can be read out on the SDA line during a read operation. During a read operation, the loop

‘in-lock’ ﬂag, the power-on reset ﬂag and the automatic loop bandwidth control ﬂag are

read.

The device has 4 programmable addresses. Each address can be selected by applying a

speciﬁc voltage to pin AS, enabling the use of multiple devices in the same system.

The I²C-bus is fast mode compatible, except for the timing as described in the functional

description and is compatible with 5 V, 3.3 V and 2.5 V microcontrollers depending on the

voltage applied to pin BVS.

2. Features

I Single-chip 5 V mixer/oscillator and low phase noise PLL synthesizer for TV and VCR

tuners, dedicated to hybrid (digital and analog) as well as pure digital applications

(DVB-T)

I Five possible step frequencies to cope with different digital terrestrial TV and

analog TV standards

I Eight charge pump currents between 40 µA and 600 µA to reach the optimum phase

noise performance over the bands

I Automatic Loop Bandwidth Control (ALBC) sets the optimum phase noise

performance for DVB-T channels

I I²C-bus protocol compatible with 2.5 V, 3.3 V and 5 V microcontrollers:

N Address + 5 data bytes transmission (I²C-bus write mode)

N Address + 1 status byte (I²C-bus read mode)

N Four independent I²C-bus addresses.

I Five PMOS open-drain ports with 15 mA source capability for band switching and

general purpose; one of these ports is combined with a 5-step ADC

I Wideband AGC detector for internal tuner AGC:

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

2 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

N Six programmable take-over points

N Two programmable time constants

N AGC ﬂag.

I In-lock ﬂag

I Crystal frequency output buffer

I 33 V tuning voltage output

I Fractional-N programmable divider

I Balanced mixers with a common emitter input for the low band and for the mid band

(each single input)

I Balanced mixer with a common base input for the high band (balanced input)

I 2-pin asymmetrical oscillator for the low band

I 2-pin symmetrical oscillator for the mid band

I 4-pin symmetrical oscillator for the high band

I Switched concept IF ampliﬁer with both asymmetrical and symmetrical outputs to drive

low impedance or SAW ﬁlters i.e. 500 Ω / 40 pF.

3. Applications

For all applications, the recommendations given in the latest application note AN10544

must be used.

3.1 Application summary

I Digital and analog terrestrial tuners (OFDM, PAL, etc.)

I Cable tuners (QAM)

I Digital TV sets

I Digital set-top boxes.

4. Ordering information

Table 3.

Ordering information

Type number

Package

Name

Description

Version

TDA6650TT/C3

TSSOP38 plastic thin shrink small outline package; 38 leads; body width 4.4 mm;

lead pitch 0.5 mm

SOT510-1

TDA6650TT/C3/S2

TDA6651TT/C3

TDA6651TT/C3/S2

TDA6651TT/C3/S3

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

3 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

5. Block diagram

IFFIL1

IFFIL2

IFOUTA

IFOUTB

V

CCA

n.c.

21 (18)

26 (13)

6 (33)

7 (32) 28 (11)

27 (12)

(30) 9

AGC

IF

AGC

AMP

DETECTOR

TDA6650TT

AGC

flag

(TDA6651TT)

AL0, AL1, AL2 ATC

(10) 29

IFGND

(1) 38

(2) 37

LOSCIN

4 (35)

3 (36)

LOW

INPUT

LOW

MIXER

LOW

OSCILLATOR

LBIN

BS1

LOSCOUT

(5) 34

(4) 35

MOSCIN1

MOSCIN2

MID

INPUT

MID

MIXER

MID

OSCILLATOR

MBIN

BS2

(9) 30

(8) 31

(7) 32

(6) 33

1 (38)

2 (37)

HOSCIN1

HBIN1

HBIN2

HIGH

INPUT

HIGH

MIXER

HOSCOUT1

HOSCOUT2

HOSCIN2

HIGH

OSCILLATOR

BS1 . BS2

5 (34)

(3) 36

RFGND

OSCGND

XTOUT

(21) 18

OUTPUT

BUFFER

R0, R1,

R2

24 (15)

[ ]

N 14:0

V

CCD

T0, T1, T2

PHASE

COMPARATOR

FRACTIONAL

DIVIDER

FRACTIONAL

CALCULATOR

(17) 22

(16) 23

LOOP

AMP

VT

CP

19 (20)

20 (19)

XTAL1

XTAL2

CHARGE

PUMP

CRYSTAL

OSCILLATOR

REFERENCE

DIVIDER

15 (24)

16 (23)

17 (22)

13 (26)

T0, T1, CP0, CP1,

SCL

SDA

AS

LOCK

DETECTOR

T2

CP2

2

I C-BUS

TRANSCEIVER

FRACTIONAL

SPURIOUS

COMPENSATION

BAND SWITCH

OUTPUT PORTS

BS5-

BS1

BVS

AGC

(14) 25

POR

ADC

14

8

10

11

12

PLLGND

(25) (31) (29) (28) (27)

fce723

ADC/

BS5

BS3

BS1

BS4

BS2

The pin numbers in parenthesis represent the TDA6651TT.

Fig 1. Block diagram

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

4 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

6. Pinning information

6.1 Pin description

Table 4.

Symbol

Pin description

Description

TDA6650TT TDA6651TT

HBIN1

HBIN2

MBIN

LBIN

1

38

37

36

35

34

33

32

31

30

29

28

high band RF input 1

2

high band RF input 2

3

mid band RF input

4

low band RF input

RFGND

IFFIL1

IFFIL2

BS4

5

RF ground

6

IF ﬁlter output 1

7

IF ﬁlter output 2

8

PMOS open-drain output port 4 for general purpose

AGC output

AGC

9

BS3

10

11

PMOS open-drain output port 3 for general purpose

BS2

PMOS open-drain output port 2 to select the mid

band

BS1

12

27

PMOS open-drain output port 1 to select the low

band

BVS

13

14

26

25

bus voltage selection input

ADC/BS5

ADC input or PMOS open-drain output port 5 for

general purpose

SCL

15

16

17

18

19

20

21

22

23

24

25

26

27

24

23

22

21

20

19

18

17

16

15

14

13

12

I²C-bus serial clock input

I²C-bus serial data input and output

I²C-bus address selection input

crystal frequency buffer output

crystal oscillator input 1

crystal oscillator input 2

not connected

SDA

AS

XTOUT

XTAL1

XTAL2

n.c

VT

tuning voltage output

CP

charge pump output

V_CCD

PLLGND

V_CCA

IFOUTB

supply voltage for the PLL part

PLL ground

supply voltage for the analog part

IF output B for symmetrical ampliﬁer and

asymmetrical IF ampliﬁer switch input

IFOUTA

IFGND

28

29

30

11

10

9

IF output A

IF ground

HOSCIN1

high band oscillator input 1

high band oscillator output 1

high band oscillator output 2

high band oscillator input 2

HOSCOUT1 31

HOSCOUT2 32

8

7

HOSCIN2

33

6

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

5 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

Table 4.

Pin description…continued

Symbol

Description

TDA6650TT TDA6651TT

MOSCIN1

MOSCIN2

OSCGND

LOSCOUT

LOSCIN

34

35

36

37

38

5

4

3

2

1

mid band oscillator input 1

mid band oscillator input 2

oscillators ground

low band oscillator output

low band oscillator input

6.2 Pinning

1

2

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

1

2

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

HBIN1

HBIN2

MBIN

LBIN

LOSCIN

LOSCOUT

OSCGND

MOSCIN2

MOSCIN1

HOSCIN2

HOSCOUT2

HOSCOUT1

HOSCIN1

IFGND

HBIN1

HBIN2

MBIN

LBIN

LOSCOUT

OSCGND

MOSCIN2

MOSCIN1

HOSCIN2

3

4

5

RFGND

IFFIL1

IFFIL2

BS4

RFGND

IFFIL1

IFFIL2

BS4

6

7

HOSCOUT2

HOSCOUT1

HOSCIN1

IFGND

8

9

AGC

10

11

12

13

14

15

16

17

18

19

10

11

12

13

14

15

16

17

18

19

BS3

TDA6650TT

TDA6651TT

BS3

BS2

IFOUTA

BS2

BS1

IFOUTB

BS1

BVS

V

CCA

V

CCA

BVS

ADC/BS5

SCL

PLLGND

ADC/BS5

SCL

V

CCD

V

CCD

SDA

CP

SDA

AS

VT

AS

XTOUT

XTAL1

n.c.

XTOUT

XTAL1

XTAL2

001aac025

001aac026

Fig 2. Pin conﬁguration TDA6650TT

Fig 3. Pin conﬁguration TDA6651TT

7. Functional description

7.1 Mixer, Oscillator and PLL (MOPLL) functions

Bit BS1 enables the BS1 port, the low band mixer and the low band oscillator. Bit BS2

enables the BS2 port, the mid band mixer and the mid band oscillator. When both BS1

and BS2 bits are logic 0, the high band mixer and the high band oscillator are enabled.

The oscillator signal is applied to the fractional-N programmable divider. The divided

signal f_divis fed to the phase comparator where it is compared in both phase and

frequency with the comparison frequency f_comp. This frequency is derived from the signal

present on the crystal oscillator f_xtaland divided in the reference divider. There is a

fractional calculator on the chip that generates the data for the fractional divider as well as

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

6 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

the reference divider ratio, depending on the step frequency selected. The crystal

oscillator requires a 4 MHz crystal in series with an 18 pF capacitor between pins XTAL1

and XTAL2.

The output of the phase comparator drives the charge pump and the loop ampliﬁer

section. This ampliﬁer has an on-chip high voltage drive transistor. Pin CP is the output of

the charge pump, and pin VT is the pin to drive the tuning voltage to the varicap diodes of

the oscillators and the tracking ﬁlters. The loop ﬁlter has to be connected between pins CP

and VT. The spurious signals introduced by the fractional divider are automatically

compensated by the spurious compensation block.

It is possible to drive the clock input of a digital demodulation IC from pin XTOUT with the

4 MHz signal from the crystal oscillator. This output is also used to output ¹⁄₂f_divand f_comp

signals in a speciﬁc test mode (see Table 9). It is possible to switch off this output, which is

recommended when it is not used.

For test and alignment purposes, it is also possible to release the tuning voltage output by

selecting the sinking mode (see Table 9), and by applying an external voltage on pin VT.

In addition to the BS1 and BS2 output ports that are used for the band selection, there are

three general purpose ports BS3, BS4 and BS5. All ﬁve ports are PMOS open-drain type,

each with 15 mA drive capability. The connection for port BS5 and the ADC input is

combined on one pin. It is not possible to use the ADC if port BS5 is used.

The AGC detector compares the level at the IF ampliﬁer output to a reference level which

is selected from 6 different levels via the I²C-bus. The time constant of the AGC can be

selected via the I²C-bus to cope with normal operation as well as with search operation.

When the output level on pin AGC is higher than the threshold V_RMH, then bit AGC = 1.

When the output level on pin AGC is lower than the threshold V_RML, then bit AGC = 0.

Between these two thresholds, bit AGC is not deﬁned. The status of the AGC bit can be

read via the I²C-bus according to the read mode as described in Table 15.

7.2 I²C-bus voltage

The I²C-bus lines SCL and SDA can be connected to an I²C-bus system tied to 2.5 V,

3.3 V or 5 V. The choice of the bus input threshold voltages is made with pin BVS that can

be left open-circuit, connected to the supply voltage or to ground (see Table 5).

Table 5.

I²C-bus voltage selection

Pin BVS connection

Bus voltage

Logic level

LOW

HIGH

To ground

Open-circuit

To V_CC

2.5 V

3.3 V

5 V

0 V to 0.75 V

0 V to 1.0 V

0 V to 1.5 V

1.75 V to 5.5 V

2.3 V to 5.5 V

3.0 V to 5.5 V

7.3 Phase noise, I²C-bus trafﬁc and crosstalk

While the TDA6650TT; TDA6651TT is dedicated for hybrid terrestrial applications, the low

noise PLL will clean up the noise spectrum of the VCOs close to the carrier to reach noise

levels at 1 kHz offset from the carrier compatible with e.g. DVB-T reception.

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

7 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

Linked to this noise improvement, some disturbances may become visible while they were

not visible because they were hidden into the noise in analog dedicated applications and

circuits.

This is especially true for disturbances coming from the I²C-bus trafﬁc, whatever this trafﬁc

is intended for the MOPLL or for another slave on the bus.

To avoid this I²C-bus crosstalk and be able to have a clean noise spectrum, it is necessary

to use a bus gate that enables the signal on the bus to drive the MOPLL only when the

communication is intended for the tuner part (such a kind of I²C-bus gate is included into

the NXP terrestrial channel decoders), and to avoid unnecessary repeated sending of the

same information.

8. I²C-bus protocol

The TDA6650TT; TDA6651TT is controlled via the two-wire I²C-bus. For programming,

there is one device address (7 bits) and the R/W bit for selecting read or write mode. To be

able to have more than one MOPLL in an I²C-bus system, one of four possible addresses

is selected depending on the voltage applied to address selection pin AS (see Table 8).

The TDA6650TT; TDA6651TT fulﬁls the fast mode I²C-bus, according to the NXP I²C-bus

speciﬁcation, except for the timing as described in Figure 4. The I²C-bus interface is

designed in such a way that the pins SCL and SDA can be connected to 5 V, 3.3 V

or to 2.5 V pulled-up I²C-bus lines, depending on the voltage applied to pin BVS (see

Table 5).

8.1 Write mode; R/W = 0

After the address transmission (ﬁrst byte), data bytes can be sent to the device (see

Table 6). Five data bytes are needed to fully program the TDA6650TT; TDA6651TT. The

I²C-bus transceiver has an auto-increment facility that permits programming the device

within one single transmission (address + 5 data bytes).

The TDA6650TT; TDA6651TT can also be partly programmed on the condition that the

ﬁrst data byte following the address is byte 2 (divider byte 1) or byte 4 (control byte 1). The

ﬁrst bit of the ﬁrst data byte transmitted indicates whether byte 2 (ﬁrst bit = 0) or byte 4

(ﬁrst bit = 1) will follow. Until an I²C-bus STOP condition is sent by the controller, additional

data bytes can be entered without the need to re-address the device. The fractional

calculator is updated only at the end of the transmission (STOP condition). Each control

byte is loaded after the 8th clock pulse of the corresponding control byte. Main divider

data are valid only if no new I²C-bus transmission is started (START condition) during the

computation period of 50 µs.

Both DB1 and DB2 need to be sent to change the main divider ratio. If the value of the

ratio selection bits R2, R1 and R0 are changed, the bytes DB1 and DB2 have to be sent in

the same transmission.

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

8 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

50 µs

ADDRESS

BYTE

ADDRESS

BYTE

DIVIDER DIVIDER CONTROL CONTROL CONTROL CONTROL

STOP

START

2

BYTE 1

BYTE 2

BYTE 1

BYTE 2

BYTE 1

BYTE 2

2

I C-bus transmission dedicated to

the MOPLL

I C-bus transmission

dedicated to

another IC

fce921

Fig 4. Example of I²C-bus transmission frame

Table 6.

Name

I²C-bus write data format

Byte

Bit

Ack

MSB^[1]

LSB

Address byte

1

2

3

4

1

0

MA1

MA0

N9

R/W = 0 A

Divider byte 1 (DB1)

Divider byte 2 (DB2)

0

N14

N6

N13

N5

N12

N4

T1

0

N11

N3

N10

N2

N8

A

N7

1

N1

N0

Control byte 1 (CB1);

see Table 7

T/A = 1 T2

T0

R2

R1

R0

1

T/A = 0

CP1

0

ATC

BS4

AL2

BS3

AL1

BS2

AL0

BS1

Control byte 2 (CB2)

5

CP2

CP0

BS5

[1] MSB is transmitted ﬁrst.

Table 7.

Description of write data format bits

Description

Bit

A

acknowledge

MA1 and MA0

R/W

programmable address bits; see Table 8

logic 0 for write mode

N14 to N0

programmable LO frequency;

N = N14 × 2¹⁴+ N13 × 2¹³+ N12 × 2¹²+ ... + N1 × 2¹+ N0

T/A

test/AGC bit

T/A = 0: the next 6 bits sent are AGC settings

T/A = 1: the next 6 bits sent are test and reference divider ratio settings

test bits; see Table 9

T2, T1 and T0

R2, R1 and R0

ATC

reference divider ratio and programmable frequency step; see Table 10

AGC current setting and time constant; capacitor on pin AGC = 150 nF

ATC = 0: AGC current = 220 nA; AGC time constant = 2 s

ATC = 1: AGC current = 9 µA; AGC time constant = 50 ms

AGC take-over point bits; see Table 11

AL2, AL1 and AL0

CP2, CP1 and CP0 charge pump current; see Table 12

BS5, BS4, BS3, BS2 PMOS ports control bits

and BS1

BSn = 0: corresponding port is off, high-impedance state (status at

power-on reset)

BSn = 1: corresponding port is on; V_O= V_CC− V_DS(sat)

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

9 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

8.1.1 I²C-bus address selection

The device address contains programmable address bits MA1 and MA0, which offer the

possibility of having up to four MOPLL ICs in one system. Table 8 gives the relationship

between the voltage applied to the AS input and the MA1 and MA0 bits.

Table 8.

Address selection

Voltage applied to pin AS

0 V to 0.1V_CC

MA1

MA0

0

1

0

1

0

1

0.2V_CCto 0.3V_CCor open-circuit

0.4V_CCto 0.6V_CC

0.9V_CCto V_CC

8.1.2 XTOUT output buffer and mode setting

The crystal frequency can be sent to pin XTOUT and used in the application, for example

to drive the clock input of a digital demodulator, saving a quartz crystal in the bill of

material. To output f_xtal, it is necessary to set T[2:0] to 001. If the output signal on this pin

is not used, it is recommended to disable it, by setting T[2:0] to 000. This pin is also used

to output ¹⁄₂f_divand f_compin a test mode. At power-on, the XTOUT output buffer is set to

on, supplying the f_xtalsignal. The relation between the signal on pin XTOUT and the

setting of the T[2:0] bits is given in Table 9.

Table 9.

XTOUT buffer status and test modes

T2

0

T1

0

T0

0

Pin XTOUT

disabled

f_xtal(4 MHz)

¹⁄₂f_div

Mode

normal mode with XTOUT buffer off

normal mode with XTOUT buffer on

charge pump off

0

1

0

1

0

1

f_xtal(4 MHz)

f_comp

switch ALBC on or off^[1]

1

0

test mode

1

0

1

¹⁄₂f_div

test mode

1

0

f_xtal(4 MHz)

disabled

charge pump sinking current^[2]

1

charge pump sourcing current

[1] Automatic Loop Bandwidth Control (ALBC) is disabled at power-on reset. After power-on reset this feature

is enabled by setting T[2:0] = 011. To disable again the ALBC, set T[2:0] = 011 again. This test mode acts

like a toggle switch, which means each time it is set the status of the ALBC changes. To toggle the ALBC,

two consecutive Control byte 1s (CB1), should be sent: one byte with T[2:0] = 011 indicating that ALBC will

be switched on or off and one byte programming the test mode to be selected (see Table 30, example of

I²C-bus sequence).

[2] This is the default mode at power-on reset. This mode disables the tuning voltage.

8.1.3 Step frequency setting

The step frequency is set by three bits, giving ﬁve steps to cope with different application

requirements.

The reference divider ratio is automatically set depending on bits R2, R1 and R0. The

phase detector works at either 4 MHz, 2 MHz or 1 MHz.

Table 10 shows the step frequencies and corresponding reference divider ratios. When

the value of bits R2, R1 and R0 are changed, it is necessary to re-send the data bytes

DB1 and DB2.

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

10 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

Table 10. Reference divider ratio select bits

R2

R1

R0

Referencedivider Frequency

Frequency step

ratio

comparison

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

1

4

1

-

2 MHz

4 MHz

1 MHz

4 MHz

-

62.5 kHz

142.86 kHz

166.67 kHz

50 kHz

125 kHz

reserved

-

8.1.4 AGC detector setting

The AGC take-over point can be selected out of 6 levels according to Table 11.

Table 11. AGC programming

AL2

0

AL1

0

AL0

0

Typical take-over point level

124 dBµV (p-p)

121 dBµV (p-p)

118 dBµV (p-p)

115 dBµV (p-p)

112 dBµV (p-p)

109 dBµV (p-p)

I_AGC= 0 A

[1]

[2]

[3]

[4]

0

1

0

1

0

1

0

1

0

1

0

1

V_AGC= 3.5 V

[1] This take-over point is available for both symmetrical and asymmetrical modes.

[2] This take-over point is available for asymmetrical mode only.

[3] The AGC current sources are disabled. The AGC output goes into a high-impedance state and an external

AGC source can be connected in parallel and will not be inﬂuenced.

[4] The AGC detector is disabled and I_AGC= 9 µA.

8.1.5 Charge pump current setting

The charge pump current can be chosen from 8 values depending on the value of bits

CP2, CP1 and CP0 bits; see Table 12. The programming of the CP bits are not taken into

account when ALBC mode is in use.

Table 12. Charge pump current

CP2

CP1

CP0

Charge pump current

number

Typical current (absolute

value in µA)

0

1

0

1

0

1

0

1

0

1

2

3

4

5

38

54

83

122

163

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

11 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

Table 12. Charge pump current…continued

CP2

CP1

CP0

Charge pump current

number

Typical current (absolute

value in µA)

1

0

1

0

1

6

7

8

254

400

580

8.1.6 Automatic Loop Bandwidth Control (ALBC)

In a PLL controlled VCO in which the PLL reduces phase noise close to the carrier, there

is an optimum loop bandwidth corresponding to the minimum integrated phase jitter. This

loop bandwidth depends on different parameters like the VCO slope, the loop ﬁlter

components, the dividing ratio and the gain of the phase detector and charge pump.

In order to reach the best phase noise performance it is necessary, especially in a

wideband system like a digital tuner, to set the charge pump current to different values

depending on the band and frequency used. This is to cope with the variations of the

different parameters that set the bandwidth. The selection can be done in the application

and requires for each frequency to program not only the divider ratios, but also the band

and the best charge pump current.

The TDA6650TT; TDA6651TT includes the ALBC feature that automatically sets the band

and the charge pump current, provided the IC is used in the DVB-T standard application

shown in Figure 27 and 28. This feature is activated by setting bits T[2:0] = 011 after

power-on reset. This feature is disabled when the same bits are set again. When ALBC is

activated, the output ports BS1, BS2 and BS3 are not programmed by the corresponding

BS bits, but are set according to Table 13 and 14. When ALBC is active, bit ALBC = 1.

Table 14 summarizes the programming of the band selection and the charge pump

current when ALBC is active.

Table 13. ALBC settings

Bit

Band

selected current

Charge pump Port

BS3

ALBC

0

BS3

BS2

BS1

BS2

BS1

X

0

high

see Table 14

follows off

bit BS3

off

0

X

0

1

0

low

see Table 14

follows off

bit BS3

on

off

mid

follows on

bit BS3

0

1

X

1

forbidden

X

depends on LO program, shown in Table 14

Table 14. ALBC band selection and charge current setting

LO frequency

Band

Charge pump current

number

80 MHz to 92 MHz

92 MHz to 144 MHz

144 MHz to 156 MHz

156 MHz to 176 MHz

176 MHz to 184 MHz

low

2

3

4

5

6

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

12 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

Table 14. ALBC band selection and charge current setting…continued

LO frequency

Band

Charge pump current

number

184 MHz to 196 MHz

196 MHz to 224 MHz

224 MHz to 296 MHz

296 MHz to 380 MHz

380 MHz to 404 MHz

404 MHz to 448 MHz

448 MHz to 472 MHz

472 MHz to 484 MHz

484 MHz to 604 MHz

604 MHz to 676 MHz

676 MHz to 752 MHz

752 MHz to 868 MHz

868 MHz to 904 MHz

low

7

2

3

4

5

6

7

8

4

5

6

7

8

mid

high

8.2 Read mode; R/W = 1

Data can be read from the device by setting the R/W bit to 1 (see Table 15). After the

device address has been recognized, the device generates an acknowledge pulse and the

ﬁrst data byte (status byte) is transferred on the SDA line (MSB ﬁrst). Data is valid on the

SDA line during a HIGH level of the SCL clock signal.

A second data byte can be read from the device if the microcontroller generates an

acknowledge on the SDA line (master acknowledge). End of transmission will occur if no

master acknowledge occurs. The device will then release the data line to allow the

microcontroller to generate a STOP condition.

Table 15. I²C-bus read data format

Name

Byte Bit

MSB^[1]

ACK

LSB

R/W = 1 A

A0

Address byte 1

Status byte

1

0

1

0

MA1

A2

MA0

A1

2

POR

FL

ALBC

AGC

-

[1] MSB is transmitted ﬁrst.

Table 16. Description of read data format bits

Bit

A

Description

acknowledge bit

POR

power-on reset ﬂag

POR = 0, normal operation

POR = 1, power-on reset

in-lock ﬂag

FL

FL = 0, not locked

FL = 1, the PLL is locked

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

13 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

Table 16. Description of read data format bits…continued

Bit

Description

ALBC

automatic loop bandwidth control ﬂag

ALBC = 0, no automatic loop bandwidth control

ALBC = 1, automatic loop bandwidth control selected

internal AGC ﬂag

AGC

AGC = 0 when internal AGC is active (V_AGC< V_RML

)

AGC = 1 when internal AGC is not active (V_AGC> V_RMH

)

A2, A1, A0

digital outputs of the 5-level ADC; see Table 17

Table 17. ADC levels

Voltage applied to pin ADC^[1]

0.6V_CCto V_CC

A2

1

A1

A0

0

1

0

0.45V_CCto 0.6V_CC

0.3V_CCto 0.45V_CC

0.15V_CCto 0.3V_CC

0 V to 0.15V_CC

0

1

0

1

0

[1] Accuracy is ±0.03V_CC. Bit BS5 must be set to logic 0 to disable the BS5 output port. The BS5 output port

uses the same pin as the ADC and can not be used when the ADC is in use.

8.3 Status at power-on reset

At power on or when the supply voltage drops below approximately 2.85 V (at

T_amb= 25 °C), internal registers are set according to Table 18.

At power on, the charge pump current is set to 580 µA, the test bits T[2:0] are set to 110

which means that the charge pump is sinking current, the tuning voltage output is disabled

and the ALBC function is disabled. The XTOUT buffer is on, driving the 4 MHz signal from

the crystal oscillator and all the ports are off. As a consequence, the high band is selected

by default.

Table 18. Default setting at power-on reset

Name

Byte

Bit^[1]

MSB

LSB

Address byte

1

2

3

4

1

0

MA1

MA0

X

Divider byte 1 (DB1)

Divider byte 2 (DB2)

Control byte 1 (CB1)

0

N14 = X

N13 = X N12 = X N11 = X N10 = X N9 = X

N8 = X

N0 = X

R0 = X

AL0 = 0

N7 = X

N6 = X

N5 = X

N4 = X

T1 = 1

0

N3 = X

T0 = 0

N2 = X

R2 = X

N1 = X

R1 = X

AL1 = 1

1

T/A = X^[2]T2 = 1

T/A = X^[3]

0

ATC = 0 AL2 = 0

Control byte 2 (CB2)

5

CP2 = 1 CP1 = 1

CP0 = 1 BS5 = 0 BS4 = 0 BS3 = 0 BS2 = 0 BS1 = 0

[1] X means that this bit is not set or reset at power-on reset.

[2] The next six bits are written, when bit T/A = 1 in a write sequence.

[3] The next six bits are written, when bit T/A = 0 in a write sequence.

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

14 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

9. Internal circuitry

Table 19. Internal pin conﬁguration

Symbol

Average DC voltage versus band Description^[1]

selection

TDA6650TT TDA6651TT Low

Mid

n.a

High

1.0 V

HBIN1

HBIN2

1

2

38

37

n.a.

(38) 1

2 (37)

fce899

MBIN

3

4

5

36

35

34

n.a.

1.8 V

-

1.8 V

n.a.

-

n.a.

n.a

-

(36) 3

fce901

LBIN

(35) 4

fce898

RFGND

5 (34)

fce897

IFFIL1

IFFIL2

6

7

33

32

3.7 V

7 (32)

(33) 6

fce896

BS4

8

31

high-Z or

V_CC− V_DSV_CC− V_DSV_CC− V_DS

8 (31)

fce895

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

15 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

Table 19. Internal pin conﬁguration…continued

Symbol

Average DC voltage versus band Description^[1]

selection

TDA6650TT TDA6651TT Low

Mid

High

AGC

9

30

0 V or

3.5 V

0 V or

3.5 V

0 V or

3.5 V

9 (30)

fce907

BS3

BS2

BS1

BVS

10

11

12

13

29

28

27

26

high-Z or

V_CC− V_DS

V_CC− V_DSV_CC− V_DS

10 (29)

fce893

high-Z

V_CC− V_DShigh-Z

11 (28)

fce892

V_CC− V_DShigh-Z

high-Z

2.5 V

12 (27)

fce891

2.5 V

(26) 13

mce163

ADC/BS5

14

25

V

_CEsator

V_CEsator

high-Z

V_CEsator

high-Z

(25) 14

fce887

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

16 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

Table 19. Internal pin conﬁguration…continued

Symbol

Average DC voltage versus band Description^[1]

selection

TDA6650TT TDA6651TT Low

Mid

High

SCL

15

24

high-Z

(24) 15

fce889

SDA

16

23

high-Z

(23) 16

fce888

AS

17

18

22

21

1.25 V

(22) 17

fce890

XTOUT

3.45 V

18 (21)

mce164

XTAL1

XTAL2

19

20

19

2.2 V

20 (19)

fce883

19 (20)

n.c.

21

18

n.a.

not connected

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

17 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

Table 19. Internal pin conﬁguration…continued

Symbol

Average DC voltage versus band Description^[1]

selection

TDA6650TT TDA6651TT Low

Mid

High

VT

22

17

V_VT

22 (17)

fce884

CP

23

16

1.8 V

23 (16)

fce885

V_CCD

24

25

15

14

5 V

-

5 V

-

5 V

-

PLLGND

25 (14)

fce882

V_CCA

26

27

28

13

12

11

5 V

IFOUTB

IFOUTA

2.1 V

28 (11)

fce886

IFGND

29

30

10

-

29 (10)

fce880

HOSCIN1

9

8

7

6

2.2 V

5 V

2.2 V

5 V

1.8 V

2.5 V

1.8 V

HOSCOUT1 31

HOSCOUT2 32

5 V

32 (7)

30 (9)

(8) 31

(6) 33

HOSCIN2

33

2.2 V

fce879

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

18 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

Table 19. Internal pin conﬁguration…continued

Symbol

Average DC voltage versus band Description^[1]

selection

TDA6650TT TDA6651TT Low

Mid

High

2.3 V

MOSCIN1

MOSCIN2

34

35

5

4

2.3 V

1.3 V

35 (4)

fce878

34 (5)

OSCGND

36

3

-

36 (3)

fce908

LOSCOUT

LOSCIN

37

38

2

1

1.7 V

2.9 V

1.4 V

3.5 V

1.4 V

3.5 V

37 (2)

(1) 38

fce877

[1] The pin numbers in parenthesis refer to the TDA6651TT.

10. Limiting values

Table 20. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Positive currents are

entering the IC and negative currents are going out of the IC; all voltages are referenced to ground

[1]

.

Symbol

V_CCA

V_CCD

V_VT

Parameter

Conditions

Min

Max

+6

Unit

V

analog supply voltage

digital supply voltage

tuning voltage output

−0.3

+6

V

+35

+6

V

V_SDA

serial data input and output

voltage

V

I_SDA

serial data output current

during

0

10

mA

acknowledge

V_SCL

V_AS

serial clock input voltage

−0.3

+6

V

address selection input

voltage

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

19 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

Table 20. Limiting values…continued

In accordance with the Absolute Maximum Rating System (IEC 60134). Positive currents are

entering the IC and negative currents are going out of the IC; all voltages are referenced to ground

[1]

.

Symbol

Parameter

Conditions

Min

Max

Unit

V_n

voltage on all other inputs,

outputs and combined

inputs and outputs, except

grounds

4.5 V < V_CC< 5.5 V

−0.3

V_CC+ 0.3

V

I_BSn

PMOS port output current

corresponding port

on; open-drain

−20

−50

-

0

mA

s

I_BS(tot)

t_sc(max)

sum of all PMOS port output open-drain

currents

0

maximum short-circuit time each pin to V_CCor

to ground

10

T_stg

T_amb

T_j

storage temperature

ambient temperature

junction temperature

−40

−20

-

+150

°C

[2]

T_amb(max)

150

[1] Maximum ratings cannot be exceeded, not even momentarily without causing irreversible IC damage.

Maximum ratings cannot be accumulated.

[2] The maximum allowed ambient temperature T_amb(max)depends on the assembly conditions of the package

and especially on the design of the printed-circuit board. The application mounting must be done in such a

way that the maximum junction temperature is never exceeded. An estimation of the junction temperature

can be obtained through measurement of the temperature of the top center of the package (T_package). The

temperature difference junction to case (∆T_j-c) is estimated at about 13 °C on the demo board (PCB 827-3).

The junction temperature: T_j= T_package+ ∆T_j-c

.

11. Thermal characteristics

Table 21. Thermal characteristics

Symbol

Parameter

Conditions

Typ

Unit

[1][2][3]

R_th(j-a)

thermal resistance from in free air

junction to ambient

TDA6650TT

TDA6651TT

82

74

K/W

[1] Measured in free air as deﬁned by JEDEC standard JESD51-2.

[2] These values are given for information only. The thermal resistance depends strongly on the nature and

design of the printed-circuit board used in the application.The thermal resistance given corresponds to the

value that can be measured on a multilayer printed-circuit board (4 layers) as deﬁned by JEDEC standard.

[3] The junction temperature inﬂuences strongly the reliability of an IC. The printed-circuit board used in the

application contributes in a large part to the overall thermal characteristic. It must therefore be insured that

the junction temperature of the IC never exceeds T_j(max)= 150 °C at the maximum ambient temperature.

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

20 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

12. Characteristics

Table 22. Characteristics

V_CCA= V_CCD= 5 V; T_amb= 25 °C; values are given for an asymmetrical IF output loaded with a 75 Ω load or with a

symmetrical IF output loaded with 1.25 kΩ; positive currents are entering the IC and negative currents are going out of the IC;

the performances of the circuits are measured in the measurement circuits Figure 27 and 28 for digital application or in the

measurement circuits Figure 29 and 30 for hybrid application; unless otherwise speciﬁed.

Symbol

Supply

V_CC

Parameter

Conditions

Min

Typ Max

Unit

supply voltage

supply current

4.5

80

5.0

96

5.5

V

I_CC

PMOS ports off

115

mA

one PMOS port on: sourcing 15 mA

96

112 131

117 136

two PMOS ports on: one port sourcing

15 mA and one other port sourcing 5 mA

101

General functions

V_POR

power-on reset supply

power-on reset active if V_CC< V_POR

-

2.85 3.5

V

voltage

∆f_lock

frequency range the PLL

is able to synthesize

64

-

1024 MHz

Crystal oscillator^[1]

f_xtal

crystal frequency

-

4.0

-

MHz

|Z_xtal

|

input impedance

(absolute value)

f_xtal= 4 MHz; V_CC= 4.5 V to 5.5 V;

_amb= −20 °C to + T_amb(max), see Section 10

350

430

Ω

T

[2]

P_xtal

crystal drive level

f_xtal= 4 MHz

-

70

-

µW

PMOS ports: pins BS1, BS2, BS3, BS4 and BS5

I_LO(off)

output leakage current in V_CC= 5.5 V; V_BS= 0 V

off state

−10

-

µA

V_DS(sat)

output saturation voltage only corresponding buffer is on, sourcing

-

0.2

0.4

V

15 mA; V_DS(sat)= V_CC− V_BS

ADC input: pin ADC

V_i

ADC input voltage

see Table 17

HIGH-level input current V_ADC= V_CC

LOW-level input current V_ADC= 0 V

0

-

5.5

10

-

V

I_IH

I_IL

-

µA

−10

Address selection input: pin AS

I_IH

I_IL

HIGH-level input current V_AS= 5.5 V

LOW-level input current V_AS= 0 V

-

10

-

µA

−10

Bus voltage selection input: pin BVS

I_IH

I_IL

HIGH-level input current V_BVS= 5.5 V

LOW-level input current V_BVS= 0 V

-

100

-

µA

−100

Buffered output: pin XTOUT

V_o(p-p)square wave AC output

[3]

-

400

175

-

mV

voltage (peak-to peak

value)

Z_o

output impedance

Ω

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

21 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

Table 22. Characteristics…continued

V_CCA= V_CCD= 5 V; T_amb= 25 °C; values are given for an asymmetrical IF output loaded with a 75 Ω load or with a

symmetrical IF output loaded with 1.25 kΩ; positive currents are entering the IC and negative currents are going out of the IC;

the performances of the circuits are measured in the measurement circuits Figure 27 and 28 for digital application or in the

measurement circuits Figure 29 and 30 for hybrid application; unless otherwise speciﬁed.

Symbol

I²C-bus

Parameter

Conditions

Min

Typ Max

Unit

Inputs: pins SCL and SDA

f_clk

V_IL

clock frequency

frequency on SCL

-

400

0.75

1.0

1.5

5.5

10

kHz

V

LOW-level input voltage V_BVS= 0 V

V_BVS= 2.5 V or open-circuit

0

V

V_BVS= 5 V

0

V

V_IH

HIGH-level input voltage V_BVS= 0 V

1.75

2.3

3.0

-

V

V_BVS= 2.5 V or open-circuit

V

V_BVS= 5 V

HIGH-level input current V_CC= 0 V; V_BUS= 5.5 V

V_CC= 5.5 V; V_BUS= 5.5 V

V

I_IH

µA

-

10

I_IL

LOW-level input current V_CC= 0 V; V_BUS= 1.5 V

V_CC= 5.5 V; V_BUS= 0 V

-

10

−10

-

Output: pin SDA

I_LH

leakage current

V_SDA= 5.5 V

I_SDA= 3 mA

-

10

µA

V_O(ack)

output voltage during

acknowledge

0.4

V

Charge pump output: pin CP

|I_o|

output current (absolute see Table 12

value)

-

µA

I_L(off)

off-state leakage current charge pump off (T[2:0] = 010)

−15

0

+15

nA

Tuning voltage output: pin VT

I_L(off)

leakage current when

switched-off

tuning supply voltage = 33 V

-

10

µA

V_o(cl)

output voltage when the tuning supply voltage = 33 V; R_L= 15 kΩ

0.3

32.7

V

loop is closed

Noise performance

J_φ(rms)

phase jitter (RMS value) integrated between 1 kHz and 1 MHz offset

from the carrier

digital only application:

TDA6650TT/C3/S2; TDA6651TT/C3/S2;

TDA6651TT/C3/S3

-

0.5

0.6

-

deg

hybrid application: TDA6650TT/C3;

TDA6651TT/C3

Low band mixer, including IF ampliﬁer

[4]

f_RF

RF frequency

picture carrier for digital only application:

TDA6650TT/C3/S2; TDA6651TT/C3/S2;

TDA6651TT/C3/S3

47.00

43.25

-

160.00 MHz

157.25 MHz

picture carrier for hybrid application:

TDA6650TT/C3; TDA6651TT/C3

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

22 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

Table 22. Characteristics…continued

V_CCA= V_CCD= 5 V; T_amb= 25 °C; values are given for an asymmetrical IF output loaded with a 75 Ω load or with a

symmetrical IF output loaded with 1.25 kΩ; positive currents are entering the IC and negative currents are going out of the IC;

the performances of the circuits are measured in the measurement circuits Figure 27 and 28 for digital application or in the

measurement circuits Figure 29 and 30 for hybrid application; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ Max

Unit

G_v

voltage gain

asymmetrical IF output; R_L= 75 Ω;

see Figure 14

f_RF= 44.25 MHz

f_RF= 157.25 MHz

21

24

27

dB

symmetrical IF output; R_L= 1.25 kΩ;

see Figure 15

f_RF= 44.25 MHz

25

28

31

dB

f_RF= 157.25 MHz

NF

V_o

noise ﬁgure

see Figure 16 and 17

f_RF= 50 MHz

-

8.0

10.0

dB

f_RF= 150 MHz

[5]

output voltage causing

1 % cross modulation in

channel

asymmetrical application; see Figure 18

f_RF= 44.25 MHz

107

110

-

dBµV

f_RF= 157.25 MHz

symmetrical application; see Figure 19

f_RF= 44.25 MHz

117

-

120

90

-

dBµV

f_RF= 157.25 MHz

V_i

input voltage causing

750 Hz frequency

deviation pulling in

channel

asymmetrical IF output

[6]

[7]

INT_SO2

V_i(lock)

G_i

channel SO2 beat

hybrid application: TDA6650TT/C3;

TDA6651TT/C3; V_RFpix= 80 dBµV

57

-

60

-

dBc

input level without

lock-out

see Figure 25

120

dBµV

input conductance

f_RF= 44.25 MHz; see Figure 5

f_RF= 157.25 MHz; see Figure 5

-

0.13

0.11

1.36

-

mS

pF

C_i

input capacitance

f_RF= 44.25 MHz to 157.25 MHz;

see Figure 5

Mid band mixer, including IF ampliﬁer

[4]

f_RF

RF frequency

picture carrier for digital only application:

TDA6650TT/C3/S2; TDA6651TT/C3/S2;

TDA6651TT/C3/S3

160.00 -

157.25 -

446.00 MHz

443.25 MHz

picture carrier for hybrid application:

TDA6650TT/C3; TDA6651TT/C3

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

23 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

Table 22. Characteristics…continued

V_CCA= V_CCD= 5 V; T_amb= 25 °C; values are given for an asymmetrical IF output loaded with a 75 Ω load or with a

symmetrical IF output loaded with 1.25 kΩ; positive currents are entering the IC and negative currents are going out of the IC;

the performances of the circuits are measured in the measurement circuits Figure 27 and 28 for digital application or in the

measurement circuits Figure 29 and 30 for hybrid application; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ Max

Unit

G_v

voltage gain

asymmetrical IF output; load = 75 Ω;

see Figure 14

f_RF= 157.25 MHz

f_RF= 443.25 MHz

21

24

27

dB

symmetrical IF output; load = 1.25 kΩ;

see Figure 15

f_RF= 157.25 MHz

25

28

31

dB

f_RF= 443.25 MHz

NF

V_o

noise ﬁgure

see Figure 16 and 17

f_RF= 150 MHz

-

8.0

9.0

10.0

11.0

dB

f_RF= 300 MHz

[5]

[8]

output voltage causing

1 % cross modulation in

channel

asymmetrical application; see Figure 18

f_RF= 157.25 MHz

107

110

-

dBµV

f_RF= 443.25 MHz

symmetrical application; see Figure 19

f_RF= 157.25 MHz

117

-

120

80

-

dBµV

f_RF= 443.25 MHz

V_f(N+5)−1

V_i

(N + 5) − 1 MHz pulling

f_RF(wanted)= 443.25 MHz; f_osc= 482.15 MHz;

f_RF(unwanted)= 482.25 MHz

input voltage causing

750 Hz frequency

deviation pulling in

channel

asymmetrical IF output

-

89

-

dBµV

[7]

V_i(lock)

input level without

lock-out

see Figure 25

-

120

dBµV

G_i

C_i

input conductance

input capacitance

see Figure 6

-

0.3

1.1

-

mS

pF

High band mixer, including IF ampliﬁer

[4]

f_RF

RF frequency

picture carrier for digital only application:

TDA6650TT/C3/S2; TDA6651TT/C3/S2;

TDA6651TT/C3/S3

446.00 -

443.25 -

866.00 MHz

863.25 MHz

picture carrier for hybrid application:

TDA6650TT/C3; TDA6651TT/C3

G_v

voltage gain

asymmetrical IF output; load = 75 Ω;

see Figure 20

f_RF= 443.25 MHz

f_RF= 863.25 MHz

31.5

34.5 37.5

dB

symmetrical IF output; load = 1.25 kΩ;

see Figure 21

f_RF= 443.25 MHz

f_RF= 863.25 MHz

35.5

38.5 41.5

dB

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

24 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

Table 22. Characteristics…continued

V_CCA= V_CCD= 5 V; T_amb= 25 °C; values are given for an asymmetrical IF output loaded with a 75 Ω load or with a

symmetrical IF output loaded with 1.25 kΩ; positive currents are entering the IC and negative currents are going out of the IC;

the performances of the circuits are measured in the measurement circuits Figure 27 and 28 for digital application or in the

measurement circuits Figure 29 and 30 for hybrid application; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ Max

Unit

NF

noise ﬁgure, not

see Figure 22

corrected for image

f_RF= 443.25 MHz

-

6.0

7.0

8.0

9.0

dB

f_RF= 863.25 MHz

[5]

V_o

output voltage causing

1 % cross modulation in

channel

asymmetrical application; see Figure 23

f_RF= 443.25 MHz

107

110

-

dBµV

f_RF= 863.25 MHz

symmetrical application; see Figure 24

f_RF= 443.25 MHz

117

-

120

-

dBµV

f_RF= 863.25 MHz

-

[7]

[8]

V_i(lock)

V_f(N+5)−1

V_i

input level without

lock-out

see Figure 26

120

(N + 5) − 1 MHz pulling

f_RF(wanted)= 815.25 MHz; f_osc= 854.15 MHz;

-

80

79

-

dBµV

f_RF(unwanted)= 854.25 MHz

input voltage causing

750 Hz frequency

deviation pulling in

channel

asymmetrical IF output

Z_i

input impedance

f_RF= 443.25 MHz; see Figure 7

(R_S+ jL_Sω)

R_S

-

35

8

-

Ω

L_S

nH

f_RF= 863.25 MHz; see Figure 7

R_S

L_S

-

36

8

-

Ω

nH

Low band oscillator

[9]

f_osc

oscillator frequency

83.15

-

196.15 MHz

[10]

∆f_osc(V)

oscillator frequency shift

with supply voltage

110

-

kHz

[11]

∆f_osc(T)

oscillator frequency drift ∆T = 25 °C; V_CC= 5 V with compensation

-

900

-

kHz

with temperature

Φ_osc(dig)

phase noise, carrier to

TDA6650TT/C3/S2; TDA6651TT/C3/S2;

sideband noise in digital TDA6651TT/C3/S3

application

±1 kHz frequency offset; f_comp= 4 MHz;

82

87

95

-

dBc/Hz

see Figure 8, 27 and 28

±10 kHz frequency offset; worst case in

the frequency range;

100

see Figure 9, 27 and 28

±100 kHz frequency offset; worst case in

the frequency range;

see Figure 10, 27 and 28

104

-

110

117

-

dBc/Hz

±1.4 MHz frequency offset; worst case in

the frequency range; see Figure 27 and 28

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

25 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

Table 22. Characteristics…continued

V_CCA= V_CCD= 5 V; T_amb= 25 °C; values are given for an asymmetrical IF output loaded with a 75 Ω load or with a

symmetrical IF output loaded with 1.25 kΩ; positive currents are entering the IC and negative currents are going out of the IC;

the performances of the circuits are measured in the measurement circuits Figure 27 and 28 for digital application or in the

measurement circuits Figure 29 and 30 for hybrid application; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ Max

Unit

Φ_osc(hyb)

phase noise, carrier to

sideband noise in hybrid

application

TDA6650TT/C3; TDA6651TT/C3

±1 kHz frequency offset; f_comp= 4 MHz;

see Figure 11, 29, and 30

80

85

95

96

-

dBc/Hz

±10 kHz frequency offset; worst case in

the frequency range;

see Figure 12, 29, and 30

±100 kHz frequency offset; worst case in

the frequency range;

104

110

-

dBc/Hz

see Figure 13, 29, and 30

±1.4 MHz frequency offset; worst case in

the frequency range; see Figure 29 and 30

-

117

200

-

dBc/Hz

mV

[12]

RSC_p-p

ripple susceptibility of

V_CC= 5 V ± 5 %; worst case in the frequency

15

V_CC(peak-to-peak

range; ripple frequency 500 kHz

value)

Mid band oscillator

[9]

f_osc

oscillator frequency

196.15 -

482.15 MHz

[10]

∆f_osc(V)

oscillator frequency shift

with supply voltage

-

110

-

kHz

[11]

∆f_osc(T)

oscillator frequency drift ∆T = 25 °C; V_CC= 5 V with compensation

-

1500 -

kHz

with temperature

Φ_osc(dig)

phase noise, carrier to

TDA6650TT/C3/S2; TDA6651TT/C3/S2;

sideband noise in digital TDA6651TT/C3/S3

application

±1 kHz frequency offset; f_comp= 4 MHz;

85

87

90

95

-

dBc/Hz

see Figure 8, 27 and 28

±10 kHz frequency offset; worst case in

the frequency range;

see Figure 9, 27 and 28

±100 kHz frequency offset; worst case in

the frequency range;

see Figure 10, 27 and 28

104

-

110

115

-

dBc/Hz

±1.4 MHz frequency offset; worst case in

the frequency range; see Figure 27 and 28

Φ_osc(hyb)

phase noise, carrier to

sideband noise in hybrid

application

TDA6650TT/C3; TDA6651TT/C3

±1 kHz frequency offset; f_comp= 4 MHz;

see Figure 11, 29, and 30

82

85

88

90

-

dBc/Hz

±10 kHz frequency offset; worst case in

the frequency range;

see Figure 12, 29, and 30

±100 kHz frequency offset; worst case in

the frequency range;

see Figure 13, 29, and 30

104

-

110

115

-

dBc/Hz

±1.4 MHz frequency offset; worst case in

the frequency range; see Figure 29 and 30

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

26 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

Table 22. Characteristics…continued

V_CCA= V_CCD= 5 V; T_amb= 25 °C; values are given for an asymmetrical IF output loaded with a 75 Ω load or with a

symmetrical IF output loaded with 1.25 kΩ; positive currents are entering the IC and negative currents are going out of the IC;

the performances of the circuits are measured in the measurement circuits Figure 27 and 28 for digital application or in the

measurement circuits Figure 29 and 30 for hybrid application; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

_CC= 5 V ± 5 %; worst case in the frequency

range; ripple frequency 500 kHz

Min

Typ Max

140

Unit

[12]

RSC_p-p

ripple susceptibility of

V

15

-

mV

V_CC(peak-to-peak

value)

High band oscillator

[9]

f_osc

oscillator frequency

482.15 -

902.15 MHz

[10]

∆f_osc(V)

oscillator frequency shift

with supply voltage

-

300

-

kHz

[11]

∆f_osc(T)

oscillator frequency drift ∆T = 25 °C; V_CC= 5 V; with compensation

-

1100 -

kHz

with temperature

Φ_osc(dig)

phase noise, carrier to

TDA6650TT/C3/S2; TDA6651TT/C3/S2;

sideband noise in digital TDA6651TT/C3/S3

application

±1 kHz frequency offset; f_comp= 4 MHz;

85

87

89

93

-

dBc/Hz

see Figure 8, 27 and 28

±10 kHz frequency offset; worst case in

the frequency range;

see Figure 9, 27 and 28

±100 kHz frequency offset; worst case in

the frequency range;

see Figure 10, 27 and 28

104

-

107

117

-

dBc/Hz

±1.4 MHz frequency offset; worst case in

the frequency range; see Figure 27 and 28

Φ_osc(hyb)

phase noise, carrier to

sideband noise in hybrid

application

TDA6650TT/C3; TDA6651TT/C3

±1 kHz frequency offset; f_comp= 4 MHz;

see Figure 11, 29, and 30

80

82

85

86

-

dBc/Hz

±10 kHz frequency offset; worst case in

the frequency range;

see Figure 12, 29, and 30

±100 kHz frequency offset; worst case in

the frequency range;

104

107

-

dBc/Hz

see Figure 13, 29, and 30

±1.4 MHz frequency offset; worst case in

the frequency range; see Figure 29 and 30

-

117

40

-

dBc/Hz

mV

[12]

RSC_p-p

ripple susceptibility of

V_CC= 5 V ± 5 %; worst case in the frequency

15

V_CC(peak-to-peak

range; ripple frequency 500 kHz

value)

IF ampliﬁer

Z_o

output impedance

asymmetrical IF output

R_Sat 38.9 MHz

-

50

-

Ω

L_Sat 38.9 MHz

5.4

nH

symmetrical IF output

R_Sat 38.9 MHz

100

Ω

L_Sat 38.9 MHz

10.4

nH

Rejection at the IF output (IF ampliﬁer in asymmetrical mode)

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

27 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

Table 22. Characteristics…continued

V_CCA= V_CCD= 5 V; T_amb= 25 °C; values are given for an asymmetrical IF output loaded with a 75 Ω load or with a

symmetrical IF output loaded with 1.25 kΩ; positive currents are entering the IC and negative currents are going out of the IC;

the performances of the circuits are measured in the measurement circuits Figure 27 and 28 for digital application or in the

measurement circuits Figure 29 and 30 for hybrid application; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ Max

Unit

[13]

[14]

[15]

INT_div

divider interferences in

IF level

worst case

-

20

dBµV

INT_xtal

crystal oscillator

interferences rejection

V_IF= 100 dBµV; worst case in the frequency

range

-

−50

dBc

INT_f(step)

step frequency rejection measured in digital application for DVB-T;

f_step= 166.67 kHz; IF = 36.125 MHz

TDA6650TT/C3; TDA6651TT/C3;

-

−50

dBc

TDA6650TT/C3/S2; TDA6651TT/C3/S2

TDA6651TT/C3/S3

-

−35

−57

dBc

[15]

[16]

measured in hybrid application for DVB-T;

f_step= 166.67 kHz; IF = 36.125 MHz

measured in hybrid application for PAL;

-

−57

45

dBc

f

_step= 62.5 kHz; IF = 38.9 MHz

measured in hybrid application for FM;

_step= 50 kHz; IF = 38.9 MHz

dBc

f

INT_XTH

crystal oscillator

harmonics in the

IF frequency

dBµV

AGC output (IF ampliﬁer in asymmetrical mode): pin AGC^[17]

AGC_TOP(p-p)AGC take-over point

(peak-to-peak level)

bits AL[2:0] = 000

122.5 124 125.5 dBµV

I_source(fast)

source current fast

7.5

9.0

11.6

µA

I_source(slow)source current slow

185

220 280

nA

V_o

output voltage

maximum level

TDA6650TT/C3; TDA6651TT/C3;

TDA6650TT/C3/S2; TDA6651TT/C3/S2

3.45

3.55 3.8

V

TDA6651TT/C3/S3

minimum level

3.3

0

V

-

0.1

V_o(dis)

output voltage with AGC bits AL[2:0] = 111

disabled

TDA6650TT/C3; TDA6651TT/C3;

3.45

3.55 3.8

V

TDA6650TT/C3/S2; TDA6651TT/C3/S2

TDA6651TT/C3/S3

3.3

-

V

V_RF(slip)

RF voltage range to

-

0.5

dB

switch the AGC from

active to not active mode

V_RML

V_RMH

I_LO

low threshold AGC

output voltage

AGC bit = 0 or AGC not active

AGC bit = 1 or AGC active

0

-

2.8

V

high threshold AGC

output voltage

3.2

−50

3.55 3.8

+50

V

leakage current

bits AL[2:0] = 110; 0 V < V_AGC< 3.5 V

-

nA

[1] Important recommendation: to obtain the performances mentioned in this speciﬁcation, the serial resistance of the crystal used with this

oscillator must never exceed 120 Ω. The crystal oscillator is guaranteed to operate at any supply voltage between 4.5 V and 5.5 V and

at any temperature between −20 °C and T_amb(max), as deﬁned in Section 10.

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

28 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

[2] The drive level is expected with a 50 Ω series resistance of the crystal at series resonance. The drive level will be different with other

series resistance values.

[3] The V_XTOUTlevel is measured when the pin XTOUT is loaded with 5 kΩ in parallel with 10 pF.

[4] The RF frequency range is deﬁned by the oscillator frequency range and the Intermediate Frequency (IF).

[5] The 1 % cross modulation performance is measured with AGC detector turned off (AGC bits set to 110).

[6] Channel SO2 beat is the interfering product of f_RFpix, f_IFand f_oscof channel SO2; f_beat= 37.35 MHz. The possible mechanisms are:

f_osc− 2 × f_IFpixor 2 × f_RFpix− f_osc.

[7] The IF output signal stays stable within the range of the step frequency for any RF input level up to 120 dBµV.

[8] (N + 5) − 1 MHz pulling is the input level of channel N + 5, at frequency 1 MHz lower, causing 100 kHz FM sidebands 30 dB below the

wanted carrier.

[9] Limits are related to the tank circuits used in Figure 27 and 28 for digital application or Figure 29 and 30 for hybrid application.

Frequency bands may be adjusted by the choice of external components.

[10] The frequency shift is deﬁned as a change in oscillator frequency when the supply voltage varies from V_CC= 5 V to 4.5 V or from

V_CC= 5 V to 5.25 V. The oscillator is free running during this measurement.

[11] The frequency drift is deﬁned as a change in oscillator frequency when the ambient temperature varies from T_amb= 25 °C to 50 °C or

from T_amb= 25 °C to 0 °C. The oscillator is free running during this measurement.

[12] The supply ripple susceptibility is measured in the measurement circuit according to Figure 27, 28, 29 and 30 using a spectrum

analyzer connected to the IF output. An unmodulated RF signal is applied to the test board RF input. A sine wave signal with a

frequency of 500 kHz is superimposed onto the supply voltage. The amplitude of this ripple signal is adjusted to bring the 500 kHz

sidebands around the IF carrier to a level of −53.5 dB with respect to the carrier.

[13] This is the level of divider interferences close to the IF frequency. For example channel S3: f_osc= 158.15 MHz, ¹⁄₄f_osc= 39.5375 MHz.

The low and mid band inputs must be left open (i.e. not connected to any load or cable); the high band inputs are connected to an

hybrid.

[14] Crystal oscillator interference means the 4 MHz sidebands caused by the crystal oscillator.

[15] The step frequency rejection is the level of step frequency sidebands (e.g. 166.67 kHz) related to the carrier.

[16] This is the level of the 9th and 11th harmonics of the 4 MHz crystal oscillator into the IF output.

[17] Pin AGC (pin 9 for TDA6650TT, pin 30 for TDA6651TT) must not be connected to a voltage higher than 3.6 V.

1

2

0.5

0.2

5

10

∞

10

− j

+ j

10

5

2

1

0.5

0.2

40 MHz

0

200 MHz

5

0.2

2

0.5

mce160

1

Fig 5. Input admittance (s₁₁) of the low band mixer (40 MHz to 200 MHz); Y_o= 20 mS

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

29 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

1

2

0.5

0.2

5

10

∞

10

− j

10

5

2

1

0.5

0.2

100 MHz

0

+ j

500 MHz

5

0.2

2

0.5

mce161

1

Fig 6. Input admittance (s₁₁) of the mid band mixer (100 MHz to 500 MHz); Y_o= 20 mS

1

0.5

2

900 MHz

0.2

5

400 MHz

0.5

10

+ j

− j

0.2

1

2

5

10

0

∞

10

5

0.2

2

0.5

mce165

1

Fig 7. Input impedance (s₁₁) of the high band mixer (400 MHz to 900 MHz); Z_o= 100 Ω

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

30 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

fce915

−80

Φ_osc

(dBc/Hz)

−85

−90

−95

−100

40

140

240

340

440

540

640

740

840

940

f

(MHz)

RF

For measurement circuit see Figure 27 and 28

Fig 8. 1 kHz phase noise typical performance in digital application

fce916

−80

Φ_osc

(dBc/Hz)

−85

−90

−95

−100

−105

−110

40

140

240

340

440

540

640

740

840

940

f

(MHz)

RF

For measurement circuit see Figure 27 and 28

Fig 9. 10 kHz phase noise typical performance in digital application

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

31 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

fce917

−100

Φ_osc

(dBc/Hz)

−105

−110

−115

−120

40

140

240

340

440

540

640

740

840

940

f

(MHz)

RF

For measurement circuit see Figure 27 and 28

Fig 10. 100 kHz phase noise typical performance in digital application

fce918

−80

Φ_osc

(dBc/Hz)

−85

−90

−95

−100

−105

40

140

240

340

440

540

640

740

840

940

f

(MHz)

RF

For measurement circuit see Figure 29 and 30

Fig 11. 1 kHz phase noise typical performance in hybrid application

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

32 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

fce919

−80

Φ_osc

(dBc/Hz)

−85

−90

−95

−100

−105

40

140

240

340

440

540

640

740

840

940

f

(MHz)

RF

For measurement circuit see Figure 29 and 30

Fig 12. 10 kHz phase noise typical performance in hybrid application

fce920

−100

Φ_osc

(dBc/Hz)

−105

−110

−115

−120

40

140

240

340

440

540

640

740

840

940

f

(MHz)

RF

For measurement circuit see Figure 29 and 30

Fig 13. 100 kHz phase noise typical performance in hybrid application

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

33 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

signal

LBIN

or

source

50 Ω

27 Ω

IFOUTA

spectrum

analyzer

MBIN

DUT

V

e

meas

V

50 Ω

V'

meas

50 Ω

V

i

o

IFOUTB

RMS

voltmeter

V

CCA

fce747

Z_i>> 50 Ω → V_i= 2 × V_meas= 70 dBµV.

V_i= V_meas+ 6 dB = 70 dBµV.

V_o= V’_meas+ 3.75 dB.

V_o

G = 20log

------

v

V_i

DVB-T and PAL.

IF = 38.9 MHz.

Fig 14. Gain (G_V) measurement in low and mid band with asymmetrical IF output

signal

50 Ω source

LBIN

or

transformer

IFOUTA

spectrum

analyzer

MBIN

V

DUT

N1

N2

V'

meas

C

e

50 Ω

V

i

V

o

meas

IFOUTB

RMS

voltmeter

fce748

Z_i>> 50 Ω → V_i= 2 × V_meas= 70 dBµV.

V_i= V_meas+ 6 dB = 70 dBµV.

V_o= V’_meas+ 15 dB (transformer ratio N1/N2 = 5 and transformer loss).

V_o

G = 20log

------

v

V_i

N1 = 10 turns.

N2 = 2 turns.

N1/N2 = 5.

DVB-T and PAL.

IF = 38.9 MHz.

Fig 15. Gain (G_V) measurement in low and mid band with symmetrical IF output

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

34 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

NOISE

FIGURE

METER

LBIN

or

MBIN

27 Ω

NOISE

SOURCE

BNC

RIM

IFOUTA

INPUT

CIRCUIT

DUT

IFOUTB

V

CCA

fce750

NF = NF_meas− loss of input circuit (dB).

Fig 16. Noise ﬁgure (NF) measurement in low and mid band with asymmetrical IF output

BNC

connector

BNC

connector

Cs

TL

Cc

Cp

Cc

Cp

Ls

to the IC

mixer input

to the IC

mixer input

Lp

mce452

a. Schematic 1

b. Schematic 2

For f_RF= 50 MHz (Schematic 1)

For f_RF= 300 MHz (Schematic 2)

Loss = 0 dB.

Loss = 0.5 dB.

Cs = 12 pF in parallel with a 0.8 pF to 8 pF trimmer.

Cp = 18 pF in parallel with a 0.8 pF to 8 pF trimmer.

Cc = 4.7 nF.

Cp = 8.2 pF in parallel with a 0.8 pF to 8 pF trimmer.

Cc = 4.7 nF.

Ls = 2 turns, 1.5 mm, wire = 0.4 mm air coil.

Lp = 2 turns, 1.5 mm, wire = 0.4 mm air coil.

TL = 50 Ω semi rigid cable, length = 75 mm.

Lp = 8 turns, 5 mm, wire = 0.4 mm air coil

TL = 50 Ω semi rigid cable, length = 75 mm.

For f_RF= 150 MHz (Schematic 1)

Loss = 0 dB.

Cs = 0.8 pF to 8 pF trimmer.

Cp = 0.4 pF to 2.5 pF trimmer.

Cc = 4.7 nF.

Lp = 4 turns, 4.5 mm, wire = 0.4 mm air coil

TL = 50 Ω semi rigid cable, length = 75 mm.

Fig 17. Input circuit for optimum noise ﬁgure in low and mid band

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

35 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

FILTER

10 dB

attenuator

AM = 30 %

1 kHz

LBIN

or

MBIN

50 Ω

27 Ω

A

C

IFOUTA

modulation

analyzer

unwanted

signal

source

e

u

38.9 MHz

V

o

HYBRID

DUT

V

meas

50 Ω

V

50 Ω

IFOUTB

B

D

wanted

signal

e

w

50 Ω

RMS

voltmeter

V

CCA

source

fce749

V_o= V_meas+ 3.75 dB.

Wanted signal source at f_RFpixis 80 dBµV.

Unwanted output signal at f_snd

.

The level of unwanted signal is measured by causing 0.3 % AM modulation in the wanted signal.

Fig 18. Cross modulation measurement in low and mid band with asymmetrical IF output

FILTER

6 dB

attenuator

AM = 30 %

1 kHz

LBIN

or

MBIN

50 Ω

transformer

A

IFOUTA

C

modulation

analyzer

unwanted

signal

e

u

38.9 MHz

source

HYBRID

C

N2

DUT

N1

o

V

V'

meas

50 Ω

V

50 Ω

B

D

IFOUTB

wanted

signal

e

w

RMS

voltmeter

source

50 Ω

fce793

V’_meas= V_o− (transformer ratio N1/N2 = 5 and loss).

Wanted signal source at f_RFpixis 80 dBµV.

The level of unwanted signal V_oat f_sndis measured by causing 0.3 % AM modulation in the wanted output signal.

N1 = 10 turns.

N2 = 2 turns.

N1/N2 = 5.

Fig 19. Cross modulation measurement in low and mid band with symmetrical IF output

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

36 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

signal

source

50 Ω

27 Ω

A

HBIN1

HBIN2

C

IFOUTA

spectrum

analyzer

DUT

HYBRID

V

V'

meas

e

o

50 Ω

V

50 Ω

V

i

meas

IFOUTB

B

D

50 Ω

RMS

voltmeter

V

CCA

fce751

Loss in hybrid = 1 dB.

V_i= V_meas− loss = 70 dBµV.

V_o= V’_meas+ 3.75 dB.

V_o

G = 20log

.

------

v

V_i

DVB-T and PAL.

IF = 38.9 MHz.

Fig 20. Gain (G_V) measurement in high band with asymmetrical IF output

signal

source

50 Ω

transformer

C

D

HBIN1

HBIN2

IFOUTA

A

spectrum

analyzer

DUT

HYBRID

V

meas

C

N1

N2

V'

V

i

50 Ω

e

V

50 Ω

V

o

meas

B

IFOUTB

50 Ω

RMS

voltmeter

fce752

Loss in hybrid = 1 dB.

V_i= V_meas− loss = 70 dBµV.

V_o= V’_meas+ 15 dB (transformer ratio N1/N2 = 5 and transformer loss).

V_o

G = 20log

.

------

v

V_i

DVB-T and PAL.

IF = 38.9 MHz.

Fig 21. Gain (G_V) measurement in high band with symmetrical IF output

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

37 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

NOISE

FIGURE

METER

27 Ω

NOISE

SOURCE

A

HBIN1 IFOUTA

C

HYBRID

DUT

B

D

IFOUTB

HBIN2

50 Ω

V

CCA

fce753

Loss in hybrid = 1 dB.

NF = NF_meas− loss.

Fig 22. Noise ﬁgure (NF) measurement in high band with asymmetrical IF output

FILTER

AM = 30 %

1 kHz

10 dB

attenuator

50 Ω

27 Ω

A

C

HBIN1

IFOUTA

IFOUTB

modulation

analyzer

unwanted

signal

source

e

u

38.9 MHz

HYBRID

DUT

V

o

V

50 Ω

V

meas

50 Ω

B

D

B

D

HBIN2

wanted

signal

source

e

w

50 Ω

V

CCA

RMS

voltmeter

fce754

Wanted signal source at f_RFpixis 70 dBµV.

Unwanted output signal at f_snd

.

The level of unwanted signal is measured by causing 0.3 % AM modulation in the wanted signal.

Fig 23. Cross modulation measurement in high band with asymmetrical IF output

FILTER

6 dB

attenuator

AM = 30 %

1 kHz

transformer

50 Ω

A

C

A

C

HBIN1 IFOUTA

DUT

modulation

unwanted

signal

source

analyzer

e

u

38.9 MHz

HYBRID

V'

N1

N2

C

V

meas

50 Ω

V

o

50 Ω

B

D

HBIN2 IFOUTB

B

wanted

signal

source

e

w

50 Ω

RMS

voltmeter

fce794

V’_meas= V_o− (transformer ratio N1/N2 = 5 and loss)

The level of unwanted signal is measured by causing 0.3 % AM modulation in the wanted signal.

N1 = 10 turns.

N2 = 2 turns.

N1/N2 = 5.

Fig 24. Cross modulation measurement in high band with symmetrical IF output

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

38 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

signal

source

LBIN

or

27 Ω

50 Ω

IFOUTA

spectrum

analyzer

MBIN

DUT

e

V

meas

50 Ω

V

50 Ω

IFOUTB

RMS

voltmeter

V

CCA

fce755

Z_i>> 50 Ω → V_i= 2 × V_meas

.

V_i= V_meas+ 6 dB.

Fig 25. Maximum RF input level without lock-out in low and mid band with asymmetrical

IF output

signal

source

27 Ω

50 Ω

A

HBIN1

HBIN2

IFOUTA

IFOUTB

C

spectrum

analyzer

DUT

HYBRID

V

meas

50 Ω

V

50 Ω

e

i

B

D

50 Ω

RMS

voltmeter

V

CCA

fce756

Loss in hybrid = 1 dB.

V_i= V_meas− loss.

Fig 26. Maximum RF input level without lock-out in high band with asymmetrical IF output

12.1 PLL loop stability of measurement circuit

The TDA6650TT; TDA6651TT PLL loop stability is guaranteed in the conﬁguration of

Figure 27, 28, 29 and 30. In this conﬁguration, the external supply source is 30 V

minimum, the pull-up resistor R19 is 15 kΩ and all of the local oscillators are aligned to

operate at a maximum tuning voltage of 26 V. If the conﬁguration is changed, there might

be an impact on the loop stability.

For any other conﬁgurations, a stability analysis must be performed. The conventional PLL

AC model used for the stability analysis, is valid provided the external source (DC supply

source or DC-to-DC converter) is able to deliver a minimum current that is equal to the

charge pump current in use.

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

39 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

The delivered current can be simply calculated with the following formula:

V

– V

T

DC

I

=

> I

(1)

------------------------

delivered

CP

R

pu

where:

I_deliveredis the delivered current.

V_DCis the supply source voltage or DC-to-DC converter output voltage.

V_Tis the tuning voltage.

R_puis the pull-up resistor between the DC supply source (or the DC-to-DC converter

output) and the tuning line (R19 in Figure 27 to 30).

I_CPis the charge pump current in use.

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

40 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

13. Application information

13.1 Tuning ampliﬁer

The tuning ampliﬁer is capable of driving the varicap voltage without an external transistor.

The tuning voltage output must be connected to an external load of 15 kΩ which is

connected to the tuning voltage supply rail. The loop ﬁlter design depends on the oscillator

characteristics and the selected reference frequency as well as the required PLL loop

bandwidth.

Applications with the TDA6650TT; TDA6651TT have a large loop bandwidth, in the order

of a few tens of kHz. The calculation of the loop ﬁlter elements has to be done for each

application, it depends on the reference frequency and charge pump current.

13.2 Crystal oscillator

The TDA6650TT; TDA6651TT needs to be used with a 4 MHz crystal in series with a

capacitor with a typical value of 18 pF, connected between pin XTAL1 and pin XTAL2.

NXP crystal 4322 143 04093 is recommended. When choosing a crystal, take care to

select a crystal able to withstand the drive level of the TDA6650TT; TDA6651TT without

suffering from accelerated ageing. For optimum performances, it is highly recommended

to connect the 4 MHz crystal without any serial resistance.

The crystal oscillator of the TDA6650TT; TDA6651TT should not be driven (forced) from

an external signal.

Do not use the signal on pin XTAL1 or pin XTAL2, or the signal present on the crystal, to

drive an external IC or for any other use as this may dramatically degrade the phase noise

performance of the TDA6650TT; TDA6651TT.

13.3 Examples of I²C-bus program sequences

Table 23 to 30 show various sequences where:

S = START

A = acknowledge

P = STOP.

The following conditions apply:

LO frequency is 800 MHz

f_comp= 166.666 kHz

Divider ratio (programmable) N = 4800

BS3 output port is on and all other ports are off: thus the high band is selected

Charge pump current I_CP= 280 µA

Normal mode, with XTOUT buffer on

I_AGC= 220 nA

AGC take-over point is set to 112 dBµV (p-p)

Address selection is adjusted to make address C2 valid.

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

45 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

To fully program the device, either sequence of Table 23 or 24 can be used, while other

arrangements of the bytes are also possible.

Table 23. Complete sequence 1

Start Address

byte

Divider

byte 1

Divider

byte 2

Control

byte 1^[1]

Control

byte 2

Control

byte 1^[2]

Stop

S

C2

A

12

A

C0

A

CA

A

A4

A

84

A

P

[1] Control byte 1 with bit T/A = 1, to program test bits T2, T1 and T0 and reference divider ratio bits R2, R1

and R0.

[2] Control byte 1 with bit T/A = 0, to program AGC time constant bit ATC and AGC take-over point bits

AL2, AL1 and AL0.

Table 24. Complete sequence 2

Start Address

byte

Control

byte 1^[1]

Control

byte 2

Divider

byte 1

Divider

byte 2

Control

byte 1^[2]

Stop

S

C2

A

CA

A

A4

A

12

A

C0

A

84

A

P

[1] Control byte 1 with bit T/A = 1, to program test bits T2, T1 and T0 and reference divider ratio bits R2, R1

and R0.

[2] Control byte 1 with bit T/A = 0, to program AGC time constant bit ATC and AGC take-over point bits

AL2, AL1 and AL0.

Table 25. Sequence to program only the main divider ratio

Start

Address byte

C2

Divider byte 1

12

Divider byte 2

C0

Stop

S

A

P

Table 26. Sequence to change the charge pump current, the ports and the test mode. If the

reference divider ratio is changed, it is necessary to send the DB1 and DB2 bytes

Start

Address byte

C2

Control byte 1^[1]

Control byte 2

A4

Stop

S

A

CA

A

P

[1] Control byte 1 with bit T/A = 1, to program test bits T2, T1 and T0 and reference divider ratio bits R2, R1

and R0.

Table 27. Sequence to change the test mode. If the reference divider ratio is changed, it is

necessary to send the DB1 and DB2 bytes

Start

Address byte

Control byte 1^[1]

Stop

S

C2

A

CA

A

P

[1] Control byte 1 with bit T/A = 1, to program test bits T2, T1 and T0 and reference divider ratio bits R2, R1

and R0.

Table 28. Sequence to change the charge pump current, the ports and the AGC data

Start

Address byte

C2

Control byte 1^[1]

Control byte 2

A4

Stop

S

A

82

A

P

[1] Control byte 1 with bit T/A = 0, to program AGC time constant bit ATC and AGC take-over point bits

AL2, AL1 and AL0.

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

46 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

Table 29. Sequence to change only the AGC data

Start

Address byte

Control byte 1^[1]

Stop

S

C2

A

84

A

P

[1] Control byte 1 with bit T/A = 0, to program AGC time constant bit ATC and AGC take-over point bits

AL2, AL1 and AL0.

Table 30. Sequence to program the main divider, the ALBC on and the test modes in normal

mode with XTOUT buffer off

Start Address

byte

Divider

byte 1

Divider

byte 2

Control

byte 1^[1]

Control

byte 2

Control

byte 1

Stop

S

C2

A

12

A

C0

A

DA

A

00

A

C2

A

P

[1] Control byte 1 with bit T/A = 1, to program test bits T2, T1 and T0 and reference divider ratio bits R2, R1

and R0.

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

47 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

14. Package outline

TSSOP38: plastic thin shrink small outline package; 38 leads; body width 4.4 mm;

lead pitch 0.5 mm

SOT510-1

E

H

D

A

X

c

v

M

A

y

E

Z

20

38

A

(A )

3

2

A

1

pin 1 index

θ

L

p

L

1

19

detail X

w

M

b

e

p

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions).

A

(1)

(2)

(1)

Z

UNIT

A

b

c

D

E

e

H

L

p

v

w

y

θ

1

2

3

p

E

max.

8^o

0^o

0.15

0.05

0.95

0.85

0.27

0.17

0.20

0.09

9.8

9.6

4.5

4.3

0.7

0.5

0.49

0.21

mm

1.1

0.5

1

0.2

0.25

6.4

0.08

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

03-02-18

05-11-02

SOT510-1

MO-153

Fig 31. Package outline SOT510-1 (TSSOP38)

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

48 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

15. Handling information

Inputs and outputs are protected against electrostatic discharge in normal handling.

However, to be completely safe you must take normal precautions appropriate to handling

integrated circuits.

16. Soldering

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

16.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

16.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus PbSn soldering

16.3 Wave soldering

Key characteristics in wave soldering are:

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

49 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

16.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 32) than a PbSn process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 31 and 32

Table 31. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 32. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 32.

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

50 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 32. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

17. Abbreviations

Table 33. Abbreviations

Acronym

ADC

Description

Analog to Digital Converter

Automatic Gain Control

AGC

ALBC

DVB-T

I²C-bus

IF

Automatic Loop Bandwidth Control

Digital Video Broadcasting TV

Inter-Integrated Circuit bus

Intermediate Frequency

LO

Local Oscillator

LSB

Least Signiﬁcant Bit

MOPLL

MSB

Mixer Oscillator Phase-Locked Loop

Most Signiﬁcant Bit

OFDM

PAL

Orthogonal Frequency Division Multiplexing

Phase Alternation Line

PLL

Phase-Locked Loop

PMOS

QAM

VCO

Positive Channel Metal Oxide Semiconductor

Quadrature Amplitude Modulation

Voltage Controlled Oscillator

Video Cassette Recorder

VCR

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

51 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

18. Revision history

Table 34. Revision history

Document ID

Release date

20070110

Data sheet status

Change notice

Supersedes

TDA6650TT_6651TT_5

Modiﬁcations:

Product data sheet

-

TDA6650TT_6651TT_4

• The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors

• Legal texts have been adapted to the new company name where appropriate

• Table 3 “Ordering information” updated with type numbers TDA6650TT/C3/S2,

DA6651TT/C3/S2 and TDA6651TT/C3/S3

• Table 22 “Characteristics” condition of leakage current (I_LO) changed from

0 < V_AGC< V_CCinto 0 V < V_AGC< 3.5 V

• Table 22 “Characteristics” added value of the TDA6651TT/C3/S3 for INT_f(step)(rejection

at the IF output)

• Table 22 “Characteristics” added value of the TDA6651TT/C3/S3 for V_o(pin AGC)

• Table 22 “Characteristics” added value of the TDA6651TT/C3/S3 for V_o(dis)(pin AGC)

TDA6650TT_6651TT_4

(9397 750 14178)

20041208

Product data sheet

-

TDA6650TT_6651TT_3

Modiﬁcations:

• Section 3: Note added to the applications list

• Table 10 on page 11: Notes 1 and 2 added

• Section 10: Table notes modiﬁed

• Figure 18, 19, 23 and 24: Replaced “1 % AM modulation” with “0.3 % AM modulation”

• Figure 20: Modiﬁed by adding V’_meas

• Figure 24: Added ﬁgure note

• Figure : Changed value of C17 and R13

TDA6650TT_6651TT_3

(9397 750 13025)

20040322

20030911

20030717

Product speciﬁcation

-

TDA6650TT_6651TT_2

(9397 750 11854)

Preliminary speciﬁcation -

TDA6650TT_6651TT_1

-

TDA6650TT_6651TT_1

-

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

52 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

19. Legal information

19.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

result in personal injury, death or severe property or environmental damage.

19.2 Deﬁnitions

NXP Semiconductors accepts no liability for inclusion and/or use of NXP

Semiconductors products in such equipment or applications and therefore

such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

19.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

19.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of a NXP Semiconductors product can reasonably be expected to

I²C-bus — logo is a trademark of NXP B.V.

20. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

TDA6650TT_6651TT_5

Product data sheet

Rev. 05 — 10 January 2007

53 of 54

TDA6650TT; TDA6651TT

NXP Semiconductors

5 V mixer/oscillator and low noise PLL synthesizer

21. Contents

1

General description . . . . . . . . . . . . . . . . . . . . . . 1

19.3

19.4

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 53

2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Application summary . . . . . . . . . . . . . . . . . . . . 3

Ordering information. . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

20

21

Contact information . . . . . . . . . . . . . . . . . . . . 53

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3

3.1

4

5

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

7

Functional description . . . . . . . . . . . . . . . . . . . 6

Mixer, Oscillator and PLL (MOPLL) functions. . 6

I²C-bus voltage . . . . . . . . . . . . . . . . . . . . . . . . . 7

Phase noise, I²C-bus trafﬁc and crosstalk . . . . 7

7.1

7.2

7.3

8

8.1

I²C-bus protocol. . . . . . . . . . . . . . . . . . . . . . . . . 8

Write mode; R/W = 0 . . . . . . . . . . . . . . . . . . . . 8

I²C-bus address selection. . . . . . . . . . . . . . . . 10

XTOUT output buffer and mode setting . . . . . 10

Step frequency setting . . . . . . . . . . . . . . . . . . 10

AGC detector setting . . . . . . . . . . . . . . . . . . . 11

Charge pump current setting . . . . . . . . . . . . . 11

Automatic Loop Bandwidth Control (ALBC) . . 12

Read mode; R/W = 1 . . . . . . . . . . . . . . . . . . . 13

Status at power-on reset. . . . . . . . . . . . . . . . . 14

8.1.1

8.1.2

8.1.3

8.1.4

8.1.5

8.1.6

8.2

8.3

9

Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 15

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 19

Thermal characteristics. . . . . . . . . . . . . . . . . . 20

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 21

PLL loop stability of measurement circuit . . . . 39

10

11

12

12.1

13

Application information. . . . . . . . . . . . . . . . . . 45

Tuning ampliﬁer. . . . . . . . . . . . . . . . . . . . . . . . 45

Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . 45

Examples of I²C-bus program sequences . . . 45

13.1

13.2

13.3

14

15

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 48

Handling information. . . . . . . . . . . . . . . . . . . . 49

16

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Introduction to soldering . . . . . . . . . . . . . . . . . 49

Wave and reﬂow soldering . . . . . . . . . . . . . . . 49

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 49

Reﬂow soldering . . . . . . . . . . . . . . . . . . . . . . . 50

16.1

16.2

16.3

16.4

17

18

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 51

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 52

19

19.1

19.2

Legal information. . . . . . . . . . . . . . . . . . . . . . . 53

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 53

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 10 January 2007

Document identifier: TDA6650TT_6651TT_5


型号：	TDA6651TT/C3
厂家：	NXP
描述：	5 V mixer/oscillator and low noise PLL synthesizer for hybrid terrestrial tuner (digital and analog) 5 V混频器/振荡器和低噪声的PLL合成器，用于混合动力地面调谐器（数字和模拟）振荡器晶体时钟发生器微控制器和处理器外围集成电路光电二极管
文件：	总54页 (文件大小：335K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TDA6651TT/C3 [NXP]

相关型号：

TDA6651TT/C3/S2

TDA6651TT/C3/S3

TDA6800

TDA6800T

TDA6811

TDA6812-2M

TDA6812-5

TDA684K35CB

TDA685K06CB

TDA6900S

TDA6920

TDA6920X