TDA8035HN/C1_技术文档

TDA8035

High integrated and low power smart card interface

Rev. 3.1 — 30 June 2016

Product data sheet

1. General description

The TDA8035 is the cost efficient successor of the established integrated contact smart

card reader IC TDA8024. It offers a high level of security for the card by performing

current limitation, short-circuit detection, ESD protection as well as supply supervision.

The current consumption during the standby mode of the contact reader is very low as it

operates in the 3 V supply domain. The TDA8035 is therefore the ideal component for a

power efficient contact reader.

2. Features and benefits

2.1 Protection of the contact smart card

 Thermal and short-circuit protection on all card contacts

 V_CCregulation:

 5 V, 3 V, 1.8 V  5 % on 2 220 nF multilayer ceramic capacitors with low ESR

 Current spikes of 40 nA/s (V_CC= 5 V and 3 V) or 15 nA/s (V_CC= 1.8 V) up to

20 MHz, with controlled rise and fall times. Filtered overload detection is

approximately 120 mA.

 Automatic activation and deactivation sequences initiated by software or by hardware

in the event of a short-circuit, card take-off, overheating, falling V_REGV_DD(INTF),V_DDP

 Enhanced card-side ElectroStatic Discharge (ESD) protection of (> 8 kV)

 Supply supervisor for killing spikes during power on and off:

 threshold internally fixed

 externally by a resistor bridge

2.2 Easy integration into your contact reader

 SW compatible to TDA8024 and TDA8034

 5 V, 3 V, 1.8 V smart card supply

 DC-to-DC converter for V_CCgeneration separately powered from 2.7 V to 5.5 V supply

(V_DDPand GNDP)

 Very low power consumption in Deep Shutdown mode

 Three protected half-duplex bidirectional buffered I/O lines (C4, C7 and C8)

 External clock input up to 26 MHz

 Card clock generation up to 20 MHz using pins CLKDIV1 and CLKDIV2 with

synchronous frequency changes of f_XTAL, fXTAL/2, fXTAL/4 or fXTAL/8

 Non-inverted control of pin RST using pin RSTIN

 Built-in debouncing on card presence contact

 Multiplexed status signal using pin OFFN

TDA8035

NXP Semiconductors

High integrated and low power smart card interface

 Chip Select digital input for parallel operation of several TDA8035 ICs.

2.2.1 Other

 HVQFN32 package

 Compliant with ISO 7816, NDS and EMV 4.3 ^(*)payment systems

^(*)for C2 version

3. Applications

 Pay TV

 Electronic payment

 Identification

 IC card readers for banking

4. Quick reference data

Table 1.

Quick reference data

V_DDP= 3.3 V; V_DD(INTF)= 3.3 V; f_Xtal= 10 MHz; GND = 0 V; T_amb= 25 C; unless otherwise specified

Symbol

Supply

V_DDP

Parameter

Conditions

Min

Typ

Max

Unit

power supply voltage

interface supply voltage

power supply current

2.7

1.6

-

3.3

0.1

5.5

3.6

3

V

V_DD(INTF)

I_DDP

V

deep shutdown mode;

f_XTAL= stopped;

A

shutdown mode;

f_XTAL= stopped;

-

300

500

A

active mode; V_CC= +5 V

CLK = f_XTAL/2; no load

-

5

mA

A

active mode; CLK = f_XTAL/2;

V_CC= +5 V; I_CC= 65 mA

220

160

120

1

active mode; CLK = f_XTAL/2;

V_CC= +3 V; I_CC= 65 mA

active mode; CLK = f_XTAL/2;

V_CC= +1.8 V; I_CC= 35 mA

I_DD(INTF)

interface supply current

deep shutdown mode;

f_XTAL= stopped;

present card

shutdown mode;

-

1

A

f

_XTAL= stopped;

present card

Internal supply voltage

V_DD

supply voltage

1.62

1.8

1.98

V

TDA8035

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Product data sheet

Rev. 3 — June 30, 2016

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TDA8035

NXP Semiconductors

High integrated and low power smart card interface

Table 1.

Quick reference data …continued

V_DDP= 3.3 V; V_DD(INTF)= 3.3 V; f_Xtal= 10 MHz; GND = 0 V; T_amb= 25 C; unless otherwise specified

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Card supply voltage: pin VCC

V_CC

supply voltage

5 V card; DC ICC < 65 mA

4.75

4.65

5.0

5.25

V

5 V card; AC current spikes

of 40 nA/s

3 V card; DC I_CC< 65 mA

2.85

2.76

-

3.15

3.24

V

3 V card; AC current spikes

of 40 nA/s

1.8 V card; DC I_CC< 35 mA

1.71

1.66

-

1.89

1.94

V

1.8 V card; AC current

spikes of 15 nA/s

V_ripple(p-p)

I_CC

peak-to-peak ripple voltage

supply current

from 20 kHz to 200 MHz

V_{CC = 5 V or 3 V}

-

300

65

mV

mA

V_{CC = 1.8 V}

35

General

t_deact

deactivation time

total sequence

35

-

90

-

250

0.45

+85

s

W

P_tot

total power dissipation

ambient temperature

T_amb

25

-

C

5. Ordering information

The TDA8035 is available in 2 versions, which have the same functionalities. The C2

version is compliant with the EMVC0 4.3 standard.

Table 2.

Ordering information

Type number

Package

Name

Description

Version

TDA8035HN/C1

HVQFN32

plastic thermal enhanced very thin quad flat package; no leads;

SOT617-7

32 terminals; body 5  5  0.85 mm

TDA8035HN/C1/S1 HVQFN32

TDA8035HN/C2/S1 HVQFN32

plastic thermal enhanced very thin quad flat package; no leads;

SOT617-7

32 terminals; body 5  5  0.85 mm; ^[1]

plastic thermal enhanced very thin quad flat package; no leads;

32 terminals; body 5  5  0.85 mm; ^[1]

[1] copper wiring

TDA8035

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Product data sheet

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TDA8035

NXP Semiconductors

High integrated and low power smart card interface

6. Block diagram

V

DDP

DD(INTF)

330 nF

100 nF

10 μF

100 nF

V

DD(INTF)

V

REG

V

DDP

PORADJ

GND

GNDP

SAP SAM SBP SBM

CS

VUP

1 μF

INTERNAL

deep

shutdown

CMDVCCN

EN_5V/3VN

EN_1.8VN

RSTIN

DCDC

REGULATOR

DEEP

CONVERTER

SHUTDOWN

V

CC

LATCH

CLKDIV1

CLKDIV2

ISO7816

READER

INTERFACE

reset and

supalarm

2 ×

INPUT SENSE

GNDC

220 nF

SUPERVISOR

HOST

INTERFACE

DEEP SHUTDOWN

RST

CLK

AUX1

AUX2

I/O

I/OUC

AUX1UC

AUX2UC

BANDGAP

C5

C1

C2

C3

C4

H

Z

UC

TDA8035

C6

C7

C8

INTERNAL

OSCILLATOR

V

DD(INTF)

THERMAL

configurations

bus for smartcard

reader interface

PROTECTION

XTAL1

OFFN

H

Z

CRYSTAL

OSCILLATOR

DIGITAL

SEQUENCER

XTAL2

interuption

PRESN

001aan745

Fig 1. Block diagram

TDA8035

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Product data sheet

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TDA8035

NXP Semiconductors

High integrated and low power smart card interface

7. Pinning information

7.1 Pinning

terminal 1

index area

I/OUC

PORADJ

1

2

3

4

5

6

7

8

24 CLK

23 RST

CMDVCCN

22 V

CC

V

21 VUP

20 SAP

19 SBP

DD(INTF)

TDA8035

CLKDIV1

CLKDIV2

EN_5V/3VN

EN_1.8VN

18

V

DDP

17 SBM

001aan746

Transparent top view

Fig 2. Pin configuration HVQFN32

7.2 Pin description

Table 3.

Symbol

I/OUC

Pin description

1

Supply

Type

I/O

I

Description

host data I/O line (internal 10 k pull-up resistor to V_DD(INTF)

V_DD(INTF)

)

PORADJ

2

Input for V_DD(INTF)supervisor. PORADJ threshold can be changed with an

external R bridge

CMDVCCN

V_DD(INTF)

3

4

5

6

7

V_DD(INTF)

I

start activation sequence input from the host (active LOW)

supply interface supply voltage

CLKDIV1

CLKDIV2

EN_5V/3VN

I

control with CLKDIV2 for choosing CLK frequency (see Table 4)

control with CLKDIV1 for choosing CLK frequency (see Table 4)

control signal for selecting V_CC= 5 V (HIGH) or V_CC= 3 V (LOW) if

EN_1.8 VN = High

EN_1.8 VN

RSTIN

8

V_DD(INTF)

I

control signal for selecting V_CC= 1.8 V (low)

card reset input from the host (active HIGH)

9

I

OFFN

10

O

NMOS interrupt to the host (active LOW) with 10 k internal pull-up resistor to

V_DD(INTF)(See fault detection)

GND

11

12

13

14

15

-

supply ground

XTAL1

XTAL2

V_REG

V_DD(INTF)

V_DDP

I

crystal connection 1

crystal connection 2

O

supply Internal supply voltage

I/O DC-to-DC converter capacitor; connected between SAM and SAP; C = 330 nF

or 100 nF (see Figure 13) with ESR < 100 m at Freq=100kHz

SAM

V_DDP

GNDP

16

-

supply DC-to-DC converter power supply ground

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TDA8035

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High integrated and low power smart card interface

Table 3.

Symbol

SBM

Pin description …continued

Supply

Type

Description

17

V_DDP

I/O

DC-to-DC converter capacitor; connected between SBM and SBP; C = 330 nF

or 100nF (see Figure 13) with ESR < 100 m at Freq=100kHz

V_DDP

SBP

18

19

V_DDP

supply Power supply voltage

I/O

O

DC-to-DC converter capacitor; connected between SBM and SBP; C = 330 nF

or 100nF (see Figure 13) with ESR < 100 m at Freq=100kHz

SAP

VUP

V_CC

20

21

22

V_DDP

V_CC

DC-to-DC converter capacitor; connected between SAM and SAP; C = 330 nF

or 100nF (see Figure 13) with ESR < 100 m at Freq=100kHz

DC-to-DC converter output decoupling capacitor connected between VUP and

GNDP; C = 1 F with ESR < 100 m at Freq=100kHz

supply for the card (C1), decouple to GND with 2  220 nF capacitors with

ESR < 100 m

RST

23

24

25

26

V_CC

-

O

card reset (C2)

CLK

clock to the card (C3)

GNDC

AUX1

supply card signal ground

V_CC

I/O

auxiliary data line to and from the card (C4), internal 10 k pull-up resistor to

V_CC

AUX2

27

V_CC

I/O

auxiliary data line to and from the card (C8), internal 10 k pull-up resistor to

V_CC

I/O

28

29

30

V_CC

I/O

data line to and from the card (C7), internal 10 k pull-up resistor to V_CC

CS

V_DD(INTF)

I

Chip Select input from the host (active High)

PRESN

Card presence contact input (active LOW); if PRESN is true, then the card is

considered as present. A debouncing feature of 4.05 ms typical is built in.

AUX1UC

AUX2UC

31

32

V_DD(INTF)

I/O

auxiliary data line to and from the host, internal 10 k pull-up resistor to

V_DD(INTF)

auxiliary data line to and from the host, internal 10 k pull-up resistor to

V_DD(INTF)

TDA8035

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Product data sheet

Rev. 3 — June 30, 2016

6 of 32

TDA8035

NXP Semiconductors

High integrated and low power smart card interface

8. Functional description

Remark: The ISO 7816 terminology convention has been adhered to throughout this

document, and it is assumed that the reader is familiar with this convention.

8.1 Power supply

Power supply voltage V_DDPis from 2.7 V to 5.5 V

All interface signals with the system controller are referenced to V_DD(INTF). All card

contacts remain inactive during powering up or powering down.

Internal regulator V_REGis 1.8 V

After powering the device, OFFN remains low until CMDVCCN is set high and PRESN is

low.

During power off, OFFN falls low when V_DDPis below the threshold voltage falling.

While the card is not activated, CMDVCCN is kept at high level. To save power

consumption, the frequency of the internal oscillator (f_osc(int)) used for the activation

sequences is put in low frequency mode.

This device includes a DC-to-DC converter to generate the 5 V, 3 V or 1.8 V card supply

voltage (V_CC). The DC-to-DC converter is separately supplied by V_DDPand G_NDP. The

DC-to-DC converter operates as a voltage tripler, doubler or follower according to the

respective values of V_CCand V_DDP

.

Special care has to me made in the selection of the capacitors of the DC/DC converter

specially with respect to capacitor value versus voltage and ESR (see Table 7)

The operating mode is as follows (see Figure 3):

• V_CC= 5 V and V_DDP> 3.8 V; voltage doubler

• V_CC= 5 V and V_DDP< 3.6 V; voltage tripler

• V_CC= 3 V and V_DDP> 3.8 V; voltage follower

• V_CC= 3 V and V_DDP< 3.6 V; voltage doubler

• V_CC= 1.8 V and V_DDP> 3.8 V; voltage doubler

• V_CC= 1.8 V and V_DDP< 3.6 V; voltage tripler

TDA8035

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Product data sheet

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TDA8035

NXP Semiconductors

High integrated and low power smart card interface

8.2 Voltage supervisor

V

REG

vbg

V

REG

V

DDP

Deep_shutdown

V

DD(INTF)

vbg

Poradj

001aan747

Fig 3. Block voltage supervisor

The voltage supervisor is used as a power-on reset, and also as supply drop detection

during a card session. The threshold of the voltage supervisor is set internally in the IC for

VDDP and VREG. The threshold can be adjusted externally for VDD(INTF) using the

PORADJ pin. As long as VREG is less than V_th(VREG)+ V_hys(VREG), the IC remains inactive

whatever the levels on the command lines are. The inactivity lasts for the duration of t_w

after VREG has reached a level higher than V_th(VREG)+ V_hys(VREG). The outputs of the

VDDP, VREG and VDD(INTF) supervisors are combined and sent to a digital controller in

order to reset the TDA8035. The reset pulse of approximately 5.7 ms (t_w= 2048 

1/(f_{osc(int)_Low}) is used internally for maintaining the IC in an inactive mode during the

supply voltage power-on (see Figure 4 and Figure 5). A deactivation sequence is

performed when:

• VREG falls below V_th(VREG)

• V_DD(INTF)falls below V_th(PORADJ)

• VDDP falls below V_th(VDDP)

TDA8035

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Product data sheet

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TDA8035

NXP Semiconductors

High integrated and low power smart card interface

V

DDP

Vth_vddp_Ih

V

REG

Vt

Supervisor outputs

vsup

X

Tw

reset

X

2 Tw

supalarm

Supervisor inputs

Deep_shutdown

X

Oscint

180 kHz

1.2 V

Vbg

IC pins

OFFN

X

debouncing

001aan748

Fig 4. Voltage supervisor

V

DDP

Vth_Vddp_Ih

2.65 V

2.5 V

Vth_vddp_hI

V

REG

1

1.8 V

1

Vsup

2

3

Supalarm

Reset

Tw

3

100 μs analog delay

Start debouncing if a card

has been inserted during

shutdown mode

001aan749

Fig 5. Voltage supervisor

TDA8035

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Product data sheet

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9 of 32

TDA8035

NXP Semiconductors

High integrated and low power smart card interface

8.3 Clock circuitry

DIGITAL

Enclkin

clkxtal

MUX

XTAL

001aan750

Fig 6. Switch external clock

To generate the card clock CLK, the TDA8035 can either use an external clock provided

on XTAL1 pin or a crystal oscillator connected on both XTAL1 and XTAL2 pins. The

TDA8035 automatically detects when an external clock is provided on XTAL1.

Consequently, there is no need for an extra pin to configure the clock source (external

clock or crystal).

The automatic clock source detection is performed on each activation command

(CMDVCCN pin falling edge). During a time window defined by the internal oscillator, the

presence of an external clock on XTAL1 pin is checked. If a clock is detected, the crystal

oscillator is kept stopped, else, the crystal oscillator is started. It is mandatory when an

external clock is used, that the clock is applied on XTAL1 before CMDVCCN falling edge

signal.

The frequency is chosen as f_XTAL, f_XTAL/2, f_XTAL/4or f_XTAL/8via the pins CLKDIV1 and

CLKDIV2. Both selection inputs are not changed simultaneously. A minimum of 10 ns is

required between changes on CLKDIV1 and CLKDIV2.

The frequency change is synchronous, which means that during transition, no pulse is

shorter than 45 % of the smallest period. This ensures that the first and last clock pulse

around the change has the correct width. When changing the frequency dynamically, the

change is effective for only 10 periods of XTAL1 after the command.

The duty cycle on pin CLK is between 45 % and 55 %:

• When an external clock is used on XTAL1 pin and f_XTALis used, the duty cycle is

between 48 % and 52 %. The subsequent rise and fall times (t_r(i)and t_f(i)) conform to

values listed in Table 7. It has to connect a 56 pF serial capacitor (see Figure 13).

• CLK frequency is f_XTAL, f_XTAL/2,f_XTAL/4or f_XTAL/8

:

It is guaranteed between 45 % and 55 % of the period by the frequency dividers.

Table 4.

Clock configuration

CLKDIV1

CLKDIV2

CLK

0

1

0

1

0

f_XTAL/8

f_XTAL/4

f_XTAL/2

f_XTAL

TDA8035

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Product data sheet

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TDA8035

NXP Semiconductors

High integrated and low power smart card interface

8.4 I/O circuitry

The three data lines I/O, AUX1 and AUX2 are identical.

To enter the idle state, both lines (I/O and I/OUC) are pulled HIGH via a 10 k resistor (I/O

to V_CCand I/OUC to V_DD(INTF)).

I/O is referenced to V_CC, and I/OUC to V_DD(INTF)which allows operation with

V_CC V_DD(INTF)

.

The first side on which a falling edge occurs becomes the master. An anti-latch circuit

disables the detection of falling edges on the other line, which becomes the slave.

After a time delay t_d(edge), the logic 0 present on the master side is transmitted to the slave

side.

When the master side returns to logic 1, the slave side transmits the logic 1 during the

time delay t_puand both sides return to their idle states.

The active pull-up feature ensures fast Low to High transitions. It is able to deliver more

than 1 mA to an output voltage of 0.9 V_CCon an 80 pF load. At the end of the active

pull-up pulse, the output voltage depends on the internal pull-up resistor and on the load

current.

The current to and from the cards I/O lines is internally limited to 15 mA.

The maximum frequency on these lines is 1.5 MHz.

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Product data sheet

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TDA8035

NXP Semiconductors

High integrated and low power smart card interface

8.5 CS control

The CS (Chip Select) input allows multiple devices to operate in parallel. When CS is

high, the system interface signals operate as described. When CS is low, the signals

CMDVCCN, RSTIN, CLKDIV1, CLKDIV2, EN_5V/3VN and EN_1.8VN are latched.

I/OUC, AUX1UC and AUX2UC are set to high impedance pull-up mode and data is no

longer passed to or from the smart card. The OFFN output is a 3-state output.

8.6 Shutdown mode and Deep Shutdown mode

After power-on reset, the circuit enters the Shutdown mode if CMDVCCN input pin is set

to a logic high. A minimum number of circuits are active while waiting for the

microcontroller to start a session.

1. All card contacts are inactive (approximately 200  to GND).

2. I/OUC, AUX1UC and AUX2UC are high impedance (10 kW pull-up resistor connected

to V_DD(INTF)).

3. Voltage generators are stopped.

4. Voltage supervisor is active.

5. The internal oscillator runs at its low frequency.

A Deep Shutdown mode can be entered by forcing CMDVCCN input pin to a logic-High

state and EN_5V/3VN, EN_1.8VN input pins to a logic-Low state. Deep Shutdown mode

can only be entered when the smart card reader is inactive. In Deep Shutdown mode, all

circuits are disabled. The OFFN pin follows the status of PRESN pin. To exit Deep

Shutdown mode, change the state of one or more of the three control pins. Figure 8

shows the control sequence for entering and exiting.

DEACTIVATION

SEQUENCE

CMDVCCN

EN_1.8VN

EN_5V/3VN

Shutdown

debounce

Mode

(internal pin)

Activation

Deep Shutdown

Activation

OFFN

PRESN

V

CC

001aan751

Fig 7. Shutdown mode and Deep Shutdown mode

TDA8035

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Product data sheet

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TDA8035

NXP Semiconductors

High integrated and low power smart card interface

8.7 Activation sequence

The following sequence then occurs with crystal oscillator (see Figure 8):

T = 64  T_oscint(freq high)

1. CMDVCCN is pulled low (t0)

2. Crystal oscillator start-up time (t0).

3. The internal oscillator changes to its high frequency and DC-to-DC starts

t1 = t0 + 768  T_{osc (freq low)}

4. V_CCrises from 0 to selected V_CCvalue (5 V, 3 V, 1.8 V) with a controlled slope

(t₂= t₁+ 3T/2)

5. I/O, AUX1 and AUX2 are enabled (t₃= t₁+ 10T), until now, they were pulled LOW

6. CLK is applied to the C3 contact (t₄= t₃+ ×) with 200 ns < × < 10 × 1/f_Xtal

7. RST is enabled (t₅= t₁+ 13T).

Oscint

CMDVCCN

Xtal1

low frequency

high frequency

VUP

V

CC

I/O

CLK

RST

T / 2

≈ 3 ms

t0

t1

t2

t3 t4

t5

001aan752

Fig 8. Activation sequence at t3

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Product data sheet

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13 of 32

TDA8035

NXP Semiconductors

High integrated and low power smart card interface

8.8 Deactivation sequence

When a session is completed, the microcontroller sets the CMDVCCN line to the HIGH

state. The circuit then executes an automatic deactivation sequence by counting the

sequencer back and ends in the inactive state (see Figure 9):

1. RST goes LOW (t₁₁= t₁₀+ 3T/64)

2. CLK is stopped LOW (t₁₂= t₁₁+T/2)

3. I/O, AUX1 and AUX2 are pulled LOW (t₁₃= t₁₁+ T)

4. V_CCfalls to zero (t₁₄= t₁₁+ 3T/2). The deactivation sequence is completed when V_CC

reaches its inactive state

5. VUP falls to zero (t₁₅= t₁₁+ 7T/2)

6. V_CC< 0.4 V (t_de= t₁₁+ 3T/2 + V_CCfall time)

7. All card contacts become low-impedance to GND. I/OUC, AUX1UC and AUX2UC

remain pulled up to V_DD(INTF)via a 10 k resistor.

8. The internal oscillator reverts to its lower frequency.

CMDVCCN

RST

CLK

I/O

V

CC

VUP

Xtal1

Oscint

high frequency

low frequency

T / 2

t10

t11

t12 t13 t14

t15

001aan753

Fig 9. Deactivation sequence

8.9 V_CCregulator

V_CCbuffer is able to deliver up to 65 mA continuously at V_CC= 5 V and V_CC= 3 V, and

35 mA at V_CC= 1.8 V.

V_CCbuffer has an internal overload detection at approximately 125 mA.

This detection is internally filtered, allowing the card to draw spurious current pulses of up

to 200 mA for some milliseconds, without causing a deactivation. The average current

value must remain below the maximum.

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Product data sheet

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14 of 32

TDA8035

NXP Semiconductors

High integrated and low power smart card interface

8.10 Fault detection

The circuit monitors the following fault conditions:

• short-circuit or high current on V_CC

• Card removal during transaction

• V_DDPor V_DD(INTF)or V_regdropping

• overheating.

There are two different cases (see Figure 10 on page 16):

1. CMDVCCN High (outside a card session): OFFN is Low when the card is not in the

reader, and High when the card is in the reader. The supply supervisor detects a

supply voltage drop on V_DDPand generates an internal power-on reset pulse, but it

does not act upon OFFN. The card is not powered-up, so no short-circuit or

overheating is detected.

2. CMDVCCN Low (within a card session): OFFN falls Low in any of the previously

mentioned cases. As soon as the fault is detected, an emergency deactivation is

automatically performed. When the system controller sets CMDVCCN back to High, it

senses OFFN again. After a complete deactivation sequence, the system controller

sets CMDVCCN back to High and it senses OFFN again. This is to distinguish

between a hardware problem or a card extraction. OFFN reverts to High when the

card is still present.

A bounce can occur on the PRESN signal during card insertion or withdrawal. The bounce

depends on the type of card presence switch within the connector (normally closed or

normally open), and on the mechanical characteristics of the switch. To prevent this

bounce, a debounce function of approximately 4.05 ms (tdeb = 1280  1/(f_{osc(int)_Low}) is

integrated in the device.

When the card is inserted, OFFN goes High only at the end of the debounce time (see

Figure 11 on page 16).

When the card is extracted, an automatic deactivation sequence of the card is performed

on the first true/false transition on PRESN. OFFN goes Low.

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TDA8035

NXP Semiconductors

High integrated and low power smart card interface

OFFN

PRESN

RST

CLK

I/O

V

CC

VUP

Xtal1

Oscint

high frequency

low frequency

T / 2

t10 = t11 t12 t13 t14

t15

001aan754

Fig 10. Emergency deactivation sequence (card extraction)

PRESN

OFFN

CMDVCCN

tdeb

V

CC

Deactivation caused by

cards withdrawal

Deactivation caused by

short circuit

001aan757

Fig 11. Behavior of OFFN, CMDVCCN, PRESN and V_CC

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TDA8035

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High integrated and low power smart card interface

9. Limiting values

All card contacts are protected against a short-circuit with any other card contact.

Stress beyond the limiting values can damage the device permanently. The values are

stress ratings only and functional operation of the device under these conditions is not

implied.

Table 5.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

0.3

Max

6

Unit

V

V_DDP

power supply voltage

V_DD(INTF)interface supply voltage

4.1

V

V_IH

HIGH-level input

voltage

CS, PRESN,

V

CMDVCCN, CLKDIV2,

CLKDIV1, EN_1.8VN,

EN_5V/3VN, RSTIN,

OFFN, PORADJ, XTAL1,

I/OUC, AUX1UC, AUX2UC,

VDDP, VDD(INTF)

I/O, RST, AUX1, AUX2 and

CLK

0.3

5.75

V

T_amb

T_stg

T_j

ambient temperature

storage temperature

junction temperature

total power dissipation

25

55

+85

C

W

+150

+125

0.45

+10

P_tot

V_ESD

electrostatic discharge Human Body Model (HBM)

voltage on card pins I/O, RST, V_CC

10

kV

,

AUX1, CLK, AUX2, PRESN

within typical application

Human Body Model (HBM)

on all other pins

2

+2

kV

V

Machine Model (MM) on all

pins

200

500

+200

+500

Field Charged Device

V

Model (FCDM) on all pins

10. Thermal characteristics

Table 6.

Symbol

R_th(j-a)

Thermal characteristics

Package name Parameter

Conditions

Typ

Unit

HVQFN32

thermal resistance from junction in free air with 4 thermal vias

55

K/W

to ambient

on PCB

in free air without thermal

vias on PCB

63

K/W

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High integrated and low power smart card interface

11. Characteristics

Table 7.

Characteristics of IC

V_DDP= 3.3 V; V_DD(INTF)= 3.3 V; f_XTAL= 10 MHz; GND = 0 V; T_amb=25 C; unless otherwise specified

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Supply voltage

V_DDP

power supply voltage

interface supply voltage

power supply current

2.7

1.6

-

3.3

0.1

5.5

3.6

3

V

V_DD(INTF)

I_DDP

V

deep Shutdown mode;

f_XTAL= stopped

A

Shutdown mode;

-

300

500

A

f

_XTAL= stopped

active mode; CLK = f_XTAL/2;

_CC= +5 V; no load

-

5

mA

A

V

active mode; CLK = f_XTAL/2;

V_CC= +5 V; I_CC= 65 mA

220

160

120

1

active mode; CLK = f_XTAL/2;

V_CC= +3 V; I_CC= 65 mA

active mode; CLK = f_XTAL/2;

V_CC= +1.8 V; I_CC= 35 mA

I_DD(INTF)

interface supply current

deep Shutdown mode

f_XTAL= stopped;

present card

Shutdown mode

-

1

A

f_XTAL= stopped;

present card

V_th(VREG)

V_hys(VREG)

V_th(VDDP)

V_hys(VDDP)

threshold voltage on pin

V_REG

internal voltage regulator

falling

1.38

90

1.45

100

2.25

100

1.52

110

V

hysteresis voltage on pin

V_REG

mV

V

threshold voltage on pin

V_DDP

pin VDDP falling

2.15

90

2.35

110

hysteresis voltage on pin

V_DDP

mV

t_w

pulse width

3.0

6.5

8.9

ms

V

V_{th(L)(PORADJ)}

LOW-level threshold

external resistors on PORADJ 0.81

0.85

0.89

voltage on pin PORADJ

V_hys(PORADJ)

hysteresis voltage on pin

PORADJ

30

60

-

90

+1

mV

I_L

leakage current

pin PORADJ

-1

A

VREG

V_o

t_r

output voltage

rise time

1.62

-

1.80

-

1.98

200

V

exit of deep Shutdown mode

s

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Table 7.

Characteristics of IC …continued

V_DDP= 3.3 V; V_DD(INTF)= 3.3 V; f_XTAL= 10 MHz; GND = 0 V; T_amb=25 C; unless otherwise specified

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VUP (DC-to-DC converter)

V_OH

HIGH-level output voltage VDDP=3.3V, VCC = 5 V,

ICC < 65 mA DC

5.10

3.50

5.10

-

5.60

3.95

5.60

5.80

5.00

5.80

7.00

5.00

7.00

-

V

VDDP=3.3V, VCC = 3 V,

ICC < 65 mA DC

VDDP=3.3V, VCC = 1.8 V,

ICC < 35 mA DC

VDDP=5V, VCC = 5 V,

ICC < 65 mA DC

VDDP=5V, VCC = 3 V,

ICC < 65 mA DC

VDDP=5V, VCC = 1.8 V,

ICC < 35 mA DC

5.10

7.00

SAP (DC-to-DC converter)

V_OH

HIGH-level output voltage VDDP=3.3V, VCC = 5 V,

-

8.20

6.00

8.20

-

V

ICC < 65 mA DC

VDDP=3.3V, VCC = 3 V,

ICC < 65 mA DC

-

VDDP=3.3V, VCC = 1.8 V,

ICC < 35 mA DC

-

VDDP=5V, VCC = 5 V,

ICC < 65 mA DC

-

VDDP=5V, VCC = 3 V,

ICC < 65 mA DC

5.00

-

VDDP=5V, VCC = 1.8 V,

ICC < 35 mA DC

8.20

DC-to-DC converter capacitors

C_SAPSAM

C_SBPSBM

C_VUP

DC/DC converter

capacitance

connected between SAP and

SAM (330 nF ^[4]) with

VDDP=3.3v

231

70

-

429

130

429

130

1300

nF

connected between SAP and

SAM (100 nF ^[4]) with

VDDP=5v

DC/DC converter

capacitance

connected between SBP and

SBM (330 nF ^[4]) with

VDDP=3.3v

231

70

connected between SBP and

SBM (100 nF ^[4]) with

VDDP=5v

DC/DC converter

capacitance

connected on VUP(1uF ^[4]

)

700

[1]

Card supply voltage (V_CC

)

C_dec

decoupling capacitance

connected on V_CC(220 nF +

220 nF 10 %)

396

-

484

nF

V_o

output voltage

inactive mode; no load

-0.1

-

+0.1

+0.3

V

inactive mode; Io = 1 mA

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Table 7.

Characteristics of IC …continued

V_DDP= 3.3 V; V_DD(INTF)= 3.3 V; f_XTAL= 10 MHz; GND = 0 V; T_amb=25 C; unless otherwise specified

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

I_o

output current

inactive mode

-

1

mA

at grounded pin VCC

V_CC

supply voltage

active mode; 5 V card;

ICC < 65 mA DC

4.75

2.85

1.71

5.0

5.25

3.15

1.89

5.25

V

active mode; 3 V card;

ICC < 65 mA DC

3.05

1.83

5.0

active mode; 1.8 V card;

ICC < 35 mA DC

active mode; current pulses of 4.65

40 nA/s with ICC < 200 mA,

t < 400 ns; 5 V card

active mode; current pulses of 2.76

40 nA/s with ICC < 200 mA,

t < 400 ns; 3 V card

-

3.20

1.94

350

V

active mode; current pulses of 1.66

15 nA/s with ICC < 200 mA,

t < 400 ns; 1.8 V card

V

V_ripple(p-p)

I_CC

peak-to-peak ripple

voltage

from 20 kHz to 200 MHz

-

mV

supply current

VCC = 0 V to 5 V, 3 V

VCC = 0 V to 1.8 V

5 V card

-

65

mA

-

35

mA

SR

slew rate

0.055

0.040

0.025

0.18

0.8

V/s

3 V card

1.8 V card

Crystal oscillator (XTAL1 and XTAL2)

C_ext

external capacitance

connected on pins

-

33

pF

XTAL1/XTAL2 (depending on

specification of crystal or

resonator used)

f_xtal

crystal frequency

2

0

-

27

MHz

f_xtal(XTAL1)

crystal frequency on pin

XTAL1

with 56 pF serial capacitor

V_IL

V_IH

t_r(i)

LOW-level input voltage

HIGH-level input voltage

input rise time

-0.3

-

+0.3 V_DD(INTF)

V_DD(INTF)+ 0.3

4

V

0.7 V_DD(INTF)

-

V

f_CLK= f_XTAL1= 20 MHz on

external clock

ns

f_CLK= f_XTAL1= 10 MHz on

external clock

-

8

ns

f_CLK= f_XTAL1= 5 MHz on

16

external clock

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Table 7.

Characteristics of IC …continued

V_DDP= 3.3 V; V_DD(INTF)= 3.3 V; f_XTAL= 10 MHz; GND = 0 V; T_amb=25 C; unless otherwise specified

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_f(i)

input fall time

f_CLK= f_XTAL1= 20 MHz on

external clock

-

4

ns

f_CLK= f_XTAL1= 10 MHz on

external clock

-

8

ns

f_CLK= f_XTAL1= 5 MHz on

external clock

16

Data lines (pins I/O, I/OUC, AUX1, AUX2, AUXIUC, AUX2UC)

t_d

delay time

falling edge on pins I/O and

I/OUC or I/OUC and I/O

-

200

ns

t_w(pu)

f_max

C_i

pull-up pulse width

maximum frequency

input capacitance

200

400

1

ns

on data lines

-

MHz

pF

10

Data lines to the card (pins I/O, AUX1, AUX2); (Integrated 10 k pull-up resistor connected to V_CC

)

V_o

I_o

output voltage

inactive mode; no load

inactive mode; Io= 1 mA

inactive mode

0

-

0.1

0.3

1

V

output current

mA

at grounded pin I/O

V_OL

LOW-level output voltage I_OL= 1 mA - C1 version

I_OL= 1 mA - C2 version

I_OL 15 mA

0

-

0.3

V

0

0.15 V_CC

V_CC

V_CC- 0.4

0.9 V_CC

0

V_OH

HIGH-level output voltage No DC load

I_OH -15 mA

V_CC+ 0.1

0.4

C1 version

I_OH< -40 A 5 V or 3 V

I_OH< -20 A 1.8 V

0.75 V_CC

V_CC+ 0.1

V

C2 version

I_OH< -40 A 5 V or 3 V

I_OH< -20 A 1.8 V

0.8 V_CC

1.28

V_CC+ 0.1

+0.8

V

V_IL

V_IH

LOW-level input voltage

C1 version

C2 version

0.3

-

-0.3

0.2 V_CC

HIGH-level input voltage C1 Version

VCC = +5 V

0.6 V_CC

0.7 V_CC

-

V_CC+ 0.3

V

VCC = +3 V or 1.8 V

C2 Version

VCC = +5 V or 3V

VCC =1.8 V

on I/O

0.6 V_CC

-

V_CC+ 0.3

120

V

1.4

30

-

V

V_hys

I_IL

hysteresis voltage

75

-

mV

A

LOW-level input current

on I/O; VIL = 0

on I/O; V_IH= V_CC

600

I_LH

HIGH-level leakage

current

-

10

t_r(i)

input rise time

from V_ILmax to V_IHmin

-

1.2

s

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Table 7.

Characteristics of IC …continued

V_DDP= 3.3 V; V_DD(INTF)= 3.3 V; f_XTAL= 10 MHz; GND = 0 V; T_amb=25 C; unless otherwise specified

Symbol

t_f(i)

Parameter

Conditions

Min

Typ

Max

1.2

Unit

s

input fall time

output rise time

from V_ILmax to V_IHmin

-

t_r(o)

C_L< = 80 pF; 10 % to 90 %

from 0 to V_CC

0.1

s

t_f(o)

output fall time

C_L< = 80 pF; 10 % to 90 %

from 0 to V_CC

-

0.1

s

R_pu

I_pu

pull-up resistance

pull-up current

connected to VCC

8

10

-6

12

-4

k

V_OH= 0.9 V_CC, C = 80 pF

-8

mA

Data lines to the system; pins I/OC, AUX1C, AUX2C (Integrated k pull-up resistor to V_DD(INTF)

)

V_OL

V_OH

LOW-level output voltage I_OL= 1 mA

HIGH-level output voltage No DC load

0

-

0.3

V

0.9 V_DD(INTF)

0.75 V_DD(INTF)

0.3

V_DD(INTF)+ 0.1 V

I_OH 40 A; V_DD(INTF)>2 V

V_DD(INTF)+ 0.1

0.3 V_DD(INTF)

V

I_OH 20 A; V_DD(INTF)<2 V

V_IL

LOW-level input voltage

HIGH-level input voltage

hysteresis voltage

V_IH

V_hys

I_LH

0.7 V_DD(INTF)

0.05 V_DD(INTF)

V_DD(INTF)+ 0.3 V

on I/Ouc

-

0.25 V_DD(INTF)

10

V

HIGH-level leakage

current

V_IH= V_DD(INTF)

A

I_IL

LOW-level input current

pull-up resistance

input rise time

V_IL= 0

600

12

A

k

s

R_pu

t_r(i)

t_f(i)

t_r(o)

connected to VDD(INTF)

from V_ILmax to V_IHmin

8

-

10

-

1.2

0.1

input fall time

-

output rise time

C_L 30 pF; 10 % to 90 %

-

from 0 to V_DD(INTF)

t_f(o)

output fall time

pull-up current

C_L 30 pF; 10 % to 90 %

from 0 to V_DD(INTF)

-

0.1

-

s

I_pu

Internal oscillator

f_osc(int)internal oscillator

frequency

Reset output to the card (RST)

V_OH= 0.9 V_DD, C = 30 pF

-1

mA

inactive state: osc(int)_Low

active state: osc(int)_High

230

2.0

315

2.5

430

3.0

kHz

MHz

V_o

output voltage

output current

delay time

inactive mode; no load

inactive mode; Io= 1 mA

inactive mode

0

-

0.1

0.3

1

V

I_o

mA

at grounded pin RST

between RSTIN and RST,

RST enabled

t_d

-

200

ns

V_OL

LOW-level output voltage I_OL= 200 A, VCC = +5 V

0

-

0.3

0.2

V

I_OL= 200 A, VCC = +3 V or

1.8 V

I_OL= 20 mA (current limit)

V_CC- 0.4

-

V_CC

V

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Table 7.

Characteristics of IC …continued

V_DDP= 3.3 V; V_DD(INTF)= 3.3 V; f_XTAL= 10 MHz; GND = 0 V; T_amb=25 C; unless otherwise specified

Symbol

Parameter

HIGH-level output voltage I_OH= -200 A

I_OH= -20 mA (current limit)

C_L= 100 pF

Conditions

Min

Typ

Max

V_CC

0.4

Unit

V

V_OH

0.9 V_CC

-

0

-

V

t_r

rise time

0.1

s

V_CC= +5 V and +3 V

C_L= 100 pF

-

0.2

0.1

0.2

s

V_CC= +18 V

t_f

fall time

C_L= 100 pF

V_CC= +5 V and +3 V

C_L= 100 pF

V_CC= +18 V

Clock output to the card (CLK)

V_o

output voltage

inactive mode; no load

inactive mode; I_o= 1 mA

inactive mode

0

-

0.1

0.3

1

V

I_o

output current

mA

at grounded pin CLK

V_OL

LOW-level output voltage I_OL= 70 mA (current limit)

V_CC- 0.4

-

V_CC

0.3

V

C1 version

I_OL= 200 A

C2 Version

0

I

_OL= 200 A

HIGH-level output voltage I_OH= -200 A

I_OH= -70 mA (current limit)

C_L= 30 pF ^[2]

0

-

0.15 V_CC

V

V_OH

0.9 V_CC

V_CC

0.4

16

20

55

-

V

0

V

t_r

rise time

-

ns

MHz

%

t_f

fall time

C_L= 30 pF ^[2]

-

f_CLK

frequency on pin CLK

duty cycle

operational

C_L= 30 pF ^[2]

0

45

0.2

SR

slew rate

rise and fall; C_L= 30 pF;

VCC = +5 V

V/ns

rise and fall; C_L= 30 pF;

VCC = +3 V

0.12

-

V/ns

rise and fall; C_L= 30 pF;

VCC = +1.8 V

0.072

Control inputs (pins CS, CMDVCCN, CLKDIV1, CLKDIV2, RSTIN, EN_5V/ 3VN, EN_1.8VN)^[3]

V_IL

V_IH

V_hys

I_LL

LOW-level input voltage

HIGH-level input voltage

hysteresis voltage

0.3

-

+0.3 V_DD(INTF)

V

0.7 V_DD(INTF)

V_DD(INTF)+ 0.3 V

on control input

V_IL= 0

0.05 V_DD(INTF)

-

0.25 V_DD(INTF)

1

V

LOW-level leakage

current

A

I_LH

HIGH-level leakage

current

V_IH= V_DD(INTF)

-

1

A

Card presence input (PRESN); PRESN has an integrated pull down resistor^[3]

V_IL

V_IH

LOW-level input voltage

HIGH-level input voltage

0.3

-

+0.3 V_DD(INTF)

V_DD(INTF)+ 0.3

V

0.7 V_DD(INTF)

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High integrated and low power smart card interface

Table 7.

Characteristics of IC …continued

V_DDP= 3.3 V; V_DD(INTF)= 3.3 V; f_XTAL= 10 MHz; GND = 0 V; T_amb=25 C; unless otherwise specified

Symbol

V_hys

Parameter

Conditions

Min

Typ

Max

Unit

V

hysteresis voltage

0.05 V_DD(INTF)

-

0.10 V_DD(INTF)

1

I_LL

LOW-level leakage

current

V_IL= 0

A

I_LH

HIGH-level leakage

current

V_IH= V_DD(INTF)

-

5

A

OFFN output (pin OFFN is an NMOS drain with a k pull-up resistor to V_DD(INTF)

)

V_OL

V_OH

R_pu

LOW-level output voltage I_OL= 2 mA

HIGH-level output voltage I_OH= -15 A

pull-up resistance

0

-

0.3

12

V

0.75 V_DD(INTF)

8

-

V

10

k

Protections and limitations

T_sd

shutdown temperature

at die

-

150

-

C

I_Olim

output current limit

on pin I/O

-15

-70

-20

90

80

+15

+70

+20

160

260

150

250

mA

on pin CLK

-

on pin RST

-

on pin VCC = 5 V or 1.8 V

on pin VCC = 3 V

on pin VCC = 5 V or 1.8 V

on pin VCC = 3 V

125

160

115

150

I_sd

shutdown current

Timing

t_act

activation time

deactivation time

activation time

see Figure 8 on page 13

see Figure 9 on page 14

1847

35

-

3390

250

s

t_deact

t_act

90

time of the window for sending 1992

CLK to the card with XTAL1

2690 3653

t_act(start)= t3; see Figure 8 on 2055

page 13

2766 3749

s

t_act(end) = t5; see Figure 8 on

page 13

t_deb

debounce time

on pin PRESN

2.96

4.05

5.55

ms

[1] To meet these specifications, VCC is decoupled to CGND using two ceramic multilayer capacitors of low ESR with both capacitors

having a value of 220 nF.

[2] The transition time and the duty factor definitions are shown in Figure 12 on page 25; d = t1/(t1+ t2)

[3] PRESN and CMDVCCN are active LOW; RSTIN is active HIGH; for CLKDIV1 and CLKDIV2 see Table 4.

[4] Capacitance should not vary more than +- 30% compared to nominal value, taking all parameters into account (temperature, process

variation, biasing voltage, etc. Non exhaustive list)

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Product data sheet

Rev. 3 — June 30, 2016

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TDA8035

NXP Semiconductors

High integrated and low power smart card interface

t

f

t

r

V

OH

90%

(V

+ V ) /2

OL

OH

10%

V

OL

t

2

1

fce666

Fig 12. Definition of output and input transition times

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12. Application information

(1) Place close to the protected pin with good (low resistive) and straight connection to the main ground

(2) Place close to the supply pin with good (low resistive) and straight connection to GNDP

(3) Place close to TDA8035´s VCC pin with good connection to GNDC

(4) Place close to card connector´s C1 (VCC) pin with good connection to GNDC

(5) Optional bridge. If not used, R1 must be O  and R2 absent (direct connection to V_DD(INTF)

)

(6) GNDP and GNDC are connected to the main ground with a straight and low resistive connection

(7) The card connector represented here has a normally closed presence switch

(8) DC/DC converter capacitance value:

If VDDP=3.3v, C3=C4= 330nF & C5=1uF

If VDDP=5.0v, C3=C4= 100nF & C5=1uF

Fig 13. Application diagram

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Rev. 3 — June 30, 2016

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13. Package outline

HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;

32 terminals; body 5 x 5 x 0.85 mm

SOT617-7

D

B

A

terminal 1

index area

E

A

1

c

detail X

e

1

1/2 e

C

v

C A

B

e

b

y

C

1

y

w

C

9

16

L

8

17

e

E

e

2

h

1/2 e

1

24

X

terminal 1

index area

32

25

D

h

0

2.5

scale

5 mm

w

Dimensions

Unit

(1)

A

b

c

D

h

E

e

1

e

2

L

v

y

1

h

max 1.00 0.05 0.30

5.1 2.2 5.1 2.2

0.5

mm nom 0.85 0.02 0.21 0.2 5.0 2.1 5.0 2.1 0.5 3.5 3.5 0.4 0.1 0.05 0.05 0.1

min 0.80 0.00 0.18 4.9 2.0 4.9 2.0 0.3

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

sot617-7_po

References

Outline

version

European

projection

Issue date

IEC

JEDEC

- - -

JEITA

- - -

10-02-08

10-02-09

SOT617-7

Fig 14. Package outline SOT617-7

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14. Soldering

For all "Surface mount reflow soldering" information for the SOT617 packaging, utilize the

following NXP Semiconductors documentation link:

http://www.nxp.com/documents/application_note/AN10365.pdf

15. Abbreviations

Table 8.

Abbreviations

Description

Acronym

ESD

ElectroStatic Discharge

16. Revision history

Table 9.

Revision history

Document ID

TDA8035HN v. 3.1

Modifications

Release date Data sheet status

Change notice

Supersedes

20160630

Product data sheet

-

TDA8035HN v. 3.0

• Addition of C2 Version - EMVCo 4.3 compliant

• Table 7 “Characteristics of IC”; updated

TDA8035HN v. 3.0

Modifications:

20140625

Product data sheet

-

TDA8035HN v. 2.1

TDA8035HN v. 2.0

• Section 5 “Ordering information”: type TDA8035HN/C1/S1 added

• Descriptive title changed

TDA8035HN v. 2.1

Modifications:

20121203

Product data sheet

-

• Table 3 “Pin description”: updated

• Section 8.1 “Power supply”: updated

• Table 7 “Characteristics of IC”: updated

• Figure 13 “Application diagram”: Table note (7) added

TDA8035HN v. 2.0

Modifications:

20111220

• All text updated to NXP standards

20110706 Product data sheet

Product data sheet

-

TDA8035HN v. 1.1

Modifications:

-

TDA8035HN v. 1.0

-

• Table 7 “Characteristics of IC”: V_{th(L)(PORADJ)}values updated

20110419 Product data sheet

TDA8035HN v. 1.0

-

TDA8035

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Product data sheet

Rev. 3 — June 30, 2016

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TDA8035

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17. Legal information

17.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use — NXP Semiconductors products are not designed,

17.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

17.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

TDA8035

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Product data sheet

Rev. 3 — 30 June 2016

29 of 32

TDA8035

NXP Semiconductors

High integrated and low power smart card interface

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

non-automotive qualified products in automotive equipment or applications.

17.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

18. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

TDA8035

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Product data sheet

Rev. 3 — 30 June 2016

30 of 32

TDA8035

NXP Semiconductors

High integrated and low power smart card interface

19. Tables

Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .2

Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .3

Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5

Table 4. Clock configuration. . . . . . . . . . . . . . . . . . . . . .10

Table 5. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .17

Table 6. Thermal characteristics . . . . . . . . . . . . . . . . . . 17

Table 7. Characteristics of IC . . . . . . . . . . . . . . . . . . . . 18

Table 8. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 9. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 28

20. Figures

Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Fig 2. Pin configuration HVQFN32 . . . . . . . . . . . . . . . . .5

Fig 3. Block voltage supervisor . . . . . . . . . . . . . . . . . . . .8

Fig 4. Voltage supervisor . . . . . . . . . . . . . . . . . . . . . . . . .9

Fig 5. Voltage supervisor . . . . . . . . . . . . . . . . . . . . . . . . .9

Fig 6. Switch external clock . . . . . . . . . . . . . . . . . . . . . .10

Fig 7. Shutdown mode and Deep Shutdown mode . . . .12

Fig 8. Activation sequence at t3 . . . . . . . . . . . . . . . . . .13

Fig 9. Deactivation sequence . . . . . . . . . . . . . . . . . . . .14

Fig 10. Emergency deactivation sequence

(card extraction). . . . . . . . . . . . . . . . . . . . . . . . . .16

Fig 11. Behavior of OFFN, CMDVCCN, PRESN

and V_CC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Fig 12. Definition of output and input transition times . . .25

Fig 13. Application diagram . . . . . . . . . . . . . . . . . . . . . . .26

Fig 14. Package outline SOT617-7 . . . . . . . . . . . . . . . . .27

TDA8035

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Product data sheet

Rev. 3 — 30 June 2016

31 of 32

TDA8035

NXP Semiconductors

High integrated and low power smart card interface

21. Contents

1

General description. . . . . . . . . . . . . . . . . . . . . . 1

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Protection of the contact smart card. . . . . . . . . 1

Easy integration into your contact reader . . . . . 1

Other. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.1

2.2

2.2.1

3

4

5

6

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Quick reference data . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

7

7.1

7.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

8

Functional description . . . . . . . . . . . . . . . . . . . 7

Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Voltage supervisor . . . . . . . . . . . . . . . . . . . . . . 8

Clock circuitry . . . . . . . . . . . . . . . . . . . . . . . . . 10

I/O circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

CS control. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Shutdown mode and Deep Shutdown mode . 12

Activation sequence . . . . . . . . . . . . . . . . . . . . 13

Deactivation sequence . . . . . . . . . . . . . . . . . . 14

V_CCregulator . . . . . . . . . . . . . . . . . . . . . . . . . 14

Fault detection . . . . . . . . . . . . . . . . . . . . . . . . 15

8.1

8.2

8.3

8.4

8.5

8.6

8.7

8.8

8.9

8.10

9

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17

Thermal characteristics . . . . . . . . . . . . . . . . . 17

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 18

Application information. . . . . . . . . . . . . . . . . . 26

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 27

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 28

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 28

10

11

12

13

14

15

16

17

Legal information. . . . . . . . . . . . . . . . . . . . . . . 29

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 29

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 30

17.1

17.2

17.3

17.4

18

19

20

21

Contact information. . . . . . . . . . . . . . . . . . . . . 30

Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 30 June 2016

Document identifier: TDA8035


型号：	TDA8035HN/C1
厂家：	NXP
描述：	IC SPECIALTY ANALOG CIRCUIT, PQCC32, 5 X 5 MM, 0.85 MM HEIGHT, PLASTIC, SOT617-7, HVQFN-32, Analog IC:Other
文件：	总32页 (文件大小：837K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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