TDA8594SD/N1,112 [NXP]
TDA8594 - I²C-bus controlled 4 x 50 W power amplifier ZIP 27-Pin;
| 型号： | TDA8594SD/N1,112 |
| 厂家： | 
NXP |
| 描述： | TDA8594 - I²C-bus controlled 4 x 50 W power amplifier ZIP 27-Pin 局域网 放大器 CD 商用集成电路 |
| 文件： | 总49页 (文件大小：496K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TDA8594
I2C-bus controlled 4 50 W power amplifier
Rev. 5 — 11 June 2013
Product data sheet
1. General description
The TDA8594 is a complementary quad Bridge Tied Load (BTL) audio power amplifier
made in BCDMOS technology. It contains four independent amplifiers in BTL
configuration. Through the I2C-bus, diagnosis of temperature warning and clipping level is
fully programmable and the information available via two diagnostic pins is selectable.
The status of each amplifier (output offset, load or no load, short-circuit or speaker
incorrectly connected) can be read separately.
2. Features and benefits
2.1 General
Operates in legacy mode (non I2C-bus) and I2C-bus mode (3.3 V and 5 V compliant)
Three hardware-programmable I2C-bus addresses
Drives 4 or 2 loads
Speaker fault detection
Independent short-circuit protection per channel
Loss of ground and open VP safe (with 200 m series impedance and a supply
decoupling capacitor of 2200 F maximum)
All outputs short-circuit proof to ground, supply voltage and across the load
All pins short-circuit proof to ground
Temperature-controlled gain reduction to prevent audio holes at high junction
temperatures
Low battery voltage detection
Offset detection
This part has been qualified in accordance with AEC-Q100
2.2 I2C-bus mode
DC load detection: open-circuit, short-circuit and load present
AC load (tweeter) detection
During start-up, can detect which load is connected so the appropriate gain can be
selected without audio pop
Independently selectable soft mute of front channels (channel 1 and channel 3) and
rear channels (channel 2 and channel 4)
Programmable gain (26 dB and 16 dB) of front channels (channel 1 and channel 3)
and rear channels (channel 2 and channel 4)
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
Fully programmable diagnostic levels can be set:
Programmable clip detection: 2 %, 5 % or 10 %
Programmable thermal pre-warning
Selectable information on the DIAG and STB pins:
The STB pin can be programmed/multiplexed with second clip detection
Clip information of each channel can be directed separately to the DIAG pin or the
STB pin
Independent enabling of thermal, clip or load fault detection (short across or to VP
or to ground) on DIAG pin
3. Quick reference data
Table 1.
Quick reference data
Symbol Parameter
Conditions
Min
Typ
Max Unit
VP
Iq
supply voltage
quiescent current
output power
RL = 4
8
-
14.4 18
V
no load
270
400
mA
Po
VP = 14.4 V
RL = 4 ; THD = 0.5 %
RL = 4 ; THD = 10 %
19
26
42
22
28
44
-
-
-
W
W
W
RL = 4 ; maximum
power; Vi = 2 V (RMS)
square wave
RL = 2 ; maximum
power; Vi = 2 V (RMS)
square wave
70
-
75
-
W
%
THD
Vn(o)
total harmonic
distortion
RL = 4 ; f = 1 kHz;
0.01 0.1
Po = 1 W to 12 W
output noise voltage
filter 20 Hz to 22 kHz;
RS = 1 k
normal mode
-
-
45
22
65
29
V
V
line driver mode
4. Ordering information
Table 2.
Ordering information
Type number Package
Name
Description
Version
TDA8594J
DBS27P
plastic DIL-bent-SIL (special bent) power package;
27 leads (lead length 6.8 mm)
SOT827-1
TDA8594SD
RDBS27P
plastic rectangular-DIL-bent-SIL (reverse bent) power SOT878-1
package; 27 leads (row spacing 2.54 mm)
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
2 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
5. Block diagram
ADSEL SDA SCL
26 23
V
V
P1
P2
7
1
21
5
2
2
STANDBY/
FAST MUTE
I C-BUS
DIAG
STB
CLIP DETECT/DIAGNOSTIC
INTERFACE
10
8
12
16
13
15
MUTE
OUT1+
26 dB/
16 dB
IN1
IN3
IN2
IN4
OUT1−
PROTECTION/
DIAGNOSTIC
18
20
MUTE
OUT3+
26 dB/
16 dB
OUT3−
PROTECTION/
DIAGNOSTIC
6
4
MUTE
OUT2+
26 dB/
16 dB
OUT2−
PROTECTION/
DIAGNOSTIC
22
24
MUTE
OUT4+
26 dB/
16 dB
OUT4−
V
P
PROTECTION/
DIAGNOSTIC
27
TAB
TDA8594
11
SVR
14
17
9
3
19
25
PGND4
SGND
ACGND
PGND1 PGND2 PGND3
001aad119
Fig 1. Block diagram
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
3 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
6. Pinning information
6.1 Pinning
1
ADSEL
STB
2
3
PGND2
OUT2−
DIAG
4
5
6
OUT2+
7
V
P2
8
OUT1−
PGND1
OUT1+
SVR
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
IN1
IN2
SGND
IN4
TDA8594
IN3
ACGND
OUT3+
PGND3
OUT3−
V
P1
OUT4+
SCL
OUT4−
PGND4
SDA
TAB
001aad120
Fig 2. Pin configuration
6.2 Pin description
Table 3.
Symbol
ADSEL
STB
Pin description
Pin
1
Description
I2C-bus address select input
2
standby (I2C-bus mode) or mode pin (legacy mode); programmable second
clip indicator
PGND2
OUT2
DIAG
3
4
5
6
7
power ground channel 2
negative channel 2 output
diagnostic/clip detection output
positive channel 2 output
supply voltage 2
OUT2+
VP2
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
4 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
Table 3.
Pin description …continued
Symbol
OUT1
PGND1
OUT1+
SVR
Pin
8
Description
negative channel 1 output
power ground channel 1
positive channel 1 output
half supply filter capacitor
channel 1 input
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
IN1
IN2
channel 2 input
SGND
IN4
signal ground
channel 4 input
IN3
channel 3 input
ACGND
OUT3+
PGND3
OUT3
VP1
AC ground input
positive channel 3 output
power ground channel 3
negative channel 3 output
supply voltage 1
OUT4+
SCL
positive channel 4 output
I2C-bus clock input
OUT4
PGND4
SDA
negative channel 4 output
power ground channel 4
I2C-bus data input/output
heatsink connection, must be connected to ground
TAB
To keep the output pins on the front side, special reverse bending is applied.
7. Functional description
The TDA8594 is a complementary quad BTL audio power amplifier made in BCDMOS
technology. It contains four independent amplifiers in BTL configuration (see Figure 1).
Through the I2C-bus, the diagnostic functions of temperature level and clip level are fully
programmable and the information to be shown on the two diagnostic pins can be
selected. The status of each amplifier (output offset, load or no load, short-circuit or
speaker incorrectly connected) can be read separately. The TDA8594 is protected against
overvoltage, short-circuit, over-temperature, open ground and open VP connections.
Three different I2C-bus addresses are selected with an external resistor connected to the
ADSEL pin. If the ADSEL pin is short-circuit to ground, the TDA8594 operates in legacy
mode. In this mode, no I2C-bus is needed and the function of the STB pin will change from
two-level (Standby mode and On mode) to a three-level pin (Standby mode, On mode and
mute).
7.1 Input stage
The input stage is a high-impedance pseudo-differential input stage. The negative inputs
of the four channels are combined on the ACGND pin. For the best performance on
supply voltage ripple rejection and pop noise, the capacitor connected to the ACGND pin
must be four times the value of the input capacitor (or as close to the value as possible).
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
5 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
7.2 Output stage
The output stage of each amplifier channel consists of two PMOS power transistors and
two NMOS transistors in a BTL configuration. The process used is the BCDMOS process
with an isolated substrate, Silicon On Insulator (SOI) process, which has almost no
parasitic components and therefore prevents latch-up.
7.3 Distortion (clip) detection
If the output of the amplifier starts clipping to the supply voltage or to ground, the output
will become distorted. If the distortion per channel exceeds a selectable threshold (2 %,
5 % or 10 %), one of the two diagnostic pins (DIAG pin or STB pin) will be activated. To be
able to detect if, for instance, the front channels (channel 1 and channel 3) or rear
channels (channel 2 and channel 4) are clipping, the clip information can be directed per
channel to the DIAG pin or the STB pin. It is possible to have only the clip information on
the diagnostic pins by disabling the temperature and load information on the DIAG pin. In
this mode the temperature and load protection are still functional but can only be read via
the I2C-bus.
7.4 Output protection and short-circuit operation
When a short-circuit to ground, VP or across the load occurs on one or more outputs of an
amplifier, only the amplifier with the short-circuit is switched off. The channel that has a
short-circuit and the type of short-circuit can be read-back via the I2C-bus. If the DIAG pin
is enabled for load fault information (IB2[D4] = 0) the DIAG pin will be pulled LOW. After
16 ms the amplifier will be switched on again and, if the short-circuit conditions still occur,
the amplifier will be switched off.
The 16 ms cycle will reduce the dissipation. To prevent audible distortion, the amplifier
channel with the short-circuit can be disabled via the I2C-bus.
7.5 SOAR protection
The output transistors are protected by Safe Operating ARea (SOAR) protection. The
TDA8594 has a two-stage SOAR protection:
• If the differential output voltage across the load is less than 1 V, and the current
through the load is more than 4 A, the amplifier channel will be switched off for 16 ms.
To prevent incorrect switch-off with an inductive load or very high input signals, the
condition (Vo < 1 V and IL > 4 A) must exist for more than 300 s.
• If the differential output voltage across the load is more than 1 V, and the current
through the load is more than 8 A, the amplifier channel will be switched off for 16 ms.
7.6 Speaker protection
To prevent damage of the speaker when one side of the speaker is connected to ground,
a missing current protection is implemented. When in one channel the current in the high
side power is not equal to the current in the low side power, a fault condition is assumed
and the channel will be switched off. The speaker protection will be activated under the
following conditions:
• Vo < 1.75 V and Imissing(det) > 1 A for 80 s
• Vo > 1.75 V and Imissing(det) > 3 A for 80 s
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
6 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
7.7 Standby and mute operation
The function of the STB pin is different in legacy mode and I2C-bus mode.
7.7.1 Legacy mode (pin ADSEL connected to ground)
The function of the STB pin will change from standby/operating to standby/mute/operating
and the amplifier will start directly when the STB is put into mute or operating mode. Mute
operating is controlled via an internal timer (20 ms) to minimize mute-on pops. When the
STB pin is switched directly from operating to standby, first the fast mute will be activated
(switching to mute within 100 s) and then the amplifier will shut-down.
7.7.2 I2C-bus mode
When the STB pin is LOW, the total quiescent current is low, and the I2C-bus lines will not
be loaded.
When the STB pin is switched HIGH, the TDA8594 is put in operating condition and will
perform a Power-On Reset (POR), which results in a LOW level DIAG pin. The TDA8594
will start up when instruction bit IB1[D0] is set. Bit D0 will also reset the ‘power-on reset
occurred’ bit (DB2[D7]) and releases the DIAG pin.
The soft mute and fast mute can be activated via the I2C-bus. The soft mute can be
activated independently for the front channels (channel 1 and channel 3) and rear
channels (channel 2 and channel 4), and mutes the audio in 20 ms. The fast mute
activates the mute for all channels at the same time and mutes the audio in 0.1 ms.
Releasing the mute after a fast mute will be by a soft un-mute of approximately 20 ms.
When the STB pin is switched to Standby mode and the amplifier has started, first the fast
mute will be activated and then the amplifier will shut-down. For instance, during an
engine start, it is possible to fully mute the amplifiers within 100 s by switching the STB
pin to zero.
7.8 Start-up and shut-down sequence
To prevent the amplifier producing switch-on or switch-off pop noise, the capacitor on the
SVR pin is used for smooth start-up and shut-down. Increasing the value of the SVR
capacitor will mean a longer start-up and shut-down time. The amplifier output voltage is
charged to half the supply voltage minus 1.4 V in mute condition, independent of the
I2C-bus mute settings in I2C-bus mode or STB voltage in legacy mode. The last 1.4 V,
where the output will reach half the supply voltage, is used to release the mute if the
I2C-bus bits were set to mute off (IB2[D2:D0] = 000; VSTB > 6.5 V in legacy mode), or will
stay in mute when the bits were set to mute (2.6 V < VSTB < 4.5 V in legacy mode).
When the amplifier is switched off by pulling the STB pin LOW, the amplifier is first muted
(fast mute) and then the capacitor on the SVR pin is discharged. With an SVR capacitor of
22 F, the standby current has reached 1 second after the STB pin is switched to zero
(see Figure 3, Figure 4, Figure 5 and Figure 6).
The start-up and shut-down pop can be further decreased by activating the low pop mode.
When the low pop mode is enabled (IB2[D3] = 0), the output voltage rise from ground
level during start-up will be slower (see Figure 5). This will decrease the pop even more
but will increase the start-up time.
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
7 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
V
P
DIAG
DB2 bit D7
POR
IB1 bit D0
start enable
t
wake
STB
SVR
t
t
off
amp_on
fast
mute
amplifier
output
t
t
t
d(fast_mute)
d(mute_off)
d(soft_mute)
001aad168
Fig 3. Start-up and shut-down timing in I2C-bus mode
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
8 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
V
P
DIAG
DB2 bit D7
POR
IB1 bit D0
start enable
t
wake
STB
SVR
t
load
t
t
off
amp_on
fast
mute
amplifier
output
t
t
t
d(fast_mute)
d(mute_off)
d(soft_mute)
001aad169
Fig 4. Start-up and shut-down timing with DC load active in I2C-bus mode
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
9 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
V
P
DIAG
DB2 bit D7
POR
IB1 bit D0
start enable
t
wake
STB
SVR
t
load
t
t
off
amp_on
fast
mute
amplifier
output
t
t
t
d(fast_mute)
d(mute_off)
d(soft_mute)
001aad170
Fig 5. Start-up and shut-down timing with low audible pop and DC load activated
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
10 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
V
P
DIAG
STB
on
mute
standby
SVR
t
t
off
amp_on
soft
mute
fast
mute
amplifier
output
t
d(mute_off)
t
t
t
d(fast_mute)
d(soft_mute)
d(mute_on)
001aad171
Fig 6. Start-up and shut-down timing in legacy mode
7.9 Power-on reset and supply voltage spikes
If in I2C-bus mode the supply voltage drops below 5 V (see Figure 9), the content of the
I2C-bus latches cannot be guaranteed and the power-on reset will be activated. All latches
are reset, the amplifier is switched off and the DIAG pin is pulled LOW to indicate that a
power-on reset has occurred (bit DB2[D7]). When IB1[D0] is set, the power-on flag is
reset, the DIAG pin will be released and the amplifier will start up.
In legacy mode a supply voltage drop below 5 V will switch off the amplifier and the DIAG
pin will not be pulled LOW.
7.10 Engine start and low voltage operation
The DC output voltage of the amplifier (VO) is set to half of the supply voltage and is
related to the voltage on the SVR pin (see Figure 7; VO = VSVR 1.4 V). A capacitor is
connected on the SVR pin to suppress the ripple on the power supply.
If the supply voltage drops, for instance, during an engine start, the output follows slowly
due to the SVR capacitor. The headroom voltage is the voltage needed for good operation
of the amplifier and is defined as Vhr = VP VO (see Figure 7). If the headroom voltage
becomes lower than the headroom protection threshold of 1.6 V, the headroom protection
is activated to prevent pop noise at the output. This protection first activates the fast mute
and then discharges the capacitors on the SVR and ACGND pins to generate more
headroom for the amplifier (see Figure 8).
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
11 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
When the SVR capacitor has discharged, the amplifier starts up again if the VP voltage is
above the low VP mute threshold, typically 7.5 V. Below the low VP mute threshold, the
outputs of the amplifier remain low. In I2C-bus mode, a supply voltage drop below VP(reset)
typically 5 V, results in setting bit DB2[D7] and not starting of the amplifiers but waiting for
an I2C-bus command to start.
,
The amplifier prevents audio pops during engine start. To prevent pops on the output
caused by the application during an engine start (for instance tuner regulator out of
regulation), the STB pin can be made zero when an engine start is detected. The STB pin
activates the fast mute and disturbances at the amplifier inputs are suppressed.
V
(V)
V
V
P
14
SVR
(1)
V
hr
8.4
7
(2)
O
V
1.6 V
t (s)
headroom protection
(3)
threshold
001aad172
(1) Headroom voltage Vhr = VP VO.
(2) Steady state output voltage VO = VSVR 1.4 V.
(3) Headroom protection threshold = VO + 1.6 V.
Fig 7. Low headroom protection
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
12 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
2
V
legacy and I C-bus mode
O
(V)
V
P
14.4
output
voltage
(1)
8.8
V
hr
8.6
7.2
(3)
(2)
V
SVR
3.5
output voltage
(3)
t (s)
t
(start-Vo(off))
001aad173
t
(start-SVRoff)
(1) Headroom protection activated:
a) Fast mute
b) Discharge of SVR.
(2) Low VP mute activated.
(3) Low VP mute released.
Fig 8. Low VP behavior; legacy and I2C-bus modes
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
13 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
2
V
I C-bus mode only
O
(V)
V
P
14.4
8.8
8.6
7.2
(1)
(2)
5.0
3.5
V
SVR
output voltage
0
POR
IB1 bit D0
DIAG
t (s)
001aad185
(1) Low VP mute activated.
(2) VPOR: VP level at which Power-On Reset (POR) is activated.
Fig 9. Low VP behavior; I2C-bus mode only
7.11 Overvoltage and load dump protection
When the battery voltage VP is higher than 22 V, the amplifier stage will be switched to
high-impedance. The TDA8594 is protected against load dump voltage with supply
voltage up to 50 V.
7.12 Thermal pre-warning and thermal protection
If the average junction temperature reaches a level that is adjustable via the I2C-bus,
selected with IB3[D4], the pre-warning will be activated resulting in a LOW level on
pin DIAG (if selected) and can be read out via the I2C-bus. The default setting for the
thermal pre-warning is IB3[D4] = 0 setting the warning level at 145 C. In legacy mode the
thermal pre-warning is set at 145 C.
If the temperature increases further, the temperature controlled gain reduction will be
activated for all four channels to reduce the output power (see Figure 10). If this does not
reduce the average junction temperature, all four channels will be switched off at the
absolute maximum temperature Toff, typical 175 C.
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
14 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
001aad174
30
G
v
(dB)
20
10
0
145
155
165
175
T (°C)
j
Fig 10. Temperature controlled amplifier gain
7.13 Diagnostics
Diagnostic information can be read via the I2C-bus, and can also be available on the DIAG
pin or on the STB pin. The DIAG pin has both fixed information (power-on reset occurred,
low battery and high battery) and, via the I2C-bus, selectable information (temperature,
load fault and clip). This information will be seen at the DIAG pin as a logic OR. In case of
a failure, the DIAG pin remains LOW and the failure information can be read from the
microprocessor via the I2C-bus (the DIAG pin can be used as a microprocessor interrupt
to minimize I2C-bus traffic). When the failure is removed, the DIAG pin will be released.
To have full control over the clipping information, the STB pin can be programmed as a
second clip detection pin. The clip detection level can be selected for all channels at once.
It is possible to select whether the clip information is available on the DIAG pin or on the
STB pin for each channel separately. It is, for instance, possible to distinguish between
clipping of the front and the rear channels.
Diagnostic information selection possibilities are shown in Table 4.
Table 4.
Diagnostic information availability
Diagnostic information I2C-bus mode
Legacy mode
DIAG pin
no
DIAG pin
STB pin
POR
after power-on reset, DIAG
no
pin will remain LOW until
amplifier has been started
Low battery
yes
no
yes
Clip detection
can be enabled per channel
can be enabled yes, fixed level for all
per channel
channels on 2 %
Temperature
pre-warning
can be enabled
no
yes, pre-warning
level is 145 C
Short
can be enabled
can be enabled
no
no
yes
yes
Speaker protection
(missing current)
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
15 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
Table 4.
Diagnostic information availability …continued
Diagnostic information I2C-bus mode
Legacy mode
DIAG pin
STB pin
no
DIAG pin
Offset detection
Load detection
Overvoltage
no
no
no
no
no
yes
no
yes
7.14 Offset detection
The offset detection can be performed with no input signal (for instance when the digital
signal processor is in mute after a start-up) or with an input signal. In I2C-bus mode, if an
I2C-bus read of the output offset is performed, the I2C-bus latches DBx[D2] will be set.
When the amplifier BTL output voltage is within a window with a threshold of 1.75 V
typical, the latches DBx[D2] are reset and setting is disabled. If, for instance, after 1
second an I2C-bus read is performed again and the offset bits are still set, the output has
not crossed the offset threshold during the last 1 second (see Figure 11). This can mean
the applied frequency is below 1 Hz (I2C-bus read interval = 1 s) or an output offset of
more than 1.75 V is present.
2
V
O
= V
− V
OUT+ OUT−
I C-bus mode only
offset
threshold
t
reset:
t = 1 s:
setting
disabled
read = no offset
DB1 bit D2 reset
V
= V
− V
OUT+ OUT−
O
offset
threshold
t
read = set bit
t = 1 s:
read = offset
DB1 bit D2 set
001aad175
Fig 11. Offset detection
7.15 DC load detection
When the DC load detection is enabled with IB1[D1], a DC offset is slowly applied at the
output of the amplifiers during the start-up cycle and the load currents are measured.
Different load levels will be detected to differentiate between normal load, line driver load
or open load.
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
16 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
LOAD
NORMAL
LINE DRIVER MODE
OPEN-CIRCUIT
DETECTION
LEVEL
20 Ω 100 Ω
800 Ω 5 kΩ
001aad176
Fig 12. DC load detection levels
If the amplifier is used as line driver and the external booster has an input impedance of
more than 100 and less than 800 (DC-coupled), the DC load bits will contain
DBx[D5:D4] = 10, independent of the gain setting (see Table 5).
Table 5.
DC load detection
DC load bits
Meaning (when IB1[D2] = 0)
DBx[D5]
DBx[D4]
0
1
1
0
0
0
1
1
normal load
line driver load
open load
not valid
By reading the I2C-bus bits the microprocessor can determine, after the start-up of the
amplifier, whether a speaker or an external booster is connected.
Depending on these bits, the amplifier gain can be selected, 26 dB for normal mode or
16 dB for line driver mode. If the gain select is performed when the amplifier is muted, the
gain select will be pop free.
The DC load bits are combined with the AC load bits and are only valid when the AC load
detection is disabled. When the AC load detection is enabled (IB1[D2] = 1), the bits
DBx[D4] will show the content of the AC load detection. When the AC load detection is
disabled again, bit DBx[D4] will show the content of the DC load measurement, which was
stored during the AC load measurement. The AC load detection can only be performed
after the amplifier has completed its start-up cycle and will not conflict with the DC load
detection.
7.16 AC load detection
The AC load detection, enabled with IB1[D2] = 1, is used to detect if AC-coupled
speakers, for example tweeters, are connected correctly during assembly. The detection
is audible because a sine wave of a certain frequency (e.g. 19 kHz) needs to be applied to
the inputs of the amplifier. The output voltage over the load impedance will generate an
amplifier current. If the amplifier peak current triggers a 460 mA (peak) threshold detector
three times, the AC load detection bit will be set. A three ‘threshold cross’ counter is used
to prevent false AC load detection when switching the input signal on or off.
An AC-coupled speaker will reduce the impedance at the output of the amplifier in a
certain frequency band. The presence of an AC-coupled speaker can be determined
using 460 mA (peak) and 230 mA (peak) threshold current detection. For instance, at an
output voltage of 2 V (peak) the total impedance must be less than 4 to detect the
AC-coupled load, or more than 8 to guarantee only a DC connection is detected.
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
17 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
The interpretation of line driver and normal mode DC load bit settings for AC load
detection is shown in Table 6.
Table 6.
AC load detection
DBx[D4]
Meaning (when IB1[D2] = 1)
no AC load detected
AC load detected
0
1
When bit IB1[D2] = 1, the AC load detection is enabled. The AC load detection can only
be performed after the amplifier has completed its start-up cycle and will not conflict with
the DC load detection.
001aad177
20
|Z
|
th(load)
(Ω)
16
12
8
(1)
(2)
4
0
0
1
2
3
4
5
V
(V)
oM
(1) Ith(o)det(load)AC < 230 mA (no load detection level)
(2) th(o)det(load)AC > 460 mA (load detection level)
I
Fig 13. AC load impedance as a function of peak output voltage
7.17 I2C-bus diagnostic readout
The diagnostic information of the amplifier can be read via the I2C-bus. The I2C-bus bits
are set on a failure and will be reset with the I2C-bus read command. Even when the
failure is removed, the microprocessor will know what was wrong by reading the I2C-bus.
The consequence of this procedure is that old information is read during the I2C-bus
readout. Most actual information will be gathered after two successive read commands.
The DIAG pin will give actual diagnostic information (when selected). When a failure is
removed, the DIAG pin will be released instantly, independently of the I2C-bus latches.
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
18 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
8. I2C-bus specification
Table 7.
Pin ADSEL
Open
TDA8594 hardware address select
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
0
1
1
0
0
0 = write to TDA8594
1 = read from TDA8594
0 = write to TDA8594
1 = read from TDA8594
0 = write to TDA8594
1 = read from TDA8594
51 k to ground
10 k to ground
Ground
1
1
1
1
0
0
1
1
1
1
0
1
1
1
no I2C-bus; legacy mode
SDA
SCL
S
P
STOP condition
mba608
START condition
Fig 14. Definition of START and STOP conditions
SDA
SCL
data line
stable;
data valid
change
of data
allowed
mba607
Fig 15. Bit transfer
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
19 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
2
I C-BUS WRITE
SCL
1
2
7
8
9
1
2
7
8
9
MSB − 1
MSB MSB − 1
LSB + 1
LSB
MSB
LSB + 1
ACK
ACK
SDA
S
A
A
P
ADDRESS
WRITE DATA
W
To stop the transfer, after the last acknowledge (A)
a STOP condition (P) must be generated
2
I C-BUS READ
SCL
SDA
1
2
7
8
9
1
2
7
8
9
MSB MSB − 1
LSB + 1
MSB MSB − 1
LSB + 1
LSB
ACK
A
ACK
NA
P
S
R
READ DATA
ADDRESS
To stop the transfer, the last byte must not be acknowledged
and a STOP condition (P) must be generated
: generated by master (microcontroller)
: generated by slave
: START
001aac649
S
P
: STOP
A
: acknowledge
NA
: not acknowledge
R/W : read / write
Fig 16. I2C-bus read and write modes
8.1 Instruction bytes
I2C-bus mode:
• If bit R/W = 0, the TDA8594 expects three instruction bytes; IB1, IB2 and IB3
• After a power-on reset, all instruction bits are set to zero.
Legacy mode:
• All bits equal to zero define the setting, with the exception of bit IB1[D0] which is
ignored; see Table 8.
Table 8.
Bit
Instruction byte IB1
Description
D7
don’t care
D6
channel 3 clip information on DIAG or STB pin
0 = clip information on DIAG pin
1 = clip information on STB pin
channel 1 clip information on DIAG or STB pin
0 = clip information on DIAG pin
1 = clip information on STB pin
D5
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
20 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
Table 8.
Instruction byte IB1 …continued
Bit
Description
D4
channel 4 clip information on DIAG or STB pin
0 = clip information on DIAG pin
1 = clip information on STB pin
D3
D2
D1
D0
channel 2 clip information on DIAG or STB pin
0 = clip information on DIAG pin
1 = clip information on STB pin
AC load detection enable
0 = AC load detection disabled
1 = AC load detection enabled; DBx[D4] bits not available for DC load detection
DC load detection enable
0 = DC load detection disabled
1 = DC load detection enabled
amplifier start enable
0 = amplifier not enabled, DIAG pin will remain LOW
1 = amplifier will start up, power-on occurred (DB2[D7] will be reset) and DIAG
pin will be released
Table 9.
Bit
Instruction byte IB2
Description
D7 and D6
clip detection level
00 = clip detection level 2 %
01 = clip detection level 5 %
10 = clip detection level 10 %
11 = clip detection level disabled
temperature information on DIAG pin
0 = temperature information on DIAG pin
1 = no temperature information on DIAG pin
load fault information (shorts, missing current) on DIAG pin
0 = fault information on DIAG pin
1 = no fault information on DIAG pin
low pop (slow start) enable
0 = low pop enabled
D5
D4
D3
D2
D1
1 = low pop disabled
soft mute channel 1 and channel 3 (mute delay 20 ms)
0 = no mute
1 = mute
soft mute channel 2 and channel 4 (mute delay 20 ms)
0 = no mute
1 = mute
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
21 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
Table 9.
Instruction byte IB2 …continued
Bit
Description
D0
fast mute all amplifier channels (mute delay 100 s)
0 = no mute
1 = mute
Table 10. Instruction byte IB3
Bit
D7
D6
Description
don’t care
amplifier channel 1 and channel 3 gain select
0 = 26 dB
1 = 16 dB
D5
D4
D3
D2
D1
D0
amplifier channel 2 and channel 4 gain select
0 = 26 dB
1 = 16 dB
temperature pre-warning level
0 = warning level on 145 C
1 = warning level on 122 C
disable channel 3
0 = channel 3 enabled
1 = channel 3 disabled
disable channel 1
0 = channel 1 enabled
1 = channel 1 disabled
disable channel 4
0 = channel 4 enabled
1 = channel 4 disabled
disable channel 2
0 = channel 2 enabled
1 = channel 2 disabled
8.2 Data bytes
I2C-bus mode:
• If bit R/W = 1, the TDA8594 sends four data bytes to the microprocessor: DB1, DB2,
DB3, and DB4
• All bits except DB1[D7] and DB3[D7] are latched.
• All bits except DBx[D4] and DBx[D5] are reset after a read operation. Bit DBx[D2] is
set after a read operation; see Section 7.14
• For explanation of AC and DC load detection bits; see Section 7.15 and Section 7.16.
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
22 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
Table 11. Data byte DB1
Bit
Description
D7
temperature pre-warning
0 = no warning
1 = junction temperature too high
speaker fault channel 2 (missing current)
0 = no missing current
D6
1 = missing current
D5 and D4
channel 2 DC load or AC load detection
if bit IB1[D2] = 1, AC load detection is enabled, bit D5 is don’t care, bit D4 has the
following meaning
0 = no AC load
1 = AC load detected
if bit IB1[D2] = 0, AC load detection is disabled, bits D5 and D4 are available for
DC load detection
00 = normal load
01 = not valid
10 = line driver load
11 = open load
D3
D2
D1
D0
channel 2 shorted load
0 = not shorted load
1 = shorted load
channel 2 output offset
0 = no output offset
1 = output offset
channel 2 short to VP
0 = no short to VP
1 = short to VP
channel 2 short to ground
0 = no short to ground
1 = short to ground
Table 12. Data byte DB2
Bit
Description
D7
power-on reset and amplifier status
0 = amplifier on
1 = power-on reset has occurred; amplifier off
speaker fault channel 4 (missing current)
0 = no missing current
D6
1 = missing current
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
23 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
Table 12. Data byte DB2 …continued
Bit
Description
D5 and D4
channel 4 DC load or AC load detection
if bit IB1[D2] = 1, AC load detection is enabled, bit D5 is don’t care, bit D4 has the
following meaning
0 = no AC load
1 = AC load detected
if bit IB1[D2] = 0, AC load detection is disabled, bits D5 and D4 are available for
DC load detection
00 = normal load
01 = not valid
10 = line driver load
11 = open load
D3
D2
D1
D0
channel 4 shorted load
0 = not shorted load
1 = shorted load
channel 4 output offset
0 = no output offset
1 = output offset
channel 4 short to VP
0 = no short to VP
1 = short to VP
channel 4 short to ground
0 = no short to ground
1 = short to ground
Table 13. Data byte DB3
Bit
Description
D7
maximum temperature protection
0 = no protection
1 = maximum temperature protection
speaker fault channel 1 (missing current)
0 = no missing current
D6
1 = missing current
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
24 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
Table 13. Data byte DB3 …continued
Bit
Description
D5 and D4
channel 1 DC load or AC load detection
if bit IB1[D2] = 1, AC load detection is enabled, bit D5 is don’t care, bit D4 has the
following meaning
0 = no AC load
1 = AC load detected
if bit IB1[D2] = 0, AC load detection is disabled, bits D5 and D4 are available for
DC load detection
00 = normal load
01 = not valid
10 = line driver load
11 = open load
D3
D2
D1
D0
channel 1 shorted load
0 = not shorted load
1 = shorted load
channel 1 output offset
0 = no output offset
1 = output offset
channel 1 short to VP
0 = no short to VP
1 = short to VP
channel 1 short to ground
0 = no short to ground
1 = short to ground
Table 14. Data byte DB4
Bit
D7
D6
Description
reserved
speaker fault channel 3 (missing current)
0 = no missing current
1 = missing current
D5 and D4
channel 3 DC load or AC load detection
if bit IB1[D2] = 1, AC load detection is enabled, bit D5 is don’t care, bit D4 has the
following meaning
0 = no AC load
1 = AC load detected
if bit IB1[D2] = 0, AC load detection is disabled, bits D5 and D4 are available for
DC load detection
00 = normal load
01 = not valid
10 = line driver load
11 = open load
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
25 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
Table 14. Data byte DB4 …continued
Bit
Description
D3
channel 3 shorted load
0 = not shorted load
1 = shorted load
D2
D1
D0
channel 3 output offset
0 = no output offset
1 = output offset
channel 3 short to VP
0 = no short to VP
1 = short to VP
channel 3 short to ground
0 = no short to ground
1 = short to ground
9. Limiting values
Table 15. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
operating
Min
8
Max
18
Unit
V
VP
supply voltage
non operating
1
-
+50
50
V
load dump protection;
duration 50 ms, rise
time > 2.5 ms
V
VP(r)
IOSM
reverse supply voltage tmax = 10 minutes
-
-
2
V
A
non-repetitive peak
output current
13
IORM
repetitive peak output
current
-
-
8
A
Tj(max)
maximum junction
temperature
150
C
Tstg
storage temperature
ambient temperature
55
40
-
+150
+105
VP
C
C
V
Tamb
V(prot)
protection voltage
AC and DC short-circuit
of output pins and
across the load
Vx
voltage on pin x
pins SCL and SDA
0
0
6.5
13
V
V
pins IN1, IN2, IN3, IN4,
SVR, ACGND and
DIAG
pin STB
0
24
V
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
26 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
Table 15. Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Ptot
Parameter
Conditions
Min
Max
80
Unit
W
total power dissipation Tcase = 70 C
-
-
Vesd
electrostatic discharge human body model;
2000
V
voltage
C = 100 pF;
Rs = 1.5 k
machine model;
C = 200 pF; Rs = 10 ;
Ls = 0.75 H
-
200
V
10. Thermal characteristics
Table 16. Thermal characteristics
Symbol
Parameter
Conditions
Typ
Unit
Rth(j-c)
thermal resistance from junction
to case
1
K/W
Rth(j-a)
thermal resistance from junction in free air
to ambient
40
K/W
11. Characteristics
Table 17. Characteristics
Refer to Figure 29 at VP = VP1 = VP2 = 14.4 V; RL = 4 ; f = 1 kHz; RS = 0 ; normal mode; unless otherwise specified.
Tested at Tamb = 25 C; guaranteed for Tamb = 40 C to +105 C.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supply voltage behavior
VP
supply voltage
RL = 4
RL = 2
no load
8
14.4
14.4
270
4
18
16
400
15
7.2
8
V
[1]
8
V
Iq
quiescent current
standby current
-
mA
A
V
Istb
VSTB = 0.4 V
-
VO
output voltage
6.7
6.9
6.3
0.1
7
VP(low)(mute)
low supply voltage mute
with rising supply voltage
with falling supply voltage
7.5
6.8
0.7
V
7.4
1
V
VP(low)(mute)
Vth(ovp)
low supply voltage mute
hysteresis
V
overvoltage protection
threshold voltage
18
20
22
V
V
Vhr
headroom voltage
when headroom protection is
activated; see Figure 7
1.1
1.6
2.0
VPOR
power-on reset voltage
output offset voltage
see Figure 9
amplifier on
amplifier mute
line driver mode
VP 18 V
4.1
95
25
40
3.2
1.6
5.0
0
5.8
+95
+25
+40
-
V
VO(offset)
mV
mV
mV
0
0
RL(tol)
load resistance tolerance
4
VP 16 V
2
-
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
27 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
Table 17. Characteristics …continued
Refer to Figure 29 at VP = VP1 = VP2 = 14.4 V; RL = 4 ; f = 1 kHz; RS = 0 ; normal mode; unless otherwise specified.
Tested at Tamb = 25 C; guaranteed for Tamb = 40 C to +105 C.
Symbol
Mode select and second clip detection: pin STB
VSTB voltage on pin STB
Parameter
Conditions
Min
Typ
Max
Unit
Standby mode selected
I2C-bus mode
legacy mode (I2C-bus off)
-
-
-
-
1
1
V
V
mute selected
legacy mode (I2C-bus off)
Operating mode selected
I2C-bus mode
2.5
-
4.5
V
2.5
6.5
-
-
VP
VP
V
V
legacy mode (I2C-bus off)
[2]
low voltage on pin STB when
pulled down during clipping
ISTB = 150 A
ISTB = 500 A
5.6
6.1
-
-
6.1
7.2
V
V
ISTB
current on pin STB
VSTB = 0 V to 8.5 V
clip detection not active;
I2C-bus mode
-
-
4
30
70
A
A
legacy mode
10
Start-up, shut-down and mute timing
twake
wake-up time
time after wake-up via STB pin
before first I2C-bus transmission
is recognized; see Figure 3
-
-
300
-
500
10
s
ILO(SVR)
output leakage current on pin
SVR
A
[3]
td(mute_off)
mute off delay time
10 % of output signal; ILO = 0 A
I2C-bus mode;
295
500
640
430
465
640
830
650
795
ms
ms
ms
ms
with ILO = 10 A +15 ms;
no DC load (IB1[D1] = 0);
low pop disabled (IB2[D3] = 1);
see Figure 3
I2C-bus mode;
940
with ILO = 10 A +20 ms;
DC load active (IB1[D1] = 1);
low pop disabled (IB2[D3] = 1);
see Figure 4
I2C-bus mode;
1190
1030
with ILO = 10 A +20 ms;
DC load active (IB1[D1] = 1);
low pop enabled (IB2[D3] = 0);
see Figure 5
legacy mode;
with ILO = 10 A +20 ms;
VSTB = 7 V; RADSEL = 0 ;
see Figure 6
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
28 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
Table 17. Characteristics …continued
Refer to Figure 29 at VP = VP1 = VP2 = 14.4 V; RL = 4 ; f = 1 kHz; RS = 0 ; normal mode; unless otherwise specified.
Tested at Tamb = 25 C; guaranteed for Tamb = 40 C to +105 C.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[3]
tamp_on
amplifier on time
time from amplifier mute to
amplifier on; 90 % of output
signal; ILO = 0 A
I2C-bus mode;
360
520
870
ms
with ILO = 10 A +30 ms;
no DC load (IB1[D1] = 0);
low pop disabled (IB2[D3] = 1);
see Figure 3
I2C-bus mode;
565
710
510
695
890
720
1015
1270
1120
ms
ms
ms
with ILO = 10 A +35 ms;
DC load active (IB1[D1] = 1);
low pop disabled (IB2[D3] = 1);
see Figure 4
I2C-bus mode;
with ILO = 10 A +30 ms;
DC load active (IB1[D1] = 1);
low pop enabled (IB2[D3] = 0);
see Figure 5
legacy mode;
with ILO = 10 A +20 ms;
VSTB = 7 V; RADSEL = 0 ;
see Figure 6
[3]
toff
amplifier switch-off time
time to DC output voltage < 0.1 V;
I2C-bus mode; ILO = 0 A
with ILO = 10 A +0 ms;
low pop enabled (IB2[D3] = 0);
see Figure 4
120
245
280
20
530
620
40
ms
ms
ms
ms
with ILO = 10 A +0 ms;
low pop disabled (IB2[D3] = 1);
see Figure 5
140
td(mute-on)
mute to on delay time
soft mute delay time
from 10 % to 90 % of output
signal; IB2[D1] and IB2[D2] = 1 to
0; Vi = 50 mV; see Figure 6
-
-
td(soft_mute)
from 90 % to 10 % of output
signal; Vi = 50 mV; IB2[D1] and
IB2[D2] = 0 to 1 (soft mute);
see Figure 6
20
40
td(fast_mute)
fast mute delay time
from 90 % to 10 % of output
signal; VSTB from 8 V to 1.3 V
(fast mute); see Figure 6
-
0.1
1
ms
t(start-Vo(off))
t(start-SVRoff)
I2C-bus interface[4]
engine start to output off time VP from 14.4 V to 7 V; Vo < 0.5 V;
-
-
0.1
40
1
ms
ms
see Figure 8
engine start to SVR off time
VP from 14.4 V to 7 V;
75
VSVR < 2 V; see Figure 8
VIL
LOW-level input voltage
pins SCL and SDA
pins SCL and SDA
pin SDA; IL = 5 mA
-
-
-
-
1.5
5.5
0.4
V
V
V
VIH
VOL
HIGH-level input voltage
LOW-level output voltage
2.3
-
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
29 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
Table 17. Characteristics …continued
Refer to Figure 29 at VP = VP1 = VP2 = 14.4 V; RL = 4 ; f = 1 kHz; RS = 0 ; normal mode; unless otherwise specified.
Tested at Tamb = 25 C; guaranteed for Tamb = 40 C to +105 C.
Symbol
fSCL
Parameter
Conditions
Min
-
Typ
400
-
Max
Unit
kHz
k
SCL clock frequency
resistance on pin ADSEL
-
-
RADSEL
I2C-bus address
A[6:0] = 110 1100
155
I2C-bus address
A[6:0] = 110 1101
I2C-bus address
A[6:0] = 110 1111
42
7
51
10
-
57
15
0.5
k
k
k
legacy mode
-
Diagnostic
VOL(DIAG)
LOW-level output voltage on fault condition; IDIAG = 1 mA
pin DIAG
-
-
0.3
V
V
VO(offset_det)
THDclip
output voltage at offset
detection
1.5
1.75 2.2
total harmonic distortion clip
detection level
IB2[D7:D6] = 10
IB2[D7:D6] = 01
IB2[D7:D6] = 00
5
3
1
1
10
5
18
9
%
%
%
%
2
3
THDclip
total harmonic distortion clip
detection level variation
no overlap between IB2[D7:D6] =
10 and IB2[D7:D6] = 01
4
9
no overlap between IB2[D7:D6] =
01 and IB2[D7:D6] = 00
1
3.5
6
%
Tj(AV)(pwarn)
pre-warning average junction IB3[D4] = 0
135
112
150
145
122
155
155
132
160
C
C
C
temperature
IB3[D4] = 1
Tj(AV)(G(0.5dB))
average junction temperature Vi = 0.05 V
for 0.5 dB gain reduction
Tj(pw-G(0.5dB)) prewarning to 0.5 dB gain
reduction junction
7
10
15
20
13
20
-
C
C
dB
temperature difference
Tj(G(0.5dB)-of)
junction temperature
difference between 0.5 dB
gain reduction and off
from thermal foldback to when all
outputs are switched off
10
-
G(th_fold)
gain reduction of thermal
foldback
all channels switched off
Zth(load)
load detection threshold
impedance
I2C-bus mode
normal load detection
-
-
-
-
20
800
-
line driver load detection
100
5000
Zth(open)
open load detection threshold I2C-bus mode
impedance
Ith(o)det(load)AC
AC load detection output
threshold current
I2C-bus mode
AC load bit is set
AC load bit is not set
460
-
-
-
-
mA
mA
230
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
30 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
Table 17. Characteristics …continued
Refer to Figure 29 at VP = VP1 = VP2 = 14.4 V; RL = 4 ; f = 1 kHz; RS = 0 ; normal mode; unless otherwise specified.
Tested at Tamb = 25 C; guaranteed for Tamb = 40 C to +105 C.
Symbol
Amplifier
Po
Parameter
Conditions
Min
Typ
Max
Unit
output power
RL = 4 ; VP = 14.4 V;
THD = 0.5 %
19
26
42
22
28
44
-
-
-
W
W
W
RL = 4 ; VP = 14.4 V;
THD = 10 %
RL = 4 ; VP = 14.4 V; maximum
power; Vi = 2 V (RMS) square
wave
RL = 4 ; VP = 15.2 V; maximum
power; Vi = 2 V (RMS) square
wave
47
50
-
W
RL = 2 ; VP = 14.4 V;
THD = 0.5 %
34
45
70
37
48
75
-
-
-
W
W
W
RL = 2 ; VP = 14.4 V;
THD = 10 %
RL = 2 ; VP = 14.4 V; maximum
power; Vi = 2 V (RMS) square
wave
THD
total harmonic distortion
Po = 1 W to 12 W; f = 1 kHz;
-
0.01
0.1
%
RL = 4
Po = 1 W to 12 W; f = 10 kHz
Po = 1 W to 12 W; f = 20 kHz
-
-
-
0.09
0.14
0.02
0.3
%
%
%
0.4
line driver mode; Vo = 1 V (RMS)
and 5 V (RMS),
0.05
f = 20 Hz to 20 kHz; complex
load; see Figure 31
[5]
[5]
[5]
[5]
cs
channel separation
f = 1 kHz; RS = 1 k;
RACGND = 250
65
60
55
45
80
65
70
65
-
-
-
-
dB
dB
dB
dB
f = 10 kHz; RS = 1 k;
RACGND = 250
SVRR
CMRR
supply voltage ripple rejection 100 Hz to 10 kHz; RS = 1 k;
RACGND = 250
common mode rejection ratio normal mode; Vcm = 0.3 V (p-p);
f = 1 kHz to 3 kHz; RS = 1 k;
RACGND = 250
Vcm(max)(rms)
Vn(o)
maximum common mode
voltage (RMS value)
f = 1 kHz
-
-
0.6
V
output noise voltage
filter 20 Hz to 22 kHz; RS = 1 k
mute mode
-
-
-
19
22
45
26
29
65
V
V
V
line driver mode
normal mode
Gv
voltage gain
single-ended in; differential out
normal mode
25.5
15.5
26
16
26.5
16.5
dB
dB
line driver mode
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
31 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
Table 17. Characteristics …continued
Refer to Figure 29 at VP = VP1 = VP2 = 14.4 V; RL = 4 ; f = 1 kHz; RS = 0 ; normal mode; unless otherwise specified.
Tested at Tamb = 25 C; guaranteed for Tamb = 40 C to +105 C.
Symbol
Parameter
Conditions
Min
50
60
80
-
Typ
70
Max
95
95
-
Unit
k
k
dB
Zi
input impedance
Tamb = 40 C to +105 C
Tamb = 0 C to 105 C
Vo / Vo(mute); Vi = 50 mV
70
mute
mute attenuation
92
Vo(mute)(RMS)
RMS mute output voltage
Vi = 1 V (RMS);
25
-
V
filter 20 Hz to 22 kHz
Bp
power bandwidth
1 dB
-
20 to
-
Hz
20000
[1] Operation above 16 V in a 2 mode with reactive load can trigger the amplifier protection. The amplifier switches off and will restart
after 16 ms resulting in an ‘audio hole’.
[2]
VSTB depends on the current into the STB pin: minimum = (1429 ISTB) + 5.4 V, maximum = (3143 ISTB) + 5.6 V.
[3] The times are specified without leakage current. For a leakage current of 10 A on the SVR pin, the delta time is specified. If the
capacitor value on the SVR pin changes with 30 %, the specified time will also change with 30 %. The specified times include an
Equivalent Series Resistance (ESR) of 15 for the capacitor on the SVR pin.
[4] Standard I2C-bus specification: maximum LOW level = 0.3 VDD, minimum HIGH level = 0.7 VDD. To comply with 5 V and 3.3 V logic,
the maximal LOW level is defined by VDD = 5 V and the minimum HIGH level by VDD = 3.3 V.
RS
-----
[5] For optimum channel separation, supply voltage ripple rejection and common mode rejection ratio, a resistor RACGND
=
should
4
be in series with the ACGND capacitor.
12. Performance diagrams
001aad121
2
10
THD
(%)
10
1
(1)
−1
10
−2
10
10
(2)
(3)
−3
10
−2
−1
2
10
1
10
10
P
(W)
o
VP = 14.4 V; RL = 4 .
(1) f = 10 kHz.
(2) f = 1 kHz.
(3) f = 100 Hz.
Fig 17. Total harmonic distortion as a function of output power
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
32 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
001aad122
2
10
THD
(%)
10
1
(1)
−1
10
−2
10
10
(2)
(3)
−3
10
−2
−1
2
10
1
10
10
P
(W)
o
VP = 14.4 V; RL = 2 .
(1) f = 10 kHz.
(2) f = 1 kHz.
(3) f = 100 Hz.
Fig 18. Total harmonic distortion as a function of output power
001aad123
30
P
(W)
o
(1)
28
26
24
22
20
(2)
−2
−1
2
10
10
1
10
10
f (kHz)
VP = 14.4 V; RL = 4 .
(1) THD = 10 %.
(2) THD = 0.5 %.
Fig 19. Output power as a function of frequency
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
33 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
001aad124
60
P
o
(W)
(1)
(2)
50
40
30
10
−2
−1
2
10
1
10
10
f (kHz)
VP = 14.4 V; RL = 2 .
(1) THD = 10 %.
(2) THD = 0.5 %.
Fig 20. Output power as a function of frequency
001aad125
80
P
o
(W)
(1)
60
(2)
(3)
40
20
0
5
10
15
20
V
(V)
P
VP = 14.4 V; RL = 4 .
(1) Po(max)
.
(2) THD = 10 %.
(3) THD = 0.5 %.
Fig 21. Output power as a function of supply voltage
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
34 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
001aad126
120
P
(W)
o
(1)
80
(2)
(3)
40
0
5
10
15
20
V
(V)
P
VP = 14.4 V; RL = 2 .
(1) Po(max)
.
(2) THD = 10 %.
(3) THD = 0.5 %.
Fig 22. Output power as a function of supply voltage
001aad127
1
THD
(%)
−1
10
−2
10
(1)
(2)
−3
10
10
−2
−1
2
10
1
10
10
f (kHz)
VP = 14.4 V; RL = 4 .
(1) Po = 1 W.
(2) Po = 10 W.
Fig 23. Total harmonic distortion as a function of frequency; in normal mode
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
35 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
001aad128
−1
10
THD
(%)
(1)
(2)
−2
10
−3
10
10
−2
−1
2
10
1
10
10
f (kHz)
VP = 14.4 V; RL = 600 .
(1) Vo = 1 V.
(2) Vo = 5 V; front channels.
Fig 24. Total harmonic distortion as a function of frequency in line driver mode
001aad129
−40
SVRR
(dB)
−50
−60
−70
−80
−90
−2
−1
2
10
10
1
10
10
f (kHz)
VP = 14.4 V; RL = 4 ; RS = 1 k; Vripple = 2 V (p-p).
Fig 25. Supply voltage ripple rejection as a function of frequency
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
36 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
001aad130
90
α
cs
(dB)
80
70
60
50
−2
−1
2
10
10
1
10
10
f (kHz)
VP = 14.4 V; RL = 4 ; RS = 1 k; Po = 1 W.
Fig 26. Channel separation as a function of frequency
001aad730
50
P
(W)
40
30
20
10
0
0
10
20
30
40
P
(W)
o
VP = 14.4 V; RL = 4 ; f = 1 kHz.
Fig 27. Power dissipation as a function of output power
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
37 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
001aad731
100
P
(W)
80
60
40
20
0
0
20
40
60
80
P
(W)
o
VP = 14.4 V; RL = 2 ; f = 1 kHz.
Fig 28. Power dissipation as a function of output power
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
38 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
13. Application information
8.5 V
R
ADSEL
5 V
SDA SCL
V
V
(2)
ADSEL
P1
21
P2
7
1
26
23
10 kΩ
10 kΩ
5
DIAG
2
STB 2
STANDBY/
FAST MUTE
I C-BUS
CLIP DETECT/DIAGNOSTIC
INTERFACE
470 nF
470 nF
470 nF
470 nF
R
S
R
S
R
S
R
S
10 OUT1+
OUT1−
MUTE
IN1 12
26 dB/
16 dB
8
(1)
1.8 nF
PROTECTION/
DIAGNOSTIC
18 OUT3+
MUTE
IN3 16
26 dB/
16 dB
20 OUT3−
(1)
1.8 nF
PROTECTION/
DIAGNOSTIC
6
4
OUT2+
MUTE
IN2 13
26 dB/
16 dB
OUT2−
(1)
1.8 nF
PROTECTION/
DIAGNOSTIC
22 OUT4+
IN4 15
MUTE
26 dB/
16 dB
24 OUT4−
(1)
V
P
1.8 nF
PROTECTION/
DIAGNOSTIC
27 TAB
TDA8594
11
14
17
9
3
19
25
PGND4
PGND1 PGND2 PGND3
SVR
SGND
ACGND
(2)
(3)
22 μF
2.2 μF
001aad132
For EMC reasons, a 10 nF capacitor (not shown) can be added from each amplifier output to ground.
(1) For EMC reasons a capacitor of 1.8 nF from the input pin to SGND is advised (optional).
(2) The SVR and ACGND capacitors and the RADSEL resistor should first be connected to SGND before connecting to PGNDn
pins.
(3) ACGND capacitor value must be close to 4 input capacitor value; 4 470 nF capacitors can be used as an alternative to the
2.2 F capacitor shown.
Fig 29. Test and application diagram
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
39 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
ACGND
17
TDA8594
1 μF
0.22 μF
1.7 kΩ
MICRO-
PROCESSOR
47 pF
100 Ω
001aad133
Fig 30. Beep input circuit (gain = 0 dB) to apply a microprocessor beep signal to all four
amplifiers
positive output
180 pF
a)
47 kΩ
negative output
3.9 nF
3.9 nF
47 kΩ
positive output
negative output
180 pF
200 Ω
b)
3.9 nF
3.9 nF
001aad134
Fig 31. Complex loads for measuring THD in line driver mode
8.5 V
5.6 kΩ
4.7 kΩ
18 kΩ
10 kΩ
3.3 V
MICRO-
STB
2
TDA8594
PROCESSOR
switch
001aad131
Fig 32. Circuit for combined mode selection and clip detection functions on pin STB
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
40 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
13.1 PCB layout
top
001aad162
Fig 33. PCB layout of test and application circuit; copper layer top
b o t
001aad163
Fig 34. PCB layout of test and application circuit; copper layer bottom (top view)
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
41 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
Sense
TDA8594/TDA8595
GND
top
V
P
address
select
1 μF
2200 μF
+
D8 (00)
12C
supply
Philips Semiconductors
10 μF
DA (01)
DE (11)
clip 2
+
+
2.2 μF
2.2 μF
+
+
mode on
D1
470 nF
470 nF
diag s. by
12C
on
Mute
off
SCL
GND
+ 5V
SDA
− 4 +
− 3 +
+ 1 −
+ 2 −
GND
V
P
OUT
OUT
SGND
IN
10 kΩ
Legacy
3
4
2
1
DZ 8.2 V
001aad164
Fig 35. PCB layout of test and application circuit; components top
b o t
220 nF
220 nF
BC859
10 kΩ
12 kΩ
TDA3664
2 kΩ
10 kΩ
4 × 470 nF
51 kΩ
250
Ω
4.7 kΩ
470 nF
470 nF
18 kΩ
22 kΩ
001aad165
Fig 36. PCB layout of test and application circuit; components bottom (top view)
14. Test information
14.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q100 - Failure mechanism based stress test qualification for integrated
circuits, and is suitable for use in automotive applications.
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
42 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
15. Package outline
DBS27P: plastic DIL-bent-SIL (special bent) power package; 27 leads (lead length 6.8 mm)
SOT827-1
non-concave
x
D
h
D
E
h
view B: mounting base side
A
d
2
B
j
E
A
L
4
L
3
L
L
2
1
Z
27
e
c
w
v
1
Q
b
p
e
e
2
m
0
10
20 mm
(1)
x
Z
scale
1.8
0.03
1.2
w
Dimensions (mm are the original dimensions)
(1)
(1)
Unit
A
A
2
b
c
D
d
D
E
e
2
e
e
E
j
L
L
L
L
4
m
4
Q
v
p
h
1
2
h
2
3
max
4.6 0.60 0.5 29.2 24.8
15.9
3.55
3.40 6.8
3.25
3.9 1.15 22.9
3.1 0.85 22.1
2.1
0.25
mm nom 19
min
12
1
4
8
0.6
4.4 0.45 0.3 28.8 24.4
15.5
1.8
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
sot827-1_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
13-02-13
13-05-30
SOT827-1
Fig 37. Package outline SOT827-1 (DBS27P)
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
43 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
RDBS27P: plastic rectangular-DIL-bent-SIL (reverse bent) power package; 27 leads (row spacing 2.54 mm)
SOT878-1
non-concave
D
h
x
D
E
h
view B: mounting base side
d
A
2
B
j
E
A
L
1
Z
27
c
e
2
e
1
Q
v
e
w
L
1
b
p
0
10
scale
20 mm
Dimensions (mm are the original dimensions)
(1)
(1)
(1)
Unit
A
A
2
b
c
D
d
D
E
e
2
e
e
E
j
L
L
Q
v
w
x
Z
p
h
1
2
h
1
max
4.6 0.60 0.5 29.2 24.8
15.9
3.55 3.75 3.75 2.1
3.40
3.25 3.15 3.15 1.8
1.8
1.2
mm nom 13.5
min
12
1
2.54
8
0.6 0.25 0.03
4.4 0.45 0.3 28.8 24.4
15.5
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
sot878-1_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
12-12-19
13-02-13
SOT878-1
Fig 38. Package outline SOT878-1 (RDBS27P)
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
44 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
16. Mounting
2
1
27
1
2.54
26
2
M
hole diameter min. 0.92
∅ 0.08
Dimensions in mm
sot878-1_fr
Dimensions in mm.
Reflow soldering is the recommended soldering method.
Dimension ‘1’ relates to dimension ‘e1’ in Figure 38; dimension ‘2’ relates to dimension ‘e2’ in
Figure 38.
Fig 39. SOT878-1 reflow soldering footprint
17. Abbreviations
Table 18. Abbreviations
Acronym
ACK
Description
ACKnowledge not
BCDMOS
BTL
Bipolar CMOS/DMOS
Bridge Tied Load
CMOS
DMOS
DSP
Complementary Metal-Oxide Semiconductor
Double-diffused Metal-Oxide Semiconductor
Digital Signal Processor
EMC
ElectroMagnetic Compatibility
Equivalent Series Resistance
Least Significant Bit
ESR
LSB
MSB
Most Significant Bit
NMOS
PMOS
PCB
Negative-channel Metal-Oxide Semiconductor
Positive-channel Metal-Oxide Semiconductor
Printed-Circuit Board
POR
Power-On Reset
SOAR
SOI
Safe Operating ARea
Silicon On Insulator
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
45 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
18. Revision history
Table 19. Revision history
Document ID
TDA8594 v.5
Modifications:
TDA8594 v.4
Modifications:
TDA8594 v.3
Modifications:
TDA8594_2
Release date
20130611
Data sheet status
Change notice
Supersedes
Product data sheet
-
TDA8594_4
• The package outline Figure 37 has been updated.
20130226 Product data sheet
• The data sheet template has been updated to the latest version.
20130221 Product data sheet
-
TDA8594_3
TDA8594_2
-
• The package outline figures, Figure 37 and Figure 38, have been updated.
20071211 Product data sheet TDA8594_1
-
Modifications:
• The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Section 2.1 and Section 14: Added device qualification “AEC-Q100 qualification”.
• Figure 1 and Figure 29: Changed internal circuit on pin SVR.
• Figure 32: Value of base-emitter resistor changed to 5.6 k.
• Table 17, Diagnostic:
–
Symbols and parameters of “junction temperature” characteristics updated (4).
–
(Old) symbol and parameter “IoM = peak current output” changed to “Ith(o)det(load)AC
AC load detection output threshold current”.
=
TDA8594_1
20060302
Product data sheet
-
-
(9397 750 15066)
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
46 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
19. Legal information
19.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
19.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
19.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
47 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
I2C-bus — logo is a trademark of NXP B.V.
20. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
TDA8594
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 11 June 2013
48 of 49
TDA8594
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
21. Contents
1
General description. . . . . . . . . . . . . . . . . . . . . . 1
18
Revision history . . . . . . . . . . . . . . . . . . . . . . . 46
2
2.1
2.2
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
I2C-bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . 1
19
Legal information . . . . . . . . . . . . . . . . . . . . . . 47
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 47
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 48
19.1
19.2
19.3
19.4
3
4
5
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
20
21
Contact information . . . . . . . . . . . . . . . . . . . . 48
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
Functional description . . . . . . . . . . . . . . . . . . . 5
Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Distortion (clip) detection . . . . . . . . . . . . . . . . . 6
Output protection and short-circuit operation . . 6
SOAR protection. . . . . . . . . . . . . . . . . . . . . . . . 6
Speaker protection . . . . . . . . . . . . . . . . . . . . . . 6
Standby and mute operation. . . . . . . . . . . . . . . 7
Legacy mode (pin ADSEL connected to
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.7.1
ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
I2C-bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Start-up and shut-down sequence . . . . . . . . . . 7
Power-on reset and supply voltage spikes . . . 11
Engine start and low voltage operation. . . . . . 11
Overvoltage and load dump protection. . . . . . 14
Thermal pre-warning and thermal protection . 14
Diagnostics. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Offset detection. . . . . . . . . . . . . . . . . . . . . . . . 16
DC load detection. . . . . . . . . . . . . . . . . . . . . . 16
AC load detection . . . . . . . . . . . . . . . . . . . . . . 17
I2C-bus diagnostic readout . . . . . . . . . . . . . . . 18
7.7.2
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
8
8.1
8.2
I2C-bus specification . . . . . . . . . . . . . . . . . . . . 19
Instruction bytes . . . . . . . . . . . . . . . . . . . . . . . 20
Data bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 26
Thermal characteristics . . . . . . . . . . . . . . . . . 27
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 27
Performance diagrams . . . . . . . . . . . . . . . . . . 32
Application information. . . . . . . . . . . . . . . . . . 39
PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Test information. . . . . . . . . . . . . . . . . . . . . . . . 42
Quality information . . . . . . . . . . . . . . . . . . . . . 42
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 43
Mounting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 45
10
11
12
13
13.1
14
14.1
15
16
17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 11 June 2013
Document identifier: TDA8594
相关型号：
©2020 ICPDF网 联系我们和版权申明