TDA8760 [NXP]
10-bit high-speed analog-to-digital converter; 10位高速模拟 - 数字转换器型号: | TDA8760 |
厂家: | NXP |
描述: | 10-bit high-speed analog-to-digital converter |
文件: | 总28页 (文件大小:199K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA8760
10-bit high-speed analog-to-digital
converter
1996 Sep 12
Product specification
Supersedes data of April 1994
File under Integrated Circuits, IC02
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
FEATURES
APPLICATIONS
• 10-bit resolution
• High-speed analog-to-digital conversion for
– Video signal digitizing
• Sampling rate up to 40 MHz
• Total Harmonic Distortion (THD): −65 dB at 4.43 MHz
full-scale and a 40 MHz clock frequency
– High Definition TV (HDTV)
– Digital video broadcasting (satellite and cable)
– Transient signal analysis
• High signal-to-noise ratio over a large analog input
frequency range (8.8 effective bits at 10 MHz full-scale
input at a 40 MHz clock frequency)
– High energy physics research
– Sigma-delta (SD) modulators
– Medical imaging
• +5 V power supplies
• Binary or two’s complement 3-state TTL outputs
• In-range 3-state TTL output
– Radar pulse digitizing.
• TTL compatible digital inputs
GENERAL DESCRIPTION
• LOW-level AC clock input signal allowed
• Power dissipation 850 mW (typical)
The TDA8760 is a monolithic bipolar 10-bit
Analog-to-Digital Converter (ADC) for video or other
applications. It converts the analog input signal into 10-bit
binary coded digital words at a maximum sampling rate of
40 MHz. All digital inputs and outputs are TTL compatible.
However, a sine wave clock input signal is allowed.
• Low analog input capacitance (typ. 4.5 pF), no buffer
amplifier required
• No external sample-and-hold circuit required
• Analog Input; single or differential
• External amplitude range control
• Voltage controlled regulator included.
1996 Sep 12
2
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
QUICK REFERENCE DATA
SYMBOL
PARAMETER
analog supply voltage
CONDITIONS
MIN.
4.75
TYP.
5.0
MAX.
5.25
UNIT
VCCA
VCCD
VCCO
ICCA
ICCD
ICCO
ILE
V
V
V
digital supply voltage
output supply voltage
analog supply current
digital supply current
4.75
5.0
5.0
95
5.25
5.25
100
45
4.75
−
mA
−
40
mA
output supply current
DC integral linearity error
DC differential linearity error
AC integral linearity error
−
35
40
mA
f
f
f
clk = 4 MHz
−
±1.0
±0.6
±1.2
±2.0
±1.0
±2.0
LSB
LSB
LSB
DLE
AILE
clk = 4 MHz
−
clk = 40 MHz;
−
fi = 4.43 MHz
fclk(max)
maximum clock frequency
TDA8760K/2
20
40
−
−
−
MHz
MHz
mW
°C
TDA8760K/4
−
−
Ptot
total power dissipation
operating ambient temperature
850
−
970
+70
Tamb
0
ORDERING INFORMATION
TYPE
PACKAGE
SAMPLING
FREQUENCY
(MHz)
NUMBER
NAME
DESCRIPTION
VERSION
TDA8760K/2
PLCC44
20
40
plastic leaded chip carrier; 44 leads
SOT187-2
TDA8760K/4
1996 Sep 12
3
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V
V
V
V
V
V
V
refH
refL
CCA1
7
CCA2
13
CCA3
17
CCD1
3
CCD2
21
CLK
2
CLK
1
15 14
24
30
37
44
OGND1
output ground
AMP
OGND2
output ground
TDA8760
10
11
V
V
I
AMP
OGND3
output ground
I
SAMPLE
AND
HOLD
OGND4
output ground
COARSE
ADC
FINE
DAC
FINE
ADC
42
43
V
V
CCO3
CCO4
data outputs
27
29
31
32
33
34
35
36
40
41
D9 (MSB)
D8
D7
D6
D5
D4
ERROR
CORECTION
TTL
OUTPUTS
D3
D2
D1
D0 (LSB)
26
IR
8
9
12
16
4
20
22 23 28 25
MBD222 - 2
V
OTC
V
CCO1
CCO2
AGND1 AGND2 AGND3 AGND4
analog ground
DGND1 DGND2
digital ground
CS
Fig.1 Block diagram for SO187 package.
ahdnbok,uflapegwidt
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
PINNING
SYMBOL
CLK
PIN
DESCRIPTION
1
clock input
CLK
2
complementary clock input
digital supply voltage (+5 V)
digital ground
VCCD1
DGND1
n.c.
3
4
5
not connected
n.c.
6
not connected
VCCA1
AGND1
AGND2
VI
7
analog supply voltage (+5 V)
analog ground
8
9
analog ground
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
analog input voltage
VI
complementary analog input voltage
analog ground
AGND3
VCCA2
VrefL
VrefH
AGND4
VCCA3
n.c.
analog supply voltage (+5 V)
reference voltage LOW
reference voltage HIGH
analog ground
analog supply voltage (+5 V)
not connected
n.c.
not connected
DGND2
VCCD2
CS
digital ground
digital supply voltage (+5 V)
chip select input (TTL level input; active HIGH)
output two’s complement
output ground
OTC
OGND1
VCCO1
IR
output supply voltage (+5 V)
in-range output
D9
data output, bit 9 (MSB)
output supply voltage (+5 V)
data output, bit 8
VCCO2
D8
OGND2
D7
output ground
data output, bit 7
D6
data output, bit 6
D5
data output, bit 5
D4
data output, bit 4
D3
data output, bit 3
D2
data output, bit 2
OGND3
n.c.
output ground
not connected
n.c.
not connected
D1
data output, bit 1
1996 Sep 12
5
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
SYMBOL
PIN
DESCRIPTION
D0
41
42
43
44
data output, bit 0 (LSB)
output supply voltage (+5 V)
output supply voltage (+5 V)
output ground
VCCO3
VCCO4
OGND4
V
n.c.
7
8
9
39
CCA1
38 n.c.
AGND1
AGND2
37 OGND3
V
I
36
10
11
12
13
14
15
16
17
D2
V
I
35 D3
AGND3
TDA8760
34
D4
V
33 D5
CCA2
V
D6
D7
32
31
30
refL
V
refH
OGND2
AGND4
V
29 D8
CCA3
MGA928-1
Fig.2 Pin configuration for SOT187-2.
1996 Sep 12
6
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VCCA
PARAMETER
analog supply voltage
CONDITIONS
MIN.
−0.3
MAX.
+7.0
UNIT
V
V
V
V
VCCD
VCCO
∆VCC1
digital supply voltage
output supply voltage
−0.3
−0.3
−0.5
+7.0
+7.0
+0.5
supply voltage difference between
VCCA and VCCD
∆VCC2
∆VCC3
supply voltage difference between
VCCO and VCCD
−0.5
−0.5
+0.5
0.5
V
V
supply voltage difference between
VCCA and VCCO
VI
input voltage
referenced to AGND
0.3
VCCA
VCCD
V
V
VI(p-p)
input voltage for differential clock
drive (peak-to-peak value)
−
IO
output current
−
10
mA
°C
°C
°C
Tstg
Tamb
Tj
storage temperature
operating ambient temperature
junction temperature
−55
0
+150
+70
+150
−
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
PARAMETER
Thermal resistance from junction to ambient in free air
TDA8760K/4
THERMAL RESISTANCE
35 K/W
46 K/W
TDA8760K/2
1996 Sep 12
7
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
CHARACTERISTICS
V
CCA = VCCD = VCCO = 4.75 to 5.25 V; AGND and DGND shorted together;
CCA − VCCD = VCCO − VCCD = VCCA − VCCO = −0.25 to +0.25 V; Tamb = 0 to +70 °C; unless otherwise specified.
V
Typical values measured at VCCA = VCCD = VCCO = 5 V; Tamb = 25 °C.
SYMBOL
Supplies
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VCCA
VCCD
VCCO
ICCA
analog supply voltage
digital supply voltage
output supply voltage
analog supply current
digital supply current
output supply current
4.75
5.0
5.25
V
V
V
4.75
4.75
−
5.0
5.0
95
5.25
5.25
100
45
mA
mA
mA
ICCD
−
40
ICCO
all outputs LOW
−
35
40
Inputs
CLK AND CLK (REFERENCED TO DGND); note 1
VIL
VIH
IIL
LOW level input voltage
HIGH level input voltage
LOW level input current
HIGH level input current
0
−
0.8
VCCD
−
V
2.0
−400
−
−
V
Vclk or Vclk = 0.4 V
Vclk or Vclk = 2.0 V
Vclk or Vclk = VCCD
fclk = 40 MHz
−
mA
mA
mA
kΩ
pF
V
IIH
−
100
300
−
−
−
ZI
input impedance
input capacitance
−
2
CI
fclk = 40 MHz
−
4.5
−
−
∆Vclk
AC input voltage for
switching (Vclk − Vclk)
DC level = 1.5 V
DC level = 2.5 V
0.5
1.5
2.0
5.0
−
V
OTC AND CS (REFERENCED TO DGND); see Table 3
VIL
VIH
IIL
LOW level input voltage
HIGH level input voltage
LOW level input current
HIGH level input current
0
−
−
−
−
0.8
VCCD
−
V
2.0
−400
−
V
VIL = 0.8 V
VIH = 2.0 V
µA
µA
IIH
20
1996 Sep 12
8
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VI AND VI (REFERENCED TO AGND); see also Tables 1 and 2
IIL
LOW level input current
HIGH level input current
input impedance
V
refH − VrefL = 1.5 V
refH − VrefL = 1.5 V
−
−
−
−
7
−
−
−
−
µA
IIH
V
22
2
µA
kΩ
pF
ZI
fi = 4.43 MHz
fi = 4.43 MHz
CI
input capacitance
4.5
VIoffset(d)
input offset voltage
differential mode; VI = VI;
output code 511; Table 1
V
V
CCA = 5 V
3.3
3.2
3.3
3.4
−
3.6
V
V
V
CCA = 4.75 V
3.45
3.8
VCCA = 5.25 V
−
VIoffset(s)
input offset voltage
single mode; VI = VIoffset(s)
;
output code 511; Table 2
VCCA = 5 V
3.6
3.5
3.6
3.7
−
3.8
V
V
V
V
CCA = 4.75 V
3.65
4.0
VCCA = 5.25 V
−
Voltage controlled regulator inputs VrefH and VrefL (referenced to AGND); differential input
VrefH
VrefL
reference voltage HIGH
reference voltage LOW
4.0
2.5
1.4
4.5
3.0
1.5
VCCA
3.5
V
V
V
VI(p-p)
input voltage amplitude
(peak-to-peak value)
1.6
IrefH
IrefL
input current at VrefH
input current at VrefL
−
−
10
10
−
−
µA
µA
Voltage controlled regulator inputs VrefH and VrefL (referenced to AGND); single input
VrefH
VrefL
reference voltage HIGH
reference voltage LOW
4.0
2.5
1.3
4.4
3.0
1.4
VCCA
3.5
V
V
V
VI(p-p)
input voltage amplitude
(peak-to-peak value)
1.5
IrefH
IrefL
input current at VrefH
input current at VrefL
−
−
10
10
−
−
µA
µA
Outputs (referenced to DGND)
DIGITAL OUTPUTS D9 TO D0 AND IR (REFERENCED TO DGND)
VOL
VOH
IO
LOW level output voltage
HIGH level output voltage
IO = 2 mA
0
−
−
−
0.4
V
IO = −0.4 mA
0.4 V < VO < VCCO
2.4
−20
VCCD
+20
V
output current in 3-state
mode
µA
1996 Sep 12
9
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Switching characteristics
CLOCK FREQUENCY fclk (note 1; see Fig.3)
fclk(min)
fclk(max)
minimum clock frequency
maximum clock frequency
TDA8760K/4
−
−
1
MHz
40
20
10
8
−
−
−
−
−
−
−
−
MHz
MHz
ns
TDA8760K/2
tCPH
tCPL
clock pulse width HIGH
clock pulse width LOW
note 7
ns
Analog signal processing in differential input mode; see Table 1; 50% clock duty factor;
I(p-p) = VrefH − VrefL = 1.5 V
V
LINEARITY
ILE
DC integral linearity error
DC differential linearity error
AC integral linearity error
offset error
fclk = 4 MHz
clk = 4 MHz
note 3
−
−
−
±1.0
±0.6
±1.2
−
±2.0
±1.0
±2.0
+3
LSB
LSB
LSB
LSB
DLE
AILE
OFE
f
VCCA = VCCD = VCCO = 5 V; −3
VI = VI; Tamb = 25 °C;
output code = 511
GE
gain error; amplitude spread
between devices
V
T
V
CCA = VCCD = VCCO = 5 V; −10
amb = 25 °C;
refH − VrefL = 1.5 V
−
+10
LSB
BANDWIDTH (fclk = 40 MHZ); note 9
Analog bandwidth
B
−1 dB
−3 dB
−
−
140
220
−
−
MHz
MHz
HARMONICS (fclk = 40 MHZ); see Figs 6, 8 and 9
f1
fundamental harmonics
(full scale)
fi = 4.43 MHz
−
−
0
dB
fall
harmonics (full scale);
all components
fi = 4.43 MHz
second harmonics
third harmonics
−
−
−
−70
−70
−65
−63
−63
−60
dB
dB
dB
THD
total harmonic distortion
fi = 4.43 MHz; note 2
SIGNAL-TO-NOISE RATIO; notes 4 and 5; see Figs 6, 8 and 9
SNR
signal-to-noise ratio
without harmonics;
clk = 40 MHz;
54
56
−
dB
f
fi = 4.43 MHz; Tamb = 25 °C
1996 Sep 12
10
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
EFFECTIVE BITS; notes 4 and 5; see Figs 6, 8 and 9
EB
effective bits
TDA8760K/2 (fclk = 20 MHz)
fi = 4.43 MHz
−
−
−
−
−
8.90
−
−
−
−
−
bits
fi = 7.5 MHz
fi = 4.43 MHz
fi = 10 MHz
fi = 15 MHz
8.70
8.80
8.80
8.70
bits
bits
bits
bits
effective bits
TDA8760K/4 (fclk = 40 MHz)
TWO-TONE
Two-tone two-tone intermodulation
rejection
fclk = 40 MHz; note 8
−
−
−65
−
−
dB
BIT ERROR RATE
BER
bit error rate
fclk = 40 MHz;
2 × 10−12
times/
fi = 4.43 MHz; VI = ±16 LSB
at code 512
samples
DIFFERENTIAL GAIN; SEE Fig.5
Gdiff
differential gain
fclk = 20 MHz; fi = 4.43 MHz
−
−
0.5
1.0
−
−
%
%
f
clk = 40 MHz; fi = 4.43 MHz
DIFFERENTIAL PHASE
Φdiff
differential phase
fclk = 40 MHz; fi = 4.43 MHz
−
0.1
0.2
deg
Analog signal processing in single input mode; see Table 2; 50% clock duty factor; VI(p-p) = VrefH − VrefL = 1.4 V
LINEARITY
ILE
DC integral linearity error
fclk = 4 MHz
−
−
−
±1.0
±0.6
±1.2
±2.0
±1.0
±2.0
LSB
LSB
LSB
DLE
AILE
DC differential linearity error fclk = 4 MHz
AC integral linearity error
note 3
BANDWIDTH (fclk = 40 MHZ); note 9
Analog bandwidth
B
−1 dB
−3 dB
−
−
140
220
−
−
MHz
MHz
HARMONICS (fclk = 40 MHZ); see Fig.7
f1
fundamental harmonics
(full scale)
fi = 4.43 MHz
fi = 4.43 MHz
−
−
0
dB
fall
harmonics (full scale);
all components
second harmonics
third harmonics
−
−
−
−61
−62
−59
−
−
−
dB
dB
dB
THD
total harmonic distortion
fi = 4.43 MHz; note 2
1996 Sep 12
11
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
SIGNAL-TO-NOISE RATIO; notes 4 and 5; see Fig.7
SNR
signal-to-noise ratio
without harmonics;
fclk = 40 MHz;
54
56
−
dB
fi = 4.43 MHz; Tamb = 25 °C
EFFECTIVE BITS; notes 4 and 5; see Fig.7
EB
effective bits
TDA8760K/2 (fclk = 20 MHz)
fi = 4.43 MHz
fi = 7.5 MHz
fi = 4.43 MHz
fi = 10 MHz
−
−
−
−
8.70
8.50
8.50
8.20
−
−
−
−
bits
bits
bits
bits
effective bits
TDA8760K/4 (fclk = 40 MHz)
TWO-TONE
Two-tone two-tone intermodulation
rejection
fclk = 40 MHz; note 8
−
−
−60
−
−
dB
BIT ERROR RATE
BER
bit error rate
fclk = 40 MHz;
2 × 10−12
times/
fi = 4.43 MHz; VI = ±16 LSB
at code 512
samples
DIFFERENTIAL GAIN; see Fig.5
Gdiff
differential gain
fclk = 20 MHz; fi = 4.43 MHz
−
−
0.5
1.0
−
−
%
%
f
clk = 40 MHz; fi = 4.43 MHz
DIFFERENTIAL PHASE
Φdiff
differential phase
fclk = 40 MHz; fi = 4.43 MHz
−
0.1
0.2
deg
Timing (note 6; see Fig.3; CL = 15 pF)
tds
th
sampling delay time
output hold time
−
8
−
−
2
ns
ns
ns
−
−
td
output delay time
12
16
3-state output delay times (see Fig.4)
tdZH
tdZL
tdHZ
tdLZ
enable HIGH
enable LOW
disable HIGH
disable LOW
−
−
−
−
12
12
8
16
16
12
20
ns
ns
ns
ns
16
1996 Sep 12
12
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
Notes
1. The circuit has two clock inputs: CLK and CLK. There are three modes of operation:
a) TTL mode 1:
CLK input is at TTL level with a threshold voltage of 1.5 V and sampling is taken on the falling edge of the clock
input signal. CLK decoupled to DGND via a 100 nF capacitor.
b) TTL mode 2:
CLK input is at TTL level with threshold voltage of 1.5 V and sampling is taken on the rising edge of the clock
input signal. CLK decoupled to DGND via a 100 nF capacitor.
c) TTL mode 3:
CLK and CLK inputs are at differential TTL levels.
d) AC driving modes:
When driving the CLK input directly and with any AC signal of minimum 0.5 V (p-p) and with a DC level of 1.5 V,
the sampling takes place at the falling edge of the clock signal.
When driving the CLK input with the same signal, sampling takes place at the rising edge of the clock signal.It is
recommended to decouple the CLK or CLK input to DGND via a 100 nF capacitor.
2. THD (total harmonic distortion) is obtained with the addition of the first five harmonics:
F
a) THD = 20 log---------------------------------------------------------------------------------------------------------------
2
2
2
2
2
(2nd) + (3rd) + (4th) + (5th) + (6th)
b) F being the fundamental harmonic referenced at 0 dB for a full-scale sine wave input.
3. AC linearity: full-scale differential sine wave (fi = 4.43 MHz; fclk = 40 MHz).
4. Effective bits with differential input and single input are respectively executed with full scale differential input and
full-scale single sine wave.
5. Effective bits are obtained via a Fast Fourier Transformer (FFT) treatment taking 8K acquisition points per period.
The calculation takes into account all harmonics and noise up to half of the clock frequency (NYQUIST frequency).
Conversion to SNR: SNR = EB × 6.02 + 1.76 dB.
6. Output data acquisition: the output data is available after the maximum delay of td.
7. tCPH of 9 ns (minimum) can be applied at the penalty of 0.5 effective bit drop compared to typical values.
8. Intermodulation measured relative to either tone with analog input frequencies of 4.43 MHz and 4.53 MHz. The two
input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter.
9. The −3 dB (or −1 dB) analog bandwidth is determined by the 3 dB (or 1 dB) reduction in the reconstructed output,
the input being a full-scale sine wave.
1996 Sep 12
13
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
Table 1 Output coding with differential inputs (typical values to AGND); VI(p-p) = VrefH − VrefL = 1.5 V
TWO’S COMPLEMENT
BINARY OUTPUTS
D9 TO D0
OUTPUTS
CODE
VI(p-p)
VI(p-p)
IR
D9 TO D0
underflow
<3.025
3.025
−
>3.775
3.775
−
0
1
1
•
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 1
• • • • • • • • • •
1 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 1
• • • • • • • • • •
0
1
•
−
−
511
3.40
−
3.40
−
1
•
0 1 1 1 1 1 1 1 1 1
• • • • • • • • • •
1 1 1 1 1 1 1 1 1 1
• • • • • • • • • •
•
1022
1023
overflow
−
−
1
1
0
1 1 1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1 0
0 1 1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1
3.775
>3.775
3.025
<3.025
Table 2 Output coding with single inputs (typical values to AGND); VI(p-p) = VrefH − VrefL = 1.4 V; VI(p-p) = 3.7 V
TWO’S COMPLEMENT
BINARY OUTPUTS
OUTPUTS
CODE
VI(p-p)
IR
D9 TO D0
D9 TO D0
underflow
<3.0
3.0
−
0
1
1
•
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 1
• • • • • • • • • •
1 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 1
• • • • • • • • • •
0
1
•
−
511
3.7
−
1
•
0 1 1 1 1 1 1 1 1 1
• • • • • • • • • •
1 1 1 1 1 1 1 1 1 1
• • • • • • • • • •
•
1022
1023
overflow
−
1
1
0
1 1 1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1 0
0 1 1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1
4.4
>4.4
Table 3 Mode selection.
OTC
1
CS
1
D0 TO D9 AND IR
binary; active
0
X(1)
1
two’s complement; active
high impedance
0
Note
1. Where: X = don’t care.
1996 Sep 12
14
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
t
CPL
t
CPH
1.4 V
CLK
sample N
sample N + 1
sample N + 2
V
l
t
t
dS
HD
2.4 V
1.4 V
0.4 V
DATA
D0 to D7
DATA
N - 2
DATA
N - 1
DATA
N
DATA
N + 1
t
d
MBD721
Fig.3 Timing diagram.
V
CCD
f
CS
50 %
dZH
t
t
dHZ
HIGH
90 %
output
data
50 %
LOW
t
t
dZL
dLZ
HIGH
output
data
50 %
LOW
TEST
S1
VCCD
VCCD
GND
GND
10 %
tdLZ
V
tdZL
tdHZ
tdZH
CCD
3.3 kΩ
15 pF
S1
TDA8760
CS
MBD723
CS = 100 kHz.
Fig.4 Timing diagram and test conditions of 3-state output delay time.
15
1996 Sep 12
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
digital output
CODE 1023
V4
f
= 4.43 MHz
i
V
i
(1)
f
= 4.43 MHz
i
V3
V2
V1
V0
(1)
f
= 4.43 MHz
i
(1)
f
= 4.43 MHz
i
(1)
f
= 4.43 MHz
i
(1)
DC offset voltage
CODE 0
MBD722
(1) Full-scale divided-by-5.
V
n (1 to 4) – V0
Gdiff = maximum of ------------------------------------------ × 100%
V0
Fig.5 Differential gain measurement conditions.
MBD223 - 1
MGA931 - 2
9.0
9.0
f
= 20 MHz
effective
bits
clk
effective
bits
f
= 20 MHz
40 MHz
clk
40 MHz
8.8
8.6
8.4
8.2
8.0
8.8
8.6
8.4
8.2
8.0
0
2
4
6
8
10
(MHz)
0
4
8
12
16
f
20
(MHz)
f
i
i
Fig.6 Typical effective bits under differential input
mode as a function of input signal
frequency.
Fig.7 Typical effective bits under single input
mode as a function of input signal
frequency.
1996 Sep 12
16
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
MRC299
0
amplitude
(dB)
–20.2
–40.4
–60.6
–80.8
–101
–121
0
1.25
2.50
3.75
5.00
6.25
7.50
8.75
10.0
f (MHz)
Effective bits: 9.1; THD = −65.81 dB;
Harmonic levels (dB): 2nd = −75.54; 3rd = −76.29; 4th = −74.90; 5th = −67.50; 6th = −90.87.
Fig.8 Fast Fourier Transformer (fclk = 20 MHz; fi = 4.43 MHz); for differential input mode.
MBD220
0
amplitude
(dB)
–20
–40
–60
–80
–100
–120
0
2.5
5
7.5
10
12.5
15
17.5
20
f (MHz)
Effective bits: 8.92; THD = −65.86 dB;
Harmonic levels (dB): 2nd = −70.92; 3rd = −68.48; 4th = −75.32; 5th = − 81.40; 6th = −72.69.
Fig.9 Fast Fourier Transformer (fclk = 40 MHz; fi = 4.43 MHz); for differential input mode.
17
1996 Sep 12
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
INTERNAL PIN CONFIGURATION
V
V
V
V
V
CCA1 CCA2 CCA3
CCD1 CCD2
CLK
1
CLK
2
7
13
17
3
21
V
CCD
V
CCA
V
and
I
10 and 11
V
I
30
kΩ
30
kΩ
AGND
1.5 V
V
CCA
DGND
14
15
V
V
refL
refH
25 and 43
V
/
CCO1
V
CCO4
AGND
V
CCO3
20
kΩ
31 to 36,
40 and 41
CS
and
22 and 23
1.5 V
data output
bit 7 to 0
OTC
30 and 37
OGND2 /
OGND3
TDA8760
DGND
12
8
9
16
4
20
MGA978
AGND1 AGND2 AGND3 AGND4 DGND1 DGND2
analog ground digital ground
Fig.10 Description of input and output circuitry.
1996 Sep 12
18
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
APPLICATION INFORMATION
100 nF
100 nF
(1)
CLK
5 V
5 V
100 nF
differential
analog inputs
IN
IN
D0 (LSB)
D1
100 nF
6
5
4
3
2
1 44 43 42 41 40
4.7
µ
F
4.7 µF
7
39
38
37
36
35
34
33
32
31
30
29
8
9
IN
IN
10
11
12
13
14
15
16
17
D2
D3
D4
D5
D6
D7
TDA8760
100 nF
100 nF
(2)
(2) (2)
R2 R3
(2)
R1
R4
D8
(3)
(3)
18 19 20 21 22 23 24 25 26 27 28
100
nF
100
nF
D9 (MSB)
5 V
100 nF
3 V 4.5 V
100 nF
100 nF
5 V
5 V
output format select
chip select input
MGA979
The analog, digital and output supplies should be separated and decoupled.
(1) Differential clock signals can be applied if required.
(2) R1 and R2 must be determined in order to obtain a middle voltage of 3.4 V; see Table 1.
(3) VrefH and VrefL must be decoupled to AGND.
Fig.11 Application diagram for differential input mode.
1996 Sep 12
19
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
100 nF
100 nF
(1)
single
analog
input
CLK
5 V
5 V
100 nF
IN
D0 (LSB)
D1
100 nF
6
5
4
3
2
1 44 43 42 41 40
7
39
38
37
36
35
34
33
32
31
30
29
8
9
100
nF
IN
IN
10
11
12
13
14
15
16
17
D2
D3
D4
D5
D6
D7
TDA8760
100 nF
100 nF
(2)
(2)
R1
R2
D8
(3)
(3)
18 19 20 21 22 23 24 25 26 27 28
100
nF
100
nF
D9 (MSB)
5 V
100 nF
3 V 4.5 V
100 nF
100 nF
5 V
5 V
output format select
chip select input
MGA980
The analog, digital and output supplies should be separated and decoupled.
(1) Differential clock signals can be applied if required.
(2) R1 and R2 must be determined in order to obtain 3.4 V at the transformer; see Table 1.
Adaptation with the single input signal impedance must be taken care of.
(3) VrefH and VrefL must be decoupled to AGND.
Fig.12 Application diagram for differential input mode using an input transformer.
1996 Sep 12
20
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
100 nF
100 nF
(1)
single
analog
input
CLK
5 V
5 V
100 nF
IN
D0 (LSB)
D1
100 nF
6
5
4
3
2
1 44 43 42 41 40
4.7
µ
F
4.7 µF
7
39
38
37
36
35
34
33
32
31
30
29
8
9
IN
IN
10
11
12
13
14
15
16
17
D2
D3
D4
D5
D6
D7
TDA8760
100 nF
100 nF
(2)
(2) (2)
R2 R3
(2)
R1
R4
D8
(3)
(3)
18 19 20 21 22 23 24 25 26 27 28
100
nF
100
nF
D9 (MSB)
5 V
100 nF
3 V 4.5 V
100 nF
100 nF
5 V
5 V
output format select
chip select input
MGA981
The analog, digital and output supplies should be separated and decoupled.
(1) Differential clock signals can be applied if required.
(2) R1 = R3; R2 = R4. R1, R2, R3 and R4 must be determined in order to obtain a middle voltage of 3.7 V; see Table 2.
(3) VrefH and VrefL must be decoupled to AGND.
Fig.13 Application diagram for single input mode.
1996 Sep 12
21
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
PACKAGE OUTLINE
PLCC44: plastic leaded chip carrier; 44 leads
SOT187-2
e
e
E
D
y
X
A
39
29
b
p
Z
E
28
40
b
1
w M
44
1
H
E
E
pin 1 index
A
A
1
A
4
e
(A )
3
6
18
k
1
β
L
p
k
detail X
7
17
v
M
A
e
Z
D
D
B
H
v
M
B
D
0
5
10 mm
scale
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
(1)
(1)
A
min.
A
max.
k
1
max.
Z
Z
E
(1)
(1)
1
4
D
UNIT
mm
A
A
b
D
E
e
e
e
H
H
k
L
p
v
w
y
β
b
D
E
D
E
3
p
1
max. max.
4.57
4.19
0.81 16.66 16.66
0.66 16.51 16.51
16.00 16.00 17.65 17.65 1.22
14.99 14.99 17.40 17.40 1.07
1.44
1.02
0.53
0.33
0.51
0.51 0.25 3.05
0.020 0.01 0.12
1.27
0.05
0.18 0.18 0.10 2.16 2.16
0.007 0.007 0.004 0.085 0.085
o
45
0.180
0.165
0.032 0.656 0.656
0.026 0.650 0.650
0.630 0.630 0.695 0.695 0.048
0.590 0.590 0.685 0.685 0.042
0.057
0.040
0.021
0.013
inches
0.020
Note
1. Plastic or metal protrusions of 0.01 inches maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-02-25
97-12-16
SOT187-2
112E10
MO-047AC
1996 Sep 12
22
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
SOLDERING
Introduction
Wave soldering
Wave soldering techniques can be used for all PLCC
packages if the following conditions are observed:
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
• The package footprint must incorporate solder thieves at
the downstream corners.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering
Reflow soldering techniques are suitable for all PLCC
packages.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
The choice of heating method may be influenced by larger
PLCC packages (44 leads, or more). If infrared or vapour
phase heating is used and the large packages are not
absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9397 750 00192).
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
1996 Sep 12
23
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATION
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1996 Sep 12
24
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
NOTES
1996 Sep 12
25
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
NOTES
1996 Sep 12
26
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
NOTES
1996 Sep 12
27
Philips Semiconductors – a worldwide company
Argentina: see South America
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
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MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
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Tel. +1 800 234 7381
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Tel. +60 3 750 5214, Fax. +60 3 757 4880
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Tel. +9-5 800 234 7381
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Tel. +381 11 825 344, Fax.+381 11 635 777
Middle East: see Italy
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Internet: http://www.semiconductors.philips.com
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1996
SCA51
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
537021/1200/02/pp28
Date of release: 1996 Sep 12
Document order number: 9397 750 01092
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NXP
TDA8760KWP/2-T
IC 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40, Analog to Digital Converter
NXP
TDA8760KWP/4-T
IC 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40, Analog to Digital Converter
NXP
TDA8760KWP/5
IC 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40, Analog to Digital Converter
NXP
TDA8760KWP/5-T
IC 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40, Analog to Digital Converter
NXP
TDA8760KWPA/2
IC 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC44, PLASTIC, MO-047AC, SOT-187-2, LCC-44, Analog to Digital Converter
NXP
TDA8760KWPA/2-T
IC 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC44, PLASTIC, MO-047AC, SOT-187-2, LCC-44, Analog to Digital Converter
NXP
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