TDA8766G [NXP]
10-bit high-speed 2.7 to 5.25 V analog-to-digital converter; 10位高速2.7至5.25 V的模拟 - 数字转换器
| 型号： | TDA8766G |
| 厂家： | 
NXP |
| 描述： | 10-bit high-speed 2.7 to 5.25 V analog-to-digital converter |
| 文件： | 总20页 (文件大小：161K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA8766
10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter
1996 Mar 20
Product specification
Supersedes data of 1995 Mar 22
File under Integrated Circuits, IC02
Philips Semiconductors
Product specification
10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter
TDA8766
FEATURES
APPLICATIONS
• 10-bit resolution
High-speed analog-to-digital conversion for:
• Video data digitizing
• Camera
• 2.7 to 5.25 V operation
• Sampling rate up to 20 MHz
• DC sampling allowed
• Camcorder
• High signal-to-noise ratio over a large analog input
frequency range (9.3 effective bits at 1.0 MHz full-scale
input at fclk = 20 MHz)
• Radio communication.
GENERAL DESCRIPTION
• In range (IR) CMOS output
The TDA8766 is a 10-bit high-speed analog-to-digital
converter (ADC) for professional video and other
• CMOS/TTL compatible digital inputs and outputs
• External reference voltage regulator
• Power dissipation only 53 mW (typical)
applications. It converts with 2.7 to 5.25 V operation the
analog input signal into 10-bit binary-coded digital words at
a maximum sampling rate of 20 MHz. All digital inputs and
outputs are CMOS compatible. A standby mode allows
reduction of the device power consumption down to 4 mW.
• Low analog input capacitance, no buffer amplifier
required
• Standby mode
• No sample-and-hold circuit required.
QUICK REFERENCE DATA
SYMBOL
VDDA
PARAMETER
analog supply voltage
digital supply voltage 1
digital supply voltage 2
output stages supply voltage
analog supply current
digital supply current
CONDITIONS
MIN.
2.7
TYP.
3.3
MAX.
5.25
5.25
5.25
5.25
10
UNIT
V
VDDD1
VDDD2
VDDO
IDDA
2.7
2.7
2.5
−
3.3
3.3
3.3
7.5
7.5
1
V
V
V
mA
mA
mA
IDDD
−
10
IDDO
output stages supply current
fclk = 20 MHz; CL = 20 pF;
ramp input
−
2
INL
integral non-linearity
fclk = 20 MHz; ramp input
−
±1
±2
±0.7
−
LSB
LSB
MHz
mW
DNL
fclk(max)
Ptot
differential non-linearity
maximum clock frequency
total power dissipation
fclk = 20 MHz; ramp input
−
±0.25
−
20
−
VDDA = VDDD = VDDO = 3.3 V
53
73
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
TDA8766G
LQFP32
plastic low profile quad flat package; 32 leads; body 5 × 5 × 1.4 mm
SOT401-1
1996 Mar 20
2
Philips Semiconductors
Product specification
10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter
TDA8766
BLOCK DIAGRAM
V
CLK
5
V
DDD2
OE
16
DDA
7
18
6
1
CLOCK DRIVER
STDBY
MSB
TDA8766
V
RT 15
D9
31 D8
30 D7
29 D6
28 D5
27 D4
26 D3
25 D2
23 D1
R
LAD
V
I
14
CMOS
OUTPUTS
ANALOG -TO - DIGITAL
CONVERTER
analog
voltage input
LATCHES
data outputs
V
RM 11
22
20
D0
LSB
V
V
RB 10
DDO
2
IR
output
CMOS
OUTPUT
IN RANGE LATCH
4
V
DDD1
9
19
V
21
3
V
V
V
MLC853
SSA
SSD2
SSO
SSD1
analog
ground
digital
ground 2
output
ground ground 1
digital
Fig.1 Block diagram.
1996 Mar 20
3
Philips Semiconductors
Product specification
10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter
TDA8766
PINNING
SYMBOL PIN
DESCRIPTION
SYMBOL PIN
DESCRIPTION
D9
1
2
3
4
5
6
7
8
9
data output; bit 9 (MSB)
in range data output
digital ground 1
VDDD2
VSSD2
VDDO
18 digital supply voltage 2 (2.7 to 5.25 V)
19 digital ground 2
IR
VSSD1
VDDD1
CLK
STDBY
VDDA
n.c.
20 positive supply voltage for output
stage (2.5 to 5.25 V)
digital supply voltage 1 (2.7 to 5.25 V)
clock input
VSSO
D0
21 digital output ground
22 data output; bit 0 (LSB)
23 data output; bit 1
24 not connected
standby mode input
analog supply voltage (2.7 to 5.25 V)
not connected
D1
n.c.
D2
25 data output; bit 2
26 data output; bit 3
27 data output; bit 4
28 data output; bit 5
29 data output; bit 6
30 data output; bit 7
31 data output; bit 8
32 not connected
VSSA
VRB
VRM
n.c.
analog ground
D3
10 reference voltage BOTTOM input
11 reference voltage MIDDLE
12 not connected
D4
D5
D6
n.c.
13 not connected
D7
VI
14 analog input voltage
15 reference voltage TOP input
16 output enable input
17 not connected
D8
VRT
n.c.
OE
n.c.
index
corner
D9
IR
1
2
3
4
5
6
7
8
24 n.c.
23 D1
V
V
22 D0
V
SSD1
21
20
19
18
SSO
DDD1
CLK
TDA8766
V
V
V
DDO
SSD2
DDD2
STDBY
V
DDA
n.c.
17 n.c.
MLC854
Fig.2 Pin configuration.
4
1996 Mar 20
Philips Semiconductors
Product specification
10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter
TDA8766
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VDDA
VDDD1, VDDD2
VDDO
PARAMETER
CONDITIONS
note 1
MIN.
−0.3
MAX.
+7.0
UNIT
analog supply voltage
V
V
V
digital supply voltages
note 1
note 1
−0.3
−0.3
+7.0
+7.0
output stages supply voltage
supply voltage difference
∆VDD
V
V
V
DDA − VDDD
DDD − VDDO
DDA − VDDO
−1.0
−1.0
−1.0
−0.3
−
+4.0
+4.0
+4.0
+7.0
VDDD
V
V
V
V
V
VI
input voltage
referenced to VSSA
referenced to VSSD
Vclk(p-p)
AC input voltage for switching
(peak-to-peak value)
IO
output current
−
10
mA
°C
°C
°C
Tstg
Tamb
Tj
storage temperature
operating ambient temperature
junction temperature
−55
−20
−
+150
+75
+150
Note
1. The supply voltages VDDA, VDDD and VDDO may have any value between −0.3 V and +7.0 V provided that the supply
voltage differences ∆VDD are respected.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
PARAMETER
VALUE
UNIT
thermal resistance from junction to ambient in free air
90
K/W
1996 Mar 20
5
Philips Semiconductors
Product specification
10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter
TDA8766
CHARACTERISTICS
VDDA = V7 to V9 = 3.3 V; VDDD = V4 to V3 = V18 to V19 = 3.3 V; VDDO = V20 to V21 = 3.3 V; VSSA, VSSD and VSSO
short-circuited together; Vi(p-p) = 1.83 V; CL = 20 pF; Tamb = 0 to +70 °C; typical values measured at Tamb = 25 °C;
unless otherwise specified.
SYMBOL
Supply
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDDA
VDDD1
VDDD2
VDDO
∆VDD
analog supply voltage
2.7
2.7
2.7
2.5
3.3
5.25
V
digital supply voltage 1
digital supply voltage 2
output stages supply voltage
voltage difference
3.3
3.3
3.3
5.25
5.25
5.25
V
V
V
V
V
V
DDA − VDDD
DDA − VDDO
DDD − VDDO
−0.2
−0.2
−0.2
−
−
+0.2
+3.0
+3.0
10
V
−
V
−
V
IDDA
IDDD
IDDO
analog supply current
digital supply current
7.5
7.5
1
mA
mA
mA
−
10
output stages supply current
fclk = 20 MHz;
ramp input; CL = 20 pF
−
2
Inputs
CLOCK INPUT CLK (REFERENCED TO VSSD); see note 1
VIL
VIH
LOW level input voltage
HIGH level input voltage
0
−
−
−
0
−
4
3
0.3VDDD
V
0.7VDDD
VDDD
VDDD
+1
5
V
V
DDD ≤ 3.6 V
0.6VDDD
V
IIL
IIH
ZI
LOW level input current
HIGH level input current
input impedance
Vclk = 0.3VDDD
Vclk = 0.7VDDD
fclk = 20 MHz
fclk = 20 MHz
−1
−
µA
µA
kΩ
pF
−
−
CI
input capacitance
−
−
INPUTS OE AND STDBY (REFERENCED TO VSSD); see Table 3
VIL
VIH
LOW level input voltage
HIGH level input voltage
0
−
−
−
−
−
0.3VDDD
VDDD
VDDD
−
V
0.7VDDD
0.6VDDD
−1
V
V
DDD ≤ 3.6 V
V
IIL
LOW level input current
HIGH level input current
VIL = 0.3VDDD
VIH = 0.7VDDD
µA
µA
IIH
−
+1
VI (ANALOG INPUT VOLTAGE REFERENCED TO VSSA
)
IIL
IIH
ZI
LOW level input current
HIGH level input current
input impedance
VI = VRB
VI = VRT
−
−
−
−
0
−
−
−
−
µA
µA
kΩ
pF
35
5
fi = 1 MHz
fi = 1 MHz
CI
input capacitance
8
1996 Mar 20
6
Philips Semiconductors
Product specification
10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter
TDA8766
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Reference voltages for the resistor ladder; see Table 1
VRB
VRT
Vdiff
reference voltage BOTTOM
reference voltage TOP
1.1
2.7
1.5
1.2
−
V
VTOP ≤ VDDA
3.3
2.1
VDDA
2.7
V
V
differential reference voltage
VRT − VRB
Iref
reference current
resistor ladder
−
7.2
−
mA
Ω
RLAD
TCRLAD
−
290
1860
539
135
135
1.83
−
temperature coefficient of the resistor
ladder
−
−
ppm
mΩ/K
mV
mV
V
−
−
VosB
VosT
Vi(p-p)
offset voltage BOTTOM
offset voltage TOP
note 2
note 2
note 3
−
−
−
−
analog input voltage
(peak-to-peak value)
1.4
2.4
Outputs
DIGITAL OUTPUTS D9 TO D0 AND IR (REFERENCED TO VSSD
)
VOL
VOH
IOZ
LOW level output voltage
HIGH level output voltage
output current in 3-state mode
IO = 1 mA
0
−
0.5
V
IO = −1 mA
V
DDO − 0.5 −
VDDO
+20
V
0.5 V < VO < VDDO
−20
−
µA
Switching characteristics
CLOCK INPUT CLK; see Fig.4; note 1
fclk(max)
tCPH
maximum clock frequency
clock pulse width HIGH
clock pulse width LOW
20
15
15
−
−
−
−
−
−
MHz
ns
tCPL
ns
Analog signal processing
LINEARITY
INL
integral non-linearity
fclk = 20 MHz;
ramp input; (see Fig.6)
−
−
±1
±2
LSB
LSB
DNL
differential non-linearity
fclk = 20 MHz;
±0.25 ±0.7
ramp input; (see Fig.7)
INPUT SET RESPONSE (fclk = 20 MHz; see Fig.8; note 4)
tSTLH
analog input settling time
LOW-to-HIGH
full-scale square wave
−
−
4
4
6
6
ns
ns
tSTHL
analog input settling time
HIGH-to-LOW
full-scale square wave
HARMONICS; (fclk = 20 MHZ; see Fig.9; note 5)
THD total harmonic distortion
SIGNAL-TO-NOISE RATIO; see Fig.9; note 5
fi = 1 MHz
−
−
−63
−
−
dB
dB
S/N
signal-to-noise ratio (full scale)
without harmonics;
60
fclk = 20 MHz;
fi = 1 MHz
1996 Mar 20
7
Philips Semiconductors
Product specification
10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter
TDA8766
SYMBOL
EFFECTIVE BITS; see Fig.9; note 5
EB effective bits
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
fclk = 20 MHz
fi = 300 kHz
fi = 1 MHz
−
−
−
9.5
−
−
−
bits
bits
bits
9.3
8.0
fi = 3.58 MHz
Timing (fclk = 20 MHz; CL = 20 pF); see Fig.4; note 6
tds
th
sampling delay time
output hold time
−
5
8
8
8
−
5
ns
ns
ns
ns
ns
−
−
td
output delay time
VDDO = 4.75 V
VDDO = 3.15 V
12
17
21
15
20
24
VDDO = 2.7 V
3-state output delay times; see Fig.5
tdZH
tdZL
tdHZ
tdLZ
enable HIGH
enable LOW
disable HIGH
disable LOW
−
−
−
−
14
16
16
14
18
20
20
18
ns
ns
ns
ns
Standby mode output delay times
tdSTBLH standby (LOW-to-HIGH transition)
tdSTBHL start-up (HIGH-to-LOW transition)
−
−
−
−
200
500
ns
ns
Notes
1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 1 ns.
2. Analog input voltages producing code 0 up to and including 1023:
a) VosB (voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and
the reference voltage BOTTOM (VRB) at Tamb = 25 °C.
b) VosT (voltage offset TOP) is the difference between VRT (reference voltage TOP) and the analog input which
produces data outputs equal to 1023 at Tamb = 25 °C.
3. In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities
of the converter reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to
pins VRB and VRT via offset resistors ROB and ROT as shown in Fig.3.
V
RT – VRB
a) The current flowing into the resistor ladder is IL =
and the full-scale input range at the converter,
-----------------------------------------
R
OB + RL + ROT
R L
to cover code 0 to code 1023, is V I = R L × I L =
× (V RT – VRB) = 0.871 × (VRT – VRB)
-----------------------------------------
R
OB + RL + ROT
b) Since RL, ROB and ROT have similar behaviour with respect to process and temperature variation, the ratio
RL
will be kept reasonably constant from part to part. Consequently variation of the output codes
-----------------------------------------
OB + RL + ROT
R
at a given input voltage depends mainly on the difference VRT − VRB and its variation with temperature and supply
voltage. When several ADCs are connected in parallel and fed with the same reference source, the matching
between each of them is then optimized.
1996 Mar 20
8
Philips Semiconductors
Product specification
10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter
TDA8766
4. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square-wave signal) in order to sample the signal and obtain correct output data.
5. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB.
6. Output data acquisition: the output data is available after the maximum delay time of td.
handbook, halfpage
V
RT
R
OT
code 1023
R
L
V
I
L
RM
R
LAD
code 0
R
OB
V
RB
MGD281
Fig.3 Explanation of note 3.
1996 Mar 20
9
Philips Semiconductors
Product specification
10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter
TDA8766
Table 1 Output coding and input voltage (typical values; referenced to VSSA
)
BINARY OUTPUT BITS
VI(p-p)
(V)
STEP
IR
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Underflow
<1.335
0
1
1
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
1
.
0
1.335
1
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1022
1023
Overflow
.
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
3.165
>3.165
Table 2 Mode selection
OE
D9 TO D0
IR
1
0
high impedance
active; binary
high impedance
active
Table 3 Standby selection
STDBY
D9 TO D0
IDDA + IDDD (typ.)
1
0
last logic state
active
1.2 mA
15 mA
t
CPL
t
CPH
50%
CLK
sample N
sample N + 1
sample N + 2
V
l
t
t
ds
h
V
DDO
DATA
D0 to D9
DATA
N - 2
DATA
N - 1
DATA
N
DATA
N + 1
50%
0 V
t
d
MGD346
Fig.4 Timing diagram.
10
1996 Mar 20
Philips Semiconductors
Product specification
10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter
TDA8766
V
DDD
OE
50 %
dZH
t
t
dHZ
HIGH
90 %
output
data
50 %
LOW
t
t
dZL
dLZ
HIGH
output
data
50 %
LOW
10 %
TEST
S1
V
DDD
t
t
t
t
V
DDD
dLZ
dZL
dHZ
dZH
3.3 kΩ
20 pF
V
DDD
GND
GND
S1
TDA8766
OE
MLC855
fOE = 100 kHz.
Fig.5 Timing diagram and test conditions of 3-state output delay time.
1996 Mar 20
11
Philips Semiconductors
Product specification
10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter
TDA8766
MLD115
0.6
A
(LSB)
0.4
0.2
0
−0.2
−0.4
−0.6
0
200
400
600
800
1000
1100
f (codes)
1023
Fig.6 Typical integral non-linearity (INL) performance.
MLD116
0.25
A
(LSB)
0.15
0.05
−0.05
−0.15
−0.25
0
200
400
600
800
1000
1100
f (codes)
1023
Fig.7 Typical differential non-linearity (DNL) performance.
12
1996 Mar 20
Philips Semiconductors
Product specification
10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter
TDA8766
t
t
STLH
STHL
50 %
code 1023
V
I
50 %
code 0
5 ns
5 ns
CLK
50 %
50 %
MBD875
2 ns
2 ns
Fig.8 Analog input settling-time diagram.
MLD117
0
A
(dB)
20
40
60
80
100
120
0
1.25
2.5
3.76
5.01
6.26
7.51
8.76
10
f (MHz)
Effective bits: 9.59; THD = −76.60 dB.
Harmonic levels (dB): 2nd = −81.85; 3rd = −87.56; 4th = −88.81; 5th = −88.96; 6th = −79.58.
Fig.9 Typical Fast Fourier Transform (fclk = 20 MHz; fi = 1 MHz).
13
1996 Mar 20
Philips Semiconductors
Product specification
10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter
TDA8766
INTERNAL PIN CONFIGURATIONS
handbook, halfpage
handbook, halfpage
V
V
DDO
DDA
D9 to D0
IR
V
I
V
V
SSO
SSA
MLC856
MLC857
Fig.10 CMOS data and In Range (IR) outputs.
Fig.11 Analog inputs.
handbook, halfpage
handbook, halfpage
V
V
DDO
DDA
V
V
RT
R
LAD
RM
OE
(STDBY)
V
RB
V
SSA
V
SSO
MLC859
MLC858
Fig.12 OE (STDBY) input.
Fig.13 VRB, VRM and VRT.
1996 Mar 20
14
Philips Semiconductors
Product specification
10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter
TDA8766
V
DDD
handbook, halfpage
1
/ V
2
CLK
DDD
V
SSD
MLC860
Fig.14 CLK input.
1996 Mar 20
15
Philips Semiconductors
Product specification
10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter
TDA8766
APPLICATION INFORMATION
Additional application information will be supplied upon request (please quote number “AN96012”).
(2)
n.c.
32
D8
31
D7
30
D6
29
D5
28
D4
27
D3
26
D2
25
(2)
D9
IR
n.c.
1
2
3
4
5
6
7
8
24
D1
23
22
21
20
19
18
17
V
V
SSD1
DDD1
CLK
D0
V
SSO
TDA8766
V
V
V
DDO
STDBY
SSD2
V
DDA
DDD2
(2)
(2)
n.c.
n.c.
9
10
11
12
13
14
15
16
MLC861
(2)
(2)
(4)
V
(1)
(1)
(1)
OE
V
V
V
V
RT
SSA
n.c.
n.c.
I
RB
RM
(3)
100
nF
100
nF
V
V
SSA
SSA
100
nF
V
SSA
The analog and digital supplies should be separated and decoupled.
The external voltage reference generator must be built such that a good supply voltage ripple rejection is achieved with respect to the LSB value.
Eventually, the reference ladder voltages can be derived from a well regulated VDDA supply through a resistor bridge and a decoupled capacitor.
(1) VRB, VRM and VRT are decoupled to VSSA
.
(2) Pins 8, 12, 13, 17, 24 and 32 should be connected to the closest ground pin in order to prevent noise influence.
(3) When VRM is not used, pin 11 can be left open, avoiding the decoupling capacitor. In any case, pin 11 must not be grounded.
(4) When analog input signal is AC coupled, an input bias or a clamping level must be applied to VI input (pin 14).
Fig.15 Application diagram.
1996 Mar 20
16
Philips Semiconductors
Product specification
10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter
TDA8766
PACKAGE OUTLINE
LQFP32: plastic low profile quad flat package; 32 leads; body 5 x 5 x 1.4 mm
SOT401-1
c
y
X
A
E
17
24
Z
16
25
E
e
A
H
2
E
A
(A )
3
A
1
w M
p
θ
pin 1 index
b
L
p
32
9
L
1
8
detail X
Z
v M
D
A
e
w M
b
p
D
B
H
v M
B
D
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.15 1.5
0.05 1.3
0.27 0.18 5.1
0.17 0.12 4.9
5.1
4.9
7.15 7.15
6.85 6.85
0.75
0.45
0.95 0.95
0.55 0.55
mm
1.60
0.25
0.5
1.0
0.2 0.12 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-12-19
97-08-04
SOT401-1
1996 Mar 20
17
Philips Semiconductors
Product specification
10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter
TDA8766
If wave soldering cannot be avoided, the following
conditions must be observed:
SOLDERING
Introduction
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
Even with these conditions, do not consider wave
soldering LQFP packages LQFP48 (SOT313-2),
LQFP64 (SOT314-2) or LQFP80 (SOT315-1).
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011). During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering
Reflow soldering techniques are suitable for all LQFP
packages.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
Wave soldering
Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
1996 Mar 20
18
Philips Semiconductors
Product specification
10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter
TDA8766
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1996 Mar 20
19
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Internet: http://www.semiconductors.philips.com/ps/
For all other countries apply to: Philips Semiconductors,
Marketing & Sales Communications, Building BE-p,
P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands,
Fax. +31-40-2724825
SCDS48
© Philips Electronics N.V. 1996
All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.
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Tel. (022) 74 8000, Fax. (022) 74 8341
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Printed in The Netherlands
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Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. (022) 612 2831, Fax. (022) 612 2327
537021/1100/02/pp20
Date of release: 1996 Mar 20
9397 750 00746
Document order number:
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