TDA8798HLBD [NXP]
IC DUAL 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP64, PLASTIC, SOT-314-2, LQFP-64, Analog to Digital Converter;
| 型号： | TDA8798HLBD |
| 厂家： | 
NXP |
| 描述： | IC DUAL 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP64, PLASTIC, SOT-314-2, LQFP-64, Analog to Digital Converter 转换器 |
| 文件： | 总26页 (文件大小：262K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA8798
Dual 8-bit, 100 Msps A/D converter
with DPGA
Objective specification
1999 Sep 16
Supersedes data of 1998 Apr 15
File under Integrated Circuits, IC02
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with
DPGA
TDA8798
FEATURES
APPLICATIONS
• High-dynamic range acquisition front-ends
• Dual 8-bit Analog-to-Digital Converter (ADC)
• Sampling rate up to 100 million samples per
• Digital data storage read channels.
second (Msps)
• Dual 34 dBV 6-bit Digitally Programmable Gain
Amplifier (DPGA) with optional power-off
GENERAL DESCRIPTION
The TDA8798 is a dual 8-bit ADC with DPGA.
The 100 Msps maximum sampling rate and 34 dBV DPGA
gain range optimizes the ADC for high dynamic range
applications.
• Optional external equalization filter with capacitive
coupling between DPGA and ADC
• Serial Interface (SI) for DPGA gain control using either
parallel load mode or count-up/count-down mode
• 3.3 V TTL/CMOS compatible I/O
• Differential or single-ended TTL/CMOS clock interface
• AC or DC coupling for DPGA inputs.
QUICK REFERENCE DATA
SYMBOL
VDDA
PARAMETER
analog supply voltage
digital supply voltage
CONDITIONS
MIN.
TYP. MAX. UNIT
3.15
3.0
2.7
−
3.3
3.3
3.3
106
tbf
3.45
3.6
3.6
−
V
VDDD
VDDO
IDDA
V
output stage supply voltage
analog supply current
V
with DPGAEN LOW
mA
mA
mA
mA
with DPGAEN HIGH
−
−
IDDD
IDDO
INL
digital supply current
−
30
−
output stage supply current
DC integral non-linearity
−
3
−
from IC analog input to digital
output; ramp input;
f
CLK = 100 MHz
with DPGA at G(min)
without DPGA
−
−
±3.0
±1.0
tbf
tbf
LSB
LSB
DNL
DC differential non-linearity
from IC analog input to digital
output; ramp input;
fCLK = 100 MHz
with DPGA at G(min)
without DPGA
−
−
−
±0.5
±0.5
tbf
tbf
tbf
2
LSB
LSB
Vn(o)(rms)
output referred noise (RMS value) DPGA at G(max); Zi = 50 Ω;
mVrms
noise bandwidth = 15 MHz
B(−3dB)(ADC) ADC −3 dB analogue bandwidth
B(−3dB)(DPGA) DPGA −3 dB bandwidth
f(sample)(max) maximum sampling rate
at Vi(dif)(FS)
at Vi(dif)(max)
−
120
tbf
−
MHz
MHz
Msps
mW
30
100
−
−
−
−
Ptot
total power dissipation
with DPGAEN LOW
with DPGAEN HIGH
460
tbf
500
tbf
−
mW
1999 Sep 16
2
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with
DPGA
TDA8798
ORDERING INFORMATION
PACKAGE
TYPE
NUMBER
NAME
DESCRIPTION
VERSION
TDA8798HL
LQFP64
plastic low profile quad flat package; 64 leads;
SOT314-2
body 10 × 10 × 1.4 mm
BLOCK DIAGRAM
OPTIONAL
EXTERNAL
FILTER 2
to DPGA2
to BUF2
to DPGA2N
to BUF2N
V
V
TE
OE
DPGA2 BUF2N
SSA4
V
oref2
DPGAC2
DPGA2N BUF2
TEST
DDA4
SR
3
2
1
63 64
62 54 55 52 60 61 51
58
59
CLK2
REGULATOR
CLK2N
6
41 to 48
digital
output 2
B0 to B7
VIN2N
A
analog
input 2
DPGA2
6
BUFFER
7
D
VIN2
5
V
ADC2
4
DDA2
V
ref2
8
TDA8798
V
V
SSA2
24
25
SSD1
DDD1
27
29
26
28
30
SEN2
V
SCLK
53
SERIAL
INTERFACE
DPGAEN
SMODE
SDATA
SEN1
56
57
9
V
DDD2
V
SSD2
V
SSA1
13
6
12
V
ref1
V
DDA1
ADC1
10
11
40 to 33
digital
output 1
A0 to A7
VIN1
A
analog
input 1
BUFFER
DPGA1
D
VIN1N
23
22
CLK1
REGULATOR
19 20 21 31 50 32 49
CLK1N
14
15 16 18 17
DPGA1N BUF1
MGM863
V
V
V
DPGAC1
DDO1
V
SSO1
V
DDA3
V
DPGA1 BUF1N
V
oref1
DDO2
SSO2
SSA3
OPTIONAL
EXTERNAL
FILTER 1
to DPGA1N
to DPGA1
to BUF1N
to BUF1
Fig.1 Block diagram.
1999 Sep 16
3
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with
DPGA
TDA8798
100 nF
C
C
o(DPGA)
10 µH
(1)
(2)
DPGA
BUF
L
I
C
C
R
R
R
R
OUT
OUT
i(ADC)
o(DPGA)
i(ADC)
R
1 kΩ
−
I
i(ADC)
o(DPGA)
i(ADC)
C
(3)
L
(4)
DPGAN
BUFN
10 µH
C
o(DPGA)
100 nF
TDA8798
TDA8798
FCE267
External filtering may be used between DPGA and ADC to limit the noise bandwidth.
R ⁄ 2 + Ro(DPGA)
1
The external filter has a low-pass cut-off frequency of fl(–3dB)
≈
×
.
------ ------------------------------------------
2π
L
(1) DPGA1/DPGA2
(2) BUF1/BUF2
1
1
and a high-pass cut-off frequency of f h(–3dB)
≈
×
------ -----------------------------
.
2π R i(ADC) × C
(3) DPGA1N/DPGA2N
(4) BUF1N/BUF2N
Other types of filter may be used if DC biasing is correct.
Fig.2 External filter.
PINNING
SYMBOL
PIN
DESCRIPTION
DPGA2N
DPGA2
DPGAC2
Vref2
1
2
DPGA2 inverting output
DPGA2 non-inverting output
DPGA2 bandwidth limitation control
ADC2 reference output
3
4
VDDA2
5
DPGA2 analog supply voltage
DPGA2 inverting input voltage
DPGA2 non-inverting input voltage
DPGA2 analog ground
VIN2N
VIN2
6
7
VSSA2
8
VSSA1
9
DPGA1 analog ground
VIN1
10
11
12
13
14
15
16
DPGA1 non-inverting input voltage
DPGA1 inverting input voltage
DPGA1 analog supply voltage
ADC1 reference output
VIN1N
VDDA1
Vref1
DPGAC1
DPGA1
DPGA1N
DPGA1 bandwidth limitation control
DPGA1 non-inverting output
DPGA1 inverting output
1999 Sep 16
4
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with
DPGA
TDA8798
SYMBOL
BUF1
PIN
DESCRIPTION
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
buffer1 non-inverting input
buffer1 inverting input
BUF1N
Voref1
VDDA3
VSSA3
CLK1N
CLK1
VSSD1
VDDD1
SMODE
SEN2
SDATA
SCLK
SEN1
VDDO1
VSSO1
A7
buffer1 common mode reference output
ADC1 analog supply voltage 3
ADC1 analog ground 3
ADC1 inverting clock input
ADC1 non-inverting clock input
digital ground 1
digital supply voltage 1
serial interface mode input
serial interface enable 2 (active low)
serial interface data input
serial interface clock input
serial interface enable 1 (active low)
output stage supply voltage 1
output stage ground 1
channel 1 output bit 7 (MSB)
channel 1 output bit 6
A6
A5
channel 1 output bit 5
A4
channel 1 output bit 4
A3
channel 1 output bit 3
A2
channel 1 output bit 2
A1
channel 1 output bit 1
A0
channel 1 output bit 0 (LSB)
channel 2 output bit 0 (LSB)
channel 2 output bit 1
B0
B1
B2
channel 2 output bit 2
B3
channel 2 output bit 3
B4
channel 2 output bit 4
B5
channel 2 output bit 5
B6
channel 2 output bit 6
B7
channel 2 output bit 7 (MSB)
output stage ground 2
VSSO2
VDDO2
OE
output stage supply voltage 2
digital output enable (active LOW)
digital output bit slew-rate control
DPGA enable (active LOW)
test input (to be grounded)
track-and-hold enable (active LOW)
digital supply voltage 2
SR
DPGAEN
TEST
TE
VDDD2
VSSD2
digital ground 2
1999 Sep 16
5
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with
DPGA
TDA8798
SYMBOL
CLK2
PIN
DESCRIPTION
58
59
60
61
62
63
64
ADC2 non-inverting clock input
ADC2 inverting clock input
ADC2 analog ground 4
CLK2N
VSSA4
VDDA4
Voref2
ADC2 analog supply voltage 4
buffer2 common mode reference output
buffer2 inverting input
BUF2N
BUF2
buffer2 non-inverting input
DPGA2N
1
48 B7
2
3
DPGA2
47 B6
46 B5
45 B4
44 B3
43 B2
42 B1
41 B0
40 A0
39 A1
38 A2
37 A3
36 A4
35 A5
34 A6
33 A7
DPGAC2
V
4
ref2
V
5
DDA2
VIN2N
VIN2
6
7
V
8
SSA2
TDA8798HL
V
9
SSA1
VIN1
10
11
12
13
VIN1N
V
DDA1
V
ref1
DPGAC1 14
DPGA1 15
DPGA1N 16
MGM864
Fig.3 Pin configuration.
6
1999 Sep 16
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with
DPGA
TDA8798
FUNCTIONAL DESCRIPTION
Serial Interface (SI)
The TDA8798 comprises two independent fully differential
signal chains each having a DPGA and a high-speed ADC.
A serial interface allows the gain of each DPGA to be
controlled independently. To improve signal conditions, an
AC-coupled external filter can be connected between a
DPGA and ADC. The TDA8798 can be used as a dual 8-bit
ADC without DPGA functionality, using less power.
The SI allows the gain of each DPGA to be controlled
independently using either a parallel load mode or a
count-up/count-down mode. The gain control mode is
selected by the state of SMODE. The operation of DPGA
gain control is shown in Timing diagram, (see Fig.4).
Parallel load mode
This mode loads gain control data serially into a decoder
in the SI. Each of the six bits are loaded on the rising edge
of SCLK. After the load has completed, SEN goes inactive,
loading the data in parallel to a gain control register in the
SI, changing the gain of the DPGA.
Digitally Programmable Gain Amplifier (DPGA)
The gain of the differential DPGA is programmable from
0 to 34 dBV in 63 equal steps by a 6-bit word output in
parallel from a gain control register in the SI. For all gain
settings, the DPGA signal bandwidth exceeds 30 MHz.
The settling time between gain changes can be adjusted
by an external decoupling capacitor connected to
DPGAC1 (pin 14) and/or DPGAC2 (pin 3). The analog
input signals can be either AC or DC coupled. When used
only as a dual 8-bit ADC, both DPGAs can be disabled to
reduce power consumption.
Count-up/count-down mode
Count-up/count-down mode is selected when SMODE is
in the opposite state to parallel load mode. This mode
either increments or decrements the SI gain control
register in one-bit steps when SEN and SCLK are both
active; the state of SDATA determines the count direction
(up or down). This allows the gain of the DPGA to be
changed asynchronously and intermittently.
Analog-to-Digital Converter (ADC)
The 8-bit ADC converts the differential analog input signal
into a binary output format at a maximum conversion rate
of 100 Msps. All digital input and output signals are
TTL/CMOS compatible.
ADC digital outputs
Digital noise on the internal supply lines increases when
the VDDO voltage increases, affecting the crosstalk
between channels. This effect can be reduced by making
SR (pin 52) HIGH, changing the slew-rate of the ADC
digital outputs.
The ADC clock signal can be from either a differential or a
single-ended source; when single-ended, the unused
clock input pin should be decoupled externally. The analog
input to the ADC is AC coupled.
When used only as a dual ADC, the ADC can be externally
biased by regulator output Voref1 (pin 19) and/or
Voref2 (pin 62) using series resistors of, for example, 50 Ω,
connected to the ADC buffer inputs providing a lower input
impedance. This requires Voref1 and/or Voref2 to be
decoupled to ground by a 10 nF capacitor.
Vref1 (pin 13) and/or Vref2 (pin 4) provide a voltage
corresponding to the bias of the ADC which can be used
as a reference output to an external control circuit.
Alternatively, an external control voltage can be applied to
these pins to adjust the full-scale range of the ADC.
1999 Sep 16
7
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with
DPGA
TDA8798
Table 1 Serial interface truth table; see notes 1 and 2
SMODE
SCLK
SEN1
SEN2
SDATA
ACTION
0
1
1
U
WAIT
X,
0
0
0
0
0
0
1
0
0
1
1
0
1
1
1
0
0
0
Di
1
SISR: SISR ← Di
SISR: SISR ← 1
GCR1: GCR1 + 1
0
SISR: SISR ← 0
GCR1: GCR1 − 1
1
SISR: SISR ← 1
GCR2: GCR2 + 1
0
SISR: SISR ← 0
GCR2: GCR2 − 1
1
SISR: SISR ← 1
GCR1: GCR1 + 1
GCR2: GCR2 + 1
SISR: SISR ← 0
GCR1: GCR1 − 1
GCR2: GCR2 − 1
WAIT
0
0
0
0
1
1
1
1
1
U
Di
U
U
U
X,
X,
X,
X,
X,
X,
SISR: SISR ← Di
GCR1: SISR
X,
X,
X,
GCR2: SISR
X,
GCR1: SISR
GCR2: SISR
Notes
1. ‘← Di’: shifting LSB and loading new LSB with value Di.
2. In count-up/count-down mode, the gain control register cannot be incremented above the maximum gain value of 63,
or decremented below the minimum gain value of 0.
1999 Sep 16
8
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with
DPGA
TDA8798
Table 2 Abbreviations
Table 4 SR truth table
SYMBOL
DESCRIPTION
SR
ADC DIGITAL OUTPUT SLEW RATE
GCR1
GCR2
SISR
X
DPGA1 gain control register value
DPGA2 gain control register value
Serial interface shift register value
0
1
maximum
minimum
Table 5 DPGAEN truth table
can be either logic state 0 or logic
state 1
DPGAEN
DPGA FUNCTIONALITY
rising edge
0
1
enabled
disabled
falling edge
Table 6 Gain Control
U
can be either undefined logic state X
rising edge or falling edge
GAIN CONTROL
REGISTER VALUE
GAIN (dBV)
Di
Data input
000000
000001
000010
...
0.00
0.54
1.08
...
Table 3 TE truth table
TE
ADC TRACK-AND-HOLD
track-and-hold enabled
track enabled
0
1
...
...
...
...
111110
111111
33.46
34.00
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS
VDDA analog supply voltage
MIN.
MAX.
UNIT
−0.3
−0.3
−0.3
+7.0
+7.0
+7.0
V
VDDD
VDDO
∆VDDX
digital supply voltage
V
output stage supply voltage
supply voltage differences between
V
V
V
V
DDA and VDDD
DDO and VDDD
DDA and VDDO
−1.0
−1.0
−1.0
−0.3
+1.0
+1.0
+1.0
+7.0
V
V
V
V
Vi(VIN)
input voltage range on VIN1 and VIN2 referenced to VSSA
(pins 10 and 7)
IO
output current
−
10
mA
°C
°C
°C
Tstg
Tamb
Tj
storage temperature
ambient temperature
junction temperature
−55
0
+150
70
−
104
1999 Sep 16
9
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with
DPGA
TDA8798
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
VALUE
UNIT
Rth(j-a)
thermal resistance from junction to ambient in free air
68
K/W
CHARACTERISTICS
DDA = V5 (or V12 or V20 or V61) to V8 (or V9 or V21 or V60) = 3.15 to 3.45 V; VDDD = V25 (or V56) to V24 (or V57) = 3.0
to 3.6 V; VDDO = V31 (or V50) to V32 (or V49) = 2.7 to 3.6 V; VSSA, VSSD and VSSO shorted together; VDDA to
DDD = −0.25 to +0.25 V; VDDD to VDDO = −0.25 to +0.90 V; VDDA to VDDO = −0.25 to +0.75 V; Tamb = 0 to 70 °C; typical
values measured at VDDA = VDDD = VDDO = 3.3 V and Tamb = 25 °C; unless otherwise specified.
V
V
SYMBOL
Supplies
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
VDDA
VDDD
VDDO
IDDA
analog supply voltage
digital supply voltage
output stage supply voltage
analog supply current
3.15
3.0
2.7
−
3.3
3.3
3.3
106
tbf
3.45
3.6
3.6
−
V
V
V
DPGAEN LOW
DPGAEN HIGH
mA
mA
mA
mA
−
−
IDDD
IDDO
digital supply current
−
30
−
output stage supply current
fCLK = 100 MHz;
ramp input
−
3
−
Digital programmable gain amplifiers
ANALOG INPUTS (VIN1, VIN1N, VIN2 AND VIN2N)
Vi(dif)(max)(p-p) maximum differential input
voltage (peak-to-peak value)
at G(min)
at G(max)
−
0.5
10
2.8
tbf
−
−
V
−
−
mV
V
Vi(cm)(DPGA)
Ii(DPGA)
Ri(DPGA)
Ci(DPGA)
common mode input voltage
input current
tbf
−
tbf
−
at Vi(cm)(DPGA)
µA
kΩ
pF
input resistance
1
−
input capacitance
−
−
5
ANALOG OUTPUTS (DPGA1, DPGA1N, DPGA2 AND DPGA2N)
Vo(dif)(max)(p-p) maximum differential output
voltage (peak-to-peak value)
at G(min)
at G(max)
−
−
−
−
−
0.5
0.5
3.1
115
−
−
V
−
V
Vo(cm)(DPGA)
Ro(DPGA)
common mode output voltage
output resistance
−
V
at Vo(cm)(DPGA)
160
5
Ω
pF
Co(DPGA)
output capacitance
1999 Sep 16
10
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with
DPGA
TDA8798
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
BANDWIDTH AND SETTLING
B(−3dB)(DPGA) DPGA −3 dB bandwidth
at Vi(dif)(max)
30
40
tbf
−
−
MHz
ns
tst
settling time
full-scale transition
10% to 90%
−
td(g)
group delay
fi up to 15 MHz
at G(min)
−
−
tbf
tbf
−
−
ps
ps
at G(max)
GAIN
G(min)
G(max)
Gstep
minimum gain setting
maximum gain setting
gain step size
tbf
tbf
−
0
tbf
tbf
−
dBV
dBV
dBV
34
0.54
−
Gstep(L)
gain step size linearity (actual
−0.75
+0.75 dBV
gain step/average − 1)
G(m)(c-c)
∆G/∆T
channel-to-channel gain
matching
at G(min)
at G(max)
at G(min)
at G(max)
at G(min)
at G(max)
−
−
−
−
−
−
tbf
tbf
8
−
dB
−
dB
amplifier gain stability as a
function of temperature
tbf
tbf
tbf
tbf
mdB/°C
mdB/°C
dB/V
dB/V
8
∆G/∆VDD
amplifier gain stability as a
function of power supply
voltage
0.4
0.8
GAIN SWITCHING; TAMB = 25 °C
tst(G-G)
settling time between two
consecutive gain settings
CL = 68 pF
−
−
160
−
ns
ns
tPD
propagation delay
−
20
REJECTION
PSRR
power supply rejection ratio
common mode rejection ratio
DC to 15 MHz
at G(min)
40
40
−
−
−
−
dB
dB
CMRR
HARMONICS; TAMB = 25 °C
HD2
second harmonic distortion
fi = 15 MHz;
at Vo(dif)(max); at gain
control register:
00H
20H
3FH
40
40
−
tbf
tbf
tbf
−
−
−
dB
dB
dB
HD3
third harmonic distortion
fi = 15 MHz;
at Vo(dif)(max); at gain
control register:
00H
20H
3FH
tbf
tbf
−
50
50
50
−
−
−
dB
dB
dB
1999 Sep 16
11
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with
DPGA
TDA8798
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
NOISE
Vn(o)(rms)
output referred noise
(RMS value)
DPGA at G(max)
Zi = 50 Ω; noise
;
−
tbf
2
mVrms
bandwidth = 15 MHz
ADC (without DPGA; fCLK = 100 MHz; from buffer input to digital output)
ANALOG INPUTS (BUF1, BUF1N, BUF2 AND BUF2N)
Vi(dif)(FS)(p-p)
differential input voltage
full-scale amplitude;
(peak-to-peak value)
−
500
−
mV
Vi(cm)(ADC)
Ii(ADC)
common mode input voltage
input current
−
−
−
−
tbf
tbf
20
3
−
−
−
−
V
at Vi(cm)(ADC)
µA
kΩ
pF
Ri(ADC)
Ci(ADC)
input resistance
input capacitance
STATIC LINEARITY
NLdc(i)
DC integral non-linearity
ramp input;
without DPGA
−
−
±1.0
±3.0
tbf
tbf
LSB
LSB
with DPGA
at G(min)
NLdc(dif)
DC differential non-linearity
ramp input;
without DPGA
−
−
±0.5
±0.5
tbf
tbf
LSB
LSB
with DPGA
at G(min)
DYNAMIC PERFORMANCE
THD
S/N
total harmonic distortion
fi = 4.43 MHz
−
−
−55
−46
−
−
dB
dB
signal-to-noise ratio
without harmonics
BANDWIDTH
B(−3dB)(ADC)
ADC −3 dB analog bandwidth
−
−
120
−
−
MHz
dB
CROSSTALK BETWEEN ADC1 AND ADC2
αct
crosstalk between channels
−40
CLOCK INPUTS: CLK1, CLK1N, CLK2 AND CLK2N; note 1
VIL
VIH
IIH
LOW-level clock input voltage
HIGH-level clock input voltage
HIGH-level clock input current
LOW-level clock input current
−
−
−
−
−
0.8
VDDD
100
−
V
2.0
−
V
µA
µA
IIL
−100
DIGITAL CONTROL INPUTS (OE, TE, TEST, DPGAEN AND SR)
VIL
VIH
IIH
LOW-level input voltage
HIGH-level input voltage
HIGH-level input current
LOW-level input current
−
−
−
−
−
0.8
VDDD
+5
V
2.0
−5
−5
V
µA
µA
IIL
+5
1999 Sep 16
12
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with
DPGA
TDA8798
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
DIGITAL OUTPUTS (A0 TO A7 AND B0 TO B7)
VOL
VOH
IOZ
LOW-level output voltage
HIGH-level output voltage
IO = 1 mA
IO = −1 mA
−
−
−
−
0.4
−
V
V
DDO − 0.4 V
V
output current in 3-state mode VO > 0.4 V;
VO < (VDDO − 0.4 V)
−20
+20
µA
ADC CLOCK TIMING
fCLK(max)
tW(CLKL)
maximum clock frequency
100
4.0
−
−
−
−
MHz
ns
clock pulse width LOW
duration
tW(CLKH)
clock pulse width HIGH
duration
4.0
−
−
ns
tr(CLK)
tf(CLK)
clock pulse rise time
clock pulse fall time
0.75
0.75
1
1
2
2
ns
ns
DATA TIMING (see Fig.4); FCLK = 100 MHZ; CDPGAC = 10 PF
td(s)(D)
td(Q)
data sampling delay time
data output delay time
−
−
tbf
tbf
tbf
−
ns
ns
ns
ns
ns
SR HIGH
SR LOW
SR HIGH
SR LOW
−
5.0
tbf
5.0
tbf
−
th(Q)
data output hold time
tbf
tbf
−
3-STATE OUTPUT DELAY TIMES (see Fig.6)
tdZH
tdZL
tdHZ
tdLZ
output delay enable at logic
HIGH
SR HIGH
SR LOW
SR HIGH
SR LOW
SR HIGH
SR LOW
SR HIGH
SR LOW
−
−
−
−
−
−
−
−
tbf
tbf
tbf
tbf
tbf
tbf
tbf
tbf
tbf
tbf
tbf
tbf
tbf
tbf
tbf
tbf
ns
ns
ns
ns
ns
ns
ns
ns
output delay enable at logic
LOW
output delay disable at logic
HIGH
output delay disable at logic
LOW
ADC REFERENCE OUTPUTS (VREF1 AND VREF2
)
Vo(ref)
Ro(ref)
ADC reference output voltage
−
−
1.24
−
V
ADC reference output
resistance
at Vo(ref)
−
10
Ω
Io(ref)(max)
Co(ref)
ADC reference maximum
output current
−
−
4.0
−
mA
pF
ADC reference output
capacitance
−
3
1999 Sep 16
13
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with
DPGA
TDA8798
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
COMMON MODE REFERENCE OUTPUTS (VOREF1 AND VOREF2
)
Vo(ref)
Ro(ref)
Io(ref)
reference output voltage
−
−
−
V
DDA − 0.42 V −
V
reference output resistance
at Vo(cm)(ref)
400
170
−
−
Ω
reference maximum output
current
at Vo(cm)(ref) − 0.2 V
µA
Co(ref)
reference output capacitance
−
−
3
pF
Serial Interface
DIGITAL INPUTS (SEN1, SEN2, SCLK, SDATA AND SMODE)
VIL
VIH
IIH
LOW-level input voltage
HIGH-level input voltage
HIGH-level input current
LOW-level input current
0
−
−
0
0
0.8
VDDD
+5
V
2.0
−5
−5
V
µA
µA
IIL
+5
GAIN CONTROL DATA TIMING (see Fig.4)
fSCLK(max)
tW(SCLKH)
maximum clock frequency
clock pulse width HIGH
clock pulse width LOW
SEN to SCLK set-up time
SEN to SCLK hold time
5
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
5
MHz
ns
20
20
5
tW(SCLKL)
ns
tsu(SEN-SCLK
)
ns
th(SEN-SCLK)
5
ns
tsu(SDATA-SCLK) SDATA to SCLK set-up time
th(SMODE-SCLK) SMODE to SCLK hold time
th(SMODE-SEN) SMODE to SEN hold time
5
ns
5
ns
5
ns
td(SEN-Q)
delay SEN rising edge to
change gain control register
value
−
ns
td(SCLK-Q)
delay SCLK rising edge to
change gain control register
value
−
−
5
ns
Note
1. Single-ended clock signal sources are allowed. The unused clock input is internally biased at the logical threshold
(1.65 V for nominal supply conditions), and should be correctly decoupled.
1999 Sep 16
14
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ahdnbok,uflapegwidt
parallel load mode
count-up/count-down mode
50%
50%
SMODE
SEN
t
h(SMODE-SEN)
t
h(SMODE-SCLK)
t
su(SEN-SCLK)
t
t
t
W(SCLKL)
su(SEN-SCLK)
W(SCLKH)
t
t
su(SEN-SCLK)
h(SEN-SCLK)
50%
SCLK
t
su(SDATA-SCLK)
up = 1
up = 1
down = 0
down = 0
SDATA
D5
(MSB)
D4
D3
D2
D1
D0
(LSB)
t
d(SEN-Q)
t
d(SCLK-Q)
SI GAIN
CONTROL
REGISTER
D5 D4 D3 D2 D1 D0 REG +/−1
REG +/−1
t
st(G-G)
10%
90%
DPGA
OUTPUTS
t
PD
MGM865
Fig.4 Timing diagram of serial interface.
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with
DPGA
TDA8798
t
W(CLKL)
t
W(CLKH)
HIGH
50 %
LOW
CLK
sample N
sample N + 1
sample N + 2
V
i
t
t
h(Q)
d(s)(D)
HIGH
50 %
LOW
DATA
A0 to A7
B0 to B7
DATA
N − 2
DATA
N − 1
DATA
N
DATA
N + 1
MGM866
t
d(Q)
Fig.5 Timing diagram for the ADC.
V
DDO
OE
0 V
50%
t
tdHZ
dZH
logic HIGH
90%
data
output
50%
t
tdLZ
dZL
high impedance
high impedance
data
output
50%
logic LOW
10%
TEST
S1
V
DDO
t
t
V
dLZ
DDO
A0 to A7
B0 to B7
3.3 kΩ
V
dZL
DDO
S1
TDA8798
t
t
GND
dHZ
dZH
10 pF
OE
GND
MGM868
Fig.6 Timing diagram and test conditions of 3-state output delay time.
16
1999 Sep 16
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with
DPGA
TDA8798
TEST AND APPLICATION INFORMATION
3.3 V
3.3 V
100 nF
3.3 V
100 nF
(1)
(1)
(1)
100 nF
V
V
V
SSA
SSD
SSO
V
SSD
V
SSD
100 nF
V
V
V
SSO
SSA
SSD
100 nF
(2)
100 nF
(2)
DPGA2N
DPGA2
B7
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
B7
B6
B5
B4
B3
B2
B1
B0
A0
A1
A2
A3
A4
A5
A6
A7
B6
B5
B4
B3
B2
B1
B0
A0
A1
A2
A3
A4
A5
A6
A7
2
(3)
68 pF
DPGAC2
V
3
SSA
V
V
ref2
SSA
4
(1)
100 nF
V
DDA2
3.3 V
V
5
(4)
100 nF
VIN2N
VIN2
6
IN2N
(4)
100 nF
V
7
IN2
V
SSA2
8
TDA8798HL
V
SSA1
9
(4)
(4)
100 nF
VIN1
V
10
11
12
13
14
15
16
IN1
100 nF
VIN1N
V
IN1N
V
DDA1
3.3 V
(1)
V
100 nF
ref1
V
SSA
DPGAC1
DPGA1
V
SSA
(3)
68 pF
DPGA1N
100 nF
(2)
100 nF
(2)
V
V
V
SSO
SSA
SSD
100 nF
V
SSD
SSA
(1)
(1)
(1)
100 nF
100 nF
100 nF
V
V
V
SSO
SSD
3.3 V
Analog and digital supplies must be separate and decoupled.
3.3 V
3.3 V
MGM867
(1) Supply decoupling capacitor must be placed as close as possible to the chip’s pin. Value may need changing depending on the external filter
characteristics.
(2) Capacitor may be replaced when an external filter is used with AC coupling.
(3) Capacitor value may be changed to adjust settling time between DPGA gain changes.
(4) Capacitor value may need changing depending on the high-pass cut-off frequency of the external filter.
Fig.7 Application diagram.
1999 Sep 16
17
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with
DPGA
TDA8798
INTERNAL PIN CONFIGURATIONS
handbook, halfpage
V
DDA2
handbook, halfpage
V
DDA1
0.5 V
VIN2
0.5 V
1 kΩ
VIN1
1 kΩ
VIN2N
VIN1N
V
SSA2
V
SSA1
MGM870
MGM869
Fig.8 DPGA1 analog input.
Fig.9 DPGA2 analog input.
handbook, halfpage
handbook, halfpage
V
V
DDA4
DDA3
V
V
oref2
oref1
0.42 V
0.42 V
BUF2
20
kΩ
BUF1
20
kΩ
BUF2N
BUF1N
V
V
SSA4
SSA3
MGM872
MGM871
Fig.10 ADC1 buffer input and Voref1 output.
Fig.11 ADC2 buffer input and Voref2 output.
handbook, halfpage
handbook, halfpage
V
V
DDD1
DDD2
CLK1
CLK2
CLK1N
CLK2N
20
kΩ
20
kΩ
1.4 V
1.4 V
V
V
SSD1
SSD2
MGM873
MGM874
Fig.12 ADC1 clock buffer input.
Fig.13 ADC2 clock buffer input.
1999 Sep 16
18
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with
DPGA
TDA8798
handbook, halfpage
handbook, halfpage
V
V
DDA4
DDA3
V
V
DDA2
DDA1
100 Ω
100 Ω
DPGA2
DPGA1
DPGA2N
DPGA1N
V
V
SSA2
SSA1
MGM876
MGM875
Fig.14 DPGA1 buffer output.
Fig.15 DPGA2 buffer output.
handbook, halfpage
handbook, halfpage
V
V
DDD1
DDD2
SMODE
SEN1
TE
DPGAEN
SEN2
SDATA
SCLK
V
V
SSD1
SSD2
MGM877
MGM878
Fig.16 Serial Interface inputs.
Fig.17 TE and DPGAEN inputs.
handbook, halfpage
V
DDO1
OE
handbook, halfpage
V
DDO2
OE
SR
A0N
A0
V
SSO2
MGM879
V
SSO1
MGM880
Fig.18 OE and SR inputs.
Fig.19 ADC1 A0 to A7 outputs.
1999 Sep 16
19
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with
DPGA
TDA8798
handbook, halfpage
V
DDO2
V
OE
DDA3
V
B0N
ref1
B0
1.24 V
V
SSA3
V
SSO2
FCE268
MGM881
Fig.20 ADC2 B0 to B7 outputs.
Fig.21 Vref1 output.
V
DDA4
V
ref2
1.24 V
V
SSA4
FCE269
Fig.22 Vref2 output.
1999 Sep 16
20
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with
DPGA
TDA8798
PACKAGE OUTLINE
LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm
SOT314-2
y
X
A
48
33
Z
49
32
E
e
H
A
E
2
E
A
(A )
3
A
1
w M
p
θ
b
L
p
pin 1 index
L
64
17
detail X
1
16
Z
v M
D
A
e
w M
b
p
D
B
H
v M
B
D
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.20 1.45
0.05 1.35
0.27 0.18 10.1 10.1
0.17 0.12 9.9 9.9
12.15 12.15
11.85 11.85
0.75
0.45
1.45 1.45
1.05 1.05
1.60
mm
0.25
0.5
1.0
0.2 0.12 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-12-19
97-08-01
SOT314-2
1999 Sep 16
21
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with
DPGA
TDA8798
SOLDERING
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
1999 Sep 16
22
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with
DPGA
TDA8798
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
REFLOW(1)
BGA, SQFP
not suitable
suitable
suitable
suitable
suitable
suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable(2)
PLCC(3), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
not recommended(3)(4)
not recommended(5)
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 Sep 16
23
Philips Semiconductors – a worldwide company
Argentina: see South America
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
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Brazil: see South America
Philippines: Philips Semiconductors Philippines Inc.,
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Slovakia: see Austria
Slovenia: see Italy
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Indonesia: PT Philips Development Corporation, Semiconductors Division,
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TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
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Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Uruguay: see South America
Vietnam: see Singapore
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Middle East: see Italy
Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
68
SCA
© Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545004/25/02/pp24
Date of release: 1999 Sep 16
Document order number: 9397 750 05466
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The TDA8798 is a dual 8-bit ADC with DPGA. The 100 Msps maximum sampling rate and 34 dBV DPGA gain range optimizes the ADC for
high dynamic range applications.
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End of Life information
Datahandbook system
l Dual 8-bit Analog-to-Digital Converter (ADC)
l Sampling rate up to 100 million samples per second (Msps)
l Dual 34 dBV 6-bit Digitally Programmable Gain Amplifier (DPGA) with optional power-off
l Optional external equalization filter with capacitive coupling between DPGA and ADC
l Serial Interface (SI) for DPGA gain control using either parallel load mode or count-up/count-down mode
l 3.3 V TTL/CMOS compatible I/O
l Differential or single-ended TTL/CMOS clock interface
Relevant Links
l AC or DC coupling for DPGA inputs.
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TDA8798
TDA8798
l High-dynamic range acquisition front-ends
l Digital data storage read channels.
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TDA8798 Dual 8-bit, 100 Msps A/D converter
with DPGA
16-Sep-99
Objective
Specification
24
195
Products, packages, availability and ordering
North American
Partnumber
Order code
(12nc)
Partnumber
marking/packing
package device status
buy online
-
Standard Marking * Reel Pack,
SMD, 13"
TDA8798HL/C1
9352 613 27118
SOT314 Samples available
SOT314 Samples available
SOT314 Samples available
SOT314 Samples available
Standard Marking * Reel Dry
Pack, SMD, 13"
TDA8798HLBD-T
TDA8798HLBD
9352 613 27518
9352 613 27551
9352 613 27557
Standard Marking * Tray Dry
Pack, Bakeable, Single
-
Standard Marking * Tray Dry
Pack, Bakeable, Multiple
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相关型号：
TDA8798HLBD-T
IC DUAL 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP64, PLASTIC, SOT-314-2, LQFP-64, Analog to Digital Converter
NXP
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