TDA9321_技术文档

INTEGRATED CIRCUITS

DATA SHEET

TDA9321H

I²C-bus controlled TV input

processor

1998 Dec 16

Preliminary speciﬁcation

File under Integrated Circuits, IC02

Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

FEATURES

• Multistandard Vision IF (VIF) circuit with Phase-Locked

Loop (PLL) demodulator

• Sound IF (SIF) amplifier with separate input for single

reference Quasi Split Sound (QSS) mode and separate

Automatic Gain Control (AGC) circuit

• Horizontal synchronization circuit with switchable time

constant for the PLL and Macrovision/subtitle gating

• AM demodulator without extra reference circuit

• Switchable group delay correction circuit which can be

used to compensate the group delay pre-correction of

the B/G TV standard in multistandard TV receivers

• Horizontal synchronization pulse output or clamping

pulse input/output

• Vertical count-down circuit

• Several (I²C-bus controlled) switch outputs which can

• Vertical synchronization pulse output

• Two-level sandcastle pulse output

• I²C-bus control of various functions

• Low dissipation.

be used to switch external circuits such as sound traps,

etc.

• Flexible source selection circuit with 2 external

CVBS inputs, 2 Luminance (Y) and Chrominance (C)

(or additional CVBS) inputs and 2 independently

switchable outputs

GENERAL DESCRIPTION

• Comb filter interface with CVBS output and Y/C input

• Integrated chrominance trap circuit

The TDA9321H (see Fig.1) is an input processor for

‘High-end’ television receivers. It contains the following

functions:

• Integrated luminance delay line with adjustable delay

time

• Multistandard IF amplifier with PLL demodulator

• QSS-IF amplifier and AM sound demodulator

• CVBS and Y/C switch with various inputs and outputs

• Integrated chrominance band-pass filter with switchable

centre frequency

• Multistandard colour decoder with 4 separate pins for

crystal connection and automatic search system

• Multistandard colour decoder which can also decode the

PALplus helper signal

• PALplus helper demodulator

• Integrated baseband delay line (64 µs)

• Possible blanking of the helper signals for PALplus and

EDTV-2

• Sync processor which generates the horizontal and

vertical drive pulses for the feature box

(100 Hz applications) or display processor

(50 Hz applications).

• Internal baseband delay line

• Two linear RGB inputs with fast blanking; the

RGB signals are converted to YUV signals before they

are supplied to the outputs; one of the RGB inputs can

also be used as YUV input

The supply voltage for the TDA9321H is 8 V.

ORDERING INFORMATION

TYPE

PACKAGE

NUMBER

NAME

DESCRIPTION

VERSION

TDA9321H

QFP64

plastic quad ﬂat package; 64 leads (lead length 1.95 mm);

SOT319-2

body 14 × 20 × 2.8 mm

1998 Dec 16

2

Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

QUICK REFERENCE DATA

SYMBOL

Supply

PARAMETER

MIN.

TYP.

MAX.

UNIT

V_P

I_P

supply voltage (pins V_P1and V_P2

)

7.2

8.0

8.8

V

supply current (pins V_P1and V_P2)

−

120

−

mA

Input signals

V_i(VIF)(rms)

VIF ampliﬁer sensitivity (RMS value)

SIF ampliﬁer sensitivity (RMS value)

CVBS or Y input signal (peak-to-peak value)

−

35

−

µV

V

V_i(SIF)(rms)

30

V_{i(CVBS/Y)(p-p)}

V_i(C)(p-p)

1.0

0.3

chrominance input signal (burst amplitude)

(peak-to-peak value)

V

V_i(RGB)(p-p)

RGB input signal (peak-to-peak value)

−

0.7

−

V

Output signals

V_o(VIFO)(p-p)

demodulated CVBS output signal (peak-to-peak value)

−

2.5

1.0

−

V

V_{o(CVBSPIP)(p-p)}CVBS output signal for Picture-In-Picture

(peak-to-peak value)

V_{o(CVBSTXT)(p-p)}CVBS output signal for teletext (peak-to-peak value)

−

0

−

2.0

−

5

−

V

I_o(TAGC)

tuner AGC output current

mA

mV

V

V_o(QSS)(rms)

V_o(AM)(rms)

V_o(V)(p-p)

V_o(U)(p-p)

V_o(Y)(b-w)

V_o(hor)

QSS output signal (RMS value)

demodulated AM sound output signal (RMS value)

−V output signal (peak-to-peak value)

−U output signal (peak-to-peak value)

Y output signal (black-to-white value)

horizontal pulse output

100

500

1.05

1.33

1.0

5

V

V_o(ver)

vertical pulse output

5

V

V_o(sc)(p-p)

subcarrier output signal (peak-to-peak value)

250

mV

1998 Dec 16

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Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

PINNING

SYMBOL PIN

DEC_DIG

CVBSTXT 34 CVBS output for teletext

DESCRIPTION

SYMBOL PIN

DESCRIPTION

SIF AGC decoupling

33 digital supply decoupling

DEC_SIF

VIF1

1

2

3

4

5

6

7

8

9

VIF input 1

DEC_BG

RI1

35 band gap decoupling

36 red input 1

VIF2

VIF input 2

DEC_VIF

QSS/AM

VIFPLL

VIFVCO1

VIFVCO2

GND1

VIFO

VIF AGC decoupling

combined QSS and AM sound output

VIF PLL ﬁlter

GI1

37 green input 1

BI1

38 blue input 1

RGB1

RGB2

RI2

39 RGB insertion input 1

40 RGB insertion input 2

41 red input 2

VIF VCO tuned circuit 1

VIF VCO tuned circuit 2

main supply ground

GI2

42 green input 2

10 VIF output

BI2

43 blue input 2

V_P1

11 positive supply 1 (+8 V)

12 group delay correction input

13 group delay correction output

14 internal CVBS input

15 AV input 1

GND3

V_P2

44 ground 3

GDI

45 positive supply 2 (+8 V)

46 serial clock input (I²C-bus)

47 serial data input/output (I²C-bus)

48 address select input (I²C-bus)

49 luminance output

GDO

SCL

CVBS_int

AV1

SDA

AS

CVBS1

AV2

16 CVBS input 1

YO

17 AV input 2

UO

50 U-signal output

CVBS2

SW0

18 CVBS input 2

19 switch output bit 0 (I²C-bus)

VO

51 V-signal output

LFBP

DEC_SEC

XTALA

XTALB

XTALC

XTALD

PH1LF

SCO

HA/CLP

52 loop ﬁlter burst phase detector

53 SECAM PLL decoupling

54 crystal A (4.433619 MHz)

55 crystal B (3.582056 MHz)

56 crystal C (3.575611 MHz)

57 crystal D (3.579545 MHz)

58 phase 1 loop ﬁlter

59 sandcastle pulse output

CVBS/Y3 20 CVBS or luminance input 3

C3

21 chrominance input 3

SW1

22 switch output bit 1 (I²C-bus)

CVBS/Y4 23 CVBS or luminance input 4

C4

24 chrominance input 4

SYS1

CVBSCF

SYS2

YCF

25 system output 1 for comb ﬁlter

26 CVBS output for comb ﬁlter

27 system output 2 for comb ﬁlter

28 luminance input from comb ﬁlter

29 chrominance input from comb ﬁlter

30 reference output (subcarrier)

31 digital supply ground

60 horizontal pulse output or clamp pulse

input/output

CCF

VA

61 vertical pulse output

62 tuner AGC output

63 SIF input 1

REFO

GND2

TAGC

SIF1

SIF2

CVBSPIP 32 CVBS output for Picture-In-Picture

64 SIF input 2

1998 Dec 16

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Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

handbook, full pagewidth

DEC

SIF

1

2

3

4

5

6

7

8

9

51 VO

50 UO

49 YO

48 AS

47 SDA

46 SCL

VIF1

VIF2

DEC

VIF

QSS/AM

VIFPLL

VIFVCO1

VIFVCO2

GND1

V

45

44 GND3

BI2

P2

43

42 GI2

RI2

VIFO 10

TDA9321H

V

11

41

P1

GDI 12

40 RGB2

39 RGB1

38 BI1

GDO 13

CVBS

14

int

AV1 15

CVBS1 16

AV2 17

37 GI1

36 RI1

DEC

35

34 CVBSTXT

DEC

BG

CVBS2 18

SW0 19

33

DIG

MGR474

Fig.2 Pin configuration.

6

1998 Dec 16

Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

The input of the ident circuit is connected to pin 14

FUNCTIONAL DESCRIPTION

Vision IF ampliﬁer

(see Fig.3). This has the advantage that the ident circuit

can also be made operative when a scrambled signal is

received (descrambler connected between pins 10

and 14). A second advantage is that the ident circuit can

be used when the VIF amplifier is not used (e.g. with

built-in satellite tuners). The video ident circuit can also be

used to identify the selected CBVS or Y/C signal.

The switching between the 2 modes can be realized with

bit VIM.

The VIF amplifier contains 3 AC-coupled control stages

with a total gain control range which is higher than 66 dB.

The sensitivity of the circuit is comparable with that of

modern IF-ICs.

The video signal is demodulated by a PLL carrier

regenerator. This circuit contains a frequency detector and

a phase detector. During acquisition the frequency

detector will tune the VCO to the correct frequency.

The initial adjustment of the oscillator is realized via the

I²C-bus. The switching between SECAM L and L’ can also

be realized via the I²C-bus. After lock-in the phase

detector controls the VCO so that a stable phase

relationship between the VCO and the input signal is

achieved. The VCO operates at twice the IF frequency.

The reference signal for the demodulator is obtained by

means of a frequency divider circuit. To get a good

performance for phase modulated carrier signals the

control speed of the PLL can be increased by bit FFI.

The TDA9321H contains a group delay correction circuit

which can be switched between the BG and a flat group

delay response characteristic. This has the advantage that

in multistandard receivers no compromise has to be made

for the choice of the SAW filter. Both the input and output

of the group delay correction circuit are externally

available so that the sound trap can be connected

between the VIF output and the group delay correction

input. The output signal of the correction circuit can be

supplied to the internal video processing circuit and to the

external SCART plug.

The IC has several (I²C-bus controlled) output ports which

can be used to switch sound traps or other external

components.

The AFC output is obtained by using the VCO control

voltage of the PLL and can be read via the I²C-bus.

For fast search tuning systems the window of the AFC can

be increased with a factor 3. The setting is realized with

bit AFW.

When the VIF amplifier is not used the complete VIF

amplifier can be switched off with bit IFO.

The AGC detector operates on top-sync and

Sound circuit

top-white-level. The demodulation polarity is switched via

the I²C-bus. The AGC detector time constant capacitor is

connected externally; this is mainly because of the

flexibility of the application. The time constant of the AGC

system during positive modulation is rather long, this is to

avoid visible variations of the signal amplitude. To improve

the speed of the AGC system a circuit has been included

which detects whether the AGC detector is activated every

frame period. When, during 3 field periods, no action is

detected the speed of the system is increased. For signals

without peak white information the system switches

automatically to a gated black level AGC. Because a black

level clamp pulse is required for this mode of operation the

circuit will only switch to black level AGC in the internal

mode.

The SIF amplifier is similar to the VIF amplifier and has a

gain control range of approximately 66 dB. The AGC

circuit is related to the SIF carrier levels (average level of

AM or FM carriers) and ensures a constant signal

amplitude to the AM demodulator and the QSS mixer.

The single reference QSS mixer is realized by a multiplier.

In this multiplier the SIF signal is converted to the

intercarrier frequency by mixing it with the regenerated

picture carrier from the VCO. The mixer output signal is

supplied to the output via a high-pass filter for attenuation

of the residual video signals. With this system a high

performance hi-fi stereo sound processing can be

achieved.

The AM sound demodulator is realized by a multiplier.

The modulated SIF signal is multiplied in phase with the

limited SIF signal. The demodulator output signal is

supplied to the output via a low-pass filter for attenuation

of the carrier harmonics.

The circuits contain a video identification (ident) circuit

which is independent of the synchronization circuit.

Therefore search tuning is possible when the display

section of the receiver is used as a monitor. However, this

ident circuit cannot be made as sensitive as the slower

sync ident circuit (bit SL). It is recommended to use both

ident outputs to obtain a reliable search system. The ident

output is supplied to the tuning system via the I²C-bus.

1998 Dec 16

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Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

The luminance output signal which is derived from the

incoming CVBS or Y/C signal can be varied in amplitude

by means of a separate gain setting control via the I²C-bus

control bits GAI1 and GAI0. The gain variation which can

be realized with these bits is −1 to +2 dB.

Video switches

The circuit has 3 CVBS inputs (1 internal and 2 externals)

and 2 Y/C inputs. The Y/C inputs can also be used as

additional CVBS inputs. The switch configuration is given

in Fig.3. The various sources can be selected via the

I²C-bus.

Colour decoder

The circuit can be set in a mode in which it automatically

detects whether a CVBS or a Y/C signal is supplied to the

Y/C inputs. In this mode the TV-standard identification first

takes place on the added Y/CVBS and the C input signal.

Then both chrominance input signal amplitudes are

checked once and the input signal with the highest burst

signal amplitude is selected. The result of the detection

can be read via the I²C-bus.

The colour decoder can decode PAL, NTSC and SECAM

signals. The PAL/NTSC decoder contains an

alignment-free crystal oscillator with 4 separate pins for

crystal connection, a killer circuit and two colour difference

demodulators. The 90° phase shift for the reference signal

is produced internally.

Because it is possible to connect 4 different crystals to the

colour decoder, all colour standards can be decoded

without external switching circuits. Which crystals are

connected to the decoder must be indicated via the

I²C-bus. The crystal connection pins which are not used

must be left open-circuit.

The IC has 2 inputs (AV1 and AV2) which can be used to

read the status levels of pin 8 of the SCART plug.

The information is available in the output status byte 02 in

bits D0 to D3.

The 3 outputs of the video switches (CVBSCF, CVBSTXT

and CVBSPIP) can be independently switched to the

various input signals. The names are just arbitrary and it is,

for instance, possible to use the CVBSCF signal to drive

the comb filter and the teletext decoder in parallel and to

supply the CVBSTXT signal to the SCART plug (via an

emitter follower).

The horizontal oscillator is calibrated by means of the

crystal frequency of the colour PLL. For a reliable

calibration it is very important that the crystal indication

bits XA to XD are not corrupted. For this reason

bits XA to XD can be read in the output bytes so that the

software can check the I²C-bus transmission.

The IC contains an Automatic Colour Limiting (ACL) circuit

which is switchable via the I²C-bus and prevents

oversaturation occuring when signals with a high

chrominance-to-burst ratio are received. The ACL circuit is

designed such that it only reduces the chrominance signal

and not the burst signal. This has the advantage that the

colour sensitivity is not affected by this function. The ACL

function is mainly intended for NTSC signals but it can also

be used for PAL signals. For SECAM signals the ACL

function should be switched off.

For comb filter interfacing the circuit has the CVBSCF

output, a 3rd Y/C input, a reference signal output REFO

and 2 control pins (SYS1 and SYS2) which switch the

comb filter to the standard of the incoming signal (as

detected by the ident circuit of the colour decoder). When

a signal is recognized which can be combed and the comb

filter is enabled by bit ECMB the Y/C signals coming from

the comb filter are automatically selected. This is indicated

via bit CMB in output status byte 02 (D5). For signals

which cannot be combed (such as SECAM or

black-to-white signals) the Y/C signals coming from the

comb filter are not selected.

The SECAM decoder contains an auto-calibrating PLL

demodulator which has two references: the 4.43 MHz

subcarrier frequency which is obtained from the crystal

oscillator which is used to tune the PLL to the desired

free-running frequency and the band gap reference to

obtain the correct absolute value of the output signal.

The VCO of the PLL is calibrated during each vertical

blanking period, when the IC is in search or SECAM mode.

Chrominance and luminance processing

The circuits contain a chrominance band-pass, a SECAM

cloche filter and a chrominance trap circuit. The filters are

realized by means of gyrator circuits and they are

automatically calibrated by comparing the tuning

frequency with the crystal frequency of the decoder.

The luminance delay line is also realized by means of

gyrator circuits. The centre frequency of the chrominance

band-pass filter is switchable via the I²C-bus so that the

performance can be optimized for ‘front-end’ signals and

external CVBS signals.

The circuit can also decode the PALplus helper signal and

can insert the various reference signals: set-ups and

timing signals which are required for the PALplus decoder

ICs.

The baseband delay line (TDA4665 function) is integrated.

1998 Dec 16

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Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

If required the IC can select the time constant depending

on the noise content of the incoming video signal.

RGB switch and matrix

The IC has 2 RGB inputs with fast switching. The switching

of the various sourcing is controlled via the I²C-bus and the

condition of the switch inputs can be read from the I²C-bus

status bytes. If the RGB signals are not synchronous with

the selected decoder input signal, an external clamp pulse

has to be supplied to the HA/CLP input. The IC must be set

in this mode via the I²C-bus. In that case the vertical pulse

is suppressed by switching the VA output in a

The free-running frequency of the oscillator is determined

by a digital control circuit which is locked to the reference

signal of the colour decoder. When the IC is switched on

the HA/CLP is suppressed and the oscillator is calibrated

as soon as all subaddress bytes have been sent. When the

frequency of the oscillator is correct the HA/CLP signal is

switched on again. When the coincidence detector

indicates an out-of-lock situation the calibration procedure

is repeated.

high-impedance off-state.

When an external RGB signal is mixed with the internal

YUV signal it is necessary to switch-off the PALplus

demodulation. To detect the presence of a fast blanking a

circuit is added which forces bits MACP and HD to zero if

a blanking pulse is detected in 2 consecutive lines. This

system is chosen to prevent switching-off at every spike

which is detected on the fast blanking input.

The VA pulse is obtained via a vertical count-down circuit.

The count-down circuit has various windows depending on

the incoming signal (50 or 60 Hz standard or

non-standard). The count-down circuit can be forced in

various modes via the I²C-bus. To obtain short switching

times of the count-down circuit during a channel change

the divider can be forced in the search window by means

of bit NCIN.

The IC has the possibility to use the RGB1 input as YUV

input. This function can be enabled by means of bit YUV in

subaddress 0A (D3). When switched to the YUV input the

input signals must have the same amplitude and polarity

as the YUV output signals. The Y signal has to be supplied

to the GI1 input, the U signal to the BI1 input and the

V signal to the RI1 input.

I²C-BUS SPECIFICATION

The slave address of the IC is given in Table 1. Bit A1 is

controlled via pin AS. When pin AS is connected to

pin GND2 it is at logic 0 and when connected to V_P2it is at

logic 1. When pin AS is left open-circuit it is connected to

ground via an internal pull-up resistor. The circuit operates

at clock frequencies of up to 400 kHz.

Synchronization circuit

The sync separator is preceded by a controlled amplifier

which adjusts the sync pulse amplitude to a fixed level.

These pulses are fed to the slicing stage which operates at

50% of the amplitude. The separated sync pulses are fed

to the phase detector and to the coincidence detector. This

coincidence detector is used to detect whether the line

oscillator is synchronized and can also be used for

transmitter identification. This circuit can be made less

sensitive with bit STM. This mode can be used during

search tuning to avoid the tuning system stopping at very

weak input signals. The PLL has a very high statical

steepness so that the phase of the picture is independent

of the line frequency.

Table 1 Slave address bits

A6

A5

A4

A3

A2

A1

A0

R/W

1

0

1

1/0

1

1/0

Start-up procedure

Read the status bytes until bit POR = 0 and send all

subaddress bytes. It is advised to check the I²C-bus

transmission by reading the output status bits SXA

to SXD. This ensures a good operation of the calibration

system of the horizontal oscillator. The horizontal output

signal is switched on when the oscillator is calibrated.

For the horizontal output pulse 2 conditions are possible:

• An HA pulse which has a phase and width which is

identical to the incoming horizontal sync pulse

Each time before the data in the IC is refreshed, the status

bytes must be read. If bit POR = 1, then the procedure

mentioned above must be carried out to restart the IC.

When this procedure is not carried out the horizontal

frequency may be incorrect after power-up or after a power

dip.

• A clamp pulse (CLP) which has a phase and width which

is identical to the clamp pulse in the sandcastle pulse.

The HA/CLP signal is generated by means of an oscillator

which is running at a frequency of 440 × f_hor. Its frequency

is divided by 440 to lock the first loop to the incoming

signal. The time constant of the loop can be forced by the

I²C-bus (fast or slow).

The valid subaddresses are 00 to 0E. Subaddresses

FE and FF are reserved for test purposes. Auto-increment

mode is available for the subaddresses.

1998 Dec 16

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Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

Inputs and outputs

Table 2 Input status bits

DATA BYTE

SUBADDRESS

FUNCTION

(HEX)

D7

D6

CM2

MACP HOB

D5

D4

D3

D2

D1

D0

Colour decoder 0

Colour decoder 1

Luminance

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

CM3

CM1

HBC

GAI1

A5

0

CM0

HD

GAI0

A4

XD

FCO

YD3

A3

0

XC

ACL

YD2

A2

XB

CB

YD1

A1

XA

BPS

YD0

A0

0

Hue control

Spare

0

Synchronization 0

Synchronization 1

Spare

FORF FORS

FOA

0

FOB

0

VIM

HO

0

POC

EMG

0

VID

NCIN

0

BSY

0

Video switches 0

Video switches 1

RGB switch

0

ECMB DEC3 DEC2 DEC1 DEC0

0

PIP2

0

PIP1

0

PIP0

0

YUV

0

TXT2 TXT1 TXT0

0

ECL

0

IE2

OS1

STM

A1

IE1

OS0

VSW

A0

Output switches

Vision IF

0

FFI

0

IFO

0

GD

A5

MOD

A4

AFW

A3

IFS

A2

Tuner takeover

Adjustment IF-PLL

L’FA

A6

A4

A3

A1

A0

INPUT CONTROL BITS

Table 4 Crystal indication

Table 3 Colour decoder mode

XA to XD

CONDITION

0

1

crystal not present

crystal present; note 1

CM3 CM2 CM1 CM0 DECODER MODE

XTAL

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

PAL/NTSC/SECAM

PAL/NTSC

PAL

A

B

Note

1. When a comb filter is used, the various crystals must

be connected to the IC as indicated in the pinning

diagram. This is required because the ident system

switches automatically to the comb filter when a signal

is identified which can be combed (correct

NTSC

SECAM

PAL/NTSC

PAL

combination of colour standard and crystal frequency).

For applications without comb filter only the crystal on

pin XTALA is important (4.43 MHz); to pins XTALB to

XTALD an arbitrary 3.5 MHz crystal can be connected.

NTSC

PAL/NTSC/SECAM A/B/C/D

PAL/NTSC

PAL

C

NTSC

C

PAL/NTSC

PAL

A/B/C/D

D

NTSC

1998 Dec 16

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Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

Table 5 Motion Adaptive Colour Plus (MACP)

Table 10 Chrominance band-pass centre frequency

MACP

MODE

CB

CENTRE FREQUENCY

0

1

internal 4.43 MHz trap used

0

1

f_c

external MACP chrominance ﬁltering used;

4.43 MHz trap bypassed and black set-up

200 mV; note 1

1.1 × f_c

Table 11 Bypass of chrominance baseband delay line

Note

BPS

DELAY LINE MODE

1. The black set-up will only be present in a norm sync

condition.

0

1

active

bypassed

Table 6 Helper output blanking (PALplus/EDTV-2)

Table 12 Gain luminance channel

GAI1 GAI0 GAIN SETTING

HOB

HBC

SNR

BLANKING

0

1

X⁽¹⁾

0

X⁽¹⁾off

X⁽¹⁾on

0

1

0

1

0

1

−1 dB

0 dB

1

0

1

off

on

+1 dB

+2 dB

1

Note

1. X = don’t care.

Table 13 Y-delay adjustment; note 1

YD0 to YD3

Y-DELAY

Table 7 PALplus helper demodulation active

YD3

YD2

YD1

YD0

YD3 × 160 ns +

YD2 × 160 ns +

YD1 × 80 ns +

YD0 × 40 ns

HD

CONDITIONS

0

1

off

on; PALplus mode with helper set-up 400 mV

and black set-up 200 mV; note 1

Note

1. For an equal delay of the luminance and chrominance

signal the delay must be set at a value of 280 ns

(YD3 to YD0 = 1011). This is only valid for a CVBS

signal without group delay distortions.

1. Black and helper set-up will only be present in a norm

sync condition.

Table 8 Forced colour on

Table 14 Forced ﬁeld frequency

FCO

MODE

FORF FORS

FIELD FREQUENCY

0

1

not active

active

0

auto (60 Hz when line not

synchronized)

0

1

0

1

forced 60 Hz; note 1

Table 9 Automatic colour limiting

keep last detected ﬁeld frequency

ACL

COLOUR LIMITING

auto (50 Hz when line not

synchronized)

0

1

not active

active

Note

1. When switched to this mode the divider will directly

switch to forced 60 Hz only.

1998 Dec 16

12

Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

Table 15 Phase 1 (ϕ₁) time constant; see also Table 57

Table 19 Blanked sync on pin YO

BSY

CONDITIONS

FOA

FOB

MODE

0

1

unblanked sync; note 1

blanked sync

0

1

0

1

0

1

normal

slow

slow or fast

fast

Note

1. Except for PALplus with black set-up.

Table 16 Video ident mode

Table 20 Condition of horizontal output

VIM

MODE

HO

0

CONDITIONS

0

1

ident coupled to internal CVBS (pin 14)

ident coupled to selected CVBS

clamp pulse available on pin HA/CLP

horizontal pulse available on pin HA/CLP

1

Table 17 Synchronization mode

Table 21 Enable ‘Macrovision/subtitle’ gating

POC

MODE

EMG

MODE

0

1

active

0

1

disable gating

enable gating

not active

Table 18 Video ident mode

Table 22 Vertical divider mode

VID

0

VIDEO IDENT MODE

NCIN

VERTICAL DIVIDER MODE

ϕ₁loop switched-on and off

0

1

normal operation

1

not active

switched to search window

Table 23 Video switch control

ECMB⁽¹⁾

DEC3

DEC2

DEC1

DEC0

SELECTED SIGNAL

CVBS_int

SIGNAL TO COMB

CVBS_int

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X⁽²⁾

0

CVBS1

1

CVBS2

0

CVBS3

1

Y3/C3

Y3 + C3

0

CVBS4

1

Y4/C4

Y4 + C4

0

AUTO Y3/C3; note 3

AUTO Y4/C4; note 3

YCF/CCF

CVBS3 or Y3 + C3

CVBS4 or Y4 + C4

CVBS_int

0

X⁽²⁾

0

YCF/CCF

CVBS1

1

YCF/CCF

CVBS2

0

YCF/CCF

CVBS3

0

YCF/CCF

CVBS4

0

AUTO COMB3; note 4

AUTO COMB4; note 4

CVBS3 or Y3 + C3

CVBS4 or Y4 + C4

0

1998 Dec 16

13

Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

Notes

1. When bit ECMB = 1 the subcarrier frequency is present on pin 30. The YCF and CCF signals coming from the comb

filter are only switched on when a signal is received that can be combed.

2. X = don’t care.

3. AUTO YC means the decoder switches between CVBS and Y/C depending on the presence of the burst signal on

these signals.

4. AUTO COMB means the decoder switches to Y/C mode if the burst is present on the C input and to the comb filter

output if the burst is present on the CVBS signal.

Table 24 Video switch outputs

Table 29 Output switches OS0 and OS1

TXT2

PIP2

TXT1

PIP1

TXT0

PIP0

OUTPUT SIGNAL TXT

OUTPUT SIGNAL PIP

OS0; OS1

CONDITIONS

0

1

output = LOW

output = HIGH

0

1

0

1

0

1

−

0

1

0

1

0

1

CVBS_int

CVBS1

CVBS2

CVBS3

Y3 + C3

CVBS4

Y4 + C4

Table 30 Fast ﬁlter IF-PLL

FFI

CONDITIONS

normal time constant

fast time constant

0

1

Table 31 IF circuit not active

Table 25 Enable YUV input (on RGB1 input)

IFO

MODE

YUV

MODE

0

1

normal operation of IF ampliﬁer

IF ampliﬁer switched off

0

1

RGB1 input active

YUV input active

Table 32 Group delay correction

Table 26 External RGB clamp mode

GD

GROUP DELAY CHARACTERISTIC

ECL

MODE

0

1

ﬂat

0

1

off; internal clamp pulse used

according to BG standard

on; external clamp pulse has to be supplied to

pin HA/CLP

Table 33 Modulation standard

MOD

MODULATION

Table 27 Enable fast blanking RGB1

0

1

negative

positive

IE1

FAST BLANKING

0

1

not active

active

Table 34 AFC window

AFW

AFC WINDOW

Table 28 Enable fast blanking RGB2

0

1

normal

IE2

0

FAST BLANKING

enlarged

not active

active

1

1998 Dec 16

14

Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

Table 35 IF sensitivity

Table 37 Video mute

IFS

IF SENSITIVITY

VSW

STATE

0

1

normal

0

1

normal operation

VIF signal switched off

reduced

Table 36 Search tuning mode

Table 38 PLL demodulator frequency shift

STM

MODE

L’FA

MODE

normal IF frequency

0

1

normal operation

reduced sensitivity of video ident circuit

0

1

frequency shift for L’ standard

Table 39 Output status bits

DATA BYTE

SUBADDRESS

(HEX)

FUNCTION

D7

D6

D5

D4

D3

D2

D1

D0

Output status bytes

00

01

02

03

POR

CD3

IN1

X⁽¹⁾

CD2

IN2

X⁽¹⁾

CD1

CMB

ID1

X⁽¹⁾

CD0

YC

SNR

SXD

S2A

IFI

FSI

SXC

S2B

PL

SL

IVW

SXA

S1B

AFB

SXB

S1A

AFA

ID3

ID2

ID0

Note

1. X = don’t care.

OUTPUT CONTROL BITS

Table 40 Power-on reset

POR

Table 43 Phase 1 (ϕ₁) lock indication

SL

INDICATION

0

1

not locked

locked

MODE

0

1

normal

power-down

Table 44 Condition vertical divider

Table 41 Signal-to-noise ratio of sync signal

IVW

STANDARD VIDEO SIGNAL

no standard video signal

0

1

SNR

SIGNAL-TO-NOISE RATIO

S/N > 20 dB

S/N < 20 dB

standard video signal in ‘narrow window’ or

standard TV norm (525 or 625 lines)

0

1

Table 45 Crystal indication (SXA to SXD)

Table 42 Field frequency indication

SXA to SXD

CONDITIONS

no crystal connected

crystal connected

FSI

FREQUENCY

0

1

0

1

50 Hz

60 Hz

1998 Dec 16

15

Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

Table 46 Colour decoder mode

CD3

CD2

CD1

CD0

STANDARD

XTAL

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

no colour standard identiﬁed

A/B/C/D

NTSC

A

B

C

D

A

−

PAL

NTSC

PAL

NTSC

PAL

NTSC

PAL

SECAM

illegal forced mode; note 1

Note

1. This mode is generated when trying (e.g. via software control) to force the decoder to a standard with a crystal which

is not connected to the IC.

Table 47 Indication RGB1/RGB2 insertion

Table 51 Output video identiﬁcation

IN1; IN2

RGB INSERTION

IFI

VIDEO SIGNAL

0

1

no insertion

full insertion

0

1

no video signal identiﬁed

video signal identiﬁed

Table 48 Condition YCF/CCF inputs from comb ﬁlter

Table 52 In-lock indication IF-PLL

CMB

CONDITION YCF/CCF INPUTS

not selected

selected

PL

0

CONDITIONS

0

1

PLL not locked

PLL locked

1

Table 53 AFC output

Table 49 Input signal condition; note 1

AFA

AFB

CONDITIONS

YC

0

CONDITIONS

CVBS signal available

Y/C signal available

0

1

0

1

0

1

outside window; too low

outside window; too high

in window; below reference

in window; above reference

1

Note

1. During the search mode for the colour system, bit YC

will indicate logic 1.

Table 50 Condition of AV1 and AV2 inputs

S1A; S1B;

CONDITIONS

S2A

S2B

0

1

0

1

0

no external source

external source with 4 : 3 input signal

external source with 16 : 9 input signal

1998 Dec 16

16

Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

Table 54 IC version indication

ID3

ID2

ID1

ID0

IC TYPE

0

1

0

1

TDA9321HN1

TDA9321HN2

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL

PARAMETER

supply voltage on pins V_P1and V_P2

storage temperature

CONDITIONS

MIN.

MAX.

9.0

UNIT

V_P

−

V

T_stg

T_amb

T_sld

T_j

−25

−

+150

+70

°C

V

operating ambient temperature

soldering temperature

for 5 s

260

junction temperature

−

150

V_es

electrostatic handling on all pins

notes 1 and 2

notes 1 and 3

−3000

−300

+3000

+300

V

Notes

1. All pins are protected against ESD by means of internal clamping diodes.

2. Human Body Model (HBM): R = 1.5 kΩ; C = 100 pF.

3. Machine Model (MM): R = 0 Ω; C = 200 pF.

THERMAL CHARACTERISTICS

SYMBOL

R_th(j-a)

PARAMETER

CONDITIONS

VALUE

50

UNIT

thermal resistance from junction to ambient

in free air

K/W

QUALITY SPECIFICATION

Quality specification in accordance with “SNW-FQ-611E”.

Latch-up performance

At an ambient temperature of 70 °C all pins meet the following specification:

• Positive stress test: I_trigger≥ 100 mA or V_pin≥ 1.5 × V_P(max)

• Negative stress test: I_trigger≤ −100 mA or V_pin≤ −0.5 × V_P(max)

.

1998 Dec 16

17

Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

CHARACTERISTICS

V_P= 8 V; T_amb= 25 °C; unless otherwise speciﬁed.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supply (pins V_P1and V_P2); note 1

V_P

I_P

supply voltage

(pins V_P1and V_P2

7.2

8.0

8.8

V

)

supply current

(pins V_P1and V_P2

−

120

960

140

mA

P_tot

total power dissipation

−

mW

Vision IF circuit

VISION IF AMPLIFIER INPUTS (PINS VIF1 AND VIF2)

V_i(rms)

input sensitivity (RMS value)

note 2

f_i(VIF)= 38.90 MHz

f_i(VIF)= 45.75 MHz

f_i(VIF)= 58.75 MHz

−

35

100

−

µV

mV

−

35

−

40

V_i(max)(rms)

maximum input signal

(RMS value)

150

200

R_i(dif)

C_i(dif)

∆G_v

differential input resistance

differential input capacitance

voltage gain control range

note 3

−

2

−

kΩ

pF

dB

−

3

−

70

75

80

PLL DEMODULATOR (PLL FILTER ON PIN VIFPLL); note 4

f_PLL

PLL frequency range

PLL catching range

PLL acquisition time

32

2.0

−

60

3.3

20

MHz

ms

f_cr(PLL)

t_acq(PLL)

∆f_VCO/∆T

2.7

−

VCO frequency dependency

with temperature

notes 5 and 6

via I²C-bus

−

±20 × 10⁻⁶K⁻¹

f_tune(VCO)

VCO tuning frequency range

3.0

23

3.7

29

4.2

33

MHz

∆f_DAC

frequency variation per step of

the DAC (A0 to A6)

kHz

f_shift

frequency shift

with bit L’FA

−

5.5

−

MHz

VIDEO AMPLIFIER OUTPUT (PIN VIFO); note 7

V_o(z)

zero signal output level

note 8

negative modulation

positive modulation

negative modulation

positive modulation

4.6

1.9

4.4

−

4.7

2.0

4.5

0

4.8

2.1

4.6

15

V

%

V_o(ts)

V_o(w)

∆V_o

top-sync level

white level

difference in amplitude

between negative and positive

modulation

Z_o(v)

video output impedance

−

50

−

Ω

I_bias(int)

internal bias current of NPN

1.0

−

mA

emitter follower output transistor

1998 Dec 16

18

Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

I_source(max)

B_v(−3dB)

maximum source current

−

5

mA

−3 dB bandwidth of

6

8

10

MHz

demodulated output signal

G_dif

differential gain

note 9

−

1.5

2.5

5

%

deg

%

V

ϕ_dif

differential phase

notes 6 and 9

note 10

−

NL_vid

V_clamp

N_clamp

N_ins

video non-linearity

2.5

6.0

1.5

2.7

white spot clamping level

noise inverter clamping level

−

note 11

−

V

noise inverter insertion level

(identical to black level)

−

V

d_blue

intermodulation at ‘blue’

notes 6 and 12

f = 0.92 or 1.1 MHz

f = 2.66 or 3.3 MHz

notes 6 and 12

60

66

−

dB

d_yellow

intermodulation at ‘yellow’

f = 0.92 or 1.1 MHz

f = 2.66 or 3.3 MHz

notes 6 and 13

56

60

56

49

−

62

66

60

53

5.5

2.5

−

dB

mV

−

S/N_W

weighted signal-to-noise ratio

65

−

S/N_UW

∆V_rc

unweighted signal-to-noise ratio notes 6 and 13

residual carrier signal note 6

−

∆V_rc(2H)

2nd harmonic of residual carrier note 6

signal

−

PSRR

power supply ripple rejection

at the output

−

40

−

dB

VIF AND TUNER AGC; note 14

Timing of VIF-AGC with a 2.2 µF capacitor (pin DEC_VIF

)

MVI

modulated video interference

60% AM for 1 to 100 mV;

0 to 200 Hz; system B/G

−

10

%

t_res

response time

VIF input signal

2

−

ms

amplitude increase of

52 dB; positive and

negative modulation

VIF input signal

amplitude decrease of

52 dB

negative modulation

positive modulation

−

50

−

ms

µA

nA

%

100

−

I_L

leakage current of the capacitor negative modulation

10

200

2

on pin 4

positive modulation

−

∆V_o(v)

change in video output signal

capacitor on pin 4 is

−

amplitude over 1 vertical period 0.5 µF

for peak white AGC at positive

modulation

1998 Dec 16

19

Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Tuner takeover point adjustment (via I²C-bus)

V_{strt(min)(rms)}

V_{strt(max)(rms)}

∆V_max/T

minimum start level

(RMS value)

−

0.4

0.8

mV

dB

maximum start level

(RMS value)

100

150

6

−

maximum variation with

temperature

T_amb= 0 to 70 °C

−

8

Tuner control output (pin TAGC)

V_o(max)maximum output voltage

maximum tuner gain;

note 3

−

9

V

V_o(sat)

output saturation voltage

minimum tuner gain;

I_o= 2 mA

300

mV

I_o(max)

I_L

maximum output current swing

leakage current

5

−

2

−

1

4

mA

µA

dB

for RF AGC

−

∆V_i

input signal variation

for complete tuner control 0.5

AFC OUTPUT (VIA I²C-BUS); note 15

RES_AFC

AFC resolution

−

2

−

bits

kHz

∆f_w

window sensitivity

normal window mode

enlarged window mode

65

80

240

100

300

195

VIDEO IDENTIFICATION OUTPUT (VIA I²C-BUS)

t_d

delay time

for identiﬁcation after the

AGC has stabilized on a

new transmitter

−

10

ms

Sound IF circuit

SOUND IF AMPLIFIER (PINS SIF1 AND SIF2)

V_i(rms)

input sensitivity (RMS value)

FM mode (−3 dB)

AM mode (−3 dB)

FM mode

−

30

70

140

2

70

100

−

µV

mV

kΩ

pF

−

V_i(max)(rms)

maximum input signal

(RMS value)

50

80

−

AM mode

−

R_i(dif)

differential input resistance

differential input capacitance

voltage gain control range

note 3

−

C_i(dif)

note 3

−

3

−

∆G_v

64

50

−

dB

α_ct(SIF-VIF)

crosstalk between inputs SIF

and VIF

−

1998 Dec 16

20

Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

QSS AND AM SOUND OUTPUT (PIN QSS/AM)

General

R_o

output resistance

DC output voltage

−

250

Ω

V_O

−

3.3

1.0

−

V

I_bias(int)

internal bias current of emitter

follower

0.7

mA

I_sink(max)

maximum AC and DC sink

current

−

0.7

2.0

−

mA

I_source(max)

maximum AC and DC source

current

QSS output signal

V_o(rms)

output signal amplitude

SC1 on; SC2 off

75

100

125

mV

(RMS value)

B_−3dB

−3 dB bandwidth

7.5

9

2

−

MHz

mV

∆V_r(SC)(rms)

residual IF sound carrier

(RMS value)

−

S/N_W

weighted signal-to-noise ratio

(SC1/SC2)

ratio of PC/SC1 at

VIF input of 40 dB or

higher; note 16

black picture

white picture

53/48 58/55

52/47 55/53

44/42 48/46

−

dB

6 kHz sine wave

(black-to-white

modulation)

250 kHz sine wave

(black-to-white

modulation)

44/25 48/30

−

dB

SC subharmonics

(f = 2.75 MHz ±3 kHz)

45/44 51/50

46/45 52/51

−

dB

SC subharmonics

(f = 2.87 MHz ±3 kHz)

AM output signal

V_o(rms)

output signal amplitude

54% modulation

400

500

600

mV

(RMS value)

THD

total harmonic distortion

−3 dB bandwidth

−

0.5

125

53

1.0

−

%

B_−3dB

S/N_W

100

47

kHz

dB

weighted signal-to-noise ratio

−

1998 Dec 16

21

Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Video switches and comb ﬁlter interface

VIDEO SWITCHES FOR CVBS, Y AND C SIGNALS

Signal on pins CVBS_int, CVBS1, CVBS2, CVBS/Y3 and CVBS/Y4

V_i(n)(p-p)

input voltage

note 17

−

1.0

1.43

V

(peak-to-peak value)

I_i(n)

input current

−

4

−

µA

kΩ

dB

Z_source(max)

α_sup(n)

maximum source impedance

−

1.0

−

suppression of non-selected

signals

f_i= 0 to 5 MHz; note 6

notes 3 and 18

50

Signal on pins C3 and C4

V_i(n)(p-p)

input voltage

(peak-to-peak value)

−

0.3

50

1.0

V

Z_i(n)

input impedance

−

kΩ

Signal on pin CVBSTXT

V_o(p-p)

output signal amplitude

1.6

2.0

2.4

V

(peak-to-peak value)

V_bl

black level

−

2.6

4

−

V

∆V_bl/∆T

black level dependency with

temperature

mV/K

Z_o

output impedance

−

250

1.2

Ω

Signal on pin CVBSPIP

V_o(p-p)

output signal amplitude

0.8

1.0

V

(peak-to-peak value)

V_bl

black level

−

3.6

9

−

V

∆V_bl/∆T

black level dependency with

temperature

mV/K

Z_o

output impedance

−

250

Ω

COMB FILTER INTERFACE; note 19

Signal on pin CVBSCF

V_o(p-p)

output signal amplitude

0.8

1.0

1.2

V

(peak-to-peak value)

output impedance

black level

Z_o

−

250

−

Ω

V_bl

3.6

9

V

∆V_bl/∆T

black level dependency with

temperature

−

mV/K

Signal on pin YCF

V_i(p-p)input voltage

−

1.0

4

1.43

V

(peak-to-peak value)

I_i

input current

−

µA

1998 Dec 16

22

Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Signal on pin CCF

V_i

Z_i

input voltage

input impedance

burst amplitude

−

0.3

50

1.0

V

−

kΩ

Reference signal output (pin REFO); note 20

V_o(p-p)

V_O(en)

V_O(dis)

output signal amplitude

(peak-to-peak value)

C_L= 15 pF

0.2

4.0

−

0.25

4.2

0.3

4.6

1.4

V

DC output level to enable

comb ﬁlter

DC output level to disable

comb ﬁlter

0.1

Switching levels of SYS1 and SYS2 outputs (pins SYS1 and SYS2); note 21

V_OH

HIGH-level output voltage

LOW-level output voltage

output sink current

4.0

−

5.0

0.1

−

5.5

0.4

−

V

V_OL

V

I_o(sink)

I_o(source)

2

mA

output source current

2

−

DETECTION OF STATUS LEVELS OF SCART PLUG PIN 8; note 22

V_det(int-ext)

V_det(ext-ext)

R_i

detection voltage between

internal and external (16 : 9)

source

2.0

5.3

60

2.2

5.5

100

2.4

5.7

−

V

detection voltage between

external (16 : 9) and external

(4 : 3) source

V

input resistance

kΩ

Chrominance and luminance ﬁlters and delay lines

CHROMINANCE TRAP CIRCUIT; note 23

f_trap

trap frequency

f

_osc±1%

MHz

dB

during SECAM reception

f_SC= 3.58 MHz

4.3 ±1.5%

B_−3dB

−3 dB bandwidth

2.6

3.2

2.8

3.4

3.1

−

3.0

3.6

3.3

−

f_SC= 4.43 MHz

during SECAM reception 2.9

26

CSR

colour subcarrier rejection

CHROMINANCE BAND-PASS CIRCUIT

f_c

centre frequency

bit CB = 0

bit CB = 1

−

f_osc

−

MHz

1.1f_osc

3

Q_bp

band-pass quality factor

CLOCHE FILTER

f_c

B

centre frequency

bandwidth

4.26

241

4.29

268

4.31

295

MHz

kHz

1998 Dec 16

23

Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Y-DELAY LINE

t_d

delay time

bits YD3 to YD0 = 1011;

note 6

crystal A

490

520

550

ns

crystal B, C or D

530

560

590

ns

t_d(tr)

tuning range delay time

bandwidth

with respect to

−280

−

+160

520/560 ns; 12 settings;

see Table 13

B

note 6

8

−

MHz

V

GROUP DELAY CORRECTION (PINS GDI AND GDO); note 24

V_i(GDI)(p-p)

input signal amplitude on

−

2.0

pin GDI (peak-to-peak value)

I_i(GDI)

input current on pin GDI

−

0.1

2.0

1.0

2.2

µA

V_o(GDO)(p-p)

output signal amplitude on

1.8

V

pin GDO (peak-to-peak value)

V_o(GDO)

output top-sync level on

pin GDO

−

2.4

5

−

V

∆V_o(GDO)/∆T top-sync level on pin GDO

−

mV/K

Ω

variation with temperature

Z_o(GDO)

output impedance on pin GDO

−

250

Colour demodulation part

CHROMINANCE AMPLIFIER

CR_ACC

ACC control range

note 25

26

−

dB

∆V_o(CRACC)

change in amplitude of the

output signals over CR_ACC

−

2

TH_ck(on)

hys_ck(off)

threshold colour killer ON

colour killer from

OFF to ON

−40

−

−35

dB

hysteresis colour killer OFF

note 6

strong signal;

S/N ≥ 40 dB

−

3

1

−

dB

noisy input signals

ACL CIRCUIT; note 26

C/C_ACL

ACL chrominance burst ratio

when the ACL starts to

operate

−

3.0

−

REFERENCE PART

Phase-locked loop; note 27

f_cr

catching range

phase shift

±360

±600

−

Hz

∆ϕ

for a ±400 Hz deviation of

the oscillator frequency;

note 6

−

2

deg

1998 Dec 16

24

Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Oscillator

TC_fosc

temperature coefﬁcient of

oscillator frequency

note 6

−

1

Hz/K

Hz

∆f_osc/V_P

oscillator frequency variation

with respect to the supply

voltage

V_P= 8 V ±10%; note 6

−

25

R_neg(min)

C_L(max)

minimum negative resistance

maximum load capacitance

−

1.0

15

kΩ

pF

HUE CONTROL; note 28

CR_hue

hue control range

63 steps; see Fig.4

±35

±40

−

deg

∆hue/∆V_P

hue dependency with respect

to the supply voltage

V_P±10%; note 6

−

0

∆hue/∆T

hue dependency with

temperature

T_amb= 0 to 70 °C; note 6

−

0

−

deg

DEMODULATORS

General

∆V/∆V

spread of signal amplitude ratio note 6

between standards

−1

−

+1

dB

PAL/NTSC demodulator

G_(B-Y)(R-Y)

gain between both

demodulators (B − Y) and

(R − Y)

1.60

1.78

650

1.96

B_−3dB(dem)

−3 dB bandwidth of

note 29

−

kHz

demodulators

∆V_o(rc)(p-p)

residual carrier output

(peak-to-peak value)

f = f_osc; (R − Y) output

f = f_osc; (B − Y) output

f = 2f_osc; (R − Y) output

f = 2f_osc; (B − Y) output

at (R − Y) output

−

5

mV

5

RR_H/2(p-p)

∆V_o/T

∆V_o/V_P

ϕ_e

H/2 ripple rejection

(peak-to-peak value)

25

output voltage variation with

temperature

note 6

−

0.1

−

%/K

dB/V

deg

output voltage variation with

respect to the supply voltage

0.3

±5

phase error in the demodulated note 6

signals

−

1998 Dec 16

25

Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

SECAM demodulator

f_blos

_blos/T

black level offset frequency

−

7

kHz

f

black level offset frequency

variation with temperature

−

60

Hz/K

f_p

pole frequency of de-emphasis

ratio pole and zero frequency

non-linearity

77

−

85

3

93

−

kHz

f_p/f_z

NL

V_cal

−

3

%

V

calibration voltage

3

4

5

Baseband delay line

∆V_o

variation of output signal

for adjacent time samples −0.1

at constant input signals

−

0.1

5

dB

∆V_r(clk)(p-p)

residual clock signal

(peak-to-peak value)

−

mV

t_d

delay

delayed signal

63.94 64.0

64.06

80

µs

ns

%

non-delayed signal

40

60

∆V_o

difference in output amplitude

when delay line is

bypassed or not (with

bit BPS)

−

5

PALplus helper demodulator

V_{o(helper)(p-p)}helper output voltage

610

380

686

400

770

420

mV

(peak-to-peak value)

V_su(helper)

helper set-up amplitude

only helper

lines 22 and 23

t_d(g)

group delay

within pass band

−

10

5

ns

ϕ_e(dem)

α_sup

demodulation phase error

suppression

including H/2 phase error

−

deg

dB

for modulated helper in

demodulated 0 to 1 MHz

signal

−36

−

∆V_r

residual signal

at 4.43 MHz signal

in ACC

−36

−

dB

ns

THD

total harmonic distortion

helper output timing to Y output

offset voltage

−

t_o(helper-Y)

V_offset

10

5

for demodulated mid grey

to inserted mid grey level;

mid grey line 23 to line 22

−

mV

t_{W(su)(helper)}

t_d

helper set-up pulse width

−

52.8

8.6

−

µs

delay between mid sync of input bits YD3 to YD0 = 1011;

and start of helper set-up

note 30

delay between start of black

set-up and start of helper set-up

only lines 22 and 23

−

30.8

2.6

−

µs

B_{helper(−3dB)}

−3 dB bandwidth of helper

MHz

baseband

1998 Dec 16

26

Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

RGB switch and YUV switch

RGB SWITCH (PINS RI1 TO BI1 AND RI2 TO BI2)

V_i(p-p)

input signal amplitude

(peak-to-peak value)

−

0.7

1.0

V

Z_source(max)

maximum source impedance

−

1.0

10

kΩ

∆V_bl(int-ext)

difference between black level

of internal and external signals

at the outputs

mV

I_i

input current

no clamping; note 3

note 6

−

0.1

0

1

µA

∆t_d

delay difference between the

three channels

20

ns

YUV INPUTS (WHEN ACTIVATED)

V_i(Y)(p-p)

V_i(U)(p-p)

V_i(V)(p-p)

Y input signal amplitude

(peak-to-peak value)

−

1.0

−

V

U input signal amplitude

(peak-to-peak value)

1.33

1.05

V input signal amplitude

(peak-to-peak value)

Z_source(max)

maximum source impedance

−

1.0

10

kΩ

∆V_bl(int-ext)

difference between black level

of internal and external signals

at the outputs

mV

I_i

input current

no clamping; note 3

−

0.1

1

µA

FAST BLANKING (PINS RGB1 AND RGB2)

V_i

input voltage

no data insertion

data insertion

−

0.4

−

V

0.9

−

V

V_i(max)

I_i

maximum input pulse

input current

3.5

0.2

tbf

V

−

mA

ns

∆t_d(blank-RGB)delay difference between

note 6

−

blanking and RGB signals

α_sup(int)

suppression of internal YUV

signals

data insertion;

f_i= 0 to 5 MHz; note 6

55

−

dB

ns

α_sup(ext)

suppression of external RGB

signals

no data insertion;

f_i= 0 to 5 MHz; note 6

−

t_d(blank-YUV)

delay between blanking input

and YUV outputs

tbf

LUMINANCE OUTPUT (PIN YO); note 31

V_o(p-p)

output signal amplitude

(peak-to-peak value)

black-to-white

−

1.0

−

V

V_o

output voltage during PALplus

−

0.8

−

V

∆V_bl(YUV-RGB)difference in black level

−

10

mV

between YUV and RGB mode

1998 Dec 16

27

Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

SYMBOL

Z_o

PARAMETER

output impedance

CONDITIONS

MIN.

TYP.

MAX.

250

UNIT

−

Ω

V_O

output DC voltage level

black level

2.8

7

3.0

−

3.2

V

B_RGB(−3dB)

−3 dB bandwidth of the RGB

−

MHz

switch circuit

S/N

signal-to-noise ratio

f_i= 0 to 5 MHz

−

52

−

dB

V_su(bl)

black set-up amplitude

bit MACP = 1 or

bit HD = 1

190

200

210

mV

t_W(su)(bl)

t_d

black set-up pulse width

−

52.8

8.8

−

µs

delay between mid sync at input note 30

and black set-up

V_offset

offset voltage

Y_blto re-inserted black

−

10

mV

G_(Y/CVBS-YO)

gain from internal Y/CVBS

to YO

1.35

1.08

1.43

1.14

1.50

1.20

bit MACP = 1 or

bit HD = 1

UO AND VO SIGNAL OUTPUTS (PINS UO AND VO)

V_o(VO)(p-p)

output voltage on pin VO

(peak-to-peak value)

standard EBU colour bar 0.88

standard EBU colour bar 1.12

1.05

1.33

1.25

1.58

V

V_o(UO)(p-p)

output voltage on pin UO

(peak-to-peak value)

Z_o

output impedance

−

250

2.6

10

Ω

V_O

output DC voltage level

2.2

−

2.4

−

V

∆V_bl(YUV-RGB)difference in black level

mV

between YUV and RGB mode

COLOUR MATRIX FROM RGB TO YUV

G

gain

from RI to YO

0.40

0.79

0.15

0.40

0.79

1.19

0.94

0.79

0.15

0.43

0.84

0.16

0.43

0.84

1.27

1.00

0.84

0.16

0.46

0.90

0.17

0.46

0.90

1.35

1.07

0.90

0.17

from GI to YO

from BI to YO

from RI to UO

from GI to UO

from BI to UO

from RI to VO

from GI to VO

from BI to VO

Horizontal and vertical synchronization

SYNC VIDEO INPUTS

V_sync

SL_hor

SL_vert

sync pulse amplitude

slicing level for horizontal sync note 32

slicing level for vertical sync note 32

note 3

35

50

35

300

55

350

60

mV

%

40

45

%

1998 Dec 16

28

Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

HORIZONTAL OSCILLATOR

f_fr

free-running frequency

−

15625

−

Hz

∆f_fr

spread on free-running

frequency

−

±2

%

∆f/∆V_P

∆f/T

frequency dependency with

respect to the supply voltage

V_P= 8.0 V ±10%; note 6

0.2

−

0.5

80

%

frequency variation with

temperature

T_amb= 0 to 70 °C; note 6

Hz

FIRST CONTROL LOOP (PIN PH1LF); note 33

f_hr(PLL)

f_cr(PLL)

S/N

PLL holding range

PLL catching range

signal-to-noise ratio

−

±0.9

17

±1.2

−

kHz

dB

note 6

±0.6

for the video input signal 15

at which the time

19

constant is switched

hys_sw

hysteresis at the switching point

sigma value of phase jitter

2

3

4

5

dB

ns

σ_ϕ

in automatic mode; ±3 σ

−

HORIZONTAL PULSE OUTPUT AND CLAMP PULSE INPUT/OUTPUT (PIN HA/CLP)

Switched to HA output (bit HO = 1)

V_OH

HIGH-level output voltage

LOW-level output voltage

output sink current

I_o(source)= 2 mA

I_o(sink)= 2 mA

4.0

−

5.0

0.2

−

5.5

0.4

−

V

V_OL

V

I_o(sink)

I_o(source)

t_W

2

mA

µs

output source current

pulse width

2

−

at nominal horizontal

frequency

4.6

4.7

4.8

t_d

delay between mid sync of input note 30

and mid HA pulse

0.3

0.45

0.6

µs

Switched to CLP output (bit HO = 0)

t_W

pulse width

at nominal horizontal

frequency

3.5

5.2

3.6

5.3

3.7

5.4

µs

t_d1

delay between start of CLP

pulse to start of black set-up

bit HD = 1 or

bit MACP = 1;

bits YD3 to YD0 = 1011;

at nominal horizontal

frequency

t_d2

delay between mid sync of input note 30

and start CLP pulse

3.0

3.2

3.4

µs

Switched to CLP input (bit ECL = 1)

V_IL

LOW-level input voltage

HIGH-level input voltage

clamping pulse width

0

−

0.6

5.5

−

V

V_IH

2.4

1.8

−

V

t_W(clamp)

3.5

µs

1998 Dec 16

29

Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

∆V_(clamp)(n)

clamping offset between

pins UO and VO

−

10

mV

Z_i

input impedance

3

−

MΩ

VERTICAL OSCILLATOR; note 34

f_fr

free-running frequency

50 Hz mode

−

50

60

−

Hz

60 Hz mode

−

Hz

f_lock

D/D

LR

frequency locking range

divider ratio

45

−

64.5

−

Hz

not locked

625/525

lines

locking range

488

−

722

lines/

frame

VERTICAL PULSE OUTPUT (PIN VA)

V_OH

HIGH-level output voltage

I_o(source)= 2 mA

I_o(sink)= 2 mA

4.0

−

5.0

0.2

−

5.5

0.4

−

V

V_OL

LOW-level output voltage

output sink current

output source current

pulse width

V

I_o(sink)

I_o(source)

t_W

2

mA

lines

µs

2

−

f_VA= 50 Hz

−

2.5

3.0

37.7

−

f_VA= 60 Hz

−

t_d

delay between start of vertical

sync of input and positive edge

of vertical pulse on pin VA

note 35

−

Z_o

output impedance

bit ECL = 1

3

−

MΩ

SANDCASTLE OUTPUT (PIN SCO)

General

V_z

zero level voltage

output sink current

0

0.5

1.0

V

I_o(sink)

−

mA

Horizontal/vertical blanking

V_o

output voltage level

2.2

−

2.5

0.7

10

2.8

−

V

I_o(source)

t_W(h)

t_d

output source current

mA

µs

horizontal blanking pulse width

−

delay between start horizontal

blanking and start clamping

pulse

−

6.4

−

Clamping pulse

V_o

output voltage level

output source current

pulse width

4.2

−

4.5

0.7

3.6

4.8

−

V

I_o(source)

t_W

mA

µs

−

1998 Dec 16

30

Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

SYMBOL

PARAMETER

CONDITIONS

MIN.

3.0

TYP.

MAX.

3.4

UNIT

µs

t_d

delay between mid sync of input note 30

and start of clamping pulse

3.2

I²C-BUS CONTROL

SCL AND SDA INPUTS/OUTPUTS (PINS SCL AND SDA)

V_i

input voltage range

0

−

5.5

1.5

−

V

V_IL

LOW-level input voltage

HIGH-level input voltage

LOW-level input current

HIGH-level input current

−

V

V_IH

3.5

−

V

I_IL

V_IL= 0 V

−10

10

µA

V

I_IH

V_IH= 5.5 V

I_OL(SDA)= 3 mA

−

V_OL(SDA)

LOW-level output voltage on

pin SDA

−

0.4

SW0 AND SW1 OUTPUTS (PINS SW0 AND SW1); note 36

V_OH

HIGH-level output voltage

LOW-level output voltage

output sink current

4.0

−

5.0

0.2

−

5.5

0.4

−

V

V_OL

V

I_O(sink)

I_O(source)

2

mA

output source current

2

−

Notes to the characteristics

1. The two supply pins V_P1and V_P2must be decoupled separately but they must be connected to a single power supply

to avoid too big differences between them.

2. On set AGC.

3. This parameter is not tested during production and is just given as application information for the designer of the

television receiver.

4. Loop filter bandwidth B_lpf= 60 kHz (natural frequency f_n= 15 kHz; damping factor d = 2; calculated with top sync

level as f_PLLinput signal level). LC-VCO circuit between pins 7 and 8: Q₀= 60; C_int= 30 pF.

5. The optimum temperature stability of the PLL can be obtained when a TOKO coil as given in Table 55 is applied.

6. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix

batches which are made in the pilot production period.

7. Measured at 10 mV (RMS value) top sync input signal.

8. So called projected zero point, i.e. with switched demodulator.

9. Measured in accordance with the test line given in Fig.5. For the differential phase test the peak white setting is

reduced to 87%.

The differential gain is expressed as a percentage of the difference in peak amplitudes between the largest and

smallest value relative to the subcarrier amplitude at blanking level.

The differential phase is defined as the difference in degrees between the largest and smallest phase angle.

10. This figure is valid for the complete video signal amplitude (peak white-to-black). See Fig.6.

11. The noise inverter is only active in the ‘strong signal mode’ (no noise detected in the incoming signal).

1998 Dec 16

31

Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

12. The input conditions and test set-up are given in Figs 8 and 9. The figures are measured with an input signal of

10 mV (RMS value). The intermodulation figures are defined:

V₀at 3.58 MHz

α_0.92= 20 log

α_2.76= 20 log

+ 3.6 dB ; α_0.92value at 0.92 MHz referenced to black or white signal;

; α_2.76value at 2.76 MHz referenced to colour carrier.

--------------------------------------

V₀at 0.92 MHz

V₀at 3.58 MHz

--------------------------------------

V₀at 2.76 MHz

13. Measured at an input signal of 10 mV (RMS value). The S/N is the ratio of black-to-white amplitude with respect to

the black level noise voltage (RMS value). B = 5 MHz. Weighted in accordance with CCIR 567.

14. The AGC response time also depends on the acquisition time of the PLL demodulator. The values given are valid

when the PLL is in lock.

15. The AFC control voltage is obtained from the control voltage of the VCO of the PLL demodulator. The tuning

information is supplied to the tuning system via the I²C-bus. Two bits are reserved for this function. The AFC value

is valid only when bit PL = 1.

16. The weighted S/N ratio is measured under the following conditions:

a) The VIF modulator must meet the following specifications:

• Incidental phase modulation for black-to-white jumps less than 0.5 degrees.

• QSS AF performance, measured with the television-demodulator AMF2 (audio output, weighted S/N ratio)

better than 60 dB (deviation 27 kHz) for 6 kHz sine wave black-to-white modulation.

• Picture-to-sound carrier ratio: PC/SC1 = 13 dB (transmitter).

b) The measurements must be carried out with the Siemens SAW filters G3962 for VIF and G9350 for SIF.

Input level for SIF at 10 mV (RMS value) with 27 kHz deviation.

c) The PC/SC ratio at the VIF input is calculated as the addition of the TV transmitter ratio and the SAW filter PC/SC

ratio. This PC/SC ratio is necessary to achieve the S/N_Wvalues as indicated.

17. Signal with negative-going sync. Amplitude includes sync pulse amplitude.

18. Indicated is a signal for a colour bar with 75% saturation (chrominance to burst amplitude ratio = 2.2 : 1).

19. When a signal is identified which can be combed (correct combination of colour standard and reference crystal) the

comb filter is switched to that mode via pins 25 and 27 and then the filter is activated by switching on the reference

carrier signal and connecting the output signals of the comb filter (pins 28 and 29) to the video processing circuits.

20. The subcarrier output signal can be used as a reference signal for external comb filter ICs (e.g. SAA4961). When

bit ECMB = 0 the subcarrier signal is suppressed and the DC level is LOW. When bit ECMB = 1 the output level is

HIGH and the subcarrier signal is present.

21. The outputs SYS1 and SYS2 can be used to switch the comb filter to the different colour standards (e.g. PAL-M,

PAL-N, PAL-B/G and NTSC-M) and are controlled by the colour decoder identification circuit.

The setting of the outputs for the various standards is given in Table 56.

22. For the detection of the status of the incoming SCART signal a voltage divider with a ratio of 2 : 3 has to be connected

between pin 8 of the SCART plug and the detection input. The impedance of the voltage divider should not be too

high-ohmic because of the input impedance of 100 kΩ.

23. When the decoder is forced to a fixed subcarrier frequency (via bits XA to XD or bit CM) the chrominance trap is

always switched on, also when no colour signal is identified. When 2 crystals are active the chrominance trap is

switched off if no colour signal is identified.

24. The typical group delay characteristic for the B/G standard is given in Fig.7.

25. At a chrominance input voltage of 660 mV (p-p) [colour bar with 75% saturation i.e. burst signal amplitude

300 mV (p-p)] the dynamic range of the ACC is +6 and −20 dB.

26. The ACL function can be activated by bit ACL. The ACL circuit reduces the gain of the chrominance amplifier for input

signals with a C/C_ACLwhich exceeds a value of 3.0.

1998 Dec 16

32

Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

27. All frequency variations are referenced to 3.58 or 4.43 MHz carrier frequency. All oscillator specifications are

measured with the Philips crystal series 9922 520 with a series capacitance C_s= 18 pF. The oscillator circuit is rather

insensitive to the spurious responses of the crystal. As long as the resonance resistance of the third overtone is

higher than that of the fundamental frequency the oscillator will operate at the correct frequency. The typical crystal

parameters for the crystal series are:

a) Load resonance frequencies f_L: 4.433619, 3.579545, 3.582056 and 3.575611 MHz; C_s= 20 pF.

b) Motional capacitance C_mot= 20.6 fF (4.43 MHz crystal) or C_mot= 14.7 fF (3.58 MHz crystal).

c) Parallel capacitance C_p= 5.0 pF.

The minimum detuning range can only be specified if both the IC and the crystal tolerances are known and therefore

the figures regarding catching range are only valid for the specified crystal series. In this figure tolerances of the

crystal with respect to the nominal frequency, motional capacitance and ageing have been taken into account and

have been counted for gaussic addition. Whenever different typical crystal parameters are used the following

equation might be helpful for calculating the impact on the tuning capabilities:

C_mot

Detuning range =

--------------------------

2

C_p

1 +

------

C_s

The resulting detuning range should be corrected for temperature shift and supply voltage deviation of both the IC

and the crystal. To guarantee a catching range of ±300 Hz on 4.43 MHz the minimum motional capacitance of the

crystal must have a value 13.2 fF or higher. For a catching range of 250 Hz with the 3.58 MHz crystal the minimum

motional capacitance must have a value of 9 fF. The actual series capacitance in the application should be

C_s= 18 pF to account for parasitic capacitances on-chip and off-chip.

28. The hue control is active for NTSC on the demodulated colour difference signals and for PALplus on the demodulated

helper signal.

29. This parameter indicates the bandwidth of the complete chrominance circuit including the chrominance band-pass

filter. The bandwidth of the low-pass filter of the demodulator is approximately 1 MHz.

30. This delay is partially caused by the low-pass filter at the sync separator input.

31. The internal luminance signal (signal which is derived from the incoming CVBS or Y/C signals) has a separate gain

control setting (controlled by the I²C-bus bits GAI1 and GAI0 and with a gain variation between −1 and +2 dB) which

can be used to get an optimal input signal amplitude for the feature box.

32. The slicing level is independent of sync pulse amplitude. The given percentage is the distance between the slicing

level and the black level (back porch). When the amplitude of the sync pulse exceeds the value of 350 mV the sync

separator will slice the sync pulse at a level of 175 mV above top sync. The maximum sync pulse amplitude is 4 V

(peak-to-peak value).

33. To obtain a good performance for both weak signal and VCR playback the time constant of the first control loop is

switched depending on the input signal condition and the condition of the I²C-bus. Therefore the circuit contains a

noise detector and the time constant is switched to the slow mode when too much noise is present in the signal. In the

fast mode during the vertical retrace time the phase detector current is increased 50% so that phase errors due to

head-switching of the VCR are corrected as soon as possible. Switching between the two modes can be automatic

or overruled by the I²C-bus.

The circuit contains a video identification circuit which is independent of the first control loop. This identification circuit

can be used to close or open the first control loop when a video signal is present or not present on the input. This

enables a stable On Screen Display (OSD) when just noise is present at the input. The coupling of the video

identification circuit with the first control loop can be revoked via the I²C-bus.

1998 Dec 16

33

Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

To prevent the horizontal synchronization being disturbed by anti copy signals such as Macrovision the phase

detector is gated during the vertical retrace period from line 11 to 17 (60 Hz signal) or from line 11 to 22 (50 Hz

signal) so that pulses during scan have no effect on the output voltage. The width of the gate pulse is approximately

22 µs. During weak signal conditions (noise detector active) the gating is active during the complete scan period and

the width of the gate pulse is reduced to 5.7 µs so that the effect of noise is reduced to a minimum.

The output current of the phase detector in the various conditions is shown in Table 57.

34. The timing pulses for the vertical ramp generator are obtained from the horizontal oscillator via a divider circuit.

This divider circuit has 3 modes of operation:

a) Search mode large window.

This mode is switched on when the circuit is not synchronized or when a non-standard signal [number of lines

per frame outside the range between 311 and 314 (50 Hz mode) or between 261 and 264 (60 Hz mode)] is

received. In the search mode the divider can be triggered between line 244 and line 361 (approximately

43.3 to 64.5 Hz).

b) Standard mode narrow window.

This mode is switched on when more than 15 succeeding vertical sync pulses are detected in the narrow window.

When the circuit is in the standard mode and a vertical sync pulse is missing the retrace of the vertical ramp

generator is started at the end of the window. Consequently, the disturbance of the picture is very small.

The circuit will switch back to the search window when, for 6 successive vertical periods, no sync pulses are

found within the window.

c) Standard TV-norm [divider ratio 525 (60 Hz) or 625 (50 Hz)].

When the system is switched to the narrow window a check is performed to establish whether the incoming

vertical sync pulses are in accordance with the TV-norm. When 15 standard TV-norm pulses are counted the

divider system is switched to the standard divider ratio mode. In this mode the divider is always reset at the

standard value even if the vertical sync pulse is missing.

When 3 vertical sync pulses are missed the system switches back to the narrow window and when also in this

window no sync pulses are found (condition 3 missing pulses) the system switches over to the search window.

The vertical divider needs some waiting time during channel-switching of the tuner. When a fast reaction of the

divider is required during channel-switching the system can be forced to the search window by means of bit NCIN in

subaddress 06.

35. The delay between the positive edge of VA and the positive edge of CLP (≈ negative edge of HA) after VA is 32.0 µs

for field 1 and 0 µs for field 2. Especially for PALplus signals the regenerated VA pulses must have a fixed and known

phase relation to the undisturbed VA pulses of the incoming video signal. This relationship must remain correct as

long as the vertical divider is in the standard mode (indirect sync mode). Therefore the coincidence window used

here must be a half line window. With a well defined phase relationship of the generated VA pulses to the generated

HA pulses a correct field identification and all the required timing signals referring to a certain line in each frame can

be generated externally in the PALplus decoder environment.

36. Pins 19 and 22 are for general purpose outputs that can be used to switch external circuits e.g. sound traps, etc.

They are controlled via the I²C-bus by bits OS0 (pin 19) and OS1 (pin 22).

1998 Dec 16

34

Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

Table 55 Coil data for the VIF-PLL demodulator (approximated coil values)

f_VIF

(MHz)

f_VCO

(MHz)

L

(nH)

TOKO SAMPLE NUMBER

REMARKS

38.9

45.75

58.75

77.8

91.5

150

100

70

P369INAS-159HM

P369INAS-160HM

P369INAS-161HM

5 mm; 5 km long; TC = 30 ±100 ppm/°C

117.5

Table 56 Switching conditions of pins SYS1 and SYS2

COLOUR STANDARD

PAL-M

SYS1

LOW

HIGH

SYS2

LOW

HIGH

LOW

HIGH

ACTIVE CRYSTAL

C

A

D

B

PAL-B, G, H, D and I

NTSC-M

PAL-N

Table 57 Output current of the phase detector in the various conditions

I²C-BUS COMMANDS

IC CONDITIONS

ϕ-1 CURRENT/MODE

VID

POC

FOA

FOB

IDENT

COIN

NOISE

SCAN

V-RETR

GATING

MODE

−

0

−

0

−

0

1

0

1

−

0

1

0

1

−

yes

−

yes

no

yes

no

yes

−

no

yes

−

180

30

270

30

no⁽¹⁾

yes

no

auto

slow

fast

180

30

270

30

−

yes

no

−

180

30

270

30

no

yes

−

yes

no

slow

fast

180

6

270

6

no

−

no

OSD

off

−

Note

1. When the Macrovision is active a gating is present during a part of the vertical retrace, pulse width 22 µs. In the other

gating conditions the pulse width is 5.7 µs and the gating is continuous.

1998 Dec 16

35

Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

MLA739

handbook, full pagewidth

50

(deg)

30

10

30

50

0

10

20

30

40

DAC (HEX)

Fig.4 Hue control curve.

MBC212

100%

92%

16 %

30%

for negative modulation

100% = 10% rest carrier

Fig.5 Video output signal.

36

1998 Dec 16

Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

handbook, full pagewidth

MBC211

100%

86%

72%

58%

44%

30%

µs

32 36 40 44 48 52 56 60 64

10 12

22 26

Fig.6 Test signal waveform.

MGR476

500

handbook, halfpage

t

d(g)

(ns)

400

300

200

100

0

1

2

3

4

5

f (MHz)

Fig.7 Group delay characteristic.

37

1998 Dec 16

Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

3.2 dB

handbook, full pagewidth

10 dB

13.2 dB

30 dB

SC CC

PC

SC CC

PC

MBC213

BLUE

YELLOW

SC = sound carrier, with respect to top sync level.

CC = colour carrier, with respect to top sync level.

PC = picture carrier, with respect to top sync level.

Fig.8 Input signal conditions.

PC

TEST

CIRCUIT

SPECTRUM

ANALYZER

SC

Σ

ATTENUATOR

gain setting

adjusted for blue

CC

MBC210

Fig.9 Test set-up intermodulation.

38

1998 Dec 16

Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

TEST AND APPLICATION INFORMATION

handbook, full pagewidth

TAGC

RGB1 RGB2

RI1 GI1 BI1

RI2 GI2 BI2

RI1 GI1 BI1 BL1 RI2 GI2 BI2 BL2

62 36 37 38 39

2

40 41 42 43

49

30 31 32 33

28

35 36 37 38

40

VIF1

VIF2

YIN

UIN

VIN

YO

UO

VO

RO

GO

BO

IF

SAW

FILTER

3

27

26

50

51

41

42

CVBS1

16

15

18

43

44

AV1

CVBS2

AV2

BCL

FEATURE

BOX

BLKIN

TDA9321H

TDA9330H

17

VDOA

VDOB

1

2

CVBS/Y3

C3

20

21

H

D

HA

VA

60

61

24

23

EWO

3

V

D

23

24

CVBS/Y4

C4

HOUT

HFB

8

13

34

32

26

28

29

MGR477

CVBSCF YCF CCF

COMB FILTER

CVBSTXT

CVBSPIP

Fig.10 Application diagram.

1998 Dec 16

39

Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

PACKAGE OUTLINE

QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm

SOT319-2

y

X

A

51

33

52

32

Z

E

e

A

2

H

A

E

(A )

3

E

A

1

θ

w M

p

pin 1 index

L

p

b

L

20

64

detail X

1

19

w M

Z

D

v

M

A

b

p

e

D

B

H

v

M

B

D

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

E

θ

1

2

3

p

E

p

D

max.

7^o

0^o

0.25 2.90

0.05 2.65

0.50 0.25 20.1 14.1

0.35 0.14 19.9 13.9

24.2 18.2

23.6 17.6

1.0

0.6

1.2

0.8

1.2

0.8

mm

3.20

0.25

1

1.95

0.2

0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

EIAJ

95-02-04

97-08-01

SOT319-2

1998 Dec 16

40

Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

The footprint must incorporate solder thieves at the

downstream end.

SOLDERING

Introduction to soldering surface mount packages

• For packages with leads on four sides, the footprint must

be placed at a 45° angle to the transport direction of the

printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

This text gives a very brief insight to a complex technology.

A more in-depth account of soldering ICs can be found in

our “Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).

During placement and before soldering, the package must

be fixed with a droplet of adhesive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured.

There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering is not always suitable

for surface mount ICs, or for printed-circuit boards with

high population densities. In these situations reflow

soldering is often used.

Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.

Reﬂow soldering

Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied

to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement.

Manual soldering

Fix the component by first soldering two

diagonally-opposite end leads. Use a low voltage (24 V or

less) soldering iron applied to the flat part of the lead.

Contact time must be limited to 10 seconds at up to

300 °C.

Several methods exist for reflowing; for example,

infrared/convection heating in a conveyor type oven.

Throughput times (preheating, soldering and cooling) vary

between 100 and 200 seconds depending on heating

method.

When using a dedicated tool, all other leads can be

soldered in one operation within 2 to 5 seconds between

270 and 320 °C.

Typical reflow peak temperatures range from

215 to 250 °C. The top-surface temperature of the

packages should preferable be kept below 230 °C.

Wave soldering

Conventional single wave soldering is not recommended

for surface mount devices (SMDs) or printed-circuit boards

with a high component density, as solder bridging and

non-wetting can present major problems.

To overcome these problems the double-wave soldering

method was specifically developed.

If wave soldering is used the following conditions must be

observed for optimal results:

• Use a double-wave soldering method comprising a

turbulent wave with high upward pressure followed by a

smooth laminar wave.

• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the

transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the

printed-circuit board.

1998 Dec 16

41

Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

Suitability of surface mount IC packages for wave and reﬂow soldering methods

SOLDERING METHOD

PACKAGE

WAVE

REFLOW⁽¹⁾

HLQFP, HSQFP, HSOP, SMS

PLCC⁽³⁾, SO

not suitable⁽²⁾

suitable

not recommended⁽³⁾⁽⁴⁾

LQFP, QFP, TQFP

SQFP

not suitable

not recommended⁽⁵⁾

SSOP, TSSOP, VSO

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package

cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the

Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

1998 Dec 16

42

Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled TV input processor

TDA9321H

DEFINITIONS

Data sheet status

Objective speciﬁcation

Preliminary speciﬁcation

Product speciﬁcation

This data sheet contains target or goal speciﬁcations for product development.

This data sheet contains preliminary data; supplementary data may be published later.

This data sheet contains ﬁnal product speciﬁcations.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or

more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation

of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation

is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these

products can reasonably be expected to result in personal injury. Philips customers using or selling these products for

use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such

improper use or sale.

PURCHASE OF PHILIPS I²C COMPONENTS

Purchase of Philips I²C components conveys a license under the Philips’ I²C patent to use the

components in the I²C system provided the system conforms to the I²C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

1998 Dec 16

43

Philips Semiconductors – a worldwide company

Argentina: see South America

Middle East: see Italy

Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. +61 2 9805 4455, Fax. +61 2 9805 4466

Tel. +31 40 27 82785, Fax. +31 40 27 88399

Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010,

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Fax. +43 160 101 1210

Tel. +64 9 849 4160, Fax. +64 9 849 7811

Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

Norway: Box 1, Manglerud 0612, OSLO,

220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773

Tel. +47 22 74 8000, Fax. +47 22 74 8341

Belgium: see The Netherlands

Brazil: see South America

Pakistan: see Singapore

Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,

Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474

Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,

Tel. +359 2 689 211, Fax. +359 2 689 102

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,

Tel. +48 22 612 2831, Fax. +48 22 612 2327

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,

Tel. +1 800 234 7381

Portugal: see Spain

Romania: see Italy

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,

72 Tat Chee Avenue, Kowloon Tong, HONG KONG,

Tel. +852 2319 7888, Fax. +852 2319 7700

Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. +7 095 755 6918, Fax. +7 095 755 6919

Colombia: see South America

Czech Republic: see Austria

Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Tel. +65 350 2538, Fax. +65 251 6500

Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. +45 32 88 2636, Fax. +45 31 57 0044

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Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. +358 9 615800, Fax. +358 9 61580920

South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,

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Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427

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Tel. +41 1 488 2741 Fax. +41 1 488 3263

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Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,

Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080

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TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,

209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,

Tel. +66 2 745 4090, Fax. +66 2 398 0793

Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. +353 1 7640 000, Fax. +353 1 7640 200

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,

TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007

Tel. +90 212 279 2770, Fax. +90 212 282 6707

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,

20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557

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Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,

TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077

MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

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Tel. +82 2 709 1412, Fax. +82 2 709 1415

Tel. +1 800 234 7381

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. +60 3 750 5214, Fax. +60 3 757 4880

Uruguay: see South America

Vietnam: see Singapore

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. +9-5 800 234 7381

Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. +381 11 625 344, Fax.+381 11 635 777

For all other countries apply to: Philips Semiconductors,

Internet: http://www.semiconductors.philips.com

International Marketing & Sales Communications, Building BE-p, P.O. Box 218,

5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

SCA60

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

Printed in The Netherlands

545104/750/01/pp44

Date of release: 1998 Dec 16

Document order number: 9397 750 04062


型号：	TDA9321
厂家：	NXP
描述：	I2C-bus controlled TV input processor I2C总线控制的TV输入处理器电视
文件：	总44页 (文件大小：252K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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