TDA9910HW/6 [NXP]
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC) direct/ultra high IF sampling; 12位，高达80 M采样/秒，模拟数字转换器（ ADC ）直接/超高IF采样
| 型号： | TDA9910HW/6 |
| 厂家： | 
NXP |
| 描述： | 12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC) direct/ultra high IF sampling |
| 文件： | 总21页 (文件大小：135K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TDA9910
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
direct/ultra high IF sampling
Rev. 02 — 9 December 2004
Objective data sheet
1. General description
The TDA9910 is a 12-bit Analog-to-Digital Converter (ADC) optimized for direct IF
sampling, and supporting the most demanding use conditions in ultra high IF radio
transceivers for cellular infrastructure and other applications such as wireless access
system, optical networking and fixed telecommunication. Thanks to its broadband input
capabilities, the TDA9910 is ideal for single and multiple carriers data conversion.
Operating at a maximum sampling rate of 80 Msample/s, analog input signals are
converted into 12-bit binary coded digital words. All static digital inputs are CMOS
compatible. All output signals are LVCMOS compatible. The TDA9910 offers the most
possible flexible acquisition control system thanks to its programmable Complete
Conversion Signal (CCS) that allows to adjust the delay of the acquisition clock.
Thanks to its internal front-end buffer, the TDA9910 offers the lowest input capacitance
(< 1 pF) and therefore the highest flexibility in front-end aliasing filter strategy.
Released in HTQFP48, it keeps the industry's smallest ADC of its category.
2. Features
■ 12-bit resolution
■ Direct IF sampling up to 370 MHz
■ 90 dB SFDR; 71 dB SNR (fi = 225 MHz; B = 5 MHz)
■ 72 dB SFDR; 66 dB SNR (fi = 175 MHz; B = Nyquist)
■ High-speed sampling rate up to 80 Msample/s
■ Programmable acquisition output clock (complete conversion signal)
■ Internal front-end buffer (input capacitance below 1 pF)
■ Full-scale controllable from 1.5 V to 2 V (p-p); continuous scale
■ Single 5 V power supply
■ 3.3 V LVCMOS compatible digital outputs
■ Binary or two’s-complement LVCMOS outputs
■ CMOS compatible static digital inputs
■ Only 2 clock cycles latency
■ Industrial temperature range from −40 °C to +85 °C
■ HTQFP48 package.
TDA9910
Philips Semiconductors
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
3. Applications
■ 2.5G and 3G cellular base infrastructure radio transceivers
■ Wireless access systems
■ Fixed telecommunication
■ Optical networking
■ WLAN infrastructure.
4. Ordering information
Table 1:
Ordering information
Package
Name
Type number
Sampling frequency
(Msample/s)
Description
Version
TDA9910HW/6 HTQFP48
TDA9910HW/8
plastic thermal enhanced thin quad flat package;
48 leads; body 7 × 7 × 1 mm; exposed die pad
SOT545-2
60
80
5. Block diagram
CLK
CLKN
TDA9910
2
DEL0 to
DEL1
CLOCK DRIVER
CCS
12
12
D0 to D11
OTC
LATCH
front-end
buffer
TRACK
AND
HOLD
IN
RESISTOR
LADDERS
ADC
CORE
INN
V
CCO
U/I
IR
LATCH
FSIN
VREF
REFERENCE
CMADC
REFERENCE
OUTPUTS
ENABLE
FSOUT
001aaa511
CMADC
DEC
CE_N
Fig 1. Block diagram.
9397 750 14418
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Objective data sheet
Rev. 02 — 9 December 2004
2 of 21
TDA9910
Philips Semiconductors
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
6. Pinning information
6.1 Pinning
n.c.
AGND1
IN
1
2
3
4
5
6
7
8
9
36 D0
35 D1
34 D2
33 D3
32 D4
31 D5
30 D6
29 D7
28 D8
27 D9
26 D10
25 D11
CMADC
INN
AGND1
DEC
TDA9910HW
n.c.
FSOUT
FSIN 10
n.c. 11
n.c. 12
DGND
001aaa512
Fig 2. Pin configuration.
6.2 Pin description
Table 2:
Symbol
Pin description
Pin
Type[1]
Description
n.c.
1
-
not connected
AGND1
IN
2
G
I
analog ground 1
analog input voltage
3
CMADC
INN
4
O
I
regulator common mode ADC output
complementary analog input voltage
analog ground 1
5
AGND1
DEC
n.c.
6
G
I/O
-
7
decoupling node
8
not connected
FSOUT
FSIN
n.c.
9
O
I
full-scale reference voltage output
full-scale reference voltage input
not connected
10
11
12
13
14
-
n.c.
-
not connected
n.c.
-
not connected
DEL1
I
complete conversion signal delay input 1
9397 750 14418
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Objective data sheet
Rev. 02 — 9 December 2004
3 of 21
TDA9910
Philips Semiconductors
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
Table 2:
Symbol
DEL0
Pin description …continued
Pin
Type[1]
Description
15
I
complete conversion signal delay input 0
digital supply voltage 2 (5.0 V)
digital ground 2
VCCD2(5V0) 16
P
DGND2
CE_N
OTC
17
18
19
20
G
I
chip enable input (CMOS level; active LOW)
control input for two’s complement output (active HIGH)
data output ground
I
OGND
G
P
VCCO(3V3) 21
OGND 22
VCCO(3V3) 23
data output supply voltage (3.3 V)
data output ground
G
P
data output supply voltage (3.3 V)
in-range output
IR
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
O
O
O
O
O
O
O
O
O
O
O
O
O
O
G
I
D11
D10
D9
data output bit 11 (MSB)
data output bit 10
data output bit 9
D8
data output bit 8
D7
data output bit 7
D6
data output bit 6
D5
data output bit 5
D4
data output bit 4
D3
data output bit 3
D2
data output bit 2
D1
data output bit 1
D0
data output bit 0 (LSB)
complete conversion signal output
digital ground 1
CCS
DGND1
CLKN
CLK
complementary clock input
clock input
I
VCCD1(5V0) 41
P
digital supply voltage 1 (5.0 V)
digital ground 1
DGND1
AGND2
42
43
G
G
P
analog ground 2
VCCA2(5V0) 44
VCCA1(5V0) 45
analog supply voltage 2 (5.0 V)
analog supply voltage 1 (5.0 V)
analog ground 1
P
AGND1
46
G
P
VCCA1(5V0) 47
analog supply voltage 1 (5.0 V)
analog ground 1
AGND1
DGND
48
G
exposed G
die pad
digital ground
[1] P: power supply; G: ground; I: input; O: output.
9397 750 14418
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Objective data sheet
Rev. 02 — 9 December 2004
4 of 21
TDA9910
Philips Semiconductors
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
7. Limiting values
Table 3:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VCCA
Parameter
Conditions
Min
−0.5
−0.5
−0.5
Max
+7.0
+7.0
+5.0
Unit
V
[1]
[1]
[2]
analog supply voltage
digital supply voltage
output supply voltage
supply voltage difference
VCCD
V
VCCO
V
∆VCC
V
V
V
CCA − VCCD
CCD − VCCO
CCA − VCCO
−1.0
−1.0
−1.0
0
+1.0
V
V
V
V
+4.0
+4.0
VIN, VINN
input voltage
referenced
to AGND
VCCA + 1
VCLK, VCLKN input voltage for differential
clock drive
referenced
to DGND
0
VCCD + 1
V
IO
output current
-
<tbd>
+150
+85
mA
°C
°C
°C
Tstg
Tamb
Tj
storage temperature
ambient temperature
junction temperature
−55
−40
-
150
[1] The supply voltages VCCA and VCCD may have any value between −0.5 V and +7.0 V provided that the
supply voltage differences ∆VCC are respected.
[2] The supply voltage VCCO may have any value between −0.5 V and +5.0 V provided that the supply voltage
differences ∆VCC are respected.
8. Thermal characteristics
Table 4:
Thermal characteristics
Symbol
Parameter
Conditions
Typ
Unit
[1]
[1]
Rth(j-a)
thermal resistance from junction
to ambient
36.2
K/W
Rth(j-c)
thermal resistance from junction
to case
14.3
K/W
[1] In compliance with JEDEC test board, in free air.
9. Characteristics
Table 5:
Characteristics
VCCA = 4.75 V to 5.25 V; VCCD = 4.75 V to 5.25 V; VCCO = 2.7 V to 3.6 V; AGND and DGND shorted together; Tamb = −40 °C
to +85 °C; VIN(p-p) − VINN(p-p) = 2.0 V − 0.5 dB; VFSIN = VCCA1 − 1.77 V; Vi(CM) = VCCA1 − 1.85 V; typical values measured at
VCCA = VCCD = 5 V, VCCO = 3.3 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified.
Symbol Parameter
Conditions
Test[1] Min
Typ
Max
Unit
Supplies
VCCA
analog supply voltage
digital supply voltage
output supply voltage
4.75
4.75
2.7
5.0
5.0
3.3
5.25
5.25
3.6
V
V
V
VCCD
VCCO
9397 750 14418
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Objective data sheet
Rev. 02 — 9 December 2004
5 of 21
TDA9910
Philips Semiconductors
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
Table 5:
Characteristics …continued
VCCA = 4.75 V to 5.25 V; VCCD = 4.75 V to 5.25 V; VCCO = 2.7 V to 3.6 V; AGND and DGND shorted together; Tamb = −40 °C
to +85 °C; VIN(p-p) − VINN(p-p) = 2.0 V − 0.5 dB; VFSIN = VCCA1 − 1.77 V; Vi(CM) = VCCA1 − 1.85 V; typical values measured at
VCCA = VCCD = 5 V, VCCO = 3.3 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified.
Symbol Parameter
Conditions
Test[1] Min
Typ
122
52
Max
Unit
mA
mA
mA
ICCA
ICCD
ICCO
analog supply current
digital supply current
output supply current
-
-
-
-
-
-
fCLK = 80 Msample/s;
fi = 175 MHz
29
Ptot
total power dissipation
fCLK = 80 Msample/s;
DC input
-
870
-
mW
Clock inputs: pins CLK and CLKN[2]
VIL LOW-level input voltage referenced to DGND;
CCD = 5 V
V
PECL mode
TTL mode
3.19
-
-
3.52
0.8
V
V
DGND
VIH
HIGH-level input voltage referenced to DGND;
CCD = 5 V
V
PECL mode
TTL mode
VCLK or
3.83
2.0
20
-
-
-
4.12
VCCD
-
V
V
IIL
LOW-level input current
HIGH-level input current
D
µA
V
CLKN = 3.52 V
VCLK or
CLKN = 2.00 V
VCLK or
CLKN = 3.83 V
VCLK or
CLKN = 0.80 V
1
-
-
-
nA
µA
nA
V
V
IIH
-
30
2
-
V
-
-
V
∆VCLK
differential AC input
voltage for switching
AC mode; DC voltage
level is 2.5 V
-
1.5
(VCLK − VCLKN
)
Ri
Ci
input resistance
fCLK = 80 Msample/s
fCLK = 80 Msample/s
-
-
6.3
1.1
-
-
kΩ
input capacitance
pF
Analog inputs: pins IN and INN
IIL
IIH
Ri
LOW-level input current
HIGH-level input current
input resistance
VFSIN = VCCA − 1.75 V
VFSIN = VCCA − 1.75 V
fi = 21.4 MHz
-
5
5
-
-
µA
µA
MΩ
MΩ
MΩ
fF
-
-
D
D
D
D
D
D
6.3
6.3
6.3
-
-
fi = 93 MHz
-
-
fi = 175 MHz
-
-
Ci
input capacitance
fi = 21.4 MHz
-
700
700
700
fi = 93 MHz
-
-
fF
fi = 175 MHz
-
-
fF
Vi(CM)
common mode input
voltage
VIN = VINN
output code = 2047
;
VCCA − 2
VCCA − 1.85 VCCA − 1.6
V
Digital inputs: pins OTC and CE_N
VIL
LOW-level input voltage
HIGH-level input voltage
DGND
-
-
0.3 × VCCD
V
V
VIH
0.7 × VCCD
VCCD
9397 750 14418
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Objective data sheet
Rev. 02 — 9 December 2004
6 of 21
TDA9910
Philips Semiconductors
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
Table 5:
Characteristics …continued
VCCA = 4.75 V to 5.25 V; VCCD = 4.75 V to 5.25 V; VCCO = 2.7 V to 3.6 V; AGND and DGND shorted together; Tamb = −40 °C
to +85 °C; VIN(p-p) − VINN(p-p) = 2.0 V − 0.5 dB; VFSIN = VCCA1 − 1.77 V; Vi(CM) = VCCA1 − 1.85 V; typical values measured at
VCCA = VCCD = 5 V, VCCO = 3.3 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified.
Symbol Parameter
Conditions
VIL = 0.8 V
VIH = 2.0 V
Test[1] Min
Typ
5
Max
Unit
µA
IIL
LOW-level input current
HIGH-level input current
-
-
-
-
IIH
5
µA
Digital inputs: pins DEL0 and DEL1
VIL
VIH
IIL
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
HIGH-level input current
DGND
-
0.3 × VCCD
V
0.7 × VCCD
-
VCCD
V
VIL = 0.8 V
VIH = 2.0 V
-
-
80
80
-
-
µA
µA
IIH
Voltage controlled regulator output: pin CMADC
Vo(CM)
common mode output
voltage
IL = 0 mA
-
-
V
CCA − 1.88 -
CCA − 1.91 -
V
V
IL = 2 mA
V
Reference voltage input: pin FSIN[3]
VFSIN
IFSIN
full-scale fixed voltage
input current
-
V
CCA − 1.84 -
V
-
1
-
µA
V
Vi(p-p)
input voltage
see Figure 5;
1.5
1.9
2.0
(peak-to-peak value)
Vi = VIN − VINN;
Vi(CM) = VCCA − 1.91 V
Full-scale voltage controlled regulator output: pin FSOUT
Vo(ref)
1.9 V full-scale output
voltage
IL = IFSIN
IL = 2 mA
-
-
V
CCA − 1.84 -
CCA − 1.87 -
V
V
V
Digital outputs: pins D11 to D0, IR and CCS
Output levels
VOL
VOH
IOZ
LOW-level output voltage IOL = 2 mA
DGND
-
DGND + 0.5
VCCO
V
HIGH-level output voltage IOH = −0.4 mA
VCCO − 0.5 -
V
output current in 3-state
output level between
−20
1
+20
µA
0.5 V and VCCO
Timing[4]
td(s)
sampling delay time
output hold time
CL = 10 pF
CL = 10 pF
CL = 10 pF
-
-
-
0.2
4
-
-
-
ns
ns
ns
th(o)
td(o)
output delay time
5
3-state output delay
tdZH
tdZL
tdHZ
tdLZ
enable HIGH
-
-
-
-
3
5
8
5
-
-
-
-
ns
ns
ns
ns
enable LOW
disable HIGH
disable LOW
Clock timing inputs: pins CLK and CLKN
fCLK(min) minimum clock frequency
-
-
-
8
-
Msample/s
Msample/s
fCLK(max) maximum clock frequency duty cycle 45 % to
65 %
80
tCLKH
tCLKL
clock pulse width HIGH
clock pulse width LOW
fi = 175 MHz
fi = 175 MHz
5.6
5.6
-
-
-
-
ns
ns
9397 750 14418
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Objective data sheet
Rev. 02 — 9 December 2004
7 of 21
TDA9910
Philips Semiconductors
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
Table 5:
Characteristics …continued
VCCA = 4.75 V to 5.25 V; VCCD = 4.75 V to 5.25 V; VCCO = 2.7 V to 3.6 V; AGND and DGND shorted together; Tamb = −40 °C
to +85 °C; VIN(p-p) − VINN(p-p) = 2.0 V − 0.5 dB; VFSIN = VCCA1 − 1.77 V; Vi(CM) = VCCA1 − 1.85 V; typical values measured at
VCCA = VCCD = 5 V, VCCO = 3.3 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified.
Symbol Parameter
Timing complete conversion signal: pin CCS; see Figure 6
Conditions
Test[1] Min
Typ
Max
Unit
tcd(o)
complete conversion
signal delay time
CL = 10 pF;
DEL0 = LOW;
DEL1 = HIGH
-
0.2
-
ns
CL = 10 pF;
DEL0 = HIGH;
DEL1 = LOW
-
-
1.3
2.4
-
-
ns
ns
CL = 10 pF;
DEL0 = HIGH;
DEL1 = HIGH
Analog signal processing (clock duty cycle 50 %; VIN − VINN = 1.9 V; Vref = VCCA3 − 1.75 V)
INL
integral non-linearity
fCLK = 20 Msample/s;
fi = 21.4 MHz
-
±1.6
-
-
LSB
LSB
DNL
differential non-linearity
fCLK = 20 Msample/s;
fi = 21.4 MHz; no
missing code
-
±0.4
guaranteed
Eoffset
offset error
VCCA = VCCD = 5 V;
-
5
-
mV
V
CCO = 3.3 V;
amb = 25 °C;
output code = 2047
T
EG
gain error amplitude
(spread from device to
device)
V
V
CCA = VCCD = 5 V;
CCO = 3.3 V;
-
-
0.8
-
-
%FS
MHz
T
amb = 25 °C
B
analog bandwidth[5]
fCLK = 80 Msample/s;
370
−3 dB; full-scale input
THD
total harmonic distortion
TDA9910/6[6]
fi = 21.4 MHz
fi = 93 MHz
fi = 175 MHz
fi = 21.4 MHz
fi = 93 MHz
fi = 175 MHz
fi = 21.4 MHz
fi = 93 MHz
fi = 175 MHz
fi = 21.4 MHz
fi = 93 MHz
fi = 175 MHz
-
-
-
-
-
-
-
-
-
-
-
-
−74
−72
−72
−76
−74
−70
67.5
67.2
66.5
67
-
-
-
-
-
-
-
-
-
-
-
-
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
total harmonic distortion
TDA9910/8[6]
SNR
signal-to-noise ratio
TDA9910/6[7]
dBc
dBc
signal-to-noise ratio
TDA9910/8[7]
dBc
66.7
66
dBc
dBc
9397 750 14418
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Objective data sheet
Rev. 02 — 9 December 2004
8 of 21
TDA9910
Philips Semiconductors
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
Table 5:
Characteristics …continued
VCCA = 4.75 V to 5.25 V; VCCD = 4.75 V to 5.25 V; VCCO = 2.7 V to 3.6 V; AGND and DGND shorted together; Tamb = −40 °C
to +85 °C; VIN(p-p) − VINN(p-p) = 2.0 V − 0.5 dB; VFSIN = VCCA1 − 1.77 V; Vi(CM) = VCCA1 − 1.85 V; typical values measured at
VCCA = VCCD = 5 V, VCCO = 3.3 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified.
Symbol Parameter
Conditions
fi = 21.4 MHz
fi = 93 MHz
fi = 175 MHz
fi = 21.4 MHz
fi = 93 MHz
fi = 175 MHz
Test[1] Min
Typ
76
73
73
79
75
72
86
Max
Unit
dBc
dBc
dBc
dBc
dBc
dBc
dB
SFDR
spurious free dynamic
range TDA9910/6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
spurious free dynamic
range TDA9910/8
ACPR
adjacent channel power
rejection
fi = 93 MHz; 5 MHz
channel spacing;
B = 4.096 MHz
fi = 175 MHz; 5 MHz
channel spacing;
B = 4.096 MHz
-
74
-
dB
d2(IM2)
second order
intermodulation
distortion[8]
fi1 = 21 MHz;
fi2 = 22 MHz
-
-
-
-
-
-
−81
−83
−80
−87
−88
−83
-
-
-
-
-
-
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
fi1 = 93 MHz;
fi2 = 96 MHz
fi1 = 174 MHz;
fi2 = 176 MHz
d3(IM3)
third order
intermodulation
distortion[8]
fi1 = 21 MHz;
fi2 = 22 MHz
fi1 = 93 MHz;
fi2 = 96 MHz
fi1 = 174 MHz;
fi2 = 176 MHz
[1] D = guaranteed by design;
C = guaranteed by characterization;
I = 100 % industrially tested.
[2] The circuit has two clock inputs: CLK and CLKN. There are 5 modes of operation:
a) PECL mode 1: (DC levels vary 1:1 with VCCD) CLK and CLKN inputs are at differential PECL levels.
b) PECL mode 2: (DC levels vary 1:1 with VCCD) CLK input is at PECL level and sampling is taken on the falling edge of the clock input
signal. A DC level of 3.65 V has to be applied on CLKN decoupled to GND via a 100 nF capacitor.
c) PECL mode 3: (DC levels vary 1:1 with VCCD) CLKN input is at PECL level and sampling is taken on the rising edge of the clock input
signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor.
d) Differential AC driving mode 4: When driving the CLK input directly and with any AC signal of minimum 1 V (p-p) and with a DC level
of 2.5 V, the sampling takes place at the falling edge of the clock signal.
When driving the CLKN input with the same signal, sampling takes place at the rising edge of the clock signal. It is recommended to
decouple the CLKN or CLK input to DGND via a 100 nF capacitor.
e) TTL mode 5: CLK input is at TTL level and sampling is taken on the falling edge of the clock input signal.
In that case CLKN pin has to be connected to the ground.
[3] The ADC input range can be adjusted with an external reference connected to FSIN pin. This voltage has to be referenced to VCCA.
[4] Output data acquisition: the output data is available after the maximum delay of td(o)
.
[5] The −3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave.
[6] The total harmonic distortion is obtained with the addition of the first five harmonics.
[7] The signal-to-noise ratio takes into account all harmonics above five and noise up to Nyquist frequency.
9397 750 14418
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Objective data sheet
Rev. 02 — 9 December 2004
9 of 21
TDA9910
Philips Semiconductors
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
[8] Intermodulation measured relative to either tone with analog input frequencies fi1 and fi2. The two input signals have the same amplitude
and the total amplitude of both signals provides full-scale to the converter (−6 dB below full-scale for each input signal).
d3(IM3) is the ratio of the RMS value of either input tone to the RMS value of the worst case third order intermodulation product; d2(IM2) is
the ratio of the RMS value of either input tone to the RMS value of the worst case second order intermodulation product.
Table 6:
Output coding with differential inputs
VIN(p-p) − VINN(p-p) = 1.9 V; VFSIN = VCCA1 − 1.77 V; typical values to AGND.
Code
VIN(p-p) VINN(p-p) IR
(V) (V)
Binary outputs
(D11 to D0)
Two’s complement outputs
(D11 to D0)
Underflow < 2.675 > 3.625
0
1
1
...
1
...
1
1
0
0000 0000 0000
0000 0000 0000
0000 0000 0001
...
1000 0000 0000
1000 0000 0000
1000 0000 0001
...
0
2.675
3.625
1
-
-
...
...
...
2047
...
3.15
...
3.15
...
0111 1111 1111
...
1111 1111 111
...
4094
4095
Overflow
-
-
1111 1111 110
1111 1111 111
1111 1111 111
0111 1111 110
0111 1111 111
0111 1111 111
3.625
2.675
> 3.625 < 2.675
Table 7:
Mode selection
Two’s complement output
(OTC)
Chip enable
input (CE_N)
Data output (D0 to D11; IR)
0
0
0
1
binary; active
1
X[1]
two’s complement; active
high-impedance
[1] X = don’t care.
n
CLK
50 %
t
d(o)
V
− 0.5 V
CCO
data
n − 1
data
n
data
n + 1
D0 to D11
0.5 V
t
h(o)
t
d(s)
IN
sample
sample
n + 1
sample
n + 2
sample
n + 3
sample
n + 4
n
001aaa513
Fig 3. Output timing diagram.
9397 750 14418
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Objective data sheet
Rev. 02 — 9 December 2004
10 of 21
TDA9910
Philips Semiconductors
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
001aaa514
0
(1)
power
spectrum
(dBc)
−40
(2)
(3)
(4)
(5)
(6)
−80
−120
−160
0
10
20
30
40
f (MHz)
i
(1) fi = 15 MHz; 0 dBc
(2) fi = 5.1 MHz; −73.64 dBc
(3) fi = 9.88 MHz; −82.6 dBc
(4) fi = 20.1 MHz; −77.26 dBc
(5) fi = 30 MHz; −71.73 dBc
(6) fi = 35.1 MHz; −71.68 dBc
THD (5H): 66.93 dBc
SFDR: −71.68 dBc
Fig 4. Single tone; fi = 175 MHz; fCLK = 80 Msample/s.
001aaa515
2.2
V
i(CM)
(V)
(3)
2.0
1.8
1.6
1.4
(2)
(1)
1.5
1.6
1.7
1.8
1.9
− V
2.0
(V)
V
CCA
FSIN
(1) Vi(CM) = 1.54 V; VCCA − VFSIN = 1.5 V
(2) Vi(CM) = 1.9 V; VCCA − VFSIN = 1.84 V
(3) Vi(CM) = 2.07 V; VCCA − VFSIN = 2.0 V
Fig 5. ADC full-scale; Vi(CM) as a function of VCCA − VFSIN
.
9397 750 14418
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Objective data sheet
Rev. 02 — 9 December 2004
11 of 21
TDA9910
Philips Semiconductors
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
The TDA9910 allows to modify the ADC full-scale. This could be done with FSIN
(full-scale input) according to Figure 5.
The TDA9910 generates an adjustable clock output called Complete Conversion Signal
(CCS), which can be used to control the acquisition of converted output data by the digital
circuit connected to the TDA9910 output data bus. Two logic inputs, DEL0 and DEL1 pins,
allow to adjust the delay of the edge of the CCS signal to achieve an optimal position in
the stable, usable zone of the data.
Table 8:
Complete conversion signal selection
DEL1 DEL0 CCS output
0
0
1
1
0
1
0
1
high-impedance
active, typical delay 0.2 ns
active, typical delay 1.3 ns
active, typical delay 2.4 ns
(1)
D0 to D11
t
cd(o)
CCS
001aaa516
(1) tcd(o) is referenced to the middle of the active data.
Fig 6. Complete conversion signal timing diagram.
10. Definitions
10.1 Static parameters
10.1.1 INL (integral non-linearity)
It is defined as the deviation of the transfer function from a best fit straight line (linear
regression computation). The INL of the code i is obtained from the equation:
VI(i) – VI(ideal)
INL(i) =
-------------------------------------------
S
where:
S is corresponding to the slope of the ideal straight line (code width); i is corresponding to
the code value.
10.1.2 DNL (differential non-linearity)
It is the deviation in code width from the value of 1 LSB.
VI(i + 1) – VI(i)
DNL(i) =
----------------------------------------
S
9397 750 14418
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Objective data sheet
Rev. 02 — 9 December 2004
12 of 21
TDA9910
Philips Semiconductors
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
where:
i = 0x(2n – 2)
10.2 Dynamic parameters
Figure 7 shows the spectrum of a single tone full-scale input sine wave with frequency ft,
conforming to coherent sampling (ft/fs = M/N, with M number of cycles and N number of
samples, M and N being relatively prime), and digitized by the ADC under test.
001aaa518
magnitude
a
1
SFDR
a
3
a
k
a
2
measured output range (MHz)
f /2
s
Fig 7. Single tone spectrum of full-scale input sine wave with frequency ft.
Remark: In the following equations, Pnoise is the power of the terms which include the
effects of random noise, non-linearities, sampling time errors, and “quantization noise”.
10.2.1 SINAD (signal-to-noise and distortion)
The ratio of the output signal power to the noise plus distortion power for a given sample
rate and input frequency, excluding the DC component:
Psignal
SINAD[dB] = 10log10
---------------------------------------
Pnoise + distortion
10.2.2 ENOB (effective number of bits)
It is derived from SINAD and gives the theoretical resolution an ideal ADC would require
to obtain the same SINAD measured on the real ADC. A good approximation gives:
SINAD – 1.76
ENOB =
----------------------------------
6.02
10.2.3 THD (total harmonic distortion)
The ratio of the power of the harmonics to the power of the fundamental. For k − 1
harmonics the THD is:
9397 750 14418
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Objective data sheet
Rev. 02 — 9 December 2004
13 of 21
TDA9910
Philips Semiconductors
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
Pharmonics
THD[dB] = 10log10
-------------------------
Psignal
where:
Pharmonics = a22 + a32 + … + a2k
Psignal = a21
The value of k is usually 6 (i.e. calculation of THD is done on the first 5 harmonics).
10.2.4 SNR (signal-to-noise ratio)
The ratio of the output signal power to the noise power, excluding the harmonics and the
DC component is:
Psignal
SNR[dB] = 10log10
----------------
Pnoise
10.2.5 SFDR (spurious free dynamic range)
The number SFDR specifies available signal range as the spectral distance between the
amplitude of the fundamental and the amplitude of the largest spurious harmonic and
non-harmonic, excluding DC component:
a1
SFDR[dB] = 20log10
------------------
max(S)
10.2.6 IMD2 (IMD3)
001aaa527
magnitude
IMD3
measured output range (MHz)
f /2
s
Fig 8. Spectral of dual tone input sine wave with frequency.
9397 750 14418
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Objective data sheet
Rev. 02 — 9 December 2004
14 of 21
TDA9910
Philips Semiconductors
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
From a dual tone input sinusoid (ft1 and ft2, these frequencies being chosen according to
the coherence criterion), the intermodulation distortion products IMD2 and IMD3
(respectively, 2nd and 3rd order components) are defined, as follows.
The ratio of the RMS value of either tone to the RMS value of the worst second (third)
order intermodulation product.
The total intermodulation distortion IMD is given by:
Pintermod
IMD[dB] = 10log10
----------------------
Psignal
where:
Pintermod = ai2m( f
) – a2im( f
) + a2im( f
) + a2im( f
) + …
+ 2 f
t2
– f
+ f
– f
– 2 f
+ f
t1
t2
t1
t1
t2
t1
t2
t1
… + a2im(2 f
) + a2im(2 f
t1
)
t2
t2
with a2im( f corresponding to the power in the intermodulation component at frequency ft.
)
t1
Psignal = a2f + a2f
t1
t2
9397 750 14418
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Objective data sheet
Rev. 02 — 9 December 2004
15 of 21
TDA9910
Philips Semiconductors
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
11. Application information
11.1 TDA9910 in 3G radio receivers
The TDA9910 has been proven in many 3G radio receivers with various operating
conditions regarding Input Frequency (IF), signal IF bandwidth and sampling frequency.
The TDA9910 provides with a maximum analog input signal frequency of 400 MHz. It
allows a significant cost-down of the RF front-end, from two mixers to only one, even in
multi-carriers architecture.
Table 9 describes some possible applications with the TDA9910 in high IF sampling
mode.
Table 9:
fi (MHz)
350
Examples of possible fi, fCLK, IF BW combinations supported
fCLK (Msample/s)
80
IF BW (MHz)[1] SNR (dB)
SFDR (dBc)
5.00
0.25
1.60
4.80
20.00
10.00
3.50
1.25
65
71
72
71
68
70
71
72
71
80
76
77
76
85
76
79
243.95
96
9.60
76.80
96
76.80
96
76.80
80
61.44
78.4
70
44.80
40.00
[1] IF bandwidth corresponds to the observed area on the ADC output spectrum.
For a dual carrier W-CDMA receiver, the most important parameters are sensitivity and
Adjacent Channel Selectivity (ACS). The sensitivity is defined as the lowest detectable
signal level. In W-CDMA, it can be far below the noise floor. This difference, between the
sensitivity and the noise floor, is defined by the Sensitivity-to-Noise Ratio (SENR). Its
value is negative due to the gain processing. The Adjacent Channel Power Ratio (ACPR)
is the difference between the full-scale −3 dB peak and the noise floor. It represents the
ratio of the adjacent-channel power and the average power level of the channel. The ACS
is defined by the sum of SENR and ACPR.
interfering channel
wanted channel
ACS
ACPR
noise floor
NF
SENR
sensibility
thermal noise
001aaa517
Fig 9. Adjacent channel sensitivity and ADC sensibility.
9397 750 14418
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Objective data sheet
Rev. 02 — 9 December 2004
16 of 21
TDA9910
Philips Semiconductors
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
11.2 Application diagram
ADT1_1WT
100 nF
n.c.
CLK
6
2
3
5
50 Ω
4
1
V
V
CCD
CCA
2.2 kΩ
V
CCD1
TL431CPK
100
nF
48 47 46 45 44 43 42 41 40 39 38 37
330 nF
D0
n.c.
ADT1_1WT
36
1
AGND1
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
35
34
33
32
31
30
29
28
27
26
25
2
3
5
6
2
100 Ω
IN
CMADC
INN
3
n.c.
4
100 nF
1
4
5
IN
AGND1
DEC
6
TDA9910HW
100 Ω
10 nF
7
n.c.
100 nF
8
FSOUT
FSIN
9
DGND
10
11
12
n.c.
n.c.
13 14 15 16 17 18 19 20 21 22 23 24
G1
10 nF
V
CCD
V
CCO
V
CCD
4700_000_S
(16)
10
(41)
analog ground
digital ground
100
nF
10
nF
330
nF
nF
V
CCA
(44)
4700_000_S
(45)
(47)
100
nF
10
nF
10
nF
10
nF
330
nF
HF70ACB
V
CCO
(21)
LM317MDT
(23)
IN
OUT
5 V
xx
3
2
4.7
µF
470
nF
240
Ω
100
nF
10
nF
10
nF
1
10 V
xx
ADJ
GND
300
Ω
coa002
Fig 10. Application diagram.
9397 750 14418
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Objective data sheet
Rev. 02 — 9 December 2004
17 of 21
TDA9910
Philips Semiconductors
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
12. Package outline
HTQFP48: plastic thermal enhanced thin quad flat package; 48 leads;
body 7 x 7 x 1 mm; exposed die pad
SOT545-2
c
y
exposed die pad side
X
D
h
36
25
A
24
37
Z
E
e
H
E
E
E
(A )
3
h
A
2
A
A
1
w M
θ
b
p
L
p
L
pin 1 index
13
48
detail X
1
12
w M
Z
v
v
M
M
A
B
D
b
p
e
D
B
H
D
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
θ
UNIT
A
A
A
b
c
D
D
E
E
e
H
H
E
L
L
v
w
y
Z
Z
1
2
3
p
h
h
D
p
D
E
max.
0.15 1.05
0.05 0.95
0.27 0.20 7.1
0.17 0.09 6.9
4.6
4.4
7.1
6.9
4.6
4.4
9.1
8.9
9.1
8.9
0.75
0.45
0.9
0.6
0.9
0.6
7°
0°
mm
1.2
0.25
0.5
1
0.2 0.08 0.08
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
03-04-07
04-01-29
SOT545-2
MS-026
Fig 11. Package outline SOT545-2 (HTQFP48).
9397 750 14418
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Objective data sheet
Rev. 02 — 9 December 2004
18 of 21
TDA9910
Philips Semiconductors
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
13. Revision history
Table 10: Revision history
Document ID
TDA9910_2
Release date Data sheet status
20041209 Objective data sheet
Change notice Doc. number
Supersedes
-
9397 750 14418 TDA9910_1
Modifications:
• Four values changed in Table 5 (Clock timing inputs)
9397 750 14418
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Objective data sheet
Rev. 02 — 9 December 2004
19 of 21
TDA9910
Philips Semiconductors
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
14. Data sheet status
Level Data sheet status[1] Product status[2] [3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
15. Definitions
16. Disclaimers
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
17. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
9397 750 14418
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Objective data sheet
Rev. 02 — 9 December 2004
20 of 21
TDA9910
Philips Semiconductors
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
18. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
8
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal characteristics. . . . . . . . . . . . . . . . . . . 5
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5
10
10.1
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Static parameters . . . . . . . . . . . . . . . . . . . . . . 12
INL (integral non-linearity) . . . . . . . . . . . . . . . 12
DNL (differential non-linearity) . . . . . . . . . . . . 12
Dynamic parameters. . . . . . . . . . . . . . . . . . . . 13
SINAD (signal-to-noise and distortion) . . . . . . 13
ENOB (effective number of bits) . . . . . . . . . . . 13
THD (total harmonic distortion). . . . . . . . . . . . 13
SNR (signal-to-noise ratio) . . . . . . . . . . . . . . . 14
SFDR (spurious free dynamic range) . . . . . . . 14
IMD2 (IMD3) . . . . . . . . . . . . . . . . . . . . . . . . . . 14
10.1.1
10.1.2
10.2
10.2.1
10.2.2
10.2.3
10.2.4
10.2.5
10.2.6
11
11.1
11.2
Application information. . . . . . . . . . . . . . . . . . 16
TDA9910 in 3G radio receivers. . . . . . . . . . . . 16
Application diagram . . . . . . . . . . . . . . . . . . . . 17
12
13
14
15
16
17
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 19
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 20
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Contact information . . . . . . . . . . . . . . . . . . . . 20
© Koninklijke Philips Electronics N.V. 2004
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 9 December 2004
Document number: 9397 750 14418
Published in The Netherlands
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