TDA9981BHL/15/C1 [NXP]
IC,TV/VIDEO CIRCUIT,AUDIO/VIDEO DECODER FOR MPEG,QFP,80PIN,PLASTIC;
| 型号： | TDA9981BHL/15/C1 |
| 厂家： | 
NXP |
| 描述： | IC,TV/VIDEO CIRCUIT,AUDIO/VIDEO DECODER FOR MPEG,QFP,80PIN,PLASTIC 商用集成电路 电视 |
| 文件： | 总41页 (文件大小：177K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TDA9981B
HDMI transmitter up to 150 MHz pixel rate with 3 × 8-bit video
inputs and 4 × I2S-bus with S/PDIF
Rev. 01 — 4 July 2008
Product data sheet
1. General description
The TDA9981B is an HDMI transmitter (which also supports DVI) that enables a 3 × 8-bit
RGB or YCbCr video stream (with a pixel rate up to 150 MHz for the TDA9981BHL/15
version), up to 4 I2S-bus audio streams (with an audio sampling rate up to 192 kHz) and
the additional information required by all the HDMI 1.2a standards.
In order to be compatible with most applications, the TDA9981B integrates a full
programmable input formatter and color space conversion block. The video input formats
accepted are YCbCr 4 : 4 : 4 (up to 3 × 8-bit), YCbCr 4 : 2 : 2 semi-planar (up to
2 × 12-bit), YCbCr 4 : 2 : 2 compliant with ITU656 and ITU656-like (up to 1 × 12-bit).
For ITU656-like formats, double edges are supported so that data can be sampled on
rising and falling edges.
The device can be controlled via an I2C-bus interface.
2. Features
I 3 × 8-bit video data input bus, CMOS and LV-TTL compatible
I Horizontal synchronization, vertical synchronization and Data Enable (DE) inputs or
VREF, HREF and FREF could be used for input data synchronization
I Pixel rate clock input can be made active on one or both edges (selectable by I2C-bus)
I The TDA9981B has 4 I2S-bus audio input channels and 1 S/PDIF channel; audio
sampling rate up to 192 kHz
I 250 MHz to 1.50 GHz HDMI transmitter operation
I Programmable input formatter and upsampler/interpolator allows input of any of the
4 : 4 : 4, 4 : 2 : 2 semi-planar, 4 : 2 : 2 ITU656 and ITU656-like formats
I Programmable color space converter:
N RGB to YCbCr
N YCbCr to RGB
I Controllable via I2C-bus
I Low power dissipation
I 1.8 V and 3.3 V power supplies
I Power-down mode
I Hard reset
TDA9981B
NXP Semiconductors
150 MHz pixel rate HDMI transmitter
3. Applications
I DVD players and recorders
I Set-Top Box (STB)
I AV receivers and amplifiers (repeater)
I Camcorders
I Digital still cameras
I Media players
I PVRs
I Media centers PCs, graphics add-in boards, notebook PCs
I Switches
4. Quick reference data
Table 1.
VDDA(FRO_3V3) = 3.0 V to 3.6 V; VDDA(PLL_3V3) = 3.0 V to 3.6 V; VDDH(3V3) = 3.0 V to 3.6 V;
DDD(3V3) = 3.0 V to 3.6 V; VDDC(1V8) = 1.65 V to 1.95 V; VPP = 0 V; Tamb = 0 °C to 85 °C.
Typical values are measured at VDDA(FRO_3V3) = VDDA(PLL_3V3) = VDDH(3V3) = VDDD(3V3) = 3.3 V;
DDC(1V8) = 1.8 V; VPP = 0 V and Tamb = 25 °C; unless otherwise specified.
Quick reference data
V
V
Symbol
Parameter
Conditions
Min
Typ
Max Unit
TDA9981BHL/8 and TDA9981BHL/15
VDDA(FRO_3V3) free running oscillator 3.3 V
analog supply voltage
3.0
3.0
3.3
3.3
3.6
3.6
V
V
VDDA(PLL_3V3) PLL 3.3 V analog supply
voltage
VDDD(3V3)
VDDH(3V3)
VDDC(1V8)
Tamb
digital supply voltage (3.3 V)
HDMI supply voltage (3.3 V)
core supply voltage (1.8 V)
ambient temperature
3.0
3.0
3.3
3.3
3.6
3.6
1.95
85
V
V
1.65 1.8
V
0
-
°C
TDA9981BHL/8; up to 81 MHz
[1]
[1]
[1]
fclk(max)
Pcons
Ptot
maximum clock frequency
81
-
-
-
MHz
mW
mW
mW
power consumption
235
369
14
288
438
19
total power dissipation
-
Ppd
power dissipation in
Power-down mode
-
TDA9981BHL/15; up to 150 MHz
[2]
[2]
[2]
fclk(max)
Pcons
Ptot
maximum clock frequency
150
-
-
MHz
mW
mW
mW
power consumption
-
-
-
381.5 468
515.5 618
total power dissipation
Ppd
power dissipation in
Power-down mode
14
19
[1] Worst case: video input format: 720p at 60 Hz (RGB 4 : 4 : 4 embedded sync), video output format:
720p at 60 Hz (YCbCr 4 : 4 : 4).
[2] Video input format: 1080p (RGB 4 : 4 : 4 embedded sync, rising edge), video output format:
1080p (RGB 4 : 4 : 4).
TDA9981B_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 4 July 2008
2 of 41
TDA9981B
NXP Semiconductors
150 MHz pixel rate HDMI transmitter
5. Ordering information
Table 2.
Ordering information
Type number
Package
Name
Description
Version
TDA9981BHL
LQFP80
plastic low profile quad flat package; 80 leads;
SOT315-1
body 12 × 12 × 1.4 mm
5.1 Ordering options
Table 3.
Survey of type numbers
Extended type number
Sampling frequency
(MHz)
Application
TDA9981BHL/8/C1xx
TDA9981BHL/15/C1xx
81
customer specific version
customer specific version
150
TDA9981B_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 4 July 2008
3 of 41
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx
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xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x
V
PP
V
V
DDC(1V8)
DDH(3V3)
V
DDA(PLL_3V3)
V
V
I2C_SCL I2C_SDA
43 44
A0 A1
41 40
RST_N
42
DDD(3V3)
DDA(FRO_3V3)
3
13, 48,
71
16, 45, 23
59, 74
38
28, 34
20
19
DDC_SCL
DDC_SDA
2
I C-BUS
HPD
MANAGEMENT
18
DDC-BUS
HARD
RESET
HPD
SLAVE
4 to 11
12
AP7 to AP0
ACLK
17
AUDIO
PROCESSING
IRQ
GENERATION
INT
YCbCr
DATA
ISLAND
PACKET
INFORMATION
FRAMES AND
PACKETS
27
26
TXC+
TXC−
68 to 70,
75 to 79
30
29
TX0+
VIDEO PROCESSING
RGB
VPA[7:0]
TX0−
57 and 58,
61 to 65,
67
HDMI
SERIALIZER
YCbCr 4 : 4 : 4
33
32
TX1+
VPB[7:0]
VPC[7:0]
COLOR
SPACE
3 × 8-bit
DOWNSAMPLING
TX1−
49 to 56
VIDEO
INPUT
PROCESSOR
FROM
4 : 4 : 4
TO
CONVERTER
RGB TO YUV
YUV TO RGB
2
36
35
VSYNC/VREF
HSYNC/HREF
DE/FREF
UPSAMPLING
TX2+
1
FROM
4 : 2 : 2
TO
(1)
4 : 2 : 2
(1)
TX2−
(4 : 4 : 4)
80
66
(1)
4 : 4 : 4
VCLK
TDA9981B
YCbCr 4 : 2 : 2
2 × 12-bit
ITU656 or ITU656-like
or 1 × 12-bit
14, 47,
72
15, 60,
73
25, 31,
37
22
39
46
SSA(PLL_1V8)
21
TM
24
001aai221
V
V
V
V
V
V
EXT_SWING
SSD
SSC
SSA(FRO_3V3)
SSA(PLL_3V3)
SSH
(1) Block can be bypassed.
Fig 1. Block diagram
TDA9981B
NXP Semiconductors
150 MHz pixel rate HDMI transmitter
7. Pinning information
7.1 Pinning
1
2
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
HSYNC/HREF
VSYNC/VREF
V
V
SSC
DDC(1V8)
3
V
VPB[6]
VPB[7]
VPC[0]
VPC[1]
VPC[2]
VPC[3]
VPC[4]
VPC[5]
VPC[6]
VPC[7]
PP
4
AP7
AP6
AP5
AP4
AP3
AP2
AP1
AP0
ACLK
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
TDA9981B
V
V
V
V
V
V
DDD(3V3)
DDD(3V3)
SSD
V
V
SSD
SSC
SSA(PLL_1V8)
DDC(1V8)
DDC(1V8)
INT
I2C_SDA
I2C_SCL
RST_N
A0
HPD
DDC_SDA
DDC_SCL
001aai219
Fig 2. Pin configuration
7.2 Pin description
Table 4.
Symbol
Pin description
Pin Type[1] Description
HSYNC/HREF 1
I
horizontal synchronization or reference input
VSYNC/VREF
VPP
2
3
I
vertical synchronization or reference input
P
programming voltage if OTP memory is available (must always be
connected to the ground of the digital core in normal operation)
AP7
AP6
AP5
4
5
6
I
I
I
audio port 7 input; auxiliary (AUX)
audio port 6 input; S/PDIF stream
audio port 5 input; optional master clock MCLK for S/PDIF
TDA9981B_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 4 July 2008
5 of 41
TDA9981B
NXP Semiconductors
150 MHz pixel rate HDMI transmitter
Table 4.
Pin description …continued
Symbol
AP4
Pin Type[1] Description
7
I
audio port 4 input; I2S-bus port 3
AP3
8
I
audio port 3 input; I2S-bus port 2
audio port 2 input; I2S-bus port 1
audio port 1 input; I2S-bus port 0
audio port 0 input; word select WS for I2S-bus
audio clock input; clock SCK for I2S-bus
supply voltage for input ports (3.3 V)
ground for input ports
AP2
9
I
AP1
10
11
12
13
14
15
16
17
I
AP0
I
ACLK
VDDD(3V3)
VSSD
I
P
G
G
P
O
VSSC
ground for digital core
VDDC(1V8)
INT
supply voltage for digital core (1.8 V)
interrupt output (open drain); warns the external microprocessor
that a special event has occurred; must be connected to a pull-up
resistor; 5 V tolerant
HPD
18
I
hot plug detect input; 5 V tolerant
DDC_SDA
19 I/O
DDC-bus data input/output (open drain); must be connected to a
pull-up resistor; 5 V tolerant
DDC_SCL
TM
20
21
O
I
DDC-bus clock output (open drain); must be connected to a pull-up
resistor; 5 V tolerant
internal test mode input (must be connected to the ground of the
digital core in normal operation)
VSSA(FRO_3V3) 22
VDDA(FRO_3V3) 23
EXT_SWING 24
G
P
I
analog ground for free running oscillator
analog supply voltage for free running oscillator (3.3 V)
external swing adjust input; a fixed resistor must be connected
between this pin and pin VDDH(3V3) to set the HDMI output swing
(see Section 8.14.1)
VSSH
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
G
O
O
P
O
O
G
O
O
P
O
O
G
P
G
I
ground for HDMI transmitter
TXC−
negative clock channel for HDMI output
positive clock channel for HDMI output
supply voltage for HDMI transmitter (3.3 V)
negative data channel 0 for HDMI output
positive data channel 0 for HDMI output
ground for HDMI transmitter
TXC+
VDDH(3V3)
TX0−
TX0+
VSSH
TX1−
negative data channel 1 for HDMI output
positive data channel 1 for HDMI output
supply voltage for HDMI transmitter (3.3 V)
negative data channel 2 for HDMI output
positive data channel 2 for HDMI output
ground for HDMI transmitter
TX1+
VDDH(3V3)
TX2−
TX2+
VSSH
VDDA(PLL_3V3)
VSSA(PLL_3V3)
A1
analog supply voltage for PLL (3.3 V)
analog ground reference for PLL
I2C-bus slave address input 1; bit 1
I2C-bus slave address input 0; bit 0
hard reset input; active LOW
A0
I
RST_N
I
TDA9981B_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 4 July 2008
6 of 41
TDA9981B
NXP Semiconductors
150 MHz pixel rate HDMI transmitter
Table 4.
Pin description …continued
Symbol
Pin Type[1] Description
I2C_SCL
43
I
I2C-bus clock input of device (open drain); must be connected to a
pull-up resistor; 5 V tolerant
I2C_SDA
44 I/O
I2C-bus data input/output of device (open drain); must be
connected to a pull-up resistor; 5 V tolerant
VDDC(1V8)
VSSA(PLL_1V8)
VSSD
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
P
G
G
P
I
supply voltage for digital core (1.8 V)
analog ground reference for PLL
ground for input ports
VDDD(3V3)
VPC[7]
VPC[6]
VPC[5]
VPC[4]
VPC[3]
VPC[2]
VPC[1]
VPC[0]
VPB[7]
VPB[6]
VDDC(1V8)
VSSC
supply voltage for input ports (3.3 V)
video port C input bit 7
I
video port C input bit 6
I
video port C input bit 5
I
video port C input bit 4
I
video port C input bit 3
I
video port C input bit 2
I
video port C input bit 1
I
video port C input bit 0
I
video port B input bit 7
I
video port B input bit 6
P
G
I
supply voltage for digital core (1.8 V)
ground for digital core
VPB[5]
VPB[4]
VPB[3]
VPB[2]
VPB[1]
VCLK
video port B input bit 5
I
video port B input bit 4
I
video port B input bit 3
I
video port B input bit 2
I
video port B input bit 1
I
video pixel clock input
VPB[0]
VPA[7]
VPA[6]
VPA[5]
VDDD(3V3)
VSSD
I
video port B input bit 0
I
video port A input bit 7
I
video port A input bit 6
I
video port A input bit 5
P
G
G
P
I
supply voltage for input ports (3.3 V)
ground for input ports
VSSC
ground for digital core
VDDC(1V8)
VPA[4]
VPA[3]
VPA[2]
VPA[1]
VPA[0]
DE/FREF
supply voltage for digital core (1.8 V)
video port A input bit 4
I
video port A input bit 3
I
video port A input bit 2
I
video port A input bit 1
I
video port A input bit 0
I
video data enable input or field reference input
[1] P = power supply; G = ground; I = input; O = output.
TDA9981B_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 4 July 2008
7 of 41
TDA9981B
NXP Semiconductors
150 MHz pixel rate HDMI transmitter
8. Functional description
The TDA9981B is designed to convert digital data (video and audio) into an HDMI or a
DVI stream. This HDMI stream can handle RGB, YCbCr 4 : 4 : 4 and YCbCr 4 : 2 : 2. The
TDA9981B can accept at its inputs any of the following video modes:
• RGB
• YCbCr 4 : 4 : 4
• YCbCr 4 : 2 : 2 semi-planar
• YCbCr 4 : 2 : 2 ITU656 and ITU656-like
It can also handle audio. The TDA9981B can accept at its inputs any of the following audio
buses:
• I2S-bus (4 lines): up to 8 audio channels
• S/PDIF (1 channel): L-PCM (IEC 60958) or compressed audio (IEC 61937)
8.1 System clock
The clock management is based on a set of two PLLs that generate the different clocks
required inside the chip:
• PLL double edge can generate a clock at twice the VCLK input frequency to capture
the data at the video input formatter.
• PLL serializer is a system clock generator, which enables the stream produced by the
encoder to be transmitted on the HDMI data channel at ten times the sampling rate or
more; see Section 8.14.2.
8.2 Video input processor
The TDA9981B has three video input ports VPA[7:0], VPB[7:0] and VPC[7:0].
The TDA9981B can reallocate and swap each of the 3 input channel ports by inverting the
bus and swapping each port.
The TDA9981B can be set to latch data at either the rising or falling edge or both.
The video input formats accept (see Table 5):
• RGB
• YCbCr 4 : 4 : 4 (up to 3 × 8-bit)
• YCbCr 4 : 2 : 2 semi-planar (up to 2 × 12-bit)
• YCbCr 4 : 2 : 2 compliant with ITU656 and ITU656-like (up to 1 × 12-bit)
TDA9981B_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 4 July 2008
8 of 41
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 5.
Inputs of video input formatter
Color
space
Format
Channels
Sync
Rising
edge
Falling
edge
Double
edge[1]
Transmission Max. pixel clock Max. input
Reference
input format on pin VCLK
(MHz)
format
RGB
4 : 4 : 4
3 × 8-bit
external
X
X
X
X
X
150
150
150
150
150
150
150
150
Table 6
external
X
X
X
X
X
embedded
embedded
external
YCbCr
YCbCr
4 : 4 : 4
3 × 8-bit
Table 7
Table 8
external
embedded
embedded
external
4 : 2 : 2
up to 1 × 12-bit
ITU656-like
ITU656-like
ITU656-like
ITU656-like
ITU656-like
ITU656-like
ITU656-like
54.054
54.054
27.027
54.054
54.054
27.027
148.5
480p/576p
480p/576p
480p/576p
480p/576p
480p/576p
480p/576p
1080p
external
external
X
X
Table 9
embedded
embedded
embedded
external
X
Table 10
X
Table 11
Table 12
up to 2 × 12-bit
semi-planar
X
X
external
X
X
148.5
1080p
embedded
embedded
SMPTE293M 148.5
SMPTE293M 148.5
1080p
Table 13
1080p
[1] Double edge means both rising and falling edges.
TDA9981B
NXP Semiconductors
150 MHz pixel rate HDMI transmitter
Table 6.
RGB 4 : 4 : 4 mappings
RGB 4 : 4 : 4 (3 × 8-bit) external synchronization single edge.
Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h.
Video port A
Pin
Video port B
RGB 4 : 4 : 4 Pin
Video port C
RGB 4 : 4 : 4 Pin
Control
RGB 4 : 4 : 4 Pin
RGB 4 : 4 : 4
HSYNC/HREF used
VSYNC/VREF used
VPA[0]
VPA[1]
VPA[2]
VPA[3]
VPA[4]
VPA[5]
VPA[6]
VPA[7]
B[0]
B[1]
B[2]
B[3]
B[4]
B[5]
B[6]
B[7]
VPB[0]
VPB[1]
VPB[2]
VPB[3]
VPB[4]
VPB[5]
VPB[6]
VPB[7]
G[0]
G[1]
G[2]
G[3]
G[4]
G[5]
G[6]
G[7]
VPC[0]
VPC[1]
VPC[2]
VPC[3]
VPC[4]
VPC[5]
VPC[6]
VPC[7]
R[0]
R[1]
R[2]
R[3]
R[4]
R[5]
R[6]
R[7]
DE/FREF
used
VCLK
HSYNC/HREF
VSYNC/VREF
DE/FREF
CONTROL
INPUTS
VPA[7:0]
VPB[7:0]
VPC[7:0]
B0
G0
R0
B1
G1
R1
B2
G2
R2
B3
G3
R3
...
...
...
Bxxx
Gxxx
Rxxx
Bxxx
Gxxx
Rxxx
001aag380
DE could also be generated from HSYNC/HREF and VSYNC/VREF
Fig 3. Pixel encoding in RGB 4 : 4 : 4 (rising edge) input
TDA9981B_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 4 July 2008
10 of 41
TDA9981B
NXP Semiconductors
150 MHz pixel rate HDMI transmitter
Table 7.
YCbCr 4 : 4 : 4 mappings
YCbCr 4 : 4 : 4 (3 × 8-bit) external synchronization single edge.
Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h.
Video port A
Video port B
Video port C
Control
Pin
YCbCr 4 : 4 : 4 Pin
YCbCr 4 : 4 : 4 Pin
YCbCr 4 : 4 : 4 Pin
YCbCr 4 : 4 : 4
used
VPA[0] CB[0]
VPA[1] CB[1]
VPA[2] CB[2]
VPA[3] CB[3]
VPA[4] CB[4]
VPA[5] CB[5]
VPA[6] CB[6]
VPA[7] CB[7]
VPB[0] Y[0]
VPB[1] Y[1]
VPB[2] Y[2]
VPB[3] Y[3]
VPB[4] Y[4]
VPB[5] Y[5]
VPB[6] Y[6]
VPB[7] Y[7]
VPC[0] CR[0]
VPC[1] CR[1]
VPC[2] CR[2]
VPC[3] CR[3]
VPC[4] CR[4]
VPC[5] CR[5]
VPC[6] CR[6]
VPC[7] CR[7]
HSYNC/HREF
VSYNC/VREF
DE/FREF
used
used
VCLK
HSYNC/HREF
VSYNC/VREF
DE/FREF
CONTROL
INPUTS
VPA[7:0]
VPB[7:0]
VPC[7:0]
Cb0
Y0
Cb1
Y1
Cb2
Cb3
Y3
...
...
...
Cbxxx
Yxxx
C xxx
B
Y2
Yxxx
Cr0
Cr1
Cr2
Cr3
Crxxx
Crxxx
001aai431
DE could also be generated from HSYNC/HREF and VSYNC/VREF
Fig 4. Pixel encoding in YCbCr 4 : 4 : 4 (rising edge) input
TDA9981B_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 4 July 2008
11 of 41
TDA9981B
NXP Semiconductors
150 MHz pixel rate HDMI transmitter
Table 8.
YCbCr 4 : 2 : 2 ITU656-like external synchronization single edge mappings
YCbCr : 2 : 2 ITU656-like external synchronization single edge.
Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h.
Video port A
Video port B
Pin YCbCr 4 : 2 : 2 (ITU656-like)
Control
Pin
YCbCr 4 : 2 : 2 (ITU656-like)
Pin
YCbCr 4 : 2 : 2
VPA[0] CB[0] Y0[0]
VPA[1] CB[1] Y0[1]
VPA[2] CB[2] Y0[2]
VPA[3] CB[3] Y0[3]
CR[0]
Y1[0]
VPB[0] CB[4] Y0[4] CR[4] Y1[4] HSYNC/HREF used
VPB[1] CB[5] Y0[5] CR[5] Y1[5] VSYNC/VREF used
CR[1]
Y1[1]
CR[2]
Y1[2]
VPB[2] CB[6] Y0[6] CR[6] Y1[6] DE/FREF
VPB[3] CB[7] Y0[7] CR[7] Y1[7]
VPB[4] CB[8] Y0[8] CR[8] Y1[8]
VPB[5] CB[9] Y0[9] CR[9] Y1[9]
VPB[6] CB[10] Y0[10] CR[10] Y1[10]
VPB[7] CB[11] Y0[11] CR[11] Y1[11]
used
CR[3]
Y1[3]
VPA[4]
VPA[5]
VPA[6]
VPA[7]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VCLK
HSYNC/HREF
VSYNC/VREF
DE/FREF
CONTROL
INPUTS
VPB[7:0]; VPA[3:0]
Cb0
Y0
Cr0
Y1
...
Crxxx
Yxxx
001aai434
Fig 5. Pixel encoding YCbCr 4 : 2 : 2 ITU656-like external synchronization single edge (rising edge) input
TDA9981B_1
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Product data sheet
Rev. 01 — 4 July 2008
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TDA9981B
NXP Semiconductors
150 MHz pixel rate HDMI transmitter
Table 9.
YCbCr 4 : 2 : 2 ITU656-like external synchronization double edge mappings
YCbCr 4 : 2 : 2 ITU656-like external synchronization double edge.
Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h.
Video port A
Pin YCbCr 4 : 2 : 2 (ITU656-like)
Video port B
Pin YCbCr 4 : 2 : 2 (ITU656-like)
Control
Pin
YCbCr 4 : 2 : 2
VPA[0] CB[0] Y0[0] CR[0] Y1[0] VPB[0] CB[4]
VPA[1] CB[1] Y0[1] CR[1] Y1[1] VPB[1] CB[5]
VPA[2] CB[2] Y0[2] CR[2] Y1[2] VPB[2] CB[6]
VPA[3] CB[3] Y0[3] CR[3] Y1[3] VPB[3] CB[7]
Y0[4]
Y0[5]
Y0[6]
Y0[7]
Y0[8]
Y0[9]
CR[4]
CR[5]
CR[6]
CR[7]
CR[8]
CR[9]
Y1[4]
Y1[5]
Y1[6]
Y1[7]
Y1[8]
Y1[9]
HSYNC/HREF used
VSYNC/VREF used
DE/FREF
used
VPA[4]
VPA[5]
VPA[6]
VPA[7]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VPB[4] CB[8]
VPB[5] CB[9]
VPB[6] CB[10] Y0[10] CR[10] Y1[10]
VPB[7] CB[11] Y0[11] CR[11] Y1[11]
VCLK
HSYNC/HREF
VSYNC/VREF
DE/FREF
CONTROL
INPUTS
VPB[7:0]; VPA[3:0]
Cb0
Y0
Cr0
Y1
...
Crxxx
Yxxx
001aai432
Fig 6. Pixel encoding YCbCr 4 : 2 : 2 ITU656-like external synchronization double edge (rising and falling) input
TDA9981B_1
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Product data sheet
Rev. 01 — 4 July 2008
13 of 41
TDA9981B
NXP Semiconductors
150 MHz pixel rate HDMI transmitter
Table 10. YCbCr 4 : 2 : 2 ITU656-like embedded synchronization single edge mappings
YCbCr 4 : 2 : 2 ITU656-like embedded synchronization single edge.
Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h.
Video port A
Pin YCbCr 4 : 2 : 2 (ITU656-like)
Video port B
Pin YCbCr 4 : 2 : 2 (ITU656-like)
Control
Pin
YCbCr 4 : 2 : 2
VPA[0] CB[0] Y0[0] CR[0] Y1[0] VPB[0] CB[4]
VPA[1] CB[1] Y0[1] CR[1] Y1[1] VPB[1] CB[5]
VPA[2] CB[2] Y0[2] CR[2] Y1[2] VPB[2] CB[6]
VPA[3] CB[3] Y0[3] CR[3] Y1[3] VPB[3] CB[7]
Y0[4]
Y0[5]
Y0[6]
Y0[7]
Y0[8]
Y0[9]
CR[4]
CR[5]
CR[6]
CR[7]
CR[8]
CR[9]
Y1[4]
Y1[5]
Y1[6]
Y1[7]
Y1[8]
Y1[9]
HSYNC/HREF not used
VSYNC/VREF not used
DE/FREF
not used
VPA[4]
VPA[5]
VPA[6]
VPA[7]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VPB[4] CB[8]
VPB[5] CB[9]
VPB[6] CB[10] Y0[10] CR[10] Y1[10]
VPB[7] CB[11] Y0[11] CR[11] Y1[11]
VCLK
VPB[7:0]; VPA[3:0]
Cb0
Y0
Cr0
Y1
...
Crxxx
Yxxx
001aai436
Fig 7. Pixel encoding YCbCr 4 : 2 : 2 ITU656-like embedded synchronization single edge (rising edge) input
TDA9981B_1
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Product data sheet
Rev. 01 — 4 July 2008
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TDA9981B
NXP Semiconductors
150 MHz pixel rate HDMI transmitter
Table 11. YCbCr 4 : 2 : 2 ITU656-like embedded synchronization double edge mappings
YCbCr 4 : 2 : 2 ITU656-like embedded synchronization double edge.
Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h.
Video port A
Pin YCbCr 4 : 2 : 2 (ITU656-like)
Video port B
Pin YCbCr 4 : 2 : 2 (ITU656-like)
Control
Pin
YCbCr 4 : 2 : 2
VPA[0] CB[0] Y0[0] CR[0] Y1[0] VPB[0] CB[4]
VPA[1] CB[1] Y0[1] CR[1] Y1[1] VPB[1] CB[5]
VPA[2] CB[2] Y0[2] CR[2] Y1[2] VPB[2] CB[6]
VPA[3] CB[3] Y0[3] CR[3] Y1[3] VPB[3] CB[7]
Y0[4]
Y0[5]
Y0[6]
Y0[7]
Y0[8]
Y0[9]
CR[4]
CR[5]
CR[6]
CR[7]
CR[8]
CR[9]
Y1[4]
Y1[5]
Y1[6]
Y1[7]
Y1[8]
Y1[9]
HSYNC/HREF not used
VSYNC/VREF not used
DE/FREF
not used
VPA[4]
VPA[5]
VPA[6]
VPA[7]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VPB[4] CB[8]
VPB[5] CB[9]
VPB[6] CB[10] Y0[10] CR[10] Y1[10]
VPB[7] CB[11] Y0[11] CR[11] Y1[11]
VCLK
VPB[7:0]; VPA[3:0]
Cb0
Y0
Cr0
Y1
...
Crxxx
Yxxx
001aai435
Fig 8. Pixel encoding YCbCr 4 : 2 : 2 ITU656-like embedded synchronization double edge (rising and falling)
input
TDA9981B_1
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Product data sheet
Rev. 01 — 4 July 2008
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TDA9981B
NXP Semiconductors
150 MHz pixel rate HDMI transmitter
Table 12. YCbCr 4 : 2 : 2 semi-planar external synchronization mappings
YCbCr 4 : 2 : 2 semi-planar external synchronization single edge.
Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 14h.
Video port A
Pin YCbCr 4 : 2 : 2
semi-planar
Video port B
Pin YCbCr 4 : 2 : 2
semi-planar
Video port C
Pin YCbCr 4 : 2 : 2
semi-planar
Control
Pin
YCbCr
4 : 2 : 2
VPA[0] Y0[0]
VPA[1] Y0[1]
VPA[2] Y0[2]
VPA[3] Y0[3]
VPA[4] CB[0]
VPA[5] CB[1]
VPA[6] CB[2]
VPA[7] CB[3]
Y1[0]
Y1[1]
Y1[2]
Y1[3]
CR[0]
CR[1]
CR[2]
CR[3]
VPB[0] Y0[4]
VPB[1] Y0[5]
VPB[2] Y0[6]
VPB[3] Y0[7]
VPB[4] Y0[8]
VPB[5] Y0[9]
VPB[6] Y0[10]
VPB[7] Y0[11]
Y1[4]
Y1[5]
Y1[6]
Y1[7]
Y1[8]
Y1[9]
Y1[10]
Y1[11]
VPC[0] CB[4]
VPC[1] CB[5]
VPC[2] CB[6]
VPC[3] CB[7]
VPC[4] CB[8]
VPC[5] CB[9]
CR[4]
CR[5]
CR[6]
CR[7]
CR[8]
CR[9]
HSYNC/HREF
VSYNC/VREF
DE/FREF
used
used
used
VPC[6] CB[10] CR[10]
VPC[7] CB[11] CR[11]
VCLK
HSYNC/HREF
VSYNC/VREF
DE/FREF
CONTROL
INPUTS
VPB[7:0]; VPA[3:0]
VPC[7:0]; VPA[7:4]
Y0
Y1
Y2
Y3
Y4
Y5
...
...
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
001aai437
Fig 9. Pixel encoding YCbCr 4 : 2 : 2 semi-planar external synchronization (rising edge) input
TDA9981B_1
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Product data sheet
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TDA9981B
NXP Semiconductors
150 MHz pixel rate HDMI transmitter
Table 13. YCbCr 4 : 2 : 2 semi-planar embedded synchronization mappings
YCbCr 4 : 2 : 2 semi-planar embedded synchronization single edge.
Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 14h.
Video port A
Pin YCbCr 4 : 2 : 2
semi-planar
Video port B
Pin YCbCr 4 : 2 : 2
semi-planar
Video port C
Pin YCbCr 4 : 2 : 2
semi-planar
Control
Pin
YCbCr
4 : 2 : 2
VPA[0] Y0[0]
VPA[1] Y0[1]
VPA[2] Y0[2]
VPA[3] Y0[3]
VPA[4] CB[0]
VPA[5] CB[1]
VPA[6] CB[2]
VPA[7] CB[3]
Y1[0]
Y1[1]
Y1[2]
Y1[3]
CR[0]
CR[1]
CR[2]
CR[3]
VPB[0] Y0[4]
VPB[1] Y0[5]
VPB[2] Y0[6]
VPB[3] Y0[7]
VPB[4] Y0[8]
VPB[5] Y0[9]
VPB[6] Y0[10]
VPB[7] Y0[11]
Y1[4]
Y1[5]
Y1[6]
Y1[7]
Y1[8]
Y1[9]
Y1[10]
Y1[11]
VPC[0] CB[4]
VPC[1] CB[5]
VPC[2] CB[6]
VPC[3] CB[7]
VPC[4] CB[8]
VPC[5] CB[9]
CR[4]
CR[5]
CR[6]
CR[7]
CR[8]
CR[9]
HSYNC/HREF
VSYNC/VREF
DE/FREF
not used
not used
not used
VPC[6] CB[10] CR[10]
VPC[7] CB[11] CR[11]
VCLK
VPB[7:0]; VPA[3:0]
VPC[7:0]; VPA[7:4]
Y0
Y1
Y2
Y3
Y4
Y5
...
...
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
001aai438
Fig 10. Pixel encoding YCbCr 4 : 2 : 2 semi-planar embedded synchronization (rising edge) input
TDA9981B_1
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Product data sheet
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TDA9981B
NXP Semiconductors
150 MHz pixel rate HDMI transmitter
8.3 Synchronization
The TDA9981B can be synchronized with Hsync/Vsync external inputs or with extraction
of the sync information from embedded sync (SAV/EAV) codes inside the video stream.
8.3.1 Timing extraction generator
This block can extract the synchronization signals Href, Vref and Fref from Start Active
Video (SAV) and End Active Video (EAV) in case of embedded synchronization in the data
stream. Synchronization signals can be embedded in RGB, YCbCr 4 : 4 : 4, YCbCr
4 : 2 : 2 semi-planar (up to 2 × 12-bit), YCbCr 4 : 2 : 2 ITU656 and ITU656-like (up to
1 × 12-bit).
8.3.2 Data enable generator
The TDA9981B contains a Data Enable (DE) generator; this can generate an internal DE
signal for a system which does not provide one.
8.4 Input and output video format
Due to the flexible video input formatter, the TDA9981B can accept a large range of input
formats. This flexibility allows the TDA9981B to be compatible with the maximum possible
number of MPEG decoders. Moreover, these input formats may be changed in many ways
(color space converter, upsampler and downsampler) to be transmitted across the HDMI
link. Table 14 gives the possible inputs and outputs.
Table 14. Use of color space converter, upsampler and downsampler
Input
Output
Color space
RGB
Color space
RGB
Format
Channels
Format
4 : 4 : 4
4 : 2 : 2
4 : 4 : 4
4 : 4 : 4
4 : 2 : 2
4 : 4 : 4
4 : 2 : 2
4 : 4 : 4
4 : 4 : 4
4 : 2 : 2
4 : 4 : 4
4 : 4 : 4
Channels
3 × 8-bit
2 × 12-bit
3 × 8-bit
3 × 8-bit
2 × 12-bit
3 × 8-bit
2 × 12-bit
3 × 8-bit
3 × 8-bit
2 × 12-bit
3 × 8-bit
3 × 8-bit
4 : 4 : 4
3 × 8-bit
YCbCr
YCbCr
RGB
YCbCr
YCbCr
4 : 4 : 4
4 : 2 : 2
3 × 8-bit
YCbCr
YCbCr
YCbCr
YCbCr
RGB
up to
1 × 12-bit
up to
2 × 12-bit
YCbCr
YCbCr
RGB
8.5 Upsampler
The incoming YCbCr 4 : 2 : 2 (2 × 12-bit) data stream format could be upsampled into a
12-bit YCbCr 4 : 4 : 4 (3 × 12-bit) data stream by repeating or linearly interpolating the
chrominance pixels.
TDA9981B_1
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Product data sheet
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TDA9981B
NXP Semiconductors
150 MHz pixel rate HDMI transmitter
8.6 Color space converter
The color space converter is used to convert input video data from one type to another
color space (RGB to YCbCr and YCbCr to RGB). This block can be bypassed and each
coefficient is programmable via the I2C-bus register.
OinG\Y
OinR\C
OoutY \G
C11 C12 C13
C21 C22 C23
C31 C32 C33
Y\G
G\Y
OoutC \R
CB\R =
×
R\CB
+
+
B
B
CR\B
B\CR
OinB\C
OoutC \B
R
R
8.7 Downsampler
This block works only with YCbCr input format; these filters downsample the CB and CR
signals by a factor 2. A delay is added on the G/Y channel, which corresponds to the
pipeline delay of the filters, to put the Y channel in phase with the CB-CR channel.
8.8 Audio input format
The TDA9981B is compatible with HDMI 1.2a (DVD support). The TDA9981B can carry
audio in I2S-bus format (one stereo up to four stereo channels) or in S/PDIF format.
S/PDIF or I2S-bus format can be selected via the I2C-bus. Only one audio format can be
used at a time: either S/PDIF or I2S-bus. Table 15 shows the audio port allocation.
Table 15. Audio port configuration
All audio ports are LV-TTL compatible.
Audio port
AP0
I2S-bus and S/PDIF input configuration
WS (word select)
AP1
I2S-bus port 0
AP2
I2S-bus port 1
AP3
I2S-bus port 2
AP4
I2S-bus port 3
AP5
MCLK (master clock for S/PDIF)
S/PDIF input
AP6
AP7
AUX (internal test)
SCK (I2S-bus clock)
ACLK
8.9 S/PDIF
The audio port AP6 is used for the S/PDIF feature. In this format the TDA9981B supports
2-channel uncompressed PCM data (IEC 60958) layout 0 or compressed bit stream up to
8 multichannels (Dolby Digital, DTS, AC-3, etc.) layout 1. The TDA9981B is able to
recover the original clock from the S/PDIF signal (no need for an external clock). In
addition it can also use an external clock (MCLK) to decode the S/PDIF signal.
8.10 I2S-bus
The TDA9981B supports the NXP I2S-bus format. There are four I2S-bus stereo input
channels (AP1 to AP4), which enable 8 uncompressed audio channels to be carried. The
I2S-bus input interface receives an I2S-bus signal including serial data, word select and
TDA9981B_1
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Product data sheet
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TDA9981B
NXP Semiconductors
150 MHz pixel rate HDMI transmitter
serial clock. Various I2S-bus formats are supported and can be selected by setting the
appropriate bits of the register. The I2S-bus input interface can receive up to 24-bit wide
audio samples via the serial data input with a clock frequency of at least 32 times the input
sample frequency fs. Since the I2S-bus format is MSB aligned, audio data with an arbitrary
precision can be received automatically. Audio samples with a precision better than 24
bits are truncated to 24 bits. If the input clock has a frequency of 32 × fs, only 16-bit audio
samples can be received. In this case, the 8 LSBs will be set to logic 0. The serial data
signal carries the serial baseband audio data, sample by sample left/right interleaved. The
word select signal WS indicates whether left or right channel information is transferred
over the serial data line. The formats for 16-bit and 32-bit modes are shown in Figure 11.
AP0/WS
ACLK
left channel
right channel
0
R
B23
B0
L
0
L
0
L
0
L
B23
B0
R
0
R
0
R
0
R
B23
L
APx
L
R
x = 1, 2, 3, 4
001aag915
a. 32-bit mode
AP0/WS
left channel
right channel
ACLK
B0
R
B15
B14
B13
B2
L
B1
L
B0
L
B15
B14
B13
B2
R
B1
R
B0
R
B15
L
APx
L
L
L
R
R
R
x = 1, 2, 3, 4
001aag916
b. 16-bit mode
Fig 11. NXP I2S-bus formats
8.11 Power management
The TDA9981B can be powered down via the I2C-bus register.
8.12 Interrupt controller
Pin INT is used to alert the microcontroller that a critical event concerning the HDMI has
occurred (hot plug detect, RxSense). These interrupts are maskable.
Hot plug or unplug detect: pin HPD is the hot plug detection pin; it is 5 V input tolerant.
8.13 Initialization
Hard reset: after power-up, the TDA9981B is activated by a hard reset via pin RST_N.
However, the TDA9981B has a power-on reset.
TDA9981B_1
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Product data sheet
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TDA9981B
NXP Semiconductors
8.14 HDMI
150 MHz pixel rate HDMI transmitter
8.14.1 Output HDMI buffers
An external resistor must be used to set the HDMI output amplitude. It has to be
connected between pin EXT_SWING and VDDH(3V3)
.
8.14.2 Pixel repetition
To transmit video formats with pixel rates below 25 MHz or to increase the number of
audio sample packets in each frame, the TDA9981B uses pixel repetition to increase the
transmitted pixel clock.
Table 16. Pixel repetition
PIX_REP[3]
PIX_REP[2]
PIX_REP[1]
PIX_REP[0]
Pixel repeated
no repetition
once
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
x
0
1
0
1
0
1
0
1
0
1
x
x
twice
3 times
4 times
5 times
6 times
7 times
8 times
9 times
undefined
undefined
8.14.3 HDMI and DVI receiver discrimination
This information is located in the E-EDID receiver part, in the ’Vendor-Specific Datablock’
within the first CEA EDID timing extension. If the 24-bit IEEE registration identifier
contains the value 00 0C03h, then the receiver will support HDMI, otherwise the device
will be treated as a DVI device. However, the TDA9981B does not have direct access to
that information since E-EDID is read by an external microprocessor through the
TDA9981B I2C-bus gate.
8.14.4 DDC channel
The DDC-bus pins DDC_SDA and DDC_SCL are 5 V tolerant and can work at standard
mode (100 kHz).
8.14.4.1 E-EDID reading
In order to get receiver capabilities, the TDA9981B must read the E-EDID of the receiver.
This is made possible by temporarily connecting the I2C-bus to the DDC lines, so that the
microprocessor is able to read full EDID.
8.14.5 RxSense detection
The TDA9981B is able to sense the connectivity and working behavior of the receiver. The
RxSense detection feature detects the presence of the 50 Ω pull-up resistor RT on the
TMDS clock channel of the downstream site.
TDA9981B_1
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Product data sheet
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TDA9981B
NXP Semiconductors
150 MHz pixel rate HDMI transmitter
V
DDA
R
T
R
T
TRANSMITTER
Z
0
D
D
RECEIVER
001aag601
Fig 12. Receiver sensitivity detection
As long as the receiver is connected to the transmitter and powered up, bit RXS_FIL is set
to logic 1.
When the cable is unplugged or the receiver site is powered off (assuming in this case
that VDD is switched off), the RxSense generates an interrupt inside the TDA9981B,
changing the value of bit RXS_FIL to logic 0. This allows the application to stop sending
unnecessary video content.
This feature is very useful when the receiver has recovered from an off state and does not
generate an HPD HIGH-to-LOW-to-HIGH transition. In this particular case, RxSense will
generate an interrupt so that the TDA9981B restarts sending video.
Remark: According to the HDMI specification, only the HPD interrupt allows the
application to read the EDID. It is not mandatory to use RxSense to initialize the EDID
reading procedure.
8.15 I2C-bus interface
The I2C-bus pins I2C_SDA and I2C_SCL are 5 V tolerant and can work at fast mode
(400 kHz).
9. I2C–bus register definitions
9.1 I2C-bus protocol
The registers of the TDA9981B can be accessed via the I2C-bus. The TDA9981B is used
as a slave device and both the fast mode 400 kHz and the standard mode 100 kHz are
supported.
Bits A0 and A1 of the I2C-bus device address are externally selected by pins A0 and A1.
The I2C-bus device address is given in Table 17.
Table 17. Device address
Device address
R/W
-
A6
1
A5
1
A4
1
A3
0
A2
0
A1
A1
A0
A0
1/0
The I2C-bus access format is shown in Figure 13.
TDA9981B_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 4 July 2008
22 of 41
TDA9981B
NXP Semiconductors
150 MHz pixel rate HDMI transmitter
For read access, the master writes the address of the TDA9981B, the subaddress to
access the specific register and then the data.
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL
SDA
SLAVE ADDRESS
SUBADDRESS
DATA
STOP
001aaf292
Fig 13. I2C-bus access
10. Limiting values
Table 18. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
+4.6
+2.5
+0.5
+150
85
Unit
V
VDD(3V3) supply voltage (3.3 V)
VDD(1V8) supply voltage (1.8 V)
−0.5
−0.5
−0.5
−55
0
V
∆VDD
Tstg
Tamb
Tj
supply voltage difference
storage temperature
V
°C
°C
°C
V
ambient temperature
junction temperature
-
125
Vesd
electrostatic discharge voltage
HBM
−2000 +2000
11. Thermal characteristics
Table 19. Thermal characteristics
Symbol Parameter
Conditions
Typ
Unit
Rth(j-a)
thermal resistance from junction in free air; JEDEC 4L board
to ambient
50.6
K/W
Rth(j-c)
thermal resistance from junction
to case
16.2
K/W
TDA9981B_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 4 July 2008
23 of 41
TDA9981B
NXP Semiconductors
150 MHz pixel rate HDMI transmitter
12. Static characteristics
Table 20. Supplies
VDDA(FRO_3V3) = 3.0 V to 3.6 V; VDDA(PLL_3V3) = 3.0 V to 3.6 V; VDDH(3V3) = 3.0 V to 3.6 V; VDDD(3V3) = 3.0 V to 3.6 V;
DDC(1V8) = 1.65 V to 1.95 V; VPP = 0 V; Tamb = 0 °C to 85 °C.
V
Typical values are measured at VDDA(FRO_3V3) = VDDA(PLL_3V3) = VDDH(3V3) = VDDD(3V3) = 3.3 V; VDDC(1V8) = 1.8 V; VPP = 0 V
and Tamb = 25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
TDA9981BHL/8 and TDA9981BHL/15
VDDA(FRO_3V3)
VDDA(PLL_3V3)
VDDD(3V3)
free running oscillator 3.3 V analog supply voltage
3.0
3.0
3.0
3.0
1.65
3.3
3.3
3.3
3.3
1.8
3.6
3.6
3.6
3.6
1.95
V
V
V
V
V
PLL 3.3 V analog supply voltage
digital supply voltage (3.3 V)
HDMI supply voltage (3.3 V)
core supply voltage (1.8 V)
VDDH(3V3)
VDDC(1V8)
TDA9981BHL/8; up to 81 MHz
IDDA(FRO_3V3)
IDDA(PLL_3V3)
IDDD(3V3)
IDDH(3V3)
IDDC(1V8)
fclk(max)
Pcons
free running oscillator 3.3 V analog supply current
-
-
0.5
4.5
mA
mA
mA
mA
[1]
PLL 3.3 V analog supply current
digital supply current (3.3 V)
HDMI supply current (3.3 V)
core supply current (1.8 V)
maximum clock frequency
power consumption
-
3.5
-
-
1.5
-
14
94
-
14.5
[1]
[1]
[1]
[1]
-
107.5 mA
81
-
-
MHz
235
369
14
288
438
19
mW
mW
mW
Ptot
total power dissipation
-
Ppd
power dissipation in Power-down mode
-
TDA9981BHL/15; up to 150 MHz
IDDA(FRO_3V3)
IDDA(PLL_3V3)
IDDD(3V3)
IDDH(3V3)
IDDC(1V8)
fclk(max)
Pcons
free running oscillator 3.3 V analog supply current
-
-
0.5
5
mA
[2]
PLL 3.3 V analog supply current
digital supply current (3.3 V)
HDMI supply current (3.3 V)
core supply current (1.8 V)
maximum clock frequency
power consumption
-
4
mA
-
-
3.5
15
200
-
mA
-
14
175
-
mA
[2]
[2]
[2]
[2]
-
mA
150
MHz
mW
mW
mW
-
-
-
381.5 468
515.5 618
Ptot
total power dissipation
Ppd
power dissipation in Power-down mode
14
19
[1] Worst case: video input format: 720p at 60 Hz (RGB 4 : 4 : 4 embedded sync), video output format: 720p at 60 Hz (YCbCr 4 : 4 : 4).
[2] Video input format: 1080p (RGB 4 : 4 : 4 embedded sync, rising edge), video output format: 1080p (RGB 4 : 4 : 4).
TDA9981B_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 4 July 2008
24 of 41
TDA9981B
NXP Semiconductors
150 MHz pixel rate HDMI transmitter
Table 21. LV-TTL digital inputs and outputs
VDDA(FRO_3V3) = 3.0 V to 3.6 V; VDDA(PLL_3V3) = 3.0 V to 3.6 V; VDDH(3V3) = 3.0 V to 3.6 V; VDDD(3V3) = 3.0 V to 3.6 V;
DDC(1V8) = 1.65 V to 1.95 V; VPP = 0 V; Tamb = 0 °C to 85 °C.
V
Typical values are measured at VDDA(FRO_3V3) = VDDA(PLL_3V3) = VDDH(3V3) = VDDD(3V3) = 3.3 V; VDDC(1V8) = 1.8 V; VPP = 0 V
and Tamb = 25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Not 5 V tolerant inputs: pins HSYNC, VSYNC, AP[7:0], ACLK, TM, A0, A1, VPA[7:0], VPB[7:0], VPC[7:0], VCLK, DE
and RST_N
VIL
VIH
IIL
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
HIGH-level input current
input capacitance
-
-
0.8
-
V
2.0
−1
−1
-
-
V
-
+1
+1
-
µA
µA
pF
IIH
Ci
-
4.5
5 V tolerant input: pin HPD
VIL
VIH
Ci
LOW-level input voltage
-
-
0.8
V
HIGH-level input voltage
input capacitance
2.0
-
-
-
-
V
4.5
pF
Output: pin INT
VOL
LOW-level output voltage
CL = 10 pF; IOL = 2 mA
-
-
0.4
V
Table 22. TMDS outputs
VDDA(FRO_3V3) = 3.0 V to 3.6 V; VDDA(PLL_3V3) = 3.0 V to 3.6 V; VDDH(3V3) = 3.0 V to 3.6 V; VDDD(3V3) = 3.0 V to 3.6 V;
DDC(1V8) = 1.65 V to 1.95 V; VPP = 0 V; Tamb = 0 °C to 85 °C.
V
Typical values are measured at VDDA(FRO_3V3) = VDDA(PLL_3V3) = VDDH(3V3) = VDDD(3V3) = 3.3 V; VDDC(1V8) = 1.8 V; VPP = 0 V
and Tamb = 25 °C; unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
TMDS output pins: TX0−, TX0+, TX1−, TX1+, TX2−, TX2+, TXC− and TXC+
Vo(p-p)
VOH
peak-to-peak output voltage
HIGH-level output voltage
LOW-level output voltage
single output; Rext = 610 Ω
(1 % tolerance) with test load and
operating condition as in HDMI
1.2a specification
400
510
600
mV
V
3.125 3.3
3.475
3.065
VOL
2.535 2.79
V
TDA9981B_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 4 July 2008
25 of 41
TDA9981B
NXP Semiconductors
150 MHz pixel rate HDMI transmitter
13. Dynamic characteristics
Table 23. Timing characteristics
VDDA(FRO_3V3) = 3.0 V to 3.6 V; VDDA(PLL_3V3) = 3.0 V to 3.6 V; VDDH(3V3) = 3.0 V to 3.6 V; VDDD(3V3) = 3.0 V to 3.6 V;
DDC(1V8) = 1.65 V to 1.95 V; VPP = 0 V; Tamb = 0 °C to 85 °C.
V
Typical values are measured at VDDA(FRO_3V3) = VDDA(PLL_3V3) = VDDH(3V3) = VDDD(3V3) = 3.3 V; VDDC(1V8) = 1.8 V; VPP = 0 V
and Tamb = 25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Clock inputs: pins VCLK, VPA[7:0], VPB[7:0] and VPC[7:0]; see Figure 14, 15, 17 and 18
fclk(max)
maximum clock frequency
TDA9981BHL/8
TDA9981BHL/15
81
-
-
-
-
-
-
MHz
MHz
ns
150
−0.25
2.20
40
-
tsu(D)
th(D)
δclk
data input set-up time
data input hold time
clock duty cycle
-
-
ns
[1]
60
%
DDC I2C-bus; 5 V tolerant; master bus: pins DDC_SDA and DDC_SCL
fSCL
SCL clock frequency
standard mode
-
-
-
100
-
kHz
pF
Ci
capacitance for each I/O pin
7
I2C-bus; 5 V tolerant; master bus: pins I2C_SDA and I2C_SCL
fSCL
SCL clock frequency
standard mode
fast mode
-
-
-
-
100
400
-
kHz
kHz
pF
-
Ci
capacitance for each I/O pin
7
TMDS output pins: TXC− and TXC+
fclk(max) maximum clock frequency
TDA9981BHL/8
TDA9981BHL/15
81
-
-
-
-
MHz
MHz
150
TMDS output pins: TX0−, TX0+, TX1−, TX1+, TX2− and TX2+
fclk(max)
maximum clock frequency
TDA9981BHL/8
TDA9981BHL/15
810
1.5
-
-
-
-
MHz
GHz
[1] δclk = tclk(H) / (tclk(H) + tclk(L)).
TDA9981B_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 4 July 2008
26 of 41
TDA9981B
NXP Semiconductors
150 MHz pixel rate HDMI transmitter
13.1 Input format
In Table 24 the port VPA has been mapped to CB (YUV space)/B (RGB space), VPB has
been mapped to Y (YUV space)/G (RGB space) and VPC has been mapped to CR (YUV
space)/R (RGB space).
Table 24. Input format
Input pins Signal
RGB
YUV
4 : 4 : 4[1]
4 : 4 : 4[2]
4 : 2 : 2 (semi-planar)[3] 4 : 2 : 2 (ITU656-like)[4]
Video port A
VPA[0]
CB[0]/B[0]
CB[1]/B[1]
CB[2]/B[2]
CB[3]/B[3]
CB[4]/B[4]
CB[5]/B[5]
CB[6]/B[6]
CB[7]/B[7]
B[0]
B[1]
B[2]
B[3]
B[4]
B[5]
B[6]
B[7]
CB[0]
CB[1]
CB[2]
CB[3]
CB[4]
CB[5]
CB[6]
CB[7]
Y0[0]
Y0[1]
Y0[2]
Y0[3]
CB[0]
CB[1]
CB[2]
CB[3]
Y1[0]
Y1[1]
Y1[2]
Y1[3]
CR[0]
CR[1]
CR[2]
CR[3]
CB[0]
CB[1]
CB[2]
CB[3]
L
Y0[0]
Y0[1]
Y0[2]
Y0[3]
L
CR[0] Y1[0]
CR[1] Y1[1]
CR[2] Y1[2]
CR[3] Y1[3]
VPA[1]
VPA[2]
VPA[3]
VPA[4]
L
L
L
L
L
L
L
L
VPA[5]
L
L
VPA[6]
L
L
VPA[7]
L
L
Video port B
VPB[0]
VPB[1]
VPB[2]
VPB[3]
VPB[4]
VPB[5]
VPB[6]
VPB[7]
Video port C
VPC[0]
VPC[1]
VPC[2]
VPC[3]
VPC[4]
VPC[5]
VPC[6]
VPC[7]
Y[0]/G[0]
Y[1]/G[1]
Y[2]/G[2]
Y[3]/G[3]
Y[4]/G[4]
Y[5]/G[5]
Y[6]/G[6]
Y[7]/G[7]
G[0]
G[1]
G[2]
G[3]
G[4]
G[5]
G[6]
G[7]
Y[0]
Y[1]
Y[2]
Y[3]
Y[4]
Y[5]
Y[6]
Y[7]
Y0[4]
Y0[5]
Y0[6]
Y0[7]
Y0[8]
Y0[9]
Y0[10]
Y0[11]
Y1[4]
Y1[5]
Y1[6]
Y1[7]
Y1[8]
Y1[9]
Y1[10]
Y1[11]
CB[4]
CB[5]
CB[6]
CB[7]
CB[8]
CB[9]
CB[10]
CB[11]
Y0[4]
Y0[5]
Y0[6]
Y0[7]
Y0[8]
Y0[9]
CR[4] Y1[4]
CR[5] Y1[5]
CR[6] Y1[6]
CR[7] Y1[7]
CR[8] Y1[8]
CR[9] Y1[9]
Y0[10] CR[10] Y1[10]
Y0[11] CR[11] Y1[11]
CR[0]/R[0]
CR[1]/R[1]
CR[2]/R[2]
CR[3]/R[3]
CR[4]/R[4]
CR[5]/R[5]
CR[6]/R[6]
CR[7]/R[7]
R[0]
R[1]
R[2]
R[3]
R[4]
R[5]
R[6]
R[7]
CR[0]
CR[1]
CR[2]
CR[3]
CR[4]
CR[5]
CR[6]
CR[7]
CB[4]
CB[5]
CB[6]
CB[7]
CB[8]
CB[9]
CR[4]
CR[5]
CR[6]
CR[7]
CR[8]
CR[9]
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
CB[10] CR[10]
CB[11] CR[11]
[1] Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h.
[2] Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h.
[3] Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 14h.
[4] Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h.
TDA9981B_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 4 July 2008
27 of 41
TDA9981B
NXP Semiconductors
150 MHz pixel rate HDMI transmitter
13.2 Example of supported video
The TDA9981B supports all EIA/CEA-861B, ATSC video input formats.
Table 25. Timing parameters for EIA/CEA-861B
Format nr.
Format
V frequency
(Hz)
H total V total H frequency
(kHz)
Pixel frequency Pixel repetition
(MHz)
59.94 Hz systems
1 (VGA)
640 × 480p
59.9401
59.9401
59.9401
59.9401
59.9401
59.9401
59.9401
59.9401
800
858
1650
2200
858
858
858
858
525
525
750
1125
525
262
263
525
31.4685
31.4685
44.955
25.174825
27
1
1
1
1
2
2
2
2, 3
720 × 480p
1280 × 720p
1920 × 1080i
720 × 480i
720 × 240p
720 × 240p
720 × 480i
4
74.175824
74.175824
13.5
5
33.7163
15.7343
15.7043
15.7642
15.7343
6, 7 (NTSC)
8, 9
13.474286
13.525714
13.5
8, 9
10, 11
4, 5, 7[1], 8[1],
10[1]
12, 13
12, 13
720 × 240p
720 × 240p
59.9401
59.9401
858
858
262
263
15.7043
15.7642
13.474286
13.525714
4, 5, 7[1], 8[1],
10[1]
4, 5, 7[1], 8[1],
10[1]
14, 15
16[1]
1440 × 480p
59.9401
59.9401
1716
2200
525
31.4685
67.4326
54
2
1
1920 × 1080p
1125
148.35165[1]
60 Hz systems
1 (VGA)
640 × 480p
720 × 480p
1280 × 720p
1920 × 1080i
720 × 480i
720 × 240p
720 × 240p
720 × 480i
60
60
60
60
60
60
60
60
800
858
1650
2200
858
858
858
858
525
525
750
1125
525
262
263
525
31.5
25.2
1
1
1
1
2
2
2
2, 3
31.5
27.27
4
45
74.25
5
33.75
15.75
15.72
15.78
15.75
74.25
6, 7 (NTSC)
8, 9
13.5135
13.48776
13.53924
13.5135
8, 9
10, 11
4, 5, 7[1], 8[1],
10[1]
12, 13
12, 13
720 × 240p
720 × 240p
60
60
858
858
262
263
15.72
15.78
13.48776
13.53924
4, 5, 7[1], 8[1],
10[1]
4, 5, 7[1], 8[1],
10[1]
14, 15
16[1]
1440 × 480p
60
60
1716
2200
525
31.5
67.5
54.054
148.5[1]
2
1
1920 × 1080p
1125
50 Hz systems
17, 18
720 × 576p
1280 × 720p
1920 × 1080i
720 × 576i
50
50
50
50
50
50
864
625
750
1125
625
312
313
31.25
37.5
27
1
1
1
2
2
2
19
1980
2640
864
74.25
74.25
13.5
20
28.125
15.625
15.6
21, 22 (PAL)
23, 24
720 × 288p
720 × 288p
864
13.4784
13.5216
23, 24
864
15.65
TDA9981B_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 4 July 2008
28 of 41
TDA9981B
NXP Semiconductors
150 MHz pixel rate HDMI transmitter
Table 25. Timing parameters for EIA/CEA-861B …continued
Format nr.
Format
V frequency
(Hz)
H total V total H frequency
(kHz)
Pixel frequency Pixel repetition
(MHz)
23, 24
25, 26
720 × 288p
720 × 576i
50
50
864
864
314
625
15.7
13.5648
13.5
2
15.625
4, 5, 7[1], 8[1],
10[1]
27, 28
27, 28
720 × 288p
720 × 288p
50
50
864
864
312
313
15.6
13.4784
13.5216
4, 5, 7[1], 8[1],
10[1]
4, 5, 7[1], 8[1],
10[1]
15.65
27, 28
29, 30
31[1]
720 × 288p
50
50
50
864
314
15.7
13.5648
54
148.5[1]
2
1
1
1440 × 576p
1920 × 1080p
1728
2640
625
31.25
56.25
1125
Various systems
32
32
33
34
34
1920 × 1080p
23.976
24
2750
2750
2640
2200
2200
1125
1125
1125
1125
1125
26.973
27
74.175824
74.25
1
1
1
1
1
1920 × 1080p
1920 × 1080p
1920 × 1080p
1920 × 1080p
25
28.125
33.716
33.75
74.25
29.97
30
74.175824
74.25
[1] Only for TDA9981BHL/15.
Table 26. Timing parameters for PC standards below 150 MHz
Standard
Format
V frequency
(Hz)
H total
V total
H frequency
(kHz)
Pixel frequency Pixel
(MHz)
repetition
640 × 350p
640 × 400p
720 × 400p
640 × 480p
640 × 480p
640 × 480p
640 × 480p
800 × 600p
800 × 600p
800 × 600p
800 × 600p
800 × 600p
800 × 600p
848 × 480p
1024 × 768p
1024 × 768p
1024 × 768p
1024 × 768p[1]
1024 × 768i
85.080
85.080
85.039
59.940
72.809
75.000
85.008
56.250
60.317
72.188
75.000
85.061
119.972
60.000
60.004
70.069
75.029
84.997
86.957
832
445
445
446
525
520
500
509
625
628
666
625
631
636
517
806
806
800
808
817
37.861
37.861
37.927
31.469
37.861
37.500
43.269
35.156
37.879
48.077
46.875
53.674
76.302
31.020
48.363
56.476
60.023
68.677
35.522
31.500
31.500
35.500
25.175
31.500
31.500
36.000
36.000
40.000
50.000
49.500
56.250
73.250
33.750
65.000
75.000
78.750
94.500
44.900
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
832
936
0.31M3
VGA
800
832
840
832
0.48M3
SVGA
1024
1056
1040
1056
1048
960
0.48M3-R
0.41M9
1088
1344
1328
1312
1376
1264
0.79M3
XGA
TDA9981B_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
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TDA9981B
NXP Semiconductors
150 MHz pixel rate HDMI transmitter
Table 26. Timing parameters for PC standards below 150 MHz …continued
Standard
Format
V frequency
(Hz)
H total
V total
H frequency
(kHz)
Pixel frequency Pixel
(MHz)
repetition
0.79M3-R
XGA[1]
1024 × 768p[1]
119.989
1184
813
97.551
115.500
-
1.00M3[1]
1152 × 864p[1]
1280 × 768p
1280 × 768p[1]
75.000
59.995
119.798
59.870
74.893
84.837
59.910
119.909
59.810
74.934
84.880
60.000
85.002
60.020
75.025
60.015
119.967
59.948
59.978
59.901
59.887
74.984
59.883
59.954
1600
1440
1440
1664
1696
1712
1440
1440
1680
1696
1712
1800
1728
1688
1688
1792
1520
1560
1864
1600
1904
1936
1840
2240
900
67.500
47.396
97.396
47.776
60.289
68.633
49.306
101.563
49.702
62.795
71.554
60.000
85.938
63.981
79.976
47.712
97.533
64.744
65.317
55.469
55.935
70.635
64.674
65.290
108.000
68.250
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.98M9-R
790
813
140.250
79.500
0.98M9
1280 × 768p
798
1280 × 768p[1]
1280 × 768p[1]
1280 × 800p
805
102.250
117.500
71.000
809
1.02MA-R
1.02MA[1]
823
1280 × 800p[1]
1280 × 800p[1]
1280 × 800p[1]
1280 × 800p[1]
1280 × 960p[1]
1280 × 960p[1]
1280 × 1024p[1]
1280 × 1024p[1]
1360 × 768p[1]
847
146.250
83.500
831
838
106.500
122.500
108.000
148.500
108.000
135.000
85.500
843
1.23M3[1]
1000
1011
1066
1066
795
1.31M4
SXGA[1]
1.04M9[1]
1.04M9-R[1] 1360 × 768p[1]
1.47M3-R[1] 1400 × 1050p[1]
1.47M3[1]
1.29MA-R[1] 1440 × 900p[1]
813
148.250
101.000
121.750
88.750
1080
1089
926
1400 × 1050p[1]
1.29MA[1]
1440 × 900p[1]
1440 × 900p[1]
934
106.500
136.750
119.000
146.250
942
1.76MA-R[1] 1680 × 1050p[1]
1.76MA[1] 1680 × 1050p[1]
1080
1089
[1] Only for TDA9981BHL/15.
TDA9981B_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 4 July 2008
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TDA9981B
NXP Semiconductors
150 MHz pixel rate HDMI transmitter
13.3 Timing diagrams
VCLK
t
t
clk(H) clk(L)
HSYNC/HREF
VSYNC/VREF
DE/FREF
CONTROL
INPUTS
VPA[7:0]
VPB[7:0]
VPC[7:0]
B0
G0
R0
B1
G1
R1
B2
G2
R2
B3
G3
R3
...
...
...
Bxxx
Gxxx
Rxxx
Bxxx
Gxxx
Rxxx
t
h(D)
t
su(D)
001aag250
Fig 14. Timing RGB 4 : 4 : 4 (rising edge) input
VCLK
t
t
clk(H) clk(L)
HSYNC/HREF
VSYNC/VREF
DE/FREF
CONTROL
INPUTS
VPA[7:0]
VPB[7:0]
VPC[7:0]
Cb0
Y0
Cb1
Y1
Cb2
Y2
Cb3
Y3
...
...
...
Cbxxx
Yxxx
Cbxxx
Yxxx
Cr0
Cr1
Cr2
Cr3
Crxxx
Crxxx
t
h(D)
t
su(D)
001aai425
Fig 15. Timing YCbCr 4 : 4 : 4 (rising edge) input
VCLK
t
t
clk(L)
clk(H)
HSYNC/HREF
VSYNC/VREF
DE/FREF
CONTROL
INPUTS
VPB[7:0]; VPA[3:0]
Cb0
Y0
Cr0
Y1
...
Crxxx
Yxxx
t
t
h(D)
h(D)
t
t
su(D)
su(D)
001aai426
Fig 16. Timing YCbCr 4 : 2 : 2 ITU656-like double edge (rising and falling) input
TDA9981B_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 4 July 2008
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TDA9981B
NXP Semiconductors
150 MHz pixel rate HDMI transmitter
VCLK
t
t
clk(H) clk(L)
HSYNC/HREF
CONTROL
VSYNC/VREF
INPUTS
DE/FREF
VPB[7:0]; VPA[3:0]
Cb0
Y0
Cr0
Y1
...
Crxxx
Yxxx
t
h(D)
t
su(D)
001aai427
Fig 17. Timing YCbCr 4 : 2 : 2 ITU656-like single edge external (rising edge) input
VCLK
t
t
t
clk(H) clk(L)
h(D)
HSYNC/HREF
VSYNC/VREF
DE/FREF
CONTROL
INPUTS
VPB[7:0]; VPA[3:0]
VPC[7:0]; VPA[7:4]
Y0
Y1
Y2
Y3
Y4
Y5
...
...
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
t
su(D)
001aai428
Fig 18. Timing YCbCr 4 : 2 : 2 semi-planar external synchronization (rising edge) input
TDA9981B_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 4 July 2008
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TDA9981B
NXP Semiconductors
150 MHz pixel rate HDMI transmitter
14. Application information
DAC
DAC
DAC
CVBS/Y/(G)
C/Pb/(B)
Pr/(R)
DENC
G
ADC
DSP
LO
audio
I S-bus
AUX
data
2
or S/PDIF
8
HDMI
data stream
HDMI TX
STEREO
AUDIO DAC
001aai429
Fig 19. Application diagram for Set-Top Box
DAC
DAC
DAC
CVBS/Y/(G)
C/Pb/(B)
Pr/(R)
DENC
DVD
READ
ENGINE
DSP
audio
I S-bus
or S/PDIF
AUX
data
2
8
HDMI
data stream
HDMI TX
STEREO
AUDIO DAC
001aai430
Fig 20. Application diagram for DVD player
TDA9981B_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 4 July 2008
33 of 41
TDA9981B
NXP Semiconductors
150 MHz pixel rate HDMI transmitter
reset
TMDS clock
digital video
(up to 24 bits)
TMDS channel 0
TMDS channel 1
HDMI
sync signals
MICROPROCESSOR
MASTER
HDMI
TDA9981B
RECEIVER/
REPEATER
2
audio, S/PDIF and I S-bus
IRQ
TMDS channel 2
MPEG2
DECODER
hot plug detect
2
2
I C-bus
I C-bus
DDC (SCL and SDA)
SLAVE
MASTER
SLAVE
MASTER
E-EDID
SLAVE ADDRESS A0
HDMI SOURCE
CEC line
001aai220
Fig 21. Transmitter connection with external world
TDA9981B_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 4 July 2008
34 of 41
TDA9981B
NXP Semiconductors
150 MHz pixel rate HDMI transmitter
15. Package outline
LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm
SOT315-1
y
X
A
60
41
Z
61
40
E
e
H
A
E
2
E
A
(A )
3
A
1
w M
p
θ
b
L
p
L
pin 1 index
80
21
detail X
1
20
Z
D
v
M
A
e
w M
b
p
D
B
H
v
M
B
D
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
H
L
L
v
w
y
Z
Z
θ
1
2
3
p
D
E
p
D
E
max.
7o
0o
0.16 1.5
0.04 1.3
0.27 0.18 12.1 12.1
0.13 0.12 11.9 11.9
14.15 14.15
13.85 13.85
0.75
0.30
1.45 1.45
1.05 1.05
mm
1.6
0.25
0.5
1
0.2 0.15 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-01-19
03-02-25
SOT315-1
136E15
MS-026
Fig 22. Package outline SOT315-1 (LQFP80)
TDA9981B_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 4 July 2008
35 of 41
TDA9981B
NXP Semiconductors
150 MHz pixel rate HDMI transmitter
16. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
TDA9981B_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 4 July 2008
36 of 41
TDA9981B
NXP Semiconductors
150 MHz pixel rate HDMI transmitter
16.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 23) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 27 and 28
Table 27. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
235
≥ 350
220
< 2.5
≥ 2.5
220
220
Table 28. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 23.
TDA9981B_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 4 July 2008
37 of 41
TDA9981B
NXP Semiconductors
150 MHz pixel rate HDMI transmitter
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 23. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
17. Soldering: additional information
The package of this device supports the reflow soldering process only.
18. Abbreviations
Table 29. Abbreviations
Acronym
AC-3
ADC
Description
Active Coding-3
Analog-to-Digital Converter
Audio Video
AV
CEC
Consumer Electronics Control
Complementary Metal-Oxide Semiconductor
Digital-to-Analog Converter
Display Data Channel
CMOS
DAC
DDC
DENC
DSP
Digital video ENCoder
Digital Signal Processor
Digital Theater Systems
Digital Versatile Disc
DTS
DVD
DVI
Digital Visual Interface
EAV
End of Active Video
E-EDID
HBM
HDMI
Enhanced Extended Display Identification Data
Human Body Model
High-Definition Multimedia Interface
TDA9981B_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 4 July 2008
38 of 41
TDA9981B
NXP Semiconductors
150 MHz pixel rate HDMI transmitter
Table 29. Abbreviations …continued
Acronym
Description
HDTV
HPD
IRQ
High-Definition Television
Hot Plug Detect
Interrupt ReQuest
Local Oscillator
LO
L-PCM
LSB
Linear Pulse-Code Modulation
Least Significant Bit
LV-TTL
MSB
OTP
PAL
Low-Voltage Transistor-Transistor Logic
Most Significant Bit
One-Time Programmable
Phase Alternating Line
PCM
PLL
Pulse-Code Modulation
Phase-Locked Loop
PVR
RGB
SAV
Personal Video Recorder
Red, Green, Blue
Start of Active Video
STB
Set-Top Box
S/PDIF
TMDS
Tx
Sony/Philips Digital Interface
Transition Minimized Differential Signaling
Transmitter
XGA
YUV
YCbCr
Extended Graphics Array
color space used by the NTSC and PAL systems
color space originally defined by the ITU-R BT.601
19. Revision history
Table 30. Revision history
Document ID
Release date
20080704
Data sheet status
Change notice
Supersedes
TDA9981B_1
Product data sheet
-
-
TDA9981B_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 4 July 2008
39 of 41
TDA9981B
NXP Semiconductors
150 MHz pixel rate HDMI transmitter
20. Legal information
20.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
20.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
20.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
20.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
21. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
TDA9981B_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 4 July 2008
40 of 41
TDA9981B
NXP Semiconductors
150 MHz pixel rate HDMI transmitter
22. Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
16
Soldering of SMD packages . . . . . . . . . . . . . . 36
Introduction to soldering. . . . . . . . . . . . . . . . . 36
Wave and reflow soldering . . . . . . . . . . . . . . . 36
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 36
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 37
16.1
16.2
16.3
16.4
2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 3
Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
4
5
5.1
6
17
18
19
Soldering: additional information . . . . . . . . . 38
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 38
Revision history . . . . . . . . . . . . . . . . . . . . . . . 39
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
20
Legal information . . . . . . . . . . . . . . . . . . . . . . 40
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 40
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 40
20.1
20.2
20.3
20.4
8
8.1
8.2
8.3
8.3.1
8.3.2
8.4
8.5
8.6
Functional description . . . . . . . . . . . . . . . . . . . 8
System clock. . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Video input processor. . . . . . . . . . . . . . . . . . . . 8
Synchronization . . . . . . . . . . . . . . . . . . . . . . . 18
Timing extraction generator . . . . . . . . . . . . . . 18
Data enable generator . . . . . . . . . . . . . . . . . . 18
Input and output video format. . . . . . . . . . . . . 18
Upsampler . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Color space converter. . . . . . . . . . . . . . . . . . . 19
Downsampler . . . . . . . . . . . . . . . . . . . . . . . . . 19
Audio input format. . . . . . . . . . . . . . . . . . . . . . 19
S/PDIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
I2S-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Power management . . . . . . . . . . . . . . . . . . . . 20
Interrupt controller . . . . . . . . . . . . . . . . . . . . . 20
Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
HDMI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Output HDMI buffers. . . . . . . . . . . . . . . . . . . . 21
Pixel repetition . . . . . . . . . . . . . . . . . . . . . . . . 21
HDMI and DVI receiver discrimination . . . . . . 21
DDC channel . . . . . . . . . . . . . . . . . . . . . . . . . 21
21
22
Contact information . . . . . . . . . . . . . . . . . . . . 40
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.7
8.8
8.9
8.10
8.11
8.12
8.13
8.14
8.14.1
8.14.2
8.14.3
8.14.4
8.14.4.1 E-EDID reading. . . . . . . . . . . . . . . . . . . . . . . . 21
8.14.5
8.15
RxSense detection . . . . . . . . . . . . . . . . . . . . . 21
I2C-bus interface. . . . . . . . . . . . . . . . . . . . . . . 22
9
I2C–bus register definitions . . . . . . . . . . . . . . 22
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 22
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 23
Thermal characteristics. . . . . . . . . . . . . . . . . . 23
Static characteristics. . . . . . . . . . . . . . . . . . . . 24
9.1
10
11
12
13
Dynamic characteristics . . . . . . . . . . . . . . . . . 26
Input format. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Example of supported video. . . . . . . . . . . . . . 28
Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 31
13.1
13.2
13.3
14
15
Application information. . . . . . . . . . . . . . . . . . 33
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 35
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 4 July 2008
Document identifier: TDA9981B_1
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