TEA1781T_技术文档

TEA1781T; TEA1782T

GreenChip PC secondary control ICs

Rev. 01 — 13 February 2009

Preliminary data sheet

1. General description

The TEA1781T and TEA1782T are designed to cooperate with the TEA1771T primary

side controller in a unique converter topology based on the active clamp forward

converter. On the secondary side the output voltages are regulated via bidirectional

switches. A typical application area of this converter is a power supply for a desktop PC.

The TEA1781T and TEA1782T are secondary control ICs and regulate each output

voltage independently of the primary duty cycle and other secondary output voltages.

Because of these separated regulations, the system does not show any cross regulation

and makes the design of the transformer easier.

As each output can also be completely turned off, the system allows for an integrated

standby supply. To maximize the efﬁciency in Standby mode, the duty cycle and operating

frequency are minimized in Standby mode.

The TEA1781T and TEA1782T have integrated drivers and individual output voltage

regulators. In this way the 3.3 V, 5 V, 12 V and 5 V standby outputs of a typical PC power

supply are regulated separately giving accurate output voltages and fast transient

response.

All requirements according to the Intel ATX speciﬁcation (V 2.0) are integrated, such as

soft start, a PS_ON# connection, a PwrOK signal and all required protections like

OverCurrent Protection (OCP) and OverVoltage Protection (OVP). These voltage and

current levels are monitored at each output separately. The system also has an

OverTemperature Protection (OTP) function.

The system fulﬁlls the current and proposed efﬁciency standards such as 80+ gold,

energy star and blue angel.

The TEA1781T and TEA1782T are implemented in a high voltage (ABCD)

Silicon On Insulator (SOI) process.

2. Features

I Designed for ATX PC power supplies

I Integrated standby supply

I Enhanced efﬁciency in Standby mode

I No cross regulation

I Accurate output voltage regulation

I Fast transient response

I Integrated soft start for all output voltages

I Flexible transformer design without the need of a post regulator

TEA1781T; TEA1782T

NXP Semiconductors

GreenChip PC secondary control ICs

I Overvoltage protection

I Overcurrent protection

I Overtemperature protection

I System failure detection

I Soft (re)start

I Low external component count

3. Applications

I PC desktop power supply

4. Ordering information

Table 1.

Ordering information

Type number

Package

Name

SO28

Description

Version

TEA1781T

TEA1782T

Plastic small outline package; 28 leads; body width 7.5 mm

SOT136-1

TEA1781_82_1

Preliminary data sheet

Rev. 01 — 13 February 2009

2 of 32

TEA1781T; TEA1782T

NXP Semiconductors

GreenChip PC secondary control ICs

5. Block diagram

10

9

22

18

Soft Start

start

Start-up

Enable

ENABLE

Temperature

protection

PowerGood

PowerOK

4

VSTARTUP

VDD

I

V

ref(5V)

V

otp

V

trip(ENABLE)

start

15

ref(3V3)

V

reg(VDD)

PGOOD

14

13

GND

Control 5 V

I-control 5 V

V

ref(5V)

Control 3.3 V

I-control 3.3 V

V

ref(3V3)

I

V

trip

Q

R

S

V/I

t

d

V/I

Q

R

S

Pull-down

Protection 5 V

Protection

3.3 V

VSENSE_3V3

I

pd

19

Drive SR

Drive 5 V

VDD

I

> I

I

> I

ocp

O

ocp

O

V

ovp(VOUT_3V3)

V

ovp(VOUT_5V)

I

uvp(VOUT_5V)

O

V

I

Drive

3.3 V

VDD

O

ocp

uvp(VOUT_3V3)

V

ref(OCP)

28 26 27

2

3

1

11 12 6

7

6

8

24 23 25 17 16 21

20

014aaa181

Fig 1. TEA1781T block diagram

TEA1781_82_1

Preliminary data sheet

Rev. 01 — 13 February 2009

3 of 32

TEA1781T; TEA1782T

NXP Semiconductors

GreenChip PC secondary control ICs

EN_NM

ENABLE

PS_OFF

VDD GND GND

Pull-

down

Enable NM

Digital control

STARTUP

V

> V

Startup

Opto control

UP

VDD

startup(VDD)

V

VDD

< V

VDD

stop(VDD)

V

= 4 V

ENABLE

V

VDD

I

startup(VDD)

pd

V

ENABLE

V

EN_NM

startup(VDD)

OPTO

I

> I

+ EN_NM

prot(ENABLE)

ENABLE

Soft Start

DOWN

+ PS_OFF+ PROT_12V + UVP_STB

V/I

start

V

ref(stb)

Vref(12V)

Control 12 V

system

restart

NORMAL

= 11 V

PROT/STDB

= 4 V

I

V

ENABLE

V

ENABLE

start

ref(12V)

normal

PS_OFF

V/I

I

system failure

detection

V/I

SYSTEM

RESTART

Power-

Good

I-control standby

I

V

ref(stb)

EN_NM

PROT_12V PROT_STB UVP_STB

PGOOD

I

V/I

Control 12 V

V

trip

Protection 12 V

Control standby

t

d

V

uvp(VOUT_12V1)

12 V OCP detection

Drive

Q

R

S

3.3 V

Protection

standby

V

ovp(VOUT_12V1)

Q

R

S

I

VOUT_12V2

V

uvp(VOUT_STB)

I

VOUT_12V

Drive SR

Drive 12 V

VDD

I

> I

OCP_STB

VOUT_STB

V

I

ovp(VOUT_STB)

OCP_12V

Drive

standby

VDD

I

OCP_STB

I

VOUT_STB

V

ref(OCP)

V

ref(OCP)

FSR

WND_SEC_1

GSB_12V DF_12V

FSB_12V

GSR

GSF_12V CS_12V

PGND_12V

VOUT_12V2

GSB_STB

FSB_STB

VOUT_STB

CS_STB

OCP_STB

VOUT_12V1 OCP_12V

DF_STB PGND_STB GSF_STB

014aaa182

Fig 2. TEA1782T block diagram

6. Pinning information

6.1 Pinning

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

FSB_5V

GSB_5V

DF_5V

FSR

FSB_12V

GSB_12V

DF_12V

FSR

GSR

3

WND_SEC_2

FSB_3V3

GSB_3V3

DF_3V3

WND_SEC_1

FSB_STB

GSB_STB

DF_STB

OCP_STB

CS_STB

VOUT_STB

OPTO

4

VSTARTUP

OCP

OCP_12V

CS_12V

5

6

CS_5V

VOUT_12V1

VOUT_12V2

EN_NM

7

VOUT_5V

VSENSE_5V

VNTC

PGOOD

CS_3V3

VOUT_3V3

VSENSE_3V3

PWROK

PGND_3V3

GSF_3V3

VDD

TEA1781T

TEA1782T

8

9

PS_OFF

ENABLE

PGND_12V

GSF_12V

GND

10

11

12

13

14

10

11

12

13

14

ENABLE

PGND_5V

GSF_5V

GND

PGOOD

PGND_STB

GSF_STB

VDD

GND

014aaa183

014aaa184

Fig 3. TEA1781T pin conﬁguration

Fig 4. TEA1782T pin conﬁguration

TEA1781_82_1

Preliminary data sheet

Rev. 01 — 13 February 2009

4 of 32

TEA1781T; TEA1782T

NXP Semiconductors

GreenChip PC secondary control ICs

6.2 Pin description

Table 2.

Symbol

FSB_5V

GSB_5V

DF_5V

TEA1781T pin description

1

Description

ﬂoating supply switch SB_5V

2

gate driver switch SB_5V

drain voltage of switch SF_5V

start-up voltage connected to rectiﬁed secondary winding voltage

overcurrent protection

3

VSTARTUP

OCP

4

5

CS_5V

6

current sense 5 V output

output voltage 5 V output

sense voltage 5 V output

NTC voltage

VOUT_5V

VSENSE_5V

VNTC

7

8

9

ENABLE

PGND_5V

GSF_5V

GND

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

enabling Normal mode

power ground 5 V output

gate driver switch SF_5V

ground

GND

ground

VDD

supply voltage

GSF_3V3

PGND_3V3

PWROK

VSENSE_3V3

VOUT_3V3

CS_3V3

PGOOD

DF_3V3

GSB_3V3

FSB_3V3

WND_SEC_2

GSR

gate driver switch SF_3V3

power ground 3V3 output

power OK

sense voltage 3.3 V output

output voltage 3.3 V output

current sense 5 V output

PowerGood (delay setting for power OK)

drain voltage of switch SF_3V3

gate driver switch SB_3V3

secondary transformer 3.3 V / 5 V winding voltage

gate driver switch SR (3.3 V / 5 V)

ﬂoating supply switch SR (3.3 V / 5 V)

FSR

Table 3.

TEA1782T Pin description

Symbol

1

Description

FSB_12V

GSB_12V

DF_12V

ﬂoating supply switch SB_12V

gate driver switch SB_12V

drain voltage of switch SF_12V

overcurrent protection 12 V output

current sense 12 V output

output voltage 12 V1 output

output voltage 12 V2 output

enable Normal mode

2

3

OCP_12V

CS_12V

4

5

VOUT_12V1

VOUT_12V2

EN_NM

6

7

8

TEA1781_82_1

Preliminary data sheet

Rev. 01 — 13 February 2009

5 of 32

TEA1781T; TEA1782T

NXP Semiconductors

GreenChip PC secondary control ICs

Table 3.

TEA1782T Pin description …continued

Symbol

PS_OFF

ENABLE

PGND_12V

GSF_12V

GND

9

Description

power supply off (via delay network connected to PS_ON#)

enabling Normal mode

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

power ground 12 V output

gate driver switch SF_12V

ground

GND

ground

VDD

supply voltage

GSF_STB

PGND_STB

PGOOD

OPTO

gate driver switch SF_stb

power ground standby output

PowerGood (delay setting for power OK)

opto coupler

VOUT_STB

CS_STB

OCP_STB

DF_STB

GSB_STB

FSB_STB

WND_SEC_1

GSR

output voltage standby output

current sense standby output

overcurrent protection standby output

drain voltage of switch SF_stb

gate driver switch SB_stb

secondary transformer 12 V / standby winding voltage

gate driver switch SR (12 V)

ﬂoating supply switch SR (12 V)

FSR

7. Functional description

7.1 Introduction

A PC power supply has to supply a number of different supply voltages: 12 V, 5 V, 3.3 V,

−12 V and 5 V standby. To achieve the required output voltage accuracy, the systems of

today require dissipative post regulations.

Because the system must be able to switch off the main supplies (12 V, 5 V, 3.3 V, −12 V)

in Standby mode but keep the 5 V standby in operation, a separate standby supply is still

common practice.

With the GreenChip PC chip set (TEA1771T, TEA1781T, TEA1782T) a system

conﬁguration is introduced that integrates the post regulation and combines the main and

standby converter into a single system. This high level of integration reduces the total cost

of the system.

Because the output voltages are regulated separately, it makes the design of the

converter easier as none of the output voltages is directly related to the number of turns

on the transformer.

One of the main differences of this topology compared to commonly used solutions is the

use of switches instead of Schottky diodes, although the rectifying switch is a so-called

bidirectional switch. This switch is built up by two standard FETs in anti-series.

TEA1781_82_1

Preliminary data sheet

Rev. 01 — 13 February 2009

6 of 32

TEA1781T; TEA1782T

NXP Semiconductors

GreenChip PC secondary control ICs

The freewheel switch behaves like an ideal diode so the setup runs in a discontinuous

mode at low loads. Negative currents are avoided by the control ICs through this switch.

Replacement of the rectifying Schottky diode by two switches in anti-series allows:

• Integration of the 5 V standby supply, because in Standby mode the main secondary

outputs can be switched off.

The supply voltages can be individually and more accurately regulated, eliminating

ubiquitous post regulators.

• As the output voltages is now regulated by the secondary switches, the duty cycle of

the primary control switch can be kept constant, preventing ringing at the primary

reset voltage. A lower reset voltage results in lower required breakdown voltages of all

applied FETs, both primary and secondary. This reduces costs.

• The use of Zero Voltage Switching (ZVS) at the primary side to fulﬁll the required

standby efﬁciency.

To fulﬁll the ATX12V speciﬁcation on standby efﬁciency requirements, the system has a

Standby mode in which the frequency, duty cycle and supply currents are reduced.

The TEA1781T and TEA1782T are secondary control ICs. Together with the TEA1771T

primary controller they form a unique system that fulﬁlls the 80+ gold requirements at

minimum costs, eliminating any cross regulation and maximizing standby efﬁciency.

7.2 Supply

When the voltage on the primary side from the rectiﬁed input mains reaches its starting

value, the primary side starts up and switches the primary main switch. From that

moment, the secondary rectiﬁed transformer voltage at V_startup, see Figure 5, is a ratio of

the input voltage.

12 V

V

VOUT_STB

Start-up

VSTARTUP

VDD

UVLO

V

startup(VDD)

TEA1781

TEA1782

014aaa185

Fig 5. Start-up sequence TEA1771T

TEA1781_82_1

Preliminary data sheet

Rev. 01 — 13 February 2009

7 of 32

TEA1781T; TEA1782T

NXP Semiconductors

GreenChip PC secondary control ICs

The VDD capacitor is charged and regulated to the V_reg(VDD)level via a linear regulator in

the TEA1781T. This VDD voltage is the supply voltage for both secondary ICs.

Once the VDD voltage reaches the V_startup(VDD)level, measured in the TEA1782T, the

5 V standby is started up via a so-called soft start. This implies that during a certain time,

t_start(soft), the output voltage slowly ramps up from zero to the required value. Once the

system is started up, the VDD voltage is taken over by an auxiliary winding of the

5 V standby output, as shown in Figure 5. This ensures an efﬁcient 12 V VDD voltage

during standby and normal operation.

As the secondary ICs are supplied via the TEA1781T and measured in the TEA1782T,

both ICs are disabled in case of an open connection in the supply chain.

If the VDD voltage drops below its V_stop(VDD)level, the system disables all output voltages

by actively turning off all switches. This avoids undeﬁned conditions resulting from

charged gate capacitances.

7.3 Mode of operation

After the system has started up, the TEA1782T deﬁnes the mode of operation. It features

four operation modes: Start-up mode, Protection/Standby mode, Normal mode and

System restart mode, as depicted in Figure 6.

Digital control

V

< V

stop(VDD)

VDD

STARTUP

= 4 V

V

ENABLE

V

> V

startup(VDD)

VDD

I

> I

+ EN_NM

prot(ENABLE)

ENABLE

+ PS_OFF+ PROT_12V + UVP_STB

NORMAL

= 11 V

PROT/STDB

= 4 V

V

ENABLE

V

ENABLE

PS_OFF

system failure

detection

SYSTEM

RESTART

014aaa186

Fig 6. State diagram TEA1771T

When the VDD voltage is below its stop level, the TEA1782T enters the Start-up mode

and the TEA1781T charges the VDD capacitors to V_reg(VDD)via the start-up pin. When it

has charged the VDD capacitor above V_startup(VDD), the TEA1782T jumps into

Protection/Standby mode and the 5 V standby output slowly rises from zero to its required

value.

When the PS_OFF signal becomes active low, the system switches to Normal mode

enabling the main outputs (3.3 V, 5 V, 12 V and −12 V). The 12 V (and −12 V) output is

regulated by the TEA1782T itself, whereas the 3.3 V and 5 V output are regulated by the

TEA1781T. The TEA1781T activates the 3.3 V and 5 V outputs via the ENABLE signal.

TEA1781_82_1

Preliminary data sheet

Rev. 01 — 13 February 2009

8 of 32

TEA1781T; TEA1782T

NXP Semiconductors

GreenChip PC secondary control ICs

At any failure condition or as soon as the PS_OFF signal is high, the system switches to

Protection / Standby mode. When a failure, such as a shorted or overloaded output, is

detected, the system enters the Protection mode, disabling the main output circuits but

leaving the standby output in operation. However, when, for example, a secondary FET is

shorted, the system enters the System restart mode and switches off the primary side.

When VDD is discharged below its minimum level, V_stop(VDD), the IC enters the Start-up

mode and all switches are disabled.

When the system is in Protection / Standby mode, the systems lowers its duty cycle and

operating frequency to optimize the system’s efﬁciency.

7.4 Enable Normal mode

In Standby mode, an optional PFC may be switched off. When switched to Normal mode,

the system has a programmable delay before the main outputs (3.3 V, 5 V and 12 V) are

switched on. During this delay the PFC can be activated.

An extra safety feature has been built in when enabling Normal mode. If the input voltage

is too low, which can occur when the PFC fails, the system stays in Standby mode.

The input voltage is measured on a rectiﬁed secondary voltage, reﬂecting the input

voltage; see Figure 7.

Np / Ns

V

WND_SEC_2

Enable NM

Digital control

EN_NM

1.25 V

014aaa187

Fig 7. Enable Normal mode assures a proper start-up of the forward converter

In addition to a minimum input voltage, a delay can also be made to assure a proper

start-up of the PFC before the system switches to Normal mode. A circuit according to

Figure 8 must be built between the PS_ON# signal from the motherboard and the

PS_OFF pin of the TEA1782T.

TEA1781_82_1

Preliminary data sheet

Rev. 01 — 13 February 2009

9 of 32

TEA1781T; TEA1782T

NXP Semiconductors

GreenChip PC secondary control ICs

5 V standby

D1

D2

R1

PS_ON#

C1

R2

PS_OFF

Digital control

STARTUP

V

< V

stop(VDD)

VDD

V

= 4 V

ENABLE

V

> V

startup(VDD)

VDD

I

> I

+ EN_NM

prot(ENABLE)

ENABLE

+ PS_OFF+ PROT_12V + UVP_STB

NORMAL

= 11 V

PROT/STDB

= 4 V

V

ENABLE

V

ENABLE

PS_OFF

system failure

detection

SYSTEM

RESTART

TEA1782

014aaa188

Fig 8. Enable Normal mode assures a proper start-up of the PFC

7.5 Soft start

When the TEA1782T enters the Protection/Standby mode after start-up, the 5 V standby

output is started up via a soft start. The main output voltages, 3.3 V, 5 V, 12 V and −12 V

are started up via a soft start when the TEA1782T enters the Normal mode. A soft start

implies that the outputs will rise gradually and simultaneously from zero to their required

value during a deﬁned period (≈ 15 ms).

When PS_OFF is turned low, the main outputs of the TEA178x chip set ensure that power

sequencing is applied according to the ATX12V speciﬁcation of Intel, i.e., the 12 V and 5 V

outputs must be equal to, or greater than, the 3.3 V output during power-up and normal

operation.

7.6 Enable

The TEA1782T is the master of the system. The required duty cycle is communicated to

the primary controller TEA1771T via the opto coupler. The TEA1782T communicates to

the TEA1781T via the enable signal, see Figure 9, if the main outputs are enabled or

disabled. If the system is in Normal mode, the voltage of the enable signal exceeds the

trip level, V_trip(ENABLE), enabling all outputs. Otherwise the main outputs are disabled.

TEA1781_82_1

Preliminary data sheet

Rev. 01 — 13 February 2009

10 of 32

TEA1781T; TEA1782T

NXP Semiconductors

GreenChip PC secondary control ICs

3.3 V / 5 V

outputs are

enabled

ENABLE

Digital control

V

< V

stop(VDD)

VDD

STARTUP

= 4 V

V

trip(ENABLE)

V

ENABLE

V

> V

startup(VDD)

V

VDD

ENABLE

I

ENABLE

I

> I

+ EN_NM

prot(ENABLE)

ENABLE

temp.prot

+ PS_OFF+ PROT_12V + UVP_STB

protection 5 V

protection 3.3 V

NORMAL

= 11 V

TEA1781

PROT/STDB

= 4 V

V

ENABLE

V

ENABLE

PS_OFF

system failure

detection

SYSTEM

RESTART

TEA1782

014aaa189

Fig 9. The ENABLE signal is for communicating between the secondary control ICs

TEA1781_82_1

Preliminary data sheet

Rev. 01 — 13 February 2009

11 of 32

TEA1781T; TEA1782T

NXP Semiconductors

GreenChip PC secondary control ICs

7.7 Output drivers

Figure 10 shows a part of the secondary side output circuitry and the applied gate drive

system.

V

/ N

V

+ 12 V

VDD

INDC

WND_SEC_x

V

0

Drive

V

/ N

0

INDC

V

FSB_x

V

DF_x

V

VOUT_x

SR

WND_SEC_x

SB

SF

V

014aaa190

(1) WND_SEC_x: The “x” stands for either 1 or 2

(2) FSR_x,, GSR_x, GSB_x, DF_x, FSB_x:

The “x” for these pins and symbols stands for either 3V3, 5V or 12V

(3) VOUT_x: The “x” stands for either 3V3, 5V, 12V1 or 12V2.

Fig 10. Output driver circuit

The freewheel switch SF is turned on and off between the VDD voltage (12 V) and ground

level as the source of SF is connected to ground. The source of switch SB varies between

zero (actually a small negative voltage when the SF or its back gate diode is conducting)

and the maximum secondary transformer voltage. Therefore the driver of SB requires a

bootstrap circuit.

When V_{DF_x}(V_{DF_3V3}, V_{DF_5V}, or V_{DF_12V}) is (about) zero, the FSB capacitor is charged to

the VDD level. Switch SB can then be turned on via this charged capacitor, as it ensures a

VDD voltage with respect to DF_x (pins DF_3V3, DF_5V, or DF_12V). As this capacitor

will be discharged when charging the gate source capacitance of SB, the driving voltage

will be slightly less than the VDD voltage.

The source of the rectifying switch SR is connected to the transformer, which can be

positive or negative. Therefore the FSR capacitor is charged via a boost circuit with a

special voltage source that is about 12 V higher than the secondary transformer voltage at

the appropriate time.

As the source of the rectifying switch SR is connected to the transformer, which can be

either negative or positive, the TEA1781T and TEA1782T are developed in a special

process (ABCD - SOI) which is capable of handling these (high) negative and positive

voltages.

TEA1781_82_1

Preliminary data sheet

Rev. 01 — 13 February 2009

12 of 32

TEA1781T; TEA1782T

NXP Semiconductors

GreenChip PC secondary control ICs

7.8 Output voltage regulation

The output voltage is regulated to the required voltage level via a current mode control

loop.

V

0

ResetSB

INDC / N

V

WND_SEC_x

V

I-control

ref

−V / N

rst

Q

R

S

I

"1"

"0"

ResetSB

SB

V/I

I

Control

closed

open

closed

open

Drive

SF

VDD

C

R

L

V

VOUT_x

SR

SB

SF

V

WND_SEC_x

014aaa191

(1) WND_SEC_x: The “x” stands for either 1 or 2

(2) GSB_x, DF_x, FSB_x, GSF_x, CS_x:

The “x” for these pins and symbols stands for either 3V3, 5V or 12V

(3) VOUT_x: The “x” stands for either 3V3, 5V, 12V1 or 12V2.

Fig 11. Output voltage regulation

When the secondary side transformer voltage is negative, switch SB is turned off to avoid

negative currents, see Figure 11. Once the secondary side transformer voltage is positive

and the output current in the secondary coil has dropped below a certain value, switch SB

is turned on again. This value is proportional to the difference between the output voltage

and the reference voltage, increased with a ramp voltage. This type of regulation is called

current mode control. A ramp voltage is required to stabilize the control loop for duty

cycles smaller than 0.5 and is called slope compensation.

The output current is measured using the output inductor series resistance. When the

L

R_L

parallel RC network is R C =

the voltage across the parallel capacitor equals the

-----

voltage across the inductors resistance. L and R_Lrepresent the inductance and the

resistance value of the output inductor.

TEA1781_82_1

Preliminary data sheet

Rev. 01 — 13 February 2009

13 of 32

TEA1781T; TEA1782T

NXP Semiconductors

GreenChip PC secondary control ICs

7.9 PowerOK

The PowerOK signal is active HIGH when the main output voltages (12 V, 5 V and 3.3 V)

are within their regulation limits. Figure 12 shows the corresponding block diagram.

5 V standby

VDD

PWROK

PowerOK

PGOOD

PowerGood

V

PGOOD

TEA1782

Protection 5 V

Protection 3.3 V

Protection 12 V

V

uvp

TEA1781

VOUT_5V

VOUT_3V3

VOUT_12V

014aaa192

Fig 12. PowerOK circuit diagram

The PGOOD output is pulled down by the TEA1781T when either the 5 V or 3.3 V is below

its lower limit, or by the TEA1782T when the 12 V is below its lower limit. When all main

outputs are above their minimum value, the PGOOD signal slowly rises from zero to the

VDD level. Once the PGOOD signal exceeds V_PGOOD, the PWROK signal becomes active

high.

A delay can be set between the output voltages reaching their end value and the PWROK

signal being active high via an RC network connected to the PGOOD pins.

7.10 Pull-down main outputs

According to the Intel ATX speciﬁcation, the main outputs (3.3 V, 5 V and 12 V) must be at

ground level in Standby mode. Therefore, these outputs are pulled low when the system is

in Standby mode.

The pull-down transistors for the 3.3 V and 5 V outputs are integrated in the TEA1781T,

whereas the pull-down transistor for the 12 V is integrated in the TEA1782T.

7.11 OPTO control

The TEA1782T deﬁnes the mode of operation of the system. It communicates with the

TEA1781T via the ENABLE pin and with the TEA1771T primary controller via the opto

coupler connected to the OPTO control block. Depending on the mode of operation, the

current to the opto coupler has the following values:

TEA1781_82_1

Preliminary data sheet

Rev. 01 — 13 February 2009

14 of 32

TEA1781T; TEA1782T

NXP Semiconductors

GreenChip PC secondary control ICs

Table 4.

OPTO control modes

Mode of operation

Standby mode

Normal mode

I_OPTO

0 mA to ≈ 3.5 mA

≈ 3.5 mA

System restart

≈ 30 mA

In Standby mode, a higher I_OPTOcurrent implies a higher duty cycle / frequency of the

system. In Normal mode, the systems duty cycle/frequency is deﬁned by the primary

controller being related to the inverse of the input voltage. The OPTO control block

diagram is given in Figure 13.

off

PVCC

OPTO control

UP

S1 S3

S2

S4

I

OPTO

DOWN

V/I

Normal mode

014aaa193

Fig 13. TEA1782T OPTO control diagram

At system start-up, the secondary controllers are supplied via a rectiﬁed secondary

winding voltage. Therefore the secondary controllers are started up after the primary side

has started up.

As the voltage at the OPTO pin is zero when the secondary controllers are not yet

supplied, the primary side starts up at the minimum duty cycle/frequency. Once the

secondary side has started, it increases the operating duty cycle/frequency of the system

depending on the standby load and mode of operation.

When the system is in Normal mode, switch S3 is closed and the opto coupler current is

increased to I_OPTO(Normal mode). In this mode, the primary duty cycle is deﬁned by the

primary controller TEA1771T and is related to the inverse of the input voltage.

When the secondary protection mode fails, switch S4 is closed and a maximum current

ﬂows through the opto coupler. This high current triggers the primary controller into

Protection mode, switching off the primary main switch. A safe restart of the system will

follow. This implies that the system will start up again after all the supply voltages, primary

and secondary, are below their UVLO levels resulting in a total reset of the system.

In Standby mode, the system minimizes the duty cycle of the primary control switch to

reduce the magnetic losses in the transformer to a minimum. As the primary duty cycle

has to be at least equal to the secondary duty cycle, the system will equalize both duty

cycles in Standby mode. This is regulated in the opto control block.

TEA1781_82_1

Preliminary data sheet

Rev. 01 — 13 February 2009

15 of 32

TEA1781T; TEA1782T

NXP Semiconductors

GreenChip PC secondary control ICs

The opto control compares the primary and secondary standby duty cycle and deﬁnes if

the primary duty cycle has to be changed, see Figure 14.

closed

open

S1

primairy

main switch

V

0

/ N

INDC

V

WND_SEC_1

−V / N

rst

closed

open

SB

decreasing prim δ

"1"

"0"

down

increasing prim δ

"1"

"0"

up

I

OPTO

014aaa194

Fig 14. TEA1782T OPTO control duty cycles

The primary duty cycle is derived from the secondary transformer voltage. If V_{WND_SEC_1}

is above a certain positive level before the switch SB is turned on, a down pulse is

generated. An up pulse is generated when V_{WND_SEC_1}is high after SB is turned on.

The current into the opto coupler is regulated until it reaches a stable value via the down

pulse and up pulse. Through the opto coupler, the primary duty cycle and frequency

eventually stabilize to provide the duty cycle required by the secondary standby converter.

7.12 Protections

7.12.1 General

All outputs have an OVP and an OCP function. The OVP and OCP functions have a delay

of t_d(prot), which is typically 18 µs.

If the output voltage or the output current on one of the main outputs (3.3 V, 5 V, 12 V1, or

12 V2) exceeds their upper limit, the system will enter Protection mode. In this mode all

main outputs are switched off by switching off all corresponding secondary switches. The

system will enter the Normal mode again after toggling the PS_ON# signal or after a

mains interruption.

A 12 V OVP / OCP is detected in the TEA1782T. When detecting a 12 V OVP or OCP, the

pin ENABLE is pulled down and as a result both the TEA1782T and the TEA1781T will

disable the main outputs. The 5 V standby output remains on.

A 3.3 V or 5 V OVP or OCP is detected in the TEA1781T and communicated to the

TEA1782 via the pin ENABLE. As a result the TEA1782T will pull down the pin ENABLE,

disabling all main outputs.

TEA1781_82_1

Preliminary data sheet

Rev. 01 — 13 February 2009

16 of 32

TEA1781T; TEA1782T

NXP Semiconductors

GreenChip PC secondary control ICs

When the 5 V standby voltage / current exceeds its upper limit the output will be switched

off. It will be turned on again at the next cycle as soon as the output voltage/current level

drops below the upper limit.

7.12.2 Undervoltage protection

When undervoltage is detected on one of the main outputs (3.3 V, 5 V, 12 V) the pin

PGOOD is pulled low which again pulls the PWROK signal low.

When undervoltage on the 5 V standby output is detected, the system switches to

Standby mode and returns back to Normal mode once the 5 V standby is above its

minimum level.

7.12.3 Overvoltage protection

As stated previously, all outputs have an OVP function. However, the 12 V1 and 12 V2

have one OVP function. It is assumed that the 12 V2 is directly coupled to the 12 V1

voltage and therefore these voltages are about equal.

All OVP levels are integrated and cannot be set externally.

7.12.4 Overcurrent protection

The OCP levels can be set externally. The maximum output current of the 12 V1 and 12

V2 are supposed to be about equal, therefore have the same OCP setting. Figure 15

gives the 12 V OCP block diagram.

TEA1781_82_1

Preliminary data sheet

Rev. 01 — 13 February 2009

17 of 32

TEA1781T; TEA1782T

NXP Semiconductors

GreenChip PC secondary control ICs

Protection mode

Protection 12 V

I

− 2 × I

> I

VOUT_12V2 ocp_12V

VOUT_12V

or 2 × I

> I

VOUT_12V2

ocp_12V

V

ovp(VOUT_12V1)

I

VOUT_12V2

TEA1782

I

VOUT_12V

I

ocp_12V

V

ref(OCP)

CS_12V

VOUT_12V1

VOUT_12V2

OCP_12V

V

VOUT_12V1

VOUT_12V2

014aaa195

Fig 15. 12 V output overcurrent protection

The total output current (equal to I_{out_12V1}+ I_{out_12V2}) is measured via an RC network

across the output inductor, using the series resistance of the output inductor. The 12V2

output current is measured using a series resistance. Subtracting these two then gives the

12V1 output current.

Both output currents are then compared to the I_ocp(12 V output) setting. If one of these

currents exceeds the I_ocp(12 V output) setting, the system will enter the Protection

mode.The system supposes the extra series resistance to be half the value of the inductor

series resistance. The I_ocp(12 V output) has a default setting of −100 µA, corresponding

to 180 mV for 12V1, and 90 mV for 12V2.

Applying a series resistance of 5 mΩ and an inductor series resistance of 10 mΩ, the

default OCP levels of the 12 V outputs are set at 18 A. The OCP levels of the 12 V outputs

can be increased by a resistor from pin OCP_12V to ground and decreased by a resistor

from pin VDD to pin OCP_12V.

The 3.3 V and 5 V OCP can be adjusted externally, whereas the system assumes

identical 3.3 V and 5 V OCP levels, see Figure 16. The output currents are measured via

an RC network across the output inductor, making use of the inductor series resistance. If

either the 5 V or 3.3 V output exceeds its OCP setting, the system enters the Protection

mode.

TEA1781_82_1

Preliminary data sheet

Rev. 01 — 13 February 2009

18 of 32

TEA1781T; TEA1782T

NXP Semiconductors

GreenChip PC secondary control ICs

Protection mode

Protection 5 V

Protection mode

Protection 3.3 V

I

> I

I

> I

ocp

VOUT_5V

ocp

VOUT_3V3

I

V

ovp(VOUT_5V)

I

ovp(VOUT_3V3)

I

ocp

VOUT_3V3

VOUT_5V

V

ref(OCP)

V

VOUT_5V

V

VOUT_3V3

014aaa196

Fig 16. 3.3 V / 5 V output overcurrent protection

The I_ocphas a default setting of −100 µA. Applying an inductor series resistance of 10 mΩ,

the default OCP level is set at 19.5 A. The OCP levels of 3.3 V and 5 V can be increased

by a resistor from pin OCP to ground and decreased by a resistor from pin VDD to pin

OCP.

The 5 V standby OCP level is set to approximately 2.5 A, assuming an inductors series

resistance of 70 mΩ. The OCP_STB level can be increased by a resistor from pin

OCP_STB to ground and decreased by a resistor from pin VDD to pin OCP_STB.

Besides changing the OCP level by a resistor connected to the OCP pin, this level can be

changed by choosing a different series resistance of the output coil.

Whereas an OCP on one of the main outputs results in a latched Protection mode, a 5 V

standby OCP also disables the output but resumes switching at the next cycle when the

output current drops below the OCP level. When the 5 V standby output voltage drops

below its minimum level, because the output current is limited, the system switches to

Standby mode.

7.12.5 Overtemperature protection

The system will enter the Protection mode at an initialized temperature level via an

external NTC network connected to the VNTC pin of the TEA1781T. In this way the

system can be protected against overtemperature.

TEA1781_82_1

Preliminary data sheet

Rev. 01 — 13 February 2009

19 of 32

TEA1781T; TEA1782T

NXP Semiconductors

GreenChip PC secondary control ICs

If an OTP is detected all main outputs will be switched off, but the 5 V standby output

remains on.

7.12.6 System restart

If an OCP, OVP, or OTP is detected on one of the main outputs, all these outputs are

switched off and latched. A OCP or OVP detection on the 5 V standby will switch off its

output but it will be resumed again at the next cycle.

All outputs can be disabled individually by disabling the bidirectional switch (SR / SB).

Disabling an output will resolve the reason why Protection mode was entered, which can

be an OVP, OCP or OTP.

If a certain time after entering Protection mode (t_d(restart)(≈ 500 µs)) the system still

detects an OCP or OVP, the secondary side enters the system restart mode. In this mode

the primary side is switched off via the opto coupler, followed by a safe restart. A

continuous error could be caused by a shorted SB switch, for example.

If a small increase of temperature is detected because of an OTP after entering Protection

mode, the system will also turn off the primary side.

So normally, an OCP, OVP or OTP will switch off the secondary outputs. Only when an

OCP, OVP or OTP remains after the outputs are switched off, will the primary side be

switched off. In that case the 5 V standby output will also drop.

8. Limiting values

Table 5.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

TEA1781T

V_{DF_5V}

voltage on pin DF_5V

−7

+40

+75

V

V_VSTARTUP

voltage on pin

VSTARTUP

−0.4

I_ocp

overcurrent protection

current

−250

+80

µA

V_{CS_5V}

voltage on pin CS_5V

−0.4

+7

V

V_{VOUT_5V}

voltage on pin

VOUT_5V

V_{VSENSE_5V}

voltage on pin

VSENSE_5V

−0.4

+7

V

V_VNTC

voltage on pin VNTC

−0.4

+7

V

V_ENABLE

voltage on pin

ENABLE

+13

V_{PGND_5V}

voltage on pin

PGND_5V

-0.8

+0.8

V

V_DD

supply voltage

−0.4

−0.8

+13

V

V_{PGND_3V3}

voltage on pin

PGND_3V3

+0.8

V_PWROK

voltage on pin PWROK

−0.4

+13

V

TEA1781_82_1

Preliminary data sheet

Rev. 01 — 13 February 2009

20 of 32

TEA1781T; TEA1782T

NXP Semiconductors

GreenChip PC secondary control ICs

Table 5.

Limiting values …continued

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

V_{VSENSE_3V3}

voltage on pin

VSENSE_3V3

−0.4

+7

V

V_{VOUT_3V3}

voltage on pin

VOUT_3V3

−0.4

+7

V

V_{CS_3V3}

voltage on pin CS_3V3

voltage on pin PGOOD

voltage on pin DF_3V3

−0.4

−7

+7

V

V_PGOOD

+7

V_{DF_3V3}

+40

V_{WND_SEC_2}

voltage on pin

WND_SEC_2

−40

General

P_tot

total power dissipation T_amb< 45 °C

storage temperature

-

<tbd>

+150

+145

W

T_stg

−55

−20

°C

T_j

junction temperature

V_esd

electrostatic discharge human body model:^[1]

voltage

all pins

−2000

+2000

V

machine model:^[2]

all pins

−200

+200

500

V

charged device

model

-

TEA1782T

V_{DF_12V}

voltage on pin DF_12V

-7

+73

+80

V

I_{OCP_12V}

current on pin

OCP_12V

−250

µA

V_{CS_12V}

voltage on pin CS_12V with respect to

V_{VOUT_12V1}

−0.4

+0.8

+0.4

+13.4

V

V_{VOUT_12V1}

V_{VOUT_12V2}

voltage on pin

VOUT_12V1

with respect to

V_{VOUT_12V2}

voltage on pin

VOUT_12V2

V_{EN_NM}

V_{PS_OFF}

voltage on pin EN_NM

−0.4

+13

V

voltage on pin

PS_OFF

V_{PGND_12V}

voltage on pin

PGND_12V

−0.8

+0.8

V

V_DD

supply voltage

−0.4

−0.8

+13

V

V_{PGND_STB}

voltage on pin

PGND_STB

+0.8

V_PGOOD

voltage on pin PGOOD

−0.4

+13

+7

V

V_{VOUT_STB}

voltage on pin

VOUT_STB

V_{CS_STB}

I_{OCP_STB}

voltage on pin

CS_STB

−0.4

+7

V

current on pin

OCP_STB

−250

+80

µA

TEA1781_82_1

Preliminary data sheet

Rev. 01 — 13 February 2009

21 of 32

TEA1781T; TEA1782T

NXP Semiconductors

GreenChip PC secondary control ICs

Table 5.

Limiting values …continued

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

−0.8

−73

Max

+73

Unit

V

V_{DF_STB}

voltage on pin DF_STB

V_{WND_SEC_1}

voltage on pin

WND_SEC_1

V

General

P_tot

total power dissipation T_amb< 45 °C

storage temperature

-

<tbd>

+150

+145

W

T_stg

−55

−20

°C

T_j

junction temperature

V_esd

electrostatic discharge human body model:^[1]

voltage

all pins

−1500

−150

+1500

V

machine model:^[2]

all pins

+150

+500

V

charged device

model

[1] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.

[2] Machine model: equivalent to discharging a 200 pF capacitor through a 0.75 µH coil and a 10 Ω series

resistor.

[3] Peak voltages up to the OVP level are allowed.

9. Thermal characteristics

Table 6.

Thermal characteristics

Parameter

Symbol

Conditions

Typ

Unit

[1]

R_th(j-a)

thermal resistance from junction in free air

to ambient

<tbd>

K/W

[1] Thermal resistance R_th(j-a)can be lower when pin GND is connected to sufﬁcient copper area on the

printed-circuit board. See the TEA1771T application notes for details.

TEA1781_82_1

Preliminary data sheet

Rev. 01 — 13 February 2009

22 of 32

TEA1781T; TEA1782T

NXP Semiconductors

GreenChip PC secondary control ICs

10. Characteristics

Table 7.

TEA1781T characteristics

T_amb= 25 °C; no over temperature; all voltages are measured with respect to ground; currents are positive when ﬂowing into

the IC; unless otherwise speciﬁed.

Symbol

Supply

V_reg(VDD)

Parameter

Conditions

Min

Typ

Max

Unit

regulation voltage on pin V_startup= 14 V to 90 V

VDD

9.0

9.5

10.1

V

I_VDD

current on pin VDD

Standby mode

Normal mode

-

1.2

1.9

-

mA

Drivers

R_pu

pull-up resistance

SR / SB drivers;

13

17

21

Ω

V_{WND(SEC)_2}= V_{DF_3V3}= V_{DF_5V}= 40 V;

V_FSR= V_{FSB_3V3}= V_{FSB_5V}= 52 V;

V_{GSB_3V3}= V_{GSB_5V}= V_GSR= 51.5 V

SF drivers; V_{DF_3V3}= V_{DF_5V}= −1 V;

_VDD− V_{GSF_3V3}(or V_{GSF_5V}) = 0.5 V

-

30

-

Ω

V

R_pd

pull-down resistance

SR / SB drivers;

3.5

4.5

5.5

V_{WND(SEC)_2}= V_{DF_3V3}= V_{DF_5V}= 40 V;

V_FSR= V_{FSB_3V3}= V_{FSB_5V}= 52 V;

V_{GSB_3V3}= V_{GSB_5V}= V_GSR= 40.5 V

SF driver; V_{DF_3V3}= V_{DF_5V}= 0 V;

_{GSF_3V3}= V_{GSF_5V}= 0.5 V

3.5

5.0

4.5

5.4

5.5

5.8

Ω

V

V_ﬂoat(UVLO)

undervoltage lockout

ﬂoating voltage

SR/SB driver

V

Control

V_trip(L)

LOW-level trip voltage

HIGH-level trip voltage

delay time

enable GSB;

voltage on pin WND_SEC_2

−4.7 −4.1 −3.5

3.4 4.5 5.6

−2.2 −1.9 −1.6

V

enable GSR;

voltage on pin DF (3.3 V and 5 V)

V

V_trip(H)

enable GSB;

voltage on pin WND_SEC_2

V

enable GSR;

voltage on pin DF (3.3 V and 5 V)

5.8

-

7.0

0.9

8.2

-

V

t_d

enable GSB

µs

I-Control 3.3 V

V_ref(3V3)

reference voltage (3.3 V) V_{CS_3V3}= V_VOUT

V_{CS_3V3}= V_VOUT+ 100 mV

3.25 3.35 3.45

3.19 3.29 3.39

V

I-Control 5 V

V_ref(5V)

reference voltage (5 V)

V_{CS_5V}= V_VOUT

4.95 5.10 5.25

4.85 5.00 5.15

V

V_{CS_5V}= V_VOUT+ 100 mV

Pins VOUT_3V3 and VOUT_5V

I_pd

pull-down current

Standby mode;

2

4

6

mA

V

V_{VOUT_3V3}= V_{VOUT_5V}= 0.4 V

Enable

V_trip(ENABLE)

trip voltage on pin

ENABLE

7.0

8.0

9.0

TEA1781_82_1

Preliminary data sheet

Rev. 01 — 13 February 2009

23 of 32

TEA1781T; TEA1782T

NXP Semiconductors

GreenChip PC secondary control ICs

Table 7.

TEA1781T characteristics …continued

T_amb= 25 °C; no over temperature; all voltages are measured with respect to ground; currents are positive when ﬂowing into

the IC; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

I_ENABLE

current on pin ENABLE

current pulled out of the pin ENABLE to

disable, to move to Protection mode

1.0

-

mA

Soft start

t_start(soft)

soft start time

10

15

20

ms

PGOOD and PWROK

I_sink(PGOOD)

sink current on pin

PGOOD

V_PGOOD= 0.4 V

6.0

2.5

2.2

16

-

mA

V

V_{trip(H)(PGOOD)}

V_{trip(L)(PGOOD)}

I_sink(PWROK)

HIGH-level trip voltage on

pin PGOOD

2.7

2.4

-

3.0

2.7

-

LOW-level trip voltage on LOW

pin PGOOD

V

sink current on pin

PWROK

V_PWROK= 0.4 V

mA

Overcurrent protection

V_ref(OCP)reference voltage on pin OCP = n.c.

1.21 1.25 1.29

V

OCP

[1]

V_ocp

overcurrent protection

voltage

V

_{CS_x}− V_VOUTactivating current

155

320

60

180

380

80

205

440

105

410

mV

protection; OCP = n.c.

V_{CS_x}− V_VOUTactivating current

protection; I_ocp= −100 µA

V_{CS_x}− V_VOUTactivating current

protection; I_ocp= 50 µA

V_{CS_x}− V_VOUTactivating current

310

360

protection during soft start; OCP = n.c.

Undervoltage/overvoltage protection

V_{uvp(VOUT_3V3)}

undervoltage protection

voltage on pin

2.60 2.80 3.00

V

VOUT_3V3

V_{uvp(VOUT_5V)}

V_{ovp(VOUT_3V3)}

undervoltage protection

voltage on pin VOUT_5V

4.00 4.25 4.50

3.76 4.00 4.25

V

overvoltage protection

voltage on pin

VOUT_3V3

V_{ovp(VOUT_5V)}

overvoltage protection

6.00 6.40 6.80

V

voltage on pin VOUT_5V

Temperature protection

V_otp(H)HIGH-level

V_ENABLE= 12 V

450

320

505

375

560

430

mV

overtemperature

protection voltage

V_otp(L)

LOW-level

V_ENABLE= 0 V

overtemperature

protection voltage

[1] V_{CS_x}: the “x” stand for either “3V3” or ”5V”.

TEA1781_82_1

Preliminary data sheet

Rev. 01 — 13 February 2009

24 of 32

TEA1781T; TEA1782T

NXP Semiconductors

GreenChip PC secondary control ICs

Table 8.

TEA1782T characteristics

T_amb= 25 °C; no over temperature; all voltages are measured with respect to ground; currents are positive when ﬂowing into

the IC; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Supply

V_startup(VDD)

start-up voltage on

pin VDD

8.0

6.9

8.5

7.4

9.0

7.9

V

V_stop(VDD)

stop voltage on pin

VDD

I_VDD

current on pin VDD

start-up delay time

-

3.0

7

-

mA

ms

t_d(startup)

5

9

Driver SF standby

R_pu

pull-up resistance

SF driver; V_{DF_12V}= V_{DF_STB}= −1 V;

-

35

-

Ω

V

_VDD− V_{GSF_12V}(or V_{GSF_STB}) = 0.5 V

SF driver; V_{DF_12V}= V_{DF_STB}= 0 V;

_{GSF_12V}= V_{GSF_STB}= 0.5 V

R_pd

pull-down

resistance

5.0

6.5

8.0

V

Drivers (12 V and SB standby)

R_pu

pull-up resistance

SR / SB drivers;

13

17

21

Ω

V_{WND(SEC)_1}= V_{DF_12V}= V_{DF_STB}= 73 V;

V_FSR= V_{FSB_12V}= V_{FSB_STB}= 85 V;

V_GSR= V_{GSB_12V}= V_{GSB_STB}= 84.5 V

SF driver; V_{DF_12V}= V_{DF_STB}= −1 V;

_VDD− V_{GSF_12V}(or V_{GSF_STB}) = 0.5 V

-

30

-

Ω

V

R_pd

pull-down

resistance

SR / SB drivers;

3.5

4.5

5.5

V_{WND(SEC)_1}= V_{DF_12V}= V_{DF_STB}= 73 V;

V_FSR= V_{FSB_12V}= V_{FSB_STB}= 85 V;

V_GSR= V_{GSF_12V}= V_{GSF_STB}= 73.5 V

V

_{DF_12V}= V_{DF_STB}= 0 V;

3.5

5.0

4.5

5.4

5.5

5.8

Ω

V_{GSF_12V}= V_{GSF_STB}= 0.5 V

V_ﬂoat(UVLO)

undervoltage

lockout ﬂoating

voltage

V

Control standby

V_trip(L)

LOW-level trip

voltage

enable GSB standby;

voltage on pin WND_SEC_1

1.0

8.0

2.0

9.0

3.0

V

V_trip(H)

HIGH-level trip

voltage

enable GSB standby;

voltage on pin WND_SEC_1

10.0

Control 12 V

V_trip(L)

LOW-level trip

voltage

enable GSB 12 V;

voltage on pin WND_SEC_1

−12.5 −11

3.8 4.6

−9.5

V

enable GSR; voltage on pin DF

5.4

V

V_trip(H)

HIGH-level trip

voltage

enable GSB 12 V;

voltage on pin WND_SEC_1

−5.5 −5.0 −4.5

enable GSR; voltage on pin DF

enable GSB 12 V

6.4

0.7

7.2

0.9

8.0

1.1

V

t_d

delay time

µs

I-control standby

V_ref(stb)

standby reference

voltage

4.85 5.00 5.15

V

[1]

V_{CS_x}= V_VOUT+ 100 mV

4.7

4.9

5.1

TEA1781_82_1

Preliminary data sheet

Rev. 01 — 13 February 2009

25 of 32

TEA1781T; TEA1782T

NXP Semiconductors

GreenChip PC secondary control ICs

Table 8.

TEA1782T characteristics …continued

T_amb= 25 °C; no over temperature; all voltages are measured with respect to ground; currents are positive when ﬂowing into

the IC; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

I-Control 12 V

V_ref(12V)

reference voltage

(12 V)

11.7 12.1 12.4

11.5 11.9 12.3

V

[1]

V_{CS_x}= V_VOUT+ 100 mV

Standby mode;

Pins VOUT_12V and VOUT_STB

I_pdpull-down current

4

6

8

mA

V_{OUT_12V}= V_{OUT_STB}= 0.4 V

Enable Normal mode

V_{EN_NM}voltage on pin

EN_NM

Digital control pin PS_OFF

1.14 1.20 1.26

0.66 0.70 0.74

V

system to Standby mode

V_trip

trip voltage

Normal mode

Standby mode

1.0

1.4

1.2

1.7

1.4

2.0

V

Enable

V_ENABLE

voltage on pin

ENABLE

Normal mode

10.5 11.0 11.5

3.8 4.2 4.6

−600 −450 −300

V

Standby mode

V

I_prot(ENABLE)

protection current

on pin ENABLE

Normal mode; Protection mode

µA

Soft start

t_start(soft)

soft start time

10

15

-

20

-

ms

PowerGood and PowerOK

I_sink(PGOOD)

sink current on pin V_PGOOD= 0.4 V

6.0

mA

PGOOD

OPTO control

I_OPTO

current on pin

OPTO

V_OPTO= 5 V

Standby mode

0

-

I_OPTO

mA

(Normal

mode)

Normal mode

system restart

−4.5 −3.5 −2.5

−40 −30 −20

mA

Overcurrent protection (OCP levels for 12 V2 are half the values given below)

V_{ref(OCP_12V)}

reference voltage

on pin OCP_12V

1.18 1.23 1.28

V

V_{ref(OCP_STB)}

reference voltage

on pin OCP_STB

TEA1781_82_1

Preliminary data sheet

Rev. 01 — 13 February 2009

26 of 32

TEA1781T; TEA1782T

NXP Semiconductors

GreenChip PC secondary control ICs

Table 8.

TEA1782T characteristics …continued

T_amb= 25 °C; no over temperature; all voltages are measured with respect to ground; currents are positive when ﬂowing into

the IC; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

[1]

V_ocp

overcurrent

protection voltage

V_{CS_x}- V_VOUTactivating current

155

180

205

mV

protection; OCP = n.c. (Can V_CSbe

changed to e.g. VCS_12V or VCS_STB

here. If so, then that is preferred here.)

V_{CS_x}− V_VOUTactivating current

320

60

380

80

440

105

mV

protection; I_OCP= −100 mA (Can V_CSbe

changed to e.g. VCS_12V or VCS_STB

here. If so, then that is preferred here.)

V_{CS_x}− V_OUTactivating current

protection; I_OCP= +50 mA (Can V_CSbe

changed to e.g. VCS_12V or VCS_STB

here. If so, then that is preferred here.)

V

_{CS_STB}− V_{VOUT_STB}activating current

230

310

270

360

310

410

mV

protection during soft start;

OCP_STB = n.c.

V_{CS_12V}− V_{VOUT_12V}activating current

protection during soft start;

OCP_12V = n.c.

Undervoltage protection/overvoltage protection

V_{uvp(VOUT_STB)}undervoltage

protection voltage

3.90 4.25 4.60

9.70 10.20 10.70

5.70 6.10 6.50

13.7 14.5 15.2

V

on pin VOUT_STB

V_{uvp(VOUT_12V1)}undervoltage

protection voltage

on pin VOUT_12V1

V_{ovp(VOUT_STB)}overvoltage

protection voltage

on pin VOUT_STB

V_{ovp(VOUT_12V1)}overvoltage

protection voltage

on pin VOUT_12V1

Protection

t_d(prot)

protection delay

time

9

18

27

µs

System restart

t_d(restart)

restart delay time

275

550

825

[1] V_{CS_x}: The “x” stands for either “12V” or “STB”

TEA1781_82_1

Preliminary data sheet

Rev. 01 — 13 February 2009

27 of 32

TEA1781T; TEA1782T

NXP Semiconductors

GreenChip PC secondary control ICs

11. Application information

S

B_3V3

R

VOUT_3V3

PWROK

28 27 26 25 24 23 22 21 20 19 18 17 15 14

TEA1781

ntc

1

2

3

4

5

6

7

8

9 10 11 12 13 14

VOUT_5V

S

B_5V

S

F_5V

S

F_STB

S

B_STB

VOUT_STB

28 27 26 25 24 23 22 21 20 19 18 17 16 15

PS_ON#

TEA1782

S

R

1

2

3

4

5

6

7

8

9 10 11 12 13 14

VOUT_12V2

VOUT_12V1

S

B_12V

S

F_12V

014aaa755

Fig 17. Application diagram

TEA1781_82_1

Preliminary data sheet

Rev. 01 — 13 February 2009

28 of 32

TEA1781T; TEA1782T

NXP Semiconductors

GreenChip PC secondary control ICs

12. Package outline

SO28: plastic small outline package; 28 leads; body width 7.5 mm

SOT136-1

D

E

A

X

c

y

H

v

M

A

E

Z

28

15

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

14

w

detail X

e

M

b

p

0

5

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

max.

(1)

UNIT

mm

A

b

c

D

E

e

H

L

Q

v

w

y

θ

1

2

3

p

E

p

Z

0.3

0.1

2.45

2.25

0.49

0.36

0.32

0.23

18.1

17.7

7.6

7.4

10.65

10.00

1.1

0.4

1.1

1.0

0.9

0.4

2.65

0.1

0.25

0.01

1.27

0.05

1.4

0.25

0.01

0.25

0.1

8^o

0^o

0.012 0.096

0.004 0.089

0.019 0.013 0.71

0.014 0.009 0.69

0.30

0.29

0.419

0.394

0.043 0.043

0.016 0.039

0.035

0.016

inches

0.055

0.01 0.004

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT136-1

075E06

MS-013

Fig 18. Package outline SOT136-1 (SO28)

TEA1781_82_1

Preliminary data sheet

Rev. 01 — 13 February 2009

29 of 32

TEA1781T; TEA1782T

NXP Semiconductors

GreenChip PC secondary control ICs

13. Revision history

Table 9.

Revision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

TEA1781_82_1

20090213

Preliminary data sheet

-

TEA1781_82_1

Preliminary data sheet

Rev. 01 — 13 February 2009

30 of 32

TEA1781T; TEA1782T

NXP Semiconductors

GreenChip PC secondary control ICs

14. Legal information

14.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

14.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

14.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

14.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

GreenChip — is a trademark of NXP B.V.

15. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

TEA1781_82_1

Preliminary data sheet

Rev. 01 — 13 February 2009

31 of 32

TEA1781T; TEA1782T

NXP Semiconductors

GreenChip PC secondary control ICs

16. Contents

1

2

3

4

5

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

7

7.1

7.2

7.3

7.4

7.5

7.6

7.7

Functional description . . . . . . . . . . . . . . . . . . . 6

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Mode of operation. . . . . . . . . . . . . . . . . . . . . . . 8

Enable Normal mode . . . . . . . . . . . . . . . . . . . . 9

Soft start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Output drivers . . . . . . . . . . . . . . . . . . . . . . . . . 12

Output voltage regulation . . . . . . . . . . . . . . . . 13

PowerOK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Pull-down main outputs . . . . . . . . . . . . . . . . . 14

OPTO control . . . . . . . . . . . . . . . . . . . . . . . . . 14

Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Undervoltage protection . . . . . . . . . . . . . . . . . 17

Overvoltage protection . . . . . . . . . . . . . . . . . . 17

Overcurrent protection . . . . . . . . . . . . . . . . . . 17

Overtemperature protection . . . . . . . . . . . . . . 19

System restart . . . . . . . . . . . . . . . . . . . . . . . . 20

7.8

7.9

7.10

7.11

7.12

7.12.1

7.12.2

7.12.3

7.12.4

7.12.5

7.12.6

8

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 20

Thermal characteristics. . . . . . . . . . . . . . . . . . 22

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 23

Application information. . . . . . . . . . . . . . . . . . 28

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 29

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 30

9

10

11

12

13

14

Legal information. . . . . . . . . . . . . . . . . . . . . . . 31

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 31

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 31

14.1

14.2

14.3

14.4

15

16

Contact information. . . . . . . . . . . . . . . . . . . . . 31

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 13 February 2009

Document identifier: TEA1781_82_1


型号：	TEA1781T
厂家：	NXP
描述：	GreenChip PC secondary control ICs 绿色芯片PC辅助控制IC PC
文件：	总32页 (文件大小：194K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TEA1781T [NXP]

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