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TFF11094HN/N1,111 [NXP]

TFF11094HN - Low phase noise LO generator QFN 24-Pin;
TFF11094HN/N1,111
型号： TFF11094HN/N1,111
厂家： NXP    NXP
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TFF11094HN - Low phase noise LO generator QFN 24-Pin
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TFF11094HN  
Low phase noise LO generator for VSAT applications  
Rev. 1 — 24 March 2011  
Product data sheet  
1. General description  
The TFF11094HN is a Ku band frequency generator intended for low phase noise Local  
Oscillator (LO) circuits for Ku band VSAT transmitters and transceivers. The specified  
phase noise complies with IESS-308 from Intelsat.  
CAUTION  
This device is sensitive to ElectroStatic Discharge (ESD). Therefore care should be taken  
during transport and handling.  
2. Features and benefits  
„ Phase noise compliant with IESS-308 (Intelsat) in combination with appropriate source  
„ LO generator with VCO range from 9.20 GHz to 9.60 GHz  
„ Input signal 36 MHz to 600 MHz  
„ Divider settings 16, 32, 64, 128 or 256  
„ Output level −4 dBm; stability ±2 dB  
„ Third or fourth order PLL  
„ Internally stabilized voltage references for loop filter  
3. Applications  
„ VSAT up converters  
„ Local oscillator signal generation  
4. Quick reference data  
Table 1.  
Quick reference data  
Operating conditions of Table 10 apply.  
Symbol Parameter  
Conditions  
Min Typ Max Unit  
VCC  
supply voltage  
3.0  
3.3 3.6  
100 130  
V
ICC  
supply current  
-
mA  
fo(RF)  
ϕn(synth)  
RF output frequency  
synthesizer phase noise  
9.20  
-
-
9.60 GHz  
divider value = 64; at 100 kHz offset; reference  
phase noise is −149 dBc/Hz at 100 kHz offset  
−97 −92  
dBc/Hz  
RLout  
output return loss  
measured at demo board and de-embedded to  
footprint  
-
-
−10 -  
dB  
αsup(sp)ref reference spurious suppression measured at divider value = 256  
-
−70  
dBc  
 
 
 
 
TFF11094HN  
NXP Semiconductors  
Low phase noise LO generator for VSAT applications  
5. Ordering information  
Table 2.  
Ordering information  
Type number Package  
Name  
Description  
Version  
TFF11094HN HVQFN24 plastic thermal enhanced very thin quad flat package;  
SOT616-1  
no leads; 24 terminals; body 4 × 4 × 0.85 mm  
6. Marking  
Table 3.  
Marking codes  
Type number  
Marking code  
TFF11094HN  
T094  
7. Block diagram  
NSL2  
6
NSL1  
5
NSL0  
4
VTUNE  
3
CPOUT VREGVCO  
2
1
10 pF  
100 kΩ  
pull up  
100 kΩ  
pull up  
100 kΩ  
pull up  
30 pF  
V
CC(DIV)  
(3.3 V)  
lock: 2.5 V  
no lock: 0 V  
7
24  
23  
22  
21  
20  
WINDOW  
2.7 V  
LCKDET  
GND1(REF)  
IN(REF)_P  
IN(REF)_N  
GND2(REF)  
GND3(BUF)  
DETECTOR  
100 kΩ  
pull down  
8
BUF2_P  
BUF1_P  
BUF2_N  
BUF1_N  
GND2(BUF)  
V
CC(BUF)  
R
R
BUF_N  
50 Ω  
BUF_P  
50 Ω  
VCO  
9
CPOUT  
VTUNE  
PFD  
CP  
DIVIDER  
10  
11  
12  
NSL0  
NSL1  
NSL2  
19  
V
CC(REF)  
13  
14  
15  
n.c.  
16  
n.c.  
17  
18  
V
GND(DIV)  
GND1(BUF) V  
CC(BUF)  
001aal724  
CC(DIV)  
Fig 1. Block diagram  
TFF11094HN  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 1 — 24 March 2011  
2 of 17  
 
 
 
TFF11094HN  
NXP Semiconductors  
Low phase noise LO generator for VSAT applications  
8. Functional diagram  
NSL2  
6
NSL1  
5
NSL0  
4
VTUNE  
3
CPOUT VREGVCO  
2
1
10 pF  
30 pF  
lock: 2.5 V  
no lock: 0 V  
7
24  
23  
22  
21  
20  
LOCK  
DETECTOR  
LCKDET  
GND1(REF)  
IN(REF)_P  
IN(REF)_N  
GND2(REF)  
2.7 V  
GND3(BUF)  
BUF2_P  
8
VCO  
9
CPOUT  
CP  
VTUNE  
OUTPUT  
BUFFER  
BUF1_P  
PFD  
DIVIDER  
NSL0  
10  
11  
12  
BUF2_N  
NSL1  
NSL2  
PLL  
BUF1_N  
19  
V
GND2(BUF)  
CC(REF)  
13  
14  
GND(DIV)  
15  
16  
n.c.  
17  
18  
V
n.c.  
GND1(BUF) V  
CC(BUF)  
001aal725  
CC(DIV)  
Fig 2. Functional diagram  
TFF11094HN  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 1 — 24 March 2011  
3 of 17  
 
TFF11094HN  
NXP Semiconductors  
Low phase noise LO generator for VSAT applications  
9. Pinning information  
9.1 Pinning  
terminal 1  
index area  
1
2
3
4
5
6
18  
17  
16  
15  
14  
13  
VREGVCO  
CPOUT  
VTUNE  
NSL0  
V
CC(BUF)  
GND1(BUF)  
n.c.  
n.c.  
NSL1  
GND(DIV)  
NSL2  
V
CC(DIV)  
001aal726  
Transparent top view  
Fig 3. Pin configuration for HVQFN24  
9.2 Pin description  
Table 4.  
Pin description  
Pin Description  
Symbol  
VREGVCO  
CPOUT  
VTUNE  
NSL0  
1
2
3
4
5
6
7
Regulated output voltage for VCO loop filter. Connect loop filter to this pin.  
Charge pump output.  
Tuning voltage for VCO.  
Divider setting, LSB. Leave open for “1”, connect to GND for “0”. See Table 8.  
Divider setting. Leave open for “1”, connect to GND for “0”. See Table 8.  
Divider setting, MSB. Leave open for “1”, connect to GND for “0”. See Table 8.  
Lock detect. Lock = 2.5 V; out of lock = 0 V. See Table 6.  
Ground for REF input. Connect this pin to the exposed diepad landing.  
Reference signal, non-inverting input. Couple this AC to the source.  
NSL1  
NSL2  
LCKDET  
GND1(REF) 8  
IN(REF)_P  
9
IN(REF)_N 10 Reference signal, inverting input. Couple this AC to the source.  
GND2(REF) 11 Ground for REF input. Connect this pin to the exposed diepad landing.  
VCC(REF)  
12 Supply of the internal regulated voltages. Decouple this pin against  
GND2(REF) (pin 11).  
VCC(DIV)  
13 Supply of the divider and PFD/CP. Decouple this pin against GND(DIV)  
(pin 14).  
GND(DIV)  
n.c.  
14 Ground of the divider. Connect this pin to the exposed diepad landing.  
15 not connected  
16 not connected  
n.c.  
GND1(BUF) 17 Ground for RF output. Connect this pin to the exposed diepad landing.  
TFF11094HN  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 1 — 24 March 2011  
4 of 17  
 
 
 
TFF11094HN  
NXP Semiconductors  
Low phase noise LO generator for VSAT applications  
Table 4.  
Pin description …continued  
Symbol  
Pin Description  
VCC(BUF)  
18 Supply voltage for the RF output buffer. Decouple this pin against GND2(BUF)  
(pin 19).  
GND2(BUF) 19 Ground for RF output. Connect this pin to the exposed diepad landing.  
BUF1_N  
BUF2_N  
BUF1_P  
BUF2_P  
20 RF output.  
21 RF output.  
22 RF output.  
23 RF output.  
GND3(BUF) 24 Ground for RF output. Connect this pin to the exposed diepad landing.  
10. Functional description  
The TFF11094HN consists of the following blocks:  
• PLL  
• Output buffer  
• Lock detector  
• Reference input  
• Divider settings  
The functionality of the blocks will be discussed below.  
10.1 PLL  
The PLL is formed by the VCO, DIVIDER (possible settings: 16, 32, 64, 128 and 256  
(see Table 8)) and a PFD/CP. The tune voltage is referred to the band gap regulated  
voltage: VREGVCO (pin 1).  
The loop filter can be set to type 2 or type 3. If a type 2 filter is used, the pins  
CPOUT (pin 2) and VTUNE (pin 3) must be interconnected. A 10 pF capacitor is placed  
internally between pins CPOUT (pin 2) and VREGVCO (pin 1), and a 30 pF capacitor is  
placed between pins VTUNE (pin 3) and VREGVCO (pin 1). See Figure 4 and Figure 5.  
Values for the loop filter components are given in Table 5.  
The VCO input voltage range is between 0.1 and 0.9 VO(reg)VCO  
.
TFF11094HN  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 1 — 24 March 2011  
5 of 17  
 
 
TFF11094HN  
NXP Semiconductors  
Low phase noise LO generator for VSAT applications  
C2  
C1  
C3  
R1  
C2  
C1  
R1  
R2  
VTUNE  
3
CPOUT  
2
VREGVCO  
1
VTUNE  
3
CPOUT  
VREGVCO  
1
2
10 pF  
10 pF  
30 pF  
30 pF  
2.7 V  
2.7 V  
001aal727  
001aal728  
Fig 4. Type 2 loop filter  
Table 5.  
Fig 5. Type 3 loop filter  
Component values used for characterization  
fi(ref)  
Divider value  
C1  
(nF)  
27  
C2  
C3  
R1  
R2  
(MHz)  
(pF)  
82  
(pF)  
33  
(Ω)  
470  
330  
270  
120  
68  
(Ω)  
35.938 to 37.500  
71.875 to 75.000  
143.750 to 150.000  
287.500 to 300.000  
575.000 to 600.000  
256  
128  
64  
560  
560  
560  
560  
560  
18  
82  
33  
18  
120  
270  
560  
33  
32  
33  
33  
16  
68  
33  
10.2 Output buffer  
The output consists of a differential pair with 50 Ω collector resistors RBUF_P and RBUF_N. If  
only one output is used, terminate the non used output with the same impedance as the  
load (see Figure 8)  
10.3 Lock detector  
The lock detector is the output of a window detector. The window detector compares the  
output voltage over the charge pump. This voltage is identical to VTUNE when a  
type 2 loop filter is used (see Figure 4). In case of a type 3 loop filter this voltage is filtered  
by R2/C3 (see Figure 5). Due to this filtering the attack and decay time will decrease.  
The lower window detector threshold voltage is 7 % of the output voltage on  
VREGVCO (pin 1), the upper window detector threshold voltage is 93 % of the output  
voltage on VREGVCO (pin 1). The hysteresis is 0.1 V. The output is 2.5 V CMOS  
compliant. The values are shown in Table 6. The timing diagram is shown in Figure 6.  
At start-up the LCKDET (pin 7) will be LOW until the circuit has acquired lock.  
TFF11094HN  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 1 — 24 March 2011  
6 of 17  
 
 
 
 
 
TFF11094HN  
NXP Semiconductors  
Low phase noise LO generator for VSAT applications  
Table 6.  
Logical value and physical value for lock detect (LCKDET)  
Logical value  
Physical value  
Lock detect state  
out of lock  
lock  
0
1
0 V  
2.5 V  
LCKDET (pin 7) has a pull-down resistor of 100 kΩ to GND1(REF) (pin 8).  
IN(REF)_P/N(t)  
t
upper window detector threshold  
(93% of V  
hysteresis voltage (0.1 V)  
)
O(reg)VCO  
VTUNE(t)  
hysteresis voltage (0.1 V)  
low window detector threshold  
(7% of V  
)
O(reg)VCO  
t
t
IN LOCK  
2.2 V  
LCKDET(t)  
0.4 V  
OUT OF LOCK (0 V)  
timeline section  
1
2
3
4
5
6
(1)  
(1)  
attack time  
decay time  
value determined Drift to maximum  
undetermined  
undetermined  
voltage is forced  
value is determined by  
closed loop operation  
PLL  
by closed loop  
opertation PLL  
voltage = lowest behavior around behavior around by loop to closed  
frequency of  
VCO  
VTUNE  
maximum  
voltage  
maximum  
voltage  
loop value of  
PLL  
actual PLL status  
PLL is in lock  
PLL is out of lock PLL is out of lock PLL is out of lock  
PLL is in lock  
PLL is in lock  
LCKDET > 2.2 V  
LCKDET  
remains > 2.2 V  
because loop  
filter is still  
window detector LCKDET < 0.4 V window detector  
LCKDET > 2.2 V  
detects that  
VTUNE > upper  
window detector  
threshold.  
detects that  
VTUNE < upper  
window detector  
threshold − 0.1 V.  
LCKDET changes  
from < 0.4 V to  
> 2.2 V during the  
decay time  
remarks  
charged  
LCKDET changes  
from > 2.2 V to  
< 0.4 V during the  
attack time  
001aal986  
(1) The attack time and decay time are typically 10 μs and are mainly depending on the drift of the VCO tuning voltage.  
Fig 6. Timing diagram lock detector  
10.4 Reference input (IN(REF)_P, IN(REF)_N)  
The reference input is a differential pair and is internally biased. The input is high ohmic.  
The input signal must be AC coupled. If used in a single ended mode, the not used input  
must be terminated with the same impedance as the driving source.  
An example of the differential source and two single ended loads are shown in Figure 7.  
An example of a single ended application is shown in Figure 8.  
TFF11094HN  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 1 — 24 March 2011  
7 of 17  
 
TFF11094HN  
NXP Semiconductors  
Low phase noise LO generator for VSAT applications  
Note that the phase noise of the output signal is also determined by the phase noise of the  
reference signal. The reference frequency range is equal to the  
output frequency / division value. Note that the output frequency is guaranteed from  
9.20 GHz to 9.60 GHz.  
10.5 Divider settings (NSL2, NSL1, NSL0)  
The divider can be set to 16, 32, 64, 128 and 256 (See Table 8). The logic levels for  
NSL0 (pin 4), NSL1 (pin 5) and NSL2 (pin 6) are given in Table 7.  
The pins have a pull-up resistor of 100 kΩ to VCC(DIV) (pin 13).  
The device is only guaranteed when NSL2, NSL1 and NSL0 are predefined at start-up (no  
change of divider value is allowed during operation).  
Table 7.  
Logical and physical value for divider setting (NSL2, NSL1, NSL0)  
Logical value  
Physical value  
GND  
0
1
open or VCC  
The truth table is shown in Table 8.  
Table 8.  
Divider setting as function of NSL2, NSL1 and NSL0  
Setting number NSL2  
NSL1  
NSL0  
Divider value  
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16  
32  
64  
128  
256  
[1]  
[1]  
[1]  
[1] Test mode, divider output will be disabled.  
11. Limiting values  
Table 9.  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
Symbol  
VCC(REF)  
VCC(DIV)  
VCC(BUF)  
Tj  
Parameter  
Conditions  
Min  
−0.5  
−0.5  
−0.5  
−40  
−40  
Max  
+3.6  
+3.6  
+3.6  
Unit  
reference supply voltage  
divider supply voltage  
buffer supply voltage  
junction temperature  
storage temperature  
V
V
V
+125 °C  
+125 °C  
Tstg  
TFF11094HN  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 1 — 24 March 2011  
8 of 17  
 
 
 
 
 
TFF11094HN  
NXP Semiconductors  
Low phase noise LO generator for VSAT applications  
12. Recommended operating conditions  
Table 10. Operating conditions  
NSL0 (pin 4), NSL1 (pin 5) and NSL2 (Pin 6) not changed during operation.  
Loop filter component values as depicted in Table 5 are used.  
Symbol Parameter  
Conditions  
Min Typ Max Unit  
Tamb  
Z0  
ambient temperature  
−40 +25 +85 °C  
characteristic impedance  
reference phase noise  
-
50  
-
-
Ω
[1]  
[1]  
[1]  
[1]  
[1]  
ϕn(ref)  
divider value = 16  
divider value = 32  
divider value = 64  
divider value = 128  
divider value = 256  
-
−134 dBc/Hz  
−143 dBc/Hz  
−149 dBc/Hz  
−150 dBc/Hz  
−151 dBc/Hz  
600 MHz  
-
-
-
-
-
-
-
-
fi(ref)  
reference input frequency fi(ref) = fo(RF) / divider value  
reference input power  
36  
-
Pi(ref)  
−10 -  
0
dBm  
[1] Required reference phase noise is set 10 dB below equivalent input phase noise.  
13. Thermal characteristics  
Table 11. Thermal characteristics  
Symbol Parameter  
Conditions  
Typ Unit  
Rth(j-sp)  
thermal resistance from junction to solder point  
25  
K/W  
14. Characteristics  
Table 12. Characteristics  
Operating conditions of Table 10 apply.  
Symbol  
VCC  
Parameter  
Conditions  
Min  
Typ  
3.3  
Max  
3.6  
Unit  
supply voltage  
supply current  
3.0  
-
V
ICC  
100  
130  
mA  
PLL  
fo(RF)  
RF output frequency  
9.20  
-
9.60  
GHz  
VO(reg)VCO VCO regulator output voltage  
2.5  
2.7  
1
2.9  
V
Icp  
charge pump current  
VCO steepness  
-
-
-
-
-
mA  
[1]  
KO  
0.6  
−130  
−97  
-
GHz/V  
dBc/Hz  
dBc/Hz  
ϕn(VCO)  
ϕn(synth)  
VCO phase noise  
at 10 MHz offset  
-
synthesizer phase noise  
divider value = 64; at 100 kHz  
offset; reference phase noise is  
−149 dBc/Hz at 100 kHz offset  
−92  
Output buffer  
[2]  
Po  
output power  
measured single ended  
−6  
−4  
−2  
dBm  
dB  
RLout  
output return loss  
measured at demo board and  
de-embedded to footprint  
-
−10  
-
αsup(sp)ref  
reference spurious suppression  
measured at divider value = 256  
-
-
−70  
dBc  
TFF11094HN  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 1 — 24 March 2011  
9 of 17  
 
 
 
 
 
TFF11094HN  
NXP Semiconductors  
Low phase noise LO generator for VSAT applications  
Table 12. Characteristics …continued  
Operating conditions of Table 10 apply.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
αH(LO)  
LO harmonic rejection  
-
−10  
-
dBc  
Lock detector  
VOL  
VOH  
Rpd  
LOW-level output voltage  
IO = 1 mA  
-
-
0.4  
-
V
HIGH-level output voltage  
pull-down resistance  
IO = −1 mA  
2.2  
70  
-
V
100  
130  
kΩ  
Divider setting (NSL0, NSL1, NSL2)  
Rpu  
VIL  
VIH  
pull-up resistance  
70  
-
100  
130  
0.8  
-
kΩ  
V
LOW-level input voltage  
HIGH-level input voltage  
-
-
2.0  
V
[1] The typical ratio of the maximum KO in relation to the minimum KO is 1.25.  
[2] Output stage is a differential pair with 50 Ω collector impedances.  
Output power is measured per output pin for the fundamental tone only.  
Output is DC coupled and is AC coupled in on-board.  
TFF11094HN  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 1 — 24 March 2011  
10 of 17  
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C2  
C1  
R1  
1 nF  
GND = 0  
open or 3.3 V = 1  
R2  
C3  
NSL2  
NSL1  
5
NSL0  
4
VTUNE  
3
CPOUT  
2
VREGVCO  
1
6
10 pF  
100 kΩ  
pull up  
100 kΩ  
pull up  
100 kΩ  
pull up  
30 pF  
V
CC(DIV)  
(3.3 V)  
lock: 2.5 V  
no lock: 0 V  
OUT-OF-LOCK  
PROCESSING  
BLOCK  
LCKDET  
7
24 GND3(BUF)  
23 BUF2_P  
22 BUF1_P  
WINDOW  
DETECTOR  
2.7 V  
100 kΩ  
pull down  
GND1(REF)  
8
V
CC(BUF)  
Z
0
= 50 Ω  
1 pF  
R
R
BUF_N  
50 Ω  
BUF_P  
50 Ω  
10 nF  
VCO  
IN(REF)_P  
9
50 Ω  
CPOUT  
VTUNE  
50 Ω  
50 Ω  
Z
0(dif)  
= 100 Ω  
PFD  
CP  
DC block  
50 Ω  
LOAD  
100 Ω  
DC block  
10 nF  
DIVIDER  
IN(REF)_N  
10  
11  
12  
21 BUF2_N  
20 BUF1_N  
NSL0  
NSL1  
NSL2  
REFERENCE  
SOURCE  
Z
0
= 50 Ω  
1 pF  
GND2(REF)  
50 Ω  
50 Ω  
LOAD  
V
CC(REF)  
19 GND2(BUF)  
3.3 V  
13  
14  
15  
16  
17  
18  
V
GND(DIV) n.c.  
n.c.  
GND1(BUF) V  
CC(BUF)  
CC(DIV)  
001aal730  
Fig 7. Application diagram with differential source for IN(REF) and both outputs driving a load, loop filter is type 3  
 
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C2  
C1  
R1  
1 nF  
GND = 0  
open or 3.3 V = 1  
R2  
C3  
NSL2  
NSL1  
5
NSL0  
4
VTUNE  
3
CPOUT  
2
VREGVCO  
1
6
10 pF  
100 kΩ  
pull up  
100 kΩ  
pull up  
100 kΩ  
pull up  
30 pF  
V
CC(DIV)  
(3.3 V)  
lock: 2.5 V  
no lock: 0 V  
OUT-OF-LOCK  
PROCESSING  
BLOCK  
LCKDET  
7
24 GND3(BUF)  
23 BUF2_P  
22 BUF1_P  
WINDOW  
DETECTOR  
2.7 V  
100 kΩ  
pull down  
GND1(REF)  
8
V
CC(BUF)  
Z
= 50 Ω  
1 pF  
0
R
R
BUF_N  
50 Ω  
BUF_P  
50 Ω  
Z
= 50 Ω  
10 nF  
VCO  
0
50 Ω  
IN(REF)_P  
9
50 Ω  
CPOUT  
VTUNE  
PFD  
CP  
DC block  
50 Ω  
LOAD  
51 Ω  
DC block  
DIVIDER  
10 nF  
IN(REF)_N  
10  
11  
12  
21 BUF2_N  
20 BUF1_N  
REFERENCE  
SOURCE  
NSL0  
NSL1  
NSL2  
not used input  
terminated with  
same impedance  
1 pF  
24 Ω  
not used output  
terminated with  
same impedance  
GND2(REF)  
51 Ω  
V
CC(REF)  
19 GND2(BUF)  
3.3 V  
13  
14  
15  
16  
17  
18  
V
GND(DIV) n.c.  
n.c.  
GND1(BUF) V  
CC(BUF)  
CC(DIV)  
001aal731  
Fig 8. Application diagram with single ended source for IN(REF) and single ended load, loop filter is type 3  
TFF11094HN  
NXP Semiconductors  
Low phase noise LO generator for VSAT applications  
16. Package outline  
HVQFN24: plastic thermal enhanced very thin quad flat package; no leads;  
24 terminals; body 4 x 4 x 0.85 mm  
SOT616-1  
B
A
D
terminal 1  
index area  
A
A
1
E
c
detail X  
e
1
C
1/2 e  
y
y
C
1
e
v
M
M
C
C
A
B
b
7
12  
w
L
13  
6
e
e
E
h
2
1/2 e  
1
18  
terminal 1  
index area  
24  
19  
X
D
h
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
(1)  
A
(1)  
(1)  
UNIT  
mm  
A
b
c
E
e
e
e
y
D
D
E
L
v
w
y
1
1
h
1
2
h
max.  
0.05 0.30  
0.00 0.18  
4.1  
3.9  
2.25  
1.95  
4.1  
3.9  
2.25  
1.95  
0.5  
0.3  
0.05  
0.1  
1
0.2  
0.5  
2.5  
2.5  
0.1 0.05  
Note  
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
01-08-08  
02-10-22  
SOT616-1  
- - -  
MO-220  
- - -  
Fig 9. Package outline SOT616-1 (HVQFN24)  
TFF11094HN  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 1 — 24 March 2011  
13 of 17  
 
TFF11094HN  
NXP Semiconductors  
Low phase noise LO generator for VSAT applications  
17. Abbreviations  
Table 13. Abbreviations  
Acronym  
CMOS  
CP  
Description  
Complementary Metal Oxide Semiconductor  
Charge Pump  
Ku band  
LSB  
K-under band  
Least Significant Bit  
MSB  
Most Significant Bit  
PFD  
Phase Frequency Detector  
Phase-Locked Loop  
PLL  
VCO  
Voltage Controlled Oscillator  
Very Small Aperture Terminal  
VSAT  
18. Revision history  
Table 14. Revision history  
Document ID  
Release date  
20110324  
Data sheet status  
Change notice  
Supersedes  
TFF11094HN v.1  
Product data sheet  
-
-
TFF11094HN  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 1 — 24 March 2011  
14 of 17  
 
 
TFF11094HN  
NXP Semiconductors  
Low phase noise LO generator for VSAT applications  
19. Legal information  
19.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
malfunction of an NXP Semiconductors product can reasonably be expected  
19.2 Definitions  
to result in personal injury, death or severe property or environmental  
damage. NXP Semiconductors accepts no liability for inclusion and/or use of  
NXP Semiconductors products in such equipment or applications and  
therefore such inclusion and/or use is at the customer’s own risk.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Customers are responsible for the design and operation of their applications  
and products using NXP Semiconductors products, and NXP Semiconductors  
accepts no liability for any assistance with applications or customer product  
design. It is customer’s sole responsibility to determine whether the NXP  
Semiconductors product is suitable and fit for the customer’s applications and  
products planned, as well as for the planned application and use of  
customer’s third party customer(s). Customers should provide appropriate  
design and operating safeguards to minimize the risks associated with their  
applications and products.  
Product specification — The information and data provided in a Product  
data sheet shall define the specification of the product as agreed between  
NXP Semiconductors and its customer, unless NXP Semiconductors and  
customer have explicitly agreed otherwise in writing. In no event however,  
shall an agreement be valid in which the NXP Semiconductors product is  
deemed to offer functions and qualities beyond those described in the  
Product data sheet.  
NXP Semiconductors does not accept any liability related to any default,  
damage, costs or problem which is based on any weakness or default in the  
customer’s applications or products, or the application or use by customer’s  
third party customer(s). Customer is responsible for doing all necessary  
testing for the customer’s applications and products using NXP  
Semiconductors products in order to avoid a default of the applications and  
the products or of the application or use by customer’s third party  
customer(s). NXP does not accept any liability in this respect.  
19.3 Disclaimers  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) will cause permanent  
damage to the device. Limiting values are stress ratings only and (proper)  
operation of the device at these or any other conditions above those given in  
the Recommended operating conditions section (if present) or the  
Characteristics sections of this document is not warranted. Constant or  
repeated exposure to limiting values will permanently and irreversibly affect  
the quality and reliability of the device.  
Limited warranty and liability — Information in this document is believed to  
be accurate and reliable. However, NXP Semiconductors does not give any  
representations or warranties, expressed or implied, as to the accuracy or  
completeness of such information and shall have no liability for the  
consequences of use of such information.  
In no event shall NXP Semiconductors be liable for any indirect, incidental,  
punitive, special or consequential damages (including - without limitation - lost  
profits, lost savings, business interruption, costs related to the removal or  
replacement of any products or rework charges) whether or not such  
damages are based on tort (including negligence), warranty, breach of  
contract or any other legal theory.  
Terms and conditions of commercial sale — NXP Semiconductors  
products are sold subject to the general terms and conditions of commercial  
sale, as published at http://www.nxp.com/profile/terms, unless otherwise  
agreed in a valid written individual agreement. In case an individual  
agreement is concluded only the terms and conditions of the respective  
agreement shall apply. NXP Semiconductors hereby expressly objects to  
applying the customer’s general terms and conditions with regard to the  
purchase of NXP Semiconductors products by customer.  
Notwithstanding any damages that customer might incur for any reason  
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards  
customer for the products described herein shall be limited in accordance  
with the Terms and conditions of commercial sale of NXP Semiconductors.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
No offer to sell or license — Nothing in this document may be interpreted or  
construed as an offer to sell products that is open for acceptance or the grant,  
conveyance or implication of any license under any copyrights, patents or  
other industrial or intellectual property rights.  
Export control — This document as well as the item(s) described herein  
may be subject to export control regulations. Export might require a prior  
authorization from national authorities.  
Suitability for use — NXP Semiconductors products are not designed,  
authorized or warranted to be suitable for use in life support, life-critical or  
safety-critical systems or equipment, nor in applications where failure or  
TFF11094HN  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 1 — 24 March 2011  
15 of 17  
 
 
 
 
TFF11094HN  
NXP Semiconductors  
Low phase noise LO generator for VSAT applications  
Non-automotive qualified products — Unless this data sheet expressly  
states that this specific NXP Semiconductors product is automotive qualified,  
the product is not suitable for automotive use. It is neither qualified nor tested  
in accordance with automotive testing or application requirements. NXP  
Semiconductors accepts no liability for inclusion and/or use of  
liability, damages or failed product claims resulting from customer design and  
use of the product for automotive applications beyond NXP Semiconductors’  
standard warranty and NXP Semiconductors’ product specifications.  
Quick reference data — The Quick reference data is an extract of the  
product data given in the Limiting values and Characteristics sections of this  
document, and as such is not complete, exhaustive or legally binding.  
non-automotive qualified products in automotive equipment or applications.  
In the event that customer uses the product for design-in and use in  
automotive applications to automotive specifications and standards, customer  
(a) shall use the product without NXP Semiconductors’ warranty of the  
product for such automotive applications, use and specifications, and (b)  
whenever customer uses the product for automotive applications beyond  
NXP Semiconductors’ specifications such use shall be solely at customer’s  
own risk, and (c) customer fully indemnifies NXP Semiconductors for any  
19.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
20. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
TFF11094HN  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 1 — 24 March 2011  
16 of 17  
 
 
TFF11094HN  
NXP Semiconductors  
Low phase noise LO generator for VSAT applications  
21. Contents  
1
2
3
4
5
6
7
8
General description. . . . . . . . . . . . . . . . . . . . . . 1  
Features and benefits . . . . . . . . . . . . . . . . . . . . 1  
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Quick reference data . . . . . . . . . . . . . . . . . . . . . 1  
Ordering information. . . . . . . . . . . . . . . . . . . . . 2  
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3  
9
9.1  
9.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4  
10  
Functional description . . . . . . . . . . . . . . . . . . . 5  
PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Output buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Lock detector . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Reference input (IN(REF)_P, IN(REF)_N) . . . . 7  
Divider settings (NSL2, NSL1, NSL0). . . . . . . . 8  
10.1  
10.2  
10.3  
10.4  
10.5  
11  
12  
13  
14  
15  
16  
17  
18  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Recommended operating conditions. . . . . . . . 9  
Thermal characteristics . . . . . . . . . . . . . . . . . . 9  
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Application information. . . . . . . . . . . . . . . . . . 11  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13  
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14  
19  
Legal information. . . . . . . . . . . . . . . . . . . . . . . 15  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
19.1  
19.2  
19.3  
19.4  
20  
21  
Contact information. . . . . . . . . . . . . . . . . . . . . 16  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2011.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 24 March 2011  
Document identifier: TFF11094HN  
 

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