TJA1124AHG [NXP]
Quad LIN master transceiver;
| 型号： | TJA1124AHG |
| 厂家： | 
NXP |
| 描述： | Quad LIN master transceiver |
| 文件： | 总23页 (文件大小：275K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TJA1124
Quad LIN master transceiver
Rev. 1 — 8 May 2018
Product data sheet
1 General description
The TJA1124 is a quad Local Interconnect Network (LIN) master channel device.
It provides the interface between a LIN master protocol controller and the physical
bus in a LIN network. Each of the four channels contains a LIN transceiver and LIN
master termination. The TJA1124 is primarily intended for in-vehicle subnetworks using
baud rates up to 20 kBd and is compliant with LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A,
ISO 17987-4:2016 (12 V LIN) and SAE J2602-1.
The transmit data streams generated by the LIN master protocol controller are converted
by the TJA1124 into optimized bus signals shaped to minimize ElectroMagnetic Emission
(EME). The LIN bus output pins are pulled HIGH via internal LIN master termination
resistors. The receivers detect receive data streams on the LIN bus input pins and
transfer them to the microcontroller via pins RXD1 to RXD4.
Power consumption is very low in Low Power mode. However, the TJA1124 can still be
woken up via pins SLP and LIN1 to LIN4.
2 Features and benefits
2.1 General
• Four LIN master channels in a single package:
– LIN transceiver
– LIN master termination consisting of a diode and a 1 kΩ ±10 % resistor
• Compliant with:
– LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A
– ISO 17987-4:2016 (12 V LIN)
– SAE J2602-1
• Very low current consumption in Low Power mode with wake-up via SLP or LIN pins
• Option to control an external voltage regulator via the INHN output
• Bus signal shaping optimized for baud rates up to 20 kBd
• VIO input for direct interfacing with 3.3 V and 5 V microcontrollers
• Passive behavior in unpowered state
• Undervoltage detection
• K-line compatible
• Leadless DHVQFN24 package (3.5 mm × 5.5 mm) supporting improved Automated
Optical Inspection (AOI) capability
2.2 Protection
• Excellent ElectroMagnetic Immunity (EMI)
NXP Semiconductors
TJA1124
Quad LIN master transceiver
• Very high ESD robustness: ±6 kV according to IEC61000-4-2 for pins LIN1 to LIN4 and
BAT
• Bus terminal and battery pin protected against transients in the automotive environment
(ISO 7637)
• Bus terminal short-circuit proof to battery and ground
• TXD dominant timeout function
• LIN dominant timeout function
• Thermal protection
3 Ordering information
Table 1.ꢀOrdering information
Type number
Package
Name
Description
Version
TJA1124AHG[1]
TJA1124BHG[2]
DHVQFN24 plastic dual in-line compatible thermal enhanced very thin quad flat
package; no leads; 24 terminals; body 3.5 × 5.5 × 0.85 mm
SOT 815-1
[1] The LIN master termination of TJA1124AHG is enabled in Low Power mode.
[2] The LIN master termination of TJA1124BHG is disabled in Low Power mode
4 Block diagram
TJA1124
UNDERVOLTAGE
DETECTION
VOLTAGE
REFERENCE
BAT
UNDERVOLTAGE
VIO
DETECTION
LIN CHANNEL 1
V
BAT
LIN TRANSCEIVER
LIN
SLP
TRANSCEIVER
CONTROL
TXD1
LIN1
RXD1
SYSTEM
CONTROL
TXD2
RXD2
TXD3
LIN CHANNEL 2
LIN2
LIN3
LIN4
RXD3
LIN CHANNEL 3
TXD4
RXD4
LIN CHANNEL 4
GND
INHN
TEMPERATURE
PROTECTION
aaa-029893
Figure 1.ꢀBlock diagram
TJA1124
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© NXP B.V. 2018. All rights reserved.
Product data sheet
Rev. 1 — 8 May 2018
2 / 23
NXP Semiconductors
TJA1124
Quad LIN master transceiver
5 Pinning information
5.1 Pinning
terminal 1
index area
2
3
23
22
21
20
19
18
17
16
15
14
n.c.
GND
LIN1
LIN2
GND
RXD1
RXD2
VIO
n.c.
GND
LIN4
LIN3
GND
SLP
4
5
6
TJA1124
7
8
RXD4
RXD3
i.c.
9
10
11
GND
TXD1
TXD4
aaa-029894
Transparent top view
Figure 2.ꢀPin configuration diagram
5.2 Pin description
Table 2.ꢀPin description
Symbol
BAT
Pin[1]
Description
battery supply
not connected
ground
1
n.c.
2
GND
LIN1
3
4
LIN bus line 1 input/output
LIN bus line 2 input/output
ground
LIN2
5
GND
RXD1
RXD2
VIO
6
7
receive data output 1; active LOW after a wake-up event on LIN1
receive data output 2; active LOW after a wake-up event on LIN2
supply voltage for I/O level adapter
ground
8
9
GND
TXD1
TXD2
TXD3
TXD4
i.c.
10
11
12
13
14
15
16
transmit data input 1
transmit data input 2
transmit data input 3
transmit data input 4
internally connected; should be connected to ground
receive data output 3; active LOW after a wake-up event on LIN3
RXD3
TJA1124
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Product data sheet
Rev. 1 — 8 May 2018
3 / 23
NXP Semiconductors
TJA1124
Quad LIN master transceiver
Symbol
Pin[1]
17
Description
RXD4
SLP
receive data output 4; active LOW after a wake-up event on LIN4
18
sleep control input; resets wake-up request on RXD
GND
LIN3
LIN4
GND
n.c.
19
ground
20
LIN bus 3 input/output
LIN bus 4 input/output
ground
21
22
23
not connected
INHN
24
inhibit output for controlling an external voltage regulator; open-drain;
active LOW
[1] For enhanced thermal and electrical performance, solder the exposed center pad of the DHVQFN24 package to board
ground.
TJA1124
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© NXP B.V. 2018. All rights reserved.
Product data sheet
Rev. 1 — 8 May 2018
4 / 23
NXP Semiconductors
TJA1124
Quad LIN master transceiver
6 Functional description
The TJA1124 is the interface between the LIN master protocol controller and the physical
bus in a LIN network. Each of its four channels incorporates a LIN transceiver and LIN
master termination. According to the Open System Interconnect (OSI) model, this device
comprises the LIN physical layer.
The TJA1124 is intended for, but not limited to, automotive LIN master applications with
multiple LIN master channels. It provides excellent ElectroMagnetic Compatibility (EMC)
performance.
6.1 LIN 2.x/SAE J2602 compliance
The TJA1124 is fully compliant with LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A, ISO
17987-4:2016 (12 V LIN) and SAE J2602-1.
6.2 Operating modes
The TJA1124 supports two main operating modes: Normal mode and Low Power mode.
Additional battery supply undervoltage (Off), intermediate VIO undervoltage (VIO UV),
intermediate wake-up signalling (Standby) and overtemperature protection (Overtemp)
modes are supported. The TJA1124 state diagram is shown in Figure 3.
V
< V
th(det)poff
BAT
from any mode
except Low Power
Off
(1)
T
vj
< T
rel(otp)
V
> V
th(det)pon
BAT
SLP = 1
for t > t
gotolp(high)SLP
Low
Power
Overtemp
Normal
T
vj
> T
sd(otp)
(2)
SLP = 0
for t > t
wake(low)SLP
(V > V
IO
uvr(VIO)
(2)
SLP = 0 for
for t > t
)
d(uvr)
AND
SLP = 0
t > t
twake(low)SLP
V
< V
IO
for t > t
uvd(VIO)
d(uvd-lp)
LINx wake-up
V
< V
uvd(VIO)
IO
for t > t
d(uvd)
from NORMAL,
STANDBY
VIO UV
Standby
(V > V
IO
uvr(VIO)
for t > t
)
d(uvr)
AND
SLP = 1
LINx wake-up
aaa-029900
(1) A transition from Low Power mode to Off mode is triggered when VBAT drops below typ. 2.4 V.
(2) The SLP input threshold depends on VIO. This mode transition will not take place when
VSLP > 0.75VIO.
Figure 3.ꢀState diagram
TJA1124
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© NXP B.V. 2018. All rights reserved.
Product data sheet
Rev. 1 — 8 May 2018
5 / 23
NXP Semiconductors
TJA1124
Quad LIN master transceiver
6.2.1 Off mode
When the TJA1124 is in Off mode, all input signals are ignored and all output drivers are
off. All pending LIN wake-up event flags are reset. The device is in a defined passive,
low-power state in Off mode.
The TJA1124 switches to Off mode when the voltage on pin BAT drops below the power-
off detection threshold, Vth(det)poff. When the TJA1124 is in Overtemp mode, it switches to
Off mode when the junction temperature drops below Trel(otp)
.
6.2.2 Low Power mode
The TJA1124 consumes significantly less power in Low Power mode than in Normal
mode. While current consumption is very low in Low Power mode, the TJA1124 can
still detect remote wake-up events on pins LINx (see Section 6.3.1) and microcontroller
wake-up events on pin SLP (see Section 6.3.2).
Pin INHN is set floating when the TJA1124 switches to Low Power mode.
A HIGH level on pin SLP in Normal mode lasting longer than tgotolp(high)SLP initiates a
transition to Low Power mode. The LIN transmit path is disabled when pin SLP is HIGH.
The transition to Low Power mode takes up to td(lp)
The TJA1124 switches from VIO UV mode to Low Power mode if the voltage on pin VIO
remains below Vuvd(VIO) for longer than td(uvd-lp)
.
.
6.2.3 Standby mode
In Standby mode, the LIN transmitter is off and the INHN output is LOW. The TJA1124
switches from Low Power mode to Standby mode when a remote wake-up is detected
on one or more of the LIN pins (LIN1 to LIN4). The source(s) of a wake-up event(s) is
indicated to the microcontroller by a LOW level on the respective RXD pin(s) (RXD1 to
RXD4).
The remaining LIN channels are still able to detect remote wake-up events during and
after the transition to Standby mode. The transition to Standby mode takes tinit.
The TJA1124 switches from VIO UV mode to Standby mode when the voltage on pin VIO
remains above Vuvr(VIO) for longer than td(uvr) and pin SLP is HIGH.
6.2.4 Normal mode
The TJA1124 can transmit and receive data via the LIN bus in Normal mode.
The receiver detects a data stream on a LIN bus input pin (LIN1 to LIN4) and transfers it
to the microcontroller via the associated RXD pin (RXD1 to RXD4): HIGH for a recessive
level and LOW for a dominant level on the bus. The receiver has a supply-voltage related
threshold with hysteresis and an integrated filter to suppress bus line noise.
The transmitter converts a transmit data stream, received from the protocol controller
and detected on pin TXDx, into optimized bus signals. The optimized bus signals are
shaped to minimize EME. The LINx bus output pin is pulled HIGH via an internal master
termination resistor.
If pin SLP is pulled LOW for longer than twake(low)SLP while the TJA1124 is in Low Power
or Standby mode, the LIN transceiver switches to Normal mode. The transition to Normal
mode from Low Power or Off modes takes tinit.
TJA1124
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Product data sheet
Rev. 1 — 8 May 2018
6 / 23
NXP Semiconductors
TJA1124
Quad LIN master transceiver
The TJA1124 switches from VIO UV mode to Normal mode when the voltage on pin VIO
remains above Vuvr(VIO) for longer than td(uvr) and pin SLP is LOW.
6.2.5 VIO UV mode
In VIO UV mode, the LINx outputs are recessive, the INHN output is LOW, the RXDx
outputs are HIGH, and the digital inputs are ignored.
The TJA1124 switches from Normal or Standby mode to VIO UV mode when the voltage
on pin VIO drops below the VIO undervoltage detection threshold, Vuvd(VIO), for longer
than td(uvd)
.
6.2.6 Overtemp mode
Overtemp mode prevents the TJA1124 from being damaged by excessive temperatures.
If the junction temperature exceeds the shutdown threshold, Tsd(otp), the thermal
protection circuit disables the LIN channel output drivers and the LIN master pull-up
resistors (see Section 6.8) and pending wake-up events are cleared.
6.3 Device wake-up
6.3.1 Remote wake-up via the LIN bus
The TJA1124 can detect remote LIN wake-up events in Low Power and Standby modes.
A falling edge on pin LINx followed by a dominant level maintained for twake(dom)LIN
,
followed by a recessive level, is regarded as a remote wake-up request. The detection of
a remote LIN wake-up event is signaled on pin RXDx (see Figure 4 and Figure 5).
LIN recessive
V
BUSrec
V
LINx
t
V
wake(dom)LIN
BUSdom
LIN dominant
ground
t
init
Initialize Standby
Standby
Low Power
mode
RXDx
(1)
HIGH
LOW
aaa-029901
(1) RXDx HIGH level depends on VIO.
Figure 4.ꢀPrinciple of remote wake-up via LIN bus in Low Power mode
TJA1124
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© NXP B.V. 2018. All rights reserved.
Product data sheet
Rev. 1 — 8 May 2018
7 / 23
NXP Semiconductors
TJA1124
Quad LIN master transceiver
LIN recessive
V
BUSrec
V
LINx
t
V
wake(dom)LIN
BUSdom
LIN dominant
ground
mode
RXDx
Standby
LOW
Standby
(1)
HIGH
aaa-029902
(1) RXDx HIGH level depends on VIO.
Figure 5.ꢀPrinciple of remote wake-up via LIN bus in Standby mode
6.3.2 Local wake-up via pin SLP
A LOW level on pin SLP lasting at least twake(low)SLP is interpreted as a local wake-up
request.
6.4 Operation during automotive cranking pulses
The TJA1124 remains fully operational during automotive cranking pulses because it is
specified down to VBAT = 5 V.
6.5 Operation when supply voltage is outside specified operating range
If VBAT > 28 V or VBAT < 5 V, the TJA1124 may remain operational, but parameter values
(as specified in Table 5 and Table 6) cannot be guaranteed.
If the voltage on pin BAT drops below the power-off detection threshold, Vth(det)poff, the
TJA1124 switches to Off mode (see Section 6.2.1).
In Normal mode:
• If the input level on pin LINx is recessive, the respective receiver output on pin RXDx
will be HIGH.
• If the input level on pin TXDx is HIGH, the respective LIN transmitter ouput on pin LINx
will be recessive.
6.6 TXD dominant time-out function
Once a transmitter has been enabled, its TXD dominant timeout timer is started every
time the associated TXD pin goes LOW. If the LOW state on TXDx persists for longer
than the TXD dominant timeout time (tto(dom)TXD), the transmitter is disabled, releasing the
bus line to recessive state. The TXD dominant timeout timer is reset when pin TXDx goes
HIGH.
TJA1124
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Product data sheet
Rev. 1 — 8 May 2018
8 / 23
NXP Semiconductors
TJA1124
Quad LIN master transceiver
6.7 LIN dominant timeout function
Each LIN channel has an associated LIN dominant timeout function. This function
switches off the LIN master termination resistor, Rmaster or Rmaster(lp), if the LIN bus level
remains dominant for longer than tto(dom)LIN. LIN termination resistor Rslave remains active
as pull-up when Rmaster or Rmaster(lp) is switched off.
Once the LIN bus level is recessive again, the LIN master termination is switched on and
the LIN dominant timeout timer is reset.
6.8 LIN master pull-up
In Normal and Standby modes, the integrated LIN master termination, Rmaster, is a
trimmed 1 kΩ pull-up with a tolerance of ±10 %.
In Low Power mode, the integrated LIN pull-up depends on the TJA1124 variant. In
the TJA1124A, an untrimmed LIN master termination, Rmaster(lp), is enabled. In the
TJA1124B, LIN master termination is disabled and the LINx pins are terminated with the
LIN termination resistor, Rslave
.
6.9 Fail-safe features
A loss of power (pin BAT or GND) has no impact on the bus lines or on the
microcontroller interface pins. When the battery supply is lost, reverse current
IBUS_NO_BAT flows from the bus into pins LINx. When the ground connection is lost,
current IBUS_NO_GND continues to flow from BAT to LINx via an integrated LIN termination
resistor, Rslave. The current path through the LIN master termination is disabled.
The output drivers on the LINx pins are protected against overtemperature conditions
(see Section 6.2.6).
7 Limiting values
Table 3.ꢀLimiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to pin GND; unless
otherwise specified. Positive currents flow into the IC.
Symbol Parameter
Conditions
Min
-0.3
-0.3
-0.3
-43
-
Max
+43
Unit
V
Vx
voltage on pin x
pins BAT, INHN
pin VIO
+6
V
pins SLP, RXDx, TXDx
pins LINx with respect to any other pin
VIO + 0.3
+43
V
V
IINHN
Vtrt
input current on pin INHN
3
mA
V
[1]
[2]
transient voltage on pin BAT
on pin BAT with inverse-polarity protection
diode and 22 µF capacitor to ground
-150
+100
on pins LIN1, LIN2, LIN3, LIN4 coupled
via 1 nF capacitor
VESD
electrostatic discharge voltage IEC61000-4-2
on pins LIN1, LIN2, LIN3 and LIN4; on
-6
+6
kV
pin BAT with capacitor
TJA1124
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Product data sheet
Rev. 1 — 8 May 2018
9 / 23
NXP Semiconductors
TJA1124
Quad LIN master transceiver
Symbol Parameter
Conditions
Min
Max
Unit
[3]
[4]
Human Body Model (HBM)
on pins LIN1, LIN2, LIN3 and LIN4
on pin BAT, INHN
-6
-4
-2
+6
+4
+2
kV
kV
kV
on pins SLP, RXDx, TXDx
Charged Device Model
all pins
[5]
[6]
-500
-40
+500
+150
+150
V
Tvj
virtual junction temperature
storage temperature
°C
°C
Tstg
-55
[1] According to ISO 7637 part 2 automotive transient test pulses 1, 2a, 3a and 3b.
[2] Equivalent to discharging a 150 pF capacitor through a 330 Ω resistor.
[3] According to AEC-Q100-002; equivalent to discharging a 100 pF capacitor through a 1.5 kΩ resistor.
[4] BAT and VIO connected to GND, emulating the application circuit.
[5] According to AEC-Q100-011.
[6] Junction temperature in accordance with IEC 60747-1. An alternative definition is: Tvj = Tamb + P × Rth(vj-a), where Rth(vj-a) is a fixed value. The rating for Tvj
limits the allowable combinations of power dissipation (P) and ambient temperature (Tamb).
8 Thermal characteristics
Table 4.ꢀThermal characteristics
Symbol
Parameter
Conditions
Typ
Unit
[1]
Rth(j-a)
thermal resistance from junction to ambient
DHVQFN24; four-layer
board
51
K/W
[1] According to JEDEC JESD51-2, JESD51-5 and JESD51-7 at natural convection on 2s2p board. Board with two inner copper layers (thickness: 35 µm)
and thermal via array under the exposed pad connected to the first inner copper layer
9 Static characteristics
Table 5.ꢀStatic characteristics
Tvj = -40 °C to +150 °C; VBAT = 5.0 V to 28 V; VIO = 2.97 V to 5.5 V; all voltages are referenced to pin GND; positive currents
flow into the IC; typical values are given at VBAT = 12 V; unless otherwise specified [1]
Symbol
Supply
VBAT
Parameter
Conditions
Min
Typ
Max
Unit
battery supply voltage
operating range
operating range
5
-
-
28
V
V
VIO
supply voltage for I/O level
adapter
2.97
5.5
[2]
[2]
IBAT
battery supply current
TJA1124A; Low Power mode;
-
-
-
7.3
6
17.2
15
µA
µA
mA
VSLP = VIO; VLINx = VBAT
;
-40 °C < Tvj < 85 °
TJA1124B; Low Power mode;
VSLP = VIO; VLINx = VBAT
;
-40 °C < Tvj < 85 °
Normal mode; bus recessive;
12
22
VTXDx = VIO; VSLP = 0 V;
VLINx = VBAT
TJA1124
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© NXP B.V. 2018. All rights reserved.
Product data sheet
Rev. 1 — 8 May 2018
10 / 23
NXP Semiconductors
TJA1124
Quad LIN master transceiver
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Normal mode; bus dominant;
-
66
87
mA
VLINx = VSLP = 0 V;
VBAT = 12 V
IIO
supply current on pin VIO
Low Power mode;
-40 °C < Tvj < 85 °C
-
-
6
-
9
1
µA
Normal mode
mA
Supply undervoltage; pins BAT and VIO
Vth(det)poff
Vth(det)pon
Vhys(det)pon
Vuvd(VIO)
power-off detection threshold
voltage
4.0
4.25
200
2.7
2.8
50
-
4.51
4.77
-
V
power-on detection threshold
voltage
-
V
power-on detection hysteresis
voltage
-
mV
V
undervoltage detection voltage on
pin VIO
2.8
2.9
-
2.9
3.1
-
Vuvr(VIO)
undervoltage recovery voltage on
pin VIO
V
Vuvhys(VIO)
undervoltage hysteresis voltage
on pin VIO
mV
Sleep control input and LIN transmit data inputs: SLP and TXDx; all measurements taken in Normal mode
Vth(sw)
switching threshold voltage
0.25VIO
-
-
0.75VIO
-
V
V
Vth(sw)hys
switching threshold voltage
hysteresis
0.035VIO
Rpu
pull-up resistance
on pin SLP
38
38
38
60
60
60
88
88
88
kΩ
kΩ
kΩ
on pins TXDx; VTXD > 0.75 VIO
on pins TXDx; VTXD < 0.25 VIO
Rpd
pull-down resistance
LIN receive data outputs; pins RXDx; all measurements taken in Normal mode
VOH
VOL
HIGH-level output voltage
LOW-level output voltage
pull-up resistance
IOH = -4 mA
IOL = 4 mA
VIO – 0.4
V
0.4
88
+5
V
Rpu
38
-5
60
kΩ
µA
ILO(off)
off-state output leakage current
VO = 0 V to VIO
IOL = 0.2 mA
Inhibit output; pin INHN
VOL
LOW-level output voltage
off-state output leakage current
0.4
+5
V
ILO(off)
-5
µA
LIN bus line; pins LIN1, LIN2, LIN3, LIN4
VO(dom)
dominant output voltage
Normal mode;
VBAT = 7.0 V
-
-
-
-
1.4
3.6
200
V
Normal mode;
VBAT = 18.0 V
-
V
IBUS_LIM
current limitation for driver
dominant state
VBAT = 18 V; VLINx = 18 V; LIN
driver on; Rmaster off
40
mA
TJA1124
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© NXP B.V. 2018. All rights reserved.
Product data sheet
Rev. 1 — 8 May 2018
11 / 23
NXP Semiconductors
TJA1124
Quad LIN master transceiver
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IBUS_PAS_dom receiver dominant input leakage
current including pull-up resistor
VBAT = 12 V; VLINx = 0 V; LIN
driver off; Rmaster off
-1
-
-
mA
VBAT = 28 V; VLINx = 0 V; LIN
driver off; Rmaster off
-1.5
-
-
-
-
mA
µA
IBUS_PAS_rec receiver recessive input leakage 5 V < VBAT < 18 V;
20
current
5 V < VLINx < 18 V;
VLINx ≥ VBAT; LIN driver off
18 V < VBAT < 28 V;
-
-
30
µA
18 V < VLINx < 28 V;
VLINx ≥ VBAT; LIN driver off
[2]
[2]
[2]
IBUS_NO_GND loss-of-ground bus current
VBAT = 12 V; VGND = VBAT
0 V < VLINx < 18 V
;
-1
-
-
+1
mA
mA
VBAT = 12 V; VGND = VBAT
0 V < VLINx < 28 V
;
-1.5
+1.5
IBUS_NO_BAT loss-of-battery bus current
VBAT = 0 V; 0 V < VLINx < 28 V
-
-
-
-
30
µA
V
VBUSdom
VBUSrec
receiver dominant state
receiver recessive state
receiver center voltage
-
0.4VBAT
-
0.6VBAT
V
[3]
VBUS_CNT
Normal mode; VBUS_CNT
Vth_rec + Vth_dom) / 2;
7 V ≤ VBAT < 28 V
=
=
0.475VBAT 0.5VBAT 0.525VBAT
0.45VBAT 0.5VBAT 0.55VBAT
0.47VBAT 0.5VBAT 0.54VBAT
V
Normal mode; VBUS_CNT
Vth_rec + Vth_dom) / 2;
5 V < VBAT < 7 V
V
V
Low Power mode; VBUS_CNT
(Vth_rec + Vth_dom) / 2
=
[3]
[2]
VHYS
receiver hysteresis voltage
VHYS = (Vth_rec - Vth_dom
)
-
-
-
0.175VBAT
1.0
V
V
VSerDiode
voltage drop at the serial diodes
in pull-up path with Rmaster
;
0.4
ISerDiode = 12 mA
[2]
in pull-up path with Rslave
;
0.4
-
1.0
V
ISerDiode = 0.9 mA
Rmaster
master resistance
Normal mode; including Rslave
900
900
1000
1200
1100
1500
Ω
Ω
Rmaster(lp)
low -power master resistance
Low Power mode; including
Rslave
Rslave
CLIN
slave resistance
Rmaster off
20
-
30
-
60
20
kΩ
pF
[2]
capacitance on pin LINx
Thermal shutdown
Tsd(otp) overtemperature protection
[2]
[2]
150
122
165
137
179
150
°C
°C
shutsown temperature
Trel(otp)
overtemperature protection
release temperature
[1] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to cover the specified
temperature and power supply voltage ranges.
[2] Not tested in production; guaranteed by design.
[3] Vth_dom: receiver threshold of the recessive to dominant LIN bus edge. Vth_rec: receiver threshold of the dominant to recessive LIN bus edge.
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10 Dynamic characteristics
Table 6.ꢀDynamic characteristics
Tvj = -40 °C to +150 °C; VBAT = 5.0 V to 28 V; VIO = 2.97 V to 5.5V; all voltages are referenced to pin GND; positive currents
flow into the IC; typical values are given at VBAT = 12V; unless otherwise specified [1]
Symbols Parameter
Conditions
Min Typ Max Unit
Duty cycles; pins LIN1, LIN2, LIN3, LIN4
[2]
[3]
[4]
δ1
δ2
δ3
δ4
duty cycle 1
duty cycle 2
duty cycle 3
duty cycle 4
Vth(rec)(max) = 0.744 x VBAT
;
0.396 -
-
Vth(dom)(max) = 0.581 x VBAT
tbit = 50 µs; VBAT = 7 V to 28 V
Vth(rec)(max) = 0.744 x VBAT
Vth(dom)(max) = 0.581 x VBAT
tbit = 50 µs; VBAT = 5 V to 7 V
Vth(rec)(min) = 0.442 x VBAT
Vth(dom)(min) = 0.284 x VBAT
tbit = 50 µs; VBAT = 7.6 V to 28 V
Vth(rec)(min) = 0.442 x VBAT
Vth(dom)(min) = 0.284 x VBAT
tbit = 50 µs; VBAT = 5.6 V to 7.6 V
Vth(rec)(max) = 0.778 x VBAT
Vth(dom)(max) = 0.616 x VBAT
tbit = 96 µs; VBAT = 7 V to 28 V
Vth(rec)(max) = 0.778 x VBAT
Vth(dom)(max) = 0.616 x VBAT
tbit = 96 µs; VBAT = 5 V to 7 V
Vth(rec)(min) = 0.389 x VBAT
Vth(dom)(min) = 0.251 x VBAT
tbit = 96 µs; VBAT = 7.6 V to 28 V
Vth(rec)(min) = 0.389 x VBAT
Vth(dom)(min) = 0.251 x VBAT
;
[2]
[3]
[4]
;
0.37
-
-
-
-
;
[2]
[3]
[4]
;
-
-
0.581
0.581
-
;
[2]
[3]
[4]
;
;
[2]
[3]
[4]
;
0.417 -
0.417 -
;
[2]
[3]
[4]
;
-
;
[2]
[3]
[4]
;
-
-
-
-
0.590
0.590
;
[2]
[3]
[4]
;
;
tbit = 96 µs; VBAT = 5.6 V to 7.6 V
LIN receiver; pins LIN1, LIN2, LIN3, LIN4
[4]
[4]
trx_pd
receiver propagation delay
rising and falling edge;
7 V ≤ VBAT < 28 V
-
-
-
-
6
µs
µs
rising and falling edge;
5 V < VBAT < 7 V
6.5
trx_sym
receiver propagation delay
symmetry
rising edge with respect to falling edge
-2
-
+2
µs
µs
twake(dom)LIN LIN dominant wake-up time
30
80
150
tto(dom)LIN
tto(dom)TXD
Mode transition
LIN dominant time-out time
timer started at falling edge on LINx
timer started at falling edge on TXDx
17.5 20
23.5 ms
10 ms
TXD dominant time-out time
6
-
-
twake(low)SLP sleep LOW wake-up timeout time for wake-up from Low Power or Standby
to Normal mode
1.75
4.65 µs
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Symbols Parameter
Conditions
Min Typ Max Unit
ttgotolp(high)SLP sleep HIGH to low power time
for transition form Normal to Low Power
mode
5.2
6
6.7
µs
tinit
initialization time
Normal and Standby modes
-
-
-
-
1
ms
ms
ms
td(lp)
low power mode delay time
-
2
td(uvd-lp)
delay time from VIO UV to low
power mode
175
225
td(uvd)
td(uvr)
undervoltage detection delay time
undervoltage recovery delay time
5
5
-
-
10
10
µs
µs
[1] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to cover the specified
temperature and power supply voltage ranges.
[2]
[3] Bus load conditions: Rmaster = off; CLIN = 1 nF and RLIN = 1 kΩ; CLIN = 6.8 nF and RLIN = 660 Ω; CLIN = 10 nF and RLIN = 500 Ω. See timing test circuit in
Fig 9.
[4] See timing diagram in Fig 10.
V
t
t
TXDx
bit
bit
V
V
V
V
th(rec)(max)
th(dom)(max)
th(rec)(min)
th(dom)(min)
threshold of
receiving node 1
LINx bus
signal
t
t
bus(rec)min
bus(dom)max
V
BAT
threshold of
receiving node 2
t
t
bus(rec)max
bus(dom)min
receiving node 1
receiving node 2
V
t
t
RXDx
rx_pdf
rx_pdr
V
t
RXDx
t
t
rx_pdr
rx_pdf
rx_pdf
aaa-027897
Figure 6.ꢀTiming diagram of LIN duty cycle
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11 Application information
11.1 Application diagram
V
ECU
BATTERY
+3 V/
+5 V
V
V
IO
DD
INHN
TJA1124
GND
BAT
GPIO
TX1
RX1
TX2
RX2
TX3
RX3
TX4
RX4
SLP
TXD1
RXD1
TXD2
RXD2
TXD3
RXD3
TXD4
RXD4
LIN1
LIN2
LIN3
LIN4
MICRO-
CONTROLLER
LIN BUS
LINES
(1)
GND
aaa-029903
1. Typically specified by car manufacturer, e.g. 680pF
Figure 7.ꢀApplication diagram
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11.2 ESD robustness according to LIN EMC test specification
ESD robustness (IEC 61000-4-2) has been tested by an external test house according to
the LIN EMC test specification (part of Conformance Test Specification Package for LIN
2.1, October 10th, 2008). The test report is available on request.
Table 7.ꢀESD robustness (IEC 61000-4-2) according to LIN EMC test specification
Pin
Test configuration
Value
±8
Unit
kV
LINx
no capacitor connected to LINx pin
220 pF capacitor connected to LINx pin
22 µF and 100 nF capacitors connected to pin BAT
±8
kV
BAT
>|15|
kV
12 Test information
12.1 Quality information
After product release this product has been qualified in accordance with the Automotive
Electronics Council (AEC) standard Q100 - Failure mechanism based stress test
qualification for integrated circuits, and is suitable for use in automotive applications.
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13 Package outline
DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package;
no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm
SOT815-1
D
B
A
A
A
E
1
c
detail X
terminal 1
index area
C
e
1
terminal 1
index area
y
y
v
M
C
C
A B
C
1
e
b
w
M
2
11
L
12
13
1
e
E
h
2
24
23
14
X
D
h
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
D
D
E
E
h
e
e
e
L
v
w
y
y
1
1
2
1
h
max.
0.05 0.30
0.00 0.18
5.6
5.4
4.25
3.95
3.6
3.4
2.25
1.95
0.5
0.3
mm
1
0.2
0.5
4.5
1.5
0.1
0.05 0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
03-04-29
SOT815-1
- - -
- - -
- - -
Figure 8.ꢀPackage outline DHVQFN24
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14 Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate precautions are taken as
described in JESD625-A or equivalent standards.
15 Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
15.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached
to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides
both the mechanical and the electrical connection. There is no single soldering method
that is ideal for all IC packages. Wave soldering is often preferred when through-hole
and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is
not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
15.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming
from a standing wave of liquid solder. The wave soldering process is suitable for the
following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
15.3 Wave soldering
Key characteristics in wave soldering are:
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TJA1124
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• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
15.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 9) than a SnPb process, thus reducing
the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board
is heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder
paste characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with Table 8
and Table 9.
Table 8.ꢀSnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
235
350
220
220
< 2.5
2.5
220
Table 9.ꢀLead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
>2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 9.
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maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Figure 9.ꢀTemperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
16 Soldering of DHVQFN packages
Section 15 contains a brief introduction to the techniques most commonly used to solder
Surface Mounted Devices (SMD). A more detailed discussion on soldering HVSON
leadless package ICs can be found in the following application notes:
• AN10365 “Surface mount reflow soldering description”
• AN10366 “HVQFN application information”
17 Revision history
Table 10.ꢀRevision history
Document ID
Release date
Data sheet status Change notice Supersedes
TJA1124 v.1
20180508
Product data sheet
-
-
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18 Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Product [short] data sheet
Qualification
Production
This document contains data from the preliminary specification.
This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes
18.2 Definitions
no representation or warranty that such applications will be suitable
for the specified use without further testing or modification. Customers
Draft — The document is a draft version only. The content is still under
are responsible for the design and operation of their applications and
internal review and subject to formal approval, which may result in
products using NXP Semiconductors products, and NXP Semiconductors
modifications or additions. NXP Semiconductors does not give any
accepts no liability for any assistance with applications or customer product
representations or warranties as to the accuracy or completeness of
design. It is customer’s sole responsibility to determine whether the NXP
information included herein and shall have no liability for the consequences
Semiconductors product is suitable and fit for the customer’s applications
of use of such information.
and products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
Short data sheet — A short data sheet is an extract from a full data sheet
design and operating safeguards to minimize the risks associated with
with the same product type number(s) and title. A short data sheet is
their applications and products. NXP Semiconductors does not accept any
intended for quick reference only and should not be relied upon to contain
liability related to any default, damage, costs or problem which is based
detailed and full information. For detailed and full information see the
on any weakness or default in the customer’s applications or products, or
relevant full data sheet, which is available on request via the local NXP
the application or use by customer’s third party customer(s). Customer is
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
responsible for doing all necessary testing for the customer’s applications
and products using NXP Semiconductors products in order to avoid a
default of the applications and the products or of the application or use by
customer’s third party customer(s). NXP does not accept any liability in this
respect.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
Limiting values — Stress above one or more limiting values (as defined in
shall an agreement be valid in which the NXP Semiconductors product
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
is deemed to offer functions and qualities beyond those described in the
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
Product data sheet.
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
18.3 Disclaimers
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed
Terms and conditions of commercial sale — NXP Semiconductors
to be accurate and reliable. However, NXP Semiconductors does not
products are sold subject to the general terms and conditions of commercial
give any representations or warranties, expressed or implied, as to the
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
accuracy or completeness of such information and shall have no liability
agreed in a valid written individual agreement. In case an individual
for the consequences of use of such information. NXP Semiconductors
agreement is concluded only the terms and conditions of the respective
takes no responsibility for the content in this document if provided by an
agreement shall apply. NXP Semiconductors hereby expressly objects to
information source outside of NXP Semiconductors. In no event shall NXP
applying the customer’s general terms and conditions with regard to the
Semiconductors be liable for any indirect, incidental, punitive, special or
purchase of NXP Semiconductors products by customer.
consequential damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the removal or replacement
of any products or rework charges) whether or not such damages are based
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
on tort (including negligence), warranty, breach of contract or any other
the grant, conveyance or implication of any license under any copyrights,
legal theory. Notwithstanding any damages that customer might incur for
patents or other industrial or intellectual property rights.
any reason whatsoever, NXP Semiconductors’ aggregate and cumulative
liability towards customer for the products described herein shall be limited
in accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
malfunction of an NXP Semiconductors product can reasonably be expected
limitation specifications and product descriptions, at any time and without
to result in personal injury, death or severe property or environmental
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
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TJA1124
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applications and therefore such inclusion and/or use is at the customer's own
risk.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
18.4 Trademarks
Notice: All referenced brands, product names, service names and
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
trademarks are the property of their respective owners.
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Contents
1
General description ............................................ 1
2
Features and benefits .........................................1
General .............................................................. 1
Protection ...........................................................1
Ordering information .......................................... 2
Block diagram ..................................................... 2
Pinning information ............................................ 3
Pinning ...............................................................3
Pin description ...................................................3
Functional description ........................................5
LIN 2.x/SAE J2602 compliance .........................5
Operating modes ............................................... 5
Off mode ............................................................6
Low Power mode ...............................................6
Standby mode ................................................... 6
Normal mode .....................................................6
VIO UV mode .................................................... 7
Overtemp mode .................................................7
Device wake-up .................................................7
Remote wake-up via the LIN bus ...................... 7
Local wake-up via pin SLP ................................8
Operation during automotive cranking
2.1
2.2
3
4
5
5.1
5.2
6
6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.3
6.3.1
6.3.2
6.4
pulses .................................................................8
Operation when supply voltage is outside
6.5
specified operating range .................................. 8
TXD dominant time-out function ........................ 8
LIN dominant timeout function ...........................9
LIN master pull-up .............................................9
Fail-safe features ...............................................9
Limiting values ....................................................9
Thermal characteristics ....................................10
Static characteristics ........................................10
Dynamic characteristics ...................................13
Application information ....................................15
Application diagram ......................................... 15
ESD robustness according to LIN EMC test
6.6
6.7
6.8
6.9
7
8
9
10
11
11.1
11.2
specification ..................................................... 16
Test information ................................................16
Quality information ...........................................16
Package outline .................................................17
Handling information ........................................18
Soldering of SMD packages .............................18
Introduction to soldering .................................. 18
Wave and reflow soldering .............................. 18
Wave soldering ................................................18
Reflow soldering .............................................. 19
Soldering of DHVQFN packages ......................20
Revision history ................................................ 20
Legal information ..............................................21
12
12.1
13
14
15
15.1
15.2
15.3
15.4
16
17
18
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© NXP B.V. 2018.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 8 May 2018
Document identifier: TJA1124
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