TJA1443_技术文档

TJA1443

High-speed CAN transceiver with Sleep mode

Rev. 1 — 12 August 2020

Product data sheet

1 General description

The TJA1443 is a member of the TJA144x family of transceivers that provide an interface

between a Controller Area Network (CAN) or CAN FD (Flexible Data rate) protocol

controller and the physical two-wire CAN bus. TJA144x transceivers implement the CAN

physical layer as defined in ISO 11898-2:2016 and SAE J2284-1 to SAE J2284-5, and

are fully interoperable with high-speed Classical CAN and CAN FD transceivers. All

TJA144x variants enable reliable communication in the CAN FD fast phase at data rates

up to 5 Mbit/s.

The TJA1443 is intended as a simple replacement for high-speed Classical CAN and

CAN FD transceivers, such as the TJA1043 from NXP. It offers pin compatibility and is

designed to avoid changes to hardware and software design, allowing the TJA1443 to be

easily retrofitted to existing applications.

An AEC-Q100 Grade 0 variant, the TJR1443, is available for high temperature

applications, supporting operation at 150 °C ambient temperature.

2 Features and benefits

2.1 General

• ISO 11898-2:2016, SAE J2284-1 to SAE J2284-5 and SAE J1939-14 compliant

• Standard CAN and CAN FD data bit rates up to 5 Mbit/s

• Low Electromagnetic Emission (EME) and high Electromagnetic Immunity (EMI)

• Qualified according to AEC-Q100 Grade 1

• VIO input for interfacing with 3.3 V to 5 V microcontrollers

• Listen-only mode for node diagnosis and failure containment

• Available in SO14 and leadless HVSON14 (3.0 mm x 4.5 mm) packages; HVSON14

with improved Automated Optical Inspection (AOI) capability.

• Dark green product (halogen free and Restriction of Hazardous Substances (RoHS)

compliant)

2.2 Predictable and fail-safe behavior

• Undervoltage detection with defined handling on all supply pins

• Full functionality guaranteed from the undervoltage detection thresholds up to the

maximum limiting voltage values

• Defined behavior below the undervoltage detection thresholds

• Transceiver disengages from the bus (high-ohmic) when the battery voltage drops

below the Off mode threshold

• Internal biasing of TXD and mode selection input pins, to enable defined fail-safe

behavior

NXP Semiconductors

TJA1443

High-speed CAN transceiver with Sleep mode

2.3 Low-power management

• Very low-current Standby and Sleep modes, with host, local and bus wake-up

capability

• Entire node with TJA1443 can be powered down while still supporting local, bus and

host wake-up

• CAN wake-up receiver powered by V_BATallowing V_IOand V_CCto be shut down

• CAN wake-up pattern filter time of 0.5 μs to 1.8 μs, meeting Classical CAN and CAN

FD requirements

2.4 Diagnosis & Protection

• Overtemperature diagnosis

• Transmit Data (TXD) dominant time-out and TXD-to-RXD short-circuit handler with

diagnosis

• Bus dominant clamping diagnosis

• Cold start diagnosis (first battery connection)

• High ESD handling capability on the bus pins (8 kV IEC and HBM)

• Bus pins and VBAT protected against transients in automotive environments

• Thermally protected

TJA1443

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Product data sheet

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NXP Semiconductors

TJA1443

High-speed CAN transceiver with Sleep mode

3 Quick reference data

Table 1.ꢀQuick reference data

Symbol

V_BAT

Parameter

Conditions

Min

Typ

-

Max

28

Unit

V

battery supply voltage

battery supply current

4.5

I_BAT

Normal or Listen-only mode

Standby or Sleep mode

-

80

13

-

300

20

µA

V

-

V_uvd(VBAT)

undervoltage detection voltage

on pin VBAT

4

4.5

V_CC

I_CC

supply voltage

supply current

4.5

-

5.5

60

7

V

Normal mode, dominant

Normal mode, recessive

Listen-only mode

-

38

4

3

-

mA

μA

V

-

5

Standby or Sleep mode

-

2

V_uvd(VCC)

undervoltage detection voltage V_BAT> 4.5 V

on pin VCC

4

-

4.5

V_uvhys(VCC)

undervoltage hysteresis

voltage on pin VCC

50

-

mV

V_IO

I_IO

supply voltage on pin VIO

2.95

-

5.5

250

2

V

supply current on pin VIO

Normal mode, dominant; V_TXD= 0 V

-

90

-

µA

Normal mode, recessive; all other

modes; V_TXD= V_IO

V_uvd(VIO)

undervoltage detection voltage V_BAT> 4.5 V

on pin VIO

2.65

50

-

2.95

-

V

V_uvhys(VIO)

undervoltage hysteresis

voltage on pin VIO

mV

V_ESD

V_CANH

V_CANL

T_vj

electrostatic discharge voltage IEC 61000-4-2 on pins CANH and CANL -8

-

+8

kV

V

voltage on pin CANH

voltage on pin CANL

limiting value according to IEC 60134

-36

-40

+40

+150

V

virtual junction temperature

°C

4 Ordering information

Table 2.ꢀOrdering information

Type number

Package

Name

Description

Version

TJA1443AT

SO14

plastic small outline package; 14 leads; body width 3.9 mm

SOT108-1

TJA1443ATK

HVSON14

plastic thermal enhanced very thin small outline package; no

leads; 14 terminals; body 3 × 4.5 × 0.85 mm

SOT1086-2

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TJA1443

High-speed CAN transceiver with Sleep mode

5 Block diagram

VIO

5

VCC

3

VBAT

10

TEMPERATURE

PROTECTION

V

IO

13

CANH

TRANSMITTER

1

12

TXD

TIME-OUT

CANL

V

BAT

5 V

9

WAKE

MODE

CONTROL

AND

V

BAT

IO

WAKE-UP

CONTROL

AND

LOCAL

FAILURE

DETECTION

8

ERR_N

STB_N

EN

7

INH

14

6

normal

receiver

V

IO

MUX

AND

DRIVER

low-power

receiver

4

RXD

WAKE-UP

FILTER

11

2

aaa-038098

n.c.

GND

Figure 1.ꢀTJA1443 block diagram

TJA1443

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TJA1443

High-speed CAN transceiver with Sleep mode

6 Pinning information

6.1 Pinning

terminal 1

index area

TXD

1

2

3

4

5

6

7

14 STB_N

13 CANH

12 CANL

11 n.c.

1

2

3

4

5

6

7

14

13

12

11

10

9

TXD

GND

VCC

RXD

VIO

STB_N

CANH

CANL

n.c.

GND

VCC

RXD

VIO

EN

10 VBAT

VBAT

WAKE

ERR_N

9

WAKE

EN

INH

8

ERR_N

8

INH

aaa-038083

Transparent top view

aaa-038082

TJA1443AT: SO14

Figure 2.ꢀPin configuration diagrams

TJA1443ATK: HVSON14

6.2 Pin description

Table 3.ꢀPin description

Symbol

1

Type^[1]Description

TXD

I

transmit data input; inputs data (from the CAN controller) to be written to the bus lines

ground

GND^[2]

VCC

2

G

P

O

P

I

3

5 V supply voltage input

RXD

4

receive data output; outputs data read from the bus lines (to the CAN controller)

supply voltage input for I/O level adapter

enable control input

VIO

5

EN

6

INH

7

AO

O

inhibit output for switching external voltage regulators

ERR_N

8

local failure detection; wake-up source recognition and power-on indication output

(active-LOW)

WAKE

VBAT

n.c.

9

AI

P

local wake-up input

10

11

12

13

14

battery supply voltage input

not connected

-

CANL

CANH

STB_N

AIO

I

LOW-level CAN bus line

HIGH-level CAN bus line

Standby mode control input (active-LOW)

[1] I: digital input; O: digital output; AI: analog input; AO: analog output; AIO: analog input/output; P: power supply; G: ground

[2] HVSON14 package die supply ground is connected to both the GND pin and the exposed center pad. The GND pin must be soldered to board ground.

For enhanced thermal and electrical performance, it is also recommended to solder the exposed center pad to board ground.

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Product data sheet

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TJA1443

High-speed CAN transceiver with Sleep mode

7 Functional description

7.1 Operating modes

The TJA1443 contains two independent state machines, a system state machine and

a CAN state machine. Two state machines are needed to secure flag handling during

undervoltage conditions. These state machines support a number of interdependent

operating modes. The system state machine controls the CAN state machine, but both

state machines are independently affected by the V_CCundervoltage status. For both

state machines, undervoltage detection is defined as V_x< V_uvd(x)for t > t_det(uv)and

undervoltage recovery is defined as V_x> V_uvd(x)for t > t_rec(uv)

.

7.1.1 System operating modes

The system state machine in the TJA1443 supports five system operating modes.

Control pins STB_N and EN are used to select the operating mode. Figure 3 describes

how to switch between operating modes. Mode changes are completed after transition

time t_t(moch). Fail-safe diagnostic information, as described in Section 7.2, is available on

pin ERR_N with a delay of t_{d(moch-ERR_N)}after a mode change.

from any mode when

V

< V for t > t

uvd(VBAT) det(uv)BAT

BAT

Off

(INH = high-

ohmic)

from Standby, Normal or

Listen-only when

V

> V for t > t

uvd(VBAT) startup

BAT

V

< V for

uvd(VCC)

STB_N = HIGH AND EN = HIGH AND

> V for t > t

CC

t > t

V

det(uv)long

IO

uvd(VIO)

rec(uv)VIO

Wake flag set

OR (rising edge on STB_N AND V > V

for t > t

)

rec(uv)VIO

IO uvd(VIO)

OR [V

> V

uvd(VCC)

for t > t

AND

CC

rec(uv)VCC

NOT(STB_N = LOW AND EN = HIGH) AND

> V for t > t

V

]

rec(uv)VIO

IO

uvd(VIO)

Sleep

(INH = high-

ohmic)

Standby

(INH = HIGH)

Normal

(INH = HIGH)

STB_N = LOW OR

< V for t > t

det(uv)VIO

V

IO

uvd(VIO)

(STB_N = LOW AND EN = HIGH for t > t

AND

h(gotosleep)

for t > t

Wake flag not set AND V > V

)

IO uvd(VIO)

rec(uv)VIO

OR V < V

IO uvd(VIO)

for t > t

det(uv)long

STB_N = HIGH AND EN = HIGH AND

> V for t > t

V

IO

uvd(VIO)

rec(uv)VIO

STB_N = HIGH AND EN = LOW AND

V

> V

for t > t

uvd(VIO) rec(uv)VIO

IO

STB_N = LOW OR

< V for t > t

det(uv)VIO

STB_N = HIGH AND EN = LOW AND

V

IO

uvd(VIO)

V

> V for t > t

uvd(VIO) rec(uv)VIO

IO

Listen-only

(INH = HIGH)

aaa-037553

Figure 3.ꢀTJA1443 system state diagram

7.1.1.1 Off mode

The TJA1443 switches to Off mode from any mode mode when the battery voltage falls

below the undervoltage detection threshold, V_uvd(VBAT). The device starts up in Off mode

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TJA1443

High-speed CAN transceiver with Sleep mode

when the battery is connected for the first time (cold start). Pins INH and ERR_N are in a

high-ohmic state in Off mode.

7.1.1.2 Standby mode

Standby mode is the first-level power-saving mode of the TJA1443. When V_BATrises

above the undervoltage detection threshold, V_uvd(VBAT), the TJA1443 starts to boot up,

triggering an initialization procedure. It switches to Standby mode after t_startup, resulting in

a HIGH level on pin INH.

When V_IOrises above the undervoltage detection threshold, V_uvd(VIO), the TJA1443

switches to Normal mode if pins STB_N and EN are HIGH, and to Listen-only mode if

STBN_N is HIGH and EN is LOW. It will remain in Standby mode if STBN_N is LOW.

The TJA1443 will switch to Sleep mode if V_IOremains below V_uvd(VIO)for t_det(uv)longand/or

V_CCremains below V_uvd(VCC)for t_det(uv)long. A transition from Standby mode to Sleep

mode can also be triggered by holding STB_N LOW and EN HIGH for t_h(gotosleep)(also

known as a 'go-to-sleep' command). This 'go-to-sleep' command is overruled if the Wake

flag is set, in which case the device remains in Standby mode.

7.1.1.3 Normal mode

HIGH levels on pin STB_N and pin EN selects Normal mode, provided the battery

supply voltage, V_BAT, and V_IOare present. Pin INH remains HIGH, so voltage regulators

controlled by pin INH will also be active (see Figure 10).

7.1.1.4 Listen-only mode

A HIGH level on pin STB_N and a LOW level on pin EN selects Listen-only mode,

provided V_BATand V_IOare present. Pin INH remains HIGH, so voltage regulators

controlled by pin INH will also be active.

In Listen-only mode the receiver is enabled, but the transmitter is disabled.

7.1.1.5 Sleep mode

Sleep mode is the second-level power-saving mode of the TJA1443. Sleep mode is

entered in a number of ways:

• via Standby mode, in response to a 'go-to-sleep' command

• via Standby mode as a result of a V_IOundervoltage longer than t_det(uv)long

• via all other modes, except Off mode, as a result of a V_CCundervoltage longer than

t_det(uv)long

In Sleep mode, the transceiver behaves as described for Standby mode, with the

exception that pin INH is set high-ohmic. Voltage regulators controlled by this pin are

switched off and the current into pin VBAT is reduced to a minimum.

A number of events will cause the TJA1443 to exit Sleep mode, switching to Standby

mode:

• setting the Wake flag

• a rising edge on pin STB_N (if V_IO> V_uvd(VIO)

)

• V_CC> V_uvd(VCC), V_IO> V_uvd(VIO)and the ‘go-to-sleep’ command has not been activated.

After entering Standby mode, the TJA1443 will enter Normal or Listen-Only if STB_N is

HIGH.

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TJA1443

High-speed CAN transceiver with Sleep mode

7.1.1.6 System operating modes and gap-free operation

Gap-free operation guarantees defined behavior at all voltage levels. Supply voltage-to-

operating mode mapping is detailed in Figure 4.

[1][2]

V

> 4.5 V

BAT

[2]

[3][4]

5.5 - 6 V

Fully functional

[3]

Fully functional AND

V

CC

operating range

(4.5 - 5.5 V)

characteristics

[5]

guaranteed

[3]

[6]

Fully functional OR Standby OR Sleep

[7]

V

range

uvd(vcc)

-0.3 V - 4 V

Sleep

Voltage range on VIO

[1] V

operating range is 4.5 V - 28 V and the undervoltage detection threshold range, V

, is 4 V - 4.5 V. For V

uvd(BAT)

< 4 V, the device

BAT

is in Off state. For 4 V ≤ V

≤ 4.5 V the device is either in Off state (if a V

undervoltage has been triggered) or in the state as shown in

< 40 V this diagram applies, with the single exception that the

BAT

this diagram (if a V

undervoltage has not been triggered). For 28 V < V

BAT

datasheet characteristics are not guaranteed.

[2]

6 V is the IEC 60134 Absolute Maximum Rating (AMR) for VCC and VIO, 40 V the AMR for VBAT (see Limiting values table). Above the AMR,

irreversible changes in characteristics, functionality or performance may occur. Returning from above AMR to the operating range, datasheet

characteristics and functionality cannot be guaranteed.

[3]

[4]

Target transceiver functionality as described in the datasheet is applicable.

Prolonged operation of the device outside the operating range may impact reliability over lifetime. Returning to the operating range, datasheet

characteristics are guaranteed provided the AMR has not been exceeded.

[5]

[6]

Datasheet characteristics are guaranteed within the V

characteristics tables.

, V

and V operating ranges. Exceptions are described in the Static and Dynamic

BAT CC IO

For a given value of V

and V , a specific device will be in a single defined state, determined by its undervoltage detection thresholds

CC

IO

V

and V

. The actual thresholds can vary between devices (within the ranges specified in this datasheet). To guarantee the

uvd(VIO)

uvd(VCC)

device will be in a specific state, V

undervoltage detection ranges.

and V must be either above the maximum or below the minimum thresholds specified for these

IO

CC

[7]

The device is fully functional when both V

and V are above the undervoltage threshold. If V or V is below the undervoltage threshold,

CC IO

CC

IO

the device will be in Standby or Sleep mode.

aaa-037492

Figure 4.ꢀTJA1443 supply voltage ranges and gap-free operation

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TJA1443

High-speed CAN transceiver with Sleep mode

7.1.2 CAN operating modes

The CAN state machine supports six operating modes.

from any mode

Off

CAN Off

(CAN Bias =

high-ohmic)

Standby OR Sleep

(Standby OR Sleep) AND

Wake flag set

CAN Offline

(CAN Bias =

0 V)

(Standby OR Sleep) AND

Wake flag not set

Standby OR

Sleep

Normal OR

Listen-only

Standby OR

Sleep

Standby OR

Sleep

CAN

CAN Wake

(CAN Bias =

0 V)

Pass-through

(CAN Bias =

0 V)

Normal AND

Listen-only AND

for t > t

V

> V

for t > t

CC

uvd(VCC) rec(uv)VCC

V

> V

uvd(VCC)

CC

rec(uv)VCC

V

)

< V for t > t

uvd(VCC) det(uv)VCC

CC

Normal AND

for t > t

V

> V

uvd(VCC)

V

< V

for t > t

CC

rec(uv)VCC

CC

uvd(VCC)

det(uv)VCC

Listen-only AND

V

> V

for t > t

CC

uvd(VCC) rec(uv)VCC

CAN Active

(CAN Bias =

CAN Listen-only

(CAN Bias =

V

/2)

CC

V

/2)

CC

Normal AND

for t > t

V

> V

uvd(VCC)

rec(uv)VCC

Listen-only AND

for t > t

V

> V

uvd(VCC)

CC

rec(uv)VCC

aaa-037828

Figure 5.ꢀTJA1443 CAN state diagram

7.1.2.1 CAN Off mode

When the TJA1443 system state machine is in Off mode, the CAN state machine will be

in CAN Off mode, with the bus pins and pin RXD in a high-ohmic state.

7.1.2.2 CAN Offline mode

When the TJA1443 system state machine is in Sleep or Standby mode and the Wake

flag has not been set, the CAN state machine will be in CAN Offline mode. The bus pins

are biased to ground.

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TJA1443

High-speed CAN transceiver with Sleep mode

The transceiver is unable to transmit or receive data and the low-power receiver is

activated to monitor the bus for a wake-up pattern. Pin RXD is HIGH.

7.1.2.3 CAN Wake mode

When the TJA1443 system state machine is in Sleep or Standby mode and the wake flag

has been set, the CAN state machine will be in CAN Wake mode. Pin RXD will be LOW,

reflecting the active wake-up request. The bus pins are biased to ground.

7.1.2.4 CAN Pass-through mode

When the TJA1443 system state machine is in Normal or Listen-only mode and V_CCis

below the undervoltage detection threshold, V_uvd(VCC), the CAN state machine will be in

CAN Pass-through mode.

The transceiver cannot transmit data via the bus lines in this mode. The output voltage

on the bus pins is biased to ground. Differential data on the bus pins is converted to

digital data via the low-power receiver and the results are output on pin RXD.

7.1.2.5 CAN Active mode

When the TJA1443 system state machine is in Normal mode and V_CCis above the

undervoltage detection threshold, V_uvd(VCC), the CAN state machine will be in CAN Active

mode. The transceiver can transmit and receive data via bus lines CANH and CANL. Pin

TXD must be HIGH at least once in CAN Active mode before the first transmission can

begin. The differential receiver converts the analog data on the bus lines into digital data

on pin RXD. In recessive state, the output voltage on the bus pins is V_CC/2.

7.1.2.6 CAN Listen-only mode

When the TJA1443 system state machine is in Listen-only mode and V_CCis above

the undervoltage detection threshold, V_uvd(VCC), the CAN state machine will be in CAN

Listen-only mode. The transmitter is disabled. The differential receiver converts the

analog data on the bus lines into digital data on pin RXD. As in CAN Active mode, the

bus pins are biased to V_CC/2.

7.2 Internal flags

The device makes use of four internal flags for fail-safe fallback control and system

diagnosis. These flags can be polled by the controller via pin ERR_N while V_IOis active.

Which flag is available on pin ERR_N at any time depends on the current system

operating mode; see Table 4.

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TJA1443

High-speed CAN transceiver with Sleep mode

Table 4.ꢀAccessing internal flags via pin ERR_N

Internal flag

Flag available on pin ERR_N^[1]Flag status: set^[2]

Flag status: not set^[2]

Flag cleared

Pwon

in Listen-only mode (coming from V_BAThas risen above

V_BAThas not risen above

V_uvd(VBAT)

on entering Normal mode

Standby or Sleep mode)

V_uvd(VBAT)

Wake

in Standby and Sleep modes

(provided V_IOand V_BATare

present)

remote or local wake-up

detected OR Pwon flag has

been set

no remote or local wake-up on entering Normal mode

detected

Wake-up source in Normal mode

local wake-up OR Pwon flag

has been set

remote wake-up OR no

wake-up

on leaving Normal mode

Local failure

in Listen-only mode (coming from on occurrence of:

none of the set conditions when Pwon flag is set or, provided all

Normal mode)

have been met

local failures have been resolved, when:

- TXD dominant failure OR

- TXD-RXD short circuit OR

- Bus dominant failure OR

- Overtemperature

- device enters Normal mode OR

- RXD dominant while TXD recessive OR

- bus dominant failure resolved AND no

other local failure has set the flag

[1] Pin ERR_N is an active-LOW output; a LOW level indicates a set flag and a HIGH level indicates the flag has not been set.

[2] Status since flag was last cleared.

7.2.1 Pwon flag

Pwon is the V_BATpower-on flag. This flag is set when the voltage on pin VBAT

recovers after previously dropping below V_uvd(VBAT)(usually because the battery was

disconnected). The Pwon flag can be used for cold start diagnosis. The Wake and

Wake-up source flags are set to ensure consistent system power-up under all supply

conditions. Coming from Sleep or Standby and entering Listen-Only mode, a LOW level

on pin ERR_N signals that the Pwon flag has been set. The flag is cleared when the

transceiver enters Normal mode.

7.2.2 Wake flag

The Wake flag is set when the transceiver detects a local or remote wake-up request.

7.2.2.1 Local wake-up

A local wake-up request is registered when the logic level on pin WAKE changes and the

new level remains stable for at least t_wake. The system state machine can set the Wake

flag in Standby or Sleep mode. Setting the Wake flag clears the timers. Once set, the

Wake flag status is immediately available on pins ERR_N and RXD (provided V_IOand

V_BATare present). This flag is also set at power-on and cleared when the transceiver

enters Normal mode.

7.2.2.2 Remote wake-up (via the CAN bus)

The TJA1443 wakes up from Sleep to Standby mode when a dedicated wake-up pattern

(specified in ISO 11898-2: 2016) is detected on the bus.

The wake-up pattern consists of:

• a dominant phase of at least t_wake(busdom)followed by

• a recessive phase of at least t_wake(busrec)followed by

• a dominant phase of at least t_wake(busdom)

Dominant or recessive bits between the above mentioned phases that are shorter than

t_wake(busdom)and t_wake(busrec)respectively are ignored.

The complete dominant-recessive-dominant pattern must be received within t_to(wake)busto

be recognized as a valid wake-up pattern (see Figure 6). Otherwise, the internal wake-

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TJA1443

High-speed CAN transceiver with Sleep mode

up logic is reset. The complete wake-up pattern then needs to be retransmitted to trigger

a wake-up event. Pins RXD and ERR_N remain HIGH until the wake-up event has been

triggered and then switch LOW after t_startup(RXD). Pin INH remains floating until the wake-

up event has been triggered and then switches HIGH after t_startup(INH)

.

A wake-up event is not flagged on RXD if any of the following events occurs while a valid

wake-up pattern is being received:

• The device switches to Normal mode

• The complete wake-up pattern was not received within t_to(wake)bus

• A V_CCor V_IOundervoltage is detected

CANH

CANL

V

O(dif)

t

wake(busdom)

wake(busrec)

wake-up

pattern detected

RXD

≤ t

t

startup(RXD)

to(wake)bus

INH

t

startup(INH)

aaa-038570

Figure 6.ꢀTJA1443 wake-up timing

7.2.3 Wake-up source flag

Wake-up source recognition is provided via the Wake-up source flag. It is set after the

Wake flag has been set by a local wake-up request via the WAKE pin. The Wake-up

source flag can be polled via the ERR_N pin in Normal mode (see Table 4). This flag is

also set at power-on and cleared when the transceiver leaves Normal mode.

7.2.4 Local failure flag

In Normal and Listen-only modes, the transceiver can distinguish four local failure events,

any of which will cause the Local failure flag to be set. The four local failure events are:

• TXD dominant failures

• TXD-to-RXD short circuit

• Bus dominant failures

• Overtemperature

The nature and detection of these local failures is described in Section 7.3. The Local

failure flag can be polled via the ERR_N pin in Listen-only mode, when coming from

Normal mode (see Table 4).

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High-speed CAN transceiver with Sleep mode

This flag is cleared at power-on when the Pwon flag is set or, provided all local failures

have been resolved, when:

• The device enters Normal mode OR

• RXD is dominant while TXD is recessive OR

• Bus dominant failure has been resolved AND no other local failure has set the flag

7.3 Local failure events

The TJA1443 can detect four different local failure conditions, any of which will set the

Local failure flag. In most cases, the transmitter is disabled.

7.3.1 TXD dominant failures

A hardware and/or software application failure that caused pin TXD to be held

LOW would drive the bus lines to a permanent dominant state (blocking all network

communications). The TXD dominant time-out function prevents such a network lock-up.

A 'TXD dominant time-out' timer is started when pin TXD goes LOW. If the LOW state on

this pin persists for longer than t_to(dom)TXD, the transmitter is disabled, releasing the bus

lines to recessive state. The transmitter remains disabled until the Local failure flag has

been cleared. The TXD dominant time-out timer is reset when pin TXD is set HIGH.

7.3.2 TXD-to-RXD short circuit

A short-circuit between pins RXD and TXD would lock the bus in a permanent dominant

state once it had been driven dominant, because the low-side driver of RXD is typically

stronger than the high-side driver of the controller connected to TXD. TXD-to-RXD

short-circuit detection prevents such a network lock-up by disabling the transmitter. The

transmitter remains disabled until the Local failure flag has been cleared.

7.3.3 Bus dominant failures

A CAN bus short circuit (to V_BAT, V_CCor GND) or a failure in one of the other network

nodes could result in a differential voltage on the bus high enough to represent a bus

dominant state. Because a node will not begin to transmit while the bus is dominant, the

host controller would not be able to detect this failure condition. However, bus dominant

clamping detection will detect the short circuit. The Local failure flag is set if the dominant

state on the bus persists for longer than t_to(dom)bus. By checking this flag, the controller

can determine if a clamped bus is blocking network communications. There is no need to

disable the transmitter. Note that the Local failure flag is reset as soon as the bus returns

to recessive state.

7.3.4 Overtemperature

The device is protected against overtemperature conditions. If the junction temperature

exceeds the shutdown junction temperature, T_j(sd), the CAN bus drivers are disabled. The

transmitter will remain disabled until the junction temperature drops below T_j(sd)reland the

Local failure flag has been cleared.

7.4 I/O levels

Pin VIO should be connected to the same supply voltage used to supply the

microcontroller. This adjusts the signal levels on pins TXD, RXD, STB_N, EN and

TJA1443

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NXP Semiconductors

TJA1443

High-speed CAN transceiver with Sleep mode

ERR_N to the I/O levels of the microcontroller, allowing for direct interfacing without

additional glue logic. Spurious signals from the microcontroller on pins STB_N and EN

are filtered out with a filter time of t_fltr(IO)

.

7.5 WAKE pin

A local wake-up event is triggered by a LOW-to-HIGH or HIGH-to-LOW transition on the

WAKE pin when V_WAKEpasses the wake-up threshold, V_th(wake). After the transition, the

new HIGH or LOW level should remain stable for at least t_wake. This allows for maximum

flexibility when designing a local wake-up circuit.

A local wake-up is guaranteed in the case of:

- a LOW-to-HIGH transition from V_WAKE< V_th(wake)minto V_WAKE> V_th(wake)max, followed

by V_WAKE> V_th(wake)maxfor t > t_wake(max)

- a HIGH-to-LOW transition from V_WAKE> V_th(wake)maxto V_WAKE< V_th(wake)min, followed

by V_WAKE< V_th(wake)minfor t > t_wake(max)

A local wake-up is guaranteed not to occur if the HIGH/LOW level after the transition

does not remain stable for at least t_(wake)min

.

To minimize current consumption, the internal bias voltage follows the logic state on the

pin after a delay of t_wake. A HIGH level on pin WAKE is followed by an internal pull-up

to V_BAT. A LOW level on pin WAKE is followed by an internal pull-down towards GND.

In applications that do not make use of the local wake-up facility, it is recommended to

connect the WAKE pin to pin VBAT or GND for optimal EMI performance.

7.6 Internal biasing of TXD, STB_N and EN input pins

Pin TXD has an internal pull-up to V_IOand pins STB_N and EN have internal pull-downs

to GND to ensure a safe, defined state in case one, or all, of these pins is left floating.

Pull-up/pull-down resistors are present on these pins in all states. Pull-down on pin EN is

only active when V_BATis present.

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TJA1443

High-speed CAN transceiver with Sleep mode

8 Limiting values

Table 5.ꢀLimiting values

In accordance with the Absolute Maximum Rating System (IEC 60134); all voltages are referenced to pin GND, unless

otherwise specified; positive currents flow into the IC.

Symbol

Parameter

Voltage on pin x^[1]

Conditions

Min Max

Unit

V

V_x

pins VCC, VIO, TXD, STB_N, EN

−0.3 +6

-

+7^[2]

V

pin VBAT, load dump

pin INH

−0.3 +40^[3]

−0.3 V_BAT+0.3^[4]

V

pins CANH, CANL, WAKE

pins RXD, ERR_N

−36 +40

−0.3 V_IO+0.3^[5]

V

I_O(INH)

output current on pin INH

-2

-

mA

V

V_(CANH-CANL)voltage between pin CANH

and pin CANL

−40 +40

[6]

V_trt

transient voltage

on pins CANH, CANL

pulse 1

-100

-

V

pulse 2a

-

+75

-

pulse 3a

-150

-

pulse 3b

+100

[7]

V_ESD

electrostatic discharge

voltage

IEC 61000-4-2 (150 pF, 330 Ω discharge circuit)

on pins CANH, CANL; pin VBAT with 100 nF

capacitor; pin WAKE with 33 kΩ resistor

-8

+8

kV

Human Body Model (HBM)

on any pin

[8]

[9]

-4

-8

+4

+8

kV

on pins CANH, CANL

Charged Device Model (CDM)

on corner pins

[10]

-750 +750

-500 +500

V

on any other pin

V

[11]

T_vj

virtual junction temperature

storage temperature

-40

-55

+150

°C

T_stg

[1] The device can sustain voltages up to the specified values over the product lifetime, provided applied voltages (including transients) never exceed these

values.

[2] The device can withstand voltages between 6 V and 7 V for a total of 20 s over the product lifetime.

[3] For a maximum of 400 ms over the product lifetime.

[4] Absolute maximum of 40 V for a maximum of 400 ms over the product lifetime.

[5] Subject to the qualifications detailed in Table notes 1 and 2 above for pins VCC, VIO, TXD, STB_N and EN.

[6] Verified by an external test house according to IEC TS 62228, Section 4.2.4; parameters for standard pulses defined in ISO7637.

[7] Verified by an external test house according to IEC TS 62228, Section 4.3.

[8] According to AEC-Q100-002.

[9] Pins stressed to reference group containing all ground and supply pins, emulating the application circuits (Figure 10). HBM pulse as specified in AEC-

Q100-002 used.

[10] According to AEC-Q100-011.

[11] In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: T_vj= T_amb+ P × R_th(j-a), where R_th(j-a)is a fixed value used in

the calculation of T_vj. The rating for T_vjlimits the allowable combinations of power dissipation (P) and ambient temperature (T_amb).

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High-speed CAN transceiver with Sleep mode

9 Thermal characteristics

Table 6.ꢀThermal characteristics

Value determined for free convection conditions on a JEDEC 2S2P board.

Symbol

Parameter

Conditions^[1]

SO14

Typ

83

54

21

19

11

Unit

K/W

R_th(j-a)

thermal resistance from junction to ambient

HVSON14

SO14

R_th(j-c)

Ѱ_j-top

thermal resistance from junction to case^[2]

thermal characterization parameter from junction to top of package

HVSON14

[1] According to JEDEC JESD51-2, JESD51-5 and JESD51-7 at natural convection on 2s2p board. Board with two inner copper layers (thickness: 35 μm)

and thermal via array under the exposed pad connected to the first inner copper layer (thickness: 70 μm).

[2] Case temperature refers to the center of the heatsink at the bottom of the package.

10 Static characteristics

Table 7.ꢀStatic characteristics

T_vj= -40 °C to +150 °C; V_CC= 4.5 V to 5.5 V; V_IO= 2.95 V to 5.5 V; V_BAT= 4.5 V to 28 V; R_L= 60 Ω unless specified

otherwise; all voltages are defined with respect to ground; positive currents flow into the IC.^[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Supply; pin VCC

V_CC

V_uvd

supply voltage

4.5

4

-

5.5

4.5

V

[2]

undervoltage detection

voltage

V_uvhys

I_CC

undervoltage hysteresis

voltage

50

-

mV

supply current

Normal mode

dominant; V_TXD= 0 V; t < t_to(dom)TXD

-

38

-

60

mA

dominant; V_TXD= 0 V;

125

short circuit on bus lines;

-3 V < (V_CANH= V_CANL) < +40 V

Normal mode, recessive; V_TXD= V_IO

Listen-only mode

-

4

3

-

7

5

2

mA

µA

Standby or Sleep mode; T_vj< 85 °C

I/O level adapter supply; pin VIO

V_IO

supply voltage

2.95

2.65

-

5.5

V

[2]

V_uvd

undervoltage detection

voltage

2.95

V_uvhys

I_IO

undervoltage hysteresis

voltage

50

-

mV

supply current

Normal mode, dominant; V_TXD= 0 V

-

90

-

250

2

µA

Normal mode, recessive, V_TXD= V_IOor

Listen-only mode

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TJA1443

High-speed CAN transceiver with Sleep mode

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Standby or Sleep mode; T_vj< 85 °C

-

2

µA

Supply; pin VBAT

V_BAT

V_uvd

battery supply voltage

4.5

4

-

28

V

[2]

undervoltage detection

voltage

4.5

I_BAT

battery supply current

Normal or Listen-only mode; pin INH left

open

-

80

13

300

100

20

µA

Normal or Listen-only mode; pin INH left

open; T_vj≤ 25 °C; V_BAT= 14.5 V

Standby mode; pin INH left open; V_WAKE

V_BAT; T_vj< 85 °C

=

Sleep mode; V_WAKE= V_BAT; T_vj< 85 °C

20

CAN transmit data input; pin TXD

V_IH

HIGH-level input voltage

LOW-level input voltage

0.7V_IO

-

V

V_IL

-

0.3V_IO

-

V

V_hys(TXD)

hysteresis voltage on pin

TXD

50

mV

R_pu

C_i

pull-up resistance

input capacitance

20

-

80

10

kΩ

pF

[3]

CAN receive data output; pin RXD

I_OH

I_OL

HIGH-level output current

LOW-level output current

V_RXD= V_IO- 0.4 V

V_RXD= 0.4 V

-10

1

-

-1

mA

10

Standby and enable control inputs; pins STB_N and EN

V_IH

V_IL

V_hys

R_pd

C_i

HIGH-level input voltage

LOW-level input voltage

hysteresis voltage

0.7V_IO

-

V

-

0.3V_IO

V

50

20

-

mV

kΩ

pF

[4]

[3]

pull-down resistance

input capacitance

80

10

Local failure detection and power-on indication output; pin ERR_N

I_OH

I_OL

HIGH-level output current

LOW-level output current

V_{ERR_N}= V_IO- 0.4 V

V_{ERR_N}= 0.4 V

-50

0.1

-

-4

2

µA

mA

Local wake-up input; pin WAKE

R_pu

pull-up resistance

V_WAKE> V_{th(wake)(max)}for t > t_wake(max)

V_WAKE< V_{th(wake)(min)}for t > t_wake(max)

Sleep or Standby mode

100

1.8

90

-

400

2.6

-

kΩ

V

R_pd

pull-down resistance

wake-up threshold voltage

hysteresis voltage

V_th(wake)

V_hys

mV

Inhibit output; pin INH

ΔV_H

HIGH-level voltage drop

ΔV_H= V_BAT- V_INH; I_INH= -1 mA

ΔV_H= V_BAT- V_INH; I_INH= -2 mA

0

-

1

2

V

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TJA1443

High-speed CAN transceiver with Sleep mode

Symbol

I_L

Parameter

Conditions

Min

-2

Typ

Max

+2

-

Unit

µA

leakage current

Sleep mode; Off mode

V_INH= 0 V

-

I_O(sc)

short-circuit output current

-15

mA

Bus lines; pins CANH and CANL

V_O(dom)

dominant output voltage

V_TXD= 0 V; t < t_to(dom)TXD; V_CC≥ 4.75 V

pin CANH; R_L= 50 Ω to 65 Ω

2.75

3.5

1.5

-

4.5

V

pin CANL; R_L= 50 Ω to 65 Ω

0.5

2.25

[3]

[5]

V_TXsym

transmitter voltage

symmetry

V_TXsym= V_CANH+ V_CANL; C_SPLIT= 4.7 nF;

f_TXD= 250 kHz, 1 MHz or 2.5 MHz

0.9V_CC

1.1V_CC

[3]

[5]

[6]

V_cm(step)

common mode voltage step

-150

-300

-

+150

+300

mV

[3]

[5]

[6]

V_cm(p-p)

peak-to-peak common mode

voltage

[5]

[3]

V_O(dif)

differential output voltage

dominant; Normal mode; V_TXD= 0 V;

t < t_to(dom)TXD; V_CC≥ 4.75 V

R_L= 50 Ω to 65 Ω

R_L= 45 Ω to 70 Ω

1.5

1.4

1.5

-

3

V

3.3

5

R_L= 2240 Ω

recessive; no load

Normal or Listen-only mode; V_TXD= V_IO

Standby or Sleep mode

-50

-0.2

2

-

+50

+0.2

3

mV

V

-

V_O(rec)

recessive output voltage

Normal or Listen-only mode; V_TXD= V_IO;

no load

2.5

V

Standby or Sleep mode; no load

-0.1

0

+0.1

V

V_th(RX)dif

differential receiver

threshold voltage

-12 V ≤ V_CANH≤ +12 V;

-12 V ≤ V_CANL≤ +12 V

Normal or Listen-only mode

Standby or Sleep mode

0.5

0.4

-

0.9

1.1

V

V_rec(RX)

receiver recessive voltage

receiver dominant voltage

-12 V ≤ V_CANH≤ +12 V;

-12 V ≤ V_CANL≤ +12 V

Normal or Listen-only mode

Standby or Sleep mode

-4

-

+0.5

+0.4

V

V_dom(RX)

-12 V ≤ V_CANH≤ +12 V;

-12 V ≤ V_CANL≤ +12 V

Normal or Listen-only mode

Standby or Sleep mode

0.9

1.1

50

-

9

-

V

V_hys(RX)difdifferential receiver

hysteresis voltage

-12 V ≤ V_CANH≤ +12 V;

-12 V ≤ V_CANL≤ +12 V; Normal or Listen-

only mode

mV

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TJA1443

High-speed CAN transceiver with Sleep mode

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

I_O(sc)

short-circuit output current

-15 V ≤ V_CANH≤ +40 V;

-15 V ≤ V_CANL≤ +40 V

-

115

mA

I_O(sc)rec

recessive short-circuit output -27 V ≤ V_CANH≤ +32 V;

-3

-

+3

mA

µA

current

-27 V ≤ V_CANL≤ +32 V; Normal or Listen-

only mode; V_TXD= V_IO

I_L

leakage current

V_CC= V_IO= 0 V or pins shorted to GND via

47 KΩ; V_CANH= V_CANL= 5 V;

-10

+10

R_i

input resistance

-2 V ≤ V_CANL≤ +7 V; -2 V ≤ V_CANH≤ +7 V

0 V ≤ V_CANL≤ +5 V; 0 V ≤ V_CANH≤ +5 V

25

-3

50

-

40

-

50

kΩ

%

ΔR_i

input resistance deviation

+3

R_i(dif)

C_i(cm)

differential input resistance -2 V ≤ V_CANL≤ +7 V; -2 V ≤ V_CANH≤ +7 V

80

-

100

20

kΩ

pF

[3]

common-mode input

capacitance

C_i(dif)

differential input capacitance

-

10

pF

Temperature detection

[3]

T_j(sd)

shutdown junction

temperature

180

175

-

200

195

°C

T_j(sd)rel

release shutdown junction

temperature

[1] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to cover the specified

temperature and power supply voltage range.

[2] Undervoltage is detected between min and max values. Undervoltage is guaranteed to be detected below min value and guaranteed not to be detected

above max value.

[3] Not tested in production; guaranteed by design.

[4] Pull-down on EN pin is only active when V_BATis present.

[5] The test circuit used to measure the bus output voltage symmetry and the common-mode voltages (which includes C_SPLIT) is shown in Figure 12.

[6] See Figure 9.

11 Dynamic characteristics

Table 8.ꢀDynamic characteristics

T_vj= -40 °C to +150 °C; V_CC= 4.5 V to 5.5 V; V_IO= 2.95 V to 5.5 V; V_BAT= 4.5 V to 28 V; R_L= 60 Ω unless specified

otherwise; all voltages are defined with respect to ground.^[1]

Symbol

Parameter

Conditions

Min

Typ

Max Unit

CAN timing characteristics; t_bit(TXD)≥ 200 ns; see Figure 7, Figure 8 and Figure 11

t_{d(TXD-busdom)}delay time from TXD to bus dominant

t_{d(TXD-busrec)}delay time from TXD to bus recessive

t_{d(busdom-RXD)}delay time from bus dominant to RXD

t_{d(busrec-RXD)}delay time from bus recessive to RXD

Normal mode

-

102.5 ns

127.5 ns

Normal mode

Normal or Listen-Only mode

t_d(TXDL-RXDL)delay time from TXD LOW to RXD LOW Normal mode

t_d(TXDH-RXDH)delay time from TXD HIGH to RXD HIGH Normal mode

CAN FD timing characteristics according to ISO 11898-2:2016; see Figure 8 and Figure 11

230

ns

t_bit(bus)

transmitted recessive bit width

t_bit(TXD)= 500 ns

t_bit(TXD)= 200 ns

t_bit(TXD)= 500 ns

435

155

-65

-

530

210

+40

ns

Δt_rec

receiver timing symmetry

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TJA1443

High-speed CAN transceiver with Sleep mode

Symbol

Parameter

Conditions

Min

-45

Typ

Max Unit

t_bit(TXD)= 200 ns

t_bit(TXD)= 500 ns

t_bit(TXD)= 200 ns

-

+15

550

220

ns

t_bit(RXD)

bit time on pin RXD

400

120

Dominant time-out times

t_to(dom)TXDTXD dominant time-out time

[2]

[3]

V_TXD= 0 V; Normal mode

0.8

-

9

ms

[2]

[3]

t_to(dom)bus

bus dominant time-out time

V_O(dif)> 0.9 V; Normal or Listen-

Only mode

Bus wake-up times; pins CANH and CANL; see Figure 6

t_wake(busdom)bus dominant wake-up time

[2]

[4]

Standby or Sleep mode

0.5

0.8

-

1.8

9

µs

ms

[2]

[4]

t_wake(busrec)

t_to(wake)bus

Mode transitions

bus recessive wake-up time

[2]

[3]

bus wake-up time-out time

[2]

t_t(moch)

mode change transition time

-

50

1

µs

ms

µs

t_startup

start-up time

-

[2]

[5]

t_startup(RXD)

RXD start-up time

after remote wake-up detected;

Standby or Sleep mode

4

20

[2]

[6]

t_startup(INH)

t_h(gotosleep)

INH start-up time

after remote wake-up detected;

Standby or Sleep mode

4

-

50

µs

[2]

[7]

go-to-sleep hold time

STB_N = LOW and EN = HIGH

hold time for entering Sleep

mode

24

[2]

t_{d(moch-ERR_N)}delay time from mode change to ERR_N to ERR_N stable after mode

transition

-

20

50

µs

Local wake-up input; pin WAKE

t_wake

wake-up time

in response to a falling or rising

edge on pin WAKE; Standby or

Sleep mode

20

IO filter; pins STB_N, EN

t_fltr(IO)I/O filter time

Undervoltage detection; see Figure 3 and Figure 5

[8]

1

-

5

µs

[2]

t_det(uv)

undervoltage detection time

on pin VBAT

-

30

µs

ms

on pin VCC

-

30

on pin VIO

-

30

[2]

[9]

t_det(uv)long

t_rec(uv)

long undervoltage detection time

undervoltage recovery time

on pins VCC and/or VIO

100

150

[2]

on pin VCC

on pin VIO

-

50

µs

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[1] All parameters are guaranteed over the junction temperature range by design. Factory testing uses correlated test conditions to cover the specified

temperature and power supply voltage range.

[2] Not tested in production; guaranteed by design.

[3] Time-out occurs between the min and max values. Time-out is guaranteed not to occur below the min value; time-out is guaranteed to occur above the

max value.

[4] A dominant/recessive phase shorter than the min value is guaranteed not be seen as a dominant/recessive bit; a dominant/recessive phase longer than

the max value is guaranteed to be seen as a dominant/recessive bit.

[5] When a wake-up is detected, RXD start-up time is between the min and max values. RXD cannot be relied on below the min value; RXD can be relied on

above the max value; see Figure 6.

[6] INH switches HIGH between the min and max values after a wake-up had been detected. INH is guaranteed to be floating below the min value and

guaranteed to be HIGH above the max value; see Figure 6.

[7] The device is guaranteed to switch to Sleep mode when STB_N = LOW and EN = HIGH for longer than max value, and guaranteed not to switch to Sleep

mode when less than the min value.

[8] Pulses shorter than the min value are guaranteed to be filtered out; pulses longer than the max value are guaranteed to be processed.

[9] An undervoltage longer than the max value is guaranteed to force a transition to Sleep mode; an undervoltage shorter than the min value is guaranteed

not to force a transition to Sleep mode.

HIGH

70 %

TXD

30 %

LOW

CANH

CANL

dominant

0.9 V

V

O(dif)

0.5 V

recessive

HIGH

70 %

RXD

30 %

LOW

t

d(TXD-busrec)

d(TXD-busdom)

t

d(busdom-RXD)

t

d(busrec-RXD)

aaa-029311

Figure 7.ꢀCAN transceiver timing diagram

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NXP Semiconductors

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High-speed CAN transceiver with Sleep mode

70 %

TXD

30 %

t

5 x t

bit(TXD)

d(TXDL-RXDL)

t

bit(TXD)

0.9 V

V

O(dif)

0.5 V

t

bit(bus)

70 %

RXD

30 %

t

d(TXDH-RXDH)

t

bit(RXD)

aaa-029312

Figure 8.ꢀCAN FD timing definitions according to ISO 11898-2:2016

CANH

CANL

V

cm(step)

V

CANH

+ V

CANL

V

cm(p-p)

aaa-037830

Figure 9.ꢀCAN bus common-mode voltage according to SAE 1939-14

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High-speed CAN transceiver with Sleep mode

12 Application information

12.1 Application diagram

BAT

3.3 V

(1)

on/off control

(1)

5 V

VBAT

INH

VCC

VIO

10

7

3

5

STB_N

EN

14

6

port w, x, y, z

WAKE

GND

9

ERR_N

8

MICRO-

CONTROLLER

RXD

TXD

4

1

2

13

CANH

12

CANL

CAN bus wires

aaa-038117

(1) Optional, depends on regulator.

Figure 10.ꢀTypical TJA1443 application with a 3.3 V microcontroller

12.2 Application hints

Further information on the application of the TJA1443 can be found in NXP application

hints AH2002 'TJx144x/TJx146x Application Hints', available on request from NXP

Semiconductors.

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13 Test information

TXD

RXD

CANH

CANL

R

60 Ω

C

L

100 pF

L

15 pF

aaa-030850

Figure 11.ꢀCAN transceiver timing test circuit

TXD

RXD

CANH

CANL

30 Ω

f

TXD

C

4.7 nF

SPLIT

aaa-030851

Figure 12.ꢀTest circuit for measuring transceiver driver symmetry

13.1 Quality information

This product has been qualified in accordance with the Automotive Electronics Council

(AEC) standard Q100 Rev-H - Failure mechanism based stress test qualification for

integrated circuits, and is suitable for use in automotive applications.

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14 Package outline

SO14: plastic small outline package; 14 leads; body width 3.9 mm

SOT108-1

D

E

A

X

v

c

y

H

M

A

E

Z

8

14

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

7

e

detail X

w

M

b

p

0

2.5

scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

8.75

8.55

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

mm

1.75

1.27

0.05

1.05

0.25

0.1

0.25

0.01

8^o

0^o

0.010 0.057

0.004 0.049

0.019 0.0100 0.35

0.014 0.0075 0.34

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.024

0.028

0.012

inches

0.041

0.01 0.01 0.004

0.069

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT108-1

076E06

MS-012

Figure 13.ꢀPackage outline SOT108-1 (SO14)

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High-speed CAN transceiver with Sleep mode

HVSON14: plastic, thermal enhanced very thin small outline package; no leads;

14 terminals; body 3 x 4.5 x 0.85 mm

SOT1086-2

X

B

A

E

D

A

1

c

terminal 1

index area

detail X

e

1

terminal 1

index area

C

v

w

C

A B

e

b

y

1

y

C

1

7

L

k

E

h

14

8

D

h

0

2.5

5 mm

w

scale

Dimensions

Unit

A

b

c

D

h

E

e

1

k

L

v

y

1

h

max 1.00 0.05 0.35

mm nom 0.85 0.03 0.32 0.2 4.5 4.20 3.0 1.60 0.65 3.9 0.30 0.40 0.1 0.05 0.05 0.1

min 0.80 0.00 0.29 4.4 4.15 2.9 1.55 0.25 0.35

4.6 4.25 3.1 1.65

0.35 0.45

sot1086-2

References

Outline

version

European

projection

Issue date

IEC

- - -

JEDEC

MO-229

JEITA

- - -

10-07-14

10-07-15

SOT1086-2

Figure 14.ꢀPackage outline SOT1086-2 (HVSON14)

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15 Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling ensure that the appropriate precautions are taken as

described in JESD625-A or equivalent standards.

16 Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

16.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached

to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides

both the mechanical and the electrical connection. There is no single soldering method

that is ideal for all IC packages. Wave soldering is often preferred when through-hole

and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is

not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

16.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming

from a standing wave of liquid solder. The wave soldering process is suitable for the

following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

16.3 Wave soldering

Key characteristics in wave soldering are:

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• Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath specifications, including temperature and impurities

16.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads

to higher minimum peak temperatures (see Figure 15) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reflow temperature profile; this profile includes preheat, reflow (in which the board

is heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder

paste characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with Table 9

and Table 10

Table 9.ꢀSnPb eutectic process (from J-STD-020D)

Package thickness (mm)

Package reflow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

< 2.5

≥ 2.5

220

Table 10.ꢀLead-free process (from J-STD-020D)

Package thickness (mm)

Package reflow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 15.

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High-speed CAN transceiver with Sleep mode

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Figure 15.ꢀTemperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

17 Soldering of HVSON packages

Section 16 contains a brief introduction to the techniques most commonly used to solder

Surface Mounted Devices (SMD). A more detailed discussion on soldering HVSON

leadless package ICs can be found in the following application note:

• AN10365 “Surface mount reflow soldering description”

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High-speed CAN transceiver with Sleep mode

18 Appendix: ISO 11898-2:2016 parameter cross-reference list

Table 11.ꢀISO 11898-2:2016 to NXP data sheet parameter conversion

ISO 11898-2:2016

NXP data sheet

Notation Symbol Parameter

Parameter

HS-PMA dominant output characteristics

Single ended voltage on CAN_H

Single ended voltage on CAN_L

Differential voltage on normal bus load

Differential voltage on effective resistance during arbitration

Optional: Differential voltage on extended bus load range

HS-PMA driver symmetry

V_{CAN_H}

V_{CAN_L}

V_Diff

V_O(dom)

dominant output voltage

differential output voltage

V_O(dif)

Driver symmetry

V_SYM

V_TXsym

transmitter voltage symmetry

short-circuit output current

Maximum HS-PMA driver output current

Absolute current on CAN_H

I_{CAN_H}

I_{CAN_L}

I_O(sc)

Absolute current on CAN_L

HS-PMA recessive output characteristics, bus biasing active/inactive

Single ended output voltage on CAN_H

Single ended output voltage on CAN_L

Differential output voltage

V_{CAN_H}

V_{CAN_L}

V_Diff

V_O(rec)

recessive output voltage

differential output voltage

TXD dominant time-out time

V_O(dif)

Optional HS-PMA transmit dominant time-out

Transmit dominant time-out, long

t_dom

t_to(dom)TXD

Transmit dominant time-out, short

HS-PMA static receiver input characteristics, bus biasing active/inactive

Recessive state differential input voltage range

Dominant state differential input voltage range

V_Diff

V_th(RX)dif

differential receiver threshold

voltage

V_rec(RX)

receiver recessive voltage

receiver dominant voltage

V_dom(RX)

HS-PMA receiver input resistance (matching)

Differential internal resistance

R_Diff

R_{CAN_H}

R_{CAN_L}

R_i(dif)

R_i

differential input resistance

input resistance

Single ended internal resistance

Matching of internal resistance

HS-PMA implementation loop delay requirement

Loop delay

MR

ΔR_i

input resistance deviation

t_Loop

t_d(TXDH-RXDH)delay time from TXD HIGH to

RXD HIGH

t_d(TXDL-RXDL)

delay time from TXD LOW to

RXD LOW

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High-speed CAN transceiver with Sleep mode

ISO 11898-2:2016

Parameter

NXP data sheet

Notation Symbol

Parameter

Optional HS-PMA implementation data signal timing requirements for use with bit rates above 1 Mbit/s up to 2

Mbit/s and above 2 Mbit/s up to 5 Mbit/s

Transmitted recessive bit width @ 2 Mbit/s / @ 5 Mbit/s,

intended

t_Bit(Bus)

t_bit(bus)

transmitted recessive bit width

Received recessive bit width @ 2 Mbit/s / @ 5 Mbit/s

Receiver timing symmetry @ 2 Mbit/s / @ 5 Mbit/s

HS-PMA maximum ratings of V_{CAN_H}, V_{CAN_L}and V_Diff

Maximum rating V_Diff

t_Bit(RXD)

Δt_Rec

t_bit(RXD)

Δt_rec

bit time on pin RXD

receiver timing symmetry

V_Diff

V_(CANH-CANL)voltage between pin CANH and

pin CANL

General maximum rating V_{CAN_H}and V_{CAN_L}

V_{CAN_H}

V_{CAN_L}

V_x

voltage on pin x

Optional: Extended maximum rating VCAN_H and VCAN_L

HS-PMA maximum leakage currents on CAN_H and CAN_L, unpowered

Leakage current on CAN_H, CAN_L

I_{CAN_H}

I_{CAN_L}

I_L

leakage current

HS-PMA bus biasing control timings

CAN activity filter time, long

CAN activity filter time, short

Wake-up time-out, short

[1]

t_Filter

t_wake(busdom)

t_wake(busrec)

bus dominant wake-up time

bus recessive wake-up time

t_Wake

t_to(wake)bus

bus wake-up time-out time

Wake-up time-out, long

[1] t_{fltr(wake)bus}- bus wake-up filter time, in devices with basic wake-up functionality

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High-speed CAN transceiver with Sleep mode

19 Legal information

19.1 Data sheet status

Document status^[1][2]

Product status^[3]

Definition

Objective [short] data sheet

Development

This document contains data from the objective specification for product

development.

Preliminary [short] data sheet

Product [short] data sheet

Qualification

Production

This document contains data from the preliminary specification.

This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple

devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

19.2 Definitions

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes

no representation or warranty that such applications will be suitable

for the specified use without further testing or modification. Customers

are responsible for the design and operation of their applications and

products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications

and products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with

their applications and products. NXP Semiconductors does not accept any

liability related to any default, damage, costs or problem which is based

on any weakness or default in the customer’s applications or products, or

the application or use by customer’s third party customer(s). Customer is

responsible for doing all necessary testing for the customer’s applications

and products using NXP Semiconductors products in order to avoid a

default of the applications and the products or of the application or use by

customer’s third party customer(s). NXP does not accept any liability in this

respect.

Draft — A draft status on a document indicates that the content is still

under internal review and subject to formal approval, which may result

in modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included in a draft version of a document and shall have no

liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the

relevant full data sheet, which is available on request via the local NXP

Semiconductors sales office. In case of any inconsistency or conflict with the

short data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product

is deemed to offer functions and qualities beyond those described in the

Product data sheet.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

19.3 Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, NXP Semiconductors does not

give any representations or warranties, expressed or implied, as to the

accuracy or completeness of such information and shall have no liability

for the consequences of use of such information. NXP Semiconductors

takes no responsibility for the content in this document if provided by an

information source outside of NXP Semiconductors. In no event shall NXP

Semiconductors be liable for any indirect, incidental, punitive, special or

consequential damages (including - without limitation - lost profits, lost

savings, business interruption, costs related to the removal or replacement

of any products or rework charges) whether or not such damages are based

on tort (including negligence), warranty, breach of contract or any other

legal theory. Notwithstanding any damages that customer might incur for

any reason whatsoever, NXP Semiconductors’ aggregate and cumulative

liability towards customer for the products described herein shall be limited

in accordance with the Terms and conditions of commercial sale of NXP

Semiconductors.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or

the grant, conveyance or implication of any license under any copyrights,

patents or other industrial or intellectual property rights.

Suitability for use in automotive applications — This NXP

Semiconductors product has been qualified for use in automotive

applications. Unless otherwise agreed in writing, the product is not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

Right to make changes — NXP Semiconductors reserves the right to

make changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

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Rev. 1 — 12 August 2020

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NXP Semiconductors

TJA1443

High-speed CAN transceiver with Sleep mode

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer's own

risk.

Security — While NXP Semiconductors has implemented advanced

security features, all products may be subject to unidentified vulnerabilities.

Customers are responsible for the design and operation of their applications

and products to reduce the effect of these vulnerabilities on customer’s

applications and products, and NXP Semiconductors accepts no liability for

any vulnerability that is discovered. Customers should implement appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

19.4 Trademarks

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

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NXP Semiconductors

TJA1443

High-speed CAN transceiver with Sleep mode

Contents

1

2

2.1

2.2

2.3

2.4

3

4

5

6

6.1

6.2

7

7.1

7.1.1

7.1.1.1

7.1.1.2

7.1.1.3

7.1.1.4

7.1.1.5

7.1.1.6

General description ............................................ 1

13.1

14

15

Quality information ...........................................24

Package outline .................................................25

Handling information ........................................27

Soldering of SMD packages .............................27

Introduction to soldering .............................

Wave and reflow soldering .........................

Wave soldering ...........................................

Reflow soldering .........................................

Soldering of HVSON packages ........................29

Appendix: ISO 11898-2:2016 parameter

cross-reference list ...........................................30

Legal information ..............................................32

Features and benefits .........................................1

General .............................................................. 1

Predictable and fail-safe behavior ..................... 1

Low-power management ................................... 2

Diagnosis & Protection ...................................... 2

Quick reference data .......................................... 3

Ordering information .......................................... 3

Block diagram ..................................................... 4

Pinning information ............................................ 5

Pinning ...............................................................5

Pin description ...................................................5

Functional description ........................................6

Operating modes ............................................... 6

System operating modes ...................................6

Off mode ............................................................6

Standby mode ................................................... 7

Normal mode .....................................................7

Listen-only mode ............................................... 7

Sleep mode ....................................................... 7

System operating modes and gap-free

16

16.1

16.2

16.3

16.4

17

18

19

operation ............................................................8

CAN operating modes ....................................... 9

CAN Off mode ...................................................9

CAN Offline mode ............................................. 9

CAN Wake mode .............................................10

CAN Pass-through mode .................................10

CAN Active mode ............................................10

CAN Listen-only mode .....................................10

Internal flags ....................................................10

Pwon flag .........................................................11

Wake flag .........................................................11

Local wake-up ................................................. 11

Remote wake-up (via the CAN bus) ................ 11

Wake-up source flag ....................................... 12

Local failure flag .............................................. 12

Local failure events ......................................... 13

TXD dominant failures .....................................13

TXD-to-RXD short circuit .................................13

Bus dominant failures ......................................13

Overtemperature ..............................................13

I/O levels ..........................................................13

WAKE pin ........................................................ 14

Internal biasing of TXD, STB_N and EN input

7.1.2

7.1.2.1

7.1.2.2

7.1.2.3

7.1.2.4

7.1.2.5

7.1.2.6

7.2

7.2.1

7.2.2

7.2.2.1

7.2.2.2

7.2.3

7.2.4

7.3

7.3.1

7.3.2

7.3.3

7.3.4

7.4

7.5

7.6

pins .................................................................. 14

Limiting values ..................................................15

Thermal characteristics ....................................16

Static characteristics ........................................16

Dynamic characteristics ...................................19

Application information ....................................23

Application diagram ......................................... 23

Application hints .............................................. 23

Test information ................................................24

8

9

10

11

12

12.1

12.2

13

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section 'Legal information'.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 12 August 2020

Document identifier: TJA1443


型号：	TJA1443
厂家：	NXP
描述：	High-speed CAN transceiver with Sleep mode
文件：	总34页 (文件大小：400K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TJA1443 [NXP]

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