TM-1100 [NXP]
Programmable Media Processor; 可编程的媒体处理器
| 型号： | TM-1100 |
| 厂家： | 
NXP |
| 描述： | Programmable Media Processor |
| 文件： | 总8页 (文件大小：343K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TriMediaTM-1100
Programmable Media Processor
On a single chip, a TriMedia™ TM-1100 delivers
rea l- t ime pro c es sin g o f a udio , video , gr ap hi cs ,
an d c o mmu n ic at io n s dat as t rea ms . Wit h i ts l ow-
c o st 1 33 -M Hz C PU a n d a f u ll c o mpl e men t of
o n -c hip I/ O an d c op ro c es sin g p er ip her a l un i ts ,
t he T M-1 10 0 media pro c es so r del iver s u p to
5 . 3 BO PS t o n ew mul t im edia pro duc t s . 1 00%
pi n co mp at ib il it y wit h th e T M-1 00 0 proc e ss or
en s ures t hat de vel o pe rs c an t ak e i mme diat e
advan t age o f up t o 3 3% mo re p ro c es sin g powe r
in t heir e xi st in g T M-1 00 0 des ign s.
C om pa ra bl e in p ro gr amm abil it y t o a gen e ral -
pu rp o s e p ro c es so r, the Tr iMedia T M-1 100
arc hit ec t ure e n abl e s de vel o pm en t o f mul ti -
me dia ap pl ic at io n s en t irel y in t he C a n d C ++
pro gr amm ing la n guage s . Pro gr amm abil it y
imp roves t ime -t o -m arke t , l ower s devel o p me n t
c o st s , a nd e x t en ds pro duc t l if e t hro ugh
s o f tw are u pgr adab il it y.
FEATURES
+ Processes audio, video, graphics and communications
datastreams on a single chip
MULTIMEDIA APPLICATIONS
+ Powerful, fine-grain parallel, 133-MHzVLIW CPU with
versatile instruction set includes special multimedia and
DSP operations
The TM-1100 is an ideal building block for any multimedia appli-
cation that processes multiple multimedia and communications
datastreams. It is well suited for creating a range of consumer and
professional products such as videophones, videoconferencing and
video editing systems, security systems, DVD encode/decode
devices, and digital television appliances.
+ Pin compatibility with TM-1000 delivers up to 33%
more performance to TriMedia TM-1000 designs
+ Multiple, independent, DMA-driven multimedia I/O and
coprocessing units format data and offload the CPU
SINGLE-CHIP MULTIMEDIA ENGINE
+ Enhanced video out functionality includes 7-bit alpha
blending, full chroma keying, genlock capability, and
programmableYUV color clipping
Powered by a low-cost, 133-MHz, C-programmable CPU, the
TriMedia TM-1100 strikes a perfect compromise between cost and
performance. To streamline data throughput, TM-1100 incorporates
independent on-chip DMA-driven peripheral units that manage
datastream I/O and formatting and accelerate processing of key
multimedia algorithms. To reap the full benefit of the CPU and pro-
cessing units, TM-1100’s sophisticated memory hierarchy manages
internal I/O and streamlines access to external memory. The result —
a single, low-cost programmable chip that powers standalone and
PC-hosted multimedia products.
+ PCI/XIO bus interface supports glueless interface to a
mix of PCI and 8-bit microcomputer peripheral chips,
such as ROM/Flash, EEPROM, 68K, and x86 devices
+ Robust software development tools enable multimedia
application development entirely in C/C++
+ DVD playback authentication/descrambling functions
for PC and standalone applications
+ 16- and 64-Mbit SDRAM support up to 133-MHz
S D R A M
MAIN MEMORY
INTERFACE
VIDEO IN
AUDIO IN
VLD COPROCESSOR
ENHANCED VIDEO OUT
TIMERS
A single-chip
multimedia
engine
AUDIO OUT
SYNCHRONOUS
SERIAL INTERFACE
2
I
C INTERFACE
Powered by a low-cost,
133-MHz, C-programmable CPU,
theTriMediaTM-1100 strikes a
perfect compromise between
cost and performance.
IMAGE
COPROCESSOR
INSTR.
CACHE
VLIW CPU
DATA
CACHE
PCI XIO INTERFACE
/
TO
PCI XIO
BUS
/
INTERNAL BUS (DATA HIGHWAY)
TM-1100 ARCHITECTURE
On a single chip, the TM-1100 incorporates a powerful CPU and
peripherals to accelerate processing of audio, video, graphics, and
communications data.
PROGRAMMABLE VLIW CPU
POWERFUL, DSP-LIKE, C-CALLABLE MULTIMEDIA OPS
In addition to traditional microprocessor operations and a full
complement of 32-bit, IEEE-compliant, floating point operations,
the TM-1100 instruction set includes multimedia and DSP operations
that accelerate the performance of multimedia applications. Such mul-
timedia operations can replace up to 11 traditional microprocessor
operations. When incorporated into application source code, they
dramatically improve performance and amplify the efficiency of the
TM-1100’s parallel architecture.
The TM-1100 delivers top performance through an elegant imple-
mentation of a very-long instruction word (VLIW) architecture.
Key to the TriMedia processor’s VLIW implementation, parallelism is
optimized at compile time by the TriMedia compilation system. No
specialized scheduling hardware is required to parallelize code during
execution. Hardware saved by eliminating complex scheduling logic
reduces cost and allows the integration of multimedia features that
enhance the power of the CPU in multimedia applications.
The TM-1100 processor’s powerful DSP-like, 32-bit CPU achieves
fine-grain parallelism by simultaneously targeting five of its 27
pipelined functional units within one clock cycle. Most common
operations have their results available in one clock cycle; more
complex operations have multicycle latencies.
Multimedia operations are invoked with familiar function-call syntax
consistent with the C programming language. They are automatically
scheduled to take full advantage of the TriMedia processor’s highly
parallel VLIW implementation. As with all other operations generated
by the TriMedia VLIW compilation system, the scheduler takes care of
register allocation, operation packing, and flow analysis.
Functional units can access 128 fully general-purpose, 32-bit registers
during execution. Since registers are not separated into banks, any
operation can use any register for any operand. Both big and little
endian byte ordering are supported.
The TM-1100 processor enhances the multimedia operation set
available for the TM-1000 with 6 additional operations that improve
efficiency of MPEG-2 9-bit precise decoding, support video
de-interlacing (median filtering), and more.
The TriMedia TM-1100 CPU also provides special support for
instruction and data breakpoints, useful in debugging and program
development.
MEMORY SYSTEM OVERVIEW
To reap the full benefit of the TM-1100 processor’s CPU and pro-
cessing units, its memory hierarchy must read and write data (and
instructions) fast enough to keep these units busy. Thus to meet the
TM-1100 Specifications
PHYSICAL
CACHES
Process
Packaging
Pins
C75: CMOS 0.35 micron; 5-layer metal
Access
data 8-, 16-, 32-bit word
instruction 64 bytes
TE_QFP
Associativity
Block Size
Size
8-way set-associative with LRU replacement
64 bytes
total 240
I/O pins 3.3 V with 5 V tolerance
data 16 KB
instruction 32 KB
Power
supply 3.3 V +/- 5%
dissipation 6W (max)
consumption 1808 mA 5.97 W
management dynamic standby less than
990 mW
INTERNAL DATA HIGHWAY
Protocol
64-byte block-transfer
separate 32-bit data and 32-bit address buses
CENTRAL PROCESSING UNIT
PCI INTERFACE
Speed
Clock Speed
133 MHz
33 MHz
Instruction Length
Instruction Set
variable (2 to 23 bytes); compressed
Bus Width
Address Space
Voltage
32-bit
arithmetic and logical ops, load/store ops.,
special multimedia and DSP ops.,
IEEE-compliant floating point ops.
32 bits (4 GB)
drive and receive at 3.3V or 5V
Issue Slots
5
Standard Compliance PCI Local Bus Specification 2.1
Functional Units
27, pipelined
VIDEO IN
integer and floating-point arithmetic
units, data-parallel DSP-like units
Supported Signals
CCIR 601/656 8-bit video up to 19 Mpix/sec
raw 8-10-bit data (messages) up to 38 MB/sec
name
constant
integer ALU
memory load/store
shift
DSPALU
DSP multiply
branch
quantity latency recovery
Image Sizes
Functions
all sizes, subject to sample rate
5
5
2
2
2
2
3
2
2
1
1
1
1
3
1
2
3
3
3
3
1
1
1
1
1
1
1
1
1
programmable on-the-fly 2X horizontal
resolution subsampling
ENHANCEDVIDEO OUT
Image Sizes
flexible, including CCIR601;
maximum 4K x 4K pixels (subject to
80 MB/sec data rate)
float ALU
Input Formats
Output Formats
Clock Rates
YUV 4:2:2, YUV 4:2:0
integer/float mul
float compare
float sqrt./divide
1
17
1
16
CCIR601/656 8-bit video, PAL or NTSC
programmable (4-80 MHz), typically 27
MB/sec (13.5 Mpixels/sec for NTSC, PAL)
Registers
128 (32-bit width)
Transfer Speeds
Functions
80 MB/sec in data-streaming and
message-passing modes; 40 Mpix/sec in
YUV 4:2:2 mode
Special Multimedia/
DSP Operations
total 32 ops
MEMORY SYSTEM
Speed
full 129-level alpha blending, genlock
mode, frame synchronization, chroma key,
programmable YUV color clipping
66/80/100/133 MHz
CPU/Memory
Speed Ratios
programmable; 1:1, 5:4, 4:3, 3:2, and 2:1
AUDIO IN / AUDIO OUT
Number of Channels 2 input; 8 output
Memory Size
512 KB to 64 MB (up to four ranks)
Supported Types
16-Mbit SDRAM (x4, x8, x16);
SGRAM (x32); 64-Mbit SDRAM (x32)
Sample Size
8- or 16-bit samples per channel
Sample Rates
1 Hz to 100 KHz
programmable with 0.001 Hz resolution
Width
32-bit bus
Max. Bandwidth
Interface
532 MB/sec (at 133 MHz)
Data Formats
8-bit mono and stereo; 16-bit mono and
stereo PC standard memory data format
glueless up to 4 16-Mbit or 2 64-Mbit
chips at 133 MHz; more chips with slower
clock and/or external buffers
External Interface
4 pins each: 1 programmable clock output,
3 flexible serial input (AI) or output (AO)
interface
Signal Levels
3.3 V LVTTL
Clock Source
internal or external
2
Native Protocol
I S and other serial 3-wire protocols
Multimedia
application
development
entirely in C
and C++
By enabling development of
multimedia applications
entirely in the C and C++
programming languages, the
SDE dramatically lowers
development costs, reduces
time-to-market, and ensures
code portability to next gen-
eration architecture.
ROBUST SOFTWARE DEVELOPMENT ENVIRONMENT
The TriMedia software development environment (SDE) includes a
full suite of system software tools to compile and debug code, analyze
and optimize performance, and simulate execution for the TM-1100
processor. By enabling development of multimedia applications entire-
ly in the C and C++ programming languages, the SDE dramatically
lowers development costs, reduces time-to-market, and ensures code
portability to next generation architecture.
TRIMEDIA REAL-TIME OPERATING SYSTEM KERNELS
For multimedia applications requiring system resource and task
™
management, the TM-1100 media processor supports the pSOS+
embedded real-time operating system kernels. Developed by Integrated
Systems, Inc. (ISI), the pSOS+ kernels are optimized to deliver the
deterministic response essential for multimedia applications.
HOST-ASSISTED COPROCESSOR
internal I/O requirements of its target applications, the TM-1100
couples substantial on-chip caches with a glueless memory interface.
S D R A M
Dedicated instruction and data cache — TM-1100’s CPU is
supported by separate, dedicated on-chip data and instruction caches.
Even without a second-level cache structure, TriMedia caches deliver
media performance an order of magnitude greater than x86 processors.
VCR
TV MONITOR
CAMERA
AUDIO
GRAPHICS
CARD
AUDIO
RGB IMAGE SEQUENCES
PCI XIO BUS
/
The dual-ported data cache allows two simultaneous accesses. It is
non-blocking, thus cache misses and CPU cache accesses can be han-
dled simultaneously. Early restart techniques reduce read-miss latency.
Background copyback reduces CPU stalls.
HOST CPU
MEMORY
To reduce internal bus bandwidth requirements, instructions in main
memory and cache use a compressed format. The compressed instruc-
tion format improves the cache hit rate and reduces bus bandwidth.
Instructions are compressed during compilation and decompressed in
the instruction cache before being processed by the CPU.
STANDALONE
S D R A M
VCR
TV MONITOR
CAMERA
AUDIO
PERIPHERAL
PERIPHERAL
AUDIO
To improve cache behavior and thus performance, both caches have
a locking mechanism. Cache coherency is maintained by software.
PCI XIO BUS
/
Glueless memory system interface — TM-1100’s glueless main
memory interface couples the on-chip caches and multimedia
peripheral units to main memory (SDRAM). It acts as the SDRAM
controller and programmable central arbiter that allocates SDRAM
memory bandwidth for on-chip peripheral unit activities. Higher
BUS
ARBITER
ROM/FLASH
TM-1100 is designed for use as a coprocessor in a PC-hosted
environment or as the sole CPU in standalone systems.
bandwidth SDRAM permits TM-1100 to use a narrower and simpler
interface than would be required to achieve similar performance with
standard DRAM.
The TM-1100 memory interface provides sufficient capacity to drive
a memory system consisting of up to 133-MHz, 8-MB (four 2Mx8)
or 16-MB (two 2Mx32) SDRAMs. Larger memories can be imple-
mented by using lower memory system clock frequencies or external
buffers. Programmable speed ratios allow SDRAM to have a different
clock speed than the TM-1100 CPU. Support for a variety of memory
types, speeds, bus widths, and off-chip bank sizes allow a range of
TM-1100-based systems to be configured.
UME8UU: SUM OF ABSOLUTE VALUES
OF UNSIGNED 8-BIT DIFFERENCES
SOURCE REGISTER 1
SOURCE REGISTER 2
31
0
31
0
A
B
C
D
E
F
G
H
DSPALU
FUNCTIONAL
UNIT
|A-E|
+
|B-F|
+
|C-G|
+
|D-H|
(
)
HIGH-SPEED INTERNAL BUS DATA HIGHWAY
31
0
The memory system interface also mediates bandwidth allocation of
the TM-1100’s on-chip central data highway. A high-speed internal
bus consisting of separate 32-bit address and data buses, the data high-
way connects the CPU and all on-chip I/O and coprocessing units to
external SDRAM (through the memory interface) and to an off-chip
PCI or XIO bus (through the PCI/XIO interface). Programmable
bandwidth enables the data highway to deliver real-time responsive-
ness in a variety of multimedia applications.
DESTINATION
REGISTER
RESULT
SPECIAL MULTIMEDIA OPERATIONS
The ume8uu operation, commonly used for motion estimation in
video compression, implements 11 simple operations in one
TriMedia special op.
On-chip
multimedia I/O
& coprocessing
units
To streamline data throughput,
TM-1100’s independent DMA-driven
peripheral units manage I/O,
format video, audio, graphics, and
communications datastreams,
and perform operations specific
to key multimedia algorithms.
MULTIMEDIA I/O AND COPROCESSING UNITS
registers can be precisely controlled through programmable registers.
Programmable interrupts and dual buffers facilitate continuous data
streaming by allowing the CPU to set up a buffer while another is
being emptied by the EVO unit.
Video input — The video input (VI) unit reads digital video data-
streams from an off-chip source into main memory. The VI unit
accepts input from CCIR656-compliant devices that output 8-bit
parallel, 4:2:2 YUV time-multiplexed video data, such as digital video
cameras, digital video decoders, or devices connected through ECL-
level converters to the standard D1 parallel interface. After input, YUV
data is demultiplexed, subsampled as needed, and written to SDRAM.
While generating the multiplexed stream, the EVO unit can perform
programmed tasks, including optional horizontal 2X upscaling to con-
vert from CIF/SIF to CCIR 601 resolution. For simultaneous display
of graphics and live video, the EVO unit can perform 129-level alpha
blending to generate sophisticated graphics overlays of arbitrary size
and position within the output image. Chroma keying, genlock frame
synchronization, and programmable YUV output clipping are also
supported. The EVO unit can also pass raw data and unidirectional
messages to another TriMedia processor.
The VI unit can be programmed to perform on-the-fly 2X hori-
zontal resolution subsampling. This enables high-resolution images
(640- or 720-pixels/line) to be captured and converted to 320- or
360-pixels/line without burdening the CPU. When lower resolution
video is eventually desirable, performing subsampling during data cap-
ture reduces initial storage and bus bandwidth requirements. The VI
unit can receive raw data and unidirectional messages from another
TM-1100’s video out port.
Audio input and audio output — Together the audio input (AI)
and audio output (AO) units provide all signals needed to interface to
most high-quality, low-cost serial audio D/A and A/D converters. Both
audio units are highly programmable, providing tremendous flexibility
in developing custom datastream handling, adapting to custom proto-
cols, and upgrading to support future audio standards.
Enhanced video output — The enhanced video out (EVO) unit
outputs a digital YUV datastream to off-chip video subsystems such as
a digital video encoder chip, digital video recorder, or other CCIR656-
compatible device. The output signal is generated by gathering bits
from the separate Y, U, and V data structures in SDRAM.
The audio peripheral units connect to off-chip stereo converters
through flexible bit-serial interfaces. The AI unit supports one or two
channels of audio input; the AO unit delivers up to eight channels of
The EVO unit can either supply or receive video clock and/or
synchronizing signals from the external interface. Clock and timing
datastreams such as MPEG-1 and MPEG-2. It reads video streams
from SDRAM and outputs a decoded stream optimized for MPEG-2
decompression software. This minimizes communications with the
CPU where other portions of MPEG processing are performed.
DVD descrambler — The TM-1100 processor’s digital versatile disc
descrambler unit provides DVD authentication and descrambling
functions internally. These features enables developers to add low-cost,
flexible DVD-video playback functions in PC and standalone applica-
tions with a minimum of effort.
2
I2C interface — TM-1100’s I C interface unit provides an external
2
I C or compatible interface for use in hardware or software mode. In
2
hardware mode, it can be used to connect and control a variety of I C
multimedia devices. This allows TM-1100 to configure and inspect
status of peripheral video devices such as digital decoders and encoders,
digital cameras, parallel I/O expanders and more.
2
2
I C software operation mode enables full control of the I C interface
2
through software. The I C interface is also used to read the boot pro-
gram from an off-chip EEPROM.
Synchronous serial interface — TM-1100’s synchronous serial
interface (SSI) unit provides serial access for a variety of multimedia
applications, such as video phones or videoconferencing, and for gen-
eral data communications in PC-based systems. The SSI unit contains
all the buffers and logic necessary to interface with simple analog
modem front ends. When used with the TriMedia V.34 software
library, the SSI unit provides fully V.34-compliant modem capability.
Alternatively, it can be connected to an ISDN interface chip to pro-
vide advanced digital modem capabilities.
output. Eight-bit mono and stereo and 16-bit mono and stereo PC
standard memory data formats are supported. The AO unit can be
used to control highly integrated PC codecs.
Timers — The TM-1100 provides four general purpose timers useful
for counting/timing events such as CPU clock cycles, data/instruction
breakpoints, cache tracing, audio/video clocks, and more. Three timers
are available to programmers, the fourth is reserved for system software.
Each timer has a value that can be continuously inspected as needed
for an application and an associated modulus that can be used to gen-
erate an interrupt when the timer’s value reaches the modulus.
Driven by TM-1100, the programmable audio sampling clock sup-
ports rates from 1 Hz to 100 KHz. High resolution of .001 Hz gives
programmers subtle control over sampling frequency enabling audio
and video synchronization in even the most complex configurations.
Image coprocessor — The image coprocessor (ICP) offloads the
TriMedia CPU of several image processing and manipulation tasks
such as copying an image from SDRAM to a host’s video frame buffer.
The ICP can operate as either a memory-to-memory or a memory-to-
PCI coprocessor device. In memory-to-memory mode, the ICP can
perform horizontal or vertical image filtering and scaling. In memory-
to-PCI modes, it can perform horizontal scaling and filtering followed
by YUV to RGB color-space conversion for screen display.
High-speed PCI/XIO bus interface — TM-1100’s PCI/XIO inter-
face unit connects the CPU and on-chip I/O and coprocessing units
to a PCI/XIO bus. In embedded applications where TM-1100 is the
main processor, this interface enables the TM-1100 to access off-chip
devices that implement functions not provided by on-chip peripherals.
In PC-based applications, the PCI/XIO interface connects TM-1100
to a standard PCI bus, allowing it to be placed directly on the PC
mainboard or on a plug-in card. For low-cost standalone systems, XIO
allows glueless connection of 8-bit x86 or 68K peripheral devices such
as ROM, Flash, EEPROM, UARTs, etc.
The ICP also provides display support for live video in overlapping
windows. The number and sizes of windows processed are limited only
by available bandwidth. The final resampled and converted image pix-
els are transmitted over the PCI/XIO bus to an optional off-chip
graphics card/frame buffer.
Variable length decoder — TM-1100’s variable length decoder
(VLD) unit offloads the CPU of decoding Huffman-encoded video
FOR MORE INFORMATION CONTACT:
PHILIPS SEMICONDUCTORS TRIMEDIA BUSINESS LINE
811 EAST ARQUES AVENUE M/S 71, SUNNYVALE CA 94088-3409
PH 800-914-9239 (NORTH AMERICA), 408-991-3838 (WORLDWIDE)
FX 408-991-3300, E-MAIL info@trimedia.sv.sc.philips.com
WEBSITE www.trimedia.philips.com
TM-1100 Specifications
IMAGE COPROCESSOR
Functions
horizontal or vertical scaling and filtering
of individual Y, U, or V
horizontal scaling and filtering with
color conversion and overlay:
- YUV to RGB
Philips Semiconductors - a worldwide company
- RGB overlay and alpha blending
- bit mask blanking
Argentina: see South America
Australia: Tel. +61 2 9805 4455 Fax. +61 2 9805 4466
Austria: Tel. +43 1 60 1010, Fax. +43 1 60 101 1210
Belarus: Tel. +375 172 200 733, Fax. +375 172 200 773
Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Tel. +359 2 689 211, Fax. +359 2 689 102
Canada: Tel. +1 800 234 7381
China/Hong Kong: Tel. +852 2319 7888, Fax. +852 2319 7700
Colombia: see South America
Czech Republic: see Austria
Denmark: Tel. +45 32 88 2636, Fax. +45 31 57 0044
Finland: Tel. +358 9 615800, Fax. +358 9 61580920
France: Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427
Germany: Tel. +49 40 23 53 60, Fax. +49 40 23 536 300
Greece: Tel. +30 1 4894 339/239, Fax. +30 1 4814 240
Hungary: see Austria
Scaling
programmable scale factor (0.2X to 10X)
Filtering
32-polyphase, each instance 5-tap, fully
programmable filter coefficients
Performance
horizontal scaling and filtering: 80 MB/sec
vertical scaling and filtering: 30 MB/sec
horizontal scaling and filtering with color
conversion: 33 Mpixels/sec peak for
RGB output; 50 Mpixels/sec peak for
YUV 4:2:2 output
VLD
Function
India: Tel. +91 22 493 8541, Fax. +91 22 493 0966
Indonesia: see Singapore
parses MPEG-1 and MPEG-2 elementary
bitstreams generating run-level pairs and
filling in macroblock header
Ireland: Tel. +353 1 7640 000, Fax. +353 1 7640 200
Israel: Tel. +972 3 645 0444, Fax. +972 3 649 1007
Italy: Tel. +39 2 6752 2531, Fax. +39 2 6752 2557
Japan: Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
Korea: Tel. +82 2 709 1412, Fax. +82 2 709 1415
Malaysia: Tel. +60 3 750 5214, Fax. +60 3 757 4880
Mexico: Tel. +9-5 800 234 7381
External Interface
none
DVD DESCRAMBLER
Middle East: see Italy
Netherlands: Tel. +31 40 27 82785, Fax. +31 40 27 88399
New Zealand: Tel. +64 9 849 4160, Fax. +64 9 849 7811
Norway: Tel. +47 22 74 8000, Fax. +47 22 74 8341
Philippines: Tel. +63 2 816 6380, Fax. +63 2 817 3474
Poland: Tel. +48 22 612 2831, Fax. +48 22 612 2327
Portugal: see Spain
Functions
authentication; descrambling
External Interface
none
2
I C INTERFACE
Romania: see Italy
Supported Modes
single master only
7- and 10-bit
Russia: Tel. +7 095 755 6918, Fax. +7 095 755 6919
Singapore: Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria
Addressing
Slovenia: see Italy
Rates
up to 400 kbps
South Africa: Tel. +27 11 470 5911, Fax. +27 11 470 5494
South America: Tel. +55 11 821 2333, Fax. +55 11 821 2382
Spain: Tel. +34 3 301 6312, Fax. +34 3 301 4107
Sweden: Tel. +46 8 632 2000, Fax. +46 8 632 2745
Switzerland: Tel. +41 1 488 2686, Fax. +41 1 488 3263
Taiwan: Tel. +886 2 2134 2865, Fax. +886 2 2134 2874
Thailand: Tel. +66 2 745 4090, Fax. +66 2 398 0793
Turkey: Tel. +90 212 279 2770, Fax. +90 212 282 6707
Ukraine: Tel. +380 44 264 2776, Fax. +380 44 268 0461
United Kingdom: Tel. +44 181 730 5000, Fax. +44 181 754 8421
United States: Tel. +1 800 234 7381
External Interface
2 pins: 1 serial data, 1 clock
SYNCHRONOUS SERIAL INTERFACE
Data Formats
variable slots/frame
Frame Sync
external or internal
Clock Source
separate transmit, receive, frame sync
transmit/receive clocks external source
automatic frame sync error detection
settable edge polarity for transmit, receive,
and frame sync
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: Tel. +381 11 625 344, Fax. +381 11 635 777
For all other countries apply to: Philips Semiconductors, International
Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
External Interface
6 pins (2 can be used for tip and ring
for phone connections); compatible with
a majority of telecom devices
Internet: http://www.semiconductors.philips.com
© 1998 Philips Electronics North America Corporation. All rights are reserved.
Reproduction in whole or in part is prohibited without the prior written consent
of the copyright owner.
can be configured with multiple chips
TriMedia and the TriMedia design are trademarks of Philips Electronics North
America Corporation. pSOS, pSOS+, and pSOS+m are trademarks of Integrated
systems, Inc. Other brands and products are trademarks or registered trademarks
of their respective owners.
TIMERS
Number
4
The information presented in this document does not form part of any quotation
of contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequences of its
use. Publication thereof does not convey or imply any license under patent or
other industrial or intellectual property rights.
Width
32-bits
Sources
external clock, (prescaled) CPU clock, data
or instruction breakpoints, cache events,
video in/out clocks, audio in/out word
strobe, V.34 receive/transmit frame sync
Printed in The Netherlands. Date of release: September 1998
Pub. No.: 9397-750-03177
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