TSA5526 [NXP]
1.3 GHz universal bus-controlled TV synthesizers; 1.3 GHz的通用总线控制的电视合成
| 型号： | TSA5526 |
| 厂家： | 
NXP |
| 描述： | 1.3 GHz universal bus-controlled TV synthesizers |
| 文件： | 总28页 (文件大小：293K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TSA5526; TSA5527
1.3 GHz universal bus-controlled
TV synthesizers
1996 Sep 24
Product specification
Supersedes data of 1995 Mar 22
File under Integrated Circuits, IC02
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizers
TSA5526; TSA5527
FEATURES
• Complete 1.3 GHz single chip system
• Four PNP band switch buffers (40 mA)
• 33 V output tuning voltage
• In-lock detector
• 5-step ADC
APPLICATIONS
• 15-bit programmable divider
• TV tuners and front ends
• VCR tuners.
• Programmable reference divider ratio
(512, 640 or 1024)
• Programmable charge-pump current (60 or 280 µA)
• Programmable automatic charge-pump current switch
• Varicap drive disable
• Universal bus protocol I2C-bus or 3-wire bus:
– bus protocol for 18 or 19 bits transmission
(3-wire bus)
– extra protocol for 27 bits for test and features
(3-wire bus)
– address plus 4 data bytes transmission (I2C-bus write
mode)
– address plus 1 status byte transmission (I2C-bus
read mode)
– three independent I2C-bus addresses
• Low power and low radiation.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
VERSION
TSA5526M
TSA5526T
TSA5527M
TSA5527T
TSA5526AM
TSA5526AT
TSA5527AM
TSA5527AT
SSOP16
SO16
plastic shrink small outline package; 16 leads; body width 4.4 mm
plastic small outline package; 16 leads; body width 3.9 mm
plastic shrink small outline package; 16 leads; body width 4.4 mm
plastic small outline package; 16 leads; body width 3.9 mm
plastic shrink small outline package; 16 leads; body width 4.4 mm
plastic small outline package; 16 leads; body width 3.9 mm
plastic shrink small outline package; 16 leads; body width 4.4 mm
plastic small outline package; 16 leads; body width 3.9 mm
SOT369-1
SOT109-1
SOT369-1
SOT109-1
SOT369-1
SOT109-1
SOT369-1
SOT109-1
SSOP16
SO16
SSOP16
SO16
SSOP16
SO16
1996 Sep 24
2
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizers
TSA5526; TSA5527
QUICK REFERENCE DATA
SYMBOL
PARAMETER
supply voltage (+5 V)
CONDITIONS
MIN.
4.5
TYP.
MAX.
5.5
UNIT
VCC1
VCC2
ICC1
ICC2
fRF
−
V
V
band switch supply voltage (12 V)
supply current
VCC1
−
12
20
50
−
13.5
25
mA
band switch supply current
RF input frequency
note 1
−
55
mA
64
1300
3
MHz
dBm
dBm
dBm
MHz
mA
Vi(RF)
RF input voltage
fi = 80 to 150 MHz
−25
−28
−15
3.2
4
−
fi = 150 to 1000 MHz
fi = 1000 to 1300 MHz
−
3
−
3
fxtal
crystal oscillator input frequency
4.0
−
4.48
50
Io(PNP)
PNP band switch buffers output
current
note 2
note 3
Ptot
total power dissipation
storage temperature
−
250
−
400
mW
°C
Tstg
Tamb
−40
−20
+150
+85
operating ambient temperature
−
°C
Notes
1. One band switch buffer ON, Io = 40 mA.
2. One band switch buffer ON, Io = 40 mA; two buffers ON, maximum sum of Io = 50 mA.
3. The power dissipation is calculated as follows:
PD = VCC1 × ICC1 + VCC2 × (ICC2 – Io) + Io × VCE (satPNP) + (V33 ⁄ 2) 2 ⁄ 27kΩ.
1996 Sep 24
3
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizers
TSA5526; TSA5527
This action is taken to improve the carrier-to-noise ratio.
The status of this feature can be read in the ACPS flag
during a read operation on the I2C-bus (see Table 8).
GENERAL DESCRIPTION
The device is a single-chip PLL frequency synthesizer
designed for TV and VCR tuning systems. The circuit
consists of a divide-by-eight prescaler with its own
preamplifier, a 15-bit programmable divider, a crystal
oscillator and its programmable reference divider and a
phase/frequency detector combined with a charge-pump
which drives the tuning amplifier and the 33 V output.
Four high-current PNP band switch buffers are provided
for band switching. Two PNP buffers can be switched on
simultaneously. The sum of the collector currents is limited
to 50 mA.
I2C-bus format (SW = LOW)
Five serial bytes (including address byte) are required to
address the device, select the VCO frequency, program
the four PNP band switch buffers, set the charge-pump
current and the reference divider ratio.
The device has three independent I2C-bus addresses
which can be selected by applying a specific voltage on the
CE input (see Table 5). The general address C2 is always
valid. When the I2C-bus format is fully used, TSA5526 and
TSA5527 are equal.
Depending on the reference divider ratio (512, 640 or
1024), the phase comparator operates at 3.90625 kHz,
6.25 kHz or 7.8125 kHz using a 4 MHz crystal.
3-wire bus format (SW = VCC1 or open-circuit)
The device can be controlled in accordance with the
I2C-bus format or the 3-wire bus format depending on the
voltage applied to the SW input (see Table 2). In the 3-wire
bus mode (SW = HIGH) pin 12 is the LOCK output.
The lock output is LOW when the PLL loop is locked. In the
I2C-bus mode (SW = LOW) the LOCK detector bit FL is set
to logic 1 when the loop is locked and is read on the SDA
line (status byte) during a read operation. The ADC input
is available on pin 12 for AFC control in the I2C-bus mode
only. The ADC code is read during a read operation on the
I2C-bus. In the test mode pin 12 is used as a test output for
fref and 1⁄2fdiv in the I2C-bus mode and the 3-wire bus mode
(see Table 6).
Data is transmitted to the device during a HIGH level on
the CE input (enable line pin 15). The device is compatible
with 18-bit and 19-bit data formats. The first four bits are
used to program the PNP band switch buffers and the
remaining bits are used to control the programmable
divider. A 27-bit data format may also be used to set the
charge-pump current, the reference divider ratio and for
test purposes. The differences between TSA5526 and
TSA5527 are given in Table 1.
When the 27-bit format is used, the TSA5526 and
TSA5527 are equal and the reference divider is controlled
by the RSA and RSB bits (see Table 7 and
Figs 3, 4 and 5).
When the automatic charge-pump current switch mode is
activated, depending on the device given in Table 6, and
when the loop is phase-locked, the charge-pump current
value is automatically switched to LOW.
Table 1 Differences between TSA5526 and TSA5527
TYPE NUMBER
TSA5526
DATA WORD
18-bit
REFERENCE DIVIDER
FREQUENCY STEP (kHz)
512(1)
1024(1)
640(2)
62.5
31.25
50
TSA5526
19-bit
TSA5527
19-bit
Notes
1. The selection of the reference divider is given by an automatic identification of the data word length.
2. The reference divider is set to 640 at power-on reset.
1996 Sep 24
4
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizers
TSA5526; TSA5527
BLOCK DIAGRAM
BM3E27
bnok,lfuapgedwith
1996 Sep 24
5
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizers
TSA5526; TSA5527
PINNING
SYMBOL PIN
DESCRIPTION
RF signal input
RF
1
2
3
4
5
6
7
8
9
VEE
ground
VCC1
VCC2
BS4
BS3
BS2
BS1
CP
supply voltage (+5 V)
handbook, halfpage
RF
EE
XTAL
1
2
3
4
5
6
7
8
16
band switch supply voltage (+12 V)
PNP band switch buffer output 4
PNP band switch buffer output 3
PNP band switch buffer output 2
PNP band switch buffer output 1
charge-pump output
V
15 CE
V
V
14
13
SDA
SCL
CC1
CC2
BS4
BS3
TSA5526
TSA5527
12 LOCK/ADC
11
10
9
SW
V
Vtune
SW
10 tuning voltage output
11 bus format selection input, I2C-bus
or 3-wire
BS2
BS1
tune
CP
MBE326
LOCK/ADC 12 lock detector output (3-wire bus/
ADC input (I2C-bus)
SCL
SDA
CE
13 serial clock input
14 serial data input/output
15 chip enable/address selection input
16 crystal oscillator input
Fig.2 Pin configuration.
XTAL
The first bit of the first data byte transmitted indicates
whether frequency data (first bit = logic 0) or control and
band switch data (first bit = logic 1) will follow. Until an
I2C-bus STOP command is sent by the controller,
additional data bytes can be entered without the need to
readdress the device. The frequency register is loaded
after the 8th clock pulse of the second Divider Byte (DB2),
the control register is loaded after the 8th clock pulse of the
Control Byte (CB) and the band switch register is loaded
after the 8th clock pulse of the Band switch Byte (BB).
FUNCTIONAL DESCRIPTION
The device is controlled via the I2C-bus or the 3-wire bus
depending on the voltage applied to the SW input (pin 11).
A HIGH level on the SW input enables the 3-wire bus
inputs which are CE (Chip Enable), SDA (serial data input)
and SCL (serial clock input). A LOW level on the SW input
enables the I2C-bus inputs which are AS (Address
Selection input), SDA (serial data input/output) and SCL
(serial clock input). The bus format selection is given in
Table 2.
I2C-BUS ADDRESS SELECTION
I2C-bus mode (SW = LOW); see Table 3
The module address contains programmable address bits
(MA1 and MA0) which offer the possibility of having
several synthesizers (up to 3) in one system by applying a
specific voltage to the CE input.
WRITE MODE (R/W = 0)
Data bytes can be sent to the device after the address
transmission (first byte). Four data bytes are required to
fully program the device. The bus transceiver has an
auto-increment facility which permits the programming of
the device within one single transmission
The relationship between MA1 and MA0 and the input
voltage applied to the CE input is given in Table 5.
(address + 4 data bytes).
The device can also be partially programmed providing
that the first data byte following the address is Divider
Byte 1 (DB1) or the Control Byte (CB). The bits in the data
bytes are defined in Table 3.
1996 Sep 24
6
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizers
TSA5526; TSA5527
Table 2 Bus format selection
PIN
NAME
3-WIRE BUS MODE
I2C-BUS MODE
11
12
13
14
15
SW
LOCK/ADC
SCL
OPEN or HIGH
LOCK/TEST output
clock input
LOW
ADC input/TEST output
SCL input
SDA
data input
SDA input/output
address selection input
CE
chip enable input
Table 3 I2C-bus data format
SLAVE
LSB
BYTE
MSB
DATA BYTE
ANSWER
Address Byte (ADB)
Divider Byte 1 (DB1)
Divider Byte 2 (DB2)
Control Byte (CB)
1
0
1
N14
N6
CP
X
0
N13
N5
T2
X
0
N12
N4
T1
X
0
MA1
N10
N2
MA0
N9
R/W = 0
N8
A
A
A
A
A
N11
N3
N7
1
N1
N0
T0
RSA
BS3
RSB
BS2
OS
Band switch Byte (BB)
X
BS4
BS1
Table 4 Description of Table 3
SYMBOL
DESCRIPTION
A
acknowledge
programmable address bits (see Table 5)
programmable divider bits; N = N14 × 214 + N13 × 213 + ... + N1 × 2 + N0
charge-pump current; CP = 0 = 60 µA; CP = 1 = 280 µA (default)
test bits (see Table 6); for normal operation T2 = 0, T1 = 0 and T0 = 1 (default)
reference divider ratio select bits (see Table 7)
MA1 and MA0
N14 to N0
CP
T2 to T0
RSA and RSB
OS
tuning amplifier control bit; for normal operation OS = 0 and tuning voltage is ON (default);
when OS = 1 tuning voltage is OFF (high impedance)
BS4 to BS1
X
PNP band switch buffers control bits; when BSn = 0 buffer n is OFF; when BSn = 1 buffer n
is ON
don’t care
Table 5 I2C-bus address selection
VOLTAGE APPLIED TO THE CE INPUT (SW = LOW)
MA1
MA0
0 V to 0.1VCC1
Always valid
0
0
1
1
0
1
0
1
0.4VCC1 to 0.6VCC1
0.9VCC1 to VCC1
1996 Sep 24
7
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizers
TSA5526; TSA5527
Table 6 Test bits
T2 T1 T0
TSA5526; TSA5527
TSA5526A; TSA5527A
REMARKS
0
0
0
normal operation with automatic
charge-pump switch ON
automatic charge-pump switch OFF
0
0
1
normal operation with automatic
charge-pump switch OFF
automatic charge-pump switch ON status at POR
0
1
1
1
1
1
1
0
X
0
1
0
charge-pump is OFF
charge-pump is OFF
charge-pump is sinking current
charge-pump is sourcing current
fref is available at LOCK output
charge-pump is sinking current
charge-pump is sourcing current
fref is available at LOCK output
the ADC cannot be used
when test mode is active
1
0
1
1⁄2fdiv is available at LOCK output
1⁄2fdiv is available at LOCK output
the ADC cannot be used
when test mode is active
The device will then release the data line to allow the
microcontroller to generate a stop condition. The POR flag
is set to logic 1 at power-on. The flag is reset when an
end-of-data is detected by the device (end of a read
sequence). Control of the loop is made possible with the
in-lock flag (FL) which indicates when the loop is locked
(FL = logic 1).
Table 7 Ratio select bits
RSA
RSB
REFERENCE DIVIDER
X
0
1
0
1
1
640
1024
512
The Automatic Charge-Pump Switch flag (ACPS) is LOW
when the automatic charge-pump switch mode is ON and
the loop is locked. In other conditions ACPS = logic 1.
When ACPS = logic 0, the charge-pump current is forced
to the LOW value.
READ MODE (R/W = LOGIC 1); see Table 8
Data can be read from the device by setting the R/W bit to
logic 1. After the slave address has been recognized, the
device generates an acknowledge pulse and the first data
byte (status byte) is transferred on the SDA line (MSB
first). Data is valid on the SDA line during a HIGH level of
the SCL clock signal. A second data byte can be read from
the device if the microcontroller generates an
acknowledge on the SDA line (master acknowledge).
End of transmission will occur if no master acknowledge
occurs.
A built-in ADC is available at pin 12 (I2C-bus only).
This converter can be used to apply AFC information to the
microcontroller from the IF section of the television.
The relationship between the bits A2 to A0 is given in
Table 9.
Table 8 Read data format
SLAVE
ANSWER
BYTE
MSB
DATA BYTE
LSB
Address Byte (ADB)
Status Byte (SB)
1
1
0
0
1
0
1
MA1
A2(5)
MA0
A1(5)
R/W = 1
A0(5)
A(1)
POR(2)
FL(3) ACPS(4)
−
Notes
1. A = acknowledge.
2. POR = power-on reset flag (POR = logic 1 at power-on).
3. FL = in-lock flag (FL = logic 1 when the loop is locked).
4. ACPS = automatic charge-pump switch flag (active ACPS = logic 0; non-active ACPS = logic 1).
5. A2 to A0 = digital outputs of the 5-level ADC.
1996 Sep 24
8
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizers
TSA5526; TSA5527
application; see Fig.12), the test bits T2, T1 and T0 are set
to the 0 0 1 state in the normal mode with ACPS OFF for
TSA55226; TSA5527 and ACPS ON for TSA5526A;
TSA5527A. RSB is set to logic 1 (TSA5526) or logic 0
(TSA5527). When an 18-bit data word is transmitted, the
most significant bit of the divider N14 is internally set to
logic 0 and bit RSA is set to logic 1. When a 19-bit data
word is transmitted, bit RSA is set to logic 0.
Table 9 ADC levels
VOLTAGE APPLIED
AT ADC INPUT(1)
A2
A1
A0
0.6VCC1 to VCC1
1
0
0
0
0
0
1
1
0
0
0
1
0
1
0
0.45VCC1 to 0.6VCC1
0.3VCC1 to 0.45VCC1
0.15VCC1 to 0.3VCC1
0 to 0.15VCC1
When a 27-bit word is transmitted, the frequency bits are
loaded into the frequency register on the 20th rising edge
of the clock pulse and the control bits at the HIGH-to-LOW
transition of the chip enable line. In this mode, the
reference divider is given by the RSA and RSB bits
(see Table 7). The test bits T2, T1 and T0, the
charge-pump bit CP, the ratio select bit RSB and the
OS bit can only be selected or changed with a 27-bit
transmission. They remain programmed if an 18-bit or a
19-bit transmission occurs. Only RSA is controlled by the
transmission length when the 18-bit or 19-bit format is
used.
Note
1. Accuracy is ±0.03VCC1
.
3-wire bus mode (SW = open-circuit or VCC1);
see Figs 3, 4 and 5
During a HIGH level on the CE input, the data is clocked
into the data register at the HIGH-to-LOW transition of the
clock pulse. The first four bits control the band switch
buffers and are loaded into the internal band switch
register on the 5th rising edge of the clock pulse.
The frequency bits are loaded into the frequency register
at the HIGH-to-LOW transition of the chip enable line when
an 18-bit or 19-bit data word is transmitted.
A data word of less than 18 bits will not affect the
frequency register of the device. The definition of the bits
is unchanged compared to the I2C-bus mode.
The power-on detection threshold voltage VPOR is fixed to
At power-on the charge-pump current is set to 280 µA, the
tuning voltage output is disabled (Vtune = 33 V in
VCC1 = 2 V at room temperature. Below this threshold, the
device is reset to the power-on state previously described.
For TSA5526 bit RSB = logic 1 at power-on; the reference divider is 512 or 1024.
For TSA5527 bit RSB = logic 0 at power-on; the reference divider is 640.
For TSA5526 and TSA5527 the value of RSB can also be programmed by using the 27-bit data format. When returning to the normal mode, bit RSB
remains as programmed with the 27-bit data word.
Fig.3 Normal mode; 18-bit data format (RSA = 1).
1996 Sep 24
9
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizers
TSA5526; TSA5527
For TSA5526 bit RSB = 1 at power-on; the reference divider is 512 or 1024.
For TSA5527 bit RSB = 0 at power-on; the reference divider is 640.
For TSA5526/TSA5527 the value of RSB can also be programmed by using the 27-bit data format. When returning to the normal mode, bit RSB remains
as programmed with the 27-bit data word.
Fig.4 Normal mode; 19-bit data format (RSA = 0).
For TSA5526 bit RSB = 1 at power-on; the reference divider is 512 or 1024.
For TSA5527 bit RSB = 0 at power-on; the reference divider is 640.
For TSA5526/TSA5527 the value of RSB can also be programmed by using the 27-bit data format. When returning to the normal mode, bit RSB remains
as programmed with the 27-bit data word.
Fig.5 Test and features mode; 27-bit data format.
1996 Sep 24
10
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizers
TSA5526; TSA5527
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MIN.
−0.3
MAX.
UNIT
VCC1
supply voltage; +5 V (pin 3)
+6.0
+16
V
VCC2
band switch supply voltage; +12 V (pin 4)
prescaler input voltage (pin 1)
−0.3
−0.3
−0.3
−1
V
Vi(RF)
Vo(BSn)
Io(BSn)
Vo(CP)
Vo(tune)
Vi(SW)
Vo(LOCK)
Vi(SCL)
Vi/o(SDA)
Io(SDA)
Vi(CE)
Vi(xtal)
Tstg
VCC1
VCC2
+50
V
band switch buffers output voltage (pins 5 to 8)
band switch buffers output current
charge-pump output voltage (pin 9)
output tuning voltage (pin 10)
V
mA
V
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−1
VCC1
+35
V
input switching voltage (pin 11)
lock output voltage (pin 12)
VCC1
VCC1
+6.0
+6.0
+10
V
V
serial clock input voltage (pin 13)
serial data input/output voltage (pin 14)
serial data output current
V
V
mA
V
chip enable input voltage (pin 15)
crystal oscillator input voltage (pin 16)
storage temperature
−0.3
−0.3
−40
−
+6.0
VCC1
+150
+150
10
V
°C
°C
s
Tj
maximum junction temperature
tsc
short-circuit time; every pin except pin 4 to pin 3 and every pin to pin 2; note 1 −
Note
1. Short-circuit between VCC1 and VCC2 is allowed provided the voltage applied to VCC2 is less than the 6 V maximum
rating at VCC1
.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
VALUE
UNIT
Rth j-a
thermal resistance from junction to ambient in free air
SO16
110
142
K/W
K/W
SSOP16
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling bipolar devices. Every pin withstands the ESD test in
accordance with “MIL-STD-883C” category B (2000 V). Every pin withstands the ESD test in accordance with Philips
Semiconductors Machine Model 0 Ω, 200 pF (200 V).
1996 Sep 24
11
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizers
TSA5526; TSA5527
CHARACTERISTICS
VCC1 = 4.5 to 5.5 V; VCC2 = VCC1 to 13.2 V; Tamb = −20 to +85 °C; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN.
TYP. MAX. UNIT
Supplies
VCC1
VCC2
ICC1
supply voltage
4.5
−
5.5
13.5
25
V
band switch buffers supply voltage
supply current
VCC1
−
V
at power-on
−
−
−
20
0.5
50
mA
mA
mA
ICC2
band switch buffers supply current
at power-on
1.0
55
one band switch buffer is
ON; Isource = 40 mA
two band switch buffers are
ON;
−
56
62
mA
Isource = 40 mA + 5 mA
(any combination)
VPOR
fRF
supply voltage below which POR is active
RF input frequency
1.5
64
2.0
−
V
−
1300 MHz
32767
DR
divider ratio
15-bit frequency word
14-bit frequency word
Rxtal = 25 to 300 Ω
fi = 4 MHz
256
256
3.2
600
−
−
16383
fxtal
crystal oscillator input frequency
4
4.48
MHz
Zxtal
crystal oscillator input impedance
(absolute value)
1 200
−
Ω
Prescaler (see Figs 6 and 7)
Vi(RF)
RF input level
fi = 80 to 150 MHz
fi = 150 to 1000 MHz
fi = 1000 to 1300 MHz
see Fig.8
−25
−28
−15
−
−
−
3
3
3
dBm
dBm
dBm
Zi(RF)
input impedance
PNP band switch buffers outputs (pins 5 to 8)
ILO
output leakage current
VCC2 = 13.5 V;
Vo = 0 V
−10
−
−
µA
Vo(sat)
output saturation voltage
Isource = 40 mA;
−
0.2
0.4
V
Vo(sat) = VCC2 − Vo
LOCK output (PNP collector output) 3 wire bus mode (pin 12)
Io(ool)
output current when out-of-lock
VCC1 = 5.5 V; Vo = 5.5 V
−
−
−
100
0.8
µA
Vosat(ool)
output saturation voltage when
out-of-lock
Isource = 200 µA;
Vo(sat) = VCC1 − Vo
0.4
V
Vo(LOCK)
lock output voltage
−
0.01
0.4
V
ADC input (I2C-bus mode) pin 12
Vi(ADC)
IIH(ADC)
IIL(ADC)
ADC input voltage
see Table 9
VADC = VCC1
VADC = 0 V
0
−
−
−
VCC1
10
V
HIGH level input current
LOW level input current
−
µA
µA
−10
−
1996 Sep 24
12
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizers
TSA5526; TSA5527
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
SW input (bus format switch)
VIL
VIH
IIH
LOW level input voltage
HIGH level input voltage
HIGH level input current
LOW level input current
0
−
−
−
−
1.5
VCC1
10
V
3
V
VSW = VCC1
−
µA
µA
IIL
VSW = 0 V
−100
−
CE input (chip enable/address selection)
VIL
VIH
IIH
LOW level input voltage
HIGH level input voltage
HIGH level input current
LOW level input current
0
−
−
−
−
1.5
5.5
10
−
V
3
V
VCE = 5.5 V
VCE = 0 V
−
µA
µA
IIL
−10
SCL and SDA inputs
VIL
VIH
IIH
LOW level input voltage
0
−
−
−
−
−
−
1.5
5.5
10
10
10
−
V
HIGH level input voltage
HIGH level input current
3.0
−
V
VBUS = 5.5 V; VCC1 = 0 V
VBUS = 5.5 V; VCC1 = 5.5 V
VBUS = 1.5 V; VCC1 = 0 V
VBUS = 0 V; VCC1 = 5.5 V
µA
µA
µA
µA
kHz
−
IIL
LOW level input current
clock frequency
−
−10
−
fclk
100
400
SDA outputs (I2C-bus mode)
ILO
Vo
output leakage current
output voltage
VSDA = 5.5 V
Isink = 3 mA
−
−
−
−
10
µA
0.4
V
Charge-pump output CP
|IICPH
|
HIGH charge-pump current
LOW charge-pump current
output voltage
CP = 1
−
280
60
−
µA
µA
V
|IICPL
VCP
|
CP = 0
−
−
in-lock; Tamb = 25 °C
T2 = 0; T1 = 1
−
1.95
−0.5
−
ILI(off)
off-state leakage current
−15
+15
nA
Tuning voltage output Vtune
ILO(off) leakage current when switched-off
Vo output voltage when the loop is closed
OS = 1; Vtune = 33 V
−
−
−
10
µA
OS = 0; T2 = 0; T1 = 0;
T0 = 1; RL = 27 kΩ;
Vtune = 33 V
0.2
32.7
V
3-wire bus timing (see Figs 6 and 7)
tHIGH
clock high time
data set-up time
data hold time
2
−
−
−
−
−
−
−
−
−
−
−
−
−
−
µs
µs
µs
µs
µs
µs
µs
tSU;DAT
tHD;DAT
2
2
tSU;ENSCL enable to clock set-up time
tHD;ENDAT enable to data hold time
10
2
tEN
enable between two transmissions
10
6
tHD;ENSCL enable to clock active edge hold time
1996 Sep 24
13
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizers
TSA5526; TSA5527
Fig.6 Timing diagram for 3-wire bus; SDA, SCL and CE.
Fig.7 Timing diagram for 3-wire bus; CE and SCL.
14
1996 Sep 24
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizers
TSA5526; TSA5527
Fig.8 Prescaler Smith chart of typical input impedance at pin 1.
Fig.9 Prescaler typical input sensitivity curve.
15
1996 Sep 24
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizers
TSA5526; TSA5527
INTERNAL PIN CONFIGURATION
V
internal
reference
voltage
CC1
V
V
ref
CC1
1
RF
16
XTAL
V
V
EE
EE
V
CC1
2
V
EE
15
3
V
CE
CC1
4
V
CC2
V
EE
to address
selection
V
CC2
V
CC1
5
14
BS4
SDA
V
EE
ACK
2
V
(I C BUS)
EE
V
CC1
V
CC2
13
SCL
TSA5526
TSA5527
6
V
EE
BS3
V
CC1
command
12
LOCK/ADC
V
EE
V
V
CC2
EE
V
CC1
7
11
BS2
SW
V
V
EE
10
tune
V
EE
V
CC2
V
EE
V
CC1
8
BS1
down
up
9
CP
V
EE
V
EE
MGD635
Fig.10 Internal pin configuration.
16
1996 Sep 24
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizers
TSA5526; TSA5527
APPLICATION INFORMATION
Tuning amplifier
Crystal oscillator
The crystal oscillator uses a 4 MHz crystal connected in
series with an 18 pF capacitor thereby operating in the
series resonance mode. Connecting the oscillator to the
supply voltage is preferred but it can, however, also be
connected to ground.
The tuning amplifier is capable of driving the varicap
voltage without an external transistor. The tuning voltage
output must be connected to an external load of 27 kΩ
which is connected to the tuning voltage supply rail.
Figs 11 and 12 show a possible loop filter. The component
values depend on the oscillator characteristics and the
selected reference frequency.
Examples of I2C-bus sequences (SW = LOW)
Tables 10 to 14 show the various sequences where fosc = 100 MHz, BS4 = ON, ICP = 280 µA, N = 512, fxtal = 4 MHz,
S = START, A = acknowledge and P = STOP. The sequence is as follows:
START + address byte + divider byte 1 + divider byte 2 + control byte + band switch byte + STOP.
For the complete sequence see Table 10 (sequence 1) or Table 11 (sequence 2).
Table 10 Complete sequence 1
S
C2
A
06
A
A
40
08
A
A
CE
06
A
A
08
40
A
A
P
P
Table 11 Complete sequence 2
C2
S
A
CE
Table 12 Divider bytes only sequence
C2
S
A
06
A
A
40
08
A
A
P
P
Table 13 Control and band switch bytes only sequence
C2 CE
S
A
Table 14 Control byte only sequence
C2
S
A
CE
A
P
P
Other sequences are not allowed in the write mode.
Table 15 One status byte acquisition
S
C3
A
XX(1)
X(2)
Notes
1. XX = the read status byte.
2. X = no acknowledge from the master means end of sequence.
1996 Sep 24
17
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizers
TSA5526; TSA5527
Table 16 Two status byte acquisition
S
C3
A
XX(1)
A
XX(1)
X(2)
P
Notes
1. XX = the read status byte.
2. X = no acknowledge from the master means end of sequence.
Other I2C-bus addresses may be selected by applying an appropriate voltage to the CE input.
Examples of 3-wire bus sequences (TSA5526; SW = OPEN)
Table 17 18-bit sequence (fosc = 800 MHz, BS4 = ON)
1
0
0
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
The reference divider is automatically set to 512 unless RSB has been programmed to 0 during a 27-bit sequence
(see Table 19).
Table 18 19-bit sequence (fosc = 650 MHz, BS3 = ON)
0
1
0
0
1
0
1
0
0
0
1
0
1
0
0
0
0
0
0
The reference divider is automatically set to 1024 unless RSB has been programmed to 0 during a 27-bit sequence
(see Table 19).
Table 19 27-bit sequence (fosc = 750 MHz, BS1 = ON, N = 640, Icp = 60 µA, no test function)
0
0
0
1
0
1
1
1
0
1
0
1
0
0
1
1
1
0
0
0
1
0
0
0
1
0
0
0
0
Table 20 19-bit sequence
0
0
0
1
0
1
0
1
1
0
1
1
1
0
0
0
0
This sequence will program fosc to 600 MHz in 50 kHz steps. ICP remains at 60 µA.
Table 21 18-bit sequence
0
0
0
1
1
0
1
1
1
0
1
1
1
0
0
0
0
0
This sequence will program fosc to 600 MHz in 50 kHz steps. ICP remains at 60 µA.
Table 22 27-bit sequence (fosc = 650 MHz, BS1 = ON)
0
0
0
1
1
0
1
0
0
0
1
0
1
0
0
0
0
0
0
1
1
0
0
1
0
1
0
This sequence sets RSA to 0, RSB to 1 and CP to 1. After this sequence ICP = 280 µA, N = 1024 (19-bit transmission)
and N = 512 (18-bit transmission), RSB = 1.
1996 Sep 24
18
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizers
TSA5526; TSA5527
Example of 3-wire bus sequence (TSA5527; SW = OPEN)
Table 23 19-bit sequence (fosc = 700 MHz, BS3 = ON)
0
1
0
0
0
1
1
0
1
1
0
1
0
1
1
0
0
0
0
N = 640 unless RSB has been programmed to 0 during a 27-bit sequence.
22 kΩ
V
tune
33
nF
27
kΩ
2.2 nF
33 V
100 nF
CP
V
BS1
BS2
BS3
BS4
SWITCH
HIGH
MID
22 kΩ
tune
SW
LOCK
LOCK
LOW
TSA552X
V
SCL
SDA
CE
12 V
(2)
SCL
SDA
AS
CC2
V
10 nF
CC1
V
EE
RF
XTAL
RF
1 nF
5 V
MLC887
(1)
4 MHz
18 pF
(1) Connection to ground is also allowed.
(2) Capacitor prevents parasitic oscillation on the VCC2 line.
Fig.11 Typical I2C-bus application.
1996 Sep 24
19
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizers
TSA5526; TSA5527
22 kΩ
V
tune
33
nF
27
kΩ
2.2 nF
100 nF
33 V
CP
V
BS1
BS2
BS3
BS4
SWITCH
HIGH
MID
22 kΩ
tune
SW
LOCK
CLOCK
DATA
LOCK
LOW
12 V
TSA552X
V
SCL
SDA
CE
CC2
(2)
V
10 nF
CC1
V
ENABLE
EE
RF
XTAL
RF
1 nF
5 V
MLC888
(1)
4 MHz
18 pF
(1) Connection to ground is also allowed.
(2) Capacitor prevents parasitic oscillation on the VCC2 line.
Fig.12 Typical 3-wire bus application.
1996 Sep 24
20
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizers
TSA5526; TSA5527
PACKAGE OUTLINES
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
H
v
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.050
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.0098 0.057
0.0039 0.049
0.019 0.0098 0.39
0.014 0.0075 0.38
0.16
0.15
0.24
0.23
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
91-08-13
95-01-23
SOT109-1
076E07S
MS-012AC
1996 Sep 24
21
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizers
TSA5526; TSA5527
SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm
SOT369-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
10o
0o
0.15
0.00
1.4
1.2
0.32
0.20
0.25
0.13
5.30
5.10
4.5
4.3
6.6
6.2
0.75
0.45
0.65
0.45
0.48
0.18
mm
1.0
1.5
0.65
0.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
94-04-20
95-02-04
SOT369-1
1996 Sep 24
22
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizers
TSA5526; TSA5527
SOLDERING
Introduction
Wave soldering
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
• The package footprint must incorporate solder thieves at
the downstream end.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering
Reflow soldering techniques are suitable for all SO
packages.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
1996 Sep 24
23
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizers
TSA5526; TSA5527
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1996 Sep 24
24
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizers
TSA5526; TSA5527
NOTES
1996 Sep 24
25
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizers
TSA5526; TSA5527
NOTES
1996 Sep 24
26
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizers
TSA5526; TSA5527
NOTES
1996 Sep 24
27
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Middle East: see Italy
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Internet: http://www.semiconductors.philips.com
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1996
SCA51
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
537021/50/02/pp28
Date of release: 1996 Sep 24
Document order number: 9397 750 01258
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