Typenumber [NXP]
Real-Time Clock (RTC) and calendar; 实时时钟（RTC）和日历
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| 厂家： | 
NXP |
| 描述： | Real-Time Clock (RTC) and calendar |
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PCF8523
Real-Time Clock (RTC) and calendar
Rev. 4 — 5 July 2012
Product data sheet
1. General description
The PCF8523 is a CMOS1 Real-Time Clock (RTC) and calendar optimized for low power
consumption. Data is transferred serially via an I2C-bus with a maximum data rate of
1000 kbit/s. Alarm and timer functions are available with the possibility to generate a
wake-up signal on an interrupt pin. An offset register allows fine-tuning of the clock. The
PCF8523 has a backup battery switch-over circuit, which detects power failures and
automatically switches to the battery supply when a power failure occurs.
2. Features and benefits
Provides year, month, day, weekday, hours, minutes, and seconds based on a
32.768 kHz quartz crystal
Resolution: seconds to years
Clock operating voltage: 1.0 V to 5.5 V
Low backup current: typical 150 nA at VDD = 3.0 V and Tamb = 25 C
2 line bidirectional 1 MHz Fast-mode Plus (Fm+) I2C interface, read D1h, write D0h2
Battery backup input pin and switch-over circuit
Freely programmable timer and alarm with interrupt capability
Selectable integrated oscillator load capacitors for CL = 7 pF or CL = 12.5 pF
Internal Power-On Reset (POR)
Open-drain interrupt or clock output pins
Programmable offset register for frequency adjustment
3. Applications
Time keeping application
Battery powered devices
Metering
1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 20.
2. Devices with other I2C-bus slave addresses can be produced on request.
PCF8523
NXP Semiconductors
Real-Time Clock (RTC) and calendar
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
SO8
Description
Version
PCF8523T
plastic small outline package; 8 leads;
body width 3.9 mm
SOT96-1
PCF8523TK
HVSON8
plastic thermal enhanced very thin small outline
package; no leads; 8 terminals;
body 4 4 0.85 mm
SOT909-1
PCF8523TS
PCF8523U
TSSOP14 plastic thin shrink small outline package; 14 leads; SOT402-1
body width 4.4 mm
bare die
12 bumps (6-6)
PCF8523U
4.1 Ordering options
Table 2.
Ordering options
Type number
IC
Sales item
Bump type
Delivery form
revision (12NC)
PCF8523T/1
PCF8523TK/1
PCF8523TS/1
1
1
1
935293581118
-
tape and reel, 13 inch
tape and reel, 13 inch
tube
935293573118
935291196112
935291196118
935293887005
-
-
-
tape and reel, 13 inch
PCF8523U/12AA/1
1
soft gold bumps[1]
sawn wafer on Film Frame Carrier (FFC)
[1] Bump hardness see Table 53.
Table 3.
PCF8523U wafer information
Type number
PCF8523U/12AA/1
Wafer thickness
Wafer diameter
6 inch
FFC for wafer size
Marking of bad die
200 m
8 inch
wafer mapping
5. Marking
Table 4.
Marking codes
Type number
PCF8523T/1
Marking code
8523T
PCF8523TK/1
PCF8523TS/1
PCF8523U/12AA/1
8523
8523TS
PC8523-1
PCF8523
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 5 July 2012
2 of 74
PCF8523
NXP Semiconductors
Real-Time Clock (RTC) and calendar
6. Block diagram
OSCI
C
CLKOUT
OSCILLATOR
32.768 kHz
OSCI
DIVIDER
CLOCK OUT
OSCO
C
OSCO
&
INT1/CLKOUT
V
DD
BATTERY
BACKUP
SWITCH-OVER
CIRCUTRY
CLOCK
CALIBRATION
OFFSET
INTERRUPT
V
BAT
V
SS
SYSTEM
CONTROL
POWER-ON
RESET
REAL-TIME
CLOCK
2
I C-BUS
SDA
SCL
INTERFACE
ALARM
TIMER
INT2
PCF8523
013aaa305
Fig 1. Block diagram of PCF8523
PCF8523
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 5 July 2012
3 of 74
PCF8523
NXP Semiconductors
Real-Time Clock (RTC) and calendar
7. Pinning information
7.1 Pinning
1
2
3
4
8
7
6
5
OSCI
V
DD
OSCO
INT1/CLKOUT
SCL
PCF8523T
V
BAT
V
SS
SDA
013aaa306
Top view. For mechanical details, see Figure 37 on page 54.
Fig 2. Pin configuration for SO8 (PCF8523T)
terminal 1
index area
OSCI
1
2
3
4
8
7
6
5
V
DD
OSCO
INT1/CLKOUT
SCL
PCF8523TK
V
BAT
V
SS
SDA
013aaa308
Transparent top view
For mechanical details, see Figure 38 on page 55.
Fig 3. Pin configuration for HVSON8 (PCF8523TK)
1
2
3
4
5
6
7
14
13
12
11
10
9
OSCI
OSCO
n.c.
V
DD
INT1/CLKOUT
n.c.
V
BAT
PCF8523TS
SCL
V
SS
SDA
n.c.
n.c.
INT2
8
CLKOUT
013aaa307
Top view. For mechanical details, see Figure 39 on page 56.
Fig 4. Pin configuration for TSSOP14 (PCF8523TS)
PCF8523
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 5 July 2012
4 of 74
PCF8523
NXP Semiconductors
Real-Time Clock (RTC) and calendar
OSCI
2
3
1
V
DD
12
11
INT1/CLKOUT
n.c.
OSCO
PCF8523U
10
9
SCL
V
BAT
4
V
5
6
SS
SDA
n.c.
INT2
7
CLKOUT
8
013aaa317
Viewed from active side. For mechanical details, see Figure 40 on page 57.
Fig 5. Pin configuration for PCF8523U
7.2 Pin description
Table 5.
Symbol
Pin description
Pin
Type
Description
SO8
HVSON8
TSSOP14
PCF8523U
(PCF8523T)
(PCF8523TK) (PCF8523TS)
OSCI
OSCO
n.c.
1
2
-
1
2
-
1
2
input
output
-
oscillator input;
high-impedance node[1]
2
3
oscillator output;
high-impedance node[1]
3, 6, 9, 12[2]
6 and 11[2]
not connected; do not connect
and do not use it as feed through
VBAT
VSS
3
4
-
3
4[3]
4
5
7
4
5[4]
supply
supply
output
battery supply voltage
ground supply voltage
INT2
-
7
interrupt 2 (open-drain, active
LOW)
CLKOUT
SDA
-
-
8
8
output
clock output (open-drain)
5
6
5
6
7
10
11
13
9
input/output serial data input/output
SCL
10
12
input
serial clock input
INT1/CLKOUT 7
output
interrupt 1/clock output
(open-drain)
VDD
8
8
14
1
supply
supply voltage
[1] Wire length between quartz and package should be minimized.
[2] For manufacturing tests only; do not connect it and do not use it.
[3] The die paddle (exposed pad) is connected to VSS and should be electrically isolated.
[4] The substrate (rear side of the die) is connected to VSS and should be electrically isolated.
PCF8523
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 5 July 2012
5 of 74
PCF8523
NXP Semiconductors
Real-Time Clock (RTC) and calendar
8. Functional description
The PCF8523 contains:
• 20 8-bit registers with an auto-incrementing address register
• An on-chip 32.768 kHz oscillator with two integrated load capacitors
• A frequency divider, which provides the source clock for the Real-Time Clock (RTC)
• A programmable clock output
• A 1 Mbit/s I2C-bus interface
• An offset register, which allows fine-tuning of the clock
All 20 registers are designed as addressable 8-bit registers although not all bits are
implemented.
• The first three registers (memory address 00h, 01h, and 02h) are used as control and
status registers
• The addresses 03h through 09h are used as counters for the clock function (seconds
up to years)
• Addresses 0Ah through 0Dh define the alarm condition
• Address 0Eh defines the offset calibration
• Address 0Fh defines the clock-out mode and the addresses 10h and 12h the timer
mode
• Addresses 11h and 13h are used for the timers
The registers Seconds, Minutes, Hours, Days, Weekdays, Months, and Years are all
coded in Binary Coded Decimal (BCD) format. Other registers are either bit-wise or
standard binary. When one of the RTC registers is read, the contents of all counters are
frozen. Therefore, faulty reading of the clock and calendar during a carry condition is
prevented.
The PCF8523 has a battery backup input pin and battery switch-over circuit. The battery
switch-over circuit monitors the main power supply and switches automatically to the
backup battery when a power failure condition is detected. Accurate timekeeping is
maintained even when the main power supply is interrupted.
A battery low detection circuit monitors the status of the battery. When the battery voltage
goes below a certain threshold value, a flag is set to indicate that the battery must be
replaced soon. This ensures the integrity of the data during periods of battery backup.
PCF8523
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 5 July 2012
6 of 74
PCF8523
NXP Semiconductors
Real-Time Clock (RTC) and calendar
8.1 Registers overview
The 20 registers of the PCF8523 are auto-incrementing after each read or write data byte
up to register 13h. After register 13h, the auto-incrementing will wrap around to address
00h (see Figure 6).
address register
00h
01h
02h
03h
...
auto-increment
11h
12h
13h
wrap around
013aaa309
Fig 6. Auto-incrementing of the registers
Table 6.
Registers overview
Bit positions labeled as - are not implemented and will return a 0 when read. Bit T must always be written with logic 0.
Address Register name
Bit
7
6
5
4
3
2
1
0
Control registers
00h
01h
02h
Control_1
Control_2
Control_3
CAP_SEL T
STOP
CTBF
SR
SF
-
12_24
AF
SIE
AIE
CIE
WTAF
CTAF
WTAIE
BLF
CTAIE
BSIE
CTBIE
BLIE
PM[2:0]
BSF
Time and date registers
03h
04h
05h
Seconds
Minutes
Hours
OS
SECONDS (0 to 59)
MINUTES (0 to 59)
-
-
-
AMPM
HOURS (1 to 12 in 12 hour mode)
HOURS (0 to 23 in 24 hour mode)
DAYS (1 to 31)
06h
07h
08h
09h
Days
-
-
-
-
-
-
Weekdays
Months
Years
-
-
-
-
WEEKDAYS (0 to 6)
MONTHS (1 to 12)
YEARS (0 to 99)
Alarm registers
0Ah
0Bh
Minute_alarm
AE_M
AE_H
MINUTE_ALARM (0 to 59)
Hour_alarm
-
-
-
-
AMPM
HOUR_ALARM (1 to 12 in 12 hour mode)
HOUR_ALARM (0 to 23 in 24 hour mode)
DAY_ALARM (1 to 31)
0Ch
0Dh
Day_alarm
AE_D
AE_W
Weekday_alarm
-
-
-
WEEKDAY_ALARM (0 to 6)
Offset register
0Eh
Offset
MODE
OFFSET[6:0]
PCF8523
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 5 July 2012
7 of 74
PCF8523
NXP Semiconductors
Real-Time Clock (RTC) and calendar
Table 6.
Registers overview …continued
Bit positions labeled as - are not implemented and will return a 0 when read. Bit T must always be written with logic 0.
Address Register name
Bit
7
6
5
4
3
2
1
0
CLOCKOUT and timer registers
0Fh
10h
11h
12h
13h
Tmr_CLKOUT_ctrl
Tmr_A_freq_ctrl
Tmr_A_reg
TAM
-
TBM
-
COF[2:0]
-
TAC[1:0]
TAQ[2:0]
TBC
-
-
-
TIMER_A_VALUE[7:0]
TBW[2:0]
TIMER_B_VALUE[7:0]
Tmr_B_freq_ctrl
Tmr_B_reg
-
TBQ[2:0]
PCF8523
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 5 July 2012
8 of 74
PCF8523
NXP Semiconductors
Real-Time Clock (RTC) and calendar
8.2 Control and status registers
8.2.1 Register Control_1
Table 7.
Control_1 - control and status register 1 (address 00h) bit description
Bit
Symbol
Value
Description
7
CAP_SEL
internal oscillator capacitor selection for quartz
crystals with a corresponding load capacitance
0[1]
1
7 pF
12.5 pF
6
5
T
0[1][2]
0[1]
1
unused
STOP
RTC time circuits running
RTC time circuits frozen;
RTC divider chain flip-flops are
asynchronously set logic 0;
CLKOUT at 32.768 kHz, 16.384 kHz, or
8.192 kHz is still available
4
3
2
1
0
SR
0[1][3]
1
0[1]
no software reset
initiate software reset
12_24
SIE
24 hour mode is selected
12 hour mode is selected
second interrupt disabled
second interrupt enabled
alarm interrupt disabled
alarm interrupt enabled
no correction interrupt generated
1
0[1]
1
0[1]
AIE
1
CIE
0[1]
1
interrupt pulses are generated at every
correction cycle (see Section 8.8)
[1] Default value.
[2] Must always be written with logic 0.
[3] For a software reset, 01011000 (58h) must be sent to register Control_1 (see Section 8.3). Bit SR always
returns 0 when read.
PCF8523
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 5 July 2012
9 of 74
PCF8523
NXP Semiconductors
Real-Time Clock (RTC) and calendar
8.2.2 Register Control_2
Table 8.
Control_2 - control and status register 2 (address 01h) bit description
Bit
Symbol
Value
0[1]
1
Description
7
WTAF
no watchdog timer A interrupt generated
flag set when watchdog timer A interrupt
generated; flag is read-only and cleared by
reading register Control_2
6
5
CTAF
CTBF
0[1]
1
no countdown timer A interrupt generated
flag set when countdown timer A interrupt
generated; flag must be cleared to clear
interrupt
0[1]
1
no countdown timer B interrupt generated
flag set when countdown timer B interrupt
generated; flag must be cleared to clear
interrupt
4
3
SF
AF
0[1]
1
no second interrupt generated
flag set when second interrupt generated; flag
must be cleared to clear interrupt
0[1]
1
no alarm interrupt generated
flag set when alarm triggered; flag must be
cleared to clear interrupt
2
1
0
WTAIE
CTAIE
CTBIE
0[1]
1
0[1]
watchdog timer A interrupt is disabled
watchdog timer A interrupt is enabled
countdown timer A interrupt is disabled
countdown timer A interrupt is enabled
countdown timer B interrupt is disabled
countdown timer B interrupt is enabled
1
0[1]
1
[1] Default value.
PCF8523
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 5 July 2012
10 of 74
PCF8523
NXP Semiconductors
Real-Time Clock (RTC) and calendar
8.2.3 Register Control_3
Table 9.
Bit
Control_3 - control and status register 3 (address 02h) bit description
Symbol Value Description
7 to 5 PM[2:0]
see Table 11[1] battery switch-over and battery low detection
control
4
3
-
-
unused
BSF
0[2]
no battery switch-over interrupt generated
1
flag set when battery switch-over occurs; flag
must be cleared to clear interrupt
2
1
BLF
0[2]
1
0[2]
battery status ok
battery status low; flag is read-only
BSIE
no interrupt generated from battery switch-over
flag, BSF
1
interrupt generated when BSF is set
0
BLIE
0[2]
no interrupt generated from battery low
flag, BLF
1
interrupt generated when BLF is set
[1] Default value is 111.
[2] Default value.
PCF8523
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 5 July 2012
11 of 74
PCF8523
NXP Semiconductors
8.3 Reset
Real-Time Clock (RTC) and calendar
A reset is automatically generated at power-on. A reset can also be initiated with the
software reset command. Software reset command means setting bits 6, 4, and 3 in
register Control_1 (00h) logic 1 and all other bits logic 0 by sending the bit sequence
01011000 (58h), see Figure 7.
slave address byte
R/W
0
address 00h
software reset 58h
SDA
SCL
s
1
1
0
1
0
0
0
A
0
0
0
0
0
0
0
0
A
0
1
0
1
1
0
0
0
A P/S
internal
reset signal
013aaa320
Fig 7. Software reset command
Table 10. Register reset values
Bits labeled X are undefined at power-on and unchanged by subsequent resets. Bits labeled - are
not implemented.
Address Register name
Bit
7
0
0
1
1
-
6
0
0
1
X
X
-
5
0
0
1
X
X
X
X
-
4
0
0
-
3
0
0
0
X
X
X
X
-
2
1
0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
Control_1
Control_2
Control_3
Seconds
0
0
0
0
0
0
0
0
0
X
X
X
X
-
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
0
Minutes
Hours
-
Days
-
-
Weekdays
Months
-
-
-
-
-
X
X
X
X
X
-
X
X
X
X
X
-
Years
X
1
1
1
1
0
0
-
X
X
-
X
X
X
X
-
Minute_alarm
Hour_alarm
Day_alarm
Weekday_alarm
Offset
-
-
0
0
-
0
0
-
0
0
-
0
0
-
Tmr_CLKOUT_ctrl
Tmr_A_freq_ctrl
Tmr_A_reg
Tmr_B_freq_ctrl
Tmr_B_reg
0
0
0
1
1
1
X
-
X
0
X
X
0
X
X
0
X
X
-
X
1
X
1
X
1
X
X
X
X
X
PCF8523
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 5 July 2012
12 of 74
PCF8523
NXP Semiconductors
Real-Time Clock (RTC) and calendar
After reset, the following mode is entered:
• 32.768 kHz CLKOUT active
• 24 hour mode is selected
• Register Offset is set logic 0
• No alarms set
• Timers disabled
• No interrupts enabled
• Battery switch-over is disabled
• Battery low detection is disabled
• 7 pF of internal oscillator capacitor selected
8.4 Interrupt function
Active low interrupt signals are available at pin INT1/CLKOUT and INT2. Pin
INT1/CLKOUT has both functions of INT1 and CLKOUT combined.
INT1 Interrupt output may be sourced from different places:
• Second timer
• Timer A
• Timer B
• Alarm
• Battery switch-over
• Battery low detection
• Clock offset correction pulse
INT2 interrupt output is sourced only from timer B:
The control bit TAM (register Tmr_CLKOUT_ctrl) is used to configure whether the
interrupts generated from the second interrupt timer and timer A are pulsed signals or a
permanently active signal. The control bit TBM (register Tmr_CLKOUT_ctrl) is used to
configure whether the interrupt generated from timer B is a pulsed signal or a permanently
active signal. All the other interrupt sources generate a permanently active interrupt
signal, which follows the status of the corresponding flags.
• The flags SF, CTAF, CTBF, AF, and BSF can be cleared by using the interface
• WTAF is read only. Reading of the register Control_2 (01h) automatically resets
WTAF (WTAF = 0) and clears the interrupt
• The flag BLF is read only. It is cleared automatically from the battery low detection
circuit when the battery is replaced
PCF8523
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 5 July 2012
13 of 74
PCF8523
NXP Semiconductors
Real-Time Clock (RTC) and calendar
to interface:
read SF
SF:
SIE
SIE
0
1
SECOND FLAG
SECONDS COUNTER
SET
CLEAR
PULSE
GENERATOR 1
TRIGGER
CLEAR
TAM
TAM
INT1
from interface:
clear SF
INT1/CLKOUT
to interface:
read CTAF
CTAF:
CLKOUT
CTAIE
COUNTDOWN
TIMER A FLAG
0
1
COUNTDOWN
COUNTER A
CLEAR
SET
TAC = 01
PULSE
ENABLE
GENERATOR 2
TRIGGER
CLEAR
from interface:
clear CTAF
to interface:
read WTAF
WTAF:
WATCH DOG
TIMER FLAG
TAM
0
1
WTAIE
WATCHDOG
COUNTER A
TAC = 10
CLEAR
SET
ENABLE
PULSE
GENERATOR 3
MCU loading
watchdog counter
or reading WTAF
CLEAR
TRIGGER
to interface:
CTBF:
TBM
read CTBF
COUNTDOWN
TIMER B FLAG
CTBIE
INT2
0
1
COUNTDOWN
COUNTER B
CLEAR
SET
TBC = 1
PULSE
ENABLE
GENERATOR 4
TRIGGER
CLEAR
from interface:
clear CTBF
to interface:
AIE
CIE
AF: ALARM
FLAG
CLEAR
read AF
set alarm
flag, AF
SET
from interface:
clear AF
PULSE
GENERATOR 5
CLEAR
offset circuit:
add/subtract pulse
SET
from interface:
clear CIE
to interface:
read BSF
BSIE
BLIE
BSF: BATTERY
FLAG
set battery
flag, BSF
SET
CLEAR
from interface:
clear BSF
to interface:
read BLF
BLF: BATTERY
LOW FLAG
set battery
low flag, BLF
SET
CLEAR
from battery
low detection
013aaa330
circuit: clear BLF
When SIE, CTAIE, WTAIE, CTBIE, AIE, CIE, BSIE, BLIE, and clock-out are disabled, then INT1 remains high-impedance.
When CTBIE is disabled, then INT2 remains high-impedance.
Fig 8. Interrupt block diagram
PCF8523
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 5 July 2012
14 of 74
PCF8523
NXP Semiconductors
Real-Time Clock (RTC) and calendar
8.5 Power management functions
The PCF8523 has two power supply pins:
• VDD - the main power supply input pin
• VBAT - the battery backup input pin
The PCF8523 has two power management functions implemented:
• Battery switch-over function
• Battery low detection function
The power management functions are controlled by the control bits PM[2:0] in register
Control_3 (02h):
Table 11. Power management function control bits
PM[2:0]
Function
000
battery switch-over function is enabled in standard mode;
battery low detection function is enabled
001
battery switch-over function is enabled in direct switching mode;
battery low detection function is enabled
010,011[1]
100
battery switch-over function is disabled - only one power supply (VDD);
battery low detection function is enabled
battery switch-over function is enabled in standard mode;
battery low detection function is disabled
101
battery switch-over function is enabled in direct switching mode;
battery low detection function is disabled
110
not allowed
111[2][3]
battery switch-over function is disabled - only one power supply (VDD);
battery low detection function is disabled
[1] When the battery switch-over function is disabled, the PCF8523 works only with the power supply VDD
.
[2] When the battery switch-over function is disabled, the PCF8523 works only with the power supply VDD
VBAT must be put to ground and the battery low detection function is disabled.
.
[3] Default value.
8.5.1 Standby mode
When the device is first powered up from the battery (VBAT) but without a main supply
(VDD), the PCF8523 automatically enters the standby mode. In standby mode, the
PCF8523 does not draw any power from the backup battery until the device is powered up
from the main power supply VDD. Thereafter, the device switches over to battery backup
mode whenever the main power supply VDD is lost.
It is also possible to enter into standby mode when the chip is already supplied by the
main power supply VDD and a backup battery is connected. To enter the standby mode,
the power management control bits PM[2:0] have to be set logic 111. Then the main
power supply VDD must be removed. As a result of it, the PCF8523 enters the standby
mode and does not draw any current from the backup battery before it is powered up
again from main supply VDD
.
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8.5.2 Battery switch-over function
The PCF8523 has a backup battery switch-over circuit. It monitors the main power supply
DD and switches automatically to the backup battery when a power failure condition is
V
detected.
One of two operation modes can be selected:
• Standard mode: the power failure condition happens when:
VDD < VBAT AND VDD < Vth(sw)bat
• Direct switching mode: the power failure condition happens when VDD < VBAT
.
Direct switching from VDD to VBAT without requiring VDD to drop below Vth(sw)bat
Vth(sw)bat is the battery switch threshold voltage. Typical value is 2.5 V.
Generation of interrupts from the battery switch-over is controlled via the BSIE bit (see
register Control_2). If BSIE is enabled, the INT1 follows the status of bit BLF (register
Control_3). Clearing BLF immediately clears INT1.
When a power failure condition occurs and the power supply switches to the battery, the
following sequence occurs:
1. The battery switch flag BSF (register Control_3) is set logic 1
2. An interrupt is generated if the control bit BSIE (register Control_3) is enabled
The battery switch flag BSF can be cleared by using the interface after the power supply
has switched to VDD. It must be cleared to clear the interrupt.
The interface is disabled in battery backup operation:
• Interface inputs are not recognized, preventing extraneous data being written to the
device
• Interface outputs are high-impedance
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8.5.2.1 Standard mode
If VDD > VBAT OR VDD > Vth(sw)bat, the internal power supply is VDD
.
If VDD < VBAT AND VDD < Vth(sw)bat, the internal power supply is VBAT
.
backup battery operation
V
DD
V
V
BBS
BBS
V
BAT
internal power supply (= V
)
BBS
V
th(sw)bat
(= 2.5 V)
V
(= 0 V)
DD
BSF
INT1
cleared via interface
013aaa321
Fig 9. Battery switch-over behavior in standard mode and with bit BSIE set logic 1
(enabled)
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8.5.2.2 Direct switching mode
If VDD > VBAT the internal power supply is VDD
.
If VDD < VBAT the internal power supply is VBAT
.
The direct switching mode is useful in systems where VDD is higher than VBAT at all times
(for example, VDD = 5 V, VBAT = 3.5 V). If the VDD and VBAT values are similar (for
example, VDD = 3.3 V, VBAT 3.0 V), the direct switching mode is not recommended. In
direct switching mode, the power consumption is reduced compared to the standard mode
because the monitoring of VDD and Vth(sw)bat is not performed.
backup battery operation
V
DD
V
V
BBS
BBS
V
BAT
internal power supply (= V
)
BBS
V
th(sw)bat
(= 2.5 V)
V
(= 0 V)
DD
BSF
INT1
cleared via interface
013aaa322
Fig 10. Battery switch-over behavior in direct switching mode and with bit BSIE set
logic 1 (enabled)
8.5.2.3 Battery switch-over disabled, only one power supply (VDD
)
When the battery switch-over function is disabled:
• The power supply is applied on the VDD pin
• The VBAT pin must be connected to ground
• The battery flag (BSF) is always logic 0
8.5.3 Battery low detection function
The PCF8523 has a battery low detection circuit, which monitors the status of the battery
VBAT
.
Generation of interrupts from the battery low detection is controlled via bit BLIE (register
Control_3). If BLIE is enabled, the INT1 follows the status of bit BLF (register Control_3).
When VBAT drops below the threshold value Vth(bat)low (typically 2.5 V), the BLF flag
(register Control_3) is set to indicate that the battery is low and that it must be replaced.
Monitoring of the battery voltage also occurs during battery operation.
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An unreliable battery does not ensure data integrity during periods of backup battery
operation.
When VBAT drops below the threshold value Vth(bat)low, the following sequence occurs (see
Figure 11):
1. The battery low flag BLF is set logic 1
2. An interrupt is generated if the control bit BLIE (register Control_3) is enabled. The
interrupt remains active until the battery is replaced (BLF set logic 0) or when bit BLIE
is disabled (BLIE set logic 0)
3. The flag BLF (register Control_3) remains logic 1 until the battery is replaced. BLF
cannot be cleared using the interface. It is cleared automatically by the battery low
detection circuit when the battery is replaced
V
= V
BBS
DD
internal power supply (= V
)
BBS
V
BAT
V
th(bat)low
(= 2.5 V)
V
BAT
BLF
INT1
013aaa323
Fig 11. Battery low detection behavior with bit BLIE set logic 1 (enabled)
8.6 Time and date registers
Most of these registers are coded in the Binary Coded Decimal (BCD) format. BCD is
used to simplify application use. An example is shown for the array SECONDS in
Table 13.
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8.6.1 Register Seconds
Table 12. Seconds - seconds and clock integrity status register (address 03h) bit
description
Bit
Symbol
OS
Value
Place value Description
7
0
1[1]
-
-
clock integrity is guaranteed
clock integrity is not guaranteed;
oscillator has stopped or been
interrupted
6 to 4 SECONDS
3 to 0
0 to 5
0 to 9
ten’s place actual seconds coded in BCD
format
unit place
[1] Start-up value.
Table 13. SECONDS coded in BCD format
Seconds value in Upper-digit (ten’s place)
Digit (unit place)
Bit
decimal
Bit
6
0
0
0
:
5
0
0
0
:
4
0
0
0
:
3
0
0
0
:
2
0
0
0
:
1
0
0
1
:
0
0
1
0
:
00
01
02
:
09
10
:
0
0
:
0
0
:
0
1
:
1
0
:
0
0
:
0
0
:
1
0
:
58
59
1
1
0
0
1
1
1
1
0
0
0
0
0
1
8.6.1.1 Oscillator STOP flag
The OS flag is set whenever the oscillator is stopped (see Figure 12). The flag remains
set until cleared by using the interface. When the oscillator is not running, then the OS flag
cannot be cleared. This method can be used to monitor the oscillator.
The oscillator may be stopped, for example, by grounding one of the oscillator pins, OSCI
or OSCO. The oscillator is also considered to be stopped during the time between
power-on and stable crystal resonance. This time may be in a range of 200 ms to 2 s,
depending on crystal type, temperature, and supply voltage. At power-on, the OS flag is
always set.
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OS = 1 and flag can not be cleared
OS = 1 and flag can be cleared
V
DD
oscillation
OS flag
OS flag set when
oscillation stops
OS flag cleared
by software
oscillation now stable
t
013aaa319
Fig 12. OS flag
8.6.2 Register Minutes
Table 14. Minutes - minutes register (address 04h) bit description
Bit
Symbol
Value
-
Place value Description
- unused
7
-
6 to 4 MINUTES
3 to 0
0 to 5
0 to 9
ten’s place actual minutes coded in BCD
format
unit place
8.6.3 Register Hours
Table 15. Hours - hours register (address 05h) bit description
Bit
Symbol
Value
Place value Description
7 to 6
-
-
-
unused
12 hour mode[1]
5
AMPM
0
-
-
indicates AM
indicates PM
1
4
HOURS
0 to 1
0 to 9
ten’s place actual hours in 12 hour mode
coded in BCD format
3 to 0
unit place
24 hour mode[1]
5 to 4 HOURS
3 to 0
0 to 2
0 to 9
ten’s place actual hours in 24 hour mode
coded in BCD format
unit place
[1] Hour mode is set by bit 12_24 in register Control_1 (see Table 7).
8.6.4 Register Days
Table 16. Days - days register (address 06h) bit description
Bit
Symbol
Value
-
Place value Description
- unused
7 to 6
-
5 to 4 DAYS[1]
0 to 3
0 to 9
ten’s place actual day coded in BCD format
unit place
3 to 0
[1] If the year counter contains a value, which is exactly divisible by 4 (including the year 00), the PCF8523
compensates for leap years by adding a 29th day to February.
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Real-Time Clock (RTC) and calendar
8.6.5 Register Weekdays
Table 17. Weekdays - weekdays register (address 07h) bit description
Bit
Symbol
Value
-
Description
7 to 3
-
unused
2 to 0 WEEKDAYS
0 to 6
actual weekday, values see Table 18
Table 18. Weekday assignments
Day[1]
Bit
2
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
Sunday
0
Monday
Tuesday
Wednesday
Thursday
Friday
0
0
0
1
1
Saturday
1
[1] Definition may be reassigned by the user.
8.6.6 Register Months
Table 19. Months - months register (address 08h) bit description
Bit
Symbol
-
Value
-
Place value Description
- unused
7 to 5
4
MONTHS
0 to 1
0 to 9
ten’s place actual month coded in BCD
format; assignments see Table 20
3 to 0
unit place
Table 20. Month assignments in BCD format
Month
Upper-digit
(ten’s place)
Digit (unit place)
Bit
4
0
0
0
0
0
0
0
0
0
1
1
1
Bit
3
0
0
0
0
0
0
0
1
1
0
0
0
2
0
0
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
January
February
March
April
May
June
July
August
September
October
November
December
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8.6.7 Register Years
Table 21. Years - years register (09h) bit description
Bit
Symbol
Value
0 to 9
0 to 9
Place value Description
ten’s place actual year coded in BCD format
unit place
7 to 4 YEARS
3 to 0
8.6.8 Data flow of the time function
Figure 13 shows the data flow and data dependencies starting from the 1 Hz clock tick.
1 Hz tick
SECONDS
MINUTES
12/24 hour mode
HOURS
DAYS
LEAP YEAR
CALCULATION
WEEKDAYS
MONTHS
YEARS
013aaa324
Fig 13. Data flow diagram of the time function
During read/write operations, the time counting circuits (memory locations 03h through
09h) are blocked.
The blocking prevents:
• Faulty reading of the clock and calendar during a carry condition
• Incrementing the time registers during the read cycle
After the read/write-access is completed, the time circuit is released again and any
pending request to increment the time counters that occurred during the read/write access
is serviced. A maximum of one request can be stored; therefore, all accesses must be
completed within 1 second (see Figure 14).
t < 1 s
SLAVE ADDRESS
DATA
DATA
STOP
START
013aaa215
Fig 14. Access time for read/write operations
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Because of this method, it is very important to make a read or write access in one go, that
is, setting or reading seconds through to years should be made in one single access.
Failing to comply with this method could result in the time becoming corrupted.
As an example, if the time (seconds through to hours) is set in one access and then in a
second access the date is set, it is possible that the time will increment between the two
accesses. A similar problem exists when reading. A rollover may occur between reads
thus giving the minutes from one moment and the hours from the next.
8.7 Alarm registers
The registers at addresses 0Ah through 0Dh contain the alarm information.
8.7.1 Register Minute_alarm
Table 22. Minute_alarm - minute alarm register (address 0Ah) bit description
Bit
Symbol
Value
Place value Description
7
AE_M
0
1[1]
-
-
minute alarm is enabled
minute alarm is disabled
6 to 4 MINUTE_ALARM
3 to 0
0 to 5
0 to 9
ten’s place minute alarm information coded in
BCD format
unit place
[1] Default value.
8.7.2 Register Hour_alarm
Table 23. Hour_alarm - hour alarm register (address 0Bh) bit description
Bit
Symbol
Value
Place value Description
7
AE_H
0
1[1]
-
-
-
hour alarm is enabled
hour alarm is disabled
unused
6
-
-
12 hour mode[2]
5
AMPM
0
-
-
indicates AM
indicates PM
1
4
HOUR_ALARM
0 to 1
0 to 9
ten’s place hour alarm information in 12 hour
mode coded in BCD format
3 to 0
unit place
24 hour mode[2]
5 to 4 HOURS
3 to 0
0 to 2
0 to 9
ten’s place hour alarm information in 24 hour
mode coded in BCD format
unit place
[1] Default value.
[2] Hour mode is set by bit 12_24 in register Control_1 (see Table 7).
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8.7.3 Register Day_alarm
Table 24. Day_alarm - day alarm register (address 0Ch) bit description
Bit
Symbol
Value
Place value Description
7
AE_D
0
1[1]
-
-
-
day alarm is enabled
day alarm is disabled
unused
6
-
-
5 to 4 DAY_ALARM
3 to 0
0 to 3
0 to 9
ten’s place day alarm information coded in
BCD format
unit place
[1] Default value.
8.7.4 Register Weekday_alarm
Table 25. Weekday_alarm - weekday alarm register (address 0Dh) bit description
Bit
Symbol
Value
Description
7
AE_W
0
weekday alarm is enabled
weekday alarm is disabled
unused
1[1]
-
6 to 3
-
2 to 0 WEEKDAY_ALARM
[1] Default value.
0 to 6
weekday alarm information
8.7.5 Alarm flag
check now signal
MINUTE ALARM
MINUTE TIME
example
AE_M
AE_M = 1
=
=
=
=
1
0
AE_H
AE_D
AE_W
HOUR ALARM
HOUR TIME
(1)
set alarm flag AF
DAY ALARM
DAY TIME
WEEKDAY ALARM
WEEKDAY TIME
013aaa088
(1) Only when all enabled alarm settings are matching.
It is only on increment to a matched case that the alarm flag is set, see Section 8.7.5.
Fig 15. Alarm function block diagram
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When one or several alarm registers are loaded with a valid minute, hour, day, or weekday
value and its corresponding alarm enable bit (AE_x) is logic 0, then that information is
compared with the current minute, hour, day, and weekday value. When all enabled
comparisons first match, the alarm flag, AF (register Control_2), is set logic 1.
The generation of interrupts from the alarm function is controlled via bit AIE (register
Control_1). If bit AIE is enabled, then the INT1 pin follows the condition of bit AF. AF
remains set until cleared by the interface. Once AF has been cleared, it will only be set
again when the time increments to match the alarm condition once more. Alarm registers,
which have their AE_x bit logic 1 are ignored. The generation of interrupts from the alarm
function is described more detailed in Section 8.4.
Table 26 and Table 27 show an example for clearing bit AF. Clearing the flag is made by a
write command, therefore bits 2, 1, and 0 must be re-written with their previous values.
Repeatedly re-writing these bits has no influence on the functional behavior.
minutes counter
minute alarm
AF
44
45
45
46
INT when AIE = 1
001aaf903
Example where only the minute alarm is used and no other interrupts are enabled.
Fig 16. Alarm flag timing
To prevent the timer flags being overwritten while clearing bit AF, logic AND is performed
during a write access. A flag is cleared by writing logic 0 while a flag is not cleared by
writing logic 1. Writing logic 1 results in the flag value remaining unchanged.
Table 26. Flag location in register Control_2
Register
Bit
7
6
5
4
3
2
1
0
Control_2
WTAF
CTAF
CTBF
SF
AF
-
-
-
Table 27 shows what instruction must be sent to clear bit AF. In this example, bit CTAF,
CTBF, and bit SF are unaffected.
Table 27. Example to clear only AF (bit 3)
Register
Bit[1]
7
6
5
4
3
2
1
0
Control_2
0
1
1
1
0
-
-
-
[1] The bits labeled as - have to be rewritten with the previous values.
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8.7.6 Alarm interrupts
Generation of interrupts from the alarm function is controlled via the bit AIE (register
Control_1). If AIE is enabled, the INT1 follows the status of bit AF (register Control_2).
Clearing AF immediately clears INT1. No pulse generation is possible for alarm interrupts.
minute counter
minute alarm
AF
44
45
45
INT1
SCL
instruction
CLEAR INSTRUCTION
013aaa335
Example where only the minute alarm is used and no other interrupts are enabled.
Fig 17. AF timing
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8.8 Register Offset
The PCF8523 incorporates an offset register (address 0Eh), which can be used to
implement several functions, like:
• Aging adjustment
• Temperature compensation
• Accuracy tuning
Table 28. Offset - offset register (address 0Eh) bit description
Bit
Symbol
Value
Description
7
MODE
0[1]
offset is made once every two hours
offset is made once every minute
offset value
1
6 to 0 OFFSET[6:0]
[1] Default value.
see Table 29
For MODE = 0, each LSB introduces an offset of 4.34 ppm. For MODE = 1, each LSB
introduces an offset of 4.069 ppm. The values of 4.34 ppm and 4.069 ppm are based on a
nominal 32.768 kHz clock. The offset value is coded in two’s complement giving a range
of +63 LSB to 64 LSB.
Table 29. Offset values
OFFSET[6:0]
Offset value in
decimal
Offset value in ppm
Every two hours
(MODE = 0)
Every minute
(MODE = 1)
0111111
0111110
:
+63
+62
:
+273.420
+269.080
:
+256.347
+252.278
:
0000010
0000001
0000000
1111111
1111110
:
+2
+1
0[1]
1
2
:
+8.680
+4.340
0[1]
+8.138
+4.069
0[1]
4.340
8.680
:
4.069
8.138
:
1000001
1000000
63
64
273.420
277.760
256.347
260.416
[1] Default mode.
The correction is made by adding or subtracting clock correction pulses, thereby changing
the period of a single second.
It is possible to monitor when correction pulses are applied. To enable correction interrupt
generation, bit CIE (register Control_1) has to be set logic 1. At every correction cycle a
1
⁄
4096 s pulse is generated on pin INTx. If multiple correction pulses are applied, a 1⁄4096
s
interrupt pulse is generated for each correction pulse applied.
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8.8.1 Correction when MODE = 0
The correction is triggered once per two hours and then correction pulses are applied
once per minute until the programmed correction values have been implemented.
Table 30. Correction pulses for MODE = 0
Correction value
Hour
Minute
Correction pulses on
INT1 per minute[1]
+1 or 1
+2 or 2
+3 or 3
:
02
02
02
:
00
1
1
1
:
00 and 01
00, 01, and 02
:
+59 or 59
+60 or 60
+61 or 61
02
02
02
03
02
03
02
03
02
03
00 to 58
00 to 59
00 to 59
00
1
1
1
1
1
1
1
1
1
1
+62 or 62
+63 or 63
64
00 to 59
00 and 01
00 to 59
00, 01, and 02
00 to 59
00, 01, 02, and 03
[1] The correction pulses on pin INT1 are 1
⁄64 s wide.
In MODE = 0, any timer or clock output using a frequency below 64 Hz is affected by the
clock correction (see Table 31).
Table 31. Effect of clock correction for MODE = 0
CLKOUT frequency (Hz) Effect of correction Timer source clock
frequency (Hz)
Effect of
correction
32768
16384
8192
4096
1024
32
no effect
no effect
no effect
no effect
no effect
affected
affected
4096
64
no effect
no effect
affected
affected
affected
-
1
1
⁄
60
1
⁄
3600
-
-
1
-
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8.8.2 Correction when MODE = 1
The correction is triggered once per minute and then correction pulses are applied once
per second up to a maximum of 60 pulses. When correction values greater than 60 pulses
are used, additional correction pulses are made in the 59th second.
Clock correction is made more frequently in MODE = 1; however, this can result in higher
power consumption.
Table 32. Correction pulses for MODE = 1
Correction value
Minute
Second
Correction pulses on
INT1 per second[1]
+1 or 1
+2 or 2
+3 or 3
:
02
02
02
:
00
1
1
1
:
00 and 01
00, 01, and 02
:
+59 or 59
+60 or 60
+61 or 61
02
02
02
02
02
02
02
02
02
02
00 to 58
00 to 59
00 to 58
59
1
1
1
2
1
2
1
4
1
5
+62 or 62
+63 or 63
64
00 to 58
59
00 to 58
59
00 to 58
59
[1] The correction pulses on pin INTx are 1⁄4096 s wide. For multiple pulses, they are repeated at an interval of
1
⁄2048 s.
In MODE = 1, any timer source clock using a frequency below 4.096 kHz is also affected
by the clock correction (see Table 33).
Table 33. Effect of clock correction for MODE = 1
CLKOUT frequency (Hz) Effect of correction Timer source clock
frequency (Hz)
Effect of
correction
32768
16384
8192
4096
1024
32
no effect
no effect
no effect
no effect
no effect
affected
affected
4096
64
no effect
affected
affected
affected
affected
-
1
1
⁄
60
1
⁄
3600
-
-
1
-
PCF8523
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Real-Time Clock (RTC) and calendar
8.8.3 Offset calibration workflow
The calibration offset has to be calculated based on the time. Figure 18 shows the
workflow how the offset register values can be calculated:
Example
Measure the frequency on pin CLKOUT:
f
32768.48 Hz
30.5171 µs
meas
Convert to time:
= 1 / f
t
meas
meas
Calculate the difference to the ideal
period of 1 / 32768.00:
0.000447 µs
14.6484 ppm
D
= 1 / 32768 - t
meas
meas
Calculate the ppm deviation compared
to the measured value:
E
= 1000000 × D
/ t
meas meas
ppm
Calculate the offset register value:
Mode = 0 (low power):
Offset value = E
/ 4.34
3.375
3.600
3 correction pulses
are needed
ppm
Mode = 1 (fast correction)
Offset value = E / 4.069
4 correction pulses
are needed
ppm
013aaa683
Fig 18. Offset calibration calculation workflow
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8.9 Timer function
The PCF8523 has three timers:
• Timer A can be used as a watchdog timer or a countdown timer (see Section 8.9.2). It
can be configured by using TAC[1:0] in the Tmr_CLKOUT_ctrl register (0Fh)
• Timer B can be used as a countdown timer (see Section 8.9.3). It can be configured
by using TBC in the Tmr_CLKOUT_ctrl register (0Fh)
• Second interrupt timer is used to generate an interrupt once per second (see
Section 8.9.4)
Timer A and timer B both have five selectable source clocks allowing for countdown
periods from less than 1 ms to 255 h. To control the timer functions and timer output, the
registers 01h, 0Fh, 10h, 11h, 12h, and 13h are used.
8.9.1 Timer registers
8.9.1.1 Register Tmr_CLKOUT_ctrl and clock output
Table 34. Tmr_CLKOUT_ctrl - timer and CLKOUT control register (address 0Fh) bit
description
Bit
Symbol
Value
Description
7
TAM
0[1]
permanent active interrupt for timer A and for
the second interrupt timer
1
pulsed interrupt for timer A and the second
interrupt timer
6
TBM
0[1]
permanent active interrupt for timer B
pulsed interrupt for timer B
1
5 to 3 COF[2:0]
2 to 1 TAC[1:0]
see Table 35
00[1] to 11
01
CLKOUT frequency selection
timer A is disabled
timer A is configured as countdown timer
if CTAIE (register Control_2) is set logic 1, the
interrupt is activated when the countdown
timed out
10
timer A is configured as watchdog timer
if WTAIE (register Control_2) is set logic 1,
the interrupt is activated when timed out
0
TBC
0[1]
1
timer B is disabled
timer B is enabled
if CTBIE (register Control_2) is set logic 1, the
interrupt is activated when the countdown
timed out
[1] Default value.
8.9.1.2 CLKOUT frequency selection
Clock output operation is controlled by the COF[2:0] in the Tmr_CLKOUT_ctrl register.
Frequencies of 32.768 kHz (default) down to 1 Hz can be generated (see Table 35) for
use as a system clock, microcontroller clock, input to a charge pump, or for calibration of
the oscillator.
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A programmable square wave is available at pin INT1/CLKOUT and pin CLKOUT, which
are both open-drain outputs. Pin INT1/CLKOUT has both functions of INT1 and CLKOUT
combined.
The duty cycle of the selected clock is not controlled but due to the nature of the clock
generation, all clock frequencies except 32.768 kHz have a duty cycle of 50 : 50.
The STOP bit function can also affect the CLKOUT signal, depending on the selected
frequency. When STOP is active, the INT1/CLKOUT and CLKOUT pins are
high-impedance for all frequencies except of 32.768 kHz, 16.384 kHz and 8.192 kHz. For
more details, see Section 8.10.
Table 35. CLKOUT frequency selection
COF[2:0] CLKOUT frequency (Hz)
Typical duty cycle[1]
60 : 40 to 40 : 60
50 : 50
Effect of STOP bit
no effect
000[2]
001
010
011
100
101
110
111
32768
16384
no effect
8192
50 : 50
no effect
4096
50 : 50
CLKOUT = high-Z
CLKOUT = high-Z
CLKOUT = high-Z
CLKOUT = high-Z
1024
50 : 50
50 : 50[3]
50 : 50[3]
32
1
CLKOUT disabled (high-Z)
[1] Duty cycle definition: % HIGH-level time : % LOW-level time.
[2] Default value.
[3] Clock frequencies may be affected by offset correction.
8.9.1.3 Register Tmr_A_freq_ctrl
Table 36. Tmr_A_freq_ctrl - timer A frequency control register (address 10h) bit
description
Bit
Symbol
Value
Description
7 to 3
-
-
unused
2 to 0 TAQ[2:0]
source clock for timer A (see Table 40)
000
001
010
011
4.096 kHz
64 Hz
1 Hz
1
⁄60 Hz
1
111[1]
110
⁄3600 Hz
100
[1] Default value.
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8.9.1.4 Register Tmr_A_reg
Table 37. Tmr_A_reg - timer A value register (address 11h) bit description
Bit Symbol Value Description
7 to 0 TIMER_A_VALUE[7:0] 00 to FF timer-period in seconds
n
timerperiod =
----------------------------------------------------------
sourceclockfrequency
where n is the countdown value
8.9.1.5 Register Tmr_B_freq_ctrl
Table 38. Tmr_B_freq_ctrl - timer B frequency control register (address 12h) bit
description
Bit
Symbol
Value
Description
7
-
-
unused
6 to 4 TBW[2:0]
low pulse width for pulsed timer B interrupt
000[1]
001
010
011
100
101
110
111
-
46.875 ms
62.500 ms
78.125 ms
93.750 ms
125.000 ms
156.250 ms
187.500 ms
218.750 ms
unused
3
-
2 to 0 TBQ[2:0]
source clock for timer B (see Table 40)
4.096 kHz
000
001
010
011
64 Hz
1 Hz
1
⁄60 Hz
1
111[1]
110
⁄3600 Hz
100
[1] Default value.
8.9.1.6 Register Tmr_B_reg
Table 39. Tmr_B_reg - timer B value register (address 13h) bit description
Bit
Symbol
Value
Description
7 to 0 TIMER_B_VALUE[7:0] 00 to FF
timer-period in seconds
n
timerperiod =
----------------------------------------------------------
sourceclockfrequency
where n is the countdown value
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Real-Time Clock (RTC) and calendar
8.9.1.7 Programmable timer characteristics
Table 40. Programmable timer characteristics
TAQ[2:0] Timer source
TBQ[2:0] clock frequency
Units Minimum
timer-period
(n = 1)
Units Maximum
timer-period
(n = 255)
Units
000
001
010
011
4.096
64
kHz
Hz
Hz
Hz
Hz
244
s
62.256
3.984
255
ms
s
15.625
ms
s
1
1
1
1
s
1
⁄
min
hour
255
min
hour
60
1
111
110
100
⁄
255
3600
8.9.2 Timer A
With the bit field TAC[1:0] in register Tmr_CLKOUT_ctrl (0Fh) Timer A can be configured
as a countdown timer (TAC[1:0] = 01) or watchdog timer (TAC[1:0] = 10).
8.9.2.1 Watchdog timer function
The 3 bits TAQ[2:0] in register Tmr_A_freq_ctrl (10h) determine one of the five source
clock frequencies for the watchdog timer: 4.096 kHz, 64 Hz, 1 Hz, 1⁄60 Hz or 1⁄3600 Hz (see
Table 36).
The generation of interrupts from the watchdog timer is controlled by using WTAIE bit
(register Control_2).
When configured as a watchdog timer (TAC[1:0] = 10), the 8-bit timer value in register
Tmr_A_reg (11h) determines the watchdog timer-period.
The watchdog timer counts down from value n in register Tmr_A_reg (11h). When the
counter reaches 1, the watchdog timer flag WTAF (register Control_2) is set logic 1 on the
next rising edge of the timer clock (see Figure 19). In that case:
• If WTAIE = 1, an interrupt will be generated
• If WTAIE = 0, no interrupt will be generated
The interrupt generated by the watchdog timer function of timer A may be generated as
pulsed signal or a permanentiy active signal. The TAM bit (register Tmr_CLKOUT_ctrl) is
used to control the interrupt generation mode.
The counter does not automatically reload. When loading the counter with any valid value
of n, except 0:
• The flag WTAF is reset (WTAF = 0)
• Interrupt is cleared
• The watchdog timer starts
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When loading the counter with 0:
• The flag WTAF is reset (WTAF = 0)
• Interrupt is cleared
• The watchdog timer stops
WTAF is read only. A read of the register Control_2 (01h) automatically resets WTAF
(WTAF = 0) and clears the interrupt.
MCU
watchdog
timer value
n = 1
n = 0
n
WTAF
INT1
013aaa327
TAC[1:0] = 10, WTAIE = 1, WTAF = 1, an interrupt is generated.
Fig 19. Watchdog activates an interrupt when timed out
8.9.2.2 Countdown timer function
When configured as a countdown timer (TAC[1:0] = 01), timer A counts down from the
software programmed 8-bit binary value n in register Tmr_A_reg (11h). When the counter
reaches 1, the following events occur on the next rising edge of the timer clock (see
Figure 20):
• The countdown timer flag CTAF (register Control_2) is set logic 1
• When the interrupt generation is enabled (CTAIE = 1), an interrupt signal on INT1 is
generated
• The counter automatically reloads
• The next timer-period starts
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Real-Time Clock (RTC) and calendar
countdown value, n
XX
03
03
timer source clock
countdown counter
WD/CD [1:0]
CTAF
XX
00
02
01
03
02
01
03
02
01
03
01
INT1
n
n
duration of first timer period after
enable may range from n−1 to n+1
013aaa328
In this example, it is assumed that the countdown timer flag (CTAF) is cleared before the next
countdown period expires and that the interrupt output is set to pulse mode.
Fig 20. General countdown timer behavior
At the end of every countdown, the timer sets the countdown timer flag CTAF (register
Control_2). CTAF may only be cleared by using the interface. Instructions, how to clear a
flag, is given in Section 8.7.5.
When reading the timer, the current countdown value is returned and not the initial
value n. Since it is not possible to freeze the countdown timer counter during read back, it
is recommended to read the register twice and check for consistent results.
If a new value of n is written before the end of the actual timer-period, this value takes
immediate effect. It is not recommended to change n without first disabling the counter by
setting TAC[1:0] = 00 (register Tmr_CLKOUT_ctrl). The update of n is asynchronous to
the timer clock. Therefore changing it on the fly could result in a corrupted value loaded
into the countdown counter. This can result in an undetermined countdown period for the
first period. The countdown value n will be correctly stored and correctly loaded on
subsequent timer-periods.
Loading the counter with 0 effectively stops the timer.
When starting the countdown timer for the first time, only the first period does not have a
fixed duration. The amount of inaccuracy for the first timer-period depends on the chosen
source clock, see Table 41.
Table 41. First period delay for timer counter value n
Timer source clock
4.096 kHz
Minimum timer-period
Maximum timer-period
n + 1
n
64 Hz
n
n + 1
1 Hz
(n 1) + 1⁄64 Hz
(n 1) + 1⁄64 Hz
(n 1) + 1⁄64 Hz
n + 1⁄64 Hz
n + 1⁄64 Hz
n + 1⁄64 Hz
1
⁄60 Hz
1
⁄3600 Hz
The generation of interrupts from the countdown timer is controlled via the CTAIE bit
(register Control_2).
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Real-Time Clock (RTC) and calendar
When the interrupt generation is enabled (CTAIE = 1) and the countdown timer flag CTAF
is set logic 1, an interrupt signal on INT1 is generated. The interrupt may be generated as
a pulsed signal every countdown period or as a permanently active signal, which follows
the condition of CTAF (register Control_2). The TAM bit (register Tmr_CLKOUT_ctrl) is
used to control this mode selection. The interrupt output may be disabled with the CTAIE
bit (register Control_2).
8.9.3 Timer B
Timer B can only be used as a countdown timer and can be switched on and off by the
TBC bit in register Tmr_CLKOUT_ctrl (0Fh).
The generation of interrupts from the countdown timer is controlled via the CTBIE bit
(register Control_2).
When enabled, it counts down from the software programmed 8 bit binary value n in
register Tmr_B_reg (13h). When the counter reaches 1 on the next rising edge of the
timer clock, the following events occur (see Figure 21):
• The countdown timer flag CTBF (register Control_2) is set logic 1
• When the interrupt generation is enabled (CTBIE = 1), interrupt signals on INT1 and
INT2 are generated
• The counter automatically reloads
• The next timer-period starts
countdown value, n
timer source clock
countdown counter
WD/CD [1:0]
XX
03
XX
00
03
02
01
03
02
01
03
02
01
03
01
CTBF
INT1/INT2
n
n
duration of first timer period after
enable may range from n−1 to n+1
013aaa329
In this example, it is assumed that the countdown timer flag (CTBF) is cleared before the next
countdown period expires and that interrupt output is set to pulse mode.
Fig 21. General countdown timer behavior
At the end of every countdown, the timer sets the countdown timer flag CTBF (register
Control_2). CTBF may only be cleared by using the interface. Instructions, how to clear a
flag, is given in Section 8.7.5.
When reading the timer, the current countdown value is returned and not the initial
value n. Since it is not possible to freeze the countdown timer counter during read back, it
is recommended to read the register twice and check for consistent results.
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Real-Time Clock (RTC) and calendar
If a new value of n is written before the end of the actual timer-period, this value will take
immediate effect. It is not recommended to change n without first disabling the counter by
setting TBC logic 0 (register Tmr_CLKOUT_ctrl). The update of n is asynchronous to the
timer clock. Therefore changing it on the fly could result in a corrupted value loaded into
the countdown counter. This can result in an undetermined countdown period for the first
period. The countdown value n will be correctly stored and correctly loaded on
subsequent timer-periods.
Loading the counter with 0 effectively stops the timer.
When starting the countdown timer for the first time, only the first period does not have a
fixed duration. The amount of inaccuracy for the first timer-period depends on the chosen
source clock; see Table 41.
When the interrupt generation is enabled (CTBIE = 1) and the countdown timer flag CTAF
is set logic 1, interrupt signals on INT1 and INT2 are generated. The interrupt may be
generated as a pulsed signal every countdown period or as a permanently active signal,
which follows the condition of CTBF (register Control_2). The TBM bit (register
Tmr_CLKOUT_ctrl) is used to control this mode selection. Interrupt output may be
disabled with the CTBIE bit (register Control_2).
8.9.4 Second interrupt timer
PCF8523 has a pre-defined timer, which is used to generate an interrupt once per second.
The pulse generator for the second interrupt timer operates from an internal 64 Hz clock
and generates a pulse of 1⁄64 s in duration. It is independent of the watchdog or countdown
timer and can be switched on and off by the SIE bit in register Control_1 (00h).
The interrupt generated by the second interrupt timer may be generated as pulsed signal
every second or as a permanently active signal. The TAM bit (register Tmr_CLKOUT_ctrl)
is used to control the interrupt generation mode.
When the second interrupt timer is enabled (SIE = 1), then the timer sets the flag SF
(register Control_2) every second (see Table 42). SF may only be cleared by using the
interface. Instructions, how to clear a flag, are given in Section 8.7.5.
Table 42. Effect of bit SIE on INT1 and bit SF
SIE
0
Result on INT1
Result on SF
no interrupt generated
an interrupt once per second
SF never set
1
SF set when seconds counter increments
When SF is logic 1:
• If TAM (register Tmr_CLKOUT_ctrl) is logic 1, the interrupt is generated as a pulsed
signal every second
• If TAM is logic 0, the interrupt is a permanently active signal that remains, until SF is
cleared
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Real-Time Clock (RTC) and calendar
seconds counter
minutes counter
58
59
59
11
00
12
00
01
INT1 when SIE enabled
SF when SIE enabled
013aaa331
In this example, bit TAM is set logic 1 and the SF flag is not cleared after an interrupt.
Fig 22. Example for second interrupt when TAM = 1
seconds counter
minutes counter
58 59
59 00
11 12
00 01
INT1 when SIE enabled
SF when SIE enabled
013aaa332
In this example, bit TAM is set logic 0 and the SF flag is cleared after an interrupt.
Fig 23. Example for second interrupt when TAM = 0
8.9.5 Timer interrupt pulse
The timer interrupt is generated as a pulsed signal when TAM or TBM are set logic 1. The
pulse generator for the timer interrupt also uses an internal clock, but this time it is
dependent on the selected source clock for the timer and on the timer register value n. So,
the width of the interrupt pulse varies; see Table 43 and Table 44.
Table 43. Interrupt low pulse width for timer A
Pulse mode, bit TAM set logic 1.
Source clock (Hz)
Interrupt pulse width
n = 1[1]
n > 1[1]
4096
64
122 s
244 s
7.812 ms
15.625 ms
15.625 ms
15.625 ms
15.625 ms
1
15.625 ms
15.625 ms
15.625 ms
1
⁄
60
1
⁄
3600
[1] n = loaded timer register value. Timer stops when n = 0.
For timer B, interrupt pulse width is programmable via bit TBM (register
Tmr_CLKOUT_ctrl).
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Table 44. Interrupt low pulse width for timer B
Pulse mode, bit TBM set logic 1.
Source clock (Hz).
Interrupt pulse width
n = 1[1]
n > 1[1]
4096
64
122 s
244 s
see Table 38[2]
7.812 ms
1
see Table 38
:
:
:
1
⁄
:
:
60
1
⁄
3600
[1] n = loaded timer register value. Timer stops when n = 0.
[2] If pulse period is shorter than the setting via bit TBW[2:0], the interrupt pulse width is set to 15.625 ms.
When flags like SF, CTAF, WTAF, and CTBF are cleared before the end of the interrupt
pulse, then the interrupt pulse is shortened. This allows the source of a system interrupt to
be cleared immediately when it is serviced, that is, the system does not have to wait for
the completion of the pulse before continuing; see Figure 24 and Figure 25. Instructions
for clearing flags can be found in Section 8.7.5. Instructions for clearing the bit WTAF can
be found in Section 8.9.2.1.
seconds counter
SF
58
59
INT1
(1)
SCL
instruction
CLEAR INSTRUCTION
013aaa333
(1) Indicates normal duration of INT1 pulse.
The timing shown for clearing bit SF is also valid for the non-pulsed interrupt mode, that is, when
TAM set logic 0, where the INT1 pulse may be shortened by setting SIE logic 0.
Fig 24. Example of shortening the INT1 pulse by clearing the SF flag
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Real-Time Clock (RTC) and calendar
countdown counter
CDTF
01
n
INT1
(1)
SCL
instruction
CLEAR INSTRUCTION
013aaa334
(1) Indicates normal duration of INT1 pulse.
The timing shown for clearing CTAF is also valid for the non-pulsed interrupt mode, that is, when
TAM set logic 0, where the INT1 pulse may be shortened by setting CTAIE logic 0.
Fig 25. Example of shortening the INT1 pulse by clearing the CTAF flag
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Real-Time Clock (RTC) and calendar
8.10 STOP bit function
The STOP bit function allows the accurate starting of the time circuits. The STOP bit
function causes the upper part of the prescaler (F2 to F14) to be held in reset and thus no
1 Hz ticks are generated. The time circuits can then be set and do not increment until the
STOP bit is released (see Figure 26).
OSC STOP
DETECTOR
oscillator stop flag
F
F
F
F
F
14
0
1
2
13
OSC
1 Hz tick
stop
RES
RES
RES
512 Hz
CLKOUT source
8192 Hz
16384 Hz
013aaa336
Fig 26. STOP bit
STOP does not affect the output of 32.768 kHz, 16.384 kHz or 8.192 kHz (see
Section 8.9.1.1).
The lower two stages of the prescaler (F0 and F1) are not reset. And because the I2C-bus
interface is asynchronous to the crystal oscillator, the accuracy of re-starting the time
circuits will be between 0 and one 8.192 kHz cycle (see Figure 27).
8192 Hz
stop released
0 μs to 122 μs
001aaf912
Fig 27. STOP bit release timing
The first increment of the time circuits is between 0.499878 s and 0.500000 s after STOP
is released. The uncertainty is caused by the prescaler bits F0 and F1 not being reset (see
Table 45).
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Real-Time Clock (RTC) and calendar
Table 45. First increment of time circuits after STOP release
Bit
Prescaler bits[1]
1 Hz tick
Time
Comment
STOP
F0F1-F2 to F14
hh:mm:ss
Clock is running normally
0
12:45:12
prescaler counting normally
01-0000111010100
STOP is activated by user; F0F1 are not reset and values cannot be predicted externally
1
12:45:12
08:00:00
prescaler is reset; time circuits are frozen
prescaler is reset; time circuits are frozen
XX-0000000000000
New time is set by user
1
XX-0000000000000
STOP is released by user
0
0
0
0
:
08:00:00
08:00:00
08:00:00
08:00:00
:
prescaler is now running
XX-0000000000000
XX-1000000000000
XX-0100000000000
XX-1100000000000
:
-
-
-
:
0
0
0
:
08:00:00
08:00:01
08:00:01
:
-
11-1111111111110
00-0000000000001
10-0000000000001
:
0 to 1 transition of F14 increments the time circuits
-
:
0
0
:
08:00:01
08:00:01
:
-
11-1111111111111
00-0000000000000
:
-
:
0
0
08:00:01
08:00:02
-
11-1111111111110
00-0000000000001
0 to 1 transition of F14 increments the time circuits
013aaa337
[1] F0 is clocked at 32.768 kHz.
PCF8523
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PCF8523
NXP Semiconductors
Real-Time Clock (RTC) and calendar
8.11 I2C-bus interface
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines are
connected to a positive supply via a pull-up resistor. Data transfer is initiated only when
the bus is not busy.
8.11.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line remains
stable during the HIGH period of the clock pulse as changes in the data line at this time
are interpreted as control signals (see Figure 28).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
mbc621
Fig 28. Bit transfer
8.11.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH, is defined as the START condition (S).
A LOW-to-HIGH transition of the data line, while the clock is HIGH, is defined as the
STOP condition (P) (see Figure 29).
SDA
SCL
SDA
SCL
S
P
START condition
STOP condition
mbc622
Fig 29. Definition of START and STOP conditions
For this device, a repeated START is not allowed. Therefore, a STOP has to be released
before the next START.
8.11.3 System configuration
A device generating a message is a transmitter; a device receiving a message is the
receiver. The device that controls the message is the master and the devices, which are
controlled by the master, are the slaves.
PCF8523
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Product data sheet
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45 of 74
PCF8523
NXP Semiconductors
Real-Time Clock (RTC) and calendar
SDA
SCL
MASTER
TRANSMITTER
RECEIVER
SLAVE
TRANSMITTER
RECEIVER
MASTER
MASTER
SLAVE
RECEIVER
TRANSMITTER
TRANSMITTER
RECEIVER
mba605
Fig 30. System configuration
The PCF8523 can act as a slave transmitter and a slave receiver.
8.11.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge
cycle.
• A slave receiver, which is addressed, must generate an acknowledge cycle after the
reception of each byte
• Also a master receiver must generate an acknowledge cycle after the reception of
each byte that has been clocked out of the slave transmitter
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the related
acknowledge clock pulse (set-up and hold times must be considered)
• A master receiver must signal an end of data to the transmitter by not generating an
acknowledge cycle on the last byte that has been clocked out of the slave. In this
event, the transmitter must leave the data line HIGH to enable the master to generate
a STOP condition
Acknowledgement on the I2C-bus is shown in Figure 31.
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from
master
1
2
8
9
S
clock pulse for
acknowledgement
START
condition
mbc602
Fig 31. Acknowledgement on the I2C-bus
8.11.5 I2C-bus protocol
One I2C-bus slave address (1101000) is reserved for the PCF8523. The entire I2C-bus
slave address byte is shown in Table 46.
PCF8523
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Product data sheet
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46 of 74
PCF8523
NXP Semiconductors
Real-Time Clock (RTC) and calendar
Table 46. I2C slave address byte
Slave address[1]
Bit
7
6
5
4
3
2
1
0
MSB
LSB
R/W
1
1
0
1
0
0
0
[1] Devices with other I2C-bus slave addresses can be produced on request.
After a START condition, the I2C slave address has to be sent to the PCF8523 device.
The R/W bit defines the direction of the following single or multiple byte data transfer. For
the format and the timing of the START condition (S), the STOP condition (P) and the
acknowledge bit (A) refer to the I2C-bus characteristics (see Ref. 12 on page 67). In the
write mode, a data transfer is terminated by sending either the STOP condition or the
START condition of the next data transfer.
acknowledge
acknowledge
acknowledge
from PCF8523
from PCF8523
from PCF8523
S
1
1
0
1
0
0
0
0
A
A
A
P/S
slave address
register address
00h to 13h
0 to n
data bytes
write bit
START/
STOP
013aaa338
Fig 32. Bus protocol for write mode
acknowledge
from PCF8523
acknowledge
from PCF8523
set register
address
S
1
1
0
1
0
0
0
0
A
A
P
slave address
register address
00h to 13h
write bit
STOP
acknowledge
from PCF8523
acknowledge
from master
no acknowledge
LAST DATA BYTE
read register
data
S
1
1
0
1
0
0
0
1
A
DATA BYTE
A
A
P
slave address
0 to n data bytes
read bit
013aaa339
Fig 33. Bus protocol for read mode
PCF8523
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Product data sheet
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47 of 74
PCF8523
NXP Semiconductors
Real-Time Clock (RTC) and calendar
9. Internal circuitry
PCF8523
V
DD
OSCI
INT1/CLKOUT
SCL
OSCO
V
BAT
SDA
V
SS
CLKOUT
INT2
013aaa340
Fig 34. Device diode protection diagram of PCF8523
PCF8523
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Product data sheet
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48 of 74
PCF8523
NXP Semiconductors
Real-Time Clock (RTC) and calendar
10. Limiting values
Table 47. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions
Min
0.5
50
0.5
0.5
10
10
0.5
-
Max
+6.5
+50
Unit
V
VDD
IDD
VI
supply voltage
supply current
mA
V
input voltage
+6.5
+6.5
+10
VO
output voltage
V
II
input current
mA
mA
V
IO
output current
+10
VBAT
Ptot
VESD
battery supply voltage
total power dissipation
+6.5
300
mW
V
[1]
[2]
electrostatic discharge voltage HBM for all PCF8523
-
2000
1500
CDM for all
-
V
packaged PCF8523
[3]
[4]
Ilu
latch-up current
-
100
mA
C
Tstg
Tamb
storage temperature
65
40
+150
+85
ambient temperature
operating device
C
[1] Pass level; Human Body Model (HBM), according to Ref. 7 “JESD22-A114”.
[2] Pass level; Charged-Device Model (CDM), according to Ref. 8 “JESD22-C101”.
[3] Pass level; latch-up testing according to Ref. 9 “JESD78” at maximum ambient temperature (Tamb(max)).
[4] According to the store and transport requirements (see Ref. 13 “UM10569”) the devices have to be stored
at a temperature of +8 C to +45 C and a humidity of 25 % to 75 %.
PCF8523
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Product data sheet
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49 of 74
PCF8523
NXP Semiconductors
Real-Time Clock (RTC) and calendar
11. Static characteristics
Table 48. Static characteristics
VDD = 1.2 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; fosc = 32.768 kHz; quartz Rs = 40 k; CL = 7 pF; unless otherwise
specified.
Symbol Parameter
Supplies
Conditions
Min
Typ
Max
Unit
VDD
supply voltage
I2C-bus inactive;
for clock data integrity
[1]
[2]
Tamb = 40 C to +85 C
Tamb = +10 C to +85 C
I2C-bus active
1.2
1.0
1.6
1.8
-
-
-
-
-
-
-
-
5.5
5.5
5.5
5.5
0.5
5.5
200
V
V
V
power management function active
of VDD
V
SR
slew rate
V/ms
V
VBAT
IDD
battery supply voltage
supply current
power management function active
I2C-bus active;
fSCL = 1000 kHz
1.8
-
A
I2C-bus inactive (fSCL = 0 Hz);
interrupts disabled
clock-out disabled;
power management function disabled
(PM[2:0] = 111)
[3]
[3]
Tamb = 25 C;
VDD = 3.0 V
-
-
150
-
-
nA
nA
Tamb = 40 C to +85 C;
500
VDD = 2.0 V to 5.0 V
clock-out enabled at 32 kHz;
power management function enabled
(PM[2:0] = 000)
[4]
[4]
Tamb = 25 C;
VBAT or VDD = 3.0 V
-
-
-
1200
-
-
nA
nA
nA
Tamb = 40 C to +85 C;
VBAT or VDD = 2.0 V to 5.0 V
3600
100
IL(bat)
battery leakage current VDD active; VBAT = 3.0 V
50
Power management
Vth(sw)bat battery switch threshold
voltage
2.28
2.5
2.7
V
Inputs[5]
VIL
VIH
LOW-level input voltage
-
-
-
0.3VDD
-
V
V
HIGH-level input
voltage
0.7VDD
VI
ILI
input voltage
0.5
-
VDD + 0.5 V
input leakage current
VI = VSS or VDD
post ESD event
-
0
-
-
nA
1
-
+1
7
A
[6]
CI
input capacitance
-
pF
PCF8523
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Product data sheet
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PCF8523
NXP Semiconductors
Real-Time Clock (RTC) and calendar
Table 48. Static characteristics …continued
VDD = 1.2 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; fosc = 32.768 kHz; quartz Rs = 40 k; CL = 7 pF; unless otherwise
specified.
Symbol Parameter
Outputs
Conditions
Min
Typ
Max
Unit
VO
output voltage
on pins INT1/CLKOUT, CLKOUT, INT2,
SDA (refers to external pull-up voltage)
0.5
VSS
1.5
-
-
-
5.5
0.4
-
V
VOL
IOL
LOW-level output
voltage
V
[7]
[7]
LOW-level output
current
output sink current;
on pins INT1/CLKOUT, CLKOUT, INT2;
mA
VOL = 0.4 V; VDD = 5 V
on pin SDA
20
-
-
mA
VOL = 0.4 V; VDD = 3.0 V
ILO
output leakage current VO = VSS or VDD
post ESD event
-
0
-
-
nA
1
+1
A
[8][9]
[10]
CL(itg)
integrated load
capacitance
on pins OSCO, OSCI
CL = 7 pF
3.3
6
7
14
pF
pF
k
CL = 12.5 pF
12.5
-
25
RS
series resistance
-
100
[1] For reliable oscillator start at power-up: VDD = VDD(min) + 0.3 V.
[2] For reliable oscillator start at power-up: VDD = VDD(min) + 0.5 V.
[3] Timer source clock = 1
⁄3600 Hz, level of pins SCL and SDA is VDD or VSS.
[4] When the device is supplied via the VBAT pin instead of the VDD pin, the current values for IBAT will be as specified for IDD under the same
conditions.
[5] The I2C-bus is 5 V tolerant.
[6] Implicit by design.
[7] Tested on sample basis.
COSCI COSCO
[8] Integrated load capacitance, CL(itg), is a calculation of COSCI and COSCO in series: CLitg
[9] Tested at 25 C.
=
.
-------------------------------------------
COSCI + COSCO
[10] Crystal characteristic specification.
PCF8523
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Product data sheet
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51 of 74
PCF8523
NXP Semiconductors
Real-Time Clock (RTC) and calendar
12. Dynamic characteristics
Table 49. I2C-bus interface timing
All timing characteristics are valid within the operating supply voltage and ambient temperature range and reference to 30 %
and 70 % with an input voltage swing of VSS to VDD (see Figure 35).
Symbol Parameter
Conditions Standard mode Fast mode (FM) Fast mode plus (Fm+)[1] Unit
Min
Max
Min
Max Min
Max
Pin SCL
[2]
fSCL
SCL clock frequency
LOW period of the SCL clock
-
100
-
400
-
1000
kHz
s
tLOW
-
4.7
4.0
-
-
1.3
0.6
-
-
0.5
0.26
-
-
tHIGH
HIGH period of the SCL clock -
s
Pin SDA
tSU;DAT data set-up time
tHD;DAT data hold time
Pins SCL and SDA
-
-
250
0
-
-
100
0
-
-
50
0
-
-
ns
ns
tBUF
bus free time between a
STOP and START condition
-
-
-
4.7
4.0
4.0
4.7
-
-
1.3
0.6
0.6
0.6
-
-
-
-
0.5
0.26
0.26
0.26
-
-
s
s
s
s
ns
ns
pF
tSU;STO set-up time for STOP
condition
-
-
tHD;STA hold time (repeated) START
condition
-
-
tSU;STA set-up time for a repeated
START condition
-
-
-
[3][4]
tr
rise time of both SDA and
SCL signals
1000
300
400
20 + 0.1Cb 300
20 + 0.1Cb 300
120
120
550
[3][4]
tf
fall time of both SDA and SCL
signals
-
-
Cb
capacitive load for each bus
line
-
-
400
-
[5]
[6]
[7]
tVD;ACK data valid acknowledge time
tVD;DAT data valid time
-
-
-
3.45
3.45
50
-
-
-
0.9
0.9
50
-
-
-
0.45
0.45
50
s
s
ns
tSP
pulse width of spikes that
must be suppressed by the
input filter
[1] Fast mode plus guaranteed at 3.0 V < VDD < 5.5 V.
[2] The minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either the SDA or SCL
is held LOW for a minimum of 25 ms. The bus time-out feature must be disabled for DC operation.
[3] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to
bridge the undefined region of the falling edge of SCL.
[4] The maximum tf for the SDA and SCL bus lines is 300 ns. The maximum fall time for the SDA output stage, tf is 250 ns. This allows
series protection resistors to be connected between the SDA pin, the SCL pin and the SDA/SCL bus lines without exceeding the
maximum tf.
[5] tVD;ACK = time for acknowledgement signal from SCL LOW to SDA output LOW.
[6] tVD;DAT = minimum time for valid SDA output following SCL LOW.
[7] Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns.
PCF8523
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Product data sheet
Rev. 4 — 5 July 2012
52 of 74
PCF8523
NXP Semiconductors
Real-Time Clock (RTC) and calendar
START
condition
(S)
bit 7
MSB
(A7)
STOP
bit 0 acknowledge
condition
bit 6
(A6)
protocol
(R/W)
(A)
(P)
t
t
t
HIGH
SU;STA
LOW
1
/f
SCL
SCL
SDA
t
t
BUF
f
t
r
t
t
t
t
t
t
HD;DAT
VD;DAT
VD;ACK
SU;STO
013aaa417
HD;STA
SU;DAT
Fig 35. I2C-bus timing diagram; rise and fall times refer to 30 % and 70 %
13. Application information
V
DD
R
C
1
SCL
SDA
MASTER
TRANSMITTER
RECEIVER
1
V
SS
V
DD
INT1/
CLKOUT
CLKOUT
INT2
SCL
OSCI
V
DD
OSCO
PCF8523
R
R
SDA
R: pull-up resistor
V
V
SS
BAT
t
r
R =
C
b
013aaa341
R1 and C1 are recommended to limit the Slew Rate (SR, see Table 48) of VDD. If VDD drops too
fast, the internal supply switch to the battery is not guaranteed.
Fig 36. Application diagram
PCF8523
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Product data sheet
Rev. 4 — 5 July 2012
53 of 74
PCF8523
NXP Semiconductors
Real-Time Clock (RTC) and calendar
14. Package outline
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
4
e
w
M
detail X
b
p
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.20
0.014 0.0075 0.19
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches 0.069
0.01 0.004
Notes
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT96-1
076E03
MS-012
Fig 37. Package outline SOT96-1 (SO8) of PCF8523T
PCF8523
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Product data sheet
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54 of 74
PCF8523
NXP Semiconductors
Real-Time Clock (RTC) and calendar
HVSON8: plastic thermal enhanced very thin small outline package; no leads;
8 terminals; body 4 x 4 x 0.85 mm
SOT909-1
0
1
2 mm
scale
X
B
A
D
E
A
A
1
c
detail X
terminal 1
index area
e
1
C
y
terminal 1
index area
M
v
C
C
A
B
e
b
y
M
w
C
1
1
4
L
exposed tie bar (4×)
E
h
8
5
D
h
DIMENSIONS (mm are the original dimensions)
(1)
A
max.
(1)
(1)
UNIT
A
b
E
e
e
y
c
D
D
E
L
v
w
y
1
1
h
1
h
0.05
0.00
0.4
0.3
4.1
3.9
3.25
2.95
4.1
3.9
2.35
2.05
0.65
0.40
mm
0.05
0.1
1
0.2
0.8
2.4
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
05-09-26
05-09-28
SOT909-1
MO-229
Fig 38. Package outline SOT909-1 (HVSON8) of PCF8523TK
PCF8523
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Product data sheet
Rev. 4 — 5 July 2012
55 of 74
PCF8523
NXP Semiconductors
Real-Time Clock (RTC) and calendar
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
7
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.72
0.38
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT402-1
MO-153
Fig 39. Package outline SOT402-1 (TSSOP14) of PCF8523TS
PCF8523
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Product data sheet
Rev. 4 — 5 July 2012
56 of 74
PCF8523
NXP Semiconductors
Real-Time Clock (RTC) and calendar
15. Bare die outline
Bare die; 12 bumps (6-6)
PCF8523U
D
Y
X
2
3
1
PC8523-1
12
11
x
E
0
10
0
y
4
5
6
9
8
7
A
A
2
A
1
P
4
P
3
P
2
P
1
European
projection
detail Y
detail X
pcf8523u_do
Fig 40. Bare die outline of PCF8523U
Table 50. Dimensions of PCF8523U
Original dimensions are in mm.
[2]
[3]
[2]
[3]
Unit (mm)
max
A
A1
A2
D[1]
E[1]
P1
P2
P3
P4
0.059
Bump pitch
-
0.018
-
-
-
-
0.059
-
-
-
nom
0.22
-
0.015 0.2
0.012
1.58
-
2.15
-
0.065 0.056 0.065 0.056
0.053
min
-
-
-
0.053 0.149
[1] Dimension includes saw lane.
[2] P1 and P3: pad size.
[3] P2 and P4: bump size.
PCF8523
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Table 51. Bump locations
All x/y coordinates represent the position of the center of each bump with respect to the center
(x/y = 0) of the chip; see Figure 40.
Symbol
Bump
Coordinates (m)
X
Y
VDD
1
714.4
911.7
988.3
707.3
199.3
459.1
616.7
895.4
922.0
528.8
101.1
607.6
763.2
OSCI
OSCO
VBAT
2
714.4
714.4
714.4
714.4
714.4
714.4
714.4
3
4
VSS
5
n.c.
6
INT2
7
CLKOUT
SDA
8
9
714.4
SCL
10
11
12
714.4
n.c.
714.4
INT1/CLKOUT
714.4
Table 52. Alignment mark dimension and location
Coordinates
Location[1]
X
Y
631.3 m
44.25 m
891.7 m
36.5 m
Dimension[2]
[1] The x/y coordinates of the alignment mark location represent the position of the REF point (see Figure 41)
with respect to the center (x/y = 0) of the chip; see Figure 40.
[2] The x/y values of the dimensions represent the extensions of the alignment mark in direction of the
coordinate axis (see Figure 41).
REF
x
y
013aaa318
Fig 41. Alignment mark
Table 53. Gold bump hardness of PCF8523U
Gold bump type
Min
Max
80
Unit[1]
soft gold bump
35
HV
[1] Pressure of diamond head: 10 g to 50 g.
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16. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that
all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent
standards.
17. Packing information
17.1 Tape and reel information
TOP VIEW
4.0
Ø 1.5
W
B0
A0
K0
P1
direction of feed
Ø 1.5
Original dimensions are in mm.
Figure not drawn to scale.
013aaa698
Fig 42. Tape and reel details for PCF8523
Table 54. Carrier tape dimensions of PCF8523
Symbol
Description
Value
Unit
SOT96-1 (SO8) of PCF8523T
A0
B0
K0
P1
W
pocket width in x direction
6.30 to 6.65
5.40
mm
mm
mm
mm
mm
pocket width in y direction
pocket depth
2.05 to 2.10
8.0
pocket hole pitch
tape width in y direction
12.0
SOT909-1 (HVSON8) of PCF8523TK
A0
B0
K0
P1
W
pocket width in x direction
pocket width in y direction
pocket depth
4.25 to 4.30
4.25 to 4.30
1.1
mm
mm
mm
mm
mm
pocket hole pitch
8.0
tape width in y direction
12.0
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Table 54. Carrier tape dimensions of PCF8523 …continued
Symbol Description
SOT402-1 (TSSOP14) of PCF8523TS
Value
Unit
A0
B0
K0
P1
W
pocket width in x direction
pocket width in y direction
pocket depth
6.95
5.6
mm
mm
mm
mm
mm
1.6
pocket hole pitch
8.0
tape width in y direction
12.0
17.2 Wafer and Film Frame Carrier (FFC) information
1.492 mm
(1)
~18 μm
1
1
1.449 mm
45 μm
~18 μm
Saw lane
X
1
1
70 μm
detail X
straight edge
of the wafer
013aaa232
(1) Die marking code.
Seal ring plus gap to active circuit ~18 m. Wafer thickness 200 m.
PCF8523U: bad die are marked in wafer mapping.
Fig 43. PCF8523U wafer information
PCF8523
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276 mm
60.2 mm
63.5 mm
2.6 mm
plastic frame
0.3
straight edge
of the wafer
276 mm
∅ 250 mm
plastic film
013aaa351
Fig 44. Film Frame Carrier (FFC) (for PCF8523U)
PCF8523
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18. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
18.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
18.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
18.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
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18.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 45) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 55 and 56
Table 55. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350
235
350
220
< 2.5
2.5
220
220
Table 56. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 45.
PCF8523
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maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 45. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
19. Footprint information
5.50
0.60 (8×)
1.30
4.00 6.60 7.00
1.27 (6×)
solder lands
sot096-1_fr
placement accuracy 0.25
Dimensions in mm
occupied area
Fig 46. Footprint information for reflow soldering of SOT96-1 (SO8) of PCF8523T
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Footprint information for reflow soldering of TSSOP14 package
SOT402-1
Hx
Gx
P2
(0.125)
(0.125)
By
Ay
Hy Gy
C
D2 (4x)
P1
D1
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1 P2 Ay
By
C
D1
D2
Gx
Gy
Hx
Hy
0.650 0.750 7.200 4.500 1.350 0.400 0.600 4.950 5.300 5.800 7.450
sot402-1_fr
Fig 47. Footprint information for reflow soldering of SOT402-1 (TSSOP14) of PCF8523TS
PCF8523
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20. Abbreviations
Table 57. Abbreviations
Acronym
AM
Description
Ante Meridiem
BCD
CDM
CMOS
DC
Binary Coded Decimal
Charged-Device Model
Complementary Metal-Oxide Semiconductor
Direct Current
FFC
HBM
I2C
Film Frame Carrier
Human Body Model
Inter-Integrated Circuit bus
Integrated Circuit
IC
LSB
MCU
MSB
MSL
PCB
PM
Least Significant Bit
Microcontroller Unit
Most Significant Bit
Moisture Sensitivity Level
Printed-Circuit Board
Post Meridiem
POR
RTC
SCL
SDA
SMD
SR
Power-On Reset
Real-Time Clock
Serial CLock line
Serial DAta line
Surface Mount Device
Slew Rate
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21. References
[1] AN10365 — Surface mount reflow soldering description
[2] AN10706 — Handling bare die
[3] AN10853 — ESD and EMC sensitivity of IC
[4] IEC 60134 — Rating systems for electronic tubes and valves and analogous
semiconductor devices
[5] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena
[6] IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for
Nonhermetic Solid State Surface Mount Devices
[7] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM)
[8] JESD22-C101 — Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components
[9] JESD78 — IC Latch-Up Test
[10] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive
(ESDS) Devices
[11] SNV-FA-01-02 — Marking Formats Integrated Circuits
[12] UM10204 — I2C-bus specification and user manual
[13] UM10569 — Store and transport requirements
PCF8523
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22. Revision history
Table 58. Revision history
Document ID
PCF8523 v.4
Modifications:
Release date
20120705
Data sheet status
Change notice
Supersedes
Product data sheet
-
PCF8523 v.3
• Added Section 4.1, Section 17.1, Section 8.8.3, and Section 19
• Added I2C read and write address to feature list
• Fixed Figure 33
• Fixed typos
PCF8523 v.3
PCF8523 v.2
PCF8523 v.1
20110330
20110127
20101123
Product data sheet
Product data sheet
Product data sheet
-
-
-
PCF8523 v.2
PCF8523 v.1
-
PCF8523
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23. Legal information
23.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
23.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
23.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
PCF8523
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Real-Time Clock (RTC) and calendar
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Bare die — All die are tested on compliance with their related technical
specifications as stated in this data sheet up to the point of wafer sawing and
are handled in accordance with the NXP Semiconductors storage and
transportation conditions. If there are data sheet limits not guaranteed, these
will be separately indicated in the data sheet. There are no post-packing tests
performed on individual die or wafers.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors has no control of third party procedures in the sawing,
handling, packing or assembly of the die. Accordingly, NXP Semiconductors
assumes no liability for device functionality or performance of the die or
systems after third party sawing, handling, packing or assembly of the die. It
is the responsibility of the customer to test and qualify their application in
which the die is used.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
All die sales are conditioned upon and subject to the customer entering into a
written die sale agreement with NXP Semiconductors through its legal
department.
23.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
I2C-bus — logo is a trademark of NXP B.V.
24. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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25. Tables
Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2
Table 2. Ordering options. . . . . . . . . . . . . . . . . . . . . . . . .2
Table 3. PCF8523U wafer information . . . . . . . . . . . . . . .2
Table 4. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2
Table 5. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table 6. Registers overview . . . . . . . . . . . . . . . . . . . . . .7
Table 7. Control_1 - control and status register 1
(address 00h) bit description . . . . . . . . . . . . . . .9
Table 8. Control_2 - control and status register 2
(address 01h) bit description . . . . . . . . . . . . . .10
Table 9. Control_3 - control and status register 3
(address 02h) bit description . . . . . . . . . . . . . .11
Table 10. Register reset values . . . . . . . . . . . . . . . . . . . .12
Table 11. Power management function control bits . . . . .15
Table 12. Seconds - seconds and clock integrity status
register (address 03h) bit description . . . . . . . .20
Table 13. SECONDS coded in BCD format . . . . . . . . . . .20
Table 14. Minutes - minutes register (address 04h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 15. Hours - hours register (address 05h)
Table 27. Example to clear only AF (bit 3). . . . . . . . . . . . 26
Table 28. Offset - offset register (address 0Eh)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 29. Offset values . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 30. Correction pulses for MODE = 0 . . . . . . . . . . . 29
Table 31. Effect of clock correction for MODE = 0. . . . . . 29
Table 32. Correction pulses for MODE = 1 . . . . . . . . . . . 30
Table 33. Effect of clock correction for MODE = 1 . . . . . 30
Table 34. Tmr_CLKOUT_ctrl - timer and CLKOUT control
register (address 0Fh) bit description . . . . . . . 32
Table 35. CLKOUT frequency selection . . . . . . . . . . . . . 33
Table 36. Tmr_A_freq_ctrl - timer A frequency control
register (address 10h) bit description . . . . . . . 33
Table 37. Tmr_A_reg - timer A value register (address 11h)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 38. Tmr_B_freq_ctrl - timer B frequency control
register (address 12h) bit description . . . . . . . 34
Table 39. Tmr_B_reg - timer B value register (address 13h)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 40. Programmable timer characteristics . . . . . . . . 35
Table 41. First period delay for timer counter value n . . . 37
Table 42. Effect of bit SIE on INT1 and bit SF . . . . . . . . . 39
Table 43. Interrupt low pulse width for timer A. . . . . . . . . 40
Table 44. Interrupt low pulse width for timer B. . . . . . . . . 41
Table 45. First increment of time circuits after STOP
release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 46. I2C slave address byte. . . . . . . . . . . . . . . . . . . 47
Table 47. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 48. Static characteristics . . . . . . . . . . . . . . . . . . . . 50
Table 49. I2C-bus interface timing . . . . . . . . . . . . . . . . . . 52
Table 50. Dimensions of PCF8523U . . . . . . . . . . . . . . . . 57
Table 51. Bump locations . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 52. Alignment mark dimension and location . . . . . 58
Table 53. Gold bump hardness of PCF8523U. . . . . . . . . 58
Table 54. Carrier tape dimensions of PCF8523 . . . . . . . 59
Table 55. SnPb eutectic process (from J-STD-020C) . . . 63
Table 56. Lead-free process (from J-STD-020C) . . . . . . 63
Table 57. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 58. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 68
bit description . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 16. Days - days register (address 06h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 17. Weekdays - weekdays register (address 07h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 18. Weekday assignments . . . . . . . . . . . . . . . . . . .22
Table 19. Months - months register (address 08h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 20. Month assignments in BCD format. . . . . . . . . .22
Table 21. Years - years register (09h) bit description. . . .23
Table 22. Minute_alarm - minute alarm register
(address 0Ah) bit description . . . . . . . . . . . . . .24
Table 23. Hour_alarm - hour alarm register (address 0Bh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 24. Day_alarm - day alarm register (address 0Ch)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 25. Weekday_alarm - weekday alarm register
(address 0Dh) bit description . . . . . . . . . . . . . .25
Table 26. Flag location in register Control_2 . . . . . . . . . .26
PCF8523
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 5 July 2012
71 of 74
PCF8523
NXP Semiconductors
Real-Time Clock (RTC) and calendar
26. Figures
Fig 1. Block diagram of PCF8523 . . . . . . . . . . . . . . . . . .3
Fig 2. Pin configuration for SO8 (PCF8523T) . . . . . . . . .4
Fig 3. Pin configuration for HVSON8 (PCF8523TK) . . . .4
Fig 4. Pin configuration for TSSOP14 (PCF8523TS). . . .4
Fig 5. Pin configuration for PCF8523U . . . . . . . . . . . . . .5
Fig 6. Auto-incrementing of the registers. . . . . . . . . . . . .7
Fig 7. Software reset command. . . . . . . . . . . . . . . . . . .12
Fig 8. Interrupt block diagram . . . . . . . . . . . . . . . . . . . .14
Fig 9. Battery switch-over behavior in standard mode
and with bit BSIE set logic 1 (enabled) . . . . . . . .17
Fig 47. Footprint information for reflow soldering of
SOT402-1 (TSSOP14) of PCF8523TS . . . . . . . . 65
Fig 10. Battery switch-over behavior in direct switching
mode and with bit BSIE set logic 1 (enabled) . . .18
Fig 11. Battery low detection behavior with bit BLIE
set logic 1 (enabled) . . . . . . . . . . . . . . . . . . . . . .19
Fig 12. OS flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Fig 13. Data flow diagram of the time function. . . . . . . . .23
Fig 14. Access time for read/write operations . . . . . . . . .23
Fig 15. Alarm function block diagram. . . . . . . . . . . . . . . .25
Fig 16. Alarm flag timing . . . . . . . . . . . . . . . . . . . . . . . . .26
Fig 17. AF timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Fig 18. Offset calibration calculation workflow. . . . . . . . .31
Fig 19. Watchdog activates an interrupt when timed out.36
Fig 20. General countdown timer behavior . . . . . . . . . . .37
Fig 21. General countdown timer behavior . . . . . . . . . . .38
Fig 22. Example for second interrupt when TAM = 1. . . .40
Fig 23. Example for second interrupt when TAM = 0. . . .40
Fig 24. Example of shortening the INT1 pulse by
clearing the SF flag . . . . . . . . . . . . . . . . . . . . . . .41
Fig 25. Example of shortening the INT1 pulse by
clearing the CTAF flag . . . . . . . . . . . . . . . . . . . . .42
Fig 26. STOP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Fig 27. STOP bit release timing. . . . . . . . . . . . . . . . . . . .43
Fig 28. Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Fig 29. Definition of START and STOP conditions. . . . . .45
Fig 30. System configuration . . . . . . . . . . . . . . . . . . . . . .46
Fig 31. Acknowledgement on the I2C-bus . . . . . . . . . . . .46
Fig 32. Bus protocol for write mode. . . . . . . . . . . . . . . . .47
Fig 33. Bus protocol for read mode . . . . . . . . . . . . . . . . .47
Fig 34. Device diode protection diagram of PCF8523 . .48
Fig 35. I2C-bus timing diagram; rise and fall times refer
to 30 % and 70 % . . . . . . . . . . . . . . . . . . . . . . . .53
Fig 36. Application diagram . . . . . . . . . . . . . . . . . . . . . . .53
Fig 37. Package outline SOT96-1 (SO8) of PCF8523T. .54
Fig 38. Package outline SOT909-1 (HVSON8) of
PCF8523TK. . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Fig 39. Package outline SOT402-1 (TSSOP14) of
PCF8523TS. . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Fig 40. Bare die outline of PCF8523U. . . . . . . . . . . . . . .57
Fig 41. Alignment mark . . . . . . . . . . . . . . . . . . . . . . . . . .58
Fig 42. Tape and reel details for PCF8523 . . . . . . . . . . .59
Fig 43. PCF8523U wafer information. . . . . . . . . . . . . . . .60
Fig 44. Film Frame Carrier (FFC) (for PCF8523U) . . . . .61
Fig 45. Temperature profiles for large and small
components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Fig 46. Footprint information for reflow soldering of
SOT96-1 (SO8) of PCF8523T . . . . . . . . . . . . . . .64
PCF8523
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 5 July 2012
72 of 74
PCF8523
NXP Semiconductors
Real-Time Clock (RTC) and calendar
27. Contents
1
General description. . . . . . . . . . . . . . . . . . . . . . 1
8.8.3
8.9
8.9.1
Offset calibration workflow. . . . . . . . . . . . . . . 31
Timer function . . . . . . . . . . . . . . . . . . . . . . . . 32
Timer registers . . . . . . . . . . . . . . . . . . . . . . . . 32
Register Tmr_CLKOUT_ctrl and clock output 32
CLKOUT frequency selection . . . . . . . . . . . . 32
Register Tmr_A_freq_ctrl. . . . . . . . . . . . . . . . 33
Register Tmr_A_reg. . . . . . . . . . . . . . . . . . . . 34
Register Tmr_B_freq_ctrl. . . . . . . . . . . . . . . . 34
Register Tmr_B_reg . . . . . . . . . . . . . . . . . . . 34
Programmable timer characteristics . . . . . . . 35
Timer A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Watchdog timer function . . . . . . . . . . . . . . . . 35
Countdown timer function . . . . . . . . . . . . . . . 36
Timer B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Second interrupt timer . . . . . . . . . . . . . . . . . . 39
Timer interrupt pulse . . . . . . . . . . . . . . . . . . . 40
STOP bit function. . . . . . . . . . . . . . . . . . . . . . 43
I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . 45
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
START and STOP conditions. . . . . . . . . . . . . 45
System configuration . . . . . . . . . . . . . . . . . . . 45
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 46
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 46
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3
8.9.1.1
8.9.1.2
8.9.1.3
8.9.1.4
8.9.1.5
8.9.1.6
8.9.1.7
8.9.2
8.9.2.1
8.9.2.2
8.9.3
8.9.4
8.9.5
4
4.1
5
6
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
8
8.1
8.2
8.2.1
8.2.2
8.2.3
8.3
8.4
8.5
8.5.1
8.5.2
8.5.2.1
8.5.2.2
8.5.2.3
Functional description . . . . . . . . . . . . . . . . . . . 6
Registers overview . . . . . . . . . . . . . . . . . . . . . . 7
Control and status registers . . . . . . . . . . . . . . . 9
Register Control_1 . . . . . . . . . . . . . . . . . . . . . . 9
Register Control_2 . . . . . . . . . . . . . . . . . . . . . 10
Register Control_3 . . . . . . . . . . . . . . . . . . . . . 11
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Interrupt function. . . . . . . . . . . . . . . . . . . . . . . 13
Power management functions . . . . . . . . . . . . 15
Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . 15
Battery switch-over function . . . . . . . . . . . . . . 16
Standard mode . . . . . . . . . . . . . . . . . . . . . . . . 17
Direct switching mode . . . . . . . . . . . . . . . . . . 18
Battery switch-over disabled, only one power
supply (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Battery low detection function. . . . . . . . . . . . . 18
Time and date registers . . . . . . . . . . . . . . . . . 19
Register Seconds . . . . . . . . . . . . . . . . . . . . . . 20
Oscillator STOP flag . . . . . . . . . . . . . . . . . . . . 20
Register Minutes. . . . . . . . . . . . . . . . . . . . . . . 21
Register Hours . . . . . . . . . . . . . . . . . . . . . . . . 21
Register Days. . . . . . . . . . . . . . . . . . . . . . . . . 21
Register Weekdays. . . . . . . . . . . . . . . . . . . . . 22
Register Months . . . . . . . . . . . . . . . . . . . . . . . 22
Register Years . . . . . . . . . . . . . . . . . . . . . . . . 23
Data flow of the time function . . . . . . . . . . . . . 23
Alarm registers . . . . . . . . . . . . . . . . . . . . . . . . 24
Register Minute_alarm . . . . . . . . . . . . . . . . . . 24
Register Hour_alarm . . . . . . . . . . . . . . . . . . . 24
Register Day_alarm . . . . . . . . . . . . . . . . . . . . 25
Register Weekday_alarm . . . . . . . . . . . . . . . . 25
Alarm flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Alarm interrupts . . . . . . . . . . . . . . . . . . . . . . . 27
Register Offset . . . . . . . . . . . . . . . . . . . . . . . . 28
Correction when MODE = 0 . . . . . . . . . . . . . . 29
Correction when MODE = 1 . . . . . . . . . . . . . . 30
8.10
8.11
8.11.1
8.11.2
8.11.3
8.11.4
8.11.5
9
Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 48
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 49
Static characteristics . . . . . . . . . . . . . . . . . . . 50
Dynamic characteristics. . . . . . . . . . . . . . . . . 52
Application information . . . . . . . . . . . . . . . . . 53
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 54
Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 57
Handling information . . . . . . . . . . . . . . . . . . . 59
10
11
12
13
14
15
16
8.5.3
8.6
8.6.1
8.6.1.1
8.6.2
8.6.3
8.6.4
8.6.5
8.6.6
8.6.7
8.6.8
8.7
8.7.1
8.7.2
8.7.3
8.7.4
8.7.5
8.7.6
8.8
17
17.1
17.2
Packing information . . . . . . . . . . . . . . . . . . . . 59
Tape and reel information . . . . . . . . . . . . . . . 59
Wafer and Film Frame Carrier (FFC)
information . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
18
Soldering of SMD packages. . . . . . . . . . . . . . 62
Introduction to soldering. . . . . . . . . . . . . . . . . 62
Wave and reflow soldering. . . . . . . . . . . . . . . 62
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 62
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 63
18.1
18.2
18.3
18.4
19
20
21
22
23
Footprint information . . . . . . . . . . . . . . . . . . . 64
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 66
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Revision history . . . . . . . . . . . . . . . . . . . . . . . 68
Legal information . . . . . . . . . . . . . . . . . . . . . . 69
8.8.1
8.8.2
continued >>
PCF8523
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 5 July 2012
73 of 74
PCF8523
NXP Semiconductors
Real-Time Clock (RTC) and calendar
23.1
23.2
23.3
23.4
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 69
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 70
24
25
26
27
Contact information. . . . . . . . . . . . . . . . . . . . . 70
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 5 July 2012
Document identifier: PCF8523
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
NXP:
PCF8523T/1,118 PCF8523TK/1,118 PCF8523TS/1,112 PCF8523TS/1,118
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