UJA1065TW/3V3,512_技术文档

UJA1065

High-speed CAN/LIN fail-safe system basis chip

Rev. 07 — 25 February 2010

Product data sheet

1. General description

The UJA1065 fail-safe System Basis Chip (SBC) replaces basic discrete components that

are common in every Electronic Control Unit (ECU) with a Controller Area Network (CAN)

and a Local Interconnect Network (LIN) interface. The fail-safe SBC supports all

networking applications that control various power and sensor peripherals by using

high-speed CAN as the main network interface and LIN as a local sub-bus. The fail-safe

SBC contains the following integrated devices:

• High-speed CAN transceiver, interoperable and downward compatible with CAN

transceivers TJA1041 and TJA1041A, and compatible with the ISO 11898-2 standard

and the ISO 11898-5 standard (in preparation)

• LIN transceiver compliant with LIN 2.0 and SAE J2602, and compatible with LIN 1.3

• Advanced independent watchdog

• Dedicated voltage regulators for microcontroller and CAN transceiver

• Serial peripheral interface (full duplex)

• Local wake-up input port

• Inhibit/limp-home output port

In addition to the advantages of integrating these common ECU functions in a single

package, the fail-safe SBC offers an intelligent combination of system-specific functions

such as:

• Advanced low-power concept

• Safe and controlled system start-up behavior

• Advanced fail-safe system behavior that prevents any conceivable deadlock

• Detailed status reporting on system and subsystem levels

The UJA1065 is designed to be used in combination with a microcontroller that

incorporates a CAN controller. The fail-safe SBC ensures that the microcontroller is

always started up in a defined manner. In failure situations, the fail-safe SBC will maintain

microcontroller functionality for as long as possible to provide full monitoring and a

software-driven fall-back operation.

The UJA1065 is designed for 14 V single power supply architectures and for 14 V and

42 V dual power supply architectures.

UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

2. Features

2.1 General

Contains a full set of CAN and LIN ECU functions:

CAN transceiver and LIN transceiver

Voltage regulator for the microcontroller (3.3 V or 5.0 V)

Separate voltage regulator for the CAN transceiver (5 V)

Enhanced window watchdog with on-chip oscillator

Serial Peripheral Interface (SPI) for the microcontroller

ECU power management system

Fully integrated autonomous fail-safe system

Designed for automotive applications:

Supports 14 V and 42 V architectures

Excellent ElectroMagnetic Compatibility (EMC) performance

±8 kV ElectroStatic Discharge (ESD) protection Human Body Model (HBM) for

off-board pins

±4 kV ElectroStatic Discharge (ESD) protection IEC 61000-4-2 for off-board pins

±60 V short-circuit proof CAN/LIN-bus pins

Battery and CAN/LIN-bus pins are protected against transients in accordance with

ISO 7637-3

Very low sleep current

Supports remote flash programming via the CAN-bus

Small 6.1 mm × 11 mm HTSSOP32 package with low thermal resistance

2.2 CAN transceiver

ISO 11898-2 and ISO 11898-5 compliant high-speed CAN transceiver

Enhanced error signalling and reporting

Dedicated low dropout voltage regulator for the CAN-bus:

Independent from microcontroller supply

Guarded by CAN-bus failure management

Significantly improves EMC performance

Partial networking option with global wake-up feature, allows selective CAN-bus

communication without waking up sleeping nodes

Bus connections are truly floating when power is off

SPLIT output pin for stabilizing the recessive bus level

2.3 LIN transceiver

LIN 2.0 compliant LIN transceiver

Enhanced error signalling and reporting

Downward compatible with LIN 1.3 and the TJA1020

UJA1065_7

Product data sheet

Rev. 07 — 25 February 2010

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UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

2.4 Power management

Smart operating modes and power management modes

Cyclic wake-up capability in Standby and Sleep mode

Local wake-up input with cyclic supply feature

Remote wake-up capability via the CAN-bus and LIN-bus

External voltage regulators can easily be incorporated in the power supply system

(flexible and fail-safe)

42 V battery-related high-side switch for driving external loads such as relays and

wake-up switches

Intelligent maskable interrupt output

2.5 Fail-safe features

Safe and predictable behavior under all conditions

Programmable fail-safe coded window and time-out watchdog with on-chip oscillator,

guaranteeing autonomous fail-safe system supervision

Fail-safe coded 16-bit SPI interface for the microcontroller

Global enable pin for the control of safety-critical hardware

Detection and detailed reporting of failures:

On-chip oscillator failure and watchdog alerts

Battery and voltage regulator undervoltages

CAN and LIN-bus failures (short-circuits and open-circuit bus wires)

TXD and RXD clamping situations and short-circuits

Clamped or open reset line

SPI message errors

Overtemperature warning

ECU ground shift (two selectable thresholds)

Rigorous error handling based on diagnostics

Supply failure early warning allows critical data to be stored

23 bits of access-protected RAM is available e.g. for logging of cyclic problems

Reporting in a single SPI message; no assembly of multiple SPI frames needed

Limp-home output signal for activating application hardware in case system enters

Fail-safe mode (e.g. for switching on warning lights)

Fail-safe coded activation of Software development mode and Flash mode

Unique SPI readable device type identification

Software-initiated system reset

UJA1065_7

Product data sheet

Rev. 07 — 25 February 2010

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UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

3. Ordering information

Table 1.

Ordering information

Type number^[1]

Package

Name

Description

Version

UJA1065TW

HTSSOP32

plastic thermal enhanced thin shrink small outline package; 32 leads; SOT549-1

body width 6.1 mm; lead pitch 0.65 mm; exposed die pad

[1] UJA1065TW/5V0 is for the 5 V version; UJA1065TW/3V3 is for the 3.3 V version.

4. Block diagram

31

SENSE

BAT

MONITOR

UJA1065

32

BAT42

BAT14

27

4

V1

V2

20

V2

29

30

SYSINH

V3

17

INH/LIMP

INH

V1 MONITOR

RESET/EN

7

INTN

WAKE

TEST

18

16

6

8

WAKE

RSTN

EN

SBC

FAIL-SAFE

SYSTEM

CHIP

TEMPERATURE

WATCHDOG

OSCILLATOR

11

9

SCK

SDI

SPI

10

12

SDO

SCS

GND SHIFT

DETECTOR

26

25

3

RTLIN

LIN

24

21

22

13

14

SPLIT

CANH

CANL

TXDC

RXDC

LIN

TXDL

RXDL

HIGH

SPEED

CAN

5

23

GND

BAT42 BAT42

V2

001aac305

Fig 1. Block diagram

UJA1065_7

Product data sheet

Rev. 07 — 25 February 2010

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UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

5. Pinning information

5.1 Pinning

1

2

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

n.c.

BAT42

SENSE

V3

3

TXDL

V1

4

SYSINH

n.c.

5

RXDL

RSTN

INTN

EN

6

BAT14

RTLIN

LIN

7

8

UJA1065TW

9

SDI

SPLIT

GND

10

11

12

13

14

15

16

SDO

SCK

SCS

TXDC

RXDC

n.c.

CANL

CANH

V2

n.c.

WAKE

INH/LIMP

TEST

001aac306

Fig 2. Pin configuration

5.2 Pin description

Table 2.

Pin description

Pin Description

Symbol

n.c.

1

2

3

4

not connected

n.c.

TXDL

V1

LIN transmit data input (LOW for dominant, HIGH for recessive)

voltage regulator output for the microcontroller (3.3 V or 5 V depending on the

SBC version)

RXDL

RSTN

INTN

5

6

7

LIN receive data output (LOW when dominant, HIGH when recessive)

reset output to microcontroller (active LOW; will detect clamping situations)

interrupt output to microcontroller (active LOW; open-drain, wire-AND this pin to

other ECU interrupt outputs)

EN

8

enable output (active HIGH; push-pull, LOW with every reset/watchdog

overflow)

SDI

9

SPI data input

SDO

SCK

SCS

TXDC

RXDC

n.c.

10

11

12

13

14

15

16

SPI data output (floating when pin SCS is HIGH)

SPI clock input

SPI chip select input (active LOW)

CAN transmit data input (LOW for dominant; HIGH for recessive)

CAN receive data output (LOW when dominant; HIGH when recessive)

not connected

TEST

test pin (should be connected to ground in application)

UJA1065_7

Product data sheet

Rev. 07 — 25 February 2010

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UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

Table 2.

Pin description …continued

Symbol

Pin Description

INH/LIMP 17

inhibit/limp-home output (BAT14 related, push-pull, default floating)

local wake-up input (BAT42 related, continuous or cyclic sampling)

not connected

WAKE

n.c.

18

19

20

21

22

23

24

25

26

27

28

29

V2

5 V voltage regulator output for CAN; connect a buffer capacitor to this pin

CANH bus line (HIGH in dominant state)

CANL bus line (LOW in dominant state)

ground

CANH

CANL

GND

SPLIT

LIN

CAN-bus common mode stabilization output

LIN-bus line (LOW in dominant state)

LIN-bus termination resistor connection

14 V battery supply input

RTLIN

BAT14

n.c.

not connected

SYSINH

system inhibit output (BAT42 related; e.g. for controlling external DC-to-DC

converter)

V3

30

unregulated 42 V output (BAT42 related; continuous output, or Cyclic mode

synchronized with local wake-up input)

SENSE

BAT42

31

32

fast battery interrupt / chatter detector input

42 V battery supply input (connect this pin to BAT14 in 14 V applications)

The exposed die pad at the bottom of the package allows better dissipation of heat from

the SBC via the printed-circuit board. The exposed die pad is not connected to any active

part of the IC and can be left floating, or can be connected to GND for the best EMC

performance.

UJA1065_7

Product data sheet

Rev. 07 — 25 February 2010

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UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

6. Functional description

6.1 Introduction

The UJA1065 combines all peripheral functions around a microcontroller within typical

automotive networking applications into one dedicated chip. The functions are as follows:

• Power supply for the microcontroller

• Power supply for the CAN transceiver

• Switched BAT42 output

• System reset

• Watchdog with Window mode and Time-out mode

• On-chip oscillator

• High-speed CAN and LIN transceivers for serial communication; suitable for 14 V and

42 V applications

• SPI control interface

• Local wake-up input

• Inhibit or limp-home output

• System inhibit output port

• Compatibility with 42 V power supply systems

• Fail-safe behavior

6.2 Fail-safe system controller

The fail-safe system controller is the core of the UJA1065 and is supervised by a

watchdog timer that is clocked directly by the dedicated on-chip oscillator. The system

controller manages the register configuration and controls all internal functions of the

SBC. Detailed device status information is collected and presented to the microcontroller.

The system controller also provides the reset and interrupt signals.

The fail-safe system controller is a state machine. The different operating modes and the

transitions between these modes are illustrated in Figure 3. The following sections give

further details about the SBC operating modes.

UJA1065_7

Product data sheet

Rev. 07 — 25 February 2010

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UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

mode change via SPI

watchdog

trigger

Standby mode

V1: ON

SYSINH: HIGH

CAN: on-line/on-line listen/off-line

LIN: off-line

watchdog: time-out/OFF

INH/LIMP: HIGH/LOW/float

EN: HIGH/LOW

mode change via SPI

watchdog

trigger

wake-up detected with its wake-up interrupt disabled

OR mode change to Sleep with pending wake-up

mode change via SPI

OR watchdog time-out with watchdog timeout interrupt disabled

Sleep mode

Normal mode

OR watchdog OFF and I > I

with reset option

V1

thH(V1)

OR interrupt ignored > t

RSTN(INT)

V1: OFF

SYSINH: HIGH/float

CAN: on-line/on-line listen/off-line

LIN: off-line

watchdog: time-out/OFF

INH/LIMP: LOW/float

RSTN: LOW

V1: ON

SYSINH: HIGH

OR RSTN falling edge detected

OR V1 undervoltage detected

OR illegal Mode register code

CAN: all modes available

LIN: all modes available

watchdog: window

INH/LIMP: HIGH/LOW/float

EN: HIGH/LOW

flash entry enabled (111/001/111 mode sequence)

OR mode change to Sleep with pending wake-up

OR watchdog not properly served

OR interrupt ignored > t

RSTN(INT)

OR RSTN falling edge detected

OR V1 undervoltage detected

OR illegal Mode register code

EN: LOW

wake-up detected

OR watchdog time-out

OR V3 overload detected

init Normal mode

via SPI successful

Start-up mode

V1: ON

SYSINH: HIGH

CAN: on-line/on-line listen/off-line

LIN: off-line

init Normal mode

via SPI successful

supply connected

for the first time

watchdog: start-up

INH/LIMP: HIGH/LOW/float

EN: LOW

init Flash mode via SPI

AND flash entry enabled

t > t

WD(init)

OR SPI clock count <> 16

OR RSTN falling edge detected

OR RSTN released and V1 undervoltage detected

OR illegal Mode register code

watchdog

trigger

leave Flash mode code

OR watchdog time-out

OR interrupt ignored > t

RSTN(INT)

OR RSTN falling edge detected

OR V1 undervoltage detected

OR illegal Mode register code

Restart mode

Flash mode

V1: ON

SYSINH: HIGH

CAN: on-line/on-line listen/off-line

LIN: off-line

V1: ON

SYSINH: HIGH

wake-up detected

AND oscillator ok

CAN: all modes available

LIN: all modes available

watchdog: time-out

INH/LIMP: HIGH/LOW/float

EN: HIGH/LOW

AND t > t

ret

watchdog: start-up

INH/LIMP: LOW/float

EN: LOW

t > t

WD(init)

OR SPI clock count <> 16

OR RSTN falling edge detected

OR RSTN released and V1 undervoltage detected

OR illegal Mode register code

Fail-safe mode

V1: OFF

SYSINH: HIGH/float

CAN: on-line/on-line listen/off-line

LIN: off-line

oscillator fail

OR RSTN externally clamped HIGH detected > t

OR RSTN externally clamped LOW detected > t

RSTN(CHT)

RSTN(CLT)

from any

mode

OR V1 undervoltage detected > t

V1(CLT)

watchdog: OFF

INH/LIMP: LOW

RSTN: LOW

EN: LOW

001aad180

Fig 3. Main state diagram

UJA1065_7

Product data sheet

Rev. 07 — 25 February 2010

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UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

6.2.1 Start-up mode

Start-up mode is the ‘home page’ of the SBC. This mode is entered when battery and

ground are connected for the first time. Start-up mode is also entered after any event that

results in a system reset. The reset source information is provided by the SBC to support

different software initialization cycles that depend on the reset event.

It is also possible to enter Start-up mode via a wake-up from Standby mode, Sleep mode

or Fail-safe mode. Such a wake-up can originate either from the CAN-bus, the LIN-bus or

from the local WAKE pin.

On entering Start-up mode a lengthened reset time t_RSTNLis observed. This reset time is

either user-defined (via the RLC bit in the System Configuration register) or defaults to the

value as given in Section 6.13.12. During the reset lengthening time pin RSTN is held

LOW by the SBC.

When the reset time is completed (pin RSTN is released and goes HIGH) the watchdog

timer will wait for initialization. If the watchdog initialization is successful, the selected

operating mode (Normal mode or Flash mode) will be entered. Otherwise the Restart

mode will be entered.

6.2.2 Restart mode

The purpose of the Restart mode is to give the application a second chance to start up,

should the first attempt from Start-up mode fail. Entering Restart mode will always set the

reset lengthening time t_RSTNLto the higher value to guarantee the maximum reset length,

regardless of previous events.

If start-up from Restart mode is successful (the previous problems do not reoccur and

watchdog initialization is successful), then the selected operating mode will be entered.

From Restart mode this must be Normal mode. If problems persist or if V1 fails to start up,

then Fail-safe mode will be entered.

6.2.3 Fail-safe mode

Severe fault situations will cause the SBC to enter Fail-safe mode. Fail-safe mode is also

entered if start-up from Restart mode fails. Fail-safe mode offers the lowest possible

system power consumption from the SBC and from the external components controlled by

the SBC.

A wake-up (via the CAN-bus, the LIN-bus or the WAKE pin) is needed to leave Fail-safe

mode. This is only possible if the on-chip oscillator is running correctly. The SBC restarts

from Fail-safe mode with a defined delay t_ret, to guarantee a discharged V1 before

entering Start-up mode. Regulator V1 will restart and the reset lengthening time t_RSTNLis

set to the higher value; see Section 6.5.1.

6.2.4 Normal mode

Normal mode gives access to all SBC system resources, including CAN, LIN, INH/LIMP

and EN. Therefore in Normal mode the SBC watchdog runs in (programmable) Window

mode, for strictest software supervision. Whenever the watchdog is not properly served a

system reset is performed.

Interrupts from SBC to the host microcontroller are also monitored. A system reset is

performed if the host microcontroller does not respond within t_RSTN(INT)

.

UJA1065_7

Product data sheet

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UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

Entering Normal mode does not activate the CAN or LIN transceiver automatically. The

CAN Mode Control (CMC) bit must be used to activate the CAN medium if required,

allowing local cyclic wake-up scenarios to be implemented without affecting the CAN-bus.

The LIN Mode Control (LMC) bit must be used to activate the LIN medium if required,

allowing local cyclic wake-up scenarios to be implemented without affecting the LIN-bus.

6.2.5 Standby mode

In Standby mode the system is set into a state with reduced current consumption.

Entering Standby mode overrides the CMC bit, allowing the CAN transceiver to enter the

low-power mode autonomously. The watchdog will, however, continue to monitor the

microcontroller (Time-out mode) since it is powered via pin V1.

In the event that the host microcontroller can provide a low-power mode with reduced

current consumption in its Standby mode or Stop mode, the watchdog can be switched off

entirely in Standby mode of the SBC. The SBC monitors the microcontroller supply current

to ensure that there is no unobserved phase with disabled watchdog and running

microcontroller. The watchdog will remain active until the supply current drops below

I_thL(V1). Below this current limit the watchdog is disabled.

Should the current increase to I_thH(V1), e.g. as result of a microcontroller wake-up from

application specific hardware, the watchdog will start operating again with the previously

used time-out period. If the watchdog is not triggered correctly, a system reset will occur

and the SBC will enter Start-up mode.

If Standby mode is entered from Normal mode with the selected watchdog OFF option,

the watchdog will use the maximum time-out as defined for Standby mode until the supply

current drops below the current detection threshold; the watchdog is now OFF. If the

current increases again, the watchdog is immediately activated, again using the maximum

watchdog time-out period. If the watchdog OFF option is selected during Standby mode,

the last used watchdog period will define the time for the supply current to fall below the

current detection threshold. This allows the user to align the current supervisor function to

the application needs.

Generally, the microcontroller can be activated from Standby mode via a system reset or

via an interrupt without reset. This allows implementation of differentiated start-up

behavior from Standby mode, depending on the application needs:

• If the watchdog is still running during Standby mode, the watchdog can be used for

cyclic wake-up behavior of the system. A dedicated Watchdog Time-out Interrupt

Enable (WTIE) bit enables the microcontroller to decide whether to receive an

interrupt or a hardware reset upon overflow. The interrupt option will be cleared in

hardware automatically with each watchdog overflow to ensure that a failing main

routine is detected while the interrupt service still operates. So the application

software must set the interrupt behavior each time before a standby cycle is entered.

• Any wake-up via the CAN-bus or the LIN-bus together with a local wake-up event will

force a system reset event or an interrupt to the microcontroller. So it is possible to

exit Standby mode without any system reset if required.

UJA1065_7

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UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

When an interrupt event occurs the application software has to read the Interrupt register

within t_RSTN(INT). Otherwise a fail-safe system reset is forced and Start-up mode will be

entered. If the application has read out the Interrupt register within the specified time, it

can decide whether to switch into Normal mode via an SPI access or to stay in Standby

mode.

The following operations are possible from Standby mode:

• Cyclic wake-up by the watchdog via an interrupt signal to the microcontroller (the

microcontroller is triggered periodically and checked for the correct response)

• Cyclic wake-up by the watchdog via a reset signal (a reset is performed periodically;

the SBC provides information about the reset source to allow different start

sequences after reset)

• Wake-up by activity on the CAN-bus or LIN-bus via an interrupt signal to the

microcontroller

• Wake-up by bus activity on the CAN-bus or LIN-bus via a reset signal

• Wake-up by increasing the microcontroller supply current without a reset signal

(where a stable supply is needed for the microcontroller RAM contents to remain valid

and wake-up from an external application not connected to the SBC)

• Wake-up by increasing the microcontroller supply current with a reset signal

• Wake-up due to a falling edge at pin WAKE forcing an interrupt to the microcontroller

• Wake-up due to a falling edge at pin WAKE forcing a reset signal

6.2.6 Sleep mode

In Sleep mode the microcontroller power supply (V1) and the INH/LIMP controlled

external supplies are switched off entirely, resulting in minimum system power

consumption. In this mode, the watchdog runs in Time-out mode or is completely off.

Entering Sleep mode results in an immediate LOW level on pin RSTN, thus stopping any

operation of the microcontroller. The INH/LIMP output is floating in parallel and pin V1 is

disabled. Only pin SYSINH can remain active to support the V2 voltage supply; this

depends on the V2C bit. It is also possible for V3 to be ON, OFF or in Cyclic mode to

supply external wake-up switches.

If the watchdog is not disabled in software, it will continue to run and force a system reset

upon overflow of the programmed period time. The SBC enters Start-up mode and pin V1

becomes active again. This behavior can be used for a cyclic wake-up from Sleep mode.

Depending on the application, the following operations can be selected from Sleep mode:

• Cyclic wake-up by the watchdog (only in Time-out mode); a reset is performed

periodically, the SBC provides information about the reset source to allow different

start sequences after reset

• Wake-up by activity on the CAN-bus, LIN-bus or falling edge at pin WAKE

• An overload on V3, only if V3 is in a cyclic or in continuously on mode

UJA1065_7

Product data sheet

Rev. 07 — 25 February 2010

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UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

6.2.7 Flash mode

Flash mode can only be entered from Normal mode by entering a specific Flash mode

entry sequence. This fail-safe control sequence comprises three consecutive write

accesses to the Mode register, within the legal windows of the watchdog, using the

operating mode codes 111, 001 and 111 respectively. As a result of this sequence, the

SBC will enter Start-up mode and perform a system reset with the related reset source

information (bits RSS[3:0] = 0110).

From Start-up mode the application software now has to enter Flash mode within t_WD(init)

by writing Operating Mode code 011 to the Mode register. This feeds back a successfully

received hardware reset (handshake between the SBC and the microcontroller). The

transition from Start-up mode to Flash mode is possible only once after completing the

Flash entry sequence.

The application can also decide not to enter Flash mode but to return to Normal mode by

using the Operating Mode code 101 for handshaking. This erases the Flash mode entry

sequence.

The watchdog behavior in Flash mode is similar to its time-out behavior in Standby mode,

but Operating Mode code 111 must be used for serving the watchdog. If this code is not

used or if the watchdog overflows, the SBC immediately forces a reset and enters Start-up

mode. Flash mode is properly exited using the Operating Mode code 110 (leave Flash

mode), which results in a system reset with the corresponding reset source information.

Other Mode register codes will cause a forced reset with reset source code ‘illegal Mode

register code’.

6.3 On-chip oscillator

The on-chip oscillator provides the clock signal for all digital functions and is the timing

reference for the on-chip watchdog and the internal timers.

If the on-chip oscillator frequency is too low or the oscillator is not running at all, there is

an immediate transition to Fail-safe mode. The SBC will stay in Fail-safe mode until the

oscillator has recovered to its normal frequency and the system receives a wake-up

event.

6.4 Watchdog

The watchdog provides the following timing functions:

• Start-up mode; needed to give the software the opportunity to initialize the system

• Window mode; detects too early and too late accesses in Normal mode

• Time-out mode; detects a too late access, can also be used to restart or interrupt the

microcontroller from time to time (cyclic wake-up function)

• Off mode; fail-safe shut-down during operation thus preventing any blind spots in the

system supervision

The watchdog is clocked directly by the on-chip oscillator.

To guarantee fail-safe control of the watchdog via the SPI, all watchdog accesses are

coded with redundant bits. Therefore, only certain codes are allowed for a proper

watchdog service.

UJA1065_7

Product data sheet

Rev. 07 — 25 February 2010

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UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

The following corrupted watchdog accesses result in an immediate system reset:

• Illegal watchdog period coding; only ten different codes are valid

• Illegal operating mode coding; only six different codes are valid

Any microcontroller driven mode change is synchronized with a watchdog access by

reading the mode information and the watchdog period information from the same

register. This enables an easy software flow control with defined watchdog behavior when

switching between different software modules.

6.4.1 Watchdog start-up behavior

Following any reset event the watchdog is used to monitor the ECU start-up procedure. It

observes the behavior of the RSTN pin for any clamping condition or interrupted reset

wire. In case the watchdog is not properly served within t_WD(init), another reset is forced

and the monitoring procedure is restarted. In case the watchdog is again not properly

served, the system enters Fail-safe mode (see also Figure 3, Start-up and Restart

modes).

6.4.2 Watchdog window behavior

Whenever the SBC enters Normal mode, the Window mode of the watchdog is activated.

This ensures that the microcontroller operates within the required speed; a too fast as well

as a too slow operation will be detected. Watchdog triggering using the Window mode is

illustrated in Figure 4.

period

too early

trigger window

50 %

100 %

trigger

restarts

period

trigger

via SPI

last

trigger point

earliest possible

trigger point

latest possible

trigger point

trigger restarts period

(with different duration if

desired)

50 %

100 %

trigger

window

too early

new period

trigger

via SPI

earliest

possible

trigger

point

latest

possible

trigger

point

mce626

Fig 4. Watchdog triggering using Window mode

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The SBC provides 10 different period timings, scalable with a 4-factor watchdog prescaler.

The period can be changed within any valid trigger window. Whenever the watchdog is

triggered within the window time, the timer will be reset to start a new period.

The watchdog window is defined to be between 50 % and 100 % of the nominal

programmed watchdog period. Any too early or too late watchdog access or wrong Mode

register code access will result in an immediate system reset, entering Start-up mode.

6.4.3 Watchdog time-out behavior

Whenever the SBC operates in Standby mode, in Sleep mode or in Flash mode, the

active watchdog operates in Time-out mode. The watchdog has to be triggered within the

actual programmed period time; see Figure 5. The Time-out mode can be used to provide

cyclic wake-up events to the host microcontroller from Standby and Sleep modes.

period

trigger range

time-out

trigger

via SPI

earliest

possible

trigger

point

latest

possible

trigger

point

trigger restarts period

(with different duration if

desired)

trigger range

new period

time-out

mce627

Fig 5. Watchdog triggering using Time-out mode

In Standby and in Flash mode the nominal periods can be changed with any SPI access to

the Mode register.

Any illegal watchdog trigger code results in an immediate system reset, entering Start-up

mode.

6.4.4 Watchdog OFF behavior

The watchdog can be switched off completely in Standby and Sleep modes. For fail-safe

reasons this is only possible if the microcontroller has stopped program execution. To

ensure that there is no program execution, the V1 supply current is monitored by the SBC

while the watchdog is switched off.

When selecting the watchdog OFF code, the watchdog remains active until the

microcontroller supply current has dropped below the current monitoring threshold I_thL(V1)

.

After the supply current has dropped below the threshold, the watchdog stops at the end

of the watchdog period. In case the supply current does not drop below the monitoring

threshold, the watchdog stays active.

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If the microcontroller supply current increases above I_thH(V1)while the watchdog is OFF,

the watchdog is restarted with the last used watchdog period time and a watchdog restart

interrupt is forced, if enabled.

In case of a direct mode change towards Standby mode with watchdog OFF selected, the

longest possible watchdog period is used. It should be noted that in Sleep mode V1

current monitoring is not active.

6.5 System reset

The reset function of the UJA1065 offers two signals to deal with reset events:

• RSTN; the global ECU system reset

• EN; a fail-safe global enable signal

6.5.1 RSTN pin

The system reset pin (RSTN) is a bidirectional input/output. Pin RSTN is active LOW with

selectable pulse length upon the following events; see Figure 3:

• Power-on (first battery connection) or V_BAT42below power-on reset threshold voltage

• Low V1 supply

• V1 current above threshold during Standby mode while watchdog OFF behavior is

selected

• V3 is down due to short-circuit condition during Sleep mode

• RSTN externally forced LOW, falling edge event

• Successful preparation for Flash mode completed

• Successful exit from Flash mode

• Wake-up from Standby mode via pins CAN, LIN or WAKE if programmed accordingly,

or any wake-up event from Sleep mode

• Wake-up event from Fail-safe mode

• Watchdog trigger failures (too early, overflow, wrong code)

• Illegal mode code via SPI applied

• Interrupt not served within t_RSTN(INT)

All of these reset events have a dedicated reset source in the System Status register to

allow distinction between the different events.

The SBC will lengthen any reset event to 1 ms or 20 ms to ensure that external hardware

is properly reset. After the first battery connection, a short power-on reset of 1 ms is

provided after voltage V1 is present. Once started, the microcontroller can set the Reset

Length Control (RLC) bit within the System Configuration register; this allows the reset

pulse to be adjusted for future reset events. With this bit set, all reset events are

lengthened to 20 ms. Due to fail-safe behavior, this bit will be set automatically (to 20 ms)

in Restart mode or Fail-safe mode. With this mechanism it is guaranteed that an

erroneously shortened reset pulse will restart any microcontroller, at least within the

second trial by using the long reset pulse.

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The behavior of pin RSTN is illustrated in Figure 6. The duration of t_RSTNLdepends on the

setting of the RLC bit (defines the reset length). Once an external reset event is detected

the system controller enters the Start-up mode. The watchdog now starts to monitor pin

RSTN as illustrated in Figure 7. If the RSTN pin is not released in time then Fail-safe

mode is entered as shown in Figure 3.

V1

V

rel(UV)(V1)

det(UV)(V1)

time

power-up

under-

voltage

missing

watchdog voltage

access spike

under-

power-

down

V

RSTN

time

t

RSTNL

coa054

Fig 6. Reset pin behavior

V

RSTN

time

t

RSTNL

t

WD(init)

RSTN

externally

forced LOW

V

RSTN

time

t

RSTNL

t

RSTN externally forced LOW

WD(init)

001aad181

Fig 7. Reset timing diagram

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Pin RSTN is monitored for a continuously clamped LOW situation. Once the SBC pulls pin

RSTN HIGH but pin RSTN level remains LOW for longer than t_RSTN(CLT), the SBC

immediately enters Fail-safe mode since this indicates an application failure.

The SBC also detects if pin RSTN is clamped HIGH. If the HIGH-level remains on the pin

for longer than t_RSTN(CHT)while pin RSTN is driven internally to a LOW-level by the SBC,

the SBC falls back immediately to Fail-safe mode since the microcontroller cannot be

reset any more. By entering Fail-safe mode, the V1 voltage regulator shuts down and the

microcontroller stops.

Additionally, chattering reset signals are handled by the SBC in such a way that the

system safely falls back to Fail-safe mode with the lowest possible power consumption.

6.5.2 EN output

Pin EN can be used to control external hardware such as power components or as a

general purpose output if the system is running properly. During all reset events, when pin

RSTN is pulled LOW, the EN control bit will be cleared, pin EN will be pulled LOW and will

stay LOW after pin RSTN is released. In Normal mode and Flash mode of the SBC, the

microcontroller can set the EN control bit via the SPI. This results in releasing pin EN

which then returns to a HIGH-level.

6.6 Power supplies

6.6.1 BAT14, BAT42 and SYSINH

The SBC has two supply pins, pin BAT42 and pin BAT14. Pin BAT42 supplies most of the

SBC where pin BAT14 only supplies the linear voltage regulators and the INH/LIMP output

pin. This supply architecture allows different supply strategies including the use of

external DC-to-DC converters controlled by the pin SYSINH.

6.6.1.1 SYSINH output

The SYSINH output is a high-side switch from BAT42. It is activated whenever the SBC

requires supply voltage to pin BAT14, e.g. when V1 or V2 is on (see Figure 3 and

Figure 8). Otherwise pin SYSINH is floating. Pin SYSINH can be used to control e.g. an

external step-down voltage regulator to BAT14, to reduce power consumption in

low-power modes.

6.6.2 SENSE input

The SBC has a dedicated SENSE pin for dynamic monitoring of the battery contact of an

electronic control unit. Connecting this pin in front of the polarity protection diode of the

ECU provides an early warning if the battery becomes disconnected.

6.6.3 Voltage regulators V1 and V2

The UJA1065 has two independent voltage regulators supplied out of the BAT14 pin.

Regulator V1 is intended to supply the microcontroller. Regulator V2 is reserved for the

high-speed CAN transceiver.

6.6.3.1 Voltage regulator V1

The V1 voltage is continuously monitored to provide the system reset signal when

undervoltage situations occur. Whenever the V1 voltage falls below one of the three

programmable thresholds, a hardware reset is forced.

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A dedicated V1 supply comparator (V1 Monitor) observes V1 for undervoltage events

lower than V_UV(VFI). This allows the application to receive a supply warning interrupt in

case one of the lower V1 undervoltage reset thresholds is selected.

The V1 regulator is overload protected. The maximum output current available from pin

V1 depends on the voltage applied to pin BAT14 according to the characteristics section.

For thermal reasons, the total power dissipation should be taken into account.

6.6.3.2 Voltage regulator V2

Voltage regulator V2 provides a 5 V supply for the CAN transmitter. The pin V2 is intended

for the connection of external buffering capacitors.

V2 is controlled autonomously by the CAN transceiver control system and is activated on

any detected CAN-bus activity, or if the CAN transceiver is enabled by the application

microcontroller. V2 is short-circuit protected and will be disabled in case of an overload

situation. Dedicated bits in the System Diagnosis register and the Interrupt register

provide V2 status feedback to the application.

Besides the autonomous control of V2 there is a software accessible bit which allows

activation of V2 manually (V2C). This allows V2 to be used for other application purposes

when CAN is not actively used (e.g. while CAN is off-line). Generally, V2 should not be

used for other application hardware while CAN is in use.

If the regulator V2 is not able to start within the V2 clamped LOW time (> t_V2(CLT)), or if a

short-circuit has been detected during an already activated V2, then V2 is disabled and

the V2D bit in the System Diagnosis register is cleared. Additionally the CTC bit in the

Physical Layer Control register is set and the V2C bit is cleared.

Reactivation of voltage regulator V2 can be done by:

• Clearing the CTC bit while CAN is in Active mode

• Wake-up via CAN while CAN is not in Active mode

• Setting the V2C bit

• When entering CAN Active mode

6.6.4 Switched battery output V3

V3 is a high-side switched BAT42-related output which is used to drive external loads

such as wake-up switches or relays. The features of V3 are as follows:

• Three application-controlled operating modes; On, Off and Cyclic.

• Two different cyclic modes allow the supply of external wake-up switches; these

switches are powered intermittently, thus reducing the system’s power consumption in

case a switch is continuously active; the wake-up input of the SBC is synchronized

with the V3 cycle time.

• The switch is protected against current overloads. If V3 is overloaded, pin V3 is

automatically disabled. The corresponding System Diagnosis register bit is reset and

an interrupt is forced (if enabled). During Sleep mode, a wake-up is forced and the

corresponding reset source code becomes available in the RSS bits of the System

Status register. This signals that the wake-up source via V3 supplied wake-up

switches has been lost.

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6.7 CAN transceiver

The integrated high-speed CAN transceiver of the UJA1065 is an advanced ISO 11898-2

and ISO 11898-5 compliant transceiver. In addition to standard high-speed CAN

transceivers the UJA1065 transceiver provides the following features:

• Enhanced error handling and reporting of bus and RXD/TXD failures; these failures

are separately identified in the System Diagnosis register

• Integrated autonomous control system for determining the mode of the CAN

transceiver

• Ground shift detection with two selectable warning levels, to detect possible local

ground problems before the CAN communication is affected

• On-line Listen mode with global wake-up message filter allows partial networking

• Bus connections are truly floating when power is off

6.7.1 Mode control

The controller of the CAN transceiver provides four modes of operation: Active mode,

On-line mode, On-line Listen mode and Off-line mode; see Figure 8.

In the Diagnosis register two dedicated CAN status bits (CANMD) are available to signal

the mode of the transceiver.

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High-speed CAN/LIN fail-safe system basis chip

Active mode

V2: ON/OFF (V2D)

transmitter: ON/OFF (CTC)

RXDC: bit stream/HIGH (V2D)

SPLIT: ON/OFF (CSC/V2D)

CPNC = 0 or 1

Normal mode OR Flash mode

AND CMC = 0 AND CPNC = 1

Normal mode OR Flash mode

AND CMC = 1

Normal mode OR Flash mode

AND CMC = 0 AND CPNC = 0

Normal mode OR Flash mode

AND CMC = 1

CPNC = 1

On-line mode

On-line Listen mode

V2: ON/OFF (V2C/V2D)

transmitter: OFF

RXDC: wake-up (active LOW)

SPLIT: ON/OFF (CSC/V2D)

CPNC = 0

Normal mode

OR Flash mode

AND CMC = 1

V2: ON/OFF (V2C/V2D)

transmitter: OFF

RXDC: V1

SPLIT: ON/OFF (CSC/V2D)

CPNC = 1

global wake-up message detected

OR CPNC = 0

CAN wake-up filter passed

AND CPNC = 1

no activity for t > t

off-line

CAN wake-up filter passed

AND CPNC = 0

no activity for t > t

off-line

Off-line mode

V2: ON/OFF (V2C/V2D)

transmitter: OFF

RXDC: V1

power-on

SPLIT: OFF

CPNC = 0 or 1

001aad182

Fig 8. States of the CAN transceiver

6.7.1.1 Active mode

In Active mode the CAN transceiver can transmit data to and receive data from the

CAN-bus. To enter Active mode the CMC bit must be set in the Physical Layer register

and the SBC must be in Normal mode or Flash mode. In Active mode voltage regulator V2

is activated automatically.

The CTC bit can be used to set the CAN transceiver to a Listen-only mode. The

transmitter output stage is disabled in this mode.

After an overload condition on voltage regulator V2, the CTC bit must be cleared for

reactivating the CAN transmitter.

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When leaving Active mode the CAN transmitter is disabled and the CAN receiver is

monitoring the CAN-bus for a valid wake-up. The CAN termination is then working

autonomously.

6.7.1.2 On-line mode

In On-line mode the CAN-bus pins and pin SPLIT (if enabled) are biased to the normal

levels. The CAN transmitter is deactivated and RXDC reflects the CAN wake-up status. A

CAN wake-up event is signalled to the microcontroller by clearing RXDC.

If the bus stays continuously dominant or recessive for the Off-line time (t_off-line), the

Off-line state will be entered.

6.7.1.3 On-line Listen mode

On-line Listen mode behaves similar to On-line mode, but all activity on the CAN-bus, with

exception of a special global wake-up request, is ignored. The global wake-up request is

described in Section 6.7.2. Pin RXDC is kept HIGH.

6.7.1.4 Off-line mode

Off-line mode is the low-power mode of the CAN transceiver. The CAN transceiver is

disabled to save supply current and is high-ohmic terminated to ground.

The CAN off-line time is programmable in two steps with the CAN Off-line Timer Control

(COTC) bit. When entering On-line (Listen) mode from Off-line mode the CAN off-line time

is temporarily extended to t_{off-line(ext)}

.

6.7.2 CAN wake-up

To wake-up the UJA1065 via CAN it has to be distinguished between a conventional

wake-up and a global wake-up in case partial networking is enabled (bit CPNC = 1).

To pass the wake-up filter for a conventional wake-up a dominant, recessive, dominant,

recessive signal on the CAN-bus is needed; see Figure 9.

For a global wake-up out of On-line Listen mode two distinct CAN data patterns are

required:

• In the initial message: C6 - EE - EE - EE - EE - EE - EE - EF (hexadecimal values)

• In the global wake-up message: C6 - EE - EE - EE - EE - EE - EE - 37 (hexadecimal

values)

The second pattern must be received within t_timeoutafter receiving the first pattern. Any

CAN-ID can be used with these data patterns.

If the CAN transceiver enters On-line Listen mode directly from Off-line mode the global

wake-up message is sufficient to wake-up the SBC. This pattern must be received within

t_timeoutafter entering On-line Listen mode. Should t_timeoutelapse before receiving the

global wake-up message, then both messages are required for a CAN wake-up.

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High-speed CAN/LIN fail-safe system basis chip

CANH

CANL

wake-up

t

CAN(dom1)

t

CAN(dom2)

CAN(reces)

001aad446

Fig 9. CAN wake-up timing diagram.

6.7.3 Termination control

In Active mode, On-line mode and On-line Listen mode, CANH and CANL are terminated

to 0.5 × V_V2via R_i. In Off-line mode CANH and CANL are terminated to GND via R_i. If V2

is disabled due to an overload condition both pins become floating.

6.7.4 Bus, RXD and TXD failure detection

The UJA1065 can distinguish between bus, RXD and TXD failures as indicated in Table 3.

All failures are signalled separately in the CANFD bits in the System Diagnosis register.

Any change (detection and recovery) forces an interrupt to the microcontroller, if this

interrupt is enabled.

Table 3.

Failure

CAN-bus, RXD and TXD failure detection

Description

HxHIGH

HxGND

CANH short-circuit to V_CC, V_BAT14or V_BAT42

CANH short-circuit to GND

LxHIGH

LxGND

CANL short-circuit to V_CC, V_BAT14or V_BAT42

CANL short-circuit to GND

HxL

CANH short-circuit to CANL

Bus dom

TXDC dom

RXDC reces

RXDC dom

bus is continuously clamped dominant

pin TXDC is continuously clamped dominant

pin RXDC is continuously clamped recessive

pin RXDC is continuously clamped dominant

6.7.4.1 TXDC dominant clamping

If the TXDC pin is clamped dominant for longer than t_TXDC(dom)the CAN transmitter is

disabled. After the TXDC pin becomes recessive the transmitter is reactivated

automatically when detecting bus activity or manually by setting and clearing the CTC bit.

6.7.4.2 RXDC recessive clamping

If the RXDC pin is clamped recessive while the CAN-bus is dominant the CAN transmitter

is disabled. The transmitter is reactivated automatically when RXDC becomes dominant

or manually by setting and clearing the CTC bit.

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6.7.4.3 GND shift detection

The SBC can detect ground shifts in reference to the CAN-bus. Two different ground shift

detection levels can be selected with the GSTHC bit in the Configuration register. The

failure can be read out in the System Diagnosis register. Any detected or recovered GND

shift event is signalled with an interrupt, if enabled.

6.8 LIN transceiver

The integrated LIN transceiver of the UJA1065 is a LIN 2.0 compliant transceiver. The

transceiver has the following features:

• SAE J2602 compliant and compatible with LIN revision 1.3

• Fail-safe LIN termination to BAT42 via dedicated RTLIN pin

• Enhanced error handling and reporting of bus and TXD failures; these failures are

separately identified in the System Diagnosis register

6.8.1 Mode control

The controller of the LIN transceiver provides two modes of operation: Active mode and

Off-line mode; see Figure 10. In Off-line mode the transmitter and receiver do not

consume current, but wake-up events will be recognized by the separate wake-up

receiver.

Active mode

transmitter: ON/OFF (LTC)

receiver: ON

RXDL: bitstream

RTLIN: ON/75 μA

SBC enters

Stand-by, Start-up,

Restart or Fail-safe mode

SBC enters

Normal or Flash mode

AND LMC = 1

OR LMC = 0

Off-line mode

transmitter: OFF

receiver: wake-up

SBC enters

Fail-safe mode

power-on

RXDL: wake-up status

RTLIN: 75 μA/OFF

001aad184

Fig 10. States LIN transceiver

6.8.1.1 Active mode

In Active mode the LIN transceiver can transmit data to and receive data from the LIN bus.

To enter Active mode the LMC bit must be set in the Physical Layer Control register and

the SBC must be in Normal mode or Flash mode.

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The LTC bit can be used to set the LIN transceiver to a Listen-only mode. The transmitter

output stage is disabled in this mode.

When leaving Active mode the LIN transmitter is disabled and the LIN receiver is

monitoring the LIN-bus for a valid wake-up.

6.8.1.2 Off-line mode

Off-line mode is the low-power mode of the LIN transceiver. The LIN transceiver is

disabled to save supply current. Pin RXDL reflects any wake-up event at the LIN-bus.

6.8.2 LIN wake-up

For a remote wake-up via LIN a LIN-bus signal is required as shown in Figure 11.

LIN

wake-up

t

BUS(LIN)

001aad447

Fig 11. LIN wake-up timing diagram

6.8.3 Termination control

The RTLIN pin is in one of 3 different states: RTLIN = on, RTLIN = off or RTLIN = 75 μA;

see Figure 12.

Active mode and receiver dominant > t

LIN(dom)(det)

OR Off-line mode

RTLIN = 75 μA

RTLIN = ON

supplied directly

out of BAT42

supplied directly

out of BAT42

Active mode and receiver recessive > t

LIN(dom)(rec)

OR mode change to Active mode

Off-line mode

AND receiver recessive > t

LIN(dom)(rec)

Off-line mode

AND receiver dominant > t

mode change to Active mode

LIN(dom)(det)

power-on

RTLIN = OFF

001aad183

Fig 12. States of the RTLIN pin

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During Active mode, with no short-circuit between the LIN-bus and GND, pin RTLIN

provides an internal switch to BAT42. For master and slave operation an external resistor,

1 kΩ or 30 kΩ respectively, can be applied between pins RTLIN and LIN. An external

diode in series with the termination resistor is not required due to the incorporated internal

diode.

6.8.4 LIN slope control

The LSC bit in the Physical Layer Control register offers a choice between two LIN slope

times, allowing communication up to 20 kbit/s (normal) or up to 10.4 kbit/s (low slope).

6.8.5 LIN driver capability

Setting the LDC bit in the Physical Layer Control register will increase the driver capability

of the LIN output stage. This feature is used in auto-addressing systems, where the

standard LIN 2.0 drive capability is insufficient.

6.8.6 Bus and TXDL failure detection

The SBC handles and reports the following LIN-bus related failures:

• LIN-bus shorted to ground

• LIN-bus shorted to V_BAT14or V_BAT42; the transmitter is disabled

• TXDL clamped dominant; the transmitter is disabled

These failure events force an interrupt to the microcontroller whenever the status changes

and the corresponding interrupt is enabled.

6.8.6.1 TXDL dominant clamping

If the TXDL pin is clamped dominant for longer than t_{TXDL(dom)(dis)}the LIN transmitter is

disabled. After the TXDL pin becomes recessive the transmitter is reactivated

automatically when detecting bus activity or manually by setting and clearing the LTC bit.

6.8.6.2 LIN dominant clamping

When the LIN-bus is clamped dominant for longer than t_{LIN(dom)(det)}(which is longer than

t_{TXDL(dom)(dis)}), the state of the LIN termination is changed according to Figure 12.

6.8.6.3 LIN recessive clamping

If the LIN bus pin is clamped recessive while TXDL is driven dominant the LIN transmitter

is disabled. The transmitter is reactivated automatically when the LIN bus becomes

dominant or manually by setting and clearing the LTC bit.

6.9 Inhibit and limp-home output

The INH/LIMP output pin is a 3-state output pin which can be used either as an inhibit for

an extra (external) voltage regulator, or as a ‘limp-home’ output. The pin is controlled via

the ILEN bit and ILC bit in the System Configuration register; see Figure 13.

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state change via SPI

OR enter Fail-safe mode

INH/LIMP:

HIGH

INH/LIMP:

LOW

ILEN = 1

ILC = 1

ILEN = 1

ILC = 0

state change via SPI

OR (enter Start-up mode after

wake-up reset, external reset

or V1 undervoltage)

state change via SPI

OR enter Fail-safe mode

OR enter Restart mode

OR enter Sleep mode

state change via SPI

INH/LIMP:

floating

ILEN = 0

ILC = 1/0

power-on

001aad178

Fig 13. States of the INH/LIMP pin

When pin INH/LIMP is used as inhibit output, a pull-down resistor to GND ensures a

default LOW level. The pin can be set to HIGH according to the state diagram.

When pin INH/LIMP is used as limp-home output, a pull-up resistor to V_BAT42ensures a

default HIGH level. The pin is automatically set to LOW when the SBC enters Fail-safe

mode.

6.10 Wake-up input

The WAKE input comparator is triggered by negative edges on pin WAKE. Pin WAKE has

an internal pull-up resistor to BAT42. It can be operated in two sampling modes which are

selected via the WAKE Sample Control bit (WSC):

• Continuous sampling (with an internal clock) if the bit is set

• Sampling synchronized to the cyclic behavior of V3 if the bit is cleared; see Figure 14.

This is to save bias current within the external switches in low-power operation. Two

repetition times are possible, 16 ms and 32 ms.

If V3 is continuously ON, the WAKE input will be sampled continuously, regardless of the

level of bit WSC.

The dedicated bits Edge Wake-up Status (EWS) and WAKE Level Status (WLS) in the

System Status register reflect the actual status of pin WAKE. The WAKE port can be

disabled by clearing the WEN bit in the System Configuration register.

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t

w(CS)

t

on(CS)

V

3

approximately 70 %

t

su(CS)

sample

active

button pushed

button released

signal already HIGH

due to biasing (history)

V

WAKE

signal remains LOW

due to biasing (history)

flip flop

V

INTN

001aac307

Fig 14. Pin WAKE, cyclic sampling via V3

6.11 Interrupt output

Pin INTN is an open-drain interrupt output. It is forced LOW whenever at least one bit in

the Interrupt register is set. By reading the Interrupt register all bits are cleared. The

Interrupt register will also be cleared during a system reset (RSTN LOW).

As the microcontroller operates typically with an edge-sensitive interrupt port, pin INTN

will be HIGH for at least t_INTNafter each read-out of the Interrupt register. Without further

interrupts within t_INTNpin INTN stays HIGH, otherwise it will revert to LOW again.

To prevent the microcontroller from being slowed down by repetitive interrupts, in Normal

mode some interrupts are only allowed to occur once per watchdog period; see

Section 6.13.7.

If an interrupt is not read out within t_RSTN(INT)a system reset is performed.

6.12 Temperature protection

The temperature of the SBC chip is monitored as long as the microcontroller voltage

regulator V1 is active. To avoid an unexpected shutdown of the application by the SBC,

the temperature protection will not switch off any part of the SBC or activate a defined

system stop of its own accord. If the temperature is too high it generates an interrupt to

the microcontroller, if enabled, and the corresponding status bit will be set. The

microcontroller can then decide whether to switch off parts of the SBC to decrease the

chip temperature.

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High-speed CAN/LIN fail-safe system basis chip

6.13 SPI interface

The Serial Peripheral Interface (SPI) provides the communication link with the

microcontroller, supporting multi-slave and multi-master operation. The SPI is configured

for full duplex data transfer, so status information is returned when new control data is

shifted in. The interface also offers a read-only access option, allowing registers to be

read back by the application without changing the register content.

The SPI uses four interface signals for synchronization and data transfer:

• SCS - SPI chip select; active LOW

• SCK - SPI clock; default level is LOW due to low-power concept

• SDI - SPI data input

• SDO - SPI data output; floating when pin SCS is HIGH

Bit sampling is performed on the falling clock edge and data is shifted on the rising clock

edge; see Figure 15.

SCS

SCK

SDI

01

02

03

04

15

16

sampled

X

MSB

14

13

12

01

LSB

X

MSB

SDO

X

floating

mce634

Fig 15. SPI timing protocol

UJA1065_7

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High-speed CAN/LIN fail-safe system basis chip

To protect against wrong or illegal SPI instructions, the SBC detects the following SPI

failures:

• SPI clock count failure (wrong number of clock cycles during one SPI access): only

16 clock periods are allowed within one SCS cycle. Any deviation from the 16 clock

cycles results in an SPI failure interrupt, if enabled. The access is ignored by the SBC.

In Start-up and Restart mode a reset is forced instead of an interrupt

• Forbidden mode changes according to Figure 3 result in an immediate system reset

• Illegal Mode register code. Undefined operating mode or watchdog period coding

results in an immediate system reset; see Section 6.13.3

6.13.1 SPI register mapping

Any control bit which can be set by software is readable by the application. This allows

software debugging as well as control algorithms to be implemented.

Watchdog serving and mode setting is performed within the same access cycle; this only

allows an SBC mode change whilst serving the watchdog.

Each register carries 12 data bits; the other 4 bits are used for register selection and

read/write definition.

6.13.2 Register overview

The SPI interface gives access to all SBC registers; see Table 4. The first two bits (A1 and

A0) of the message header define the register address, the third bit is the read register

select bit (RRS) to select one out of two possible feedback registers; the fourth bit (RO)

allows ‘read only’ access to one of the feedback registers. Which of the SBC registers can

be accessed also depends on the SBC operating mode.

Table 4.

Register

Register overview

Operating

Write access (RO = 0)

Read access (RO = 0 or RO = 1)

address bits mode

(A1, A0)

Read Register Select

(RRS) bit = 0

Read Register Select

(RRS) bit = 1

00

01

all modes

Mode register

System Status register

System Diagnosis register

Interrupt register

Normal mode;

Standby mode;

Flash mode

Interrupt Enable register

Interrupt Enable Feedback

register

Start-up mode; Special Mode register

Restart mode

Interrupt Enable Feedback

register

Special Mode Feedback

register

10

11

Normal mode;

Standby mode register

System Configuration

Feedback register

General Purpose Feedback

register 0

Start-up mode; General Purpose register 0 System Configuration

Restart mode;

Flash mode

General Purpose Feedback

register 0

Feedback register

Normal mode;

Standby mode register

Physical Layer Control

Feedback register

General Purpose Feedback

register 1

Start-up mode; General Purpose register 1 Physical Layer Control

General Purpose Feedback

register 1

Restart mode;

Flash mode

Feedback register

UJA1065_7

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High-speed CAN/LIN fail-safe system basis chip

6.13.3 Mode register

In the Mode register the watchdog is defined and re-triggered, and the SBC operating

mode is selected. The Mode register also contains the global enable output bit (EN) and

the Software Development Mode (SDM) control bit. During system operation cyclic

access to the Mode register is required to serve the watchdog. This register can be written

to in all modes.

At system start-up the Mode register must be written to within t_WD(init)from releasing

RSTN (HIGH-level on pin RSTN). Any write access is checked for proper watchdog and

system mode coding. If an illegal code is detected, access is ignored by the SBC and a

system reset is forced in accordance with the state diagram of the system controller; see

Figure 3.

Table 5.

Bit

Mode register bit description (bits 15 to 12 and 5 to 0)

Symbol

Description

Value

Function

15 and 14 A1, A0

register address 00

select Mode register

13

12

RRS

RO

Read Register

Select

1

0

1

0

read System Diagnosis register

read System Status register

Read Only

read selected register without writing to Mode register

read selected register and write to Mode register

11 to 6

5 to 3

NWP[5:0]

OM[2:0]

see Table 6

Operating Mode 001

Normal mode

010

011

100

101

110

111

Standby mode

initialize Flash mode^[1]

Sleep mode

initialize Normal mode

leave Flash mode

Flash mode ^[1]

2

SDM

Software

Development

Mode

1

0

Software development mode enabled^[2]

normal watchdog, interrupt, reset monitoring and fail-safe

behavior

1

0

EN

-

Enable

1

0

EN output pin HIGH

EN output pin LOW

reserved

reserved for future use; should remain cleared to ensure

compatibility with future functions which might use this bit

[1] Flash mode can be entered only with the watchdog service sequence ‘Normal mode to Flash mode to Normal mode to Flash mode’,

while observing the watchdog trigger rules. With the last command of this sequence the SBC forces a system reset, and enters Start-up

mode to prepare the microcontroller for flash memory download. The four RSS bits in the System Status register reflect the reset source

information, confirming the Flash entry sequence. By using the Initializing Flash mode (within t_WD(init)after system reset) the SBC will

now successfully enter Flash mode.

[2] See Section 6.14.1.

UJA1065_7

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Table 6.

Bit

Mode register bit description (bits 11 to 6)^[1]

Symbol

Description

Value

Time

Normal

Standby

Flash mode Sleep mode

mode (ms)

(ms)

11 to 6

NWP[5:0]

Nominal

Watchdog Period

00 1001

00 1100

01 0010

01 0100

01 1011

10 0100

10 1101

11 0011

11 0101

11 0110

00 1001

00 1100

01 0010

01 0100

01 1011

10 0100

10 1101

11 0011

11 0101

11 0110

00 1001

00 1100

01 0010

01 0100

01 1011

10 0100

10 1101

11 0011

11 0101

11 0110

4

20

160

8

40

320

WDPRE = 00 (as

set in the Special

Mode register)

16

32

40

48

56

64

72

80

6

80

640

160

1024

2048

3072

4096

6144

8192

OFF^[3]

240

320

640

1024

2048

4096

OFF^[2]

30

1024

2048

4096

8192

30

Nominal

Watchdog Period

12

24

48

60

72

84

96

108

120

10

20

40

80

100

120

140

160

180

200

60

480

WDPRE = 01 (as

set in the Special

Mode register)

120

960

240

1536

3072

4608

6144

9216

12288

OFF^[3]

400

480

960

1536

3072

6144

OFF^[2]

50

1536

3072

6144

12288

50

Nominal

Watchdog Period

100

800

WDPRE = 10 (as

set in the Special

Mode register)

200

1600

2560

5120

7680

10240

15360

20480

OFF^[3]

400

800

1600

1560

5120

10240

OFF^[2]

1600

1560

5120

10240

20480

UJA1065_7

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High-speed CAN/LIN fail-safe system basis chip

Table 6.

Bit

Mode register bit description (bits 11 to 6)^[1]…continued

Symbol

Description

Value

Time

Normal

Standby

Flash mode Sleep mode

mode (ms)

(ms)

11 to 6

NWP[5:0]

Nominal

Watchdog Period

00 1001

00 1100

01 0010

01 0100

01 1011

10 0100

10 1101

11 0011

11 0101

11 0110

14

70

560

28

140

1120

WDPRE = 11 (as

set in the Special

Mode register)

56

280

2240

3584

7168

10752

14336

21504

28672

OFF^[3]

112

140

168

196

244

252

280

560

1120

2240

3584

7168

14336

OFF^[2]

1120

2240

3584

7168

14336

28672

[1] The nominal watchdog periods are directly related to the SBC internal oscillator. The given values are valid for f_osc= 512 kHz.

[2] See Section 6.4.4.

[3] The watchdog is immediately disabled on entering Sleep mode, with watchdog OFF behavior selected, because pin RSTN is

immediately pulled LOW by the mode change. V1 is switched off after pulling pin RSTN LOW to guarantee a safe Sleep mode entry

without dips on V1; see Section 6.4.4.

6.13.4 System Status register

This register allows status information to be read back from the SBC. This register can be

read in all modes.

Table 7.

Bit

System Status register bit description

Symbol

Description

Value

Function

15 and 14 A1, A0

register address

Read Register Select

Read Only

00

0

read System Status register

13

12

RRS

RO

1

read System Status register without writing to Mode

register

0

read System Status register and write to Mode register

UJA1065_7

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UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

Table 7.

Bit

System Status register bit description …continued

Symbol

Description

Value

Function

11 to 8

RSS[3:0]

Reset Source^[1]

0000

power-on reset; first connection of BAT42 or BAT42 below

power-on voltage threshold or RSTN was forced LOW

externally

0001

0010

cyclic wake-up out of Sleep mode

low V1 supply; V1 has dropped below the selected reset

threshold

0011

0100

V1 current above threshold within Standby mode while

watchdog OFF behavior and reset option (V1CMC bit) are

selected

V3 voltage is down due to overload occurring during Sleep

mode

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

1

SBC successfully left Flash mode

SBC ready to enter Flash mode

CAN wake-up event

LIN wake-up event

local wake-up event (via pin WAKE)

wake-up out of Fail-safe mode

watchdog overflow

watchdog not initialized in time; t_WD(init)exceeded

watchdog triggered too early; window missed

illegal SPI access

interrupt not served within t_RSTN(INT)

CAN wake-up detected; cleared upon read

no CAN wake-up

7

6

5

4

3

2

1

0

CWS

LWS

CAN Wake-up Status

LIN Wake-up Status

Edge Wake-up Status

WAKE Level Status

0

1

LIN wake-up detected; cleared upon read

no LIN wake-up

0

EWS

WLS

1

pin WAKE negative edge detected; cleared upon read

pin WAKE no edge detected

0

1

pin WAKE above threshold

0

pin WAKE below threshold

TWS

Temperature Warning

Status

1

chip temperature exceeds the warning limit

chip temperature is below the warning limit

Software Development mode on

Software Development mode off

pin EN output activated (V1-related HIGH level)

pin EN output released (LOW level)

0

SDMS

ENS

Software Development

Mode Status

1

0

Enable Status

1

0

PWONS

Power-on reset Status

1

power-on reset; cleared after a successfully entered

Normal mode

0

no power-on reset

[1] The RSS bits are updated with each reset event and not cleared. The last reset event is captured.

UJA1065_7

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UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

6.13.5 System Diagnosis register

This register allows diagnosis information to be read back from the SBC. This register can

be read in all modes.

Table 8.

Bit

System Diagnosis register bit description

Symbol

Description

Value

Function

15 and 14 A1, A0

register address

Read Register Select

Read Only

00

1

read System Diagnosis register

13

12

RRS

RO

1

read System Diagnosis register without writing to Mode

register

0

1

0

read System Diagnosis register and write to Mode register

system GND shift is outside selected threshold

system GND shift is within selected threshold

pin TXDC is continuously clamped dominant

pin RXDC is continuously clamped dominant

the bus is continuously clamped dominant

pin RXDC is continuously clamped recessive

reserved

11

GSD

Ground Shift Diagnosis

10 to 7

CANFD [3:0] CAN Failure Diagnosis 1111

1110

1100

1101

1011

1010

1001

1000

0111

0110

0101

0100

0011

0010

0001

0000

reserved

pin CANH is shorted to pin CANL

pin CANL is shorted to V_CC, V_BAT14or V_BAT42

reserved

CANH is shorted to GND

CANL is shorted to GND

CANH is shorted to V_CC, V_BAT14or V_BAT42

reserved

no failure

6 and 5

LINFD[1:0]

LIN Failure Diagnosis

11

10

01

00

1

TXDL is clamped dominant

LIN is shorted to GND (dominant clamped)

LIN is shorted to VBAT (recessive clamped)

no failure

4

3

2

V3D

V2D

V1D

V3 Diagnosis

V2 Diagnosis

V1 Diagnosis

OK

0

fail; V3 is disabled due to an overload situation

OK^[1]

1

0

fail; V2 is disabled due to an overload situation

OK; V1 always above V_UV(VFI)since last read access

1

0

fail; V1 was below V_UV(VFI)since last read access; bit is set

again with read access

UJA1065_7

Product data sheet

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High-speed CAN/LIN fail-safe system basis chip

Table 8.

Bit

System Diagnosis register bit description …continued

Symbol

Description

Value

11

Function

1 and 0

CANMD [1:0] CAN Mode Diagnosis

CAN is in Active mode

10

CAN is in On-line mode

CAN is in On-line Listen mode

CAN is in Off-line mode, or V2 is not active

01

00

[1] V2D will be set when V2 is reactivated after a failure. See Section 6.6.3.2.

6.13.6 Interrupt Enable register and Interrupt Enable Feedback register

These registers allow setting, clearing and reading back the interrupt enable bits of the

SBC.

Table 9.

Bit

Interrupt Enable and Interrupt Enable Feedback register bit description

Symbol

Description

Value

Function

15 and 14 A1, A0

register address

Read Register Select

01

1

select the Interrupt Enable register

read the Interrupt register

13

12

RRS

RO

0

read the Interrupt Enable Feedback register

Read Only

1

read the register selected by RRS without writing to

Interrupt Enable register

0

1

read the register selected by RRS and write to Interrupt

Enable register

11

WTIE

Watchdog Time-out

Interrupt Enable^[1]

a watchdog overflow during Standby mode causes an

interrupt instead of a reset event (interrupt based cyclic

wake-up feature)

0

1

no interrupt forced on watchdog overflow; a reset is forced

instead

10

9

OTIE

Over-Temperature

Interrupt Enable

exceeding or dropping below the temperature warning limit

causes an interrupt

0

1

no interrupt forced

GSIE

Ground Shift Interrupt

Enable

exceeding or dropping below the GND shift limit causes an

interrupt

0

1

no interrupt forced

8

SPIFIE

SPI clock count Failure

Interrupt Enable

wrong number of CLK cycles (more than, or less than 16)

forces an interrupt; from Start-up mode and Restart mode a

reset is performed instead of an interrupt

0

no interrupt forced; SPI access is ignored if the number of

cycles does not equal 16

7

6

5

BATFIE

VFIE

BAT Failure Interrupt

Enable

1

0

1

0

1

falling edge at SENSE forces an interrupt

no interrupt forced

Voltage Failure Interrupt

Enable

clearing of V1D, V2D or V3D forces an interrupt

no interrupt forced

CANFIE

CAN Failure Interrupt

Enable

any change of the CAN Failure status bits forces an

interrupt

0

1

0

no interrupt forced

4

LINFIE

LIN Failure Interrupt

Enable

any change of the LIN Failure status bits forces an interrupt

no interrupt forced

UJA1065_7

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UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

Table 9.

Interrupt Enable and Interrupt Enable Feedback register bit description …continued

Bit

Symbol

Description

Value

Function

3

WIE

WAKE Interrupt

Enable^[2]

1

a negative edge at pin WAKE generates an interrupt in

Normal mode, Flash mode or Standby mode

0

1

a negative edge at pin WAKE generates a reset in Standby

mode; no interrupt in any other mode

2

1

WDRIE

CANIE

Watchdog Restart

Interrupt Enable

a watchdog restart during watchdog OFF generates an

interrupt

0

1

no interrupt forced

CAN Interrupt Enable

CAN-bus event results in a wake-up interrupt in Standby

mode and in Normal or Flash mode (unless CAN is in

Active mode already)

0

1

CAN-bus event results in a reset in Standby mode; no

interrupt in any other mode

0

LINIE

LIN Interrupt Enable

LIN-bus event results in a wake-up interrupt in Standby

mode and in Normal or Flash mode (unless LIN is in Active

mode already)

0

LIN-bus event results in a reset in Standby mode; no

interrupt in any other mode

[1] This bit is cleared automatically upon each overflow event. It has to be set in software each time the interrupt behavior is required

(fail-safe behavior).

[2] WEN (in the System Configuration register) has to be set to activate the WAKE port function globally.

6.13.7 Interrupt register

The Interrupt register allows the cause of an interrupt event to be read. The register is

cleared upon a read access and upon any reset event. Hardware ensures that no interrupt

event is lost in case there is a new interrupt forced while reading the register. After reading

the Interrupt register pin INTN is released for t_INTNto guarantee an edge event at pin

INTN.

The interrupts can be classified into two groups:

• Timing critical interrupts which require immediate reaction (SPI clock count failure

which needs a new SPI command to be resent immediately, and a BAT failure which

needs critical data to be saved immediately into the nonvolatile memory)

• Interrupts which do not require an immediate reaction (overtemperature, Ground Shift,

CAN and LIN failures, V1, V2 and V3 failures and the wake-ups via CAN, LIN and

WAKE. These interrupts will be signalled in Normal mode to the microcontroller once

per watchdog period (maximum); this prevents overloading the microcontroller with

unexpected interrupt events (e.g. a chattering CAN failure). However, these interrupts

are reflected in the Interrupt register

UJA1065_7

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NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

Table 10. Interrupt register bit description

Bit

Symbol

Description

Value

Function

15 and 14 A1, A0

register address

Read Register Select

Read Only

01

1

read Interrupt register

13

12

RRS

RO

1

read the Interrupt register without writing to the Interrupt

Enable register

0

1

read the Interrupt register and write to the Interrupt Enable

register

11

WTI

Watchdog Time-out

Interrupt

a watchdog overflow during Standby mode has caused an

interrupt (interrupt-based cyclic wake-up feature)

0

1

0

1

0

1

no interrupt

10

9

OTI

OverTemperature

Interrupt

the temperature warning status (TWS) has changed

no interrupt

GSI

Ground Shift Interrupt

the ground shift diagnosis bit (GSD) has changed

no interrupt

8

SPIFI

SPI clock count Failure

Interrupt

wrong number of CLK cycles (more than, or less than 16)

during SPI access

0

no interrupt; SPI access is ignored if the number of CLK

cycles does not equal 16

7

6

5

4

3

2

BATFI

VFI

BAT Failure Interrupt

1

0

falling edge at pin SENSE has forced an interrupt

no interrupt

Voltage Failure Interrupt 1

0

V1D, V2D or V3D has been cleared

no interrupt

CANFI

LINFI

WI

CAN Failure Interrupt

LIN Failure Interrupt

Wake-up Interrupt

1

0

1

0

1

0

1

CAN failure status has changed

no interrupt

LIN failure status has changed

no interrupt

a negative edge at pin WAKE has been detected

no interrupt

WDRI

Watchdog Restart

Interrupt

A watchdog restart during watchdog OFF has caused an

interrupt

0

1

0

1

0

no interrupt

1

0

CANI

LINI

CAN Wake-up Interrupt

LIN Wake-up Interrupt

CAN wake-up event has caused an interrupt

no interrupt

LIN wake-up event has caused an interrupt

no interrupt

UJA1065_7

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UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

6.13.8 System Configuration register and System Configuration Feedback register

These registers allow configuration of the behavior of the SBC, and allow the settings to

be read back.

Table 11. System Configuration and System Configuration Feedback register bit description

Bit

Symbol

Description

Value

Function

15 and 14 A1, A0

register address

Read Register Select

10

1

select System Configuration register

read the General Purpose Feedback register 0

read the System Configuration Feedback register

13

12

RRS

RO

0

Read Only

1

read register selected by RRS without writing to System

Configuration register

0

read register selected by RRS and write to System

Configuration register

11 and 10

9

-

reserved

reserved for future use; should remain cleared to ensure

compatibility with future functions which might use this bit

GSTHC

GND Shift Threshold

Control

1

V_th(GSD)(cm)widened threshold

V_th(GSD)(cm)normal threshold

0

8

RLC

Reset Length Control

1^[1]

t_RSTNLlong reset lengthening time selected

t_RSTNLshort reset lengthening time selected

Cyclic mode 2; t_w(CS)long period; see Figure 14

Cyclic mode 1; t_w(CS)short period; see Figure 14

continuously ON

0

7 and 6

V3C[1:0]

V3 Control

11

10

01

00

0

OFF

5

4

-

reserved

reserved for future use; should remain cleared to ensure

compatibility with future functions which might use this bit

V1CMC

V1 Current Monitor

Control

1

0

an increasing V1 current causes a reset if the watchdog

was disabled during Standby mode

an increasing V1 current just reactivates the watchdog

during Standby mode

3

2

1

0

WEN

WSC

ILEN

ILC

Wake Enable^[2]

1

0

1

0

1

0

1

0

WAKE pin enabled

WAKE pin disabled

Wake Sample Control

INH/LIMP Enable

INH/LIMP Control

Wake mode cyclic sample

Wake mode continuous sample

INH/LIMP pin active (See ILC bit)

INH/LIMP pin floating

INH/LIMP pin HIGH if ILEN bit is set

INH/LIMP pin LOW if ILEN bit is set

[1] RLC is set automatically with entering Restart mode or Fail-safe mode. This guarantees a safe reset period in case of serious failure

situations. External reset spikes are lengthened by the SBC until the programmed reset length is reached.

[2] If WEN is not set, the WAKE port is completely disabled. There is no change of the bits EWS and WLS within the System Status register.

UJA1065_7

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UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

6.13.9 Physical Layer Control register and Physical Layer Control Feedback

register

These registers allow configuration of the CAN transceiver and LIN transceiver of the SBC

and allow the settings to be read back.

Table 12. Physical Layer Control and Physical Layer Control Feedback register bit description

Bit

Symbol

Description

Value

Function

15 and 14 A1, A0

register address

Read Register Select

11

1

select Physical Layer Control register

read the General Purpose Feedback register 1

read the Physical Layer Control Feedback register

13

12

RRS

RO

0

Read Only

1

read the register selected by RRS without writing to the

Physical Layer Control register

0

read the register selected by RRS and write to Physical

Layer Control register

11

10

V2C

V2 Control

1

0

1

V2 remains active in CAN Off-line mode

V2 is OFF in CAN Off-line mode

CPNC

CAN Partial Networking

Control

CAN transceiver enters On-line Listen mode instead of

On-line mode; cleared whenever the SBC enters On-line

mode or Active mode

0

1

0

1

0

1

On-line Listen mode disabled

9

8

7

COTC

CTC

CAN Off-line Time

Control^[1]

t_off-linelong period (extended to t_{off-line(ext)}after wake-up)

t_off-lineshort period (extended to t_{off-line(ext)}after wake-up)

CAN transmitter is disabled

CAN Transmitter

Control^[2]

CAN transmitter is enabled

CRC

CAN Receiver Control

TXD signal is forwarded directly to RXD for self-test

purposes (loopback behavior); only if CTC = 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

TXD signal is not forwarded to RXD (normal behavior)

CAN Active mode (in Normal mode and Flash mode only)

CAN Active mode disabled

6

5

4

3

2

1

0

CMC

CSC

LMC

LSC

CAN Mode Control

CAN Split Control

LIN Mode Control

LIN Slope Control

LIN Driver Control

LIN Wake-up Enable

CAN SPLIT pin active

CAN SPLIT pin floating

LIN Active mode (in Normal mode and Flash mode only)

LIN Active mode disabled

up to 10.4 kbit/s (low slope)

up to 20 kbit/s (normal)

LDC

LWEN

LTC

increased LIN driver current capability

LIN driver in conformance with the LIN 2.0 standard

wake-up via the LIN-bus enabled

wake-up via the LIN-bus disabled

LIN transmitter is disabled

LIN Transmitter

Control^[3]

LIN transmitter is enabled

[1] For the CAN transceiver to enter Off-Line mode from On-line or On-line Listen mode a minimum time without bus activity is needed. This

minimum time t_off-lineis defined by COTC; see Section 6.7.1.4.

[2] In case of an RXDC / TXDC interfacing failure the CAN transmitter is disabled without setting CTC. Recovery from such a failure is

automatic when CAN communication (with correct interfacing levels) is received. Manual recovery is also possible by setting and

clearing the CTC bit under software control.

UJA1065_7

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UJA1065

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High-speed CAN/LIN fail-safe system basis chip

[3] In case of an RXDL / TXDL interfacing failure the LIN transmitter is disabled without setting LTC. Recovery from such a failure is

automatic when LIN communication (with correct interfacing levels) is received. Manual recovery is also possible by setting and clearing

the LTC bit under software control.

6.13.10 Special Mode register and Special Mode Feedback register

These registers allow configuration of global SBC parameters during start-up of a system

and allow the settings to be read back.

Table 13. Special Mode register and Special Mode Feedback register bit description

Bit

Symbol

Description

Value

Function

15 and 14 A1, A0

register address

Read Register Select

01

0

select Special Mode register

read the Interrupt Enable Feedback register

read the Special Mode Feedback register

13

12

RRS

RO

1

Read Only

1

read the register selected by RRS without writing to the

Special Mode register

0

read the register selected by RRS and write to the

Special Mode register

11 and 10

9

-

reserved

reserved for future use; should remain cleared to ensure

compatibility with future functions which might use this bit

ISDM

Initialize Software

Development Mode^[1]

1

0

initialization of software development mode

normal watchdog interrupt, reset monitoring and fail-safe

behavior

8

ERREM

Error-pin Emulation

Mode

1

pin EN reflects the status of the CANFD bits:

EN is set if CANFD = 0000 (no error)

EN is cleared if CANFD is not 0000 (error)

pin EN behaves as an enable pin; see Section 6.5.2

0

7

-

reserved

reserved for future use; should remain cleared to ensure

compatibility with future functions which might use this bit

6 and 5

WDPRE [1:0] Watchdog Prescaler

00

01

10

11

10

01

00

0

watchdog prescale factor 1

watchdog prescale factor 1.5

watchdog prescale factor 2.5

watchdog prescale factor 3.5

V1 reset threshold = 0.9 × V_V1(nom)

4 and 3

2 to 0

V1RTHC [1:0] V1 Reset Threshold

Control

[2]

V1 reset threshold = 0.7 × V_V1(nom)

V1 reset threshold = 0.8 × V_V1(nom)

V1 reset threshold = 0.9 × V_V1(nom)

-

reserved

reserved for future use; should remain cleared to ensure

compatibility with future functions which might use this bit

[1] See Section 6.14.1.

[2] Not supported in the UJA1065TW/3V3 version.

UJA1065_7

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UJA1065

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6.13.11 General Purpose registers and General Purpose Feedback registers

The UJA1065 offers two 12-bit General Purpose registers (and accompanying General

Purpose Feedback registers) with no predefined bit definition. These registers can be

used by the microcontroller for advanced system diagnosis or for storing critical system

status information outside the microcontroller. After Power-up General Purpose register 0

will contain a ‘Device Identification Code’ consisting of the SBC type and SBC version.

This code is available until it is overwritten by the microcontroller (as indicated by the DIC

bit).

Table 14. General Purpose register 0 and General Purpose Feedback register 0 bit description

Bit

Symbol

A1, A0

RRS

Description

Value

Function

15, 14

13

register address

Read Register Select

10

1

read the General Purpose Feedback register 0

read the System Configuration Feedback register

0

12

RO

Read Only

1

read the register selected by RRS without writing to the

General Purpose register 0

0

read the register selected by RRS and write to the General

Purpose register 0

11

DIC

Device Identification

Control^[1]

1

0

General Purpose register 0 contains user-defined bits

General Purpose register 0 contains the Device

Identification Code

10 to 0

GP0[10:0]

General Purpose bits^[2]

1

0

user-defined

[1] The Device Identification Control bit is cleared during power-up of the SBC, indicating that General Purpose register 0 is loaded with the

Device Identification Code. Any write access to General Purpose register 0 will set the DIC bit, regardless of the value written to DIC.

[2] During power-up the General Purpose register 0 is loaded with a ‘Device Identification Code’ consisting of the SBC type and SBC

version, and the DIC bit is cleared.

Table 15. General Purpose register 1 and General Purpose Feedback register 1 bit description

Bit

Symbol

Description

Value

Function

15 and 14 A1, A0

register address

Read Register Select

11

1

select General Purpose register 1

read the General Purpose Feedback register 1

read the Physical Layer Control Feedback register

13

12

RRS

RO

0

Read Only

1

read the register selected by RRS without writing to the

General Purpose register 1

0

read the register selected by RRS and write to the General

Purpose register

11 to 0

GP1[11:0]

General Purpose bits

1

0

user-defined

6.13.12 Register configurations at reset

At power-on, Start-up and Restart mode the setting of the SBC registers is predefined.

UJA1065_7

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UJA1065

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High-speed CAN/LIN fail-safe system basis chip

Table 16. System Status register: status at reset

Symbol

RSS

Name

Power-on

0000 (power-on reset) any value except 1100

Start-up ^[1]

Restart ^[1]

Reset Source Status

CAN Wake-up Status

0000 or 0010 or 1100 or 1110

no change

CWS

0 (no CAN wake-up)

1 if reset is caused by a

CAN wake-up, otherwise

no change

LWS

EWS

LIN Wake-up Status

0 (no LIN wake-up)

1 if reset is caused by a

LIN wake-up, otherwise no

change

no change

Edge Wake-up Status 0 (no edge detected)

1 if reset is caused by a

wake-up via pin WAKE,

otherwise no change

WLS

TWS

WAKE Level Status

actual status

Temperature Warning

Status

0 (no warning)

SDMS

ENS

Software Development actual status

Mode Status

actual status

Enable Status

0 (EN = LOW)

0 if ERREM = 0, otherwise 0 if ERREM = 0, otherwise

actual CAN failure status

PWONS

Power-on Status

1 (power-on reset)

no change

[1] Depends on history.

Table 17. System Diagnosis register: status at reset

Symbol

GSD

Name

Power-on

Start-up

Restart

Ground Shift Diagnosis 0 (OK)

actual status

CANFD

LINFD

V3D

CAN Failure Diagnosis 0000 (no failure)

LIN Failure Diagnosis 00 (no failure)

V3 Diagnosis

V2 Diagnosis

V1 Diagnosis

1 (OK)

0 (fail)

V2D

V1D

CANMD

CAN Mode Diagnosis 00 (Off-line)

Table 18. Interrupt Enable register and Interrupt Enable Feedback register: status at reset

Symbol

Name

Power-on

Start-up

Restart

All

all bits

0 (interrupt disabled)

no change

Table 19. Interrupt register: status at reset

Symbol

Name

Power-on

Start-up

Restart

All

all bits

0 (no interrupt)

UJA1065_7

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UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

Table 20. System Configuration register and System Configuration Feedback register: status at reset

Symbol

Name

Power-on

Start-up

Restart

Fail-Safe

GSTHC

GND Shift level

0 (normal)

no change

Threshold Control

RLC

Reset Length Control

V3 Control

0 (short)

00 (off)

no change

1 (long)

V3C

no change

V1CMC

V1 Current Monitor

Control

0 (watchdog

restart)

WEN

WSC

ILEN

Wake Enable

1 (enabled)

no change

Wake Sample Control 0 (control)

INH/LIMP Enable

0 (floating)

see Figure 13

if ILC = 1,

0 (floating) if ILC = 1, 1 (active)

otherwise no change

ILC

INH/LIMP Control

0 (LOW)

no change

0 (LOW)

Table 21. Physical Layer Control register and Physical Layer Control Feedback register: status at reset

Symbol

V2C

Name

Power-on

Start-up

Restart

Fail-Safe

V2 Control

0 (auto)

no change

0 (auto)

CPNC

CAN Partial Networking 0 (On-line Listen

Control

0 if reset is caused

by a CAN wake-up,

otherwise no change

0 (On-line Listen

mode disabled)

1 (long)

COTC

CTC

CAN Off-line Time

Control

no change

CAN Transmitter

Control

0 (on)

no change

CRC

CMC

CAN Receiver Control 0 (normal)

no change

CAN Mode Control

0 (Active mode

disabled)

CSC

LMC

CAN Split Control

LIN Mode Control

0 (off)

no change

0 (Active mode

disabled)

LSC

LIN Slope Control

LIN Driver Control

LIN Wake-up Enable

0 (normal)

0 (LIN 2.0)

1 (enabled)

no change

LDC

LWEN

LTC

LIN Transmitter Control 0 (on)

UJA1065_7

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NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

Table 22. Special Mode register: status at reset

Symbol

ISDM

Name

Power-on

0 (no)

Start-up

Restart

Initialize Software Development Mode

Error pin emulation mode

Watchdog Prescale Factor

V1 Reset Threshold Control

no change

00 (90 %)

ERREM

WDPRE

V1RTHC

0 (EN function)

00 (factor 1)

00 (90 %)

Table 23. General Purpose register 0 and General Purpose Feedback register 0: status at reset

Symbol

DIC

Name

Power-on

Start-up

Restart

Device Identification Control

general purpose bits 10 to 7 (version)

0 (Device ID)

Mask version

no change

GP0[10:7]

GP0[6:0]

general purpose bits 6 to 0 (SBC type) 000 0101 (UJA1065) no change

Table 24. General Purpose register 1 and General Purpose Feedback register 1: status at reset

Symbol

Name

Power-on

Start-up

Restart

GP1[11:0]

general purpose bits 11 to 0

0000 0000 0000

no change

6.14 Test modes

6.14.1 Software development mode

The Software development mode is intended to support software developers in writing

and pretesting application software without having to work around watchdog triggering

and without unwanted jumps to Fail-safe mode.

In Software development mode the following events do not force a system reset:

• Watchdog overflow in Normal mode

• Watchdog window miss

• Interrupt time-out

• Elapsed start-up time

However, in case of a watchdog trigger failure the reset source information is still provided

in the System Status register as if there was a real reset event.

The exclusion of watchdog related resets allows simplified software testing, because

possible problems in the watchdog triggering can be indicated by interrupts instead of

resets. The SDM bit does not affect the watchdog behavior in Standby and Sleep mode.

This allows the cyclic wake-up behavior to be evaluated during Standby and Sleep mode

of the SBC.

All transitions to Fail-safe mode are disabled. This allows working with an external

emulator that clamps the reset line LOW in debugging mode. A V1 undervoltage of more

than t_V1(CLT)is the only exception that results in entering Fail-safe mode (to protect the

SBC). Transitions from Start-up mode to Restart mode are still possible.

UJA1065_7

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UJA1065

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High-speed CAN/LIN fail-safe system basis chip

There are two possibilities to enter Software development mode. One is by setting the

ISDM bit via the Special Mode register; possible only once after a first battery connection

while the SBC is in Start-up mode. The second possibility to enter Software development

mode is by applying the correct V_th(TEST)input voltage at pin TEST before the battery is

applied to pin BAT42.

To stay in Software development mode the SDM bit in the Mode register has to be set with

each Mode register access (i.e. watchdog triggering) regardless of how Software

development mode was entered.

The Software development mode can be exited at any time by clearing the SDM bit in the

Mode register. Reentering the Software development mode is only possible by

reconnecting the battery supply (pin BAT42), thereby forcing a new power-on reset.

6.14.2 Forced normal mode

For system evaluation purposes the UJA1065 offers the Forced normal mode. This mode

is strictly for evaluation purposes only. In this mode the characteristics as defined in

Section 9 and Section 10 cannot be guaranteed.

In Forced normal mode the SBC behaves as follows:

• SPI access (writing and reading) is blocked

• Watchdog disabled

• Interrupt monitoring disabled

• Reset monitoring disabled

• Reset lengthening disabled

• All transitions to Fail-safe mode are disabled, except a V1 undervoltage for more than

t_V1(CLT)

• V1 is started with the long reset time t_RSTNL. In case of a V1 undervoltage, a reset is

performed until V1 is restored (normal behavior), and the SBC stays in Forced normal

mode; in case of an overload at V1 > t_V1(CLT)Fail-safe mode is entered

• V2 is on; overload protection active

• V3 is on; overload protection active

• CAN and LIN are in Active mode and cannot switch to Off-line mode

• INH/LIMP pin is HIGH

• SYSINH is HIGH

• EN pin at same level as RSTN pin

Forced normal mode is activated by applying the correct V_th(TEST)input voltage at the

TEST pin during first battery connection.

UJA1065_7

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UJA1065

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High-speed CAN/LIN fail-safe system basis chip

7. Limiting values

Table 25. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to GND.

Symbol

Parameter

Conditions

Min

−0.3

-

Max

+60

Unit

V

V_BAT42

BAT42 supply voltage

load dump; t ≤ 500 ms

V_BAT42≥ V_BAT14− 1 V

continuous

V

V_BAT14

BAT14 supply voltage

−0.3

+33

+45

V

load dump; t ≤ 500 ms

-

V_DC(n)

DC voltage on pins

V1 and V2

−0.3

−1.5

−0.3

−1.5

−60

+5.5

V

V3 and SYSINH

INH/LIMP

V_BAT42+ 0.3

V_BAT42+ 1.2

+60

SENSE

WAKE

CANH, CANL, SPLIT, LIN and RTLIN with respect to any other pin

+60

TXDC, RXDC, TXDL, RXDL, SDO,

SDI, SCK, SCS, RSTN, INTN and

EN

−0.3

V_V1+ 0.3

TEST

−0.3

+15

V

V_trt

transient voltage at pins CANH, CANL in accordance with

−150

+100

and LIN

ISO 7637-3

[1]

I_WAKE

T_stg

DC current at pin WAKE

storage temperature

ambient temperature

virtual junction temperature

electrostatic discharge voltage

−15

−55

−40

-

mA

°C

+150

+125

+150

T_amb

T_vj

[2]

[3]

[4]

V_esd

HBM

at pins CANH, CANL,

SPLIT, LIN, RTLIN,

WAKE, BAT42, V3,

SENSE; with respect to

GND

−8.0

+8.0

kV

at any other pin

MM; at any pin

−2.0

+2.0

kV

V

[5]

−200

+200

[1] Only relevant if V_WAKE< V_GND− 0.3 V; current will flow into pin GND.

[2] In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: T_vj= T_amb+ P_d× R_th(vj-amb), where R_th(vj-amb)

is a fixed value to be used for the calculation of T_vj. The rating for T_vjlimits the allowable combinations of power dissipation (P_d) and

ambient temperature (T_amb).

[3] Human Body Model (HBM): C = 100 pF; R = 1.5 kΩ.

[4] ESD performance according to IEC 61000-4-2 (C = 150 pF, R = 330 Ω) of pins CANH, CANL, RTH, RTL, LIN, RTLIN, WAKE, BAT42

and V3 with respect to GND was verified by an external test house. Following results were obtained:

a) Equal or better than ±4 kV (unaided)

b) Equal or better than ±20 kV (using external ESD protection: NXP Semiconductors PESD1CAN and PESD1LIN diode)

[5] Machine Model (MM): C = 200 pF; L = 0.75 μH; R = 10 Ω.

UJA1065_7

Product data sheet

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46 of 76

UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

8. Thermal characteristics

V1 dissipation

V2 dissipation

V3 dissipation

other dissipation

T

vj

6 K/W

20 K/W

23 K/W

6 K/W

T

(heat sink)

case

R

th(c-a)

amb

001aac327

Fig 16. Thermal model of the HTSSOP32 package

9. Static characteristics

Table 26. Static characteristics

T_vj= −40 °C to +150 °C, V_BAT42= 5.5 V to 52 V; V_BAT14= 5.5 V to 27 V; V_BAT42≥ V_BAT14− 1 V; unless otherwise specified. All

voltages are defined with respect to ground. Positive currents flow into the IC.^[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Supply; pin BAT42

I_BAT42

BAT42 supply

current

V1, V2 and V3 off;

CAN and LIN in Off-line

mode; OTIE = BATFIE = 0;

I_SYSINH= I_WAKE= I_RTLIN

I_LIN= 0 mA

=

V_BAT42= 8.1 V to 52 V

V_BAT42= 5.5 V to 8.1 V

-

50

70

53

70

93

76

μA

I_BAT42(add)

additional BAT42

supply current

V1 and/or V2 on;

I_SYSINH= 0 mA

V3 in Cyclic mode; I_V3= 0 mA

-

0

1

μA

V3 continuously on;

I_V3= 0 mA

30

50

T_vjwarning enabled;

OTIE = 1

-

20

40

μA

SENSE enabled; BATFIE = 1

-

2

7

μA

CAN in Active mode;

CMC = 1

750

1500

LIN in Active mode;

-

650

1300

μA

LMC = 1; V_TXDL= V_V1

I_RTLIN= I_LIN= 0 mA

;

LIN in Active mode; LMC = 1;

_TXDL= 0 V (t < t_{LIN(dom)(det)});

V

I_RTLIN= I_LIN= 0 mA

V_BAT42= 12 V

-

1.5

3

5

mA

V_BAT42= 27 V

10

UJA1065_7

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UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

Table 26. Static characteristics …continued

T_vj= −40 °C to +150 °C, V_BAT42= 5.5 V to 52 V; V_BAT14= 5.5 V to 27 V; V_BAT42≥ V_BAT14− 1 V; unless otherwise specified. All

voltages are defined with respect to ground. Positive currents flow into the IC.^[1]

Symbol

Parameter

Conditions

Min

4.45

4.75

-

Typ

Max

5

Unit

V

V_POR(BAT42)

BAT42 voltage level for setting PWONS

for power-on reset

status bit change

PWONS = 0; V_BAT42falling

-

for clearing PWONS

PWONS = 1; V_BAT42rising

-

5.5

5

V

Supply; pin BAT14

I_BAT14

BAT14 supply

current

V1 and V2 off; CAN and LIN

in Off-line mode;

2

μA

ILEN = CSC = 0;

I_INH/LIMP= I_SPLIT= 0 mA

I_BAT14(add)

additional BAT14

supply current

V1 on; I_V1= 0 mA

-

200

150

300

200

μA

V1 on; I_V1= 0 mA;

V_BAT14= 12 V

V2 on; I_V2= 0 mA

-

200

320

250

μA

V2 on; I_V2= 0 mA;

V_BAT14= 12 V

INH/LIMP enabled; ILEN = 1;

-

1

5

2

μA

I_INH/LIMP= 0 mA

CAN in Active mode;

CMC = 1;

10

mA

I_CANH= I_CANL= 0 mA

SPLIT active; CSC = 1;

-

1

-

2

mA

V

I_SPLIT= 0 mA

V_BAT14

BAT14 voltage level for normal output current

capability at V1

9

6

27

8

for high output current

capability at V1

-

V

Battery supply monitor input; pin SENSE

V_th(SENSE)

input threshold low

battery voltage

detection

1

2.5

-

3

V

release

1.7

20

5

4

V

I_IH(SENSE)

HIGH-level input

current

Normal mode; BATFIE = 1

Standby mode; BATFIE = 1

50

10

0.2

100

20

2

μA

Normal mode or Standby

mode; BATFIE = 0

-

Voltage source; pin V1^[2]; see also Figure 17 to Figure 23

V_o(V1)

output voltage

V_BAT14= 5.5 V to 18 V;

I_V1= −120 mA to −5 mA;

T_j= 25 °C

V_V1(nom)

0.1

−

V_V1(nom)

0.1

+

V

V_BAT14= 14 V; I_V1= −5 mA;

V_V1(nom)

0.025

V_V1(nom)

0.025

T_j= 25 °C

UJA1065_7

Product data sheet

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UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

Table 26. Static characteristics …continued

T_vj= −40 °C to +150 °C, V_BAT42= 5.5 V to 52 V; V_BAT14= 5.5 V to 27 V; V_BAT42≥ V_BAT14− 1 V; unless otherwise specified. All

voltages are defined with respect to ground. Positive currents flow into the IC.^[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

ΔV_V1

supply voltage

regulation

V_BAT14= 9 V to 16 V;

-

1

25

mV

I_V1= −5 mA; T_j= 25 °C

load regulation

V_BAT14= 14 V;

I_V1= −50 mA to −5 mA;

T_j= 25 °C

-

5

-

25

mV

[3]

voltage drift with

temperature

V_BAT14= 14 V; I_V1= −5 mA;

200

ppm/K

T_j= −40 °C to +150 °C

V_det(UV)(V1)

undervoltage

detection and reset

activation level

V

_BAT14= 14 V;

0.90 ×

V_V1(nom)

0.92 ×

V_V1(nom)

0.95 ×

V_V1(nom)

V

V1RTHC[1:0] = 00 or 11

V_BAT14= 14 V;

0.80 ×

V_V1(nom)

0.82 ×

V_V1(nom)

0.85 ×

V_V1(nom)

V1RTHC[1:0] = 01

V_BAT14= 14 V;

V1RTHC[1:0] = 10

0.70 ×

V_V1(nom)

0.72 ×

V_V1(nom)

0.75 ×

V_V1(nom)

V_rel(UV)(V1)

undervoltage

detection release

level

V_BAT14= 14 V;

V1RTHC[1:0] = 00 or 11

-

0.94 ×

V_V1(nom)

-

V_BAT14= 14 V;

0.84 ×

V_V1(nom)

V1RTHC[1:0] = 01

V_BAT14= 14 V;

V1RTHC[1:0] = 10

0.74 ×

V_V1(nom)

V_UV(VFI)

I_thH(V1)

I_thL(V1)

I_V1

undervoltage level

for generating a VFI

interrupt

V_BAT14= 14 V; VFIE = 1

0.90 ×

V_V1(nom)

0.93 ×

V_V1(nom)

0.97 ×

V_V1(nom)

undercurrent

threshold for

watchdog enable

−10

−6

−5

−3

−2

mA

undercurrent

threshold for

watchdog disable

−1.5

output current

capability

V_BAT14= 9 V to 27 V;

δV_V1= 0.05 × V_V1(nom)

−200

−135

−120

-

mA

Ω

V_BAT14= 9 V to 27 V;

V1 shorted to GND

−200

−110

V_BAT14= 8 V to 9 V;

δV_V1= 0.05 × V_V1(nom)

-

−120

−150

5

V_BAT14= 5.5 V to 8 V;

-

δV_V1= 0.05 × V_V1(nom)

Z_ds(on)

regulator impedance V_BAT14= 4 V to 5 V

between pins BAT14

3

and V1

UJA1065_7

Product data sheet

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49 of 76

UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

Table 26. Static characteristics …continued

T_vj= −40 °C to +150 °C, V_BAT42= 5.5 V to 52 V; V_BAT14= 5.5 V to 27 V; V_BAT42≥ V_BAT14− 1 V; unless otherwise specified. All

voltages are defined with respect to ground. Positive currents flow into the IC.^[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Voltage source; pin V2^[4]

V_o(V2)

output voltage

V_BAT14= 9 V to 16 V;

4.8

5.0

5.2

5.05

25

V

I_V2= −50 mA to −5 mA

V_BAT14= 14 V; I_V2= −10 mA;

T_j= 25 °C

4.95

5.0

V

ΔV_V2

supply voltage

regulation

V_BAT14= 9 V to 16 V;

I_V2= −10 mA; T_j= 25 °C

-

1

mV

ppm/K

mA

V

load regulation

V_BAT14= 14 V; I_V2= −50 mA

to −5 mA; T_j= 25 °C

-

50

[3]

voltage drift with

temperature

V_BAT14= 14 V; I_V2= −10 mA;

−40 °C < T_j< +150 °C

-

200

−120

-

I_V2

output current

capability

V_BAT14= 9 V to 27 V;

δV_V2= 300 mV

−200

−300

-

V_BAT14= 9 V to 27 V;

V2 shorted to GND

-

V_BAT14= 6 V to 8 V;

δV_V2= 300 mV

-

−80

−50

4.8

V_BAT14= 5.5 V;

-

δV_V2= 300 mV

V_det(UV)(V2)

undervoltage

V_BAT14= 14 V

4.5

4.6

detection threshold

Voltage source; pin V3

V_{BAT42-V3(drop)}

I_det(OL)(V3)

⎪I_L⎪

V_BAT42to V_V3voltage V_BAT42= 9 V to 52 V;

-

1.0

−60

5

V

drop

I_V3= −20 mA

overload current

V_BAT42= 9 V to 52 V

−165

-

mA

μA

detection threshold

leakage current

V_V3= 0 V; V3C[1:0] = 00

-

0

System inhibit output; pin SYSINH

V_{BAT42-SYSINH(drop)}V_BAT42to V_SYSINH

voltage drop

I_SYSINH= −0.2 mA

-

1.0

-

2.0

5

V

⎪I_L⎪

leakage current

V_SYSINH= 0 V

μA

Inhibit/limp-home output; pin INH/LIMP

V_{BAT14-INH(drop)}

V_BAT14to V_INH

voltage drop

I_INH/LIMP= −10 μA;

ILEN = ILC = 1

-

0.7

1.2

-

1.0

2.0

4

V

I_INH/LIMP= −200 μA;

ILEN = ILC = 1

-

V

I_o(INH/LIMP)

output current

capability

V_INH/LIMP= 0.4 V;

ILEN = 1; ILC = 0

0.8

-

mA

μA

⎪I_L⎪

leakage current

V_INH/LIMP= 0 V to V_BAT14

ILEN = 0

;

-

5

Wake input; pin WAKE

V_th(WAKE)wake-up voltage

threshold

pull-up input current V_WAKE= 0 V

2.0

3.3

-

5.2

V

I_WAKE(pu)

−25

−1.3

μA

UJA1065_7

Product data sheet

Rev. 07 — 25 February 2010

50 of 76

UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

Table 26. Static characteristics …continued

T_vj= −40 °C to +150 °C, V_BAT42= 5.5 V to 52 V; V_BAT14= 5.5 V to 27 V; V_BAT42≥ V_BAT14− 1 V; unless otherwise specified. All

voltages are defined with respect to ground. Positive currents flow into the IC.^[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Serial peripheral interface inputs; pins SDI, SCK and SCS

V_IH(th)

V_IL(th)

HIGH-level input

threshold voltage

0.7 × V_V1

−0.3

50

-

V_V1+ 0.3

+0.3 × V_V1

400

V

LOW-level input

threshold voltage

-

V

R_pd(SCK)

R_pu(SCS)

I_SDI

pull-down resistor at V_SCK= 2 V; V_V1≥ 2 V

pin SCK

130

-

kΩ

μA

pull-up resistor at

pin SCS

V_SCS= 1 V; V_V1≥ 2 V

50

400

input leakage current V_SDI= 0 V to V_V1

at pin SDI

−5

+5

Serial peripheral interface data output; pin SDO

I_OH

HIGH-level output

current

V_SCS= 0 V; V_O= V_V1− 0.4 V

−50

1.6

−5

-

−1.6

20

mA

μA

I_OL

LOW-level output

current

V_SCS= 0 V; V_O= 0.4 V

I_OL(off)

OFF-state output

leakage current

V_SCS= V_V1;V_O= 0 V to V_V1

+5

Reset output with clamping detection; pin RSTN

I_OH

HIGH-level output

current

VRSTN = 0.7 × V_V1(nom)

−1000

-

−50

μA

mA

V

I_OL

LOW-level output

current

V_RSTN= 0.9 V

1

5

V_OL

LOW-level output

voltage

V_V1= 1.5 V to 5.5 V;

pull-up resistor to V1 ≥ 4 kΩ

0

0.2 × V_V1

V_V1+ 0.3

+0.3 × V_V1

V_IH(th)

V_IL(th)

HIGH-level input

threshold voltage

0.7 × V_V1

−0.3

V

LOW-level input

threshold voltage

V

Enable output; pin EN

I_OHHIGH-level output

V_OH= V_V1− 0.4 V

V_OL= 0.4 V

−20

1.6

0

-

−1.6

20

mA

V

current

I_OL

LOW-level output

current

V_OL

LOW-level output

voltage

I_OL= 20 μA; V_V1= 1.2 V

0.4

Interrupt output; pin INTN

I_OLLOW-level output

current

CAN transmit data input; pin TXDC

V_OL= 0.4 V

1.6

-

15

mA

V_IH

HIGH-level input

voltage

0.7 × V_V1

−0.3

-

V_V1+ 0.3

V

V_IL

LOW-level input

voltage

+0.3 × V_V1

UJA1065_7

Product data sheet

Rev. 07 — 25 February 2010

51 of 76

UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

Table 26. Static characteristics …continued

T_vj= −40 °C to +150 °C, V_BAT42= 5.5 V to 52 V; V_BAT14= 5.5 V to 27 V; V_BAT42≥ V_BAT14− 1 V; unless otherwise specified. All

voltages are defined with respect to ground. Positive currents flow into the IC.^[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

R_TXDC(pu)

TXDC pull-up

resistor

V_TXDC= 0 V

5

12

25

kΩ

CAN receive data output; pin RXDC

I_OH

HIGH-level output

current

V_OH= V_V1− 0.4 V

−25

-

−1.6

mA

I_OL

LOW-level output

current

V_OL= 0.4 V

1.6

25

High-speed CAN-bus lines; pins CANH and CANL

V_o(dom)

CANH dominant

output voltage

Active mode; V_TXDC= 0 V;

_V2= 4.75 V to 5.25 V

2.85

0.5

3.6

1.4

-

4.25

2

V

CANL dominant

output voltage

Active mode; V_TXDC= 0 V;

V_V2= 4.75 V to 5.25 V

V_o(m)(dom)

matching of

dominant output

voltage

R_L= 60 Ω; V_o(m)(dom)

V_V2− V_CANH− V_CANL

=

−0.3

+0.3

V_o(dif)

differential bus

output voltage

Active mode; V_TXDC= 0 V;

V_V2= 4.75 V to 5.25 V;

R_L= 45 Ω to 65 Ω

1.5

-

3

V

Active mode, On-line mode or

On-line Listen mode;

−50

0

+50

mV

V_TXDC= V_V1;

V_V2= 4.75 V to 5.25 V;

no load

V_O(reces)

recessive output

voltage

Active mode, On-line mode or

On-line Listen mode;

2.25

2.5

2.75

V

V_TXDC= V_V1

;

V_V2= 4.75 V to 5.25 V;

R_L= 60 Ω

Off-line mode; R_L= 60 Ω

−0.1

0

+0.1

0.9

V

V_th(dif)

differential receiver

threshold voltage

Active mode, On-line mode or

On-line Listen mode;

V_CAN= −30 V to +30 V;

R_L= 60 Ω

0.5

0.7

Off-line mode;

0.45

0.7

1.15

V

V_CAN= −30 V to +30 V;

R_L= 60 Ω; measured from

recessive to dominant

V_th(GSD)(cm)

common-mode bus Active mode; GSTHC = 0;

voltage threshold _V2= 5 V; R_L= 60 Ω;

level for ground shift V_cm= 0.5 × (V_CANH+ V_CANL

0.95

0.3

1.75

1

2.45

1.5

V

)

detection

Active mode; GSTHC = 1;

V

V_V2= 5 V; R_L= 60 Ω;

V_cm= 0.5 × (V_CANH+ V_CANL

I_o(CANH)(dom)

CANH dominant

output current

Active mode; t < t_TXDC(dom)

V_CANH= 0 V; V_TXDC= 0 V;

V_V2= 5 V

;

−100

−75

−45

mA

UJA1065_7

Product data sheet

Rev. 07 — 25 February 2010

52 of 76

UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

Table 26. Static characteristics …continued

T_vj= −40 °C to +150 °C, V_BAT42= 5.5 V to 52 V; V_BAT14= 5.5 V to 27 V; V_BAT42≥ V_BAT14− 1 V; unless otherwise specified. All

voltages are defined with respect to ground. Positive currents flow into the IC.^[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

I_o(CANL)(dom)

CANL dominant

output current

Active mode; t < t_TXDC(dom)

;

45

75

100

mA

V_CANL= 5 V; V_TXDC= 0 V;

V_V2= 5 V

I_o(reces)

recessive output

current

all CAN modes; V2D = 1;

−5

-

+5

mA

V_TXDC= V_V1

;

V_CAN= −40 V to +40 V

Active mode, On-line mode or

On-line Listen mode;

−10

+10

μA

V2D = 0; V_TXDC= V_V1

;

V_CAN= −0.5 V to +5 V

R_i

input resistance

Active mode, On-line mode or

On-line Listen mode;

9

15

28

kΩ

V2D = 1; V_TXDC= V_V1

;

V_CAN= −40 V to +40 V

Off-line mode;

15

−2

19

-

22

0

40

+2

52

20

10

50

kΩ

%

V_CAN= −40 V to +40 V

R_i(m)

input resistance

matching

V_CANH= V_CANL

R_i(dif)

C_i(cm)

C_i(dif)

R_sc(bus)

differential input

resistance

30

-

kΩ

pF

Ω

[3]

common-mode input

capacitance

differential input

capacitance

-

detectable

Active mode; V_TXDC= 0 V

0

-

short-circuit

resistance between

bus lines and V_V2

,

V_BAT14, V_BAT42and

GND

CAN-bus common mode stabilization output; pin SPLIT

V_o

output voltage

Active mode, On-line mode or

On-line Listen mode;

CSC = V2D = 1;

0.3 × V_V20.5 × V_V20.7 × V_V2

V

⎪I_SPLIT⎪ = 500 μA

⎪I_L⎪

leakage current

Off-line mode OR CSC = 0;

−10

0

+10

μA

V_SPLIT= −40 V to +40 V

LIN transmit data input; pin TXDL

V_IL

LOW level input

voltage

−0.3

-

+0.3 × V_V1

V_V1+ 0.3

25

V

V_IH

HIGH-level input

voltage

0.7 × V_V1

-

V

R_TXDL(pu)

TXDL pull-up resistor V_TXDL= 0 V

5

12

kΩ

LIN receive data output; pin RXDL

I_OH

HIGH-level output

current

V_RXDL= V_V1− 0.4 V

−50

-

−1.6

mA

UJA1065_7

Product data sheet

Rev. 07 — 25 February 2010

53 of 76

UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

Table 26. Static characteristics …continued

T_vj= −40 °C to +150 °C, V_BAT42= 5.5 V to 52 V; V_BAT14= 5.5 V to 27 V; V_BAT42≥ V_BAT14− 1 V; unless otherwise specified. All

voltages are defined with respect to ground. Positive currents flow into the IC.^[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

I_OL

LOW-level output

current

V_RXDL= 0.4 V

1.6

-

20

mA

LIN-bus line; pin LIN

V_o(dom)LIN dominant output Active mode;

0

-

0.20 ×

V_BAT42

V

voltage

V_BAT42= 7 V to 18 V;

LDC = 0; t < t_{TXDL(dom)(dis)}

_TXDL= 0 V;

;

V

R_BAT42-LIN= 500 Ω

Active mode;

0.7

1.4

2.1

V_BAT42= 7.6 V to 18 V;

LDC = 1; t < t_{TXDL(dom)(dis)}

V_TXDL= 0 V; I_LIN= 40 mA

;

I_LIH

HIGH-level input

leakage current

V_LIN= V_BAT42; V_TXDL= V_V1

−10

0

-

+10

μA

V_BAT42= 8 V;

V_LIN= 8 V to 18 V;

V_TXDL= V_V1

I_LIL

LOW-level input

leakage current

V_BAT42= 12 V; V_LIN= 0 V;

V_TXDL= V_V1

−100

-

μA

I_o(sc)

short-circuit output

current

Active mode;

27

40

60

mA

V_LIN= V_BAT42= 12 V;

V_TXDL= 0 V; t < t_{TXDL(dom)(dis)}

LDC = 0

;

Active mode;

40

-

60

90

mA

V_LIN= V_BAT42= 18 V;

V_TXDL= 0 V; t < t_{TXDL(dom)(dis)}

LDC = 0

V_th(dom)

V_th(reces)

V_th(hyst)

V_th(cen)

receiver dominant

state

V_BAT42= 7 V to 27 V

-

0.4 ×

V_BAT42

V

receiver recessive

state

0.6 ×

V_BAT42

-

V

receiver threshold

voltage hysteresis

0.05 ×

V_BAT42

0.175 ×

V_BAT42

V

receiver threshold

voltage center

0.475 ×

V_BAT42

0.500 ×

V_BAT42

0.525 ×

V_BAT42

V

[3]

C_i

I_L

input capacitance

leakage current

-

10

pF

V_LIN= 0 V to 18 V

V_BAT42= 0 V

−5

0

+5

μA

V_GND= V_BAT42= 12 V

−10

+10

LIN-bus termination resistor connection; pin RTLIN

V_RTLIN

RTLIN output

voltage

Active mode; I_RTLIN= −10 μA;

V_BAT42= 7 V to 27 V

V_BAT42

1.0

−

V_BAT42

0.7

−

V_BAT42

0.2

−

V

Off-line mode;

V_BAT42

1.2

−

V_BAT42

1.0

−

-

I_RTLIN= −10 μA;

V_BAT42= 7 V to 27 V

UJA1065_7

Product data sheet

Rev. 07 — 25 February 2010

54 of 76

UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

Table 26. Static characteristics …continued

T_vj= −40 °C to +150 °C, V_BAT42= 5.5 V to 52 V; V_BAT14= 5.5 V to 27 V; V_BAT42≥ V_BAT14− 1 V; unless otherwise specified. All

voltages are defined with respect to ground. Positive currents flow into the IC.^[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

ΔV_RTLIN

RTLIN load

regulation

Active mode;

-

0.65

2

V

I_RTLIN= −10 μA to −10 mA;

V_BAT42= 7 V to 27 V

I_RTLIN(pu)

RTLIN pull-up

current

Active mode;

V_RTLIN= V_LIN= 0 V;

t > t_{LIN(dom)(det)}

−150

−10

−60

0

−35

+10

μA

Off-line mode;

V_RTLIN= V_LIN= 0 V;

t < t_{LIN(dom)(det)}

I_LL

LOW-level leakage

current

Off-line mode;

V_RTLIN= V_LIN= 0 V;

t > t_{LIN(dom)(det)}

TEST input; pin TEST

V_th(TEST)input threshold

for entering Software

development mode;

T_j= 25 °C

1

5

8

V

voltage

for entering Forced normal

mode; T_j= 25 °C

2

10

4

13.5

8

V

R_(pd)TEST

pull-down resistor

between pin TEST and GND

kΩ

Temperature detection

T_j(warn)high junction

160

175

190

°C

temperature warning

level

[1] All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at 125 °C ambient

temperature on wafer level (pretesting). Cased products are 100 % tested at 25 °C ambient temperature (final testing). Both pretesting

and final testing use correlated test conditions to cover the specified temperature and power supply voltage range.

[2]

V_V1(nom)is 3.3 V or 5 V, depending on the SBC version.

[3] Not tested in production.

[4] V2 internally supplies the SBC CAN transceiver. The supply current needed for the CAN transceiver reduces the pin V2 output

capability. The performance of the CAN transceiver can be impaired if V2 is also used to supply other circuitry while the CAN transceiver

is in use.

UJA1065_7

Product data sheet

Rev. 07 — 25 February 2010

55 of 76

UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

015aaa055

6

5

4

3

2

V

V1

(V)

type 5V0

I

=

V1

−100 μA

−50 mA

−120 mA

−250 mA

type 3V3

2

3

4

5

6

7

V

(V)

BAT14

a. T_j= 25 °C.

015aaa056

6

V

V1

(V)

type 5V0

5

4

3

2

I

=

V1

−100 μA

−50 mA

−120 mA

−250 mA

type 3V3

2

3

4

5

6

7

V

(V)

BAT14

b. T_j= 150 °C.

Fig 17. V1 output voltage (dropout) as a function of battery voltage

UJA1065_7

Product data sheet

Rev. 07 — 25 February 2010

56 of 76

UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

001aaf246

10

− I

T = +150 °C

j

I

BAT14

V1

(mA)

8

6

4

2

0

T = −40 °C

j

+25 °C

+150 °C

+25 °C

−40 °C

(1)

(2)

V

BAT14

= 8 V

5.5 V

0

−50

−100

−150

−200

−250

I

(mA)

V1

(1) Types 5V0 and 3V3.

(2) Type 5V0 only.

a. At T_j= −40 °C, +25 °C and +150 °C.

001aaf247

5

I

− I

V1

BAT14

(mA)

4

3

2

1

0

(1)

(2)

V

BAT14

= 9 V to 27 V

5.5 V

0

−50

−100

−150

−200

−250

I

(mA)

V1

(1) Types 5V0 and 3V3.

(2) Type 3V3 only.

b. At T_j= −40 °C to +150 °C.

Fig 18. V1 quiescent current as a function of output current

UJA1065_7

Product data sheet

Rev. 07 — 25 February 2010

57 of 76

UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

015aaa057

6

4

2

0

type 5V0

V

V1

(V)

type 3V3

0

−40

−80

−120

−160

I

(mA)

V1

V_BAT14= 9 V to 27 V.

T_j= 25 °C to 125 °C.

Fig 19. V1 output voltage as a function of output current

001aaf248

160

PSRR

(dB)

V

BAT14

= 14 V

14 V

120

80

40

0

T = 25 °C

j

150 °C

5.5 V

25 °C to 150 °C

(1)

5.5 V

150 °C

2

3

1

10

f (Hz)

I_V1= −120 mA.

(1) Type 5V0 only.

Fig 20. V1 power supply ripple rejection as a function of frequency

UJA1065_7

Product data sheet

Rev. 07 — 25 February 2010

58 of 76

UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

001aaf250

16

200

V

ΔV

V1

(mV)

BAT14

(V)

V

BAT14

12

100

ΔV

V1

8

0

4

−100

0

100

200

300

400

500

t (μs)

I_V1= −5 mA; C = 1 μF; ESR = 0.01 Ω; T_j= 25 °C.

a. Line transient response

001aaf251

−75

400

I

ΔV

V1

(mV)

V1

(mA)

−25

200

I

V1

ΔV

V1

25

75

0

−200

0

100

200

300

400

500

t (μs)

V_BAT14= 14 V; C = 1 μF; ESR = 0.01 Ω; T_j= 25 °C.

b. Load transient response

Fig 21. V1 transient response as a function of time

UJA1065_7

Product data sheet

Rev. 07 — 25 February 2010

59 of 76

UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

001aaf249

1

ESR

(Ω)

−1

−2

−3

10

stable operation area

unstable operation area

0

−40

−80

−120

I

V1

(mA)

Fig 22. V1 output stability related to ESR value of output capacitor

UJA1065_7

Product data sheet

Rev. 07 — 25 February 2010

60 of 76

UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

I

= 30 mA

load

BAT42

BAT14

V1

SBC

100 μF/

0.1 Ω

100

nF

47 μF/

0.1 Ω

V

BAT

R

load

100

nF

GND

001aaf572

a. Switch-on test circuit.

015aaa058

6

type 5V0

V

V1

(V)

4

2

0

V

= 8 V

BAT

type 3V3

V

= 5.5 V

BAT

V

BAT

= 12 V

0

0.4

0.8

1.2

1.6

2.0

t (ms)

b. Behavior at T_j= 25 °C.

015aaa059

6

type 5V0

V

V1

(V)

V

= 8 V

BAT

4

2

0

type 3V3

V

= 5.5 V

BAT

V

= 12 V

BAT

0

0.4

0.8

1.2

1.6

2.0

t (ms)

c. Behavior at T_j= 85 °C.

Fig 23. Switch-on behavior of V_V1

UJA1065_7

Product data sheet

Rev. 07 — 25 February 2010

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NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

10. Dynamic characteristics

Table 27. Dynamic characteristics

T_vj= −40 °C to +150 °C; V_BAT42= 5.5 V to 52 V; V_BAT14= 5.5 V to 27 V; V_BAT42≥ V_BAT14− 1 V; unless otherwise specified. All

voltages are defined with respect to ground. Positive currents flow into the IC.^[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Serial peripheral interface timing; pins SCS, SCK, SDI and SDO (see Figure 24)^[2]

T_cyc

t_lead

clock cycle time

enable lead time

960

240

-

ns

clock is LOW when SPI select

falls

t_lag

enable lag time

clock is LOW when SPI select

rises

240

-

ns

t_SCKH

t_SCKL

t_su

clock HIGH time

480

80

-

ns

clock LOW time

-

input data setup time

input data hold time

output data valid time

SPI select HIGH time

-

t_h

400

-

t_DOV

t_SSH

pin SDO; C_L= 10 pF

400

-

480

CAN transceiver timing; pins CANL, CANH, TXDC and RXDC

t_t(reces-dom)

t_t(dom-reces)

t_PHL

output transition time

recessive to dominant

10 % to 90 %; C = 100 pF;

R = 60 Ω; see Figure 25 and

Figure 26

-

100

120

-

ns

ms

μs

output transition time

dominant to recessive

90 % to 10 %; C = 100 pF;

R = 60 Ω; see Figure 25 and

Figure 26

-

propagation delay TXDC to 50 % V_TXDCto 50 % V_RXDC

RXDC (HIGH-to-LOW

transition)

;

70

1.5

3

220

C = 100 pF; R = 60 Ω; see

Figure 25 and Figure 26

t_PLH

propagation delay TXDC to 50 % V_TXDCto 50 % V_RXDC

RXDC (LOW-to-HIGH

transition)

;

220

C = 100 pF; R = 60 Ω; see

Figure 25 and Figure 26

t_TXDC(dom)

TXDC permanent dominant Active mode, On-line mode or

disable time

6

-

On-line Listen mode;

V_V2= 5 V; V_TXDC= 0 V

t_CANH(dom1)

t_CANL(dom1)

,

minimum dominant time first Off-line mode

pulse for wake-up on pins

CANH and CANL

-

t_CANH(reces)

t_CANL(reces)

,

minimum recessive time

pulse (after first dominant)

for wake-up on pins CANH

and CANL

Off-line mode

1

-

t_CANH(dom2)

t_CANL(dom2)

,

minimum dominant time

second pulse for wake-up on

pins CANH, CANL

Off-line mode

1

-

μs

t_timeout

time-out period between

wake-up message and

confirm message

On-line Listen mode

115

285

ms

UJA1065_7

Product data sheet

Rev. 07 — 25 February 2010

62 of 76

UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

Table 27. Dynamic characteristics …continued

T_vj= −40 °C to +150 °C; V_BAT42= 5.5 V to 52 V; V_BAT14= 5.5 V to 27 V; V_BAT42≥ V_BAT14− 1 V; unless otherwise specified. All

voltages are defined with respect to ground. Positive currents flow into the IC.^[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_off-line

maximum time before

entering Off-line mode

On-line or On-line Listen mode;

TXDC = V_V1; V2D = 1; COTC =

0; no bus activity

50

-

66

ms

On-line or On-line Listen mode;

TXDC = V_V1; V2D = 1; COTC =

1; no bus activity

200

400

-

265

530

ms

t_{off-line(ext)}

extended minimum time

before entering Off-line

mode

On-line or On-line Listen mode

after CAN wake-up event;

TXDC = V_V1; V2D = 1; no bus

activity

LIN transceiver; pins LIN, TXDL and RXDL^[3]

[4]

[5]

[4]

[5]

δ1

δ2

δ3

δ4

duty cycle 1

duty cycle 2

duty cycle 3

duty cycle 4

V_{th(reces)(max)}= 0.744 × V_BAT42

;

0.396

-

V_th(dom)(max)= 0.581 × V_BAT42

;

LSC = 0; t_bit= 50 μs;

V_BAT42= 7 V to 18 V

V

_{th(reces)(min)}= 0.422 × V_BAT42

;

-

0.581

V_th(dom)(min)= 0.284 × V_BAT42

;

LSC = 0; t_bit= 50 μs;

V_BAT42= 7.6 V to 18 V

V

_{th(reces)(max)}= 0.778 × V_BAT42

;

0.417

-

V_th(dom)(max)= 0.616 × V_BAT42

;

LSC = 1; t_bit= 96 μs;

V_BAT42= 7 V to 18 V

V

_{th(reces)(min)}= 0.389 × V_BAT42

;

-

0.590

V_th(dom)(min)= 0.251 × V_BAT42

LSC = 1; t_bit= 96 μs;

;

V_BAT42= 7.6 V to 18 V

t_p(rx)

propagation delay of

receiver

C_RXDL= 20 pF

-

6

μs

t_p(rx)(sym)

t_BUS(LIN)

symmetry of receiver

propagation delay

rising edge with respect to

falling edge; C_RXDL= 20 pF

−2

30

+2

150

minimum dominant time for Off-line mode

wake-up of the

LIN-transceiver

t_{LIN(dom)(det)}

continuously dominant

clamped LIN-bus detection

time

Active mode; LIN = 0 V

40

0.8

20

-

160

2.2

80

ms

t_{LIN(dom)(rec)}

continuously dominant

clamped LIN-bus recovery

time

Active mode

t_{TXDL(dom)(dis)}TXDL permanent dominant Active mode; TXDL = 0 V

disable time

Battery monitoring

t_BAT42(L)

BAT42 LOW time for setting

PWONS

5

-

20

μs

t_SENSE(L)

BAT42 LOW time for setting

BATFI

UJA1065_7

Product data sheet

Rev. 07 — 25 February 2010

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UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

Table 27. Dynamic characteristics …continued

T_vj= −40 °C to +150 °C; V_BAT42= 5.5 V to 52 V; V_BAT14= 5.5 V to 27 V; V_BAT42≥ V_BAT14− 1 V; unless otherwise specified. All

voltages are defined with respect to ground. Positive currents flow into the IC.^[1]

Symbol

Power supply V1; pin V1

t_V1(CLT)V1 clamped LOW time

during ramp-up of V1

Power supply V2; pin V2

t_V2(CLT)V2 clamped LOW time

during ramp-up of V2

Power supply V3; pin V3

Parameter

Conditions

Min

Typ

Max

Unit

Start-up mode; V1 active

229

-

283

ms

V2 active

28

-

36

ms

t_w(CS)

cyclic sense period

V3C[1:0] = 10; see Figure 14

V3C[1:0] = 11; see Figure 14

V3C[1:0] = 10; see Figure 14

V3C[1:0] = 11; see Figure 14

14

-

18

ms

μs

28

36

t_on(CS)

cyclic sense on-time

345

423

μs

Wake-up input; pin WAKE

t_WU(ipf)input port filter time

V_BAT42= 5 V to 27 V

V_BAT42= 27 V to 52 V

5

-

120

250

390

μs

30

310

t_su(CS)

cyclic sense sample setup

time

V3C[1:0] = 11 or 10;

see Figure 14

Watchdog

t_WD(ETP)

earliest watchdog trigger

point

programmed Nominal

Watchdog Period (NWP);

Normal mode

0.45 × NWP -

0.55 × NWP

1.1 × NWP

t_WD(LTP)

latest watchdog trigger point programmed nominal

watchdog period; Normal

0.9 × NWP

-

mode, Standby mode and

Sleep mode

t_WD(init)

watchdog initializing period watchdog time-out in Start-up

mode

229

1.3

-

283

1.7

ms

s

Fail-safe mode

t_ret

retention time

Fail-safe mode; wake-up

detected

1.5

Reset output; pin RSTN

t_RSTN(CHT)

clamped HIGH time,

pin RSTN

RSTN driven LOW internally

but RSTN pin remains HIGH

115

229

-

141

283

ms

t_RSTN(CLT)

clamped LOW time,

pin RSTN

RSTN driven HIGH internally

but RSTN pin remains LOW

t_RSTN(INT)

t_RSTNL

interrupt monitoring time

reset lengthening time

INTN = 0

229

0.9

-

283

1.1

ms

after internal or external reset

has been released; RLC = 0

after internal or external reset

has been released; RLC =1

18

-

22

ms

UJA1065_7

Product data sheet

Rev. 07 — 25 February 2010

64 of 76

UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

Table 27. Dynamic characteristics …continued

T_vj= −40 °C to +150 °C; V_BAT42= 5.5 V to 52 V; V_BAT14= 5.5 V to 27 V; V_BAT42≥ V_BAT14− 1 V; unless otherwise specified. All

voltages are defined with respect to ground. Positive currents flow into the IC.^[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Interrupt output; pin INTN

t_INTN

interrupt release

after SPI has read out the

Interrupt register

2

-

μs

Oscillator

f_osc

oscillator frequency

460.8

512

563.2

kHz

[1] All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at 125 °C ambient

temperature on wafer level (pretesting). Cased products are 100 % tested at 25 °C ambient temperature (final testing). Both pretesting

and final testing use correlated test conditions to cover the specified temperature and power supply voltage range.

[2] SPI timing is guaranteed for V_BAT42voltages down to 5 V. For V_BAT42voltages down to 4.5 V the guaranteed SPI timing values double,

so at these lower voltages a lower maximum SPI communication speed must be observed.

[3]

t_bit= selected bit time, depends on LSC bit; 50 μs or 96 μs (20 kbit/s or 10.4 kbit/s respectively); bus load conditions (R₁/R₂/C₁):

1 kΩ/1 kΩ/10 nF; 1 kΩ/2 kΩ/6.8 nF; 1 kΩ/open/1 nF; see Figure 27 and Figure 28.

t_{bus(rec)(min)}

[4] δ1, δ3 =

[5] δ2, δ4 =

-------------------------------

2 × t_bit

t_{bus(rec)(max)}

-------------------------------

2 × t_bit

SCS

t

SSH

T

cyc

lead

lag

t

SCKL

SCKH

SCK

SDI

t

su

t

h

MSB

LSB

X

t

DOV

floating

SDO

X

MSB

LSB

001aaa405

Fig 24. SPI timing

UJA1065_7

Product data sheet

Rev. 07 — 25 February 2010

65 of 76

UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

BAT42

RXDC

BAT14

CANH

10 pF

R

C

SBC

TXDC

CANL

GND

V2

C

b

001aac308

Fig 25. Timing test circuit for CAN transceiver

HIGH

LOW

TXDC

CANH

CANL

dominant

recessive

HIGH

V

o(dif)

RXDC

LOW

t

t(dom-reces)

t(reces-dom)

t

PLH

PHL

001aac309

Fig 26. Timing diagram CAN transceiver

UJA1065_7

Product data sheet

Rev. 07 — 25 February 2010

66 of 76

UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

BAT42

SBC

GND

RXDL

TXDL

RTLIN

R1

R2

C1

20 pF

LIN

001aad179

Fig 27. Timing test circuit for LIN transceiver

t

bit

t

bit

t

bit

V

TXDL

t

bus(rec)(min)

bus(dom)(max)

V

BAT42

V

th(reces)(max)

thresholds of

receiving node 1

th(dom)(max)

LIN BUS

signal

V

th(reces)(min)

thresholds of

receiving node 2

th(dom)(min)

t

bus(rec)(max)

bus(dom)(min)

V

RXDL1

receiving

node 1

t

p(rx)r

p(rx)f

RXDL2

receiving

node 2

t

p(rx)f

p(rx)r

001aaa346

Fig 28. Timing diagram LIN transceiver

11. Test information

11.1 Quality information

This product has been qualified in accordance with the Automotive Electronics Council

(AEC) standard Q100 - Stress test qualification for integrated circuits, and is suitable for

use in automotive applications.

UJA1065_7

Product data sheet

Rev. 07 — 25 February 2010

67 of 76

UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

12. Package outline

HTSSOP32: plastic thermal enhanced thin shrink small outline package; 32 leads;

body width 6.1 mm; lead pitch 0.65 mm; exposed die pad

SOT549-1

E

A

D

X

c

H

v

M

A

y

exposed die pad side

E

D

h

Z

32

17

A

(A )

3

2

E

A

h

A

1

pin 1 index

θ

L

p

L

detail X

1

16

w

M

b

e

p

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions).

A

(1)

(2)

UNIT

A

b

c

D

E

e

H

L

p

v

w

y

Z

θ

1

2

3

p

h

E

max.

8^o

0^o

0.15 0.95

0.05 0.85

0.30 0.20 11.1

0.19 0.09 10.9

5.1

4.9

6.2

6.0

3.6

3.4

8.3

7.9

0.75

0.50

0.78

0.48

mm

1.1

0.65

1

0.2

0.25

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

03-04-07

05-11-02

SOT549-1

MO-153

Fig 29. Package outline SOT549-1 (HTSSOP32)

UJA1065_7

Product data sheet

Rev. 07 — 25 February 2010

68 of 76

UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

13. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

13.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

13.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

13.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath specifications, including temperature and impurities

UJA1065_7

Product data sheet

Rev. 07 — 25 February 2010

69 of 76

UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

13.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to

higher minimum peak temperatures (see Figure 30) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 28 and 29

Table 28. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 29. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 30.

UJA1065_7

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Rev. 07 — 25 February 2010

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UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 30. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

UJA1065_7

Product data sheet

Rev. 07 — 25 February 2010

71 of 76

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NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

14. Revision history

Table 30. Revision history

Document ID

UJA1065_7

Release date

Data sheet status

Change notice

Supersedes

20100225

Product data sheet

-

UJA1065_6

Modifications:

• 3.0 V version (UJA1065TW/3V0) discontinued

• Section 6.2.5: text of third paragraph revised

• Table 11: text of bit 4, V1CMC, revised

• Section 11.1: text revised

• Section 2.1: text revised

UJA1065_6

UJA1065_5

UJA1065_4

UJA1065_3

UJA1065_2

UJA1065_1

20071122

20061116

20060818

20060221

20051216

20050810

Product data sheet

Preliminary data sheet

Objective data sheet

-

UJA1065_5

UJA1065_4

UJA1065_3

UJA1065_2

UJA1065_1

-

UJA1065_7

Product data sheet

Rev. 07 — 25 February 2010

72 of 76

UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

15. Legal information

15.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of an NXP Semiconductors product can reasonably be expected

15.2 Definitions

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on a weakness or default in the

customer application/use or the application/use of customer’s third party

customer(s) (hereinafter both referred to as “Application”). It is customer’s

sole responsibility to check whether the NXP Semiconductors product is

suitable and fit for the Application planned. Customer has to do all necessary

testing for the Application in order to avoid a default of the Application and the

product. NXP Semiconductors does not accept any liability in this respect.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

15.3 Disclaimers

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Non-automotive qualified products — Unless the data sheet of an NXP

Semiconductors product expressly states that the product is automotive

qualified, the product is not suitable for automotive use. It is neither qualified

nor tested in accordance with automotive testing or application requirements.

NXP Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

UJA1065_7

Product data sheet

Rev. 07 — 25 February 2010

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UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

UJA1065_7

Product data sheet

Rev. 07 — 25 February 2010

74 of 76

UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

17. Contents

1

General description. . . . . . . . . . . . . . . . . . . . . . 1

6.7.4

Bus, RXD and TXD failure detection . . . . . . . 22

TXDC dominant clamping . . . . . . . . . . . . . . . 22

RXDC recessive clamping . . . . . . . . . . . . . . . 22

GND shift detection . . . . . . . . . . . . . . . . . . . . 23

LIN transceiver. . . . . . . . . . . . . . . . . . . . . . . . 23

Mode control . . . . . . . . . . . . . . . . . . . . . . . . . 23

Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Off-line mode . . . . . . . . . . . . . . . . . . . . . . . . . 24

LIN wake-up. . . . . . . . . . . . . . . . . . . . . . . . . . 24

Termination control. . . . . . . . . . . . . . . . . . . . . 24

LIN slope control . . . . . . . . . . . . . . . . . . . . . . 25

LIN driver capability . . . . . . . . . . . . . . . . . . . . 25

Bus and TXDL failure detection . . . . . . . . . . . 25

TXDL dominant clamping. . . . . . . . . . . . . . . . 25

LIN dominant clamping . . . . . . . . . . . . . . . . . 25

LIN recessive clamping . . . . . . . . . . . . . . . . . 25

Inhibit and limp-home output . . . . . . . . . . . . . 25

Wake-up input . . . . . . . . . . . . . . . . . . . . . . . . 26

Interrupt output. . . . . . . . . . . . . . . . . . . . . . . . 27

Temperature protection . . . . . . . . . . . . . . . . . 27

SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . 28

SPI register mapping . . . . . . . . . . . . . . . . . . . 29

Register overview . . . . . . . . . . . . . . . . . . . . . 29

Mode register. . . . . . . . . . . . . . . . . . . . . . . . . 30

System Status register. . . . . . . . . . . . . . . . . . 32

System Diagnosis register . . . . . . . . . . . . . . . 34

Interrupt Enable register and Interrupt

6.7.4.1

6.7.4.2

6.7.4.3

6.8

2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

CAN transceiver . . . . . . . . . . . . . . . . . . . . . . . . 2

LIN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . 2

Power management . . . . . . . . . . . . . . . . . . . . . 3

Fail-safe features . . . . . . . . . . . . . . . . . . . . . . . 3

2.1

2.2

2.3

2.4

2.5

6.8.1

6.8.1.1

6.8.1.2

6.8.2

6.8.3

6.8.4

6.8.5

6.8.6

6.8.6.1

6.8.6.2

6.8.6.3

6.9

6.10

6.11

6.12

6.13

6.13.1

6.13.2

6.13.3

6.13.4

6.13.5

6.13.6

3

4

Ordering information. . . . . . . . . . . . . . . . . . . . . 4

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

6

6.1

6.2

Functional description . . . . . . . . . . . . . . . . . . . 7

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Fail-safe system controller . . . . . . . . . . . . . . . . 7

Start-up mode. . . . . . . . . . . . . . . . . . . . . . . . . . 9

Restart mode . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Fail-safe mode . . . . . . . . . . . . . . . . . . . . . . . . . 9

Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . 10

Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Flash mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 12

On-chip oscillator . . . . . . . . . . . . . . . . . . . . . . 12

Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Watchdog start-up behavior . . . . . . . . . . . . . . 13

Watchdog window behavior . . . . . . . . . . . . . . 13

Watchdog time-out behavior. . . . . . . . . . . . . . 14

Watchdog OFF behavior. . . . . . . . . . . . . . . . . 14

System reset. . . . . . . . . . . . . . . . . . . . . . . . . . 15

RSTN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

EN output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Power supplies . . . . . . . . . . . . . . . . . . . . . . . . 17

BAT14, BAT42 and SYSINH. . . . . . . . . . . . . . 17

SYSINH output . . . . . . . . . . . . . . . . . . . . . . . . 17

SENSE input. . . . . . . . . . . . . . . . . . . . . . . . . . 17

Voltage regulators V1 and V2. . . . . . . . . . . . . 17

Voltage regulator V1 . . . . . . . . . . . . . . . . . . . . 17

Voltage regulator V2 . . . . . . . . . . . . . . . . . . . . 18

Switched battery output V3. . . . . . . . . . . . . . . 18

CAN transceiver . . . . . . . . . . . . . . . . . . . . . . . 19

Mode control. . . . . . . . . . . . . . . . . . . . . . . . . . 19

Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . 20

On-line mode . . . . . . . . . . . . . . . . . . . . . . . . . 21

On-line Listen mode . . . . . . . . . . . . . . . . . . . . 21

Off-line mode . . . . . . . . . . . . . . . . . . . . . . . . . 21

CAN wake-up . . . . . . . . . . . . . . . . . . . . . . . . . 21

Termination control . . . . . . . . . . . . . . . . . . . . . 22

6.2.1

6.2.2

6.2.3

6.2.4

6.2.5

6.2.6

6.2.7

6.3

6.4

6.4.1

6.4.2

6.4.3

6.4.4

6.5

6.5.1

6.5.2

6.6

6.6.1

6.6.1.1

6.6.2

6.6.3

6.6.3.1

6.6.3.2

6.6.4

6.7

6.7.1

6.7.1.1

6.7.1.2

6.7.1.3

6.7.1.4

6.7.2

6.7.3

Enable Feedback register . . . . . . . . . . . . . . . 35

Interrupt register. . . . . . . . . . . . . . . . . . . . . . . 36

System Configuration register and System

Configuration Feedback register . . . . . . . . . . 38

Physical Layer Control register and Physical

6.13.7

6.13.8

6.13.9

Layer Control Feedback register . . . . . . . . . . 39

6.13.10 Special Mode register and Special Mode

Feedback register . . . . . . . . . . . . . . . . . . . . . 40

6.13.11 General Purpose registers and General

Purpose Feedback registers . . . . . . . . . . . . . 41

6.13.12 Register configurations at reset . . . . . . . . . . . 41

6.14

6.14.1

6.14.2

Test modes. . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Software development mode . . . . . . . . . . . . . 44

Forced normal mode . . . . . . . . . . . . . . . . . . . 45

7

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 46

Thermal characteristics . . . . . . . . . . . . . . . . . 47

Static characteristics . . . . . . . . . . . . . . . . . . . 47

Dynamic characteristics. . . . . . . . . . . . . . . . . 62

Test information . . . . . . . . . . . . . . . . . . . . . . . 67

Quality information. . . . . . . . . . . . . . . . . . . . . 67

8

9

10

11

11.1

continued >>

UJA1065_7

Product data sheet

Rev. 07 — 25 February 2010

75 of 76

UJA1065

NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip

12

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 68

13

Soldering of SMD packages . . . . . . . . . . . . . . 69

Introduction to soldering . . . . . . . . . . . . . . . . . 69

Wave and reflow soldering . . . . . . . . . . . . . . . 69

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 69

Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 70

13.1

13.2

13.3

13.4

14

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 72

15

Legal information. . . . . . . . . . . . . . . . . . . . . . . 73

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 73

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 74

15.1

15.2

15.3

15.4

16

17

Contact information. . . . . . . . . . . . . . . . . . . . . 74

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 25 February 2010

Document identifier: UJA1065_7


型号：	UJA1065TW/3V3,512
厂家：	NXP
描述：	UJA1065 - High-speed CAN/LIN fail-safe system basis chip TSSOP 32-Pin 以太网：16GBASE-T 电信光电二极管电信集成电路
文件：	总76页 (文件大小：459K)
中文：	中文翻译
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