UJA1078TW/5V0,512_技术文档

UJA1078

High-speed CAN/dual LIN core system basis chip

Rev. 02 — 27 May 2010

Product data sheet

1. General description

The UJA1078 core System Basis Chip (SBC) replaces the basic discrete components

commonly found in Electronic Control Units (ECU) with a high-speed Controller Area

Network (CAN) and two Local Interconnect Network (LIN) interfaces.

The UJA1078 supports the networking applications used to control power and sensor

peripherals by using a high-speed CAN as the main network interface and the LIN

interfaces as local sub-busses.

The core SBC contains the following integrated devices:

• High-speed CAN transceiver, inter-operable and downward compatible with CAN

transceiver TJA1042, and compatible with the ISO 11898-2 and ISO 11898-5

standards

• LIN transceivers compliant with LIN 2.1, LIN 2.0 and SAE J2602, and compatible with

LIN 1.3

• Advanced independent watchdog (UJA1078/xx/WD versions)

• 250 mA voltage regulator for supplying a microcontroller; extendable with external

PNP transistor for increased current capability and dissipation distribution

• Separate voltage regulator for supplying the on-board CAN transceiver

• Serial Peripheral Interface (SPI) (full duplex)

• 2 local wake-up input ports

• Limp home output port

In addition to the advantages gained from integrating these common ECU functions in a

single package, the core SBC offers an intelligent combination of system-specific

functions such as:

• Advanced low-power concept

• Safe and controlled system start-up behavior

• Detailed status reporting on system and sub-system levels

The UJA1078 is designed to be used in combination with a microcontroller that

incorporates a CAN controller. The SBC ensures that the microcontroller always starts up

in a controlled manner.

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

2. Features and benefits

2.1 General

Contains a full set of CAN and LIN ECU functions:

CAN transceiver and two LIN transceivers

Scalable 3.3 V or 5 V voltage regulator delivering up to 250 mA for a

microcontroller and peripheral circuitry; an external PNP transistor can be

connected for better heat distribution over the PCB

Separate voltage regulator for the CAN transceiver (5 V)

Watchdog with Window and Timeout modes and on-chip oscillator

Serial Peripheral Interface (SPI) for communicating with the microcontroller

ECU power management system

Designed for automotive applications:

Excellent ElectroMagnetic Compatibility (EMC) performance

±8 kV ElectroStatic Discharge (ESD) protection Human Body Model (HBM) on the

CAN/LIN bus pins and the WAKE pins

±6 kV ElectroStatic Discharge (ESD) protection IEC 61000-4-2 on the CAN/LIN bus

pins and the WAKE pins

±58 V short-circuit proof CAN/LIN bus pins

Battery and CAN/LIN bus pins are protected against transients in accordance with

ISO 7637-3

Supports remote flash programming via the CAN bus

Small 6.1 mm × 11 mm HTSSOP32 package with low thermal resistance

Pb-free; RoHS and dark green compliant

2.2 CAN transceiver

ISO 11898-2 and ISO 11898-5 compliant high-speed CAN transceiver

Dedicated low dropout voltage regulator for the CAN bus:

Independent of the microcontroller supply

Significantly improves EMC performance

Bus connections are truly floating when power is off

SPLIT output pin for stabilizing the recessive bus level

2.3 LIN transceivers

2 × LIN 2.1 compliant LIN transceivers

Compliant with SAE J2602

Downward compatible with LIN 2.0 and LIN 1.3

Low slope mode for optimized EMC performance

Integrated LIN termination diode at pin DLIN

2.4 Power management

Wake-up via CAN, LIN or local WAKE pins with wake-up source detection

2 WAKE pins:

WAKE1 and WAKE2 inputs can be switched off to reduce current flow

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

2 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

Output signal (WBIAS) to bias the WAKE pins, selectable sampling time of 16 ms

or 64 ms

Standby mode with very low standby current and full wake-up capability; V1 active to

maintain supply to the microcontroller

Sleep mode with very low sleep current and full wake-up capability

2.5 Control and Diagnostic features

Safe and predictable behavior under all conditions

Programmable watchdog with independent clock source:

Window, Timeout (with optional cyclic wake-up) and Off modes supported (with

automatic re-enable in the event of an interrupt)

16-bit Serial Peripheral Interface (SPI) for configuration, control and diagnosis

Global enable output for controlling safety-critical hardware

Limp home output (LIMP) for activating application-specific ‘limp home’ hardware in

the event of a serious system malfunction

Overtemperature shutdown

Interrupt output pin; interrupts can be individually configured to signal V1/V2

undervoltage, CAN/LIN/local wake-up and cyclic and power-on interrupt events

Bidirectional reset pin with variable power-on reset length to support a variety of

microcontrollers

Software-initiated system reset

2.6 Voltage regulators

Main voltage regulator V1:

Scalable voltage regulator for the microcontroller, its peripherals and additional

external transceivers

±2 % accuracy for LIN master application

±3 % accuracy for LIN slave application

3.3 V and 5 V versions available

Delivers up to 250 mA and can be combined with an external PNP transistor for

better heat distribution over the PCB

Selectable current threshold at which the external PNP transistor starts to deliver

current

Undervoltage warning at 90 % of nominal output voltage and undervoltage reset at

90 % or 70 % of nominal output voltage

Can operate at V_BATvoltages down to 4.5 V (e.g. during cranking), in accordance

with ISO 7637 pulse 4/4b and ISO16750-2

Stable output under all conditions

Voltage regulator V2 for CAN transceiver:

Dedicated voltage regulator for on-chip high-speed CAN transceiver

Undervoltage warning at 90 % of nominal output voltage

Can be switched off; CAN transceiver can be supplied by V1 or by an external

voltage regulator

Can operate at V_BATvoltages down to 5.5 V (e.g. during cranking) in accordance

with ISO 7637, pulse 4

Stable output under all conditions

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

3 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

3. Ordering information

Table 1.

Ordering information

Type number^[1]

Package

Name

Description

Version

UJA1078TW/5V0/WD

UJA1078TW/3V3/WD

UJA1078TW/5V0

HTSSOP32

plastic thermal enhanced thin shrink small outline package;

32 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die

pad

SOT549-1

UJA1078TW/3V3

[1] UJA1078TW/5V0xx versions contain a 5 V regulator (V1); UJA1078TW/3V3xx versions contain a 3.3 V regulator (V1); WD versions

contain a watchdog.

4. Block diagram

UJA1078

V1

V2

BAT

V2

GND

V1

V2

UV

VEXCTRL

VEXCC

EXT. PNP

CTRL

SCK

SDI

WBIAS

SDO

SCSN

WAKE1

WAKE2

WDOFF

EN

SYSTEM

CONTROLLER

INTN

RSTN

WAKE

OSC

TEMP

BAT

LIMP

DLIN

LIN1

TXDL1

RXDL1

LIN1

LIN2

V2

HS-CAN

CANH

CANL

TXDC

RXDC

SPLIT

LIN2

TXDL2

RXDL2

BAT

015aaa072

Fig 1. Block diagram

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

4 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

5. Pinning information

5.1 Pinning

1

2

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

TXDL2

RXDL2

TXDL1

V1

BAT

VEXCTRL

TEST2

VEXCC

WBIAS

LIN2

3

4

5

RXDL1

RSTN

INTN

6

7

DLIN

8

EN

LIN1

UJA1078

9

SDI

SPLIT

GND

10

11

12

13

14

15

16

SDO

SCK

CANL

CANH

V2

SCSN

TXDC

RXDC

TEST1

WDOFF

WAKE2

WAKE1

LIMP

015aaa046

Fig 2. Pin configuration

5.2 Pin description

Table 2.

Symbol

TXDL2

RXDL2

TXDL1

V1

Pin description

1

Description

LIN2 transmit data input

LIN2 receive data output

LIN1 transmit data input

2

3

4

voltage regulator output for the microcontroller (5 V or 3.3 V depending on

SBC version)

RXDL1

RSTN

INTN

EN

5

LIN1 receive data output

reset input/output to and from the microcontroller

interrupt output to the microcontroller

enable output

6

7

8

SDI

9

SPI data input

SDO

10

11

12

13

14

15

16

17

SPI data output

SCK

SPI clock input

SCSN

TXDC

RXDC

TEST1

WDOFF

LIMP

SPI chip select input

CAN transmit data input

CAN receive data output

test pin; pin should be connected to ground

WDOFF pin for deactivating the watchdog

limp home output

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

5 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

Table 2.

Pin description …continued

Symbol

WAKE1

WAKE2

V2

18

19

20

21

22

23

24

25

26

27

28

29

Description

local wake-up input 1

local wake-up input 2

5 V voltage regulator output for CAN

CANH bus line

CANH

CANL

GND

CANL bus line

ground

SPLIT

LIN1

CAN bus common mode stabilization output

LIN1 bus line

DLIN

LIN termination resistor connection

LIN2 bus line

LIN2

WBIAS

VEXCC

control pin for external wake biasing transistor

current measurement for external PNP transistor; this pin is connected to

the collector of the external PNP transistor

TEST2

30

31

test pin; pin should be connected to ground

VEXCTRL

control pin of the external PNP transistor; this pin is connected to the base

of the external PNP transistor

BAT

32

battery supply for the SBC

The exposed die pad at the bottom of the package allows for better heat dissipation from

the SBC via the printed circuit board. The exposed die pad is not connected to any active

part of the IC and can be left floating, or can be connected to GND.

6. Functional description

The UJA1078 combines the functionality of a high-speed CAN transceiver, two LIN

transceivers, two voltage regulators and a watchdog (UJA1078/xx/WD versions) in a

single, dedicated chip. It handles the power-up and power-down functionality of the ECU

and ensures advanced system reliability. The SBC offers wake-up by bus activity, by

cyclic wake-up and by the activation of external switches. Additionally, it provides a

periodic control signal for pulsed testing of wake-up switches, allowing low-current

operation even when the wake-up switches are closed in Standby mode.

All transceivers are optimized to be highly flexible with regard to bus topologies. In

particular, the high-speed CAN transceiver is optimized to reduce ringing (bus reflections).

V1, the main voltage regulator, is designed to power the ECU's microcontroller, its

peripherals and additional external transceivers. An external PNP transistor can be added

to improve heat distribution. V2 supplies the integrated high-speed CAN transceiver. The

watchdog is clocked directly by the on-chip oscillator and can be operated in Window,

Timeout and Off modes.

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

6 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

6.1 System Controller

6.1.1 Introduction

The system controller manages register configuration and controls the internal functions

of the SBC. Detailed device status information is collected and presented to the

microcontroller. The system controller also provides the reset and interrupt signals.

The system controller is a state machine. The SBC operating modes, and how transitions

between modes are triggered, are illustrated in Figure 3. These modes are discussed in

more detail in the following sections.

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

7 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

from Standby or Normal

chip temperature above

OTP activatrion threshold T

th(act)otp

Overtemp

V

BAT

below

V1: OFF

V2: OFF

power-off threshold V

th(det)poff

(from all modes)

limp home = LOW (active)

CAN/LIN: Off and

high resistance

watchdog: OFF

Off

chip temperature below

OTP release threshold T

V1: OFF

V2: OFF

th(rel)otp

CAN/LIN: Off and

high resistance

watchdog: OFF

INTN: HIGH

V

below

BAT

power-on threshold V

th(det)pon

V

BAT

above

power-on threshold V

th(det)pon

watchdog

trigger

watchdog overflow or

V1 undervoltage

Standby

V1: ON

V2: OFF

CAN/LIN: Lowpower/Off

watchdog: Timeout/Off

MC = 00

MC = 01 and

INTN = HIGH and

one wake-up enabled and

no wake-up pending

reset event or

MC = 00

MC = 10 or MC = 11

wake-up event if enabled

Sleep

Normal

V1: OFF

V2: OFF

CAN/LIN: Lowpower/Off

watchdog: OFF

RSTN: LOW

V1: ON

V2: ON/OFF

CAN/LIN: Active/Lowpower

watchdog: Window/

Timeout/Off

successful

watchdog

trigger

MC = 01 and

INTN = HIGH and

one wake-up enabled and

no wake-up pending

MC = 01

MC = 1x

015aaa073

Fig 3. UJA1078 system controller

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

8 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

6.1.2 Off mode

The SBC switches to Off mode from all other modes if the battery supply drops below the

power-off detection threshold (V_th(det)poff). In Off mode, the voltage regulators are disabled

and the bus systems are in a high-resistive state. The CAN bus pins are floating in this

mode.

As soon as the battery supply rises above the power-on detection threshold (V_th(det)on),

the SBC goes to Standby mode, and a system reset is executed (reset pulse width of

t_w(rst), long or short; see Section 6.5.1 and Table 11).

6.1.3 Standby mode

The SBC will enter Standby mode:

• From Off mode if V_BATrises above the power-on detection threshold (V_th(det)on

)

• From Sleep mode on the occurrence of a CAN, LIN or local wake-up event

• From Overtemp mode if the chip temperature drops below the overtemperature

protection release threshold, T_th(rel)otp

• From Normal mode if bit MC is set to 00 or a system reset is performed (see

Section 6.5)

In Standby mode, V1 is switched on. The CAN and LIN transceivers will either be in a

low-power state (Lowpower mode; STBCC/STBCL1/STBCL2 = 1; see Table 6) with bus

wake-up detection enabled or completely switched off (Off mode; STBCx = 0) - see

Section 6.7.1 and Section 6.8.1. The watchdog can be running in Timeout mode or Off

mode, depending on the state of the WDOFF pin and the setting of the watchdog mode

control bit (WMC) in the WD_and_Status register (Table 4).

The SBC will exit Standby mode if:

• Normal mode is selected by setting bits MC to 10 (V2 disabled) or 11 (V2 enabled)

• Sleep mode is selected by setting bits MC to 01

• The chip temperature rises above the OTP activation threshold, T_th(act)otp, causing the

SBC to enter Overtemp mode

6.1.4 Normal mode

Normal mode is selected from Standby mode by setting bits MC in the Mode_Control

register (Table 5) to 10 (V2 disabled) or 11 (V2 enabled).

In Normal mode, the CAN physical layer will be enabled (Active mode; STBCC = 0; see

Table 6) or in a low-power state (Lowpower mode; STBCC = 1) with bus wake-up

detection active.

In Normal mode, the LIN physical layers (LIN1 and LIN2) will be enabled (Active mode;

STBCL1/STBCL2 = 0; see Table 6) or in a low-power state (Lowpower mode;

STBCL1/STBCL2 = 1) with bus wake-up detection active.

The SBC will exit Normal mode if:

• Standby mode is selected by setting bits MC to 00

• Sleep mode is selected by setting bits MC to 01

• A system reset is generated (see Section 6.1.3; the SBC will enter Standby mode)

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

9 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

• The chip temperature rises above the OTP activation threshold, T_th(act)otp, causing the

SBC to switch to Overtemp mode

6.1.5 Sleep mode

Sleep mode is selected from Standby mode or Normal mode by setting bits MC in the

Mode_Control register (Table 5) to 01. The SBC will enter Sleep mode providing there are

no pending interrupts (INTN = HIGH) or wake-up events and at least one wake-up source

is enabled (CAN, LIN or WAKE). Any attempt to enter Sleep mode while one of these

conditions has not been satisfied will result in a short reset (3.6 ms minimum pulse width;

see Section 6.5.1 and Table 11).

In Sleep mode, V1 and V2 are off and the bus transceivers will be switched off (Off mode;

STBCx = 0; see Table 6) or in a low-power state (Lowpower mode; STBCx = 1) with bus

wake-up detection active - see Section 6.7.1 and Section 6.8.1). The watchdog is off and

the reset pin is LOW.

A CAN, LIN or local wake-up event will cause the SBC to switch from Sleep mode to

Standby mode, generating a (short or long; see Section 6.5.1) system reset. The value of

the mode control bits (MC) will be changed to 00 and V1 will be enabled.

6.1.6 Overtemp mode

The SBC will enter Overtemp mode from Normal mode or Standby mode when the chip

temperature exceeds the overtemperature protection activation threshold, T_th(act)otp

,

In Overtemp mode, the voltage regulators are switched off and the bus systems are in a

high-resistive state. When the SBC enters Overtemp mode, the RSTN pin is driven LOW

and the limp home control bit, LHC, is set so that the LIMP pin is driven LOW.

The chip temperature must drop a hysteresis level below the overtemperature shutdown

threshold before the SBC can exit Overtemp mode. After leaving Overtemp mode the

SBC enters Standby mode and a system reset is generated (reset pulse width of t_w(rst)

,

long or short; see Section 6.5.1 and Table 11).

6.2 SPI

6.2.1 Introduction

The Serial Peripheral Interface (SPI) provides the communication link with the

microcontroller, supporting multi-slave operations. The SPI is configured for full duplex

data transfer, so status information is returned when new control data is shifted in. The

interface also offers a read-only access option, allowing registers to be read back by the

application without changing the register content.

The SPI uses four interface signals for synchronization and data transfer:

• SCSN: SPI chip select; active LOW

• SCK: SPI clock; default level is LOW due to low-power concept

• SDI: SPI data input

• SDO: SPI data output; floating when pin SCSN is HIGH

Bit sampling is performed on the falling clock edge and data is shifted on the rising clock

edge (see Figure 4).

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

10 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

SCS

SCK

01

sampled

MSB

02

03

04

15

16

SDI

X

14

13

12

01

LSB

X

MSB

SDO

X

floating

mce634

Fig 4. SPI timing protocol

6.2.2 Register map

The first three bits (A2, A1 and A0) of the message header define the register address.

The fourth bit (RO) defines the selected register as read/write or read only.

Table 3.

Register map

Address bits 15, 14 and 13

Write access bit 12 = 0

Read/Write access bits 11... 0

WD_and_Status register

Mode_Control register

Int_Control register

000

001

010

011

0 = read/write, 1 = read only

Int_Status register

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

11 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

6.2.3 WD_and_Status register

Table 4.

WD_and_Status register

Symbol Access Power-on Description

Bit

default

15:13 A2, A1, A0

R

000

register address

access status

12

RO

R/W

0

0: register set to read/write

1: register set to read only

watchdog mode control

11

WMC

R/W

0

0: Normal mode: watchdog in Window mode; Standby mode: watchdog in

Timeout mode

1: Normal mode: watchdog in Timeout mode; Standby mode: watchdog in

Off mode

10:8 NWP^[1]

100

nominal watchdog period

000: 8 ms

001: 16 ms

010: 32 ms

011: 64 ms

100: 128 ms

101: 256 ms

110: 1024 ms

111: 4096 ms

7

6

WOS/SWR R/W

-

watchdog off status/software reset

0: WDOFF pin LOW; watchdog mode determined by bit WMC

1: watchdog disabled due to HIGH level on pin WDOFF; results in software

reset

V1S

V2S

R

V1 status

0: V1 output voltage above 90 % undervoltage recovery threshold

(V_uvr; see Table 10)

1: V1 output voltage below 90 % undervoltage detection threshold

(V_uvd; see Table 10)

5

-

V2 status

0: V2 output voltage above undervoltage release threshold

(V_uvr; see Table 10 )

1: V2 output voltage below undervoltage detection threshold

(V_uvd; see Table 10)

4

WLS1

R

-

wake-up 1 status

0: WAKE1 input voltage below switching threshold (V_th(sw)

)

1: WAKE1 input voltage above switching threshold (V_th(sw)

)

3

WLS2

-

wake-up 2 status

0: WAKE2 input voltage below switching threshold (V_th(sw)

)

1: WAKE2 input voltage above switching threshold (V_th(sw)

2:0

reserved

000

[1] Bit NWP is set to it’s default value (100) after a reset.

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

12 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

6.2.4 Mode_Control register

Table 5.

Bit

Mode_Control register

Symbol

Access Power-on Description

default

15:13 A2, A1, A0 R

001

0

register address

access status

12

RO

R/W

0: register set to read/write

1: register set to read only

mode control

11:10 MC

R/W

00

00: Standby mode

01: Sleep mode

10: Normal mode; V2 off

11: Normal mode; V2 on

9

8

7

6

5

4

LHWC^[1]

R/W

1

0

limp home warning control

0: no limp home warning

1: limp home warning is set; next reset will activate LIMP output

limp home control

LHC^[2]

ENC

LSC

0: LIMP pin set floating

1: LIMP pin driven LOW

enable control

0: EN pin driven LOW

1: EN pin driven HIGH in Normal mode

LIN slope control

0: normal slope, 20 kbit/s

1: low slope, 10.4 kbit/s

WBC

PDC

wake bias control

0: WBIAS floating if WSEn = 0; 16 ms sampling if WSEn = 1

1: WBIAS on if WSEn = 0; 64 ms sampling if WSEn = 1

power distribution control

0: V1 threshold current for activating the external PNP transistor; load current

rising; I_th(act)PNP= 85 mA; V1 threshold current for deactivating the external

PNP transistor; load current falling; I_th(deact)PNP= 50 mA; see Figure 7

1: V1 threshold current for activating the external PNP transistor; load current

rising; I_th(act)PNP= 50 mA; V1 threshold current for deactivating the external

PNP transistor; load current falling; I_th(deact)PNP= 15 mA; see Figure 7

3:0

reserved

R

0000

[1] Bit LHWC is set to 1 after a reset.

[2] Bit LHC is set to 1 after a reset, if LHWC was set to 1 prior to the reset.

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

13 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

6.2.5 Int_Control register

Table 6.

Bit

Int_Control register

Symbol

Access Power-on Description

default

15:13 A2, A1, A0 R

010

0

register address

access status

12

11

10

9

RO

R/W

0: register set to read/write

1: register set to read only

V1UIE

V2UIE

STBCL1

0

V1 undervoltage interrupt enable

0: V1 undervoltage warning interrupts cannot be requested

1: V1 undervoltage warning interrupts can be requested

V2 undervoltage interrupt enable

0: V2 undervoltage warning interrupts cannot be requested

1: V2 undervoltage warning interrupts can be requested

LIN1 standby control

0: When the SBC is in Normal mode (MC = 1x):

LIN1 is in Active mode. The wake-up flag (visible on RXDL1) is cleared

regardless of the value of V_BAT

.

When the SBC is in Standby/Sleep mode (MC = 0x):

LIN1 is in Off mode. Bus wake-up detection is disabled. LIN1 wake-up

interrupts cannot be requested.

1: LIN1 is in Lowpower mode with bus wake-up detection enabled,

regardless of the SBC mode (MC = xx). LIN1 wake-up interrupts can be

requested.

8

STBCL2

R/W

0

LIN2 standby control

0: When the SBC is in Normal mode (MC = 1x):

LIN2 is in Active mode. The wake-up flag (visible on RXDL2) is cleared

regardless of the value of V_BAT

.

When the SBC is in Standby/Sleep mode (MC = 0x):

LIN2 is in Off mode. Bus wake-up detection is disabled. LIN2 wake-up

interrupts cannot be requested.

1: LIN2 is in Lowpower mode with bus wake-up detection enabled,

regardless of the SBC mode (MC = xx). LIN2 wake-up interrupts can be

requested.

7:6

5:4

WIC1

WIC2

R/W

00

wake-up interrupt 1 control

00: wake-up interrupt 1 disabled

01: wake-up interrupt 1 on rising edge

10: wake-up interrupt 1 on falling edge

11: wake-up interrupt 1 on both edges

wake-up interrupt 2 control

00: wake-up interrupt 2 disabled

01: wake-up interrupt 2 on rising edge

10: wake-up interrupt 2 on falling edge

11: wake-up interrupt 2 on both edges

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

14 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

Table 6.

Bit

Int_Control register

Symbol

Access Power-on Description

default

3

STBCC

R/W

0

CAN standby control

0: When the SBC is in Normal mode (MC = 1x):

CAN is in Active mode. The wake-up flag (visible on RXDC) is cleared

regardless of V2 output voltage.

When the SBC is in Standby/Sleep mode (MC = 0x):

CAN is in Off mode. Bus wake-up detection is disabled. CAN wake-up

interrupts cannot be requested.

1: CAN is in Lowpower mode with bus wake-up detection enabled,

regardless of the SBC mode (MC = xx). CAN wake-up interrupts can be

requested.

2

RTHC

R/W

0

reset threshold control

0: The reset threshold is set to the 90 % V1 undervoltage detection voltage

(V_uvd; see Table 10)

1: The reset threshold is set to the 70 % V1 undervoltage detection voltage

(V_uvd; see Table 10)

1

0

WSE1

WSE2

R/W

0

WAKE1 sample enable

0: sampling continuously

1: sampling of WAKE1 is synchronized with WBIAS (sample rate controlled

by WBC)

WAKE2 sample enable

0: sampling continuously

1: sampling of WAKE1 is synchronized with WBIAS (sample rate controlled

by WBC)

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

15 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

6.2.6 Int_Status register

Table 7.

Bit

Int_Status register^[1]

Symbol

Access Power-on Description

default

15:13 A2, A1, A0 R

011

0

register address

access status

12

11

10

9

RO

R/W

R

0: register set to read/write

1: register set to read only

V1UI

V2UI

LWI1

LWI2

CI

0

V1 undervoltage interrupts

0: no V1 undervoltage warning interrupt pending

1: V1 undervoltage warning interrupt pending

V2 undervoltage interrupts

0

0: no V2 undervoltage warning interrupt pending

1: V2 undervoltage warning interrupt pending

LIN wake-up interrupt 1

0

0: no LIN1 wake-up interrupt pending

1: LIN1 wake-up interrupt pending

LIN wake-up interrupt 2

8

0

0: no LIN2 wake-up interrupt pending

1: LIN2 wake-up interrupt pending

cyclic interrupt

7

0

0: no cyclic interrupt pending

1: cyclic interrupt pending

6

WI1

0

wake-up interrupt 1

0: no wake-up interrupt 1 pending

1: wake-up interrupt 1 pending

power-on status interrupt

5

POSI

WI2

1

0: no power-on interrupt pending

1: power-on interrupt pending

wake-up interrupt 2

4

0

0: no wake-up interrupt 2 pending

1: wake-up interrupt 2 pending

CAN wake-up interrupt

3

CWI

0

0: no CAN wake-up interrupt pending

1: CAN wake-up interrupt pending

2:0

reserved

000

[1] An interrupt can be cleared by writing 1 to the relevant bit in the Int_Status register.

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

16 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

6.3 On-chip oscillator

The on-chip oscillator provides the timing reference for the on-chip watchdog and the

internal timers. The on-chip oscillator is supplied by an internal supply that is connected to

V

_BATand is independent of V1/V2.

6.4 Watchdog (UJA1078/xx/WD versions)

Three watchdog modes are supported: Window, Timeout and Off. The watchdog period is

programmed via the NWP control bits in the WD_and_Status register (see Table 4). The

default watchdog period is 128 ms.

A watchdog trigger event is any write access to the WD_and_Status register. When the

watchdog is triggered, the watchdog timer is reset.

In watchdog Window mode, a watchdog trigger event within a closed watchdog window

(i.e. the first half of the window before t_trig(wd)1) will generate an SBC reset. If the watchdog

is triggered before the watchdog timer overflows in Timeout or Window mode, or within

the open watchdog window (after t_trig(wd)1but before t_trig(wd)2), the timer restarts

immediately.

The following watchdog events result in an immediate system reset:

• the watchdog overflows in Window mode

• the watchdog is triggered in the first half of the watchdog period in Window mode

• the watchdog overflows in Timeout mode while a cyclic interrupt (CI) is pending

• the state of the WDOFF pin changes in Normal mode or Standby mode

• the watchdog mode control bit (WMC) changes state in Normal mode

After a watchdog reset (short reset; see Section 6.5.1 and Table 11), the default watchdog

period is selected (NWP = 100). The watchdog can be switched off completely by forcing

pin WDOFF HIGH. The watchdog can also be switched off by setting bit WMC to 1 in

Standby mode. If the watchdog was turned off by setting WMC, any pending interrupt will

re-enable it.

Note that the state of bit WMC cannot be changed in Standby mode if an interrupt is

pending. Any attempt to change WMC when an interrupt is pending will be ignored.

6.4.1 Watchdog Window behavior

The watchdog runs continuously in Window mode.

If the watchdog overflows, or is triggered in the first half of the watchdog period (less than

t_trig(wd)1after the start of the watchdog period), a system reset will be performed.

Watchdog overflow occurs if the watchdog is not triggered within t_trig(wd)2after the start of

watchdog period.

If the watchdog is triggered in the second half of the watchdog period (at least t_trig(wd)1, but

not more than t_trig(wd)2, after the start of the watchdog period), the watchdog will be reset.

The watchdog is in Window mode when pin WDOFF is LOW, the SBC is in Normal mode

and the watchdog mode control bit (WMC) is set to 0.

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

17 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

6.4.2 Watchdog Timeout behavior

The watchdog runs continuously in Timeout mode. It can be reset at any time by a

watchdog trigger. If the watchdog overflows, the cyclic interrupt (CI) bit is set. If a CI is

already pending, a system reset is performed.

The watchdog is in Timeout mode when pin WDOFF is LOW and:

• the SBC is in Standby mode and bit WMC = 0 or

• the SBC is in Normal mode and bit WMC = 1

6.4.3 Watchdog Off behavior

The watchdog is disabled in this state.

The watchdog is in Off mode when:

• the SBC is in Off, Overtemp or Sleep modes

• the SBC is in Standby mode and bit WMC = 1

• the SBC is in any mode and the WDOFF pin is HIGH

6.5 System reset

The following events will cause the SBC to perform a system reset:

• V1 undervoltage (reset pulse length selected via external pull-up resistor on RSTN

pin)

• An external reset (RSTN forced LOW)

• Watchdog overflow (Window mode)

• Watchdog overflow in Timeout mode with cyclic interrupt (CI) pending

• Watchdog triggered too early in Window mode

• WMC value changed in Normal mode

• WDOFF pin state changed

• SBC goes to Sleep mode (MC set to 01; see Table 5) while INTN is driven LOW

• SBC goes to Sleep mode (MC set to 01; see Table 5) while

STBCC = STBCL1 = STBCL2 = WIC1 = WIC2 = 0

• SBC goes to Sleep mode (MC set to 01; see Table 5) while wake-up pending

• Software reset (SWR = 1)

• SBC leaves Overtemp mode (reset pulse length selected via external pull-up resistor

on RSTN pin)

A watchdog overflow in Timeout mode requests a cyclic interrupt (CI), if a CI is not already

pending.

The UJA1078 provides three signals for dealing with reset events:

• RSTN input/output for performing a global ECU system reset or forcing an external

reset

• EN pin, a fail-safe global enable output

• LIMP pin, a fail-safe limp home output

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

18 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

6.5.1 RSTN pin

A system reset is triggered if the bidirectional RSTN pin is forced LOW for at least t_fltrby

the microcontroller (external reset). A reset pulse is output on RSTN by the SBC when a

system reset is triggered internally.

The reset pulse width (t_w(rst)) is selectable (short or long) if the system reset was

generated by a V1 undervoltage event (see Section 6.6.2) or by the SBC leaving Off

(V_BAT> V_th(det)on) or Overtemp (temperature < T_th(rel)otp) modes. A short reset pulse is

selected by connecting a 900 Ω ±10 % resistor between pins RSTN and V1. If a resistor is

not connected, the reset pulse will be long (see Table 11).

In all other cases (e.g. watchdog-related reset events) the reset pulse length will be short.

6.5.2 EN output

The EN pin can be used to control external hardware, such as power components, or as a

general-purpose output when the system is running properly.

In Normal and Standby modes, the microcontroller can set the EN control bit (bit ENC in

the Mode_Control register; see Table 5) via the SPI interface. Pin EN will be HIGH when

ENC = 1 and MC = 10 or 11. A reset event will cause pin EN to go LOW. EN pin behavior

is illustrated in Figure 5.

STANDBY

NORMAL

STANDBY

mode

ENC

EN

RSTN

015aaa074

Fig 5. Behavior of EN pin

6.5.3 LIMP output

The LIMP pin can be used to enable the so called ‘limp home’ hardware in the event of an

ECU failure. Detectable failure conditions include SBC overtemperature events, loss of

watchdog service, RSTN or V1 clamped LOW and user-initiated or external reset events.

The LIMP pin is a battery-related, active-LOW, open-drain output.

A system reset will cause the limp home warning control bit (bit LHWC in the

Mode_Control register; see Table 5) to be set. If LHWC is already set when the system

reset is generated, bit LHC will be set which will force the LIMP pin LOW. The application

should clear LHWC after each reset event to ensure the LIMP output is not activated

during normal operation.

In Overtemp mode, bit LHC is always set and, consequently, the LIMP output is always

active. If the application manages to recover from the event that activated the LIMP

output, LHC can be cleared to deactivate the LIMP output.

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

19 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

6.6 Power supplies

6.6.1 Battery pin (BAT)

The SBC contains a single supply pin, BAT. An external diode is needed in series to

protect the device against negative voltages. The operating range is from 4.5 V to 28 V.

The SBC can handle maximum voltages up to 40 V.

If the voltage on pin BAT falls below the power-off detection threshold (V_th(det)poff), the

SBC immediately enters Off mode, which means that the voltage regulators and the

internal logic are shut down. The SBC leaves Off mode for Standby mode as soon as the

voltage rises above the power-on detection threshold, V_th(det)on. The POSI bit in the

Int_Status register is set to 1 when the SBC leaves Off mode.

6.6.2 Voltage regulator V1

Voltage regulator V1 is intended to supply the microcontroller, its periphery and additional

transceivers. V1 is supplied by pin BAT and delivers up to 250 mA at 3.3 V or 5 V

(depending on the UJA1078 version).

To prevent the device overheating at high ambient temperatures or high average currents,

an external PNP transistor can be connected as illustrated in Figure 6. In this

configuration, the power dissipation is distributed between the SBC and the PNP

transistor. Bit PDC in the Mode_Control register (Table 5) is used to regulate how the

power dissipation is distributed − if PDC = 0, the PNP transistor will be activated when the

load current reaches 85 mA (50 mA if PDC = 1) at T_vj= 150 °C. V1 will continue to deliver

85 mA while the transistor delivers the additional load current (see Figure 7 and Figure 8).

VEXCTRL

battery

VEXCC

UJA107x

BAT

V1

015aaa098

Fig 6. External PNP transistor control circuit

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

20 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

250 mA

215 mA

85 mA

50 mA

load

current

I

= 85 mA

th(act)PNP

(PDC = 0)

I

= 50 mA

th(deact)PNP

I

(PDC = 0)

V1

165 mA

PNP

current

015aaa111

Fig 7. V1 and PNP currents at a slow ramping load current of 250 mA (PDC = 0)

Figure 7 illustrates how V1 and the PNP transistor combine to supply a slow ramping load

current of 250 mA with PDC = 0. Any additional load current requirement will be supplied

by the PNP transistor, up to its current limit. If the load current continues to rise, I_V1will

increase above the selected PDC threshold (to a maximum of 250 mA).

For a fast ramping load current, V1 will deliver the required load current (to a maximum of

250 mA) until the PNP transistor has switched on. Once the transistor has been activated,

V1 will deliver 85 mA (PDC = 0) with the transistor contributing the balance of the load

current (see Figure 8).

250 mA

load

current

250 mA

I

= 85 mA

th(act)PNP

(PDC = 0)

I

0 mA

V1

−165 mA

165 mA

PNP

current

015aaa075

Fig 8. V1 and PNP currents at a fast ramping load current of 250 mA (PDC = 0)

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

21 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

For short-circuit protection, a resistor needs to be connected between pins V1 and

VEXCC to allow the current to be monitored. This resistor limits the current delivered by

the external transistor. If the voltage difference between pins VEXCC and V1 reaches

V

_th(act)Ilim, the PNP current limiting activation threshold voltage, the transistor current will

not increase further.

The thermal performance of the transistor needs to be considered when calculating the

value of this resistor. A 3.3 Ω resistor was used with the BCP52-16 (NXP Semiconductors)

employed during testing. Note that the selection of the transistor is not critical. In general,

any PNP transistor with a current amplification factor (β) of between 60 and 500 can be

used.

If an external PNP transistor is not used, pin VEXCC must be connected to V1 while pin

VEXCTRL can be left open.

One advantage of this scalable voltage regulator concept is that there are no PCB layout

restrictions when using the external PNP. The distance between the UJA1078 and the

external PNP doesn’t affect the stability of the regulator loop because the loop is realized

within the UJA1078. Therefore, it is recommended that the distance between the

UJA1078 and PNP transistor be maximized for optimal thermal distribution.

The output voltage on V1 is monitored continuously and a system reset signal is

generated if an undervoltage event occurs. A system reset is generated if the voltage on

V1 falls below the undervoltage detection voltage (V_uvd; see Table 10). The reset

threshold (90 % or 70 % of the nominal value) is set via the Reset Threshold Control bit

(RTHC) in the Int_Control register (Table 6). In addition, an undervoltage warning (a V1UI

interrupt) will be generated at 90 % of the nominal output voltage. The status of V1 can be

read via bit V1S in the WD_and_Status register (Table 4).

6.6.3 Voltage regulator V2

Voltage regulator V2 is reserved for the high-speed CAN transceiver, providing a 5 V

supply.

V2 can be activated and deactivated via the MC bits in the Mode_Control register

(Table 5). An undervoltage warning (a V2UI interrupt) is generated when the output

voltage drops below 90 % of its nominal value. The status of V2 can be read via bit V2S in

the WD_and_Status register (Table 5) in Normal mode (V2S = 1 in all other modes).

V2 can be deactivated (MC = 10) to allow the internal CAN transceiver to be supplied from

an external source or from V1. The alternative voltage source must be connected to pin

V2. All internal functions (e.g. undervoltage protection) will work normally.

6.7 CAN transceiver

The analog section of the UJA1078 CAN transceiver corresponds to that integrated into

the TJA1042/TJA1043. The transceiver is designed for high-speed (up to 1 Mbit/s) CAN

applications in the automotive industry, providing differential transmit and receive

capability to a CAN protocol controller.

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

22 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

6.7.1 CAN operating modes

6.7.1.1 Active mode

The CAN transceiver is in Active mode when:

• the SBC is in Normal mode (MC = 10 or 11)

• the transceiver is enabled (bit STBCC = 0; see Table 6)

and

• V2 is enabled and its output voltage is above its undervoltage threshold, V_uvd

or

• V2 is disabled but an external voltage source, or V1, connected to pin V2 is above its

undervoltage threshold (see Section 6.6.3)

In CAN Active mode, the transceiver can transmit and receive data via the CANH and

CANL pins. The differential receiver converts the analog data on the bus lines into digital

data which is output on pin RXDC. The transmitter converts digital data generated by a

CAN controller, and input on pin TXDC, to signals suitable for transmission over the bus

lines.

6.7.1.2 Lowpower/Off modes

The CAN transceiver will be in Lowpower mode with bus wake-up detection enabled if bit

STBCC = 1 (see Table 6). The CAN transceiver can be woken up remotely via pins CANH

and CANL in Lowpower mode.

When the SBC is in Standby mode or Sleep mode (MC = 00 or 01), the CAN transceiver

will be in Off mode if bit STBCC = 0. The CAN transceiver is powered down completely in

Off mode to minimize quiescent current consumption.

A filter at the receiver input prevents unwanted wake-up events occurring due to

automotive transients or EMI.

A recessive-dominant-recessive-dominant sequence must occur on the CAN bus within

the wake-up timeout time (t_to(wake)) to pass the wake-up filter and trigger a wake-up event

(see Figure 9; note that additional pulses may occur between the recessive/dominant

phases). The minimum recessive/dominant bus times for CAN transceiver wake-up

(t_{wake(busrec)min}and t_{wake(busdom)min}) must be satisfied (see Table 11).

recessive

dominant

recessive

dominant

wake-up

t

< t

to(wake)

wake

015aaa107

Fig 9. CAN wake-up timing diagram

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

23 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

6.7.2 Split circuit

Pin SPLIT provides a DC stabilized voltage of 0.5V_V2. It is activated in CAN Active mode

only. Pin SPLIT is floating in CAN Lowpower and Off modes. The V_SPLITcircuit can be

used to stabilize the recessive common-mode voltage by connecting pin SPLIT to the

center tap of the split termination (see Figure 10).

A transceiver in the network that is not supplied and that generates a significant leakage

current from the bus lines to ground, can result in a recessive bus voltage of < 0.5V_V2. In

this event, the split circuit will stabilize the recessive voltage at 0.5V_V2. So a start of

transmission will not generate a step in the common-mode signal which would lead to

poor ElectroMagnetic Emission (EME) performance.

V2

UJA1078

CANH

R

60 Ω

V

= 0.5 V

CC

SPLIT

CANL

SPLIT

in normal mode;

otherwise floating

GND

015aaa077

Fig 10. Stabilization circuitry and application using the SPLIT pin

6.7.3 Fail-safe features

6.7.3.1 TXDC dominant time-out function

A TXDC dominant time-out timer is started when pin TXDC is forced LOW. If the LOW

state on pin TXDC persists for longer than the TXDC dominant time-out time (t_to(dom)TXDC),

the transmitter will be disabled, releasing the bus lines to recessive state. This function

prevents a hardware and/or software application failure from driving the bus lines to a

permanent dominant state (blocking all network communications). The TXDC dominant

time-out timer is reset when pin TXDC goes HIGH. The TXDC dominant time-out time

also defines the minimum possible bit rate of 10 kbit/s.

6.7.3.2 Pull-up on TXDC pin

Pin TXDC has an internal pull-up towards V_V1to ensure a safe defined state in case the

pin is left floating.

6.8 LIN1/LIN2 transceivers

The analog sections of the UJA1078 LIN transceivers are identical to those integrated into

the TJA1021.

The transceiver is the interface between the LIN master/slave protocol controller and the

physical bus in a LIN. It is primarily intended for in-vehicle sub-networks using baud rates

from 1 kBd up to 20 kBd and is LIN 2.0/LIN 2.1/SAE J2602 compliant.

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

24 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

6.8.1 LIN operating modes

6.8.1.1 Active mode

The LIN transceivers will be in Active mode when:

• the SBC is in Normal mode (MC = 10 or 11) and

• the transceivers are enabled (STBCL1 = 0 and/or STBCL2 = 0; see Table 6) and

• the battery voltage (V_BAT) is above the LIN undervoltage recovery threshold, V_uvr(LIN)

.

In LIN Active mode, the transceivers can transmit and receive data via the LIN bus pins.

The receiver detects data streams on the LIN bus pins (LIN1 and LIN2) and transfers

them to the microcontroller via pins RXDL1 and RXDL2 (see Figure 1) - LIN recessive is

represented by a HIGH level on RXDL1/RXDL2, LIN dominant by a LOW level.

The transmit data streams of the protocol controller at the TXDL inputs (TXDL1 and

TXDL2) are converted by the transmitter into bus signals with optimized slew rate and

wave shaping to minimize EME.

6.8.1.2 Lowpower/Off modes

The LIN transceivers will be in Lowpower mode with bus wake-up detection enabled if bit

STBCLx = 1 (see Table 6). The LIN transceivers can be woken up remotely via pins LIN1

and LIN2 in Lowpower mode.

When the SBC is in Standby mode or Sleep mode (MC = 00 or 01), the LIN transceivers

will be in Off mode if bit STBCLx = 0. The LIN transceivers are powered down completely

in Off mode to minimize quiescent current consumption.

Filters at the receiver inputs prevent unwanted wake-up events due to automotive

transients or EMI.

The wake-up event must remain valid for at least the minimum dominant bus time for

wake-up of the LIN transceivers, t_{wake(busdom)min}(see Table 11).

6.8.2 Fail-safe features

6.8.2.1 General fail-safe features

The following fail-safe features have been implemented:

• Pins TXDL1 and TXDL2 have internal pull-ups towards V_V1to guarantee safe, defined

states if these pins are left floating

• The current of the transmitter output stage is limited in order to protect the transmitter

against short circuits to pin BAT

• A loss of power (pins BAT and GND) has no impact on the bus lines or on the

microcontroller. There will be no reverse currents from the bus.

6.8.2.2 TXDL dominant time-out function

A TXDL dominant time-out timer circuit prevents the bus lines being driven to a permanent

dominant state (blocking all network communications) if TXDL1 or TXDL2 is forced

permanently LOW by a hardware and/or software application failure. The timer is

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

25 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

triggered by a negative edge on the TXDL pin. If the pin remains LOW for longer than the

TXDL dominant time-out time (t_to(dom)TXDL), the transmitter is disabled, driving the bus

lines to a recessive state. The timer is reset by a positive edge on the TXDL pin.

6.9 Local wake-up input

The SBC provides 2 local wake-up pins (WAKE1 and WAKE2). The edge sensitivity

(falling, rising or both) of the wake-up pins can be configured independently via the WIC1

and WIC2 bits in the Int_Control register Table 6). These bits can also be used to disable

wake-up via the wake-up pins. When wake-up is enabled, a valid wake-up event on either

of these pins will cause a wake-up interrupt to be generated in Standby mode or Normal

mode. If the SBC is in Sleep mode when the wake-up event occurs, it will wake up and

enter Standby mode. The status of the wake-up pins can be read via the wake-up level

status bits (WLS1 and WLS2) in the WD_and_Status register (Table 4).

Note that bits WLS1 and WLS2 are only active when at least one of the wake up interrupts

is enabled (WIC1 ≠ 00 or WIC2 ≠ 00).

enable bias

disable bias

WBIASI

(internal)

WBIAS pin

WAKEx pin

Wake-up int

disable bias

wake level latched

015aaa078

Fig 11. Wake-up pin sampling synchronized with WBIAS signal

The sampling of the wake-up pins can be synchronized with the WBIAS signal by setting

bits WSE1 and WSE2 in the Int_Control register to 1 (if WSEx = 0, wake-up pins are

sampled continuously). The sampling will be performed on the rising edge of WBIAS (see

Figure 11). The sampling time, 16 ms or 64 ms, is selected via the Wake Bias Control bit

(WBC) in the Mode_Control register.

Figure 12 shows typical circuit for implementing cyclic sampling of the wake-up inputs.

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

26 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

UJA1078

BAT

47 kΩ

PDTA144E

WBIAS

biasing of

switches

WAKE1

WAKE2

t

sample of

WAKEx

sample of

WAKEx

sample of

WAKEx

GND

015aaa105

Fig 12. Typical application for cyclic sampling of wake-up signals

6.10 Interrupt output

Pin INTN is an active-LOW, open-drain interrupt output. It is driven LOW when at least

one interrupt is pending. An interrupt can be cleared by writing 1 to the corresponding bit

in the Int_Status register (Table 7). Clearing bits LWI1, LWI2 and CWI in Standby mode

only clears the interrupt status bits and not the pending wake-up. The pending wake-up is

cleared on entering Normal mode and when the corresponding standby control bit

(STBCC, STBCL1 or STBCL2) is 0.

On devices that contain a watchdog, the Cyclic Interrupt (CI) is enabled when the

watchdog switches to Timeout mode while the SBC is in Standby mode or Normal mode

(provided WDOFF = LOW). A CI is generated if the watchdog overflows in Timeout mode.

The CI is provided to alert the microcontroller when the watchdog overflows in Timeout

mode. The CI will wake up the microcontroller from a μC standby mode. After polling the

Int_Status register, the microcontroller will be aware that the application is in cyclic wake

up mode. It can then perform some checks on CAN and LIN before returning to the μC

standby mode.

6.11 Temperature protection

The temperature of the SBC chip is monitored in Normal and Standby modes. If the

temperature is too high, the SBC will go to Overtemp mode, where the RSTN pin is driven

LOW and limp home is activated. In addition, the voltage regulators and the CAN and LIN

transmitters are switched off (see also Section 6.1.6 “Overtemp mode”). When the

temperature falls below the temperature shutdown threshold, the SBC will go to Standby

mode. The temperature shutdown threshold is between 165 °C and 200 °C.

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

27 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

7. Limiting values

Table 8.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

V_x

voltage on pin x

DC value

pins V1, V2 and INTN

−0.3

7

V

pins TXDC, RXDC, EN, SDI, SDO, SCK, SCSN,

TXDL1, TXDL2, RXDL1, RXDL2, RSTN and

WDOFF

V_V1+ 0.3

pin VEXCC

V_V1− 0.3

−58

V_V1+ 0.35

+58

V

pins WAKE1, WAKE2 and WBIAS; with respect to

any other pin

pin LIMP and BAT

pin VEXCTRL

−0.3

−58

+40

V

V_BAT+ 0.3

+58

pins CANH, CANL, SPLIT, LIN1 and LIN2; with

respect to any other pin

pin DLIN; with respect to any other pin

V_BAT− 0.3 +58

V

[1]

[2]

I_R(V1-BAT)reverse current from V_V1≤ 5 V

-

250

mA

pin V1 to pin BAT

I_DLIN

V_trt

current on pin DLIN

transient voltage

−65

0

mA

V

on pins

BAT: via reverse polarity diode/capacitor

−150

+100

CANL, CANH, SPLIT: coupling with two capacitors

on the bus lines

LIN1, LIN2: coupling via 1 nF capacitor

DLIN: via 1 kΩ resistor

[3]

[4]

V_ESD

electrostatic

discharge voltage

IEC 61000-4-2

pins BAT with capacitor, CANH, CANL, LIN1 and

LIN2; via a series resistor on pins SPLIT, DLIN,

WAKE1 and WAKE2

−6

−8

+6

+8

kV

[5]

[6]

HBM

pins CANH, CANL, LIN1, LIN2, SPLIT, DLIN,

WAKE1, WAKE2

pin BAT; referenced to ground

−4

+4

+2

kV

pin TEST2; referenced to pin BAT

−1.25

−2

pin TEST2; referenced to other reference pins

any other pin

MM

−2

[7]

[8]

any pin

−300

+300

V

CDM

corner pins

any other pin

−750

−500

+750

+500

V

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

28 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

Table 8.

Limiting values …continued

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

[9]

T_vj

virtual junction

temperature

−40

+150

°C

T_stg

storage temperature

−55

−40

+150

+125

°C

T_amb

ambient

temperature

[1] A reverse diode connected between V1 (anode) and BAT (cathode) limits the voltage drop voltage from V1(+) to BAT (-).

[2] Verified by an external test house to ensure pins can withstand ISO 7637 part 2 automotive transient test pulses 1, 2a, 3a and 3b.

[3] IEC 61000-4-2 (150 pF, 330 Ω).

[4] ESD performance according to IEC 61000-4-2 (150 pF, 330 Ω) has been verified by an external test house for pins BAT, CANH, CANL,

LIN1, LIN2, WAKE1 and WAKE2. The result is equal to or better than ±6 kV.

[5] Human Body Model (HBM): according to AEC-Q100-002 (100 pF, 1.5 kΩ).

[6] V1, V2 and BAT connected to GND, emulating application circuit.

[7] Machine Model (MM): according to AEC-Q100-003 (200 pF, 0.75 μH, 10 Ω).

[8] Charged Device Model (CDM): according to AEC-Q100-011 (field Induced charge; 4 pF).

[9] In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: T_vj= T_amb+ P × R_th(vj-a), where R_th(vj-a)is a

fixed value to be used for the calculation of T_vj. The rating for T_vjlimits the allowable combinations of power dissipation (P) and ambient

temperature (T_amb).

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

29 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

8. Thermal characteristics

optional heatsink top layer

PCB copper area:

(bottom layer)

2

2 cm

optional heatsink top layer

PCB copper area:

(bottom layer)

8 cm

2

015aaa137

Layout conditions for R_th(j-a)measurements: board finish thickness 1.6 mm ±10 %, double-layer

board, board dimensions 129 mm × 60 mm, board Material FR4, Cu thickness 0.070 mm, thermal

via separation 1.2 mm, thermal via diameter 0.3 mm ±0.08 mm, Cu thickness on vias 0.025 mm.

Optional heat sink top layer of 3.5 mm × 25 mm will reduce thermal resistance (see Figure 14).

Fig 13. HTSSOP PCB

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

30 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

015aaa138

90

R

th(j-a)

(K/W)

70

without heatsink top layer

50

30

with heatsink top layer

2

0

4

6

8

10

2

PCB Cu heatsink area (cm )

Fig 14. HTSSOP32 thermal resistance junction to ambient as a function of PCB copper

area

Table 9.

Symbol Parameter

R_th(j-a)thermal resistance from junction to

ambient

Thermal characteristics

Conditions

Typ Unit

[1]

[2]

single-layer board

four-layer board

78

39

K/W

[1] According to JEDEC JESD51-2 and JESD51-3 at natural convection on 1s board.

[2] According to JEDEC JESD51-2, JESD51-5 and JESD51-7 at natural convection on 2s2p board. Board with

two inner copper layers (thickness: 35 μm) and thermal via array under the exposed pad connected to the

first inner copper layer.

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

31 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

9. Static characteristics

Table 10. Static characteristics

T_vj= −40 °C to +150 °C; V_BAT= 4.5 V to 28 V; V_BAT> V_V1; V_BAT> V_V2; R_LIN1= R_LIN2= 500 Ω; R_(CANH-CANL)= 45 Ω to 65 Ω; all

voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at V_BAT= 14 V; unless

otherwise specified.

Symbol

Supply; pin BAT

V_BATbattery supply voltage

I_BATbattery supply current

Parameter

Conditions

Min

Typ

Max

Unit

4.5

-

28

V

MC = 00 (Standby; V1 on, V2 off)

STBCC = STBCL1 = STBCL2 = 1

(CAN/LIN wake-up enabled)

WIC1 = WIC2 = 11 (WAKE interrupts

enabled)

7.5 V < V_BAT< 28 V; I_V1= 0 mA

V_RSTN= V_SCSN= V_V1

V_TXDL1= V_TXDL2= V_TXDC= V_V1

V_SDI= V_SCK= 0 V

T_vj= −40 °C

T_vj= 25 °C

-

84

77

69

99

89

81

μA

T_vj= 150 °C

MC = 01 (Sleep; V1 off, V2 off)

STBCC = STBCL1 = STBCL2 = 1

(CAN/LIN wake-up enabled)

WIC1 = WIC2 = 11 (WAKE interrupts

enabled)

7.5 V < V_BAT< 28 V; V_V1= 0 V

T_vj= −40 °C

T_vj= 25 °C

T_vj= 150 °C

-

62

57

53

1.1

72

66

59

2

μA

contributed by LIN wake-up receiver

STBCL1/STBCL2 = 1

V_LIN1= V_LIN2= V_BAT

5.5 V < V_BAT< 28 V

contributed by CAN wake-up receiver

STBCC = 1; V_CANH= V_CANL= 2.5 V

5.5 V < V_BAT< 28 V

1

0

6

5

13

10

μA

contributed by WAKE pin edge

detectors;

WIC1 = WIC2 = 11

V_WAKE1= V_WAKE2= V_BAT

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

32 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

Table 10. Static characteristics …continued

T_vj= −40 °C to +150 °C; V_BAT= 4.5 V to 28 V; V_BAT> V_V1; V_BAT> V_V2; R_LIN1= R_LIN2= 500 Ω; R_(CANH-CANL)= 45 Ω to 65 Ω; all

voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at V_BAT= 14 V; unless

otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

50

3

Unit

μA

I_BAT(add)

additional battery supply

current

5.1 V < V_BAT< 7.5 V

-

4.5 V < V_BAT< 5.1 V

V1 on (5 V version)

mA

V2 on; MC = 11

V2UIE = 1; I_V2= 0 mA

100

-

950

10

μA

CAN Active mode (recessive)

STBCC = 0; MC = 1x; V_TXDC= V_V1

I_CANH= I_CANL= 0 mA

mA

5.5 V < V_BAT< 28 V

CAN active (dominant)

STBCC = 0; MC = 1x; V_TXDC= 0 V

R_(CANH-CANL)= 45 Ω

-

70

mA

5.5 V < V_BAT< 28 V

LINx Active mode (recessive)

STBCLx = 0; MC = 1x

1300

μA

V_TXDL1= V_TXDL2= V_V1

I_DLIN= I_LIN1= I_LIN2= 0 mA

5.5 V < V_BAT< 28 V

LINx Active mode (dominant);

STBCLx = 0; MC = 1x

-

5

mA

V_TXDL1= V_TXDL2= 0 V

I_DLIN= I_LIN1= I_LIN2= 0 mA; V_BAT= 14 V

LINx Active mode (dominant);

STBCLx = 0; MC = 1x

10

V_TXDL1= V_TXDL2= 0 V

I_DLIN= I_LIN1= I_LIN2= 0 mA; V_BAT= 28 V

V_th(det)pon

V_th(det)poff

V_hys(det)pon

V_uvd(LIN)

power-on detection

threshold voltage

4.5

4.25

200

5

-

5.5

4.5

-

V

power-off detection

threshold voltage

V

power-on detection

hysteresis voltage

mV

V

LIN undervoltage detection

voltage

5.3

5.5

300

7.5

V_uvr(LIN)

LIN undervoltage recovery

voltage

5

V

V_hys(uvd)LIN

V_{uvd(ctrl)Iext}

LIN undervoltage detection

hysteresis voltage

25

mV

V

external current control

undervoltage detection

voltage

5.9

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

33 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

Table 10. Static characteristics …continued

T_vj= −40 °C to +150 °C; V_BAT= 4.5 V to 28 V; V_BAT> V_V1; V_BAT> V_V2; R_LIN1= R_LIN2= 500 Ω; R_(CANH-CANL)= 45 Ω to 65 Ω; all

voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at V_BAT= 14 V; unless

otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Voltage source; pin V1

V_O

output voltage

V_O(V1)nom= 5 V; V_BAT= 5.5 V to 28 V

4.9

5

5.1

V

I_V1= −200 mA to −5 mA

C_LIN1/2≥ 560 pF

V_O(V1)nom= 5 V; V_BAT= 5.5 V to 28 V

4.85

5

5.15

V

I

_V1= −200 mA to −5 mA

C_LIN1/2≥ 220 pF

V_O(V1)nom= 5 V; V_BAT= 5.5 V to 28 V

4.75

4.5

5

5.1

V

I

_V1= −250 mA to −200 mA

V_O(V1)nom= 5 V; V_BAT= 5.5 V to 5.75 V

_V1= −250 mA to −5 mA

I

150 °C < T_vj< 200 °C

V_O(V1)nom= 5 V; V_BAT= 5.75 V to 28 V

4.85

5

5.1

V

Ω

I

_V1= −250 mA to −5 mA

150 °C < T_vj< 200 °C

V_O(V1)nom= 3.3 V; V_BAT= 4.5 V to 28 V

3.234 3.3

3.201 3.3

3.366

3.399

3.366

3

I_V1= −250 mA to −5 mA

C_LIN1/2≥ 560 pF

V_O(V1)nom= 3.3 V; V_BAT= 4.5 V to 28 V

I_V1= −250 mA to −5 mA

C_LIN1/2≥ 220 pF

V_O(V1)nom= 3.3 V; V_BAT= 4.5 V to 28 V

2.97

-

3.3

-

I

_V1= −250 mA to −5 mA

150 °C < T_vj< 200 °C

R_(BAT-V1)

resistance between pin BAT V_O(V1)nom= 5 V; V_BAT= 4.5 V to 5.5 V

and pin V1

I

_V1= −250 mA to −5 mA

regulator in saturation

V_uvd

undervoltage detection

voltage

90 %; V_O(V1)nom= 5 V; RTHC = 0

90 %; V_O(V1)nom= 3.3 V; RTHC = 0

70 %; V_O(V1)nom= 5 V; RTHC = 1

90 %; V_O(V1)nom= 5 V

4.5

-

4.75

3.135

3.75

4.9

V

2.97

3.5

V

V_uvr

undervoltage recovery

voltage

4.56

3.025

−600

V

90 %; V_O(V1)nom= 3.3 V

3.234

−250

V

I_O(sc)

short-circuit output current

I_VEXCC= 0 mA

mA

Load regulation

ΔV_V1

voltage variation on pin V1

as a function of load current variation

V_BAT= 5.75 V to 28 V

-

25

mV

I_V1= −250 mA to −5 mA

Line regulation

ΔV_V1

voltage variation on pin V1

as a function of supply voltage variation

V_BAT= 5.5 V to 28 V; I_V1= −30 mA

-

25

8

mV

mA

PNP base; pin VEXCTRL

I_O(sc)

short-circuit output current

V_VEXCTRL≥ 4.5 V; V_BAT= 6 V to 28 V

3.5

5.8

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

34 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

Table 10. Static characteristics …continued

T_vj= −40 °C to +150 °C; V_BAT= 4.5 V to 28 V; V_BAT> V_V1; V_BAT> V_V2; R_LIN1= R_LIN2= 500 Ω; R_(CANH-CANL)= 45 Ω to 65 Ω; all

voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at V_BAT= 14 V; unless

otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

I_th(act)PNP

PNP activation threshold

current

load current increasing; external PNP

transistor connected - see Section 6.6.2

PDC 0

74

44

130

85

191

99

mA

PDC 0; T_vj= 150 °C

PDC 1

76

114

59

PDC 1; T_vj= 150 °C

50

I_th(deact)PNP

PNP deactivation threshold load current falling; external PNP

current

transistor connected - see Section 6.6.2

PDC 0

40

44

11

12

76

50

22

15

120

59

mA

PDC 0; T_vj= 150 °C

PDC 1

36

PDC 1; T_vj= 150 °C

18

PNP collector; pin VEXCC

V_th(act)Ilimcurrent limiting activation

threshold voltage

measured across resistor connected

between pins VEXCC and V1 (see

Section 6.6.2)

240

-

330

mV

2.97 V ≤ V_V1≤ 5.5 V

6 V < V_BAT< 28 V

Voltage source; pin V2

V_O

output voltage

V_BAT= 5.5 V to 28 V

I_V2= −100 mA to 0 mA

4.75

-

5

-

5.25

60

V

V_BAT= 6 V to 28 V

I_V2= −120 mA to 0 mA

V

ΔV_V2

voltage variation on pin V2

as a function of supply voltage variation

V_BAT= 5.5 V to 28 V

mV

I_V2= −10 mA

as a function of load current variation;

6 V < V_BAT< 28 V

-

80

mV

I_V2= −100 mA to −5 mA

V_uvd

undervoltage detection

voltage

4.5

-

4.70

4.75

80

V

V_uvr

undervoltage recovery

voltage

4.55

20

V

V_uvhys

undervoltage hysteresis

voltage

mV

mA

I_O(sc)

short-circuit output current

V_V2= 0 V to 5.5 V

−250

−100

Serial peripheral interface inputs; pins SDI, SCK and SCSN

V_th(sw)switching threshold voltage V_V1= 2.97 V to 5.5 V

V_hys(i)

0.3V_V1

100

-

0.7V_V1

900

V

input hysteresis voltage

V_V1= 2.97 V to 5.5 V

-

mV

kΩ

R_pd(SCK)

pull-down resistance on pin

SCK

50

130

400

R_pu(SCSN)

pull-up resistance on pin

SCSN

50

130

400

kΩ

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

35 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

Table 10. Static characteristics …continued

T_vj= −40 °C to +150 °C; V_BAT= 4.5 V to 28 V; V_BAT> V_V1; V_BAT> V_V2; R_LIN1= R_LIN2= 500 Ω; R_(CANH-CANL)= 45 Ω to 65 Ω; all

voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at V_BAT= 14 V; unless

otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

I_LI(SDI)

input leakage current on pin

SDI

−5

-

+5

μA

Serial peripheral interface data output; pin SDO

I_OH

I_OL

I_LO

HIGH-level output current

LOW-level output current

output leakage current

V_SCSN= 0 V; V_O= V_V1− 0.4 V

V_V1= 2.97 V to 5.5 V

−30

1.6

−5

-

−1.6

30

5

mA

μA

V_SCSN= 0 V; V_O= 0.4 V

V_V1= 2.97 V to 5.5 V

V_SCSN= V_V1; V_O= 0 V to V_V1

V_V1= 2.97 V to 5.5 V

Reset output with clamping detection; pin RSTN

I_OH

HIGH-level output current

V_RSTN= 0.8V_V1

V_V1= 2.97 V to 5.5 V

−1500

-

−100

μA

I_OL

LOW-level output current

strong; V_RSTN= 0.2V_V1

V_V1= 2.97 V to 5.5 V

−40 °C < T_vj< 200 °C

4.9

40

mA

weak; V_RSTN= 0.8V_V1

V_V1= 2.97 V to 5.5 V

−40 °C < T_vj< 200 °C

200

-

540

μA

V

V_OL

LOW-level output voltage

HIGH-level output voltage

V_V1= 1 V to 5.5 V

pull-up resistor to V_V1≥ 900 Ω

−40 °C < T_vj< 200 °C; V_BAT< 28 V

0

0.2V_V1

0.5

V_V1= 2.975 V to 5.5 V

pull-up resistor to V1 ≥ 900 Ω;

−40 °C < T_vj< 200 °C

0

V

V_OH

-40 °C < T_vj< 200 °C

0.8V_V1

V_V1

0.3

+

V

V_th(sw)

V_hys(i)

Interrupt output; pin INTN

switching threshold voltage V_V1= 2.97 V to 5.5 V

0.3V_V1

100

-

0.7V_V1

900

V

input hysteresis voltage

V_V1= 2.97 V to 5.5 V

mV

I_OL

LOW-level output current

V_OL= 0.4 V

1.6

-

15

mA

Enable output; pin EN

I_OH

HIGH-level output current

V_OH= V_V1− 0. 4 V

−20

−1.6

V_V1= 2.97 V to 5.5 V

I_OL

LOW-level output current

LOW-level output voltage

V_OL= 0.4 V; V_V1= 2.97 V to 5.5 V

1.6

-

20

mA

V

V_OL

I_OL= 20 μA; V_V1= 1.5 V

0.4

Watchdog off input; pin WDOFF

V_th(sw)

V_hys(i)

R_pupd

switching threshold voltage V_V1= 2.97 V to 5.5 V

0.3V_V1

100

5

-

0.7V_V1

900

V

input hysteresis voltage

V_V1= 2.97 V to 5.5 V

-

mV

kΩ

pull-up/pull-down resistance V_V1= 2.97 V to 5.5 V

10

20

Wake input; pin WAKE1, WAKE2

V_th(sw)

V_hys(i)

I_pu

switching threshold voltage

2

-

3.75

1000

0

V

input hysteresis voltage

pull-up current

100

−2

mV

μA

V_WAKE= 0 V for t < t_wake

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

36 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

Table 10. Static characteristics …continued

T_vj= −40 °C to +150 °C; V_BAT= 4.5 V to 28 V; V_BAT> V_V1; V_BAT> V_V2; R_LIN1= R_LIN2= 500 Ω; R_(CANH-CANL)= 45 Ω to 65 Ω; all

voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at V_BAT= 14 V; unless

otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

I_pd

pull-down current

V_WAKE= V_BATfor t < t_wake

0

-

2

μA

Limp home output; pin LIMP

I_Ooutput current

V_LIMP= 0.4 V; LHC = 1

T_vj= −40 °C to 200 °C

0.8

1

-

8

7

mA

Wake bias output; pin WBIAS

I_Ooutput current

CAN transmit data input; pin TXDC

V_WBIAS= 1.4 V

V_th(sw)

V_hys(i)

R_pu

switching threshold voltage V_V1= 2.97 V to 5.5 V

0.3V_V1

100

4

-

0.7V_V1

900

V

input hysteresis voltage

pull-up resistance

V_V1= 2.97 V to 5.5 V

-

mV

kΩ

12

25

CAN receive data output; pin RXDC

I_OH

HIGH-level output current

CAN Active mode

−20

-

−1.5

mA

V_RXDC= V_V1− 0.4 V

I_OL

LOW-level output current

pull-up resistance

V_RXDC= 0.4 V

1.6

4

-

20

25

mA

R_pu

MC = 00; Standby mode

12

kΩ

High-speed CAN bus lines; pins CANH and CANL

V_O(dom)

dominant output voltage

CAN Active mode

V_V2= 4.5 V to 5.5 V; V_TXDC= 0 V

R_(CANH-CANL)= 60 Ω

pin CANH

pin CANL

2.75

0.5

3.5

1.5

-

4.5

V

2.25

400

V

V_dom(TX)sym

V_O(dif)bus

transmitter dominant voltage V_dom(TX)sym= V_V2− V_CANH− V_CANL

−400

mV

symmetry

R_(CANH-CANL)= 60 Ω

bus differential output

voltage

CAN Active mode (dominant)

V_V2= 4.75 V to 5.25 V; V_TXDC= 0 V

R_(CANH-CANL)= 45 Ω to 65 Ω

1.5

−50

2

-

3.0

+50

3

V

CAN Active mode (recessive)

0

mV

V

V_V2= 4.5 V to 5.5 V; V_TXDC= V_V1

R_(CANH-CANL)= no load

V_O(rec)

recessive output voltage

CAN Active mode; V_V2= 4.5 V to 5.5 V

V_TXDC= V_V1

0.5V_V2

R_(CANH-CANL)= no load

CAN Lowpower/Off mode

R_(CANH-CANL)= no load

−0.1

-

+0.1

V

I_O(dom)

dominant output current

recessive output current

CAN Active mode

V_TXDC= 0 V; V_V2= 5 V

pin CANH; V_CANH= 0 V

pin CANL; V_CANL= 40 V

−100

40

−70

70

-

−40

100

3

mA

I_O(rec)

V_CANL= V_CANH= −27 V to +32 V

−3

V_TXDC= V_V1; V_V2= 4.5 V to 5.5 V

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

37 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

Table 10. Static characteristics …continued

T_vj= −40 °C to +150 °C; V_BAT= 4.5 V to 28 V; V_BAT> V_V1; V_BAT> V_V2; R_LIN1= R_LIN2= 500 Ω; R_(CANH-CANL)= 45 Ω to 65 Ω; all

voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at V_BAT= 14 V; unless

otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_th(RX)dif

differential receiver

threshold voltage

CAN Active mode

0.5

0.7

0.9

V

V_V2= 4.5 V to 5.5 V

−30 V < V_CANH< +30 V

−30 V < V_CANL< +30 V

CAN Lowpower mode

−12 V < V_CANH< +12 V

−12 V < V_CANL< +12 V

0.4

40

0.7

1.15

400

V

V_hys(RX)dif

differential receiver

hysteresis voltage

CAN Active mode

120

mV

V_V2= 4.5 V to 5.5 V

−30 V < V_CANH< +30 V

−30 V < V_CANL< +30 V

R_i(cm)

ΔR_i

common-mode input

resistance

CAN Active mode; V_V2= 5 V

V_CANH= V_CANL= 5 V

9

15

-

28

+1

52

20

kΩ

%

input resistance deviation

CAN Active mode; V_V2= 5 V

V_CANH= V_CANL= 5 V

−1

19

-

R_i(dif)

C_i(cm)

differential input resistance CAN Active mode; V_V2= 5.5 V

30

-

kΩ

pF

V_CANH= V_CANL= −35 V to +35 V

common-mode input

capacitance

CAN Active mode; not tested

C_i(dif)

I_LI

differential input capacitance CAN Active mode; not tested

-

10

+5

pF

input leakage current

V_BAT= 0 V; V_V2= 0 V

V_CANH= V_CANL= 5 V

−5

μA

CAN bus common mode stabilization output; pin SPLIT

V_O

output voltage

leakage current

CAN Active mode

V_V2= 4.5 V to 5.5 V

I_SPLIT= −500 μA to 500 μA

0.3V_V20.5V_V20.7V_V2

V

CAN Active mode

0.45 × 0.5 ×

0.55 ×

V_V2

V

V_V2= 4.5 V to 5.5 V; R_L≥ 1 MΩ

V_V2

I_L

CAN Lowpower/Off mode or Active

mode with V_V2< 4.5 V

−5

-

+5

μA

V_SPLIT= −30 V to + 30 V

LIN transmit data input; pin TXDL1, TXDL2

V_th(sw)

V_hys(i)

R_pu

switching threshold voltage V_V1= 2.97 V to 5.5 V

0.3V_V1

100

4

-

0.7V_V1

900

V

input hysteresis voltage

pull-up resistance

V_V1= 2.97 V to 5.5 V

-

mV

kΩ

12

25

LIN receive data output; pin RXDL1, RXDL2

I_OH

HIGH-level output current

LIN Active mode

−20

-

−1.5

mA

V_RXDL1= V_RXDL2= V_V1− 0.4 V

I_OL

LOW-level output current

pull-up resistance

V_RXDL1= V_RXDL2= 0.4 V

MC = 00; Standby mode

1.6

4

-

20

25

mA

R_pu

12

kΩ

LIN bus line; pin LIN1, LIN2

I_{BUS_LIM}

current limitation for driver

dominant state

LIN Active mode

V_BAT= V_LIN1= V_LIN2= 18 V

V_TXDL1= V_TXDL2= 0 V

40

-

100

mA

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

38 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

Table 10. Static characteristics …continued

T_vj= −40 °C to +150 °C; V_BAT= 4.5 V to 28 V; V_BAT> V_V1; V_BAT> V_V2; R_LIN1= R_LIN2= 500 Ω; R_(CANH-CANL)= 45 Ω to 65 Ω; all

voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at V_BAT= 14 V; unless

otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

[1]

I_{BUS_PAS_rec}

receiver recessive input

leakage current

V_LIN1= V_LIN2= 28 V

V_BAT= 5.5 V; V_TXDL1= V_TXDL2= V_V1

-

2

μA

I_{BUS_PAS_dom}receiver dominant input

leakage current including

pull-up resistor

V

_TXDL1= V_TXDL2= V_V1

−10

-

+10

μA

V_LIN1= V_LIN2= 0 V; V_BAT= 14 V

V_BAT= V_GND= 28 V; V_LIN1= V_LIN2= 0 V

V_BAT= 0 V; V_LIN1= V_LIN2= 28 V

V_BAT= 5.5 V to 18 V

I_L(log)

loss of ground leakage

current

−100

-

10

μA

V

[1]

I_L(lob)

loss of battery leakage

current

-

2

V_rec(RX)

receiver recessive voltage

0.6 ×

V_BAT

-

V_dom(RX)

receiver dominant voltage

V_BAT= 5.5 V to 18 V

-

0.4V_BAT

V

V_th(cntr)RX

receiver center threshold

voltage

V_th(cntr)RX= (V_th(rec)RX+ V_th(dom)RX)/2

V_BAT= 5.5 V to 18 V; LIN Active mode

0.475 0.5 ×

× V_BATV_BAT

0.525 ×

V_BAT

V_th(hys)RX

receiver hysteresis threshold V_th(hys)RX= V_th(rec)RX− V_th(dom)RX

0.05 × 0.15 × 0.175 ×

V

voltage

V_BAT= 5.5 V to 18 V; LIN Active mode

V_BAT

C_ext

external capacitance

dominant output voltage

on pins LIN1 and LIN2

-

30

pF

V

V_O(dom)

V_TXDL1= V_TXDL2= 0 V; V_BAT= 7 V

LIN Active mode

1.4

V

_TXDL1= V_TXDL2= 0 V; V_BAT= 18 V

-

2.0

1

V

LIN Active mode

LIN bus termination; pin DLIN

ΔV_(DLIN-BAT)

voltage difference between 5 mA < I_DLIN< 20 mA

pin DLIN and pin BAT

0.4

0.65

Temperature protection

T_th(act)otpovertemperature protection

165

126

180

138

200

150

°C

activation threshold

temperature

T_th(rel)otp

overtemperature protection

release threshold

temperature

[1] Guaranteed by design.

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

39 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

10. Dynamic characteristics

Table 11. Dynamic characteristics

T_vj= −40 °C to +150 °C; V_BAT= 4.5 V to 28 V; V_BAT> V_V1; V_BAT> V_V2; R_LIN1= R_LIN2= 500 Ω; R_(CANH-CANL)= 45 Ω to 65 Ω; all

voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at V_BAT= 14 V; unless

otherwise specified.

Symbol

Parameter

Conditions

Min

Typ Max

Unit

Voltage source; pin V1

t_d(uvd)

undervoltage detection

delay time

V_V1falling; dV_V1/dt = 0.1 V/μs

7

-

23

μs

t_det(CL)L

LOW-level clamping

detection time

V_V1< 0.9V_O(V1)nom; V1 active

95

140

ms

Voltage source; pin V2

t_d(uvd)undervoltage detection

delay time

Serial peripheral interface timing; pins SCSN, SCK, SDI and SDO

V_V2falling, dV_V2/dt = 0.1 V/us

7

-

23

μs

t_cy(clk)

clock cycle time

V_V1= 2.97 V to 5.5 V

320

110

-

ns

t_SPILEAD

SPI enable lead time

V_V1= 2.97 V to 5.5 V; clock is LOW

when SPI select falls

t_SPILAG

SPI enable lag time

V_V1= 2.97 V to 5.5 V; clock is LOW

when SPI select rises

140

-

ns

t_clk(H)

t_clk(L)

t_su(D)

t_h(D)

clock HIGH time

V_V1= 2.97 V to 5.5 V

160

0

-

ns

clock LOW time

-

data input set-up time

data input hold time

data output valid time

-

80

-

t_v(Q)

pin SDO; V_V1= 2.97 V to 5.5 V

C_L= 100 pF

110

t_WH(S)

chip select pulse width HIGH V_V1= 2.97 V to 5.5 V

20

-

ns

Reset output; pin RSTN

t_w(rst)

reset pulse width

long; I_pu(RSTN)< 100 μA; no pull-up

short; R_pu(RSTN)= 900 Ω to 1100 Ω

20

3.6

95

-

25

5

ms

t_det(CL)L

t_fltr

LOW-level clamping

detection time

RSTN driven HIGH internally but RSTN

remains LOW

140

filter time

7

-

18

μs

Watchdog off input; pin WDOFF

t_fltrfilter time

Wake input; pin WAKE1, WAKE2

0.9

2.3

ms

t_wake

t_d(po)

wake-up time

10

-

40

μs

power-on delay time

113

278

CAN transceiver timing; pins CANH, CANL, TXDC and RXDC

t_{d(TXDCH-RXDCH)}delay time from TXDC HIGH 50 % V_TXDCto 50 % V_RXDC

60

-

235

ns

to RXDC HIGH

V_V2= 4.5 V to 5.5 V

R_(CANH-CANL)= 60 Ω

C_(CANH-CANL)= 100 pF; C_RXDC= 15 pF

f_TXDC= 250 kHz

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

40 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

Table 11. Dynamic characteristics …continued

T_vj= −40 °C to +150 °C; V_BAT= 4.5 V to 28 V; V_BAT> V_V1; V_BAT> V_V2; R_LIN1= R_LIN2= 500 Ω; R_(CANH-CANL)= 45 Ω to 65 Ω; all

voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at V_BAT= 14 V; unless

otherwise specified.

Symbol

Parameter

Conditions

Min

Typ Max

Unit

t_{d(TXDCL-RXDCL)}delay time from TXDC LOW 50 % V_TXDCto 50 % V_RXDC

60

-

235

ns

to RXDC LOW

V_V2= 4.5 V to 5.5 V

R_(CANH-CANL)= 60 Ω

C_(CANH-CANL)= 100 pF; C_RXDC= 15 pF

f_TXDC= 250 kHz

t_{d(TXDC-busdom)}

t_{d(TXDC-busrec)}

t_{d(busdom-RXDC)}

delay time from TXDC to

bus dominant

V_V2= 4.5 V to 5. 5 V

-

70

90

75

-

ns

R_(CANH-CANL)= 60 Ω

C_(CANH-CANL)= 100 pF

delay time from TXDC to

bus recessive

V_V2= 4.5 V to 5.5 V

R_(CANH-CANL)= 60 Ω

C_(CANH-CANL)= 100 pF

delay time from bus

dominant to RXDC

V_V2= 4.5 V to 5.5 V

R_(CANH-CANL)= 60 Ω

C_(CANH-CANL)= 100 pF

C_RXDC= 15 pF

t_{d(busrec-RXDC)}

delay time from bus

recessive to RXDC

V_V2= 4.5 V to 5.5 V

R_(CANH-CANL)= 60 Ω

C_(CANH-CANL)= 100 pF

C_RXDC= 15 pF

-

95

-

ns

t_{wake(busdom)min}minimum bus dominant

wake-up time

first pulse (after first recessive) for

wake-up on pins CANH and CANL

Sleep mode

0.5

3

μs

second pulse for wake-up on pins

CANH and CANL

0.5

0.4

1.8

-

3

μs

ms

t_{wake(busrec)min}

minimum bus recessive

wake-up time

first pulse for wake-up on pins CANH

and CANL; Sleep mode

3

second pulse (after first dominant) for

wake-up on pins CANH and CANL

3

t_to(wake)

wake-up time-out time

between wake-up and confirm

messages; Sleep mode

1.2

4.5

t_to(dom)TXDC

TXDC dominant time-out

time

CAN online; V_V2= 4.5 V to 5.5 V

V_TXDC= 0 V

LIN transceivers; pins LIN1, LIN2, TXDL1, TXDL2, RXDL1, RXDL2

[1]

[2]

δ1

duty cycle 1

V

_{th(rec)RX(max)}= 0.744V_BAT

V_{th(dom)RX(max)}= 0.581V_BAT; t_bit= 50 μs

_BAT= 7 V to 18 V; LSC = 0

0.396

-

V

[1]

[2]

V_{th(rec)RX(max)}= 0.76V_BAT

V_{th(dom)RX(max)}= 0.593V_BAT; t_bit= 50 μs

V_BAT= 5.5 V to 7 V; LSC = 0

0.396

-

[2]

[3]

δ2

duty cycle 2

V

_{th(rec)RX(min)}= 0.422V_BAT

-

0.581

V_{th(dom)RX(min)}= 0.284V_BAT;t_bit= 50 μs

V_BAT= 7.6 V to 18 V; LSC = 0

[2]

[3]

V

_{th(rec)RX(min)}= 0.41V_BAT

V_{th(dom)RX(min)}= 0.275V_BAT; t_bit= 50 μs

V_BAT= 6.1 V to 7.6 V; LSC = 0

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

41 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

Table 11. Dynamic characteristics …continued

T_vj= −40 °C to +150 °C; V_BAT= 4.5 V to 28 V; V_BAT> V_V1; V_BAT> V_V2; R_LIN1= R_LIN2= 500 Ω; R_(CANH-CANL)= 45 Ω to 65 Ω; all

voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at V_BAT= 14 V; unless

otherwise specified.

Symbol

Parameter

Conditions

Min

Typ Max

Unit

[1]

[2]

δ3

duty cycle 3

V_{th(rec)RX(max)}= 0.778V_BAT

V_{th(dom)RX(max)}= 0.616V_BAT

t_bit= 96 μs; V_BAT= 7 V to 18 V; LSC = 1

0.417

-

[1]

[2]

V

_{th(rec)RX(max)}= 0.797V_BAT

_{th(dom)RX(max)}= 0.630V_BAT

0.417

-

t_bit= 96 μs; V_BAT= 5.5 V to 7 V; LSC = 1

[2]

[3]

δ4

duty cycle 4

V

_{th(rec)RX(min)}= 0.389V_BAT

_{th(dom)RX(min)}= 0.251V_BAT;t_bit= 96 μs

_BAT= 7.6 V to 18 V; LSC = 1

-

0.590

6

[2]

[3]

V_{th(rec)RX(min)}= 0.378V_BAT

V_{th(dom)RX(min)}= 0.242V_BAT; t_bit= 96 μs

V_BAT= 6.1 V to 7.6V; LSC = 1

-

t_PD(RX)r

rising receiver propagation

delay

V_BAT= 5.5 V to 18 V

R_RXDL1= R_RXDL2= 2.4 kΩ

C_RXDL1= C_RXDL2= 20 pF

-

μs

t_PD(RX)f

falling receiver propagation V_BAT= 5.5 V to 18 V

delay

-

6

R_RXDL1= R_RXDL2= 2.4 kΩ

C_RXDL1= C_RXDL2= 20 pF

[4]

t_PD(RX)sym

receiver propagation delay

symmetry

V_BAT= 5.5 V to 18 V

R_RXDL1= R_RXDL2= 2.4 kΩ

C_RXDL1= C_RXDL2= 20 pF

−2

+2

t_{wake(busdom)min}minimum bus dominant

wake-up time

28

20

-

104

80

μs

t_to(dom)TXDL

TXDL dominant time-out

time

LIN online mode; V_TXDL= 0 V

ms

Wake bias output; pin WBIAS

t_WBIASL

t_cy

WBIAS LOW time

cycle time

227

-

278

μs

WBC = 1

WBC = 0

58.1

14.5

71.2

17.8

ms

Watchdog

[5]

[7]

t_trig(wd)1

watchdog trigger time 1

watchdog trigger time 2

Normal mode

watchdog Window mode only

0.45 ×

-

0.555 × ms

NWP^[6]

t_trig(wd)2

Normal, Standby and Sleep modes

watchdog Window mode only

0.9 ×

1.11 ×

ms

NWP^[6]

Oscillator

f_osc

oscillator frequency

460.8 512 563.2

kHz

t_{bus(rec)(min)}

-------------------------------

[1] δ1, δ3 =

. Variable t_{bus(rec)(min)}is illustrated in the LIN timing diagram in Figure 18.

2 × t_bit

[2] Bus load conditions are: C_L= 1 nF and R_L= 1 kΩ; C_L= 6.8 nF and R_L= 660 Ω; C_L= 10 nF and R_L= 500 Ω.

t_{bus(rec)(max)}

-------------------------------

[3] δ2, δ4 =

. Variable t_{bus(rec)(max)}is illustrated in the LIN timing diagram in Figure 18.

2 × t_bit

[4] t_PD(RX)sym= t_PD(RX)r− t_PD(RX)f

.

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

42 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

[5] A system reset will be performed if the watchdog is in Window mode and is triggered less than t_trig(wd)1after the start of the watchdog

period (or in the first half of the watchdog period).

[6] The nominal watchdog period is programmed via the NWP control bits in the WD_and_Status register (see Table 4); valid in watchdog

Window mode only.

[7] The watchdog will be reset if it is in window mode and is triggered at least t_trig(wd)1, but not more than t_trig(wd)2, after the start of the

watchdog period (or in the second half of the watchdog period). A system reset will be performed if the watchdog is triggered more than

t

_trig(wd)2after the start of the watchdog period (watchdog overflows).

BAT

RXDC

CANH

CANL

R

− R

C

− C

CANL

CANH

CANL

CANH

SBC

C

RXDC

TXDC

GND

015aaa079

Fig 15. Timing test circuit for CAN transceiver

HIGH

LOW

TXDC

CANH

CANL

dominant

0.9 V

0.5 V

V

O(dif)bus

recessive

HIGH

RXDC

LOW

t

d(TXDC-busrec)

d(TXDC-busdom)

t

d(busrec-RXDC)

d(busdom-RXDC)

t

d(TXDCH-RXDCH)

d(TXDCL-RXDCL)

015aaa151

Fig 16. CAN transceiver timing diagram

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

43 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

BAT

RXDL1

TXDL1

RXDL2

TXDL2

DLIN

R

LIN1

C

RXDL1

RXDL2

LIN1

LIN2

C

LIN1

SBC

R

LIN2

C

LIN2

GND

015aaa081

Fig 17. Timing test circuit for LIN transceivers

t

bit

V

/V

TXDL1 TXDL2

t

bus(rec)(min)

bus(dom)(max)

V

BAT

V

th(rec)RX(max)

thresholds of

receiving node A

th(dom)RX(max)

LIN1/LIN2

bus signal

V

th(rec)RX(min)

thresholds of

receiving node B

th(dom)RX(min)

t

bus(rec)(max)

bus(dom)(min)

output of receiving

node A

V

/

RXDL1

RXDL2

t

PD(RX)r

PD(RX)f

output of receiving

node B

V

/

RXDL1

RXDL2

t

PD(RX)f

PD(RX)r

015aaa131

Fig 18. Timing diagram LIN transceivers

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

44 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

SCS

SCK

t

WH(S)

t

T

SPILAG

SPILEAD

cy(clk)

t

clk(L)

clk(H)

t

h(D)

su(D)

SDI

MSB

LSB

X

t

v(Q)

floating

SDO

X

MSB

LSB

015aaa045

Fig 19. SPI timing diagram

11. Test information

11.1 Quality information

This product has been qualified in accordance with the Automotive Electronics Council

(AEC) standard Q100 - Failure mechanism based stress test qualification for integrated

circuits, and is suitable for use in automotive applications.

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

45 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

12. Package outline

HTSSOP32: plastic thermal enhanced thin shrink small outline package; 32 leads;

body width 6.1 mm; lead pitch 0.65 mm; exposed die pad

SOT549-1

E

A

D

X

c

H

v

M

A

y

exposed die pad side

E

D

h

Z

32

17

A

(A )

3

2

E

A

h

A

1

pin 1 index

θ

L

p

L

detail X

1

16

w

M

b

e

p

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions).

A

(1)

(2)

UNIT

A

b

c

D

E

e

H

L

p

v

w

y

Z

θ

1

2

3

p

h

E

max.

8^o

0^o

0.15 0.95

0.05 0.85

0.30 0.20 11.1

0.19 0.09 10.9

5.1

4.9

6.2

6.0

3.6

3.4

8.3

7.9

0.75

0.50

0.78

0.48

mm

1.1

0.65

1

0.2

0.25

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

03-04-07

05-11-02

SOT549-1

MO-153

Fig 20. Package outline SOT549-1 (HTSSOP32)

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

46 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

13. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

13.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

13.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

13.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath specifications, including temperature and impurities

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

47 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

13.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to

higher minimum peak temperatures (see Figure 21) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 12 and 13

Table 12. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 13. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 21.

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

48 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 21. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

49 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

14. Revision history

Table 14. Revision history

Document ID

UJA1078_2

Release date

Data sheet status

Change notice

Supersedes

20100527

Product specification

-

UJA1078_1

Modifications:

• Template upgraded to Rev. 2.11 including revised legal information

• Figure 16, Figure 18: revised

• Table 4: bit 7: WOS revised

• Table 8: revised values/conditions - V_ESD, I_R(V1-BAT)

• Table 9: added

• Table 10: revised parameter values/conditions - V_th(cntr)RX, V_th(hys)RX, V_OLfor RSTN pin, I_Ofor

LIMP pin; R_(BAT-V1); V_uvrfor pin V1

• Table 11: revised parameter values/conditions - t_det(CL)Lfor RSTN pin

• Section 6.7.1.2, Section 6.8.1.2, Table 11: parameters renamed to t_{wake(busdom)min}, t_{wake(busrec)min}

UJA1078_1

20091118

Product specification

-

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

50 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

15. Legal information

15.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

suitable for use in medical, military, aircraft, space or life support equipment,

15.2 Definitions

nor in applications where failure or malfunction of an NXP Semiconductors

product can reasonably be expected to result in personal injury, death or

severe property or environmental damage. NXP Semiconductors accepts no

liability for inclusion and/or use of NXP Semiconductors products in such

equipment or applications and therefore such inclusion and/or use is at the

customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

15.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Suitability for use in automotive applications — This NXP

Semiconductors product has been qualified for use in automotive

applications. The product is not designed, authorized or warranted to be

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

51 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

UJA1078_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

52 of 53

UJA1078

NXP Semiconductors

High-speed CAN/dual LIN core system basis chip

17. Contents

1

General description. . . . . . . . . . . . . . . . . . . . . . 1

6.7.3.1

6.7.3.2

6.8

TXDC dominant time-out function . . . . . . . . . 24

Pull-up on TXDC pin . . . . . . . . . . . . . . . . . . . 24

LIN1/LIN2 transceivers . . . . . . . . . . . . . . . . . 24

LIN operating modes . . . . . . . . . . . . . . . . . . . 25

Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Lowpower/Off modes. . . . . . . . . . . . . . . . . . . 25

Fail-safe features . . . . . . . . . . . . . . . . . . . . . . 25

General fail-safe features. . . . . . . . . . . . . . . . 25

TXDL dominant time-out function . . . . . . . . . 25

Local wake-up input. . . . . . . . . . . . . . . . . . . . 26

Interrupt output. . . . . . . . . . . . . . . . . . . . . . . . 27

Temperature protection . . . . . . . . . . . . . . . . . 27

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 2

General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

CAN transceiver . . . . . . . . . . . . . . . . . . . . . . . . 2

LIN transceivers . . . . . . . . . . . . . . . . . . . . . . . . 2

Power management . . . . . . . . . . . . . . . . . . . . . 2

Control and Diagnostic features . . . . . . . . . . . . 3

Voltage regulators. . . . . . . . . . . . . . . . . . . . . . . 3

2.1

2.2

2.3

2.4

2.5

2.6

6.8.1

6.8.1.1

6.8.1.2

6.8.2

6.8.2.1

6.8.2.2

6.9

3

4

Ordering information. . . . . . . . . . . . . . . . . . . . . 4

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6.10

6.11

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

7

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 28

Thermal characteristics . . . . . . . . . . . . . . . . . 30

Static characteristics . . . . . . . . . . . . . . . . . . . 32

Dynamic characteristics. . . . . . . . . . . . . . . . . 40

Test information . . . . . . . . . . . . . . . . . . . . . . . 45

Quality information. . . . . . . . . . . . . . . . . . . . . 45

Package outline. . . . . . . . . . . . . . . . . . . . . . . . 46

8

6

6.1

Functional description . . . . . . . . . . . . . . . . . . . 6

System Controller . . . . . . . . . . . . . . . . . . . . . . 7

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Off mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 9

Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Overtemp mode . . . . . . . . . . . . . . . . . . . . . . . 10

SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Register map . . . . . . . . . . . . . . . . . . . . . . . . . 11

WD_and_Status register. . . . . . . . . . . . . . . . . 12

Mode_Control register . . . . . . . . . . . . . . . . . . 13

Int_Control register. . . . . . . . . . . . . . . . . . . . . 14

Int_Status register. . . . . . . . . . . . . . . . . . . . . . 16

On-chip oscillator . . . . . . . . . . . . . . . . . . . . . . 17

Watchdog (UJA1078/xx/WD versions) . . . . . . 17

Watchdog Window behavior. . . . . . . . . . . . . . 17

Watchdog Timeout behavior. . . . . . . . . . . . . . 18

Watchdog Off behavior. . . . . . . . . . . . . . . . . . 18

System reset. . . . . . . . . . . . . . . . . . . . . . . . . . 18

RSTN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

EN output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

LIMP output . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Power supplies . . . . . . . . . . . . . . . . . . . . . . . . 20

Battery pin (BAT) . . . . . . . . . . . . . . . . . . . . . . 20

Voltage regulator V1 . . . . . . . . . . . . . . . . . . . . 20

Voltage regulator V2 . . . . . . . . . . . . . . . . . . . . 22

CAN transceiver . . . . . . . . . . . . . . . . . . . . . . . 22

CAN operating modes . . . . . . . . . . . . . . . . . . 23

Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Lowpower/Off modes . . . . . . . . . . . . . . . . . . . 23

Split circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Fail-safe features . . . . . . . . . . . . . . . . . . . . . . 24

9

10

11

11.1

12

6.1.1

6.1.2

6.1.3

6.1.4

6.1.5

6.1.6

6.2

6.2.1

6.2.2

6.2.3

6.2.4

6.2.5

6.2.6

6.3

13

Soldering of SMD packages. . . . . . . . . . . . . . 47

Introduction to soldering. . . . . . . . . . . . . . . . . 47

Wave and reflow soldering. . . . . . . . . . . . . . . 47

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 47

Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 48

13.1

13.2

13.3

13.4

14

Revision history . . . . . . . . . . . . . . . . . . . . . . . 50

15

Legal information . . . . . . . . . . . . . . . . . . . . . . 51

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 51

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 52

15.1

15.2

15.3

15.4

6.4

6.4.1

6.4.2

6.4.3

6.5

6.5.1

6.5.2

6.5.3

6.6

6.6.1

6.6.2

6.6.3

6.7

6.7.1

6.7.1.1

6.7.1.2

6.7.2

6.7.3

16

17

Contact information . . . . . . . . . . . . . . . . . . . . 52

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 27 May 2010

Document identifier: UJA1078_2


型号：	UJA1078TW/5V0,512
厂家：	NXP
描述：	UJA1078 - Hihg-speed CAN/dual LIN core system basis chip TSSOP 32-Pin
文件：	总53页 (文件大小：349K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UJA1078TW/5V0,512 [NXP]

相关型号：

UJA1078TW/5V0/WD

UJA1079

UJA1079A

UJA1079ATW/3V3

UJA1079ATW/3V3/WD

UJA1079ATW/5V0

UJA1079ATW/5V0/WD

UJA1079TW/3V3

UJA1079TW/3V3/WD

UJA1079TW/5V0

UJA1079TW/5V0/WD

UJA1131HW/3V3