UJA1169TK [NXP]
Mini high-speed CAN system basis chip;
| 型号： | UJA1169TK |
| 厂家： | 
NXP |
| 描述： | Mini high-speed CAN system basis chip |
| 文件： | 总74页 (文件大小：623K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UJA1169
Mini high-speed CAN system basis chip
Rev. 1 — 4 February 2016
Product data sheet
1. General description
The UJA1169 is a mini high-speed CAN System Basis Chip (SBC) containing an
ISO 11898-2:201x (upcoming merged ISO 11898-2/5/6) compliant HS-CAN transceiver
and an integrated 5 V or 3.3 V 250 mA scalable supply (V1) for a microcontroller and/or
other loads. It also features a watchdog and a Serial Peripheral Interface (SPI). The
UJA1169 can be operated in very low-current Standby and Sleep modes with bus and
local wake-up capability.
The UJA1169 comes in six variants. The UJA1169TK, UJA1169TK/F, UJA1169TK/X and
UJA1169TK/X/F contain a 5 V regulator (V1). V1 is a 3.3 V regulator in the UJA1169TK/3
and the UJA1169TK/F/3.
The UJA1169TK, UJA1169TK/F, UJA1169TK/3 and UJA1169TK/F/3 variants feature a
second on-board 5 V regulator (V2) that supplies the internal CAN transceiver and can
also be used to supply additional on-board hardware.
The UJA1169TK/X and UJA1169TK/X/F are equipped with a 5 V supply (VEXT) for
off-board components. VEXT is short-circuit proof to the battery, ground and negative
voltages. The integrated CAN transceiver is supplied internally via V1, in parallel with the
microcontroller.
The UJA1169xx/F variants support ISO 11898-6:2013 and ISO 11898-2:201x compliant
CAN partial networking with a selective wake-up function incorporating CAN FD-passive.
CAN FD-passive is a feature that allows CAN FD bus traffic to be ignored in
Sleep/Standby mode. CAN FD-passive partial networking is the perfect fit for networks
that support both CAN FD and classic CAN communications. It allows normal CAN
controllers that do not need to communicate CAN FD messages to remain in partial
networking Sleep/Standby mode during CAN FD communication without generating bus
errors.
The UJA1169 implements the standard CAN physical layer as defined in the current
ISO11898 standard (-2:2003, -5:2007, -6:2013). Pending the release of the upcoming
version of ISO11898-2:201x including CAN FD, additional timing parameters defining loop
delay symmetry are included. This implementation enables reliable communication in the
CAN FD fast phase at data rates up to 2 Mbit/s.
A dedicated LIMP output pin is provided to flag system failures.
A number of configuration settings are stored in non-volatile memory. This arrangement
makes it possible to configure the power-on and limp-home behavior of the UJA1169 to
meet the requirements of different applications.
UJA1169
NXP Semiconductors
Mini high-speed CAN SBC with optional partial networking
2. Features and benefits
2.1 General
ISO 11898-2:201x (upcoming merged ISO 11898-2/5/6) compliant 1 Mbit/s high-speed
CAN transceiver supporting CAN FD active communication up to 2 Mbit/s in the CAN
FD data field (all six variants)
Autonomous bus biasing according to ISO 11898-6:2013 and ISO 11898-2:201x
Scalable 5 V or 3.3 V 250 mA low-drop voltage regulator for 5 V/3.3 V microcontroller
supply (V1) based on external PNP transistor concept for thermal scaling
CAN-bus connections are truly floating when power to pin BAT is off
No ‘false’ wake-ups due to CAN FD traffic (in variants supporting partial networking)
2.2 Designed for automotive applications
8 kV ElectroStatic Discharge (ESD) protection, according to the Human Body Model
(HBM) on the CAN-bus pins
6 kV ESD protection according to IEC 61000-4-2 on pins BAT, WAKE, VEXT and the
CAN-bus pins
CAN-bus pins short-circuit proof to 58 V
Battery and CAN-bus pins protected against automotive transients according to
ISO 7637-3
Very low quiescent current in Standby and Sleep modes with full wake-up capability
Leadless HVSON20 package (3.5 mm 5.5 mm) with improved Automated Optical
Inspection (AOI) capability and low thermal resistance
Dark green product (halogen free and Restriction of Hazardous Substances (RoHS)
compliant)
2.3 Low-drop voltage regulator for 5 V/3.3 V microcontroller supply (V1)
5 V/3.3 V nominal output; 2 % accuracy
250 mA output current capability
Thermal management via optional external PNP
Current limiting above 250 mA
Support for microcontroller RAM retention down to a battery voltage of 2 V (5 V only)
Undervoltage reset with selectable detection thresholds of 60 %, 70 %, 80 % or 90 %
of output voltage, configurable in non-volatile memory (5 V variants only)
Excellent transient response with a small ceramic output capacitor
Output is short-circuit proof to GND
Turned off in Sleep mode
2.4 On-board CAN supply (V2; UJA1169TK, UJA1169TK/F, UJA1169TK/3
and UJA1169TK/F/3 only)
5 V nominal output; 2 % accuracy
100 mA output current capability
Current limiting above 100 mA
Excellent transient response with a small ceramic output capacitor
UJA1169
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© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 4 February 2016
2 of 74
UJA1169
NXP Semiconductors
Mini high-speed CAN SBC with optional partial networking
Output is short-circuit proof to GND
User-defined on/off behavior via SPI
2.5 Off-board sensor supply (VEXT; UJA1169TK/X and UJA1169TK/X/F
only)
5 V nominal output; 2 % accuracy
100 mA output current capability
Current limiting above 100 mA
Excellent transient response with a small ceramic output load capacitor
Output is short-circuit proof to BAT, GND and negative voltages down to 18 V
User-defined on/off behavior via SPI
2.6 Power Management
Standby mode featuring very low supply current; voltage V1 remains active to maintain
the supply to the microcontroller
Sleep mode featuring very low supply current with voltage V1 switched off
Remote wake-up capability via standard CAN wake-up pattern or ISO 11898-6:2013
and ISO 11898-2:201x compliant selective wake-up frame detection including CAN FD
passive support (/F versions only)
Local wake-up via the WAKE pin
Wake-up source recognition
2.7 System control and diagnostic features
Mode control via the Serial Peripheral Interface (SPI)
Overtemperature warning and shutdown
Watchdog with Window, Timeout and Autonomous modes and microcontroller-
independent clock source
Optional cyclic wake-up in watchdog Timeout mode
Watchdog automatically re-enabled when wake-up event captured
Watchdog period selectable between 8 ms and 4 s supporting remote flash
programming via the CAN-bus
LIMP output pin with configurable activation threshold
Watchdog failure, RSTN clamping and overtemperature events trigger the dedicated
LIMP output signal
16-, 24- and 32-bit SPI for configuration, control and diagnosis
Bidirectional reset pin with variable power-on reset length; configurable in non-volatile
memory to support a number of different microcontrollers
Customer configuration of selected functions via non-volatile memory
Dedicated modes for software development and end-of-line flashing
UJA1169
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© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 4 February 2016
3 of 74
UJA1169
NXP Semiconductors
Mini high-speed CAN SBC with optional partial networking
3. Product family overview
Table 1.
Feature overview of UJA1169 SBC family
Modes
Supplies
Host
Additional Features
Interface
Device
UJA1169TK
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●
●
●
●
●
●
●
●
●
UJA1169TK/X
UJA1169TK/F
UJA1169TK/X/F
UJA1169TK/3
UJA1169TK/F/3
●
●
●
●
●
●
●
●
●
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4. Ordering information
Table 2.
Ordering information
Type number[1]
Package
Name
Description
Version
UJA1169TK
HVSON20
plastic thermal enhanced extremely thin quad flat package; no SOT1360-1
leads; 20 terminals; body 3.5 5.5 0.85 mm
UJA1169TK/X
UJA1169TK/F[2]
UJA1169TK/X/F[2]
UJA1169TK/3
UJA1169TK/F/3[2]
[1] UJA1169TK, UJA1169TK/F, UJA1169TK/3 and UJA1169TK/F/3 with dedicated CAN supply (V2); UJA1169TK/X and UJA1169TK/X/F
with protected off-board sensor supply (VEXT).
[2] UJA1169TK/F, UJA1169TK/F/3 and UJA1169TK/X/F with partial networking according to ISO 11898-6:2013 and ISO 11898-2:201x
incorporating CAN FD passive support.
UJA1169
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 4 February 2016
4 of 74
UJA1169
NXP Semiconductors
Mini high-speed CAN SBC with optional partial networking
5. Block diagram
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The internal CAN transceiver is supplied from V1 in the UJA1169TK/X and UJA1169TK/X/F and
from V2 in the other variants.
Fig 1. Block diagram of UJA1169
UJA1169
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© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 4 February 2016
5 of 74
UJA1169
NXP Semiconductors
Mini high-speed CAN SBC with optional partial networking
6. Pinning information
6.1 Pinning
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(1) V2 in the UJA1169TK, UJA1169TK/3, UJA1169TK/F and UJA1169TK/F/3; VEXT in the
UJA1169TK/X and UJA1169TK/X/F
Fig 2. Pin configuration diagram
6.2 Pin description
Table 3.
Symbol
Pin description
Pin Description
GND
TXD
SDI
1[1]
ground
2
transmit data input
SPI data input
3
GND
V1
4[1]
ground
5
5 V/3.3 V microcontroller supply voltage
VEXCC
6
current measurement for external PNP transistor; this pin is connected to
the collector of the external PNP transistor
RXD
RSTN
SDO
SCK
LIMP
WAKE
V2
7
receive data output; reflects data on bus lines and wake-up conditions
reset input/output; active-LOW
SPI data output
8
9
10
11
12
13
SPI clock input
limp home output, open-drain; active-LOW
local wake-up input
5 V CAN supply (UJA1169TK, UJA1169TK/3, UJA1169TK/F and
UJA1169TK/F/3 only)
VEXT
13
14
15
5 V sensor supply (UJA1169TK/X and UJA1169TK/X/F only)
battery supply voltage
BAT
VEXCTRL
control pin of the external PNP transistor; this pin is connected to the
base of the external PNP transistor
GND
16[1]
17
ground
CANL
LOW-level CAN-bus line
UJA1169
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© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 4 February 2016
6 of 74
UJA1169
NXP Semiconductors
Mini high-speed CAN SBC with optional partial networking
Table 3.
Pin description …continued
Symbol
CANH
GND
Pin
18
19[1]
Description
HIGH-level CAN-bus line
ground
SCSN
20
SPI chip select input; active-LOW
[1] The exposed die pad at the bottom of the package allows for better heat dissipation and grounding from the
SBC via the printed circuit board. For enhanced thermal and electrical performance, connect the exposed
die pad to GND.
7. Functional description
7.1 System controller
The system controller manages register configuration and controls the internal functions
of the UJA1169. Detailed device status information is collected and made available to the
microcontroller.
7.1.1 Operating modes
The system controller contains a state machine that supports seven operating modes:
Normal, Standby, Sleep, Reset, Forced Normal, Overtemp and Off. The state transitions
are illustrated in Figure 3.
7.1.1.1 Normal mode
Normal mode is the active operating mode. In this mode, all the hardware on the device is
available and can be activated (see Table 4). Voltage regulator V1 is enabled to supply the
microcontroller.
The CAN interface can be configured to be active and thus to support normal CAN
communication. Depending on the SPI register settings, the watchdog may be running in
Window or Timeout mode and the V2/VEXT output may be active.
7.1.1.2 Standby mode
Standby mode is the first-level power-saving mode of the UJA1169, offering reduced
current consumption. The transceiver is unable to transmit or receive data in Standby
mode. The SPI remains enabled and V1 is still active; the watchdog is active (in Timeout
mode) if enabled. The behavior of V2/VEXT is determined by the SPI setting.
If remote CAN wake-up is enabled (CWE = 1; see Table 32), the receiver monitors bus
activity for a wake-up request. The bus pins are biased to GND (via Ri(cm)) when the bus is
inactive for t > tto(silence) and at approximately 2.5 V when there is activity on the bus
(autonomous biasing). CAN wake-up can occur via a standard wake-up pattern or via a
selective wake-up frame (selective wake-up is enabled when CPNC = PNCOK = 1,
otherwise standard wake-up is enabled; see Table 15).
Pin RXD is forced LOW when any enabled wake-up event is detected. This event can be
either a regular wake-up (via the CAN-bus or pin WAKE) or a diagnostic wake-up such as
an overtemperature event (see Section 7.10).
UJA1169
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© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 4 February 2016
7 of 74
UJA1169
NXP Semiconductors
Mini high-speed CAN SBC with optional partial networking
1250$/
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Fig 3. UJA1169 system controller state diagram
7.1.1.3 Sleep mode
Sleep mode is the second-level power-saving mode of the UJA1169. The difference
between Sleep and Standby modes is that V1 is off in Sleep mode and temperature
protection is inactive.
UJA1169
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Product data sheet
Rev. 1 — 4 February 2016
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UJA1169
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Mini high-speed CAN SBC with optional partial networking
Any enabled regular wake-up via CAN or WAKE or any diagnostic wake-up event will
cause the UJA1169 to wake up from Sleep mode. The behavior of V2/VEXT is determined
by the SPI settings. The SPI and the watchdog are disabled. Autonomous bus biasing is
active.
Sleep mode can be permanently disabled in applications where, for safety reasons, the
supply voltage to the host controller must never be cut off. Sleep mode is permanently
disabled by setting the Sleep control bit (SLPC) in the SBC configuration register (see
Table 9) to 1. This register is located in the non-volatile memory area of the device (see
Section 7.11). When SLPC = 1, a Sleep mode SPI command (MC = 001) triggers an SPI
failure event instead of a transition to Sleep mode.
7.1.1.4 Reset mode
Reset mode is the reset execution state of the SBC. This mode ensures that pin RSTN is
pulled down for a defined time to allow the microcontroller to start up in a controlled
manner.
The transceiver is unable to transmit or receive data in Reset mode. The behavior of
V2/VEXT is determined by the settings of bits V2C/VEXTC and V2SUC/VEXTSUC (see
Section 7.5.3). The SPI is inactive; the watchdog is disabled; V1 and overtemperature
detection are active.
After the UJA1169 exits Reset mode (positive edge on RSTN), an SPI read/write access
must not be attempted for at least tto(SPI). Any earlier access may be ignored (without
generating an SPI failure event).
7.1.1.5 Off mode
The UJA1169 switches to Off mode when the battery is first connected or from any mode
when VBAT < Vth(det)poff. Only power-on detection is enabled; all other modules are
inactive. The UJA1169 starts to boot up when the battery voltage rises above the
power-on detection threshold Vth(det)pon (triggering an initialization process) and switches
to Reset mode after tstartup. In Off mode, the CAN pins disengage from the bus
(high-ohmic with respect to GND).
7.1.1.6 Overtemp mode
Overtemp mode is provided to prevent the UJA1169 being damaged by excessive
temperatures. The UJA1169 switches immediately to Overtemp mode from any mode
(other than Off mode or Sleep mode) when the global chip temperature rises above the
overtemperature protection activation threshold, Tth(act)otp
.
To help prevent the loss of data due to overheating, the UJA1169 issues a warning when
the IC temperature rises above the overtemperature warning threshold (Tth(warn)otp). When
this threshold is reached, status bit OTWS (see Table 6) is set and an overtemperature
warning event is captured (OTW = 1; see Table 26), if enabled (OTWE = 1; see Table 30).
In Overtemp mode, the CAN transmitter and receiver are disabled and the CAN pins are
in a high-ohmic state. No wake-up event will be detected, but a pending wake-up will still
be signaled by a LOW level on pin RXD, which will persist after the overtemperature event
has been cleared. V1 is off and pin RSTN is driven LOW. In the UJA1169TK/X and
UJA1169TK/X/F, VEXT is off. In the UJA1169TK, UJA1169TK/3, UJA1169TK/F and
UJA1169TK/F/3, V2 is turned off when the SBC enters Overtemp mode.
UJA1169
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© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 4 February 2016
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Mini high-speed CAN SBC with optional partial networking
7.1.1.7 Forced Normal mode
Forced Normal mode simplifies SBC testing and is useful for initial prototyping as well as
first flashing of the microcontroller. The watchdog is disabled in Forced Normal mode. The
low-drop voltage regulator (V1) is active, VEXT/V2 is enabled and the CAN transceiver is
active.
Bit FNMC is factory preset to 1, so the UJA1169 initially boots up in Forced Normal mode
(see Table 9). This feature allows a newly installed device to be run in Normal mode
without a watchdog. So the microcontroller can, optionally, be flashed via the CAN-bus
without having to consider the integrated watchdog.
The register containing bit FNMC (address 74h) is stored in non-volatile memory. So once
bit FNMC is programmed to 0, the SBC will no longer boot up in Forced Normal mode,
allowing the watchdog to be enabled.
Even in Forced Normal mode, a reset event (e.g. an external reset or a V1 undervoltage)
will trigger a transition to Reset mode with normal Reset mode behavior (except that the
CAN transmitter remains active if there is no VCAN undervoltage). When the UJA1169
exits Reset mode, however, it returns to Forced Normal mode instead of switching to
Standby mode.
In Forced Normal mode, only the Main status register, the Watchdog status register, the
Identification register and registers stored in non-volatile memory can be read. The
non-volatile memory area is fully accessible for writing as long as the UJA1169 is in the
factory preset state (for details see Section 7.11).
7.1.1.8 Hardware characterization for the UJA1169 operating modes
Table 4.
Block
Hardware characterization by functional block
Operating mode
Off
off[1]
Forced Normal Standby
Normal
Sleep
Reset
Overtemp
off
V1
on
on
on
off
on
[2]
[2]
[2]
[2]
VEXT/V2
RSTN
SPI
off
on
VEXT/V2 off
LOW
LOW
disabled active[3]
HIGH
HIGH
active
HIGH
active
LOW
LOW
disabled
disabled
disabled
off
Watchdog
off
off
determined by determined by bits
bits WMC (see WMC
Table 8)[4]
determined by off
bits WMC[4]
CAN
RXD
off
Active
Offline
Active/ Offline/
Listen-only
(determined by bits
CMC; see Table 15)
Offline
Offline
off
V1 level CAN bit stream V1 level/LOW CAN bit stream if
V1 level/LOW V1
V1
if wake-up
detected
CMC = 01/10/11;
otherwise same as
Standby/Sleep
if wake-up
detected
level/LOW level/LOW if
if wake-up wake-up
detected
detected
[1] When the SBC switches from Reset, Standby or Normal mode to Off mode in the 5 V variants, V1 behaves as a current source during
power down while VBAT is falling from Vth(det)pof down to 2 V (RAM retention feature; see Section 7.5.1).
[2] Determined by bits V2C/VEXTC and V2SUC/VEXTSUC (see Table 12)
[3] Limited register access: Main status register, Watchdog status register, Identification register and non-volatile memory only.
[4] Window mode is only active in Normal mode.
UJA1169
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© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 4 February 2016
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UJA1169
NXP Semiconductors
Mini high-speed CAN SBC with optional partial networking
7.1.2 System control registers
7.1.2.1 Mode control register (0x01)
The operating mode is selected via bits MC in the Mode control register. The Mode control
register is accessed via SPI address 0x01 (see Section 7.15).
Table 5.
Mode control register (address 01h)
Bit
7:3
2:0
Symbol Access Value Description
reserved
MC
R
-
R/W
mode control:
Sleep mode
001
100
111
Standby mode
Normal mode
7.1.2.2 Main status register (0x03)
The Main status register can be accessed to monitor the status of the overtemperature
warning flag and to determine whether the UJA1169 has entered Normal mode after initial
power-up. It also indicates the source of the most recent reset event.
Table 6.
Main status register (address 03h)
Bit
7
Symbol Access Value Description
reserved
OTWS
R
R
-
6
overtemperature warning status:
0
1
IC temperature below overtemperature warning threshold
IC temperature above overtemperature warning threshold
Normal mode status:
5
NMS
RSS
R
R
0
1
UJA1169 has entered Normal mode (after power-up)
UJA1169 has powered up but has not yet switched to
Normal mode
4:0
reset source status:
00000
00001
00100
01100
01101
01110
01111
left Off mode (power-on)
CAN wake-up in Sleep mode
wake-up via WAKE pin in Sleep mode
watchdog overflow in Sleep mode (Timeout mode)
diagnostic wake-up in Sleep mode
watchdog triggered too early (Window mode)
watchdog overflow (Window mode or Timeout mode with
WDF = 1)
10000
10001
10010
10011
10100
10110
illegal watchdog mode control access
RSTN pulled down externally
left Overtemp mode
V1 undervoltage
illegal Sleep mode command received
wake-up from Sleep mode due to a frame detect error
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7.2 Watchdog
7.2.1 Watchdog overview
The UJA1169 contains a watchdog that supports three operating modes: Window,
Timeout and Autonomous. In Window mode (available only in SBC Normal mode), a
watchdog trigger event within a defined watchdog window triggers and resets the
watchdog timer. In Timeout mode, the watchdog runs continuously and can be triggered
and reset at any time within the watchdog period by a watchdog trigger. Watchdog
time-out mode can also be used for cyclic wake-up of the microcontroller. In Autonomous
mode, the watchdog can be off or autonomously in Timeout mode, depending on the
selected SBC mode (see Section 7.2.5).
The watchdog mode is selected via bits WMC in the Watchdog control register (Table 8).
The SBC must be in Standby mode when the watchdog mode is changed. If Window
mode is selected (WMC = 100), the watchdog remains in (or switches to) Timeout mode
until the SBC enters Normal mode. Any attempt to change the watchdog operating mode
(via WMC) while the SBC is in Normal mode causes the UJA1169 to switch to Reset
mode and the reset source status bits (RSS) to be set to 10000 (‘illegal watchdog mode
control access’; see Table 6).
Eight watchdog periods are supported, from 8 ms to 4096 ms. The watchdog period is
programmed via bits NWP. The selected period is valid for both Window and Timeout
modes. The default watchdog period is 128 ms.
A watchdog trigger event resets the watchdog timer. A watchdog trigger event is any valid
write access to the Watchdog control register. If the watchdog mode or the watchdog
period have changed as a result of the write access, the new values are immediately
valid.
Table 7.
Watchdog configuration
Operating/watchdog mode
FNMC (Forced Normal mode control)
0
0
x
0
0
0
1
1
SDMC (Software Development mode control) x
x
WMC (watchdog mode control)
100 (Window) 010
(Timeout)
001
(Autonomous)
001
(Autonomous)
n.a.
Normal mode
Window
Timeout
Timeout
Timeout
off
Timeout
Timeout
Timeout
Timeout
off
Timeout
off
off
off
off
off
off
off
off
off
off
off
Standby mode (RXD HIGH)[1]
Standby mode (RXD LOW)[1]
Sleep mode
Timeout
off
Other modes
off
[1] RXD LOW signals a pending wake-up.
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7.2.1.1 Watchdog control register (0x00)
Table 8. Watchdog control register (address 00h)
Bit
Symbol
Access Value
Description
7:5
WMC
R/W
watchdog mode control:
Autonomous mode
Timeout mode
001[1]
010[2]
100[3]
Window mode
4
reserved
NWP
R
-
3:0
R/W
nominal watchdog period:
1000
0001
0010
1011
0100[2]
1101
1110
0111
8 ms
16 ms
32 ms
64 ms
128 ms
256 ms
1024 ms
4096 ms
[1] Default value if SDMC = 1 (see Section 7.2.2)
[2] Default value.
[3] Selected in Standby mode but only activated when the SBC switches to Normal mode.
The watchdog is a valuable safety mechanism, so it is critical that it is configured correctly.
Two features are provided to prevent watchdog parameters being changed by mistake:
• redundant coding of configuration bits WMC and NWP
• reconfiguration protection in Normal mode
Redundant codes associated with control bits WMC and NWP ensure that a single bit
error cannot cause the watchdog to be configured incorrectly (at least 2 bits must be
changed to reconfigure WMC or NWP). If an attempt is made to write an invalid code to
WMC or NWP (e.g. 011 or 1001 respectively), the SPI operation is abandoned and an SPI
failure event is captured, if enabled (see Section 7.10).
7.2.1.2 SBC configuration control register (0x74)
Two operating modes have a major impact on the operation of the watchdog: Forced
Normal mode and Software Development mode (Software Development mode is provided
for test and development purposes only and is not a dedicated SBC operating mode; the
UJA1169 can be in any functional operating mode with Software Development mode
enabled; see Section 7.2.2). These modes are enabled and disabled via bits FNMC and
SDMC respectively in the SBC configuration control register (see Table 9). Note that this
register is located in the non-volatile memory area. The watchdog is disabled in Forced
Normal mode (FNM). In Software Development mode (SDM), the watchdog can be
disabled or activated for test and software debugging purposes.
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Table 9.
SBC configuration control register (address 74h)
Bit Symbol
Access Value
Description
7:6 reserved
R
-
[1]
5:4 V1RTSUC R/W
V1 undervoltage threshold (defined by bit V1RTC) at
start-up:
00[2]
01
V1 undervoltage detection at 90 % of nominal value at
start-up (V1RTC = 00)
V1 undervoltage detection at 80 % of nominal value at
start-up (V1RTC = 01)
10
V1 undervoltage detection at 70 % of nominal value at
start-up (V1RTC = 10)
11
V1 undervoltage detection at 60 % of nominal value at
start-up (V1RTC = 11)
[3]
3
2
FNMC
SDMC
R/W
R/W
Forced Normal mode control:
0
1[2]
Forced Normal mode disabled
Forced Normal mode enabled
Software Development mode control:
Software Development mode disabled
Software Development mode enabled
0[2]
1
1
0
reserved
SLPC
R
-
R/W
Sleep control:
0[2]
1
Sleep mode commands accepted
Sleep mode commands ignored
[1] The V1 undervoltage threshold is fixed at 90 % in the UJA1169TK/3 and UJA1169TK/F/3, regardless of the
setting of bit V1RTSUC.
[2] Factory preset value.
[3] FNMC settings overrule SDMC.
7.2.1.3 Watchdog status register (0x05)
Information on the status of the watchdog is available from the Watchdog status register
(Table 10). This register also indicates whether Forced Normal and Software
Development modes are active.
Table 10. Watchdog status register (address 05h)
Bit
7:4
3
Symbol
reserved
FNMS
Access Value Description
R
-
R/W
Forced Normal mode status:
0
1
SBC is not in Forced Normal mode
SBC is in Forced Normal mode
2
SDMS
R/W
Software Development mode status:
SBC is not in Software Development mode
SBC is in Software Development mode
0
1
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Table 10. Watchdog status register (address 05h) …continued
Bit
Symbol
Access Value Description
1:0
WDS
R
watchdog status:
00
01
10
11
watchdog is off
watchdog is in first half of the nominal period
watchdog is in second half of the nominal period
reserved
7.2.2 Software Development mode
Software Development mode is provided to simplify the software design process. When
Software Development mode is enabled, the watchdog starts up in Autonomous mode
(WMC = 001) and is inactive after a system reset, overriding the default value (see
Table 8). The watchdog is always off in Autonomous mode if Software Development mode
is enabled (SDMC = 1; see Table 7).
However, it is possible to activate and deactivate the watchdog for test purposes by
selecting Window or Timeout mode via bits WMC while the SBC is in Standby mode.
7.2.3 Watchdog behavior in Window mode
In Window mode, the watchdog can only be triggered during the second half of the
watchdog period. If the watchdog overflows, or is triggered in the first half of the watchdog
period (before ttrig(wd)1), a system reset is performed. After the system reset, the reset
source (either ‘watchdog triggered too early’ or ‘watchdog overflow’) can be read via the
reset source status bits (RSS) in the Main Status register (Table 6). If the watchdog is
triggered in the second half of the watchdog period (after ttrig(wd)1 but before ttrig(wd)2), the
watchdog timer is restarted.
7.2.4 Watchdog behavior in Timeout mode
In Timeout mode, the watchdog timer can be reset at any time by a watchdog trigger. If the
watchdog overflows, a watchdog failure event (WDF) is captured. If a WDF is already
pending when the watchdog overflows, a system reset is performed. In Timeout mode, the
watchdog can be used as a cyclic wake-up source for the microcontroller when the
UJA1169 is in Standby or Sleep mode. In Sleep mode, a watchdog overflow generates a
wake-up event while setting WDF.
When the SBC is in Sleep mode with watchdog Timeout mode selected, a wake-up event
is generated after the nominal watchdog period (NWP), setting WDF. RXD is forced LOW
and V1 is turned on. The application software can then clear the WDF bit and trigger the
watchdog before it overflows again.
7.2.5 Watchdog behavior in Autonomous mode
In Autonomous mode, the watchdog will not be running when the SBC is in Standby (RXD
HIGH) or Sleep mode. If a wake-up event is captured, pin RXD is forced LOW to signal
the event and the watchdog is automatically restarted in Timeout mode. If the SBC was in
Sleep mode when the wake-up event was captured, it switches to Standby mode.
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7.2.6 Exceptional behavior of the watchdog after writing to the Watchdog register
A successful write operation to the Watchdog control register resets the watchdog timer.
Bits WDS are set to 01 and the watchdog restarts at the beginning of the watchdog period
(regardless of the selected watchdog mode). However, the watchdog may restart
unexpectedly in the second half of the watchdog period or a WDF interrupt may be
captured under the following conditions.
Case A: When the watchdog is running in Timeout mode (see Table 7) and a new
watchdog period is selected (via bits NWP) that is shorter than the existing watchdog
period, one of both of the following events may occur.
Status bits WDS can be set to 10. The timer then restarts at the beginning of the second
half of the watchdog period, causing the watchdog to overflow earlier than expected.
This can be avoided by writing the new NWP (or NWP + WMC) code twice whenever
the watchdog period needs to be changed. The write commands should be sent
consecutively. The gap between the commands must be less than half of the new
watchdog period.
If the watchdog is in the second half of the watchdog period when the watchdog period
is changed, the timer will be reset correctly. The watchdog then restarts at the beginning
of the watchdog period and WDS is set 01. However, a WDF event may be captured
unexpectedly. To counteract this effect, the WDF event should be cleared by default
after the new watchdog period has been selected as described above (two consecutive
write commands).
Case B: If the watchdog is triggered in Timeout mode (see Table 7) at exactly the same
time that WDS is set to 10, it will start up again in the second half of the watchdog period.
As in Case A, this causes the watchdog to overflow earlier than expected. This behavior
appears identical to an ignored watchdog trigger event and can be avoided by issuing two
consecutive watchdog commands. The second command should be issued before the
end of the first half of the watchdog period. Use this trigger scheme if it is possible that the
watchdog could be triggered exactly in the middle of the watchdog window.
7.3 System reset
When a system reset occurs, the SBC switches to Reset mode and initiates process that
generates a low-level pulse on pin RSTN. The UJA1169 can distinguish up to 13 different
reset sources, as detailed in Table 6.
7.3.1 Characteristics of pin RSTN
Pin RSTN is a bidirectional open-drain low side driver with integrated pull-up resistance,
as shown in Figure 4. With this configuration, the SBC can detect the pin being pulled
down externally, e.g. by the microcontroller. The input reset pulse width must be at least
tw(rst) to guarantee that external reset events are detected correctly.
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9ꢆ
5671
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Fig 4. RSTN internal pin configuration
7.3.2 Selecting the output reset pulse width
The duration of the output reset pulse is selected via bits RLC in the Start-up control
register (Table 11). The SBC distinguishes between a cold start and a warm start. A cold
start is performed if the reset event was combined with a V1 undervoltage event
(power-on reset, reset during Sleep mode, over-temperature reset, V1 undervoltage
before entering or while in Reset mode). The setting of bits RLC determines the output
reset pulse width for a cold start.
A warm start is performed if any other reset event occurs without a V1 undervoltage
(external reset, watchdog failure, watchdog change attempt in Normal mode, illegal Sleep
mode command). The SBC uses the shortest reset length (tw(rst) as defined when
RLC = 11).
7.3.2.1 Start-up control register (0x73)
Table 11. Start-up control register (address 73h)
Bit Symbol
7:6 reserved
5:4 RLC
Access
R
Value
Description
-
R/W
RSTN output reset pulse width:
tw(rst) = 20 ms to 25 ms
00[1]
01
tw(rst) = 10 ms to 12.5 ms
10
tw(rst) = 3.6 ms to 5 ms
11
tw(rst) = 1 ms to 1.5 ms
3
V2SUC[2]
R/W
R
V2/VEXT start-up control:
VEXTSUC[3]
0[1]
1
bits V2C/VEXTC set to 00 at power-up
bits V2C/VEXTC set to 11 at power-up
2:0 reserved
-
[1] Factory preset value.
[2] UJA1169TK, UJA1169TK/3, UJA1169TK/F and UJA1169TK/F/3 only.
[3] UJA1169TK/X and UJA1169TK/X/F only.
7.4 Global temperature protection
The temperature of the UJA1169 is monitored continuously, except in Sleep and Off
modes. The SBC switches to Overtemp mode if the temperature exceeds the
overtemperature protection activation threshold, Tth(act)otp. In addition, pin RSTN is driven
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LOW and V1, V2/VEXT and the CAN transceiver are switched off (if the optional external
PNP transistor is connected, it will also be; see Section 7.5.2). When the temperature
drops below the overtemperature protection release threshold, Tth(rel)otp, the SBC
switches to Standby mode via Reset mode.
In addition, the UJA1169 provides an overtemperature warning. When the IC temperature
rises about the overtemperature warning threshold (Tth(warn)otp), status bit OTWS is set
and an overtemperature warning event is captured (OTW = 1).
7.5 Power supplies
7.5.1 Battery supply voltage (VBAT
)
The internal circuitry is supplied from the battery via pin BAT. The device must be
protected against negative supply voltages, e.g. by using an external series diode. If VBAT
falls below the power-off detection threshold, Vth(det)poff, the SBC switches to Off mode.
However, in the 5 V variants, the microcontroller supply voltage (V1) remains active until
V
BAT falls below 2 V, ensuring memory in the connected microcontroller remains active for
as long as possible (RAM retention feature; not available in the 3.3 V variants).
The SBC switches from Off mode to Reset mode tstartup after the battery voltage rises
above the power-on detection threshold, Vth(det)pon. Power-on event status bit PO is set to
1 to indicate the UJA1169 has powered up and left Off mode (see Table 26).
7.5.2 Voltage regulator V1
The UJA1169 provides a 5 V or 3.3 V supply (V1), depending on the variant. V1 can
deliver up to 250 mA load current. In the UJA1169TK/X and UJA1169TK/X/F variants, the
CAN transceiver is supplied internally via V1, reducing the output current available for
external components.
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Fig 5. Typical application without external PNP (showing example component values)
To prevent the device overheating at high ambient temperatures or high average currents,
an external PNP transistor can be connected as illustrated in Figure 6. In this
configuration, the power dissipation is distributed between the SBC (IV1) and the PNP
transistor (IPNP).
The PNP transistor is activated when the load current reaches the PNP activation
threshold, Ith(act)PNP. Bit PDC in the Regulator control register (Table 12) is used to
regulate how power dissipation is distributed.
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FORVHꢁWRꢁ313
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Fig 6. Typical application with external PNP (showing example component values)
For short-circuit protection, a resistor must be connected between pins V1 and VEXCC to
allow the current to be monitored. This resistor limits the current delivered by the external
transistor. If the voltage difference between pins VEXCC and V1 reaches Vth(act)Ilim, the
PNP current limiting activation threshold voltage, the transistor current will not increase
further. In general, any PNP transistor with a current amplification factor () of between 50
and 500 can be used.
The output voltage on V1 is monitored. A system reset is generated if the voltage on V1
drops below the selected undervoltage threshold (60 %, 70 %, 80 % or 90 % of the
nominal V1 output voltage for the 5 V variants, selected via V1RTC in the Regulator
control register; fixed at 90 % for the 3.3 V variants; see Table 12).
The default value of the undervoltage threshold at power-up is determined by the value of
bits V1RTSUC in the SBC configuration control register (Table 9). The SBC configuration
control register is in non-volatile memory, allowing the user to define the default
undervoltage threshold (V1RTC) at any battery start-up.
In addition, an undervoltage warning (a V1U event; see Section 7.10) is generated if the
voltage on V1 falls below 90 % of the nominal value (and V1U event detection is enabled,
V1UE = 1; see Table 31). This information can be used as a warning, when the 60 %,
70 % or 80 % threshold is selected in the 5 V variants, to indicate that the level on V1 is
outside the nominal supply range. The status of V1, whether it is above or below the 90 %
undervoltage threshold, can be polled via bit V1S in the Supply voltage status register
(Table 13).
7.5.3 Voltage regulator V2
In the UJA1169TK, UJA1169TK/3, UJA1169TK/F and UJA1169TK/F/3, pin 13 is a voltage
regulator output (V2) delivering up to 100 mA.
The CAN transceiver is supplied internally from V2, consuming a portion of the available
current. V2 is not protected against shorts to the battery or to negative voltages and
should not be used to supply off-board components.
V2 is software controlled and must be turned on (via bit V2C in the Regulator control
register; see Table 12) to activate the supply voltage for the internal CAN transceiver. V2
is not required for wake-up detection via the CAN interface.
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The default value of V2C at power-on is defined by bits V2SUC in non-volatile memory
(see Section 7.11). The actual status of V2 can be polled from the Supply voltage status
register (Table 13).
7.5.4 Voltage regulator VEXT
In the UJA1169TK/X and UJA1169TK/X/F, pin 13 is a voltage regulator output (VEXT) that
can be used to supply off-board components, delivering up to 100 mA. VEXT is protected
against short-circuits to the battery and negative voltages. Since the CAN controller is
supplied internally via V1, the full 100 mA supply current is available for off-board loads
connected to VEXT (provided the thermal limits of the PCB are not exceeded).
VEXT is software controlled and must be turned on (via bit VEXTC in the Regulator
control register; see Table 12) to activate the supply voltage for off-board components.
The default value of VEXTC at power-on is defined by bits VEXTSUC in non-volatile
memory (see Section 7.11). The status of VEXT can be read from the Supply voltage
status register (Table 13).
7.5.5 Regulator control register (0x10)
Table 12. Regulator control register (address 10h)
Bit
7
Symbol
reserved
PDC
Access
R
Value Description
-
6
R/W
power distribution control:
V1 threshold current for activating the external PNP transistor, load current
rising; Ith(act)PNP (higher value; see Table 52)
V1 threshold current for deactivating the external PNP transistor, load
current falling; Ith(deact)PNP (higher value; see Table 52)
0
1
-
V1 threshold current for activating the external PNP transistor; load current
rising; Ith(act)PNP (lower value; see Table 52)
V1 threshold current for deactivating the external PNP transistor; load
current falling; Ith(deact)PNP (lower value; see Table 52)
5:4
3:2
reserved
R
reserved bits can be read and overwritten without affecting device functionality;
default value at power-up is 00 (other reserved bits always return 0)
V2C[1]
VEXTC[2]
R/W
V2/VEXT configuration:
00
01
10
11
V2/VEXT off in all modes
V2/VEXT on in Normal mode
V2/VEXT on in Normal, Standby and Reset modes
V2/VEXT on in Normal, Standby, Sleep and Reset modes
set V1 reset threshold:
1:0
V1RTC[3]
R/W
00
01
10
11
reset threshold set to 90 % of V1 nominal output voltage
reset threshold set to 80 % of V1 nominal output voltage
reset threshold set to 70 % of V1 nominal output voltage
reset threshold set to 60 % of V1 nominal output voltage
[1] UJA1169TK, UJA1169TK/3, UJA1169TK/F and UJA1169TK/F/3: default value at power-up defined by V2SUC bit setting (see Table 11).
[2] UJA1169TK/X and UJA1169TK/X/F: default value at power-up defined by VEXTSUC bit setting (see Table 11).
[3] 5 V variants only; default value at power-up defined by setting of bits V1RTSUC (see Table 9). The threshold is fixed at 90 % in the 3.3 V
variants and V1RTC always reads 00 (regardless of the value written to V1RTC or the start-up threshold defined by V1RTSUC).
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7.5.6 Supply voltage status register (0x1B)
Table 13. Supply voltage status register (address 1Bh)
Bit
7:3
2:1
Symbol
Access
R
Value Description
reserved
V2S[1]
VEXTS[2]
-
R/W
V2/VEXT status:
00[3]
01
V2/VEXT voltage ok
V2/VEXT output voltage below undervoltage threshold
V2/VEXT output voltage above overvoltage threshold
V2/VEXT disabled
10
11
0
V1S
R/W
V1 status:
0[3]
1
V1 output voltage above 90 % undervoltage threshold
V1 output voltage below 90 % undervoltage threshold
[1] UJA1169TK, UJA1169TK/3, UJA1169TK/F and UJA1169TK/F/3 only.
[2] UJA1169TK/X and UJA1169TK/X/F only.
[3] Default value at power-up.
7.6 LIMP output
The dedicated LIMP pin can be used to enable so called ‘limp home’ hardware in the
event of a serious ECU failure. Detectable failure conditions include SBC overtemperature
events, loss of watchdog service, short-circuits on pins RSTN or V1 and user-initiated or
external reset events (see Figure 7). The LIMP pin is a battery-robust, active-LOW,
open-drain output. The LIMP pin can also be forced LOW by setting bit LHC in the
Fail-safe control register (Table 14).
7.6.1 Reset counter
The UJA1169 uses a reset counter to detect serious failures. The reset counter is
incremented (bits RCC = RCC + 1; see Table 14) every time the SBC enters Reset mode.
When the system is running correctly, it is expected that the system software will reset this
counter (RCC = 00) periodically to ensure that routinely expected reset events do not
cause it to overflow.
If RCC is equal to 3 when the SBC enters Reset mode, the SBC assumes that a serious
failure has occurred and sets the limp-home control bit, LHC. This action forces the
external LIMP pin LOW with RCC overflowing to RCC = 0. Bit LHC can also be set via the
SPI interface.
The LIMP pin is set floating again if LHC is reset to 0 through software control or at
power-up when the SBC leaves Off mode.
The application software can preset the counter value to define how many reset events
are tolerated before the limp-home function is activated. If RCC is initialized to 3, for
example, the next reset event will immediately trigger the limp-home function. The default
counter setting at power-up is RCC = 00.
Besides a reset counter (RCC) overflow, the following events cause bit LHC to be set and
immediately trigger the limp-home function:
• overtemperature lasting longer than td(limp)
UJA1169
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• SBC remaining in Reset mode for longer than td(limp) (e.g. because of a clamped
RSTN pin or a permanent V1 undervoltage).
7.6.2 LIMP state diagram
2.
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SBC modes are derived from the SBC state diagram (see Figure 3). The reset counter overflows
from 3 to 0; t is the time the SBC remains continuously in Reset or Overtemp mode; time t is reset
at mode entry; time t is not reset on a transition between Reset and Overtemp modes
Fig 7. Limp function state diagram
Note that the SBC always switches to Reset mode after leaving Sleep mode, since the
SBC powers up V1 in response to a wake-up event. So RCC is incremented after each
Sleep mode cycle. The application software needs to monitor RCC and update the value
as necessary to ensure that multiple Sleep mode cycles do not cause the reset counter to
overflow.
The limp-home function and the reset counter are disabled in Forced Normal mode. The
LIMP pin is floating, RCC remains unchanged and bit LHC = 0.
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7.6.2.1 Fail-safe control register (0x02)
The Fail-safe control register contains the reset counter along with limp home control
settings.
Table 14. Fail-safe control register (address 02h)
Bit
7:3
2
Symbol
reserved
LHC
Access Value Description
R/W
R/W
LIMP home control:
0
1
LIMP pin is floating
LIMP pin is driven LOW
reset counter control:
1:0
RCC
xx
incremented every time the SBC enters Reset mode
while FNMC = 0; RCC overflows from 11 to 00; default at
power-on is 00
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Fig 8. LIMP pin functional diagram
7.7 High-speed CAN transceiver
The integrated high-speed CAN transceiver is designed for active communication at bit
rates up to 1 Mbit/s, providing differential transmit and receive capability to a CAN protocol
controller. The transceiver is ISO 11898-2:201x (upcoming merged ISO 11898-2/5/6
standard) compliant. Depending on the derivative, the CAN transmitter is supplied
internally from V1 (in /X variants) or V2 (in variants with a V2 regulator). Additional timing
parameters defining loop delay symmetry are included to ensure reliable communication
in fast phase at data rates up to 2 Mbit/s, as used in CAN FD networks.
The CAN transceiver supports autonomous CAN biasing as defined in ISO 11898-6:2013
and ISO 11898-2:201x. CANH and CANL are always biased to 2.5 V when the transceiver
is in Active or Listen-only modes (CMC = 01/10/11; see Table 15).
Autonomous biasing is active in CAN Offline mode, to 2.5 V if there is activity on the bus
(CAN Offline Bias mode) and to GND if there is no activity on the bus for t > tto(silence)
(CAN Offline mode). The autonomous CAN bias voltage is derived directly from VBAT
.
7.7.1 CAN operating modes
The integrated CAN transceiver supports four operating modes: Active, Listen-only,
Offline and Offline Bias (see Figure 9). The CAN transceiver operating mode depends on
the UJA1169 operating mode and on the setting of bits CMC in the CAN control register
(Table 15).
UJA1169
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When the UJA1169 is in Normal mode, the CAN transceiver operating mode (Active,
Listen-only or Offline) can be selected via bits CMC in the CAN control register (Table 15).
When the UJA1169 is in Standby or Sleep modes, the transceiver is forced to Offline or
Offline Bias mode (depending on bus activity).
7.7.1.1 CAN Active mode
In CAN Active mode, the transceiver can transmit and receive data via CANH and CANL.
The differential receiver converts the analog data on the bus lines into digital data, which
is output on pin RXD. The transmitter converts digital data generated by the CAN
controller (input on pin TXD) into analog signals suitable for transmission over the CANH
and CANL bus lines.
CAN Active mode is selected when CMC = 01 or 10.
When CMC = 01, VCAN undervoltage detection is enabled and the transceiver goes to
CAN Offline or CAN Offline Bias mode when the voltage at the CAN block drops below the
90 % threshold. V1 is monitored for the 90 % threshold in the /X versions; in the V2
versions, the 90 % threshold is related to the V2 supply voltage.
When CMC = 10, VCAN undervoltage detection is disabled. The transmitter remains active
even if the CAN supply falls below the 90 % threshold while V1 is still above the V1 reset
threshold (selected via bits V1RTC).
If pin TXD is held LOW (e.g. by a short-circuit to GND) when CAN Active mode is selected
via bits CMC, the transceiver does not enter CAN Active mode but switches to or remains
in CAN Listen-only mode. In order to prevent a hardware and/or software application
failure from driving the bus lines to an unwanted dominant state, it remains in Listen-only
mode until pin TXD goes HIGH.
In CAN Active mode, the CAN bias voltage is the CAN supply voltage divided by two
(depending on the derivative, the bias voltage is either V1 divided by two or V2 divided by
two).
The application can determine whether the CAN transceiver is ready to transmit/receive
data (CAN supply above 90 % threshold) or is disabled by reading the CAN Transceiver
Status (CTS) bit in the Transceiver Status Register (Table 16).
7.7.1.2 CAN Listen-only mode
CAN Listen-only mode allows the UJA1169 to monitor bus activity while the transceiver is
inactive, without influencing bus levels. The CAN transmitter is disabled in Listen-only
mode, reducing current consumption. The CAN receiver and CAN biasing remain active.
7.7.1.3 CAN Offline and Offline Bias modes
In CAN Offline mode, the transceiver monitors the CAN-bus for a wake-up event, provided
CAN wake-up detection is enabled (CWE = 1; see Table 32). CANH and CANL are biased
to GND.
CAN Offline Bias mode is the same as CAN Offline mode, with the exception that the
CAN-bus is biased to 2.5 V. This mode is activated automatically when activity is detected
on the CAN-bus while the transceiver is in CAN Offline mode. If the CAN-bus is silent (no
CAN-bus edges) for longer than tto(silence), the transceiver returns to CAN Offline mode.
UJA1169
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7.7.1.4 CAN Off mode
In CAN Off mode, bus pins CANH and CANL are set floating with respect to GND, which
prevents reverse currents flowing from the bus to an unsupplied ECU. The differential
input resistance between CANH and CANL remains constant.
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(1) To prevent the bus lines being driven to a permanent dominant state, the transceiver will not switch to CAN Active mode or CAN
Listen-only mode if pin TXD is held LOW (e.g. by a short-circuit to GND)
Fig 9. CAN transceiver state machine (with FNMC = 0)
7.7.2 CAN standard wake-up (partial networking not enabled)
If the CAN transceiver is in Offline mode and CAN wake-up is enabled (CWE = 1), but
CAN selective wake-up is disabled (CPNC = 0 or PNCOK = 0), the UJA1169 monitors the
bus for a wake-up pattern.
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A filter at the receiver input prevents unwanted wake-up events occurring due to
automotive transients or EMI. A dominant-recessive-dominant wake-up pattern must be
transmitted on the CAN-bus within the wake-up time-out time (tto(wake)) to pass the
wake-up filter and trigger a wake-up event (see Figure 10; note that additional pulses may
occur between the recessive/dominant phases). The recessive and dominant phases
must last at least twake(busrec) and twake(busdom), respectively.
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Fig 10. CAN wake-up timing
When a valid CAN wake-up pattern is detected on the bus, wake-up bit CW in the
Transceiver event status register is set (see Table 28) and pin RXD is driven LOW. If the
SBC was in Sleep mode when the wake-up pattern was detected, V1 is enabled to supply
the microcontroller and the SBC switches to Standby mode via Reset mode.
7.7.2.1 CAN control register (0x20)
Table 15. CAN control register (address 20h)
Bit
7
Symbol Access Value
Description
reserved R/W
CFDC[1] R/W
-
6
CAN FD control:
0
1
CAN FD tolerance disabled
CAN FD tolerance enabled
CAN partial networking configuration OK:
5
PNCOK[1] R/W
CPNC[1] R/W
0
1
partial networking register configuration invalid (wake-up
via standard wake-up pattern only)
partial networking registers configured successfully
CAN partial networking control:
4
0
1
-
disable CAN selective wake-up
enable CAN selective wake-up
3:2
reserved
R
UJA1169
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Table 15. CAN control register (address 20h) …continued
Bit
Symbol Access Value
CMC R/W
Description
1:0
CAN mode control:
Offline mode
00
01
Active mode (when the SBC is in Normal mode); CAN
supply undervoltage detection active
10
11
Active mode (when the SBC is in Normal mode); CAN
supply undervoltage detection disabled
Listen-only mode
[1] UJA1169TK/F and UJA1169TK/X/F only; otherwise reserved.
7.7.2.2 Transceiver status register (0x22)
Table 16. Transceiver status register (address 22h)
Bit
Symbol
Access Value
Description
7
CTS
R
CAN transceiver status:
0
CAN transceiver not in Active mode
CAN transceiver in Active mode
CAN partial networking error:
1
6
CPNERR[1]
R
0
no CAN partial networking error detected (PNFDE = 0
AND PNCOK = 1)
1
CAN partial networking error detected (PNFDE = 1
OR PNCOK = 0; wake-up via standard wake-up
pattern only)
5
4
CPNS[1]
R
CAN partial networking status:
0
CAN partial networking configuration error detected
(PNCOK = 0)
1
CAN partial networking configuration ok (PNCOK = 1)
CAN oscillator status:
COSCS[1]
R
0
CAN partial networking oscillator not running at target
frequency
1
CAN partial networking oscillator running at target
frequency
3
CBSS
R
0
1
CAN-bus silence status:
CAN-bus active (communication detected on bus)
CAN-bus inactive (for longer than tto(silence)
)
2
1
reserved
VCS[2]
R
R
-
VCAN status:
0
1
CAN supply voltage is above the 90 % threshold
CAN supply voltage is below the 90 % threshold
CAN failure status:
0
CFS
R
0
1
no TXD dominant time-out event detected
CAN transmitter disabled due to a TXD dominant
time-out event
[1] UJA1169TK/F and UJA1169TK/X/F only; otherwise reserved reading 0.
[2] Only active when CMC = 01.
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7.8 CAN partial networking (UJA1169 /F variants only)
Partial networking allows nodes in a CAN network to be selectively activated in response
to dedicated wake-up frames (WUF). Only nodes that are functionally required are active
on the bus while the other nodes remain in a low-power mode until needed.
If both CAN wake-up (CWE = 1) and CAN selective wake-up (CPNC = 1) are enabled,
and the partial networking registers are configured correctly (PNCOK = 1), the transceiver
monitors the bus for dedicated CAN wake-up frames.
7.8.1 Wake-up frame (WUF)
A wake-up frame is a CAN frame according to ISO11898-1:2003, consisting of an
identifier field (ID), a Data Length Code (DLC), a data field and a Cyclic Redundancy
Check (CRC) code including the CRC delimiter.
The wake-up frame format, standard (11-bit) or extended (29-bit) identifier, is selected via
bit IDE in the Frame control register (Table 20).
A valid WUF identifier is defined and stored in the ID registers (Table 18). An ID mask can
be defined to allow a group of identifiers to be recognized as valid by an individual node.
The identifier mask is defined in the ID mask registers (Table 19), where a 1 means ‘don’t
care’.
In the example illustrated in Figure 11, based on the standard frame format, the 11-bit
identifier is defined as 0x1A0. The identifier is stored in ID registers 2 (0x29) and 3 (0x2A).
The three least significant bits of the ID mask, bits 2 to 4 of Mask register 2 (0x2D), are
‘don’t care’. This means that any of eight different identifiers will be recognized as valid in
the received WUF (from 0x1A0 to 0x1A7).
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Fig 11. Evaluating the ID field in a selective wake-up frame
The data field indicates the nodes to be woken up. Within the data field, groups of nodes
can be predefined and associated with bits in a data mask. By comparing the incoming
data field with the data mask, multiple groups of nodes can be woken up simultaneously
with a single wake-up message.
The data length code (bits DLC in the Frame control register; Table 20) determines the
number of data bytes (between 0 and 8) expected in the data field of a CAN wake-up
frame. If one or more data bytes are expected (DLC 0000), at least one bit in the data
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field of the received wake-up frame must be set to 1 and at least one equivalent bit in the
associated data mask register in the transceiver (see Table 21) must also be set to 1 for a
successful wake-up. Each matching pair of 1s indicates a group of nodes to be activated
(since the data field is up to 8 bytes long, up to 64 groups of nodes can be defined). If
DLC = 0, a data field is not expected.
In the example illustrated in Figure 12, the data field consists of a single byte (DLC = 1).
This means that the data field in the incoming wake-up frame is evaluated against data
mask 7 (stored at address 6Fh; see Table 21 and Figure 13). Data mask 7 is defined as
10101000 in the example, indicating that the node is assigned to three groups (Group1,
Group 3 and Group 5).
The received message shown in Figure 12 could, potentially, wake up four groups of
nodes: groups 2, 3, 4 and 5. Two matches are found (groups 3 and 5) when the message
data bits are compared with the configured data mask (DM7).
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Fig 12. Evaluating the Data field in a selective wake-up frame
Optionally, the data length code and the data field can be excluded from the evaluation of
the wake-up frame. If bit PNDM = 0, only the identifier field is evaluated to determine if the
frame contains a valid wake-up message. If PNDM = 1 (the default value), the data field is
included for wake-up filtering.
When PNDM = 0, a valid wake-up message is detected and a wake-up event is captured
(and CW is set to 1) when:
• the identifier field in the received wake-up frame matches the pattern in the ID
registers after filtering AND
• the CRC field in the received frame (including a recessive CRC delimiter) was
received without error
When PNDM = 1, a valid wake-up message is detected when:
• the identifier field in the received wake-up frame matches the pattern in the ID
registers after filtering AND
• the frame is not a Remote frame AND
• the data length code in the received message matches the configured data length
code (bits DLC) AND
• if the data length code is greater than 0, at least one bit in the data field of the
received frame is set and the corresponding bit in the associated data mask register is
also set AND
• the CRC field in the received frame (including a recessive CRC delimiter) was
received without error
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If the UJA1169 receives a CAN message containing errors (e.g. a ‘stuffing’ error) that are
transmitted in advance of the ACK field, an internal error counter is incremented. If a CAN
message is received without any errors appearing in front of the ACK field, the counter is
decremented. Data received after the CRC delimiter and before the next Start of Frame
(SOF) is ignored by the partial networking module. If the counter overflows (counter > 31),
a frame detect error is captured (PNFDE = 1) and the device wakes up; the counter is
reset to zero when the bias is switched off and partial networking is re-enabled.
Partial networking is assumed to be configured correctly when PNCOK is set to 1 by the
application software. The UJA1169 clears PNCOK after a write access to any of the CAN
partial networking configuration registers (see Section 7.8.3).
If selective wake-up is disabled (CPNC = 0) or partial networking is not configured
correctly (PNCOK = 0), and the CAN transceiver is in Offline mode with wake-up enabled
(CWE = 1), then any valid wake-up pattern according to ISO 11898-2:201x (upcoming
merged ISO 11898-2/5/6 standard) will trigger a wake-up event.
If the CAN transceiver is not in Offline mode (CMC 00) or CAN wake-up is disabled
(CWE = 0), all wake-up patterns on the bus are ignored.
7.8.2 CAN FD frames
CAN FD stands for ‘CAN with Flexible Data-Rate’. It is based on the CAN protocol as
specified in the upcoming ISO 11898-1:201x standard.
CAN FD is being gradually introduced into automotive market. In time, all CAN controllers
will be required to comply with the new standard (enabling ‘FD-active’ nodes) or at least to
tolerate CAN FD communication (enabling ‘FD-passive’ nodes). The UJA1169TK/F,
UJA1169TK/F/3 and UJA1169TK/X/F support FD-passive features by means of a
dedicated implementation of the partial networking protocol.
The /F variants can be configured to recognize CAN FD frames as valid CAN frames.
When CFDC = 1, the error counter is decremented every time the control field of a CAN
FD frame is received. The UJA1169xx/F remains in low-power mode (CAN FD-passive)
with partial networking enabled. CAN FD frames are never recognized as valid wake-up
frames, even if PNDM = 0 and the frame contains a valid ID. After receiving the control
field of a CAN FD frame, the UJA1169xx/F ignores further bus signals until idle is again
detected.
CAN FD frames are interpreted as frames with errors by the partial networking module
when CFDC = 0. So the error counter is incremented when a CAN FD frame is received. If
the ratio of CAN FD frames to valid CAN frames exceeds the threshold that triggers error
counter overflow, bit PNFDE is set to 1 and the device wakes up.
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7.8.3 CAN partial networking configuration registers
Dedicated registers are provided for configuring CAN partial networking.
7.8.3.1 Data rate register (0x26)
Table 17. Data rate register (address 26h)
Bit
7:3
2:0
Symbol
reserved
CDR
Access
R
Value
Description
-
R/W
CAN data rate selection:
50 kbit/s
000
001
010
011
100
100 kbit/s
125 kbit/s
250 kbit/s
reserved (intended for future use; currently
selects 500 kbit/s)
101
110
500 kbit/s
reserved (intended for future use; currently
selects 500 kbit/s)
111
1000 kbit/s
7.8.3.2 ID registers (0x27 to 0x2A)
Table 18. ID registers 0 to 3 (addresses 27h to 2Ah)
Addr. Bit Symbol Access Value Description
27h
28h
29h
7:0 ID07:ID00
7:0 ID15:ID08
7:2 ID23:ID18
R/W
R/W
R/W
-
-
-
bits ID07 to ID00 of the extended frame format
bits ID15 to ID08 of the extended frame format
bits ID23 to ID18 of the extended frame format
bits ID05 to ID00 of the standard frame format
1:0 ID17:ID16
7:5 reserved
4:0 ID28:ID24
R/W
R
-
-
-
bits ID17 to ID16 of the extended frame format
2Ah
R/W
bits ID28 to ID24 of the extended frame format
bits ID10 to ID06 of the standard frame format
7.8.3.3 ID mask registers (0x2B to 0x2E)
Table 19. ID mask registers 0 to 3 (addresses 2Bh to 2Eh)
Addr. Bit Symbol
2Bh 7:0 M07:M00
2Ch 7:0 M15:M08
2Dh 7:2 M23:M18
Access Value Description
R/W
R/W
R/W
-
-
-
mask bits ID07 to ID00 of the extended frame format
mask bits ID15 to ID08 of the extended frame format
mask bits ID23 to ID18 of the extended frame format
mask bits ID05 to ID00 of the standard frame format
1:0 M17:M16
2Eh 7:5 reserved
4:0 M28:M24
R/W
R
-
-
-
mask bits ID17 to ID16 of the extended frame format
R/W
mask bits ID28 to ID24 of the extended frame format
mask. bits ID10 to ID06 of the standard frame format
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7.8.3.4 Frame control register (0x2F)
Table 20. Frame control register (address 2Fh)
Bit
Symbol
Access
Value
Description
7
IDE
R/W
-
identifier format:
0
1
-
standard frame format (11-bit)
extended frame format (29-bit)
partial networking data mask:
6
PNDM
R/W
0
data length code and data field are ‘don’t care’ for
wake-up
1
-
data length code and data field are evaluated at
wake-up
5:4
3:0
reserved
DLC
R
R/W
number of data bytes expected in a CAN frame:
0000
0001
0010
0011
0100
0101
0110
0111
1000
0
1
2
3
4
5
6
7
8
1001 to
1111
tolerated, 8 bytes expected
7.8.3.5 Data mask registers (0x68 to 0x6F)
Table 21. Data mask registers (addresses 68h to 6Fh)
Addr.
68h
Bit
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
Symbol
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
Access Value
Description
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
-
-
-
-
-
-
-
data mask 0 configuration
data mask 1 configuration
data mask 2 configuration
data mask 3 configuration
data mask 4 configuration
data mask 5 configuration
data mask 6 configuration
data mask 7 configuration
69h
6Ah
6Bh
6Ch
6Dh
6Eh
6Fh
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'/&ꢁ!ꢁꢈ
'/&ꢁ ꢁꢈ
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Fig 13. Data mask register usage for different values of DLC
7.9 CAN fail-safe features
7.9.1 TXD dominant time-out
A TXD dominant time-out timer is started when pin TXD is forced LOW while the
transceiver is in CAN Active Mode. The transmitter is disabled if the LOW state on pin
TXD persists for longer than the TXD dominant time-out time (tto(dom)TXD), releasing the
bus lines to recessive state. The TXD dominant time-out timer is reset when pin TXD goes
HIGH. The TXD dominant time-out time also defines the minimum possible bit rate of
4.4 kbit/s.
When the TXD dominant time-out time is exceeded, a CAN failure event is captured
(CF = 1; see Table 28), if enabled (CFE = 1; see Table 32). In addition, the status of the
TXD dominant time-out can be read via the CFS bit in the Transceiver status register
(Table 16) and bit CTS is cleared.
7.9.2 Pull-up on TXD pin
Pin TXD has an internal pull-up towards V1 to ensure a safe defined recessive driver state
in case the pin is left floating.
7.9.3 VCAN undervoltage event
A CAN failure event is captured (CF = 1), if enabled, when the supply to the CAN
transceiver falls below 90 % of its nominal value. In addition, status bit VCS is set to 1.
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7.9.4 Loss of power at pin BAT
When power is lost at pin BAT, the SBC behaves passively towards the CAN-bus pins,
disabling the bias circuitry. This ensures that a loss of power at BAT does not affect
ongoing communication between nodes on the network.
7.10 Wake-up and interrupt event handling
7.10.1 WAKE pin
Local wake-up is enabled via bits WPRE and WPFE in the WAKE pin event capture
enable register (see Table 33). A wake-up event is triggered by a LOW-to-HIGH (if
WPRE = 1) and/or a HIGH-to-LOW (if WPFE = 1) transition on the WAKE pin. This
arrangement allows for maximum flexibility when designing a local wake-up circuit. In
applications that do not use the local wake-up facility, local wake-up should be disabled
and the WAKE pin connected to GND.
7.10.1.1 WAKE pin status register (0x4B)
Table 22. WAKE pin status register (address 4Bh)
Bit
7:2
1
Symbol
reserved
WPVS
Access Value Description
R
R
-
WAKE pin status:
0
1
-
voltage on WAKE pin below switching threshold (Vth(sw))
voltage on WAKE pin above switching threshold (Vth(sw)
)
0
reserved
R
While the SBC is in Normal mode, the status of the voltage on pin WAKE can always be
read via bit WPVS. Otherwise, WPVS is only valid if local wake-up is enabled (WPRE = 1
and/or WPFE = 1).
7.10.2 Wake-up diagnosis
Wake-up and interrupt event diagnosis in the UJA1169 is intended to provide the
microcontroller with information on the status of a range of features and functions. This
information is stored in the event status registers (Table 26 to Table 28) and is signaled on
pin RXD, if enabled.
A distinction is made between regular wake-up events and interrupt events.
Table 23. Regular events
Symbol Event
Power-on Description
CW
CAN wake-up
disabled
rising edge on WAKE pin disabled
falling edge on WAKE pin disabled
see Transceiver event status register (Table 28)
WPR
WPF
see WAKE pin event capture status register
(Table 29)
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Table 24. Diagnostic events
Symbol Event
Power-on
always enabled
disabled
Description
PO
power-on
see System event status register
(Table 26)
OTW
SPIF
WDF
V2O[1]
overtemperature warning
SPI failure
disabled
watchdog failure
V2 overvoltage
always enabled
disabled
see Supply event status register
(Table 27)
VEXTO[2] VEXT overvoltage
V2U[1]
V2 undervoltage
VEXTU[2] VEXT undervoltage
V1U V1 undervoltage
PNFDE[3] PN frame detection error
disabled
disabled
disabled
disabled
always enabled
disabled
see Transceiver event status register
(Table 28)
CBS
CF
CAN-bus silence
CAN failure
disabled
[1] UJA1169TK, UJA1169TK/3, UJA1169TK/F and UJA1169TK/F/3 only.
[2] UJA1169TK/X and UJA1169TK/X/F only.
[3] UJA1169TK/F, UJA1169TK/F/3 and UJA1169TK/X/F only; otherwise reserved.
PO, WDF and PNFDE interrupts are always enabled and thus captured. Wake-up and
interrupt detection can be enabled/disabled for the remaining events individually via the
event capture enable registers (Table 30 to Table 32).
If an event occurs while the associated event capture function is enabled, the relevant
event status bit is set. If the transceiver is in CAN Offline mode with V1 active (SBC
Normal or Standby mode), pin RXD is forced LOW to indicate that a wake-up or interrupt
event has been detected. If the UJA1169 is in sleep mode when the event occurs, the
microcontroller supply, V1, is activated and the SBC switches to Standby mode (via Reset
mode).
The microcontroller can monitor events via the event status registers. An extra status
register, the Global event status register (Table 25), is provided to help speed up software
polling routines. By polling the Global event status register, the microcontroller can quickly
determine the type of event captured (system, supply, transceiver or WAKE pin) and then
query the relevant event status register (Table 26, Table 27, Table 28 or Table 29
respectively).
After the event source has been identified, the status flag should be cleared (set to 0) by
writing 1 to the relevant bit (writing 0 will have no effect). A number of status bits can be
cleared in a single write operation by writing 1 to all relevant bits.
Only clear the status bits that were set to 1 when the status registers were last read. This
precaution ensures that events triggered just before the write access are not lost.
7.10.3 Interrupt/wake-up delay
If interrupt or wake-up events occur very frequently while the transceiver is in CAN Offline
mode, they can have a significant impact on the software processing time (because pin
RXD is repeatedly driven LOW, requiring a response from the microcontroller each time
an interrupt/wake-up is generated). The UJA1169 incorporates an event delay timer to
limit the disturbance to the software.
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When one of the event capture status bits is cleared, pin RXD is released (HIGH) and a
timer is started. If further events occur while the timer is running, the relevant status bits
are set. If one or more events are pending when the timer expires after td(event), pin RXD
goes LOW again to alert the microcontroller. In this way, the microcontroller is interrupted
once to process a number of events rather than several times to process individual
events.
If all events are cleared while the timer is running, RXD remains HIGH after the timer
expires, since there are no pending events. The event capture registers can be read at
any time.
The event capture delay timer is stopped immediately when pin RSTN goes low (triggered
by a HIGH-to-LOW transition on the pin). RSTN is driven LOW when the SBC enters
Reset, Sleep, Overtemp and Off modes. A pending event is signaled on pin RXD when
the SBC enters Sleep mode.
7.10.4 Sleep mode protection
The wake-up event capture function is critical when the UJA1169 is in Sleep mode,
because the SBC only leaves Sleep mode in response to a captured wake-up event. To
avoid potential system deadlocks, the SBC distinguishes between regular and diagnostic
events (see Section 7.10). Wake-up events (via the CAN-bus or the WAKE pin) are
classified as regular events; diagnostic events signal failure/error conditions or state
changes. At least one regular wake-up event must be enabled before the UJA1169 can
switch to Sleep mode. Any attempt to enter Sleep mode while all regular wake-up events
are disabled triggers a system reset.
Another condition that must be satisfied before the UJA1169 can switch to Sleep mode is
that all event status bits must be cleared. If an event is pending when the SBC receives a
Sleep mode command (MC = 001), it immediately switches to Reset mode. This condition
applies to both regular and diagnostic events.
Sleep mode can be permanently disabled in applications where, for safety reasons, the
supply voltage to the host controller must never be cut off. Sleep mode is permanently
disabled by setting the Sleep control bit (SLPC) in the SBC configuration register (see
Table 9) to 1. This register is located in the non-volatile memory area of the device. When
SLPC = 1, a Sleep mode SPI command (MC = 001) triggers an SPI failure event instead
of a transition to Sleep mode.
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7.10.5 Event status and event capture registers
After an event source has been identified, the status flag should be cleared (set to 0) by
writing 1 to the relevant status bit (writing 0 will have no effect).
7.10.5.1 Event status registers (0x60 to 0x64)
Table 25. Global event status register (address 60h)
Bit
7:4
3
Symbol
reserved
WPE
Access
Value
Description
R
R
-
WAKE pin event:
0
1
no pending WAKE pin event
WAKE pin event pending at address 0x64
transceiver event:
2
1
0
TRXE
SUPE
SYSE
R
R
R
0
1
no pending transceiver event
transceiver event pending at address 0x63
supply event:
0
1
no pending supply event
supply event pending at address 0x62
system event:
0
1
no pending system event
system event pending at address 0x61
Table 26. System event status register (address 61h)
Bit
7:5
4
Symbol
reserved
PO
Access Value
Description
R
-
R/W
power-on:
0
1
-
no recent battery power-on
the UJA1169 has left Off mode after battery power-on
3
2
reserved
OTW
R
R/W
overtemperature warning:
0
1
overtemperature not detected
the global chip temperature has exceeded the
overtemperature warning threshold, Tth(warn)otp (not in
Sleep mode)
1
SPIF
R/W
SPI failure:
0
1
no SPI failure detected
SPI clock count error (only 16-, 24- and 32-bit
commands are valid), illegal WMC, NWP or MC code
or attempted write access to locked register (not in
Sleep mode)
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Table 26. System event status register (address 61h) …continued
Bit
Symbol
Access Value
Description
0
WDF
R/W
watchdog failure:
0
no watchdog failure event captured
1
watchdog overflow in Window or Timeout mode or
watchdog triggered too early in Window mode; a
system reset is triggered immediately in response to
a watchdog failure in Window mode; when the
watchdog overflows in Timeout mode, a system reset
is only performed if a WDF is already pending
(WDF = 1)
Table 27. Supply event status register (address 62h)
Bit
7:3
2
Symbol
Access
R
Value
Description
reserved
V2O[1]/
VEXTO[2]
-
R/W
V2/VEXT overvoltage:
0
1
no V2/VEXT overvoltage event captured
V2/VEXT overvoltage event captured
V2/VEXT undervoltage:
1
0
V2U[1]
/
R/W
R/W
VEXTU[2]
0
1
no V2/VEXT undervoltage event captured
V2/VEXT undervoltage event captured
V1 undervoltage:
V1U
0
1
no V1 undervoltage event captured
voltage on V1 has dropped below the 90 %
undervoltage threshold while V1 is active (event is
not captured in Sleep mode because V1 is off);
V1U event capture is independent of the setting of
bits V1RTC
[1] UJA1169TK, UJA1169TK/3, UJA1169TK/F and UJA1169TK/F/3 only.
[2] UJA1169TK/X and UJA1169TK/X/F only.
Table 28. Transceiver event status register (address 63h)
Bit
7:6
5
Symbol
reserved
PNFDE
Access
R
Value
Description
-
R/W
partial networking frame detection error:
0
1
no partial networking frame detection error
detected
partial networking frame detection error detected
CAN-bus status:
4
CBS
R/W
R
0
1
CAN-bus active
no activity on CAN-bus for tto(silence) (detected only
when CBSE = 1 while bus active)
3:2
reserved
-
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Table 28. Transceiver event status register (address 63h) …continued
Bit
Symbol
Access
Value
Description
1
CF
R/W
CAN failure:
0
1
no CAN failure detected
CAN transceiver deactivated due to VCAN
undervoltage OR dominant clamped TXD (not in
Sleep mode)
0
CW
R/W
CAN wake-up:
0
1
no CAN wake-up event detected
CAN wake-up event detected while the transceiver
is in CAN Offline Mode
Table 29. WAKE pin event status register (address 64h)
Bit
7:2
1
Symbol
reserved
WPR
Access
R
Value
Description
-
R/W
WAKE pin rising edge:
0
1
no rising edge detected on WAKE pin
rising edge detected on WAKE pin
WAKE pin falling edge:
0
WPF
R/W
0
1
no falling edge detected on WAKE pin
falling edge detected on WAKE pin
7.10.5.2 Event capture enable registers (0x04, 0x1C, 0x23, 0x4C)
Table 30. System event capture enable register (address 04h)
Bit
7:3
2
Symbol
reserved
OTWE
Access
R
Value
Description
-
R/W
overtemperature warning enable:
overtemperature warning disabled
overtemperature warning enabled
SPI failure enable:
0
1
1
0
SPIFE
R/W
R
0
1
-
SPI failure detection disabled
SPI failure detection enabled
reserved
Table 31. Supply event capture enable register (address 1Ch)
Bit
7:3
2
Symbol
Access
R
Value
Description
reserved
V2OE[1]/
VEXTOE[2]
-
R/W
V2/VEXT overvoltage enable:
0
1
V2/VEXT overvoltage detection disabled
V2/VEXT overvoltage detection enabled
V2/VEXT undervoltage enable:
1
V2UE[1]/
VEXTUE[2]
R/W
0
1
V2/VEXT undervoltage detection disabled
V2/VEXT undervoltage detection enabled
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Table 31. Supply event capture enable register (address 1Ch) …continued
Bit
Symbol
Access
Value
Description
0
V1UE
R/W
V1 undervoltage enable:
V1 undervoltage detection disabled
V1 undervoltage detection enabled
0
1
[1] UJA1169TK, UJA1169TK/3, UJA1169TK/F and UJA1169TK/F/3 only.
[2] UJA1169TK/X and UJA1169TK/X/F only.
Table 32. Transceiver event capture enable register (address 23h)
Bit
7:5
4
Symbol
reserved
CBSE
Access
R
Value
Description
-
R/W
CAN-bus silence enable:
0
1
-
CAN-bus silence detection disabled
CAN-bus silence detection enabled
3:2
1
reserved
CFE
R
R/W
CAN failure enable:
0
1
CAN failure detection disabled
CAN failure detection enabled
CAN wake-up enable:
0
CWE
R/W
0
1
CAN wake-up detection disabled
CAN wake-up detection enabled
Table 33. WAKE pin event capture enable register (address 4Ch)
Bit
7:2
1
Symbol
reserved
WPRE
Access
R
Value
Description
-
R/W
WAKE pin rising-edge enable:
0
1
rising-edge detection on WAKE pin disabled
rising-edge detection on WAKE pin enabled
WAKE pin falling-edge enable:
0
WPFE
R/W
0
1
falling-edge detection on WAKE pin disabled
falling-edge detection on WAKE pin enabled
7.11 Non-volatile SBC configuration
The UJA1169 contains Multiple Time Programmable Non-Volatile (MTPNV) memory cells
that allow some of the default device settings to be reconfigured. The MTPNV memory
address range is from 0x73 to 0x74. For details, see Table 9 and Table 11.
7.11.1 Programming MTPNV cells
NXP delivers the UJA1169 in so-called ‘Forced Normal’ mode, also referred to as the
‘factory preset’ configuration. In order to change the default settings, the device must be in
Forced Normal mode with FNMC = 1 and NVMPS = 1. In Forced Normal mode, the
watchdog is disabled, all regulators are on and the CAN transceiver is in Active mode.
UJA1169
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If the device has been programmed previously, the factory presets may need to be
restored before reprogramming can begin (see Section 7.11.2). When the factory presets
have been restored successfully, a system reset is generated automatically and UJA1169
switches back to Forced Normal mode.
Programming of the non-volatile memory (NVM) registers is performed in two steps. First,
the required values are written to addresses 0x73 and 0x74. In the second step,
reprogramming is confirmed by writing the correct CRC value to the MTPNV CRC control
register (see Section 7.11.1.2). The SBC starts reprogramming the MTPNV cells as soon
as the CRC value has been validated. If the CRC value is not correct, reprogramming is
aborted. On completion, a system reset is generated to indicate that the MTPNV cells
have been reprogrammed successfully. Note that the MTPNV cells cannot be read while
they are being reprogrammed.
After an MTPNV programming cycle has been completed, the NVM is protected from
being overwritten.
The MTPNV cells can be reprogrammed a maximum of 200 times (Ncy(W)MTP; see
Table 52). Bit NVMPS in the MTPNV status register (Table 34) indicates whether the
non-volatile cells can be reprogrammed. This register also contains a write counter,
WRCNTS, that is incremented each time the MTPNV cells are reprogrammed (up to a
maximum value of 111111; there is no overflow; performing a factory reset also increments
the counter). This counter is provided for information purposes only; reprogramming will
not be rejected when it reaches its maximum value.
An error correction code status bit, ECCS, is set to indicate the CRC check mechanism in
the SBC has detected and corrected a single bit failure in non-volatile memory. If more
than one bit failure is detected, the SBC will not restart after MTPNV reprogramming.
Check the ECCS flag at the end of the production cycle to verify the content of non-volatile
memory. When this flag is set, it indicates a device or ECU failure.
7.11.1.1 MTPNV status register (0x70)
Table 34. MTPNV status register (address 70h)
Bit
Symbol
Access
Value Description
write counter status:
7:2
WRCNTS
R
xxxxxx
contains the number of times the MTPNV cells were
reprogrammed
1
0
ECCS
R/W
R/W
error correction code status:
0
1
no bit failure detected in non-volatile memory
bit failure detected and corrected in non-volatile
memory
NVMPS
non-volatile memory programming status:
MTPNV memory cannot be overwritten
MTPNV memory is ready to be reprogrammed
0
1[1]
[1] Factory preset value.
UJA1169
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7.11.1.2 MTPNV CRC control register (0x75)
The cyclic redundancy check value stored in bits CRCC in the MTPNV CRC control
register is calculated using the data written to registers 0x73 and 0x74.
Table 35. MTPNV CRC control register (address 75h)
Bit
Symbol
Access
Value
Description
7:0
CRCC
R/W
cyclic redundancy check control:
CRC control data
-
The CRC value is calculated using the data representation shown in Figure 14 and the
modulo-2 division with the generator polynomial: X8 + X5 + X3 + X2 + X + 1. The result of
this operation must be bitwise inverted.
ꢐ
ꢏ
ꢆ
ꢌ
ꢐ
ꢏ
ꢆ
ꢌ
UHJLVWHUꢁꢌ[ꢐꢃ
UHJLVWHUꢁꢌ[ꢐꢉ
ꢁꢂꢇDDDꢉꢆꢊ
Fig 14. Data representation for CRC calculation
The following parameters can be used to calculate the CRC value (e.g. via the Autosar
method):
Table 36. Parameters for CRC coding
Parameter
Value
8 bits
0x2F
0xFF
no
CRC result width
Polynomial
Initial value
Input data reflected
Result data reflected
XOR value
no
0xFF
Alternatively, the following algorithm can be used:
data
crc
for
=
0
// unsigned byte
=
i
0xFF
=
0
to
1
data
for
=
content_of_address(0x73 + i) EXOR crc
j
=
0
to
7
if data
128
data
data
=
=
data
data EXOR 0x2F
*
2
// shift left by 1
else
data
=
data * 2 // shift left by 1
next
crc
j
=
data
next
crc
i
=
crc EXOR 0xFF
UJA1169
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7.11.2 Restoring factory preset values
Factory preset values are restored if the following conditions apply continuously for at
least td(MTPNV) during battery power-up:
• pin RSTN is held LOW
• CANH is pulled up to VBAT
• CANL is pulled down to GND
After the factory preset values have been restored, the SBC performs a system reset and
enters Forced normal Mode. Since the CAN-bus is clamped dominant, pin RXDC is forced
LOW. Pin RXD is forced HIGH during the factory preset restore process (td(MTPNV)). A
falling edge on RXD caused by bit PO being set after power-on indicates that the factory
preset process has been completed.
Note that the write counter, WRCNTS, in the MTPNV status register is incremented every
time the factory presets are restored.
7.12 Device identification
7.12.1 Device identification register (0x7E)
A byte is reserved at address 0x7E for a product identification code used to distinguish the
different UJA1169 derivatives.
Table 37. Identification register (address 7Eh)
Bit
Symbol
Access
Value
Description
7:0
IDS[7:0]
R
identification status:
UJA1169TK
CFh
C9h
EFh
E9h
CEh
EEh
UJA1169TK/3
UJA1169TK/F
UJA1169TK/F/3
UJA1169TK/X
UJA1169TK/X/F
7.13 Register locking
Sections of the register address area can be write-protected to protect against unintended
modifications. This facility only protects locked bits from being modified via the SPI and
will not prevent the UJA1169 updating status registers etc.
7.13.1 Lock control register (0x0A)
Table 38. Lock control register (address 0Ah)
Bit Symbol Access Value Description
7
6
reserved
LK6C
R
-
reserved for future use
R/W
lock control 6: address area 0x68 to 0x6F - data mask (/F
versions only)
0
1
SPI write access enabled
SPI write access disabled
UJA1169
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Table 38. Lock control register (address 0Ah) …continued
Bit Symbol Access Value Description
5
LK5C
R/W
lock control 5: address area 0x50 to 0x5F - unused register
range
0
1
SPI write access enabled
SPI write access disabled
4
3
LK4C
LK3C
R/W
R/W
lock control 4: address area 0x40 to 0x4F - WAKE pin control
SPI write access enabled
0
1
SPI write access disabled
lock control 3: address area 0x30 to 0x3F - unused register
range
0
1
SPI write access enabled
SPI write access disabled
2
1
0
LK2C
LK1C
LK0C
R/W
R/W
R/W
lock control 2: address area 0x20 to 0x2F - transceiver control
SPI write access enabled
0
1
SPI write access disabled
lock control 1: address area 0x10 to 0x1F - regulator control
SPI write access enabled
0
1
SPI write access disabled
lock control 0: address area 0x06 to 0x09 - general-purpose
memory
0
1
SPI write access enabled
SPI write access disabled
7.14 General-purpose memory
UJA1169 allocates 4 bytes of memory as general-purpose registers for storing user
information. The general-purpose registers can be accessed via the SPI at address 0x06
to 0x09 without read or write cycle limitations (see Table 39).
7.15 SPI
7.15.1 Introduction
The Serial Peripheral Interface (SPI) provides the communication link with the
microcontroller, supporting multi-slave operations. The SPI is configured for full duplex
data transfer, so status information is returned when new control data is shifted in. The
interface also offers a read-only access option, allowing the application to read back
registers without changing the register content.
The SPI uses four interface signals for synchronization and data transfer:
• SCSN: SPI chip select; active LOW; default level is HIGH (pull-up)
• SCK: SPI clock; default level is LOW due to low-power concept (pull-down)
• SDI: SPI data input (floating input; may need external pull-up or pull-down if not
available in the host controller)
• SDO: SPI data output; floating when pin SCSN is HIGH (may need external pull-up or
pull-down if not available in the host controller)
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Bit sampling is performed on the falling edge of the clock and data is shifted in/out on the
rising edge, as illustrated in Figure 15.
6&61
6&.
6',
ꢌꢆ
ꢌꢊ
ꢌꢃ
ꢌꢉ
1ꢋꢆ
1
VDPSOHG
;
06%
06%ꢋꢆ
06%ꢋꢊ
06%ꢋꢃ
ꢌꢆ
/6%
/6%
;
06%
06%ꢋꢆ
06%ꢋꢊ
06%ꢋꢃ
ꢌꢆ
6'2
;
IORDWLQJ
IORDWLQJ
ꢁꢂꢇDDDꢊꢇꢇ
Fig 15. SPI timing overview (see Figure 19 for detailed SPI timing)
The SPI data in the UJA1169 is stored in a number of dedicated 8-bit registers. Each
register is assigned a unique 7-bit address. Two bytes (16 bits) must be transmitted to the
SBC for a single register read or write operation. The first byte contains the 7-bit address
along with a ‘read-only’ bit (the LSB). The read-only bit must be 0 to indicate a write
operation (if this bit is 1, a read operation is assumed and any data on the SDI pin is
ignored). The second byte contains the data to be written to the register.
24- and 32-bit read and write operations are also supported. The register address is
automatically incremented, once for a 24-bit operation and twice for a 32-bit operation, as
illustrated in Figure 16.
5HJLVWHUꢁ$GGUHVVꢁ5DQJH
ꢌ[ꢌꢌ
ꢌ[ꢌꢆ
ꢌ[ꢌꢊ
ꢌ[ꢌꢃ
ꢌ[ꢌꢉ
ꢌ[ꢌꢀ
ꢌ[ꢌꢏ
GDWD
ꢌ[ꢌꢐ
ꢌ[ꢐ' ꢌ[ꢐ( ꢌ[ꢐ)
,' ꢌ[ꢌꢀ
GDWD
GDWD
DGGUꢁꢌꢌꢌꢌꢆꢌꢆ
GDWDꢁE\WHꢁꢆ
GDWDꢁE\WHꢁꢊ
GDWDꢁE\WHꢁꢃ
$ꢏ $ꢀ $ꢉ $ꢃ $ꢊ $ꢆ $ꢌ 52
[
[
[
[
[
[
[
[
$GGUHVVꢁ%LWV
5HDGꢋRQO\ꢁ%LW
'DWDꢁ%LWV
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
ꢁꢂꢇDDDꢊꢆꢋ
'DWDꢁ%LWV
'DWDꢁ%LWV
Fig 16. SPI data structure for a write operation (16-, 24- or 32-bit)
UJA1169
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The contents of the addressed registers are returned via pin SDO during an SPI data read
or write operation,
The UJA1169 tolerates attempts to write to registers that do not exist. If the available
address space is exceeded during a write operation, the data above the valid address
range is ignored (without generating an SPI failure event).
During a write operation, the UJA1169 monitors the number of SPI bits transmitted. If the
number recorded is not 16, 24 or 32, then the write operation is aborted and an SPI failure
event is captured (SPIF = 1).
If more than 32 bits are clocked in on pin SDI during a read operation, the data stream on
SDI is reflected on SDO from bit 33 onwards.
An SPI read/write access must not be attempted for at least tto(SPI) after the UJA1169 exits
Reset mode (positive edge on RSTN). Any earlier access may be ignored (without
generating an SPI failure event).
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7.15.2 Register map
The addressable register space contains 128 registers with addresses from 0x00 to 0x7F.
An overview of the register mapping is provided in Table 39 to Table 48. The functionality
of individual bits is discussed in more detail in relevant sections of the data sheet.
Table 39. Overview of primary control registers
Address Register Name
Bit:
7
6
5
4
3
2
1
0
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
Watchdog control
Mode control
Fail-safe control
Main status
WMC
reserved
reserved
reserved NWP
MC
LHC
RCC
reserved OTWS
reserved
NMS
RSS
System event enable
Watchdog status
Memory 0
OTWE
SDMS
SPIFE
WDS
reserved
reserved
FNMS
GPM[7:0]
Memory 1
GPM[15:8]
Memory 2
GPM[23:16]
GPM[31:24]
reserved LK6C
Memory 3
Lock control
LK5C
LK4C
LK3C
LK2C
LK1C
LK0C
Table 40. Overview of regulator control registers
Address Register Name
Bit:
7
6
5
4
3
2
1
0
0x10
Regulator control
reserved[1] PDC reserved
V2C[2]/
VEXTC[3]
V1RTC[4]
0x1B
0x1C
Supply status
reserved
reserved
V2S[2]/VEXTS[3]
V2OE[2] V2UE[2]/
VEXTOE[3] VEXTUE[3]
V1S
Supply event enable
/
V1UE
[1] Reserved bits can be read and overwritten without affecting device functionality; default value at power-up is 00 (other reserved bits
always return 0).
[2] UJA1169TK, UJA1169TK/3, UJA1169TK/F and UJA1169TK/F/3 only.
[3] UJA1169TK/X and UJA1169TK/X/F only.
[4] Fixed at 00 in UJA1169TK/3 and UJA1169TK/F/3.
Table 41. Overview of transceiver control and partial networking registers
Address Register Name
Bit:
7
6
5
4
3
2
1
0
0x20
0x22
0x23
0x26
0x27
0x28
0x29
CAN control
reserved CFDC[1]
PNCOK[1] CPNC[1] reserved
CMC
Transceiver status
CTS
CPNERR[1] CPNS[1]
COSCS[1] CBSS reserved VCS
CFS
Transceiver event enable reserved
CBSE reserved CFE
CWE
Data rate
reserved
ID[7:0][1]
ID[15:8][1]
ID[23:16][1]
CDR[1]
Identifier 0
Identifier 1
Identifier 2
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Table 41. Overview of transceiver control and partial networking registers …continued
Address Register Name
Bit:
7
6
5
4
3
2
1
0
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
Identifier 3
Mask 0
reserved
M[7:0][1]
M[15:8][1]
M[23:16][1]
reserved
IDE[1]
DM0[7:0][1]
DM1[7:0][1]
DM2[7:0][1]
DM3[7:0][1]
DM4[7:0][1]
DM5[7:0][1]
DM6[7:0][1]
DM7[7:0][1]
ID[28:24][1]
Mask 1
Mask 2
Mask 3
M[28:24][1]
Frame control
Data mask 0
Data mask 1
Data mask 2
Data mask 3
Data mask 4
Data mask 5
Data mask 6
Data mask 7
PNDM[1]
reserved
DLC[1]
[1] UJA1169TK/F, UJA1169TK/F/3 and UJA1169TK/X/F only; otherwise reserved.
Table 42. Overview of WAKE pin control and status registers
Address
Register Name
Bit:
7
6
5
4
3
2
2
1
0
0x4B
0x4C
WAKE pin status
WAKE pin enable
reserved
reserved
WPVS
WPRE
reserved
WPFE
Table 43. Overview of event capture registers
Address Register Name
Bit:
7
6
5
4
3
1
0
0x60
0x61
0x62
Global event status
System event status
Supply event status
reserved
reserved
reserved
WPE
TRXE
SUPE
SYSE
WDF
V1U
PO
reserved OTW
V2O[1]/
SPIF
V2U[1]
/
VEXTO[2] VEXTU[2]
0x63
0x64
Transceiver event status reserved
WAKE pin event status reserved
PNFDE[3] CBS
reserved
CF
CW
WPR
WPF
[1] UJA1169TK, UJA1169TK/3, UJA1169TK/F and UJA1169TK/F/3 only.
[2] UJA1169TK/X and UJA1169TK/X/F only.
[3] UJA1169TK/F, UJA1169TK/F/3 and UJA1169TK/X/F only; otherwise reserved.
Table 44. Overview of MTPNV status register
Address
Register Name
Bit:
7
6
5
4
3
2
1
0
0x70
MTPNV status
WRCNTS
ECCS
NVMPS
UJA1169
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Table 45. Overview of Start-up control register
Address
Register Name
Bit:
7
6
5
4
3
2
1
0
0x73
Start-up control
reserved
RLC
V2SUC[1]/
VEXTSUC[2]
reserved
[1] UJA1169TK, UJA1169TK/3, UJA1169TK/F and UJA1169TK/F/3 only.
[2] UJA1169TK/X and UJA1169TK/X/F only.
Table 46. Overview of SBC configuration control register
Address Register Name
Bit:
7
6
5
4
3
2
1
0
0x74
SBC configuration control reserved
V1RTSUC
FNMC
SDMC
reserved SLPC
Table 47. Overview of CRC control register
Address
Register Name
Bit:
7
6
5
5
4
3
3
2
2
1
1
0
0
0x75
MTPNV CRC control
CRCC[7:0]
Table 48. Overview of Identification register
Address
Register Name
Bit:
7
6
4
0x7E
Identification
IDS[7:0]
7.15.3 Register configuration in UJA1169 operating modes
A number of register bits may change state automatically when the UJA1169 switches
from one operating mode to another. This feature is particularly evident when the
UJA1169 switches to Off mode. These changes are summarized in Table 49. If an SPI
transmission is in progress when the UJA1169 changes state, the transmission is ignored
(automatic state changes have priority).
Table 49. Register bit settings in UJA1169 operating modes
Symbol
Off (power-on
default)
Standby
Normal
Sleep
Overtemp
Reset
CBS
0
no change
no change
actual state
no change
no change
no change
no change
actual state
no change
actual state
no change
actual state
no change
no change
actual state
no change
no change
no change
no change
actual state
no change
actual state
no change
actual state
no change
no change
no change
no change
no change
no change
no change
actual state
no change
actual state
no change
actual state
no change
no change
actual state
no change
no change
no change
no change
actual state
no change
actual state
no change
actual state
no change
no change
actual state
no change
no change
no change
no change
actual state
no change
actual state
no change
actual state
CBSE
CBSS
CDR[1]
CF
0
1
101
0
CFDC[1]
0
CFE
0
CFS
0
CMC
00
0
COSCS[1]
CPNC[1]
CPNERR[1]
0
1
UJA1169
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Table 49. Register bit settings in UJA1169 operating modes …continued
Symbol
Off (power-on
default)
Standby
Normal
Sleep
Overtemp
Reset
CPNS[1]
CRCC
CTS
0
actual state
no change
0
actual state
no change
actual state
no change
no change
no change
no change
actual state
MTPNV
actual state
no change
0
actual state
no change
0
actual state
no change
0
00000000
0
CW
0
no change
no change
no change
no change
actual state
MTPNV
no change
no change
no change
no change
actual state
MTPNV
no change
no change
no change
no change
actual state
MTPNV
no change
no change
no change
no change
actual state
MTPNV
CWE
DMn[1]
DLC[1]
ECCS
FNMC
FNMS
GPMn
IDn
0
11111111
0000
actual state
MTPNV
0
actual state
no change
no change
no change
no change
actual state
no change
no change
no change
no change
actual state
no change
no change
no change
no change
actual state
no change
no change
no change
no change
actual state
no change
no change
no change
no change
00000000
00000000
0
IDE
IDS
1100 1111 (TK)
1101 1111 (TK/3)
1110 1111 (TK/F)
1111 1111 (TK/F/3)
1100 1110 (TK/X)
1110 1110 (TK/X/F)
LHC
0
no change
no change
no change
1 if t > td(limp)
otherwise no
change
;
1 if RCC = 3 or
t > td(limp)
;
otherwise no
change
LKnC
MC
0
no change
100
no change
111
no change
001
no change
don’t care
no change
actual state
0100
no change
100
100
NMS
1
no change
actual state
no change
no change
no change
actual state
no change
no change
no change
no change
no change
no change
MTPNV
0
no change
actual state
no change
no change
no change
actual state
no change
no change
no change
no change
no change
no change
MTPNV
no change
actual state
0100
NVMPS
NWP
actual state
actual state
no change
no change
no change
actual state
no change
no change
no change
no change
no change
no change
MTPNV
0100
OTW
0
no change
no change
actual state
no change
no change
no change
no change
no change
no change
MTPNV
no change
no change
actual state
no change
no change
no change
no change
no change
RCC++
OTWE
OTWS
PDC
PNCOK[1]
PNDM[1]
PNFDE[1]
PO
0
0
0
0
1
0
1
RCC
00
RLC
MTPNV
00000
MTPNV
0
MTPNV
RSS
no change
MTPNV
no change
MTPNV
no change
MTPNV
10010
reset source
MTPNV
SDMC
SDMS
SLPC
MTPNV
actual state
MTPNV
actual state
MTPNV
actual state
MTPNV
actual state
MTPNV
actual state
MTPNV
MTPNV
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Mini high-speed CAN SBC with optional partial networking
Table 49. Register bit settings in UJA1169 operating modes …continued
Symbol
Off (power-on
default)
Standby
Normal
Sleep
Overtemp
Reset
SPIF
0
0
0
1
0
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
SPIFE
SUPE
SYSE
TRXE
V1RTC
defined by V1RTSUC no change
in 5 V variants[2]
V1RTSUC
V1S
MTPNV
MTPNV
MTPNV
MTPNV
MTPNV
MTPNV
0
0
0
0
actual state
no change
no change
actual state
no change
actual state
no change
no change
actual state
no change
actual state
no change
no change
actual state
no change
actual state
no change
no change
actual state
no change
actual state
no change
no change
actual state
no change
V1UE
V1U
VCS
V2C[3]/
VEXTC[4]
defined by
V2SUC[3]/VEXTSUC[4]
V2O[3]/
0
no change
no change
actual state
MTPNV
no change
no change
actual state
MTPNV
no change
no change
actual state
MTPNV
no change
no change
actual state
MTPNV
no change
no change
actual state
MTPNV
VEXTO[4]
V2OE[3]/
VEXTOE[4]
V2S[3]/
VEXTS[4]
V2SUC[3]/
VEXTSUC[4]
0
00
MTPNV
V2U[3]/
0
0
0
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
VEXTU[4]
V2UE[3]/
VEXTUE[4]
WDF
no change
actual state
no change
no change
no change
no change
no change
no change
no change
actual state
no change
actual state
no change
no change
no change
no change
no change
no change
no change
actual state
no change
actual state
no change
no change
no change
no change
no change
no change
no change
actual state
no change
actual state
no change
no change
no change
no change
no change
no change
no change
actual state
WDS
0
actual state
[5]
[5]
WMC
WPE
0
no change
no change
no change
no change
no change
no change
actual state
WPF
0
WPR
0
WPFE
WPRE
WPVS
WRCNTS
0
0
0
actual state
[1] UJA1169TK/F, UJA1169TK/F/3, and UJA1169TK/X/F only; otherwise reserved.
[2] Fixed at 00 in UJA1169TK/3 and UJA1169TK/F/3.
[3] UJA1169TK, UJA1169TK/3, UJA1169TK/F and UJA1169TK/F/3 only.
[4] UJA1169TK/X and UJA1169TK/X/F only.
[5] 001 if SDMC = 1; otherwise 010.
UJA1169
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Mini high-speed CAN SBC with optional partial networking
8. Limiting values
Table 50. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
[1]
Vx
voltage on pin x
pin V1, V2 (UJA1169TK, UJA1169TK/3,
UJA1169TK/F and UJA1169TK/F/3)
0.3 +6
V
pin VEXT (UJA1169TK/X, UJA1169TK/X/F)
pins TXD, RXD, SDI, SDO, SCK, SCSN, RSTN
pin VEXCC
18
+40
V
0.3 VV1 + 0.3
0.3 +6
V
V
pin WAKE
18
+40
V
pins LIMP, BAT, VEXCTRL
0.3 +40
V
pins CANH and CANL with respect to any other pin
58
-
+58
+20
+40
V
II(LIMP)
input current on pin LIMP LHC = 1
mA
V
V(CANH-CANL) voltage between pin
CANH and pin CANL
40
[2]
[3]
Vtrt
transient voltage
on pins CANL, CANH; WAKE, BAT with application
circuitry; VEXT coupling via 1 nF capacitor
150 +100
V
VESD
electrostatic discharge
voltage
IEC 61000-4-2 (150 pF, 330 )
on pins CANH and CANL; pin BAT with capacitor;
pin WAKE with 10 nF capacitor and 10 k resistor;
pin VEXT with 2.2 F capacitor
6
+6
kV
[4]
[5]
[6]
Human Body Model (HBM); 100 pF, 1.5 k
on pins CANH, CANL
8
4
+8
+4
kV
kV
on pins BAT, LIMP, WAKE, VEXT with application
circuitry
on any other pin
2
+2
kV
[7]
[8]
Charged Device Model (CDM); field Induced charge;
4 pF
on any pin
500 +500
V
Tvj
virtual junction
temperature
40
0
+150
+125
+150
C
C
C
when programming the MTPNV cells
Tstg
storage temperature
55
[1] When the device is not powered up, IV1 (max) = 25 mA.
[2] Verified by an external test house to ensure that pins can withstand ISO 7637 part 2 automotive transient test pulses 1, 2a, 3a and 3b.
[3] According to IEC TS 62228 (2007), Section 4.3; DIN EN 61000-4-2.
[4] According to AEC-Q100-002.
[5] V1 and BAT connected to GND, emulating the application circuit.
[6] Only valid with the external application circuitry connected to these pins shown in Figure 20.
[7] According to AEC-Q100-011 Rev-C1. The classification level is C4B.
[8] In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: Tvj = Tamb + P Rth(j-a), where Rth(j-a) is a
fixed value used in the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient
temperature (Tamb).
UJA1169
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Product data sheet
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Mini high-speed CAN SBC with optional partial networking
9. Thermal characteristics
Table 51. Thermal characteristics
Symbol
Parameter
Conditions
Typ
Unit
[1]
Rth(vj-a)
thermal resistance from virtual junction to ambient HVSON20
33.5
K/W
[1] According to JEDEC JESD51-2, JESD51-5 and JESD51-7 at natural convection on 2s2p board. Board with two inner copper layers
(thickness: 35 m) and thermal via array under the exposed pad connected to the first inner copper layer (thickness: 70 m).
10. Static characteristics
Table 52. Static characteristics
Tvj = 40 C to +150 C; VBAT = 2.8 V to 28 V; VCAN = 4.5 V to 5.5 V; VCAN = VV1 (UJA1169TK/X, UJA1169TK/X/F);
VCAN = VV2 (UJA1169TK, UJA1169TK/3, UJA1169TK/F, UJA1169TK/F/3); R(CANH-CANL) = 60 ; all voltages are defined with
respect to ground; positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supply; pin BAT
IBAT
battery supply current
Sleep mode; MC = 001;
CAN Offline mode; V2/VEXT off;
VBAT = 7 V to 18 V;
-
53
65
A
40 C < Tvj < 50 C;
Standby mode; MC = 100;
CAN Offline mode; V2/VEXT off;
-
-
-
71
8
83
32
81
A
A
A
I
V1 = 0 A; VBAT = 7 V to 18 V;
40 C < Tvj < 50 C
additional current with V2 on
(V2C = 01/10/11);
I
V2 = 0 A; VBAT = 7 V to 18 V;
40 C < Tvj < 85 C
additional current with VEXT on
(VEXTC = 01/10/11);
72
I
VEXT = 0 A; VBAT = 7 V to 18 V;
40 C < Tvj < 85 C
additional current in CAN Offline
Bias mode;
40 C < Tvj < 85 C
-
-
38
55
A
A
additional current when partial
networking enabled; bus active;
CPNC = 1; PNCOK = 1;
300
337
40 C < Tvj < 85 C
additional current from WAKE
input; WPRE = WPFE = 1;
40 C < Tvj < 85 C
-
2
3
A
mA
mA
V
Normal mode; MC = 111;
CAN Active mode; CAN
recessive; VTXD = VV1
-
4
7.5
67
Normal mode; MC = 111;
CAN Active mode; CAN
dominant; VTXD = 0 V
-
46
-
Vth(det)pon
power-on detection threshold
voltage
VBAT rising
4.2
4.55
UJA1169
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Mini high-speed CAN SBC with optional partial networking
Table 52. Static characteristics …continued
Tvj = 40 C to +150 C; VBAT = 2.8 V to 28 V; VCAN = 4.5 V to 5.5 V; VCAN = VV1 (UJA1169TK/X, UJA1169TK/X/F);
CAN = VV2 (UJA1169TK, UJA1169TK/3, UJA1169TK/F, UJA1169TK/F/3); R(CANH-CANL) = 60 ; all voltages are defined with
respect to ground; positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise specified.
V
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Vth(det)poff
power-off detection threshold
voltage
VBAT falling
2.8
-
3
V
Voltage source: pin V1
[1]
VO
output voltage
VO(V1)nom = 5 V;
VBAT = 5.5 V to 28 V;
IV1 = 200 mA to 0 mA
4.9
5
5.1
V
V
V
V
V
VO(V1)nom = 5 V;
4.9
5
5.1
VBAT = 5.65 V to 28 V;
IV1 = 250 mA to 0 mA
VO(V1)nom = 5 V;
-
-
5.5
VBAT below Vth(det)poff and rising;
t tstartup; Tvj 125 C
VO(V1)nom = 3.3 V;
VBAT = 3.834 V to 28 V;
IV1 = 200 mA to 0 mA
3.234
3.234
3.3
3.3
3.366
3.366
VO(V1)nom = 3.3 V;
VBAT = 3.984 V to 28 V;
IV1 = 250 mA to 0 mA
Vret(RAM)
RAM retention voltage
difference
between VBAT and VV1; 5 V
variants only
VBAT = 2 V to 3 V; IV1 = 2 mA
-
-
100
10
mV
mV
[1]
VBAT = 2 V to 3 V;
IV1 = 200 A
RON(BAT-V1)
ON resistance between pin BAT VBAT = 3.25 V to 5.65 V;
and pin V1 IV1 = 250 mA
-
-
-
-
3
VBAT = 2.8 V to 3.25 V;
3.2
IV1 = 250 mA
Vuvd
undervoltage detection voltage 5 V variants
Vuvd(nom) = 90 %
4.5
4
-
-
4.75
4.25
3.75
3.25
V
V
V
V
Vuvd(nom) = 80 %
Vuvd(nom) = 70 %
Vuvd(nom) = 60 %
3.3 V variants
3.5
3
-
Vuvd(nom) = 90 %
5 V variants (90 %)
3.3 V variants (90 %)
VBAT = 5.65 V to 18 V
2.97
4.5
-
-
-
-
-
3.135
4.75
3.135
-
V
Vuvr
undervoltage recovery voltage
V
2.97
214
500
V
Isink
sink current
mA
mA
IO(sc)
short-circuit output current
250
PNP base; pin VEXCTRL
IO(sc)
short-circuit output current
VVEXCTRL 4.5 V;
4.2
5.8
7.5
mA
VBAT = 6 V to 28 V
UJA1169
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Product data sheet
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Mini high-speed CAN SBC with optional partial networking
Table 52. Static characteristics …continued
Tvj = 40 C to +150 C; VBAT = 2.8 V to 28 V; VCAN = 4.5 V to 5.5 V; VCAN = VV1 (UJA1169TK/X, UJA1169TK/X/F);
CAN = VV2 (UJA1169TK, UJA1169TK/3, UJA1169TK/F, UJA1169TK/F/3); R(CANH-CANL) = 60 ; all voltages are defined with
respect to ground; positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise specified.
V
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Ith(act)PNP
PNP activation threshold current load current increasing; external
PNP transistor connected - see
Section 7.5.2
PDC 0
-
-
130
100
80
mA
mA
mA
mA
[1]
[1]
PDC 0; Tvj = 150 C
PDC 1
60
-
83
-
PDC 1; Tvj = 150 C
36
50
59
Ith(deact)PNP
PNP deactivation threshold
current
load current falling; external
PNP transistor connected - see
Section 7.5.2
PDC 0
-
-
70
59
18
17
7.5
mA
mA
mA
mA
V
[1]
[1]
PDC 0; Tvj = 150 C
PDC 1
26
-
44
-
PDC 1; Tvj = 150 C
rising edge on pin BAT
6
11
-
Vth(Ictrl)PNP
PNP current control threshold
voltage
5.9
PNP collector; pin VEXCC
Vth(act)Ilim current limiting activation
threshold voltage
measured across resistor
connected between pins VEXCC
and V1 (see Section 7.5.2);
2 V VV1 5.5 V;
240
-
330
mV
6 V < VBAT < 28 V
Voltage source: V2 (UJA1169TK, UJA1169TK/F, UJA1169TK/3 and UJA1169TK/F/3 only)
VO
output voltage
VBAT = 5.8 V to 28 V;
IV2 = 100 mA to 0 mA
4.9
4.5
5.2
-
5
-
5.1
V
Vth(uvp)
Vth(ovp)
RON(BAT-V2)
IO(sc)
undervoltage protection
threshold voltage
detection and recovery
thresholds
4.75
5.5
V
overvoltage protection threshold detection and recovery
voltage thresholds
-
V
ON resistance between pin BAT VBAT = 4.5 V to 5.8 V;
and pin V2
-
8.7
IV2 = 100 mA to 5 mA
short-circuit output current
250
-
100
mA
Voltage source: VEXT (UJA1169TK/X and UJA1169TK/X/F only)
VO
output voltage
VBAT = 6 V to 28 V;
IVEXT = 100 mA to 0 mA
4.9
4.5
5.2
-
5
-
5.1
V
Vth(uvp)
Vth(ovp)
undervoltage protection
threshold voltage
detection and recovery
thresholds
4.75
5.5
V
overvoltage protection threshold detection and recovery
voltage thresholds
-
V
RON(BAT-VEXT) ON resistance between pin BAT VBAT = 4.5 V to 6 V;
-
11
and pin VEXT
IVEXT = 100 mA to 5 mA
IO(sc)
short-circuit output current
250
-
100
mA
UJA1169
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Product data sheet
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NXP Semiconductors
Mini high-speed CAN SBC with optional partial networking
Table 52. Static characteristics …continued
Tvj = 40 C to +150 C; VBAT = 2.8 V to 28 V; VCAN = 4.5 V to 5.5 V; VCAN = VV1 (UJA1169TK/X, UJA1169TK/X/F);
CAN = VV2 (UJA1169TK, UJA1169TK/3, UJA1169TK/F, UJA1169TK/F/3); R(CANH-CANL) = 60 ; all voltages are defined with
respect to ground; positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise specified.
V
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Limp-home output (LIMP)
VO
ILO
output voltage
ILIMP = 0.8 mA; LHC = 1;
Tvj = 40 C to Tth(act)otp(max)
-
-
-
0.4
+5
V
output leakage current
VLIMP = 0 V to 28 V; LHC = 0
5
A
Serial peripheral interface inputs; pins SDI, SCK and SCSN
Vth(sw)
switching threshold voltage
0.25VV1
0.05VV1
-
-
0.75VV1
-
V
V
Vth(sw)hys
switching threshold voltage
hysteresis
Rpd(SCK)
Rpu(SCSN)
ILI(SDI)
Ci
pull-down resistance on pin SCK
40
40
5
-
60
60
-
80
80
+5
6
k
k
A
pF
pull-up resistance on pin SCSN
input leakage current on pin SDI VSDI = 0 V or VV1
[1]
input capacitance
Vi = VV1
3
Serial peripheral interface data output; pin SDO
VOH
HIGH-level output voltage
IOH = 4 mA
VV1
-
-
V
0.4
VOL
ILO(off)
Co
LOW-level output voltage
IOL = 4 mA
-
-
0.4
+5
6
V
off-state output leakage current VSCSN = VV1; VSDO = 0 V or VV1
5
-
-
A
pF
[1]
output capacitance
SCSN = VV1
3
CAN transmit data input; pin TXD
Vth(sw)
switching threshold voltage
0.25VV1
0.05VV1
-
-
0.75VV1
-
V
V
Vth(sw)hys
switching threshold voltage
hysteresis
Rpu
pull-up resistance
40
60
-
80
-
k
CAN receive data output; pin RXD
VOH
HIGH-level output voltage
IOH = 4 mA
VV1
V
0.4
VOL
Rpu
LOW-level output voltage
pull-up resistance
IOL = 4 mA
-
-
0.4
80
V
CAN Offline mode
40
60
k
Local wake input; pin WAKE
Vth(sw)r rising switching threshold
2.8
2.4
-
-
4.1
V
V
voltage
Vth(sw)f
falling switching threshold
voltage
3.75
Vhys(i)
Ii
input hysteresis voltage
input current
250
-
-
-
800
1.5
mV
Tvj = 40 C to +85 C
A
High-speed CAN-bus lines; pins CANH and CANL
VO(dom)
dominant output voltage
CAN Active mode; VTXD = 0 V
pin CANH
2.75
0.5
3.5
1.5
4.5
V
V
pin CANL
2.25
UJA1169
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Product data sheet
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NXP Semiconductors
Mini high-speed CAN SBC with optional partial networking
Table 52. Static characteristics …continued
Tvj = 40 C to +150 C; VBAT = 2.8 V to 28 V; VCAN = 4.5 V to 5.5 V; VCAN = VV1 (UJA1169TK/X, UJA1169TK/X/F);
CAN = VV2 (UJA1169TK, UJA1169TK/3, UJA1169TK/F, UJA1169TK/F/3); R(CANH-CANL) = 60 ; all voltages are defined with
respect to ground; positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise specified.
V
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Vdom(TX)sym
transmitter dominant voltage
symmetry
Vdom(TX)sym
VCAN VCANH VCANL
=
400
-
+400
mV
;
VCAN = 5 V
[1]
[2]
VTXsym
transmitter voltage symmetry
bus differential output voltage
VTXsym = VCANH + VCANL
fTXD = 250 kHz; CSPLIT = 4.7 nF
;
0.9VCAN
-
1.1VCAN
V
VO(dif)bus
CAN Active mode (dominant);
VTXD = 0 V;
VCAN = 4.75 V to 5.5 V
R(CANH-CANL) = 50 to 65
R(CANH-CANL) = 45 to 65
1.5
1.4
50
-
-
-
3.0
3.0
+50
V
V
CAN Active mode (recessive);
CAN Listen-only mode;
mV
CAN Offline mode; VTXD = VV1
R(CANH-CANL) = no load
;
VO(rec)
recessive output voltage
CAN Active mode; VTXD = VV1
R(CANH-CANL) = no load
2
0.5VCAN
3
V
V
V
CAN Offline mode;
R(CANH-CANL) = no load
0.1
2
-
+0.1
3
CAN Offline Bias/Listen-only
2.5
modes; R(CANH-CANL) = no load
IO(sc)dom
dominant short-circuit output
current
CAN Active mode;
VTXD = 0 V; VCAN = 5 V
pin CANH; VCANH = 3 V
55
-
-
-
-
-
mA
mA
mA
pin CANL; VCANL = +16 V
+55
+3
IO(sc)rec
recessive short-circuit output
current
VCANL = VCANH = 27 V to +32 V;
3
VTXD = VV1
Vth(RX)dif
differential receiver threshold
voltage
CAN Active/Listen-only modes;
12 V < VCANL < +12 V;
12 V < VCANH < +12 V
0.5
0.4
50
0.7
0.7
200
0.9
V
CAN Offline mode;
12 V < VCANL < +12 V;
12 V < VCANH < +12 V
1.15
400
V
Vth(RX)dif(hys) differential receiver threshold
voltage hysteresis
CAN Active/Listen-only modes;
12 V < VCANL < +12 V;
mV
12 V < VCANH < +12 V
Ri(cm)
Ri
common-mode input resistance
input resistance deviation
differential input resistance
9
15
-
28
+1
52
k
%
1
19
Ri(dif)
12 V < VCANL < +12 V;
12 V < VCANH < +12 V
30
k
[1]
[1]
Ci(cm)
common-mode input
capacitance
-
-
20
pF
Ci(dif)
ILI
differential input capacitance
input leakage current
-
-
-
10
+5
pF
VBAT = VCAN = 0 V or VBAT
=
5
A
VCAN = shorted to ground via
47 k; VCANH = VCANL = 5 V
UJA1169
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Product data sheet
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NXP Semiconductors
Mini high-speed CAN SBC with optional partial networking
Table 52. Static characteristics …continued
Tvj = 40 C to +150 C; VBAT = 2.8 V to 28 V; VCAN = 4.5 V to 5.5 V; VCAN = VV1 (UJA1169TK/X, UJA1169TK/X/F);
CAN = VV2 (UJA1169TK, UJA1169TK/3, UJA1169TK/F, UJA1169TK/F/3); R(CANH-CANL) = 60 ; all voltages are defined with
respect to ground; positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise specified.
V
Symbol
Parameter
Conditions
Min
4.2
4.5
4.5
4.5
1
Typ
Max
4.55
4.75
5
Unit
V
Vuvd(CAN)
CAN undervoltage detection
voltage
on pin BAT; VBAT falling
on VCAN; see Section 7.9.3
VBAT rising
-
-
V
Vuvr(CAN)
CAN undervoltage recovery
voltage
-
V
on VCAN; see Section 7.9.3
-
4.75
6
V
[3]
[3]
IDD(CAN)
CAN supply current
CAN Active mode; CAN
recessive; VTXD = VV1
3
mA
CAN Active mode; CAN
dominant; VTXD = 0 V;
R(CANH-CANL) = no load
3
7.5
15
mA
Temperature protection
Tth(act)otp
Tth(rel)otp
Tth(warn)otp
overtemperature protection
activation threshold temperature
167
127
127
177
137
137
187
147
147
C
C
C
overtemperature protection
release threshold temperature
overtemperature protection
warning threshold temperature
Reset output; pin RSTN
VOL
LOW-level output voltage
VV1 = 1.0 V to 5.5 V; pull-up
0
-
0.2VV1
V
resistor to VV1 900
Rpu
pull-up resistance
40
60
-
80
k
V
Vth(sw)
Vth(sw)hys
switching threshold voltage
0.25VV1
0.05VV1
0.75VV1
-
switching threshold voltage
hysteresis
-
V
MTP non-volatile memory
Ncy(W)MTP
number of MTP write cycles
VBAT = 6 V to 28 V;
-
-
200
-
Tvj = 0 C to +125 C
[1] Not tested in production; guaranteed by design.
[2] The test circuit used to measure the bus output voltage symmetry (which includes CSPLIT) is shown in Figure 22.
[3] From V1 in VEXT versions (UJA1169TK/X and UJA1169TK/X/F) and from V2 in other variants.
UJA1169
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Product data sheet
Rev. 1 — 4 February 2016
58 of 74
UJA1169
NXP Semiconductors
Mini high-speed CAN SBC with optional partial networking
11. Dynamic characteristics
Table 53. Dynamic characteristics
Tvj = 40 C to +150 C; VBAT = 2.8 V to 28 V; VCAN = 4.5 V to 5.5 V; VCAN = VV1 (UJA1169TK/X, UJA1169TK/X/F);
CAN = VV2 (UJA1169TK, UJA1169TK/3, UJA1169TK/F, UJA1169TK/F/3); R(CANH-CANL) = 60 ; all voltages are defined with
respect to ground; positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise specified.
V
Symbol
Parameter
Conditions
Min Typ
Max
Unit
Voltage source; pin V1
tstartup
start-up time
from VBAT exceeding the power-on
detection threshold until VV1 exceeds
the 90 % undervoltage threshold;
-
2.8
4.7
ms
CV1 =4.7 F
td(uvd)
undervoltage detection delay
time
VV1 falling
6
-
-
-
54
63
s
s
td(uvd-RSTNL)
delay time from undervoltage undervoltage on V1
detection to RSTN LOW
Voltage source; pin V2 (UJA1169TK, UJA1169TK/F, UJA1169TK/3 and UJA1169TK/F/3)/VEXT(UJA1169TK/X,
UJA1169TK/X/F)
td(uvd)
undervoltage detection delay
time
VV2/VVEXT falling
6
-
32
2.8
32
s
ms
s
at start-up of VV2/VVEXT
VV2/VVEXT falling
2.2
6
2.5
-
td(ovd)
overvoltage detection delay
time
Serial peripheral interface timing; pins SCSN, SCK, SDI and SDO
tcy(clk)
tSPILEAD
tSPILAG
tclk(H)
tclk(L)
clock cycle time
250
50
50
125
125
50
50
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
SPI enable lead time
SPI enable lag time
clock HIGH time
-
-
-
-
-
clock LOW time
-
-
tsu(D)
data input set-up time
data input hold time
data output valid time
chip select pulse width HIGH
SPI time-out time
-
-
th(D)
-
-
tv(Q)
pin SDO; CL = 20 pF
pin SCSN
-
50
-
tWH(S)
tto(SPI)
250
-
-
after leaving Reset mode;
VV1 = 1.0 V to 5.5 V;
RSTN rising edge
--
20
td(SCKL-SCSNL)
delay time from SCK LOW to
SCSN LOW
50
-
-
-
-
ns
ns
CAN transceiver timing; pins CANH, CANL, TXD and RXD
td(TXDL-RXDL)
delay time from TXD LOW to
RXD LOW
VTXD = 30 % VV1 to VRXD = 30 % VV1
CRXD = 15 pF;
fTXD = 250 kHz; R(CANH-CANL) = 60 ;
C(CANH-CANL) = 100 pF;
;
;
255
td(TXDH-RXDH)
delay time from TXD HIGH to VTXD = 70 % VV1 to VRXD = 70 % VV1
RXD HIGH CRXD = 15 pF;
TXD = 250 kHz; R(CANH-CANL) = 60 ;
-
-
255
ns
f
C(CANH-CANL) = 100 pF;
UJA1169
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Product data sheet
Rev. 1 — 4 February 2016
59 of 74
UJA1169
NXP Semiconductors
Mini high-speed CAN SBC with optional partial networking
Table 53. Dynamic characteristics …continued
Tvj = 40 C to +150 C; VBAT = 2.8 V to 28 V; VCAN = 4.5 V to 5.5 V; VCAN = VV1 (UJA1169TK/X, UJA1169TK/X/F);
CAN = VV2 (UJA1169TK, UJA1169TK/3, UJA1169TK/F, UJA1169TK/F/3); R(CANH-CANL) = 60 ; all voltages are defined with
respect to ground; positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise specified.
V
Symbol
Parameter
Conditions
Min Typ
Max
Unit
tbit(RXD)
bit time on pin RXD
tbit(TXD) = 500 ns (see Figure 18);
R(CANH-CANL) = 60 ;
400
-
550
ns
C(CANH-CANL) = 100 pF
td(TXD-busdom)
delay time from TXD to bus
dominant
R(CANH-CANL) = 60 ;
C(CANH-CANL) = 100 pF;
VCANH VCANL = 900 mV
-
-
80
80
105
105
ns
ns
td(TXD-busrec)
delay time from TXD to bus
recessive
R(CANH-CANL) = 60 ;
C(CANH-CANL) = 100 pF;
VCANH VCANL = 500 mV
td(busdom-RXD)
td(busrec-RXD)
twake(busdom)
delay time from bus dominant CRXD = 15 pF; VRXD = 30 % VV1
to RXD
-
105
120
-
-
ns
ns
s
delay time from bus recessive CRXD = 15 pF; VRXD = 70 % VV1
to RXD
;
-
-
bus dominant wake-up time
first pulse (after first recessive) for
0.5
3.0
wake-up on pins CANH and CANL;
CAN Offline mode
second pulse for wake-up on pins
CANH and CANL
0.5
0.5
-
-
3.0
3.0
s
s
twake(busrec)
bus recessive wake-up time
first pulse for wake-up on pins CANH
and CANL;
CAN Offline mode
second pulse (after first dominant) for
wake-up on pins CANH and CANL
0.5
570
2.7
0.95
-
-
-
-
-
-
-
3.0
s
s
ms
s
tto(wake)
wake-up time-out time
between first and second dominant
pulses; CAN Offline mode
1200
3.3
tto(dom)TXD
tto(silence)
td(busact-bias)
tstartup(CAN)
TXD dominant time-out time
bus silence time-out time
CAN Active mode;
VTXD = 0 V
recessive time measurement started
in all CAN modes
1.17
200
220
delay time from bus active to
bias
s
s
CAN start-up time
to CTS = 1; when switching to Active
mode
-
Pin RXD: event capture timing (valid in CAN Offline mode only)
td(event)
tblank
event capture delay time
blanking time
CAN Offline mode
0.9
-
-
-
1.1
25
ms
when switching from Offline to
Active/Listen-only mode
s
Watchdog
[2]
[4]
ttrig(wd)1
watchdog trigger time 1
watchdog trigger time 2
Normal mode; watchdog Window
mode only
0.45
-
-
0.55 ms
N
NWP[3]
WP[3
]
ttrig(wd)2
Normal/Standby mode
0.9
NWP
[3]
1.11 ms
NWP[3]
UJA1169
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Product data sheet
Rev. 1 — 4 February 2016
60 of 74
UJA1169
NXP Semiconductors
Mini high-speed CAN SBC with optional partial networking
Table 53. Dynamic characteristics …continued
Tvj = 40 C to +150 C; VBAT = 2.8 V to 28 V; VCAN = 4.5 V to 5.5 V; VCAN = VV1 (UJA1169TK/X, UJA1169TK/X/F);
CAN = VV2 (UJA1169TK, UJA1169TK/3, UJA1169TK/F, UJA1169TK/F/3); R(CANH-CANL) = 60 ; all voltages are defined with
respect to ground; positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise specified.
V
Symbol
Parameter
Conditions
Min Typ
Max
Unit
Pin RSTN: reset pulse width
tw(rst)
reset pulse width
output pulse width
RLC = 00
20
10
3.6
1
-
-
-
-
-
25
12.5
5
ms
ms
ms
ms
s
RLC = 01
RLC = 10
RLC = 11
1.5
-
input pulse width
18
Pin LIMP
td(limp)
limp delay time
wake-up time
117
50
-
-
-
145
-
ms
s
s
Pin WAKE
twake
MTP non-volatile memory
td(MTPNV)
MTPNV delay time
before factory presets are restored;
VBAT = 6 V to 28 V
0.9
1.1
[1] Not tested in production; guaranteed by design.
[2] A system reset will be performed if the watchdog is in Window mode and is triggered earlier than ttrig(wd)1 after the start of the watchdog
period (thus in the first half of the watchdog period).
[3] The nominal watchdog period is programmed via the NWP control bits.
[4] The watchdog will be reset if it is in window mode and is triggered after ttrig(wd)1, but not later than ttrig(wd)2, after the start of the watchdog
period (thus, in the second half of the watchdog period). If the watchdog is triggered later than ttrig(wd)2 after the start of the watchdog
period (watchdog overflow), a system reset will be performed.
UJA1169
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Product data sheet
Rev. 1 — 4 February 2016
61 of 74
UJA1169
NXP Semiconductors
Mini high-speed CAN SBC with optional partial networking
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Fig 18. Loop delay symmetry timing diagram
UJA1169
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 4 February 2016
62 of 74
UJA1169
NXP Semiconductors
Mini high-speed CAN SBC with optional partial networking
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Fig 19. SPI timing diagram
UJA1169
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© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 4 February 2016
63 of 74
UJA1169
NXP Semiconductors
Mini high-speed CAN SBC with optional partial networking
12. Application information
12.1 Application diagram
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The application diagram contains example components and component values. A PHPT60603PY transistor could be used in
place of the PHPT61003PY.
Fig 20. Typical application using the UJA1169
12.2 Application hints
Further information on the application of the UJA1169 can be found in the NXP application
hints document AH1306 Application Hints - Mini high speed CAN system basis chips
UJA116x / UJA116xA.
UJA1169
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© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 4 February 2016
64 of 74
UJA1169
NXP Semiconductors
Mini high-speed CAN SBC with optional partial networking
13. Test information
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13.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q100 Rev-G - Failure mechanism based stress test qualification for
integrated circuits, and is suitable for use in automotive applications.
UJA1169
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© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 4 February 2016
65 of 74
UJA1169
NXP Semiconductors
Mini high-speed CAN SBC with optional partial networking
14. Package outline
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Fig 23. Package outline SOT1360-1 (HVSON20)
UJA1169
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Product data sheet
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NXP Semiconductors
Mini high-speed CAN SBC with optional partial networking
15. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate precautions are taken as
described in JESD625-A or equivalent standards.
16. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
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• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
16.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 24) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 54 and 55
Table 54. SnPb eutectic process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350
235
350
220
< 2.5
2.5
220
220
Table 55. Lead-free process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 24.
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maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 24. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
17. Soldering of HVSON packages
Section 16 contains a brief introduction to the techniques most commonly used to solder
Surface Mounted Devices (SMD). A more detailed discussion on soldering HVSON
leadless package ICs can be found in the following application notes:
• AN10365 ‘Surface mount reflow soldering description”
• AN10366 “HVQFN application information”
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18. Revision history
Table 56. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
UJA1169 v.1
20160204
Product data sheet
-
-
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19. Legal information
19.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use in automotive applications — This NXP
19.2 Definitions
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
19.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
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No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
20. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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21. Contents
1
General description. . . . . . . . . . . . . . . . . . . . . . 1
7.3.2
7.3.2.1
7.4
Selecting the output reset pulse width . . . . . . 17
Start-up control register (0x73) . . . . . . . . . . . 17
Global temperature protection . . . . . . . . . . . . 17
Power supplies. . . . . . . . . . . . . . . . . . . . . . . . 18
Battery supply voltage (VBAT). . . . . . . . . . . . . 18
Voltage regulator V1 . . . . . . . . . . . . . . . . . . . 18
Voltage regulator V2 . . . . . . . . . . . . . . . . . . . 19
Voltage regulator VEXT . . . . . . . . . . . . . . . . . 20
Regulator control register (0x10) . . . . . . . . . . 20
Supply voltage status register (0x1B) . . . . . . 21
LIMP output . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Reset counter. . . . . . . . . . . . . . . . . . . . . . . . . 21
LIMP state diagram . . . . . . . . . . . . . . . . . . . . 22
Fail-safe control register (0x02) . . . . . . . . . . . 23
High-speed CAN transceiver . . . . . . . . . . . . . 23
CAN operating modes . . . . . . . . . . . . . . . . . . 23
CAN Active mode. . . . . . . . . . . . . . . . . . . . . . 24
CAN Listen-only mode. . . . . . . . . . . . . . . . . . 24
CAN Offline and Offline Bias modes . . . . . . . 24
CAN Off mode . . . . . . . . . . . . . . . . . . . . . . . . 25
CAN standard wake-up (partial networking
not enabled). . . . . . . . . . . . . . . . . . . . . . . . . . 25
CAN control register (0x20) . . . . . . . . . . . . . . 26
Transceiver status register (0x22) . . . . . . . . . 27
CAN partial networking (UJA1169 /F variants
only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Wake-up frame (WUF). . . . . . . . . . . . . . . . . . 28
CAN FD frames . . . . . . . . . . . . . . . . . . . . . . . 30
CAN partial networking configuration
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Data rate register (0x26) . . . . . . . . . . . . . . . . 31
ID registers (0x27 to 0x2A) . . . . . . . . . . . . . . 31
ID mask registers (0x2B to 0x2E) . . . . . . . . . 31
Frame control register (0x2F) . . . . . . . . . . . . 32
Data mask registers (0x68 to 0x6F). . . . . . . . 32
CAN fail-safe features . . . . . . . . . . . . . . . . . . 33
TXD dominant time-out . . . . . . . . . . . . . . . . . 33
Pull-up on TXD pin. . . . . . . . . . . . . . . . . . . . . 33
VCAN undervoltage event . . . . . . . . . . . . . . . . 33
Loss of power at pin BAT. . . . . . . . . . . . . . . . 34
Wake-up and interrupt event handling . . . . . . 34
WAKE pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 2
General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Designed for automotive applications. . . . . . . . 2
Low-drop voltage regulator for 5 V/3.3 V
microcontroller supply (V1). . . . . . . . . . . . . . . . 2
On-board CAN supply (V2; UJA1169TK,
UJA1169TK/F, UJA1169TK/3andUJA1169TK/F/3
only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Off-board sensor supply (VEXT; UJA1169TK/X
and UJA1169TK/X/F only) . . . . . . . . . . . . . . . . 3
Power Management . . . . . . . . . . . . . . . . . . . . . 3
System control and diagnostic features . . . . . . 3
2.1
2.2
2.3
7.5
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
7.6
7.6.1
7.6.2
7.6.2.1
7.7
7.7.1
7.7.1.1
7.7.1.2
7.7.1.3
7.7.1.4
7.7.2
2.4
2.5
2.6
2.7
3
4
5
Product family overview . . . . . . . . . . . . . . . . . . 4
Ordering information. . . . . . . . . . . . . . . . . . . . . 4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 6
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
7
7.1
7.1.1
Functional description . . . . . . . . . . . . . . . . . . . 7
System controller . . . . . . . . . . . . . . . . . . . . . . . 7
Operating modes . . . . . . . . . . . . . . . . . . . . . . . 7
Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 7
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Off mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Overtemp mode . . . . . . . . . . . . . . . . . . . . . . . . 9
Forced Normal mode . . . . . . . . . . . . . . . . . . . 10
Hardware characterization for the UJA1169
operating modes. . . . . . . . . . . . . . . . . . . . . . . 10
System control registers. . . . . . . . . . . . . . . . . 11
Mode control register (0x01). . . . . . . . . . . . . . 11
Main status register (0x03) . . . . . . . . . . . . . . . 11
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Watchdog overview . . . . . . . . . . . . . . . . . . . . 12
Watchdog control register (0x00) . . . . . . . . . . 13
SBC configuration control register (0x74). . . . 13
Watchdog status register (0x05). . . . . . . . . . . 14
Software Development mode . . . . . . . . . . . . . 15
Watchdog behavior in Window mode . . . . . . . 15
Watchdog behavior in Timeout mode . . . . . . . 15
Watchdog behavior in Autonomous mode . . . 15
Exceptional behavior of the watchdog after
7.7.2.1
7.7.2.2
7.8
7.1.1.1
7.1.1.2
7.1.1.3
7.1.1.4
7.1.1.5
7.1.1.6
7.1.1.7
7.1.1.8
7.8.1
7.8.2
7.8.3
7.8.3.1
7.8.3.2
7.8.3.3
7.8.3.4
7.8.3.5
7.9
7.9.1
7.9.2
7.9.3
7.9.4
7.1.2
7.1.2.1
7.1.2.2
7.2
7.2.1
7.2.1.1
7.2.1.2
7.2.1.3
7.2.2
7.2.3
7.2.4
7.10
7.10.1
7.10.1.1 WAKE pin status register (0x4B) . . . . . . . . . . 34
7.10.2
7.10.3
7.10.4
7.10.5
Wake-up diagnosis. . . . . . . . . . . . . . . . . . . . . 34
Interrupt/wake-up delay . . . . . . . . . . . . . . . . . 35
Sleep mode protection. . . . . . . . . . . . . . . . . . 36
Event status and event capture registers. . . . 37
7.2.5
7.2.6
writing to the Watchdog register . . . . . . . . . . . 16
System reset. . . . . . . . . . . . . . . . . . . . . . . . . . 16
Characteristics of pin RSTN . . . . . . . . . . . . . . 16
7.3
7.3.1
7.10.5.1 Event status registers (0x60 to 0x64) . . . . . . 37
continued >>
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Product data sheet
Rev. 1 — 4 February 2016
73 of 74
UJA1169
NXP Semiconductors
Mini high-speed CAN SBC with optional partial networking
7.10.5.2 Event capture enable registers
(0x04, 0x1C, 0x23, 0x4C). . . . . . . . . . . . . . . . 39
Non-volatile SBC configuration. . . . . . . . . . . . 40
Programming MTPNV cells . . . . . . . . . . . . . . 40
7.11
7.11.1
7.11.1.1 MTPNV status register (0x70) . . . . . . . . . . . . 41
7.11.1.2 MTPNV CRC control register (0x75) . . . . . . . 42
7.11.2
7.12
7.12.1
7.13
7.13.1
7.14
7.15
7.15.1
7.15.2
7.15.3
Restoring factory preset values . . . . . . . . . . . 43
Device identification . . . . . . . . . . . . . . . . . . . . 43
Device identification register (0x7E) . . . . . . . . 43
Register locking . . . . . . . . . . . . . . . . . . . . . . . 43
Lock control register (0x0A) . . . . . . . . . . . . . . 43
General-purpose memory. . . . . . . . . . . . . . . . 44
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Register map . . . . . . . . . . . . . . . . . . . . . . . . . 47
Register configuration in UJA1169 operating
modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 52
Thermal characteristics . . . . . . . . . . . . . . . . . 53
Static characteristics. . . . . . . . . . . . . . . . . . . . 53
Dynamic characteristics . . . . . . . . . . . . . . . . . 59
9
10
11
12
12.1
12.2
Application information. . . . . . . . . . . . . . . . . . 64
Application diagram . . . . . . . . . . . . . . . . . . . . 64
Application hints . . . . . . . . . . . . . . . . . . . . . . . 64
13
13.1
14
Test information. . . . . . . . . . . . . . . . . . . . . . . . 65
Quality information . . . . . . . . . . . . . . . . . . . . . 65
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 66
Handling information. . . . . . . . . . . . . . . . . . . . 67
15
16
Soldering of SMD packages . . . . . . . . . . . . . . 67
Introduction to soldering . . . . . . . . . . . . . . . . . 67
Wave and reflow soldering . . . . . . . . . . . . . . . 67
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 67
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 68
16.1
16.2
16.3
16.4
17
18
Soldering of HVSON packages. . . . . . . . . . . . 69
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 70
19
Legal information. . . . . . . . . . . . . . . . . . . . . . . 71
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 71
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 72
19.1
19.2
19.3
19.4
20
21
Contact information. . . . . . . . . . . . . . . . . . . . . 72
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2016.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 4 February 2016
Document identifier: UJA1169
相关型号：
UJA1169TK/3
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ALUMINUM ELECTROLYTIC CAPACITORSWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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UJB0L332THD
ALUMINUM ELECTROLYTIC CAPACITORSWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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NICHICON
UJB0L333THD
ALUMINUM ELECTROLYTIC CAPACITORSWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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