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UM10601

LPC800 User manual

Rev. 1.0 — 7 November 2012

Preliminary user manual

Document information

Info

Content

Keywords

ARM Cortex M0+, LPC800, USART, I2C, LPC810M021FN8,

LPC811M001FDH16, LPC812M101FDH16, LPC812M101FD20,

LPC812M101FDH20

Abstract

LPC800 Preliminary user manual

UM10601

NXP Semiconductors

LPC800 User manual

Revision history

Rev

Date

Description

1

20121107

Preliminary LPC800 user manual

Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

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Chapter 1: LPC800 Introductory information

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Preliminary user manual

1.1 Introduction

The LPC800 are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at

CPU frequencies of up to 30 MHz. The UM10601 support up to 16 kB of flash memory

and 4 kB of SRAM.

The peripheral complement of the UM10601 includes a CRC engine, one I²C-bus

interface, up to three USARTs, up to two SPI interfaces, one multi-rate timer, self wake-up

timer, and state-configurable timer, one comparator, function-configurable I/O ports

through a switch matrix, an input pattern match engine, and up to 18 general-purpose I/O

pins.

1.2 Features

• System:

– ARM Cortex-M0+ processor, running at frequencies of up to 30 MHz.

– ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).

– Micro Trace Buffer

– System tick timer

• Memory:

– 16 kB on-chip flash programming memory.

– 4 kB SRAM.

– In-System Programming (ISP) and In-Application Programming (IAP) via on-chip

boot loader software.

• Boot ROM API support:

– UART drivers

– I2C drivers

– Power profiles

– IAP/ISP

• Digital peripherals:

– High-speed GPIO interface connected to the ARM Cortex-M0+ I/O port with up to

18 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors.

– Pin interrupt generation capability with boolean pattern-matching feature onup to

eightselectable GPIO inputs.

– Switch matrix for flexible configuration of each I/O pin function.

– State Configurable Timer (SCT) with input and output functions (including capture

and match) assigned to pins through the switch matrix.

– Multiple-channel multi-rate timer for repetitive interrupt generation at up to four

programmable, fixed rates.

– Wake-up timer for self-timed wake-up from reduced power modes.

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Chapter 1: LPC800 Introductory information

– CRC engine.

– Windowed Watchdog timer

• Analog peripherals:

– Comparator with external voltage reference with pin functions assigned through

the switch matrix.

– Internal reference voltage.

• Serial interfaces:

– Three UART interfaces with pin functions assigned through the switch matrix.

– Two SPI controllers with pin functions assigned through the switch matrix.

– One I²C-bus interface with open-drain full I2C spec fast Modeplus.

• Clock generation:

– 12 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used

as a system clock.

– Crystal oscillator with an operating range of 1 MHz to 25 MHz.

– Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz.

– PLL allows CPU operation up to the maximum CPU rate without the need for a

high-frequency crystal. May be run from the external clock input (CLKIN), the

system oscillator, or the internal RC oscillator.

• Power control:

– Integrated PMU (Power Management Unit) to minimize power consumption.

– Reduced power modes (Sleep, deep-sleep, power-down, deep power-down).

– Power-On Reset (POR).

– Brownout detect.

• Unique device serial number for identification.

• Single power supply.

• Available in a SO20 package, TSSOP20 package, TSSOP16, and DIP8 package.

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Chapter 1: LPC800 Introductory information

1.3 Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

LPC810M021FN8

DIP8

plastic dual in-line package; 8 leads (300 mil)

SOT097-2

SOT403-1

SOT163-1

SOT360-1

LPC811M001FDH16 TSSOP16

LPC812M101FDH16 TSSOP16

plastic thin shrink small outline package; 16 leads; body width 4.4 mm

plastic small outline package; 20 leads; body width 7.5 mm

plastic thin shrink small outline package; 20 leads; body width 4.4 mm

LPC812M101FD20

SO20

LPC812M101FDH20 TSSOP20

Table 2.

Ordering options

Type number

Flash/kB SRAM/kB USART

I²C

1

SPI Comparator

GPIO

6

Package

LPC810M021FN8

LPC811M001FDH16

LPC812M101FDH16

LPC812M101FD20

LPC812M101FDH20

4

1

2

4

2

3

2

3

1

2

1

2

1

DIP8

8

1

14

TSSOP16

SO20

16

1

14

1

18

1

18

TSSOP20

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Chapter 1: LPC800 Introductory information

1.4 Block diagram

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Fig 1. LPC800 block diagram

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Chapter 1: LPC800 Introductory information

1.5 General description

1.5.1 ARM Cortex-M0+ core configuration

The ARM Cortex-M0+ core runs at an operating frequency of up to 30 MHz. Integrated in

the core are the NVIC and Serial Wire Debug with four breakpoints and two watchpoints.

The ARM Cortex-M0+ core supports a single-cycle I/O enabled port (IOP) for fast GPIO

access at address 0xA000 0000.

The core includes a single-cycle multiplier and a system tick timer (SysTick).

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Chapter 2: LPC800 Memory mapping

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Preliminary user manual

2.1 How to read this chapter

The memory mapping is identical for all LPC800 parts. Different LPC800 parts support

different flash memory sizes.

2.2 General description

The LPC800 incorporates several distinct memory regions. Figure 2 shows the overall

map of the entire address space from the user program viewpoint following reset.

The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals.

Each peripheral is allocated 16 kB of space simplifying the address decoding.

The registers incorporated into the ARM Cortex-M0+ core, such as NVIC, SysTick, and

sleep mode control, are located on the private peripheral bus.

The GPIO port and pin interrupt/pattern match registers are accessed by the ARM

Cortex-M0+ single-cycle I/O enabled port (IOP).

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Chapter 2: LPC800 Memory mapping

2.2.1 Memory mapping

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The private peripheral bus includes the ARM Cortex-M0+ peripherals such as the NVIC, SysTick, and the core control registers.

Fig 2. LPC800 Memory mapping

2.2.2 Micro Trace Buffer (MTB)

The LPC800 supports the ARM Cortex-M0+ Micro Trace Buffer.

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Chapter 3: LPC800 Nested Vectored Interrupt Controller

(NVIC)

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Preliminary user manual

3.1 How to read this chapter

The NVIC is identical on all LPC800 parts.

The SPI1 and USART2 interrupts are implemented on parts LPC812M101FDH20 and

LPC812M101FDH16 only.

3.2 Features

• Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M0+.

• Tightly coupled interrupt controller provides low interrupt latency.

• Controls system exceptions and peripheral interrupts.

• The NVIC supports 32 vectored interrupts.

• Four programmable interrupt priority levels with hardware priority level masking.

• Software interrupt generation using the ARM exceptions SVCall and PendSV.

• Support for NMI.

• ARM Cortex M0+ Vector table offset register VTOR implemented.

3.3 General description

The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0+. The

tight coupling to the CPU allows for low interrupt latency and efficient processing of late

arriving interrupts.

3.3.1 Interrupt sources

Table 3 lists the interrupt sources for each peripheral function. Each peripheral device

may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may

represent more than one interrupt source. The interrupt number does not imply any

interrupt priority.

See Ref. 1 for a detailed description of the NVIC and the NVIC register description.

Table 3.

Connection of interrupt sources to the NVIC

Interrupt

number

Name

Description

Flags

0

SPI0_IRQ

SPI0 interrupt

See Table 192 “SPI Interrupt Enable read and Set register

(INTENSET, addresses 0x4005 800C (SPI0) , 0x4005 C00C

(SPI1)) bit description”.

1

2

SPI1_IRQ

-

SPI1 interrupt

Reserved

Same as SPI0_IRQ

-

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Chapter 3: LPC800 Nested Vectored Interrupt Controller (NVIC)

Table 3.

Connection of interrupt sources to the NVIC

Interrupt

number

Name

Description

Flags

3

UART0_IRQ

USART0 interrupt

See Table 161 “USART Interrupt Enable read and set register

(INTENSET, address 0x4006 400C(USART0), 0x4006 800C

(USART1), 0x4006 C00C(USART2)) bit description”

4

5

6

7

8

UART1_IRQ

USART1 interrupt

USART2 interrupt

Reserved

Same as UART0_IRQ

UART2_IRQ

Same as UART0_IRQ

-

Reserved

I2C0_IRQ

I2C0 interrupt

See Table 175 “Interrupt Enable Clear register (INTENCLR,

address 0x4005 000C) bit description”.

9

SCT_IRQ

MRT_IRQ

State configurable timer

interrupt

EVFLAG SCT event

10

Multi-rate timer interrupt

Global MRT interrupt.

GFLAG0

GFLAG1

GFLAG2

GFLAG3

11

12

CMP_IRQ

WDT_IRQ

Analog comparator interrupt COMPEDGE - rising, falling, or both edges can set the bit

Windowed watchdog timer

interrupt

WARNINT - watchdog warning interrupt

13

BOD_IRQ

FLASH_IRQ

WKT_IRQ

-

BOD interrupts

Flash interrupt

BODINTVAL - BOD interrupt level

<tbd>

14

15

Self wake-up timer interrupt ALARMFLAG

23:16

24

Reserved

-

PININT0_IRQ

Pin interrupt 0 or pattern

match engine slice 0

interrupt

PSTAT - pin interrupt status

25

26

27

28

PININT1_IRQ

PININT2_IRQ

PININT3_IRQ

PININT4_IRQ

Pin interrupt 1 or pattern

match engine slice 1

interrupt

PSTAT - pin interrupt status

Pin interrupt 2 or pattern

match engine slice 2

interrupt

Pin interrupt 3 or pattern

match engine slice 3

interrupt

Pin interrupt 4 or pattern

match engine slice 4

interrupt

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Chapter 3: LPC800 Nested Vectored Interrupt Controller (NVIC)

Table 3.

Connection of interrupt sources to the NVIC

Interrupt

number

Name

Description

Flags

29

30

31

PININT5_IRQ

Pin interrupt 5 or pattern

match engine slice 5

interrupt

PSTAT - pin interrupt status

PININT6_IRQ

PININT7_IRQ

Pin interrupt 6 or pattern

match engine slice 6

interrupt

Pin interrupt 7 or pattern

match engine slice 7

interrupt

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Chapter 4: LPC800 System configuration (SYSCON)

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4.1 How to read this chapter

The system configuration block is identical for all LPC800 parts. USART2 and SPI1 are

only available on parts LPC812M101FDH20 and LPC812M101FDH16 and the corresponding

clocks, reset, and wake-up control bits are reserved for all other parts.

4.2 Features

• Clock control

• Reset control

• Pin interrupt set-up

• Configuration of reduced power modes

• Wake-up control

• BOD configuration

4.3 Basic configuration

Configure the SYSCON block as follows:

• The SYSCON uses the CKIN, CLKOUT, RESET, and XTALIN/OUT pins. Configure

the pin functions through the switch matrix. See Section 4.4.

• No clock configuration is needed. The clock to the SYSCON block is always enabled.

By default, the SYSCON block is clocked by the IRC.

4.3.1 Set up the PLL

The PLL creates a stable output clock at a higher frequency than the input clock. If you

need a main clock with a frequency higher than the 12 MHz IRC clock, use the PLL to

boost the input frequency.

1. Power up the system PLL in the PDRUNCFG register.

Section 4.6.32 “Power configuration register”

2. Select the PLL input in the SYSPLLCLKSEL register. You have the following input

options:

– IRC: 12 MHz internal oscillator.

– System oscillator: External crystal oscillator using the XTALIN/XTALOUT pins.

– External clock input CLKIN. Select this pin through the switch matrix.

Section 4.6.8 “System PLL clock source select register”

3. Update the PLL clock source<tbd> in the SYSPLLCKUEN register.

Section 4.6.9 “System PLL clock source update register”

4. Configure the PLL M and N dividers.

Section 4.6.3 “System PLL control register”

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5. Wait for the PLL to lock by monitoring the PLL lock status.

Section 4.6.4 “System PLL status register”

4.3.2 Configure the main clock and system clock

The clock source for the registers and memories is derived from main clock. The main

clock can be sourced from the IRC at a fixed clock frequency of 12 MHz or from the PLL.

The divided main clock is called the system clock and clocks the core, the memories, and

the peripherals (register interfaces and peripheral clocks).

1. Select the main clock . You have the following options:

– IRC: 12 MHz internal oscillator (default).

– PLL output: You must configure the PLL to use the PLL output.

Section 4.6.10 “Main clock source select register”

2. Update the main clock source.

Section 4.6.11 “Main clock source update enable register”

3. Select the divider value for the system clock. A divider value of 0 disables the system

clock.

Section 4.6.12 “System clock divider register”

4. Select the memories and peripherals that are operating in your application and

therefore must have an active clock. The core is always clocked.

Section 4.6.13 “System clock control register”

4.3.3 Set up the system oscillator using XTALIN and XTALOUT

If you want to use the system oscillator with the LPC800, you need to assign the XTALIN

and XTALOUT pins, which connect to the external crystal, through the fixed-pin function in

the switch matrix. XTALIN and XTALOUT can only be assigned to pins PIO0_8 and

PIO0_9.

1. In the IOCON block, remove the pull-up and pull-down resistors in the IOCON

registers for pins PIO0_8 and PIO0_9.

2. In the switch matrix block, enable the 1-bit functions for XTALIN and XTALOUT.

3. In the SYSOSCCTRL register, disable the BYPASS bit and select the oscillator

frequency range according to the desired oscillator output clock.

Related registers:

Table 62 “PIO0_8 register (PIO0_8, address 0x4004 4038) bit description”

Table 61 “PIO0_9 register (PIO0_9, address 0x4004 4034) bit description”

Table 105 “Pin enable register 0 (PINENABLE0, address 0x4000 C1C0) bit description”

Table 10 “System oscillator control register (SYSOSCCTRL, address 0x4004 8020) bit

description”

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4.4 Pin description

The SYSCON inputs and outputs are assigned to external pins through the switch matrix.

See Section 9.3.1 “Connect an internal signal to a package pin” to assign the CLKOUT

function to a pin on the LPC800 package.

See Section 9.3.2 to enable the clock input, the oscillator pins, and the external reset

input.

Table 4.

SYSCON pin description

Function Direction Pin

Description

SWM register

PINASSIGN8

PINENABLE0

Reference

Table 104

Table 105

CLKOUT

CLKIN

O

I

any

CLKOUT clock output.

PIO0_1/ACMP_I2/CLKIN External clock input to the system

PLL. Disable the ACMP_I2 function

in the PINENABLE register.

XTALIN

I

PIO0_8/XTALIN

PIO0_9/XTALOUT

RESET/PIO0_5

Input to the system oscillator.

Output from the system oscillator.

External reset input

PINENABLE0

Table 105

XTALOUT O

RESET

I

4.5 General description

4.5.1 Clock generation

The system control block facilitates the clock generation. Except for the USART clock and

the clock to configure the glitch filters of the digital I/O pins, the clocks to the core and

peripherals run at the same frequency. The maximum clock frequency for LPC800 is 30

MHz. See Figure 3.

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Fig 3. LPC800 clock generation

4.5.2 Power control of analog components

The system control block controls the power to the analog components such as the

oscillators and PLL, the BOD, and the analog comparator. For details, see the following

registers:

Section 4.6.30 “Deep-sleep mode configuration register”

Section 4.6.3 “System PLL control register”

Section 4.6.6 “Watchdog oscillator control register”

Section 4.6.5 “System oscillator control register”

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4.5.3 Configuration of reduced power-modes

The system control block configures analog blocks that can remain running in the reduced

power modes (the BOD and the watchdog oscillator for safe operation) and enables

various interrupts to wake up the chip when the internal clocks are shut down in

Deep-sleep and Power-down modes. For details, see the following registers:

Section 4.6.32 “Power configuration register”

Section 4.6.29 “Start logic 1 interrupt wake-up enable register”

4.5.4 Reset and interrupt control

The peripheral reset control register in the system control register allows to assert and

release individual peripheral resets. See Table 7.

Up to eight external pin interrupts can be assigned to any digital pin in the system control

block (see Section 4.6.27 “Pin interrupt select registers”).

4.6 Register description

All system control block registers reside on word address boundaries. Details of the

registers appear in the description of each function.

Reset values describe the content of the registers after the boot loader has executed.

All address offsets not shown in Table 5 are reserved and should not be written.

Register overview: System configuration (base address 0x4004 8000)

Table 5.

Name

Access Offset

Description

Reset value

Reference

Table 6

Table 7

Table 8

Table 9

-

SYSMEMREMAP

PRESETCTRL

SYSPLLCTRL

SYSPLLSTAT

-

R/W

R

0x000

0x004

0x008

0x00C

0x010

0x014

0x020

0x024

0x028

0x02C

0x030

0x040

0x044

0x070

0x074

0x078

0x080

0x094

0x098

System memory remap

Peripheral reset control

System PLL control

System PLL status

0x2

0x0000 1FFF

0

-

Reserved

-

Reserved

-

SYSOSCCTRL

WDTOSCCTRL

-

R/W

-

System oscillator control

Watchdog oscillator control

Reserved

0x000

Table 10

Table 11

-

0x0A0

-

Reserved

-

SYSRSTSTAT

SYSPLLCLKSEL

SYSPLLCLKUEN

MAINCLKSEL

MAINCLKUEN

SYSAHBCLKDIV

SYSAHBCLKCTRL

UARTCLKDIV

-

R/W

-

System reset status register

System PLL clock source select

System PLL clock source update enable

Main clock source select

Main clock source update enable

System clock divider

System clock control

USART clock divider

Reserved

0

Table 12

Table 13

Table 14

Table 15

Table 16

Table 17

Table 18

Table 19

-

0

1

0x1F

0

-

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Table 5.

Register overview: System configuration (base address 0x4004 8000) …continued

Name

Access Offset

Description

Reserved

Reset value

Reference

-

0x09C

-

0x0A0 -

0x0BC

-

0x0CC

0x0E0

0x0E4

0x0E8

0x0F0

0x0F4

0x0FC

0x100

0x104

0x134

Reserved

-

CLKOUTSEL

CLKOUTUEN

CLKOUTDIV

UARTFRGDIV

UARTFRGMULT

EXTTRACECMD

PIOPORCAP0

-

R/W

R

CLKOUT clock source select

CLKOUT clock source update enable

CLKOUT clock divider

0

Table 20

Table 21

Table 22

Table 23

Table 24

Table 25

USART fractional generator divider value

USART fractional generator multiplier value

External trace buffer command register

POR captured PIO status 0

Reserved

user dependent Table 26

-

IOCONCLKDIV6

R/W

Peripheral clock 6 to the IOCON block for

programmable glitch filter

0x0000 0000

Table 27

IOCONCLKDIV5

IOCONCLKDIV4

IOCONCLKDIV3

IOCONCLKDIV2

IOCONCLKDIV1

IOCONCLKDIV0

R/W

0x138

0x13C

0x140

0x144

0x148

0x14C

Peripheral clock 5 to the IOCON block for

programmable glitch filter

0x0000 0000

Table 27

Peripheral clock 4 to the IOCON block for

programmable glitch filter

Peripheral clock 3 to the IOCON block for

programmable glitch filter

Peripheral clock 2 to the IOCON block for

programmable glitch filter

Peripheral clock 1 to the IOCON block for

programmable glitch filter

Peripheral clock 0 to the IOCON block for

programmable glitch filter

BODCTRL

SYSTCKCAL

-

R/W

0x150

0x154

0x168

0x170

Brown-Out Detect

System tick counter calibration

Reserved

0

Table 28

Table 29

-

0x0

-

IRQLATENCY

IQR delay. Allows trade-off between interrupt 0x0000 0010

latency and determinism.

Table 30

NMISRC

R/W

0x174

0x178

0x17C

0x180

0x184

0x188

0x18C

0x190

0x194

0x204

0x214

NMI Source Control

0

Table 31

Table 32

Table 33

Table 34

PINTSEL0

PINTSEL1

PINTSEL2

PINTSEL3

PINTSEL4

PINTSEL5

PINTSEL6

PINTSEL7

STARTERP0

STARTERP1

GPIO Pin Interrupt Select register 0

GPIO Pin Interrupt Select register 1

GPIO Pin Interrupt Select register 2

GPIO Pin Interrupt Select register 3

GPIO Pin Interrupt Select register 4

GPIO Pin Interrupt Select register 5

GPIO Pin Interrupt Select register 6

GPIO Pin Interrupt Select register 7

Start logic 0 pin wake-up enable register

Start logic 1 interrupt wake-up enable

register

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Table 5.

Register overview: System configuration (base address 0x4004 8000) …continued

Name

Access Offset

Description

Reset value

0xFFFF

Reference

Table 35

Table 36

PDSLEEPCFG

PDAWAKECFG

R/W

0x230

0x234

Power-down states in deep-sleep mode

Power-down states for wake-up from

deep-sleep

0xEDF0

PDRUNCFG

DEVICE_ID

R/W

R

0x238

0x3F4

Power configuration register

Device ID

0xEDF0

Table 37

part dependent Table 38

4.6.1 System memory remap register

The system memory remap register selects whether the exception vectors are read from

boot ROM, flash, or SRAM. By default, the flash memory is mapped to address 0x0000

0000. When the MAP bits in the SYSMEMREMAP register are set to 0x0 or 0x1, the boot

ROM or RAM respectively are mapped to the bottom 512 bytes of the memory map

(addresses 0x0000 0000 to 0x0000 0200).

Table 6.

System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit

description

Bit

Symbol Value Description

Reset

value

1:0

MAP System memory remap. Value 0x3 is reserved.

0x2

0x0

0x1

0x2

-

Boot Loader Mode. Interrupt vectors are re-mapped to Boot

ROM.

User RAM Mode. Interrupt vectors are re-mapped to Static

RAM.

User Flash Mode. Interrupt vectors are not re-mapped and

reside in Flash.

31:2

-

Reserved

-

4.6.2 Peripheral reset control register

The PRESETCTRL register allows software to reset specific peripherals. A zero in any

assigned bit in this register resets the specified peripheral. A 1 clears the reset and allows

the peripheral to operate.

Table 7.

Peripheral reset control register (PRESETCTRL, address 0x4004 8004) bit

description

Bit

Symbol

Value Description

Reset

value

0

SPI0_RST_N

SPI0 reset control

1

0

1

Assert the SPI0 reset.

Clear the SPI0 reset.

SPI1 reset control

1

2

SPI1_RST_N

0

1

Assert the SPI1 reset.

Clear the SPI1 reset.

UARTFRG_RST_N

USART fractional baud rate generator

(UARTFRG) reset control

0

1

Assert the UARTFRG reset.

Clear the UARTFRG reset.

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Table 7.

Peripheral reset control register (PRESETCTRL, address 0x4004 8004) bit

description

Bit

Symbol

Value Description

Reset

value

3

USART0_RST_N

USART0 reset control

1

-

0

1

Assert the USART0 reset.

Clear the USART0 reset.

USART1 reset control

4

UART1_RST_N

UART2_RST_N

I2C_RST_N

MRT_RST_N

SCT_RST_N

WKT_RST_N

GPIO_RST_N

FLASH_RST_N

ACMP_RST_N

-

0

1

Assert the USART reset.

Clear the USART1 reset.

USART2 reset control

5

0

1

Assert the USART2 reset.

Clear the USART2 reset.

I2C reset control

6

0

1

Assert the I2C reset.

Clear the I2C reset.

7

Multi-rate timer (MRT) reset control

Assert the MRT reset.

0

1

Clear the MRT reset.

8

SCT reset control

0

1

Assert the SCT reset.

Clear the SCT reset.

9

Self wake-up timer (WKT) reset control

Assert the WKT reset.

0

1

Clear the WKT reset.

10

11

12

31:12

GPIO and GPIO pin interrupt reset control

Assert the GPIO reset.

0

1

Clear the GPIO reset.

Flash controller reset control

Assert the flash controller reset.

Clear the flash controller reset.

Analog comparator reset control

Assert the analog comparator reset.

Clear the analog comparator controller reset.

Reserved

0

1

0

1

-

4.6.3 System PLL control register

This register connects and enables the system PLL and configures the PLL multiplier and

divider values. The PLL accepts an input frequency from 10 MHz to 25 MHz from various

clock sources. The input frequency is multiplied to a higher frequency and then divided

down to provide the actual clock used by the CPU, peripherals, and memories. The PLL

can produce a clock up to the maximum allowed for the CPU.

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Table 8.

System PLL control register (SYSPLLCTRL, address 0x4004 8008) bit description

Bit

Symbol Value Description

Reset

value

4:0

MSEL

Feedback divider value. The division value M is the

0

programmed MSEL value + 1.

00000: Division ratio M = 1

to

11111: Division ratio M = 32

6:5

PSEL

Post divider ratio P. The division ratio is 2  P.

0x0

0x1

0x2

0x3

-

P = 1

P = 2

P = 4

P = 8

31:7

-

Reserved. Do not write ones to reserved bits.

-

4.6.4 System PLL status register

This register is a Read-only register and supplies the PLL lock status (see <tbd>).

Table 9.

Bit

System PLL status register (SYSPLLSTAT, address 0x4004 800C) bit description

Symbol Value Description

Reset

value

0

LOCK

PLL lock status

PLL not locked

PLL locked

0

-

0

1

-

31:1

-

Reserved

4.6.5 System oscillator control register

This register configures the frequency range for the system oscillator.

Table 10. System oscillator control register (SYSOSCCTRL, address 0x4004 8020) bit

description

Bit

Symbol

Value Description

Reset

value

0

BYPASS

Bypass system oscillator

0x0

0

1

Disabled. Oscillator is not bypassed.

Enabled. PLL input (sys_osc_clk) is fed directly

from the XTALIN pin bypassing the oscillator. Use

this mode when using an external clock source

instead of the crystal oscillator.

1

FREQRANGE

Determines frequency range for Low-power

oscillator.

0x0

0

1

-

1 - 20 MHz frequency range.

15 - 25 MHz frequency range

Reserved

31:2

-

0x00

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4.6.6 Watchdog oscillator control register

This register configures the watchdog oscillator. The oscillator consists of an analog and a

digital part. The analog part contains the oscillator function and generates an analog clock

(Fclkana). With the digital part, the analog output clock (Fclkana) can be divided to the

required output clock frequency wdt_osc_clk. The analog output frequency (Fclkana) can

be adjusted with the FREQSEL bits between 600 kHz and 4.6 MHz. With the digital part

Fclkana will be divided (divider ratios = 2, 4,...,64) to wdt_osc_clk using the DIVSEL bits.

The output clock frequency of the watchdog oscillator can be calculated as

wdt_osc_clk = Fclkana/(2  (1 + DIVSEL)) = 9.3 kHz to 2.3 MHz (nominal values).

Remark: Any setting of the FREQSEL bits will yield a Fclkana value within 40% of the

listed frequency value. The watchdog oscillator is the clock source with the lowest power

consumption. If accurate timing is required, use the IRC or system oscillator.

Remark: The frequency of the watchdog oscillator is undefined after reset. The watchdog

oscillator frequency must be programmed by writing to the WDTOSCCTRL register before

using the watchdog oscillator.

Table 11. Watchdog oscillator control register (WDTOSCCTRL, address 0x4004 8024) bit

description

Bit

Symbol

Value Description

Reset

value

4:0

DIVSEL

Select divider for Fclkana.

0

wdt_osc_clk = Fclkana/ (2  (1 + DIVSEL))

00000: 2  (1 + DIVSEL) = 2

00001: 2  (1 + DIVSEL) = 4

to

11111: 2  (1 + DIVSEL) = 64

8:5

FREQSEL

Select watchdog oscillator analog output frequency

(Fclkana).

0x00

0x1

0x2

0x3

0x4

0x5

0x6

0x7

0x8

0x9

0xA

0xB

0xC

0xD

0xE

0xF

-

0.6 MHz

1.05 MHz

1.4 MHz

1.75 MHz

2.1 MHz

2.4 MHz

2.7 MHz

3.0 MHz

3.25 MHz

3.5 MHz

3.75 MHz

4.0 MHz

4.2 MHz

4.4 MHz

4.6 MHz

Reserved

31:9

-

0x00

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4.6.7 System reset status register

The SYSRSTSTAT register shows the source of the latest reset event. The bits are

cleared by writing a one to any of the bits. The POR event clears all other bits in this

register. If another reset signal - for example the external RESET pin - remains asserted

after the POR signal is negated, then its bit is set to detected. Write a one to clear the

reset.

The reset value given in Table 12 applies to the POR reset.

Table 12. System reset status register (SYSRSTSTAT, address 0x4004 8030) bit description

Bit

Symbol

Value Description

Reset

value

0

POR

POR reset status

0

-

0

1

No POR detected

POR detected. Writing a one clears this reset.

Status of the external RESET pin. External reset status.

No reset event detected.

1

EXTRST

WDT

0

1

Reset detected. Writing a one clears this reset.

Status of the Watchdog reset

2

0

1

No WDT reset detected

WDT reset detected. Writing a one clears this reset.

Status of the Brown-out detect reset

No BOD reset detected

3

BOD

0

1

BOD reset detected. Writing a one clears this reset.

Status of the software system reset

No System reset detected

4

SYSRST

0

1

-

System reset detected. Writing a one clears this reset.

Reserved

31:5

-

4.6.8 System PLL clock source select register

This register selects the clock source for the system PLL. The SYSPLLCLKUEN register

(see Section 4.6.9) must be toggled from LOW to HIGH for the update to take effect.

Table 13. System PLL clock source select register (SYSPLLCLKSEL, address 0x4004 8040)

bit description

Bit

Symbol Value Description

Reset

value

1:0

SEL System PLL clock source

0

0x0

0x1

0x2

0x3

-

IRC

Crystal Oscillator (SYSOSC)

Reserved.

CLKIN. External clock input.

Reserved

31:2

-

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4.6.9 System PLL clock source update register

This register updates the clock source of the system PLL with the new input clock after the

SYSPLLCLKSEL register has been written to. In order for the update to take effect, first

write a zero to the SYSPLLUEN register and then write a one to SYSPLLUEN.

Table 14. System PLL clock source update enable register (SYSPLLCLKUEN, address

0x4004 8044) bit description

Bit

Symbol

Value Description

Enable system PLL clock source update

No change

Reset value

0

ENA

0

1

-

Update clock source

Reserved

31:1

-

4.6.10 Main clock source select register

This register selects the main system clock, which can be the system PLL (sys_pllclkout),

or the watchdog oscillator, or the IRC oscillator. The main system clock clocks the core,

the peripherals, and the memories.

Bit 0 of the MAINCLKUEN register (see Section 4.6.11) must be toggled from 0 to 1 for the

update to take effect.

Table 15. Main clock source select register (MAINCLKSEL, address 0x4004 8070) bit

description

Bit

Symbol Value Description

SEL Clock source for main clock

Reset value

1:0

0

0x0

0x1

0x2

0x3

-

IRC Oscillator

PLL input

Watchdog oscillator

PLL output

31:2

-

Reserved

-

4.6.11 Main clock source update enable register

This register updates the clock source of the main clock with the new input clock after the

MAINCLKSEL register has been written to. In order for the update to take effect, first write

a zero to bit 0 of this register, then write a one.

Table 16. Main clock source update enable register (MAINCLKUEN, address 0x4004 8074)

bit description

Bit

Symbol

Value Description

Enable main clock source update

No change

Reset value

0

ENA

0

1

-

Update clock source

Reserved

31:1

-

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4.6.12 System clock divider register

This register controls how the main clock is divided to provide the system clock to the

core, memories, and the peripherals. The system clock can be shut down completely by

setting the DIV field to zero.

Table 17. System clock divider register (SYSAHBCLKDIV, address 0x4004 8078) bit

description

Bit

Symbol Description

Reset

value

7:0

DIV System AHB clock divider values

0x01

0: System clock disabled.

1: Divide by 1.

to

255: Divide by 255.

31:8

-

Reserved

-

4.6.13 System clock control register

The SYSAHBCLKCTRL register enables the clocks to individual system and peripheral

blocks. The system clock (bit 0) provides the clock for the AHB, the APB bridge, the ARM

Cortex-M0+, the SYSCON block, and the PMU. This clock cannot be disabled.

Table 18. System clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit

description

Bit

Symbol

Value Description

Reset

value

0

SYS

Enables the clock for the AHB, the APB bridge, the

1

Cortex-M0+ core clocks, SYSCON, and the PMU.

This bit is read only and always reads as 1.

0

1

Reserved

Enable

1

2

3

4

5

ROM

Enables clock for ROM.

1

0

1

Disable

Enable

RAM

Enables clock for SRAM.

0

1

Disable

Enable

FLASHREG

FLASH

I2C

Enables clock for flash register interface.

0

1

Disable

Enable

Enables clock for flash.

Disable

0

1

Enable

Enables clock for I2C.

Disable

0

1

Enable

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Table 18. System clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit

description …continued

Bit

Symbol

Value Description

Enables clock for GPIO port registers and GPIO pin

Reset

value

6

GPIO

0

interrupt registers.

0

1

Disable

Enable

7

SWM

SCT

Enables clock for switch matrix.

0

1

Disable

Enable

8

Enables clock for state configurable timer.

0

1

Disable

Enable

9

WKT

Enables clock for self wake-up timer.

0

1

Disable

Enable

10

11

12

13

14

15

16

17

18

MRT

Enables clock for multi-rate timer.

0

1

Disable

Enable

SPI0

Enables clock for SPI0.

0

1

Disable

Enable

SPI1

Enables clock for SPI1.

0

1

Disable

Enable

CRC

Enables clock for CRC.

0

1

Disable

Enable

UART0

UART1

UART2

WWDT

IOCON

Enables clock for USART0.

0

1

Disable

Enable

Enables clock for USART1.

0

1

Disable

Enable

Enables clock for USART2.

0

1

Disable

Enable

Enables clock for WWDT.

0

1

Disable

Enable

Enables clock for IOCON block.

0

1

Disable

Enable

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Table 18. System clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit

description …continued

Bit

Symbol

Value Description

Reset

value

19

ACMP

Enables clock to analog comparator.

Disable

0

1

-

Enable

31:20

-

Reserved

-

4.6.14 USART clock divider register

This register configures the clock for the fractional baud rate generator and all USARTs.

The UART clock can be disabled by setting the DIV field to zero (this is the default

setting).

Table 19. USART clock divider register (UARTCLKDIV, address 0x4004 8094) bit description

Bit

Symbol Description

Reset

value

7:0

DIV USART clock divider values.

0

-

0: Clock disabled.

1: Divide by 1.

to

255: Divide by 255.

31:8

-

Reserved

4.6.15 CLKOUT clock source select register

This register selects the signal visible on the CLKOUT pin. Any oscillator or the main clock

can be selected.

Bit 0 of the CLKOUTUEN register (see Section 4.6.16) must be toggled from 0 to 1 for the

update to take effect.

Table 20. CLKOUT clock source select register (CLKOUTSEL, address 0x4004 80E0) bit

description

Bit

Symbol Value Description

Reset

value

1:0

SEL CLKOUT clock source

0

0x0

0x1

0x2

0x3

-

IRC oscillator

Crystal oscillator (SYSOSC)

Watchdog oscillator

Main clock

31:2

-

Reserved

0

4.6.16 CLKOUT clock source update enable register

This register updates the clock source of the CLKOUT pin with the new clock after the

CLKOUTSEL register has been written to. In order for the update to take effect at the input

of the CLKOUT pin, first write a zero to bit 0 of this register, then write a one.

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Table 21. CLKOUT clock source update enable register (CLKOUTUEN, address 0x4004

80E4) bit description

Bit

Symbol

Value Description

Enable CLKOUT clock source update

No change

Reset value

0

ENA

0

1

-

Update clock source

Reserved

31:1

-

4.6.17 CLKOUT clock divider register

This register determines the divider value for the signal on the CLKOUT pin.

Table 22. CLKOUT clock divider registers (CLKOUTDIV, address 0x4004 80E8) bit

description

Bit

Symbol Description

Reset

value

7:0

DIV CLKOUT clock divider values

0

0: Disable CLKOUT clock divider.

1: Divide by 1.

to

255: Divide by 255.

31:8

-

Reserved

-

4.6.18 USART fractional generator divider value register

All USART peripherals share a common clock U_PCLK, which can be adjusted by a

fractional divider:

U_PCLK = UARTCLKDIV/(1 + MULT/DIV).

UARTCLKDIV is the USART clock configured in the UARTCLKDIV register.

The fractional portion (1 + MULT/DIV) is determined by the two USART fractional divider

registers in the SYSCON block:

1. The DIV value programmed in this register is the denominator of the divider used by

the fractional rate generator to create the fractional component of U_PCLK.

2. The MULT value of the fractional divider is programmed in the UARTFRGMULT

register. See Table 24.

Remark: To use of the fractional baud rate generator, you must write 0xFF to this register

to yield a denominator value of 256. All other values are not supported.

Related links:

Section 8.7.2

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8.6 Register description

Table 79. Register overview: Pin interrupts/pattern match engine (base address: 0xA000

4000)

Name

Access Address Description

offset

Reset Reference

value

ISEL

R/W

0x000

0x004

Pin Interrupt Mode register

0

Table 80

Table 81

IENR

Pin interrupt level or rising edge interrupt

enable register

SIENR

CIENR

IENF

WO

R/W

WO

0x008

0x00C

0x010

0x014

0x018

Pin interrupt level or rising edge interrupt NA

set register

Table 82

Table 83

Table 84

Table 85

Table 86

Pin interrupt level (rising edge interrupt)

clear register

NA

Pin interrupt active level or falling edge

interrupt enable register

0

SIENF

CIENF

Pin interrupt active level or falling edge

interrupt set register

NA

Pin interrupt active level or falling edge

interrupt clear register

RISE

R/W

0x01C

0x020

0x024

0x028

0x02C

Pin interrupt rising edge register

Pin interrupt falling edge register

Pin interrupt status register

0

Table 87

Table 88

Table 89

Table 90

Table 91

FALL

IST

PMCTRL

PMSRC

Pattern match interrupt control register

Pattern match interrupt bit-slice source

register

PMCFG

R/W

0x030

Pattern match interrupt bit slice

configuration register

0

Table 92

8.6.1 Pin interrupt mode register

For each of the 8 pin interrupts selected in the PINTSELn registers (see Section 4.6.27),

one bit in the ISEL register determines whether the interrupt is edge or level sensitive.

Table 80. Pin interrupt mode register (ISEL, address 0xA000 4000) bit description

Bit

Symbol Description

Reset Access

value

7:0

PMODE Selects the interrupt mode for each pin interrupt. Bit n

configures the pin interrupt selected in PINTSELn.

0 = Edge sensitive

0

R/W

1 = Level sensitive

31:8

-

Reserved.

-

8.6.2 Pin interrupt level or rising edge interrupt enable register

For each of the 8 pin interrupts selected in the PINTSELn registers (see Section 4.6.27),

one bit in the IENR register enables the interrupt depending on the pin interrupt mode

configured in the ISEL register:

• If the pin interrupt mode is edge sensitive (PMODE = 0), the rising edge interrupt is

enabled.

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• If the pin interrupt mode is level sensitive (PMODE = 1), the level interrupt is enabled.

The IENF register configures the active level (HIGH or LOW) for this interrupt.

Table 81. Pin interrupt level or rising edge interrupt enable register (IENR, address 0xA000

4004) bit description

Bit

Symbol Description

Reset Access

value

7:0

ENRL Enables the rising edge or level interrupt for each pin

0

R/W

interrupt. Bit n configures the pin interrupt selected in

PINTSELn.

0 = Disable rising edge or level interrupt.

1 = Enable rising edge or level interrupt.

31:8

-

Reserved.

-

8.6.3 Pin interrupt level or rising edge interrupt set register

For each of the 8 pin interrupts selected in the PINTSELn registers (see Section 4.6.27),

one bit in the SIENR register sets the corresponding bit in the IENR register depending on

the pin interrupt mode configured in the ISEL register:

• If the pin interrupt mode is edge sensitive (PMODE = 0), the rising edge interrupt is

set.

• If the pin interrupt mode is level sensitive (PMODE = 1), the level interrupt is set.

Table 82. Pin interrupt level or rising edge interrupt set register (SIENR, address 0xA000

4008) bit description

Bit

Symbol

Description

Reset Access

value

7:0

SETENRL Ones written to this address set bits in the IENR, thus

enabling interrupts. Bit n sets bit n in the IENR register.

0 = No operation.

NA

WO

1 = Enable rising edge or level interrupt.

31:8

-

Reserved.

-

8.6.4 Pin interrupt level or rising edge interrupt clear register

For each of the 8 pin interrupts selected in the PINTSELn registers (see Section 4.6.27),

one bit in the CIENR register clears the corresponding bit in the IENR register depending

on the pin interrupt mode configured in the ISEL register:

• If the pin interrupt mode is edge sensitive (PMODE = 0), the rising edge interrupt is

cleared.

• If the pin interrupt mode is level sensitive (PMODE = 1), the level interrupt is cleared.

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Table 83. Pin interrupt level or rising edge interrupt clear register (CIENR, address 0xA000

400C) bit description

Bit

Symbol Description

Reset Access

value

7:0

CENRL Ones written to this address clear bits in the IENR, thus

NA

WO

disabling the interrupts. Bit n clears bit n in the IENR

register.

0 = No operation.

1 = Disable rising edge or level interrupt.

31:8

-

Reserved.

-

8.6.5 Pin interrupt active level or falling edge interrupt enable register

For each of the 8 pin interrupts selected in the PINTSELn registers (see Section 4.6.27),

one bit in the IENF register enables the falling edge interrupt or the configures the level

sensitivity depending on the pin interrupt mode configured in the ISEL register:

• If the pin interrupt mode is edge sensitive (PMODE = 0), the falling edge interrupt is

enabled.

• If the pin interrupt mode is level sensitive (PMODE = 1), the active level of the level

interrupt (HIGH or LOW) is configured.

Table 84. Pin interrupt active level or falling edge interrupt enable register (IENF, address

0xA000 4010) bit description

Bit Symbol Description

Reset Access

value

7:0 ENAF Enables the falling edge or configures the active level interrupt

0

R/W

for each pin interrupt. Bit n configures the pin interrupt selected

in PINTSELn.

0 = Disable falling edge interrupt or set active interrupt level

LOW.

1 = Enable falling edge interrupt enabled or set active interrupt

level HIGH.

31:8 -

Reserved.

-

8.6.6 Pin interrupt active level or falling edge interrupt set register

For each of the 8 pin interrupts selected in the PINTSELn registers (see Section 4.6.27),

one bit in the SIENF register sets the corresponding bit in the IENF register depending on

the pin interrupt mode configured in the ISEL register:

• If the pin interrupt mode is edge sensitive (PMODE = 0), the falling edge interrupt is

set.

• If the pin interrupt mode is level sensitive (PMODE = 1), the HIGH-active interrupt is

selected.

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Table 85. Pin interrupt active level or falling edge interrupt set register (SIENF, address

0xA000 4014) bit description

Bit

Symbol

Description

Reset Access

value

7:0

SETENAF Ones written to this address set bits in the IENF, thus

enabling interrupts. Bit n sets bit n in the IENF register.

0 = No operation.

NA

WO

1 = Select HIGH-active interrupt or enable falling edge

interrupt.

31:8

-

Reserved.

-

8.6.7 Pin interrupt active level or falling edge interrupt clear register

For each of the 8 pin interrupts selected in the PINTSELn registers (see Section 4.6.27),

one bit in the CIENF register sets the corresponding bit in the IENF register depending on

the pin interrupt mode configured in the ISEL register:

• If the pin interrupt mode is edge sensitive (PMODE = 0), the falling edge interrupt is

cleared.

• If the pin interrupt mode is level sensitive (PMODE = 1), the LOW-active interrupt is

selected.

Table 86. Pin interrupt active level or falling edge interrupt clear register (CIENF, address

0xA000 4018) bit description

Bit

Symbol Description

Reset Access

value

7:0

CENAF Ones written to this address clears bits in the IENF, thus

disabling interrupts. Bit n clears bit n in the IENF register.

0 = No operation.

NA

WO

1 = LOW-active interrupt selected or falling edge interrupt

disabled.

31:8

-

Reserved.

-

8.6.8 Pin interrupt rising edge register

This register contains ones for pin interrupts selected in the PINTSELn registers (see

Section 4.6.27) on which a rising edge has been detected. Writing ones to this register

clears rising edge detection. Ones in this register assert an interrupt request for pins that

are enabled for rising-edge interrupts. All edges are detected for all pins selected by the

PINTSELn registers, regardless of whether they are interrupt-enabled.

Table 87. Pin interrupt rising edge register (RISE, address 0xA000 401C) bit description

Bit Symbol Description

Reset Access

value

7:0 RDET Rising edge detect. Bit n detects the rising edge of the pin

0

R/W

selected in PINTSELn.

Read 0: No rising edge has been detected on this pin since

Reset or the last time a one was written to this bit.

Write 0: no operation.

Read 1: a rising edge has been detected since Reset or the

last time a one was written to this bit.

Write 1: clear rising edge detection for this pin.

31:8 -

Reserved.

-

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8.6.9 Pin interrupt falling edge register

This register contains ones for pin interrupts selected in the PINTSELn registers (see

Section 4.6.27) on which a falling edge has been detected. Writing ones to this register

clears falling edge detection. Ones in this register assert an interrupt request for pins that

are enabled for falling-edge interrupts. All edges are detected for all pins selected by the

PINTSELn registers, regardless of whether they are interrupt-enabled.

Table 88. Pin interrupt falling edge register (FALL, address 0xA000 4020) bit description

Bit

Symbol Description

Reset Access

value

7:0

FDET Falling edge detect. Bit n detects the falling edge of the pin

0

R/W

selected in PINTSELn.

Read 0: No falling edge has been detected on this pin since

Reset or the last time a one was written to this bit.

Write 0: no operation.

Read 1: a falling edge has been detected since Reset or the

last time a one was written to this bit.

Write 1: clear falling edge detection for this pin.

31:8

-

Reserved.

-

8.6.10 Pin interrupt status register

Reading this register returns ones for pin interrupts that are currently requesting an

interrupt. For pins identified as edge-sensitive in the Interrupt Select register, writing ones

to this register clears both rising- and falling-edge detection for the pin. For level-sensitive

pins, writing ones inverts the corresponding bit in the Active level register, thus switching

the active level on the pin.

Table 89. Pin interrupt status register (IST, address 0xA000 4024) bit description

Bit

Symbol Description

Reset Access

value

7:0

PSTAT Pin interrupt status. Bit n returns the status, clears the edge

interrupt, or inverts the active level of the pin selected in

PINTSELn.

0

R/W

Read 0: interrupt is not being requested for this interrupt pin.

Write 0: no operation.

Read 1: interrupt is being requested for this interrupt pin.

Write 1 (edge-sensitive): clear rising- and falling-edge

detection for this pin.

Write 1 (level-sensitive): switch the active level for this pin (in

the IENF register).

31:8

-

Reserved.

-

8.6.11 Pattern Match Interrupt Control Register

The pattern match control register contains one bit to select pattern-match interrupt

generation (as opposed to pin interrupts which share the same interrupt request lines),

and another to enable the RXEV output to the cpu. This register also allows the current

state of any pattern matches to be read.

If the pattern match feature is not used (either for interrupt generation or for RXEV

assertion) the two LSB’s of this register should be left at 0b00 to conserve power.

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Remark: Set up the pattern-match configuration in the PMSRC and PMCFG registers

before writing to this register to enable (or re-enable) the pattern-match functionality. This

eliminates the possibility of spurious interrupts as the feature is being enabled.

Table 90. Pattern match interrupt control register (PMCTRL, address 0x4004 C028)

bit description

Bit

Symbol

Value Description

Reset

value

0

SEL_PMATCH

Specifies whether the 8 pin interrupts are controlled by

0

the pin interrupt function or by the pattern match

function.

0

1

Pin interrupt. Interrupts are driven in response to the

standard pin interrupt function

Pattern match. Interrupts are driven in response to

pattern matches.

1

ENA_RXEV

Enables the RXEV output to the ARM cpu and/or to a

GPIO output when the specified boolean expression

evaluates to true.

0

1

Disabled. RXEV output to the cpu is disabled.

Enabled. RXEV output to the cpu is enabled.

Reserved. Do not write 1s to unused bits.

23:2

-

31:24 PMAT

-

This field displays the current state of pattern matches. 0x0

A 1 in any bit of this field indicates that the

corresponding product term is matched by the current

state of the appropriate inputs.

8.6.12 Pattern Match Interrupt Bit-Slice Source register

The bit-slice source register specifies the input source for each of the eight pattern match

bit slices.

Each of the possible eight inputs is selected in the pin interrupt select registers in the

SYSCON block. See Section 4.6.27. Input 0 corresponds to the pin selected in the

PINTSEL0 register, input 1 corresponds to the pin selected in the PINTSEL1 register, and

so forth.

Remark: Writing any value to either the PMCFG register or the PMSRC register, or

disabling the pattern-match feature (by clearing both the SEL_PMATCH and ENA_RXEV

bits in the PMCTRL register to zeros) will erase all edge-detect history.

Table 91. Pattern match bit-slice source register (PMSRC, address 0x4004 C02C)

bit description

Bit

Symbol

Value

Description

Reset value

7:0

Reserved

Software should not write 1s to unused bits.

0x0

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Table 91. Pattern match bit-slice source register (PMSRC, address 0x4004 C02C)

bit description

Bit

Symbol

Value

Description

Reset value

10:8

SRC0

Selects the input source for bit slice 0

000

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

Input 0. Selects pin interrupt input 0 as the source to bit slice 0.

Input 1. Selects pin interrupt input 1 as the source to bit slice 0.

Input 2. Selects pin interrupt input 2 as the source to bit slice 0.

Input 3. Selects pin interrupt input 3 as the source to bit slice 0.

Input 4. Selects pin interrupt input 4 as the source to bit slice 0.

Input 5. Selects pin interrupt input 5 as the source to bit slice 0.

Input 6. Selects pin interrupt input 6 as the source to bit slice 0.

Input 7. Selects pin interrupt input 7 as the source to bit slice 0.

Selects the input source for bit slice 1

13:11 SRC1

16:14 SRC2

19:17 SRC3

000

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

Input 0. Selects pin interrupt input 0 as the source to bit slice 1.

Input 1. Selects pin interrupt input 1 as the source to bit slice 1.

Input 2. Selects pin interrupt input 2 as the source to bit slice 1.

Input 3. Selects pin interrupt input 3 as the source to bit slice 1.

Input 4. Selects pin interrupt input 4 as the source to bit slice 1.

Input 5. Selects pin interrupt input 5 as the source to bit slice 1.

Input 6. Selects pin interrupt input 6 as the source to bit slice 1.

Input 7. Selects pin interrupt input 7 as the source to bit slice 1.

Selects the input source for bit slice 2

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

Input 0. Selects pin interrupt input 0 as the source to bit slice 2.

Input 1. Selects pin interrupt input 1 as the source to bit slice 2.

Input 2. Selects pin interrupt input 2 as the source to bit slice 2.

Input 3. Selects pin interrupt input 3 as the source to bit slice 2.

Input 4. Selects pin interrupt input 4 as the source to bit slice 2.

Input 5. Selects pin interrupt input 5 as the source to bit slice 2.

Input 6. Selects pin interrupt input 6 as the source to bit slice 2.

Input 7. Selects pin interrupt input 7 as the source to bit slice 2.

Selects the input source for bit slice 3

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

Input 0. Selects pin interrupt input 0 as the source to bit slice 3.

Input 1. Selects pin interrupt input 1 as the source to bit slice 3.

Input 2. Selects pin interrupt input 2 as the source to bit slice 3.

Input 3. Selects pin interrupt input 3 as the source to bit slice 3.

Input 4. Selects pin interrupt input 4 as the source to bit slice 3.

Input 5. Selects pin interrupt input 5 as the source to bit slice 3.

Input 6. Selects pin interrupt input 6 as the source to bit slice 3.

Input 7. Selects pin interrupt input 7 as the source to bit slice 3.

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Table 91. Pattern match bit-slice source register (PMSRC, address 0x4004 C02C)

bit description

Bit

Symbol

Value

Description

Reset value

22:20 SRC4

25:23 SRC5

28:26 SRC6

31:29 SRC7

Selects the input source for bit slice 4

000

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

Input 0. Selects pin interrupt input 0 as the source to bit slice 4.

Input 1. Selects pin interrupt input 1 as the source to bit slice 4.

Input 2. Selects pin interrupt input 2 as the source to bit slice 4.

Input 3. Selects pin interrupt input 3 as the source to bit slice 4.

Input 4. Selects pin interrupt input 4 as the source to bit slice 4.

Input 5. Selects pin interrupt input 5 as the source to bit slice 4.

Input 6. Selects pin interrupt input 6 as the source to bit slice 4.

Input 7. Selects pin interrupt input 7 as the source to bit slice 4.

Selects the input source for bit slice 5

000

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

Input 0. Selects pin interrupt input 0 as the source to bit slice 5.

Input 1. Selects pin interrupt input 1 as the source to bit slice 5.

Input 2. Selects pin interrupt input 2 as the source to bit slice 5.

Input 3. Selects pin interrupt input 3 as the source to bit slice 5.

Input 4. Selects pin interrupt input 4 as the source to bit slice 5.

Input 5. Selects pin interrupt input 5 as the source to bit slice 5.

Input 6. Selects pin interrupt input 6 as the source to bit slice 5.

Input 7. Selects pin interrupt input 7 as the source to bit slice 5.

Selects the input source for bit slice 6

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

Input 0. Selects pin interrupt input 0 as the source to bit slice 6.

Input 1. Selects pin interrupt input 1 as the source to bit slice 6.

Input 2. Selects pin interrupt input 2 as the source to bit slice 6.

Input 3. Selects pin interrupt input 3 as the source to bit slice 6.

Input 4. Selects pin interrupt input 4 as the source to bit slice 6.

Input 5. Selects pin interrupt input 5 as the source to bit slice 6.

Input 6. Selects pin interrupt input 6 as the source to bit slice 6.

Input 7. Selects pin interrupt input 7 as the source to bit slice 6.

Selects the input source for bit slice 7

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

Input 0. Selects pin interrupt input 0 as the source to bit slice 7.

Input 1. Selects pin interrupt input 1 as the source to bit slice 7.

Input 2. Selects pin interrupt input 2 as the source to bit slice 7.

Input 3. Selects pin interrupt input 3 as the source to bit slice 7.

Input 4. Selects pin interrupt input 4 as the source to bit slice 7.

Input 5. Selects pin interrupt input 5 as the source to bit slice 7.

Input 6. Selects pin interrupt input 6 as the source to bit slice 7.

Input 7. Selects pin interrupt input 7 as the source to bit slice 7.

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Chapter 8: LPC800 Pin interrupts/pattern match engine

8.6.13 Pattern Match Interrupt Bit-Slice Configuration register

The bit-slice configuration register contains bits to select from among eight alternative

conditions for each bit slice that will cause that bit slice to contribute to a pattern match.

The seven LSB’s of this register specify which bit-slices are the end-points of product

terms in the boolean expression (i.e. where OR terms are to be inserted in the

expression).

This bit is only cleared when the PMCFG or the PMSRC registers are written to.

Remark: Writing any value to either the PMCFG register or the PMSRC register, or

disabling the pattern-match feature (by clearing both the SEL_PMATCH and ENA_RXEV

bits in the PMCTRL register to zeros) will erase all edge-detect history.

Table 92. Pattern match bit slice configuration register (PMCFG, address 0x4004 C030) bit description

Bit

Symbol

Value Description

Reset

value

6:0

PROD_

A 1 in any bit of this field causes the corresponding bit slice to be the final component 0x0

ENDPTS

of a product term in the boolean expression.

This has two effects:

1. The interrupt request associated with this bit-slice will be asserted whenever a

match to that product term is detected.

2. The next bit slice will start a new, independent product term in the boolean

expression (i.e. an OR will be inserted in the boolean expression following the

element controlled by this bit slice).

7

Reserved

CFG0

(Bit slice 7 is automatically considered a product end point)

Specifies the match-contribution condition for bit slice 0.

Constant 1. This bit slice always contributes to a product term match.

0

10:8

0b000

0x0

0x1

Rising edge. Match occurs if a rising edge on the specified input has occurred since

the last time the edge detection for this bit slice was cleared. This bit is only

cleared when the PMCFG or the PMSRC registers are written to.

0x2

0x3

Falling edge. Match occurs if a falling edge on the specified input has occurred since

the last time the edge detection for this bit slice was cleared. This bit is only

cleared when the PMCFG or the PMSRC registers are written to.

Rising or falling edge. Match occurs if either a rising or falling edge on the specified

input has occurred since the last time the edge detection for this bit slice was

cleared. This bit is only cleared when the PMCFG or the PMSRC registers

are written to.

0x4

High level. Match (for this bit slice) occurs when there is a high level on the input

specified for this bit slice in the PMSRC register.

0x5

0x6

Low level. Match occurs when there is a low level on the specified input.

Constant 0. This bit slice never contributes to a match (should be used to disable

any unused bit slices)

0x7

Event. Match occurs on an event - i.e. when either a rising or falling edge is first

detected on the specified input (this is a non-sticky version of option 3)

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Chapter 8: LPC800 Pin interrupts/pattern match engine

Table 92. Pattern match bit slice configuration register (PMCFG, address 0x4004 C030) bit description …continued

Bit

Symbol

Value Description

Reset

value

13:11 CFG1

Specifies the match-contribution condition for bit slice 1.

0b000

0x0

0x1

Constant 1. This bit slice always contributes to a product term match.

Rising edge. Match occurs if a rising edge on the specified input has occurred since

the last time the edge detection for this bit slice was cleared. This bit is only

cleared when the PMCFG or the PMSRC registers are written to.

0x2

0x3

Falling edge. Match occurs if a falling edge on the specified input has occurred since

the last time the edge detection for this bit slice was cleared. This bit is only

cleared when the PMCFG or the PMSRC registers are written to.

Rising or falling edge. Match occurs if either a rising or falling edge on the specified

input has occurred since the last time the edge detection for this bit slice was

cleared. This bit is only cleared when the PMCFG or the PMSRC registers

are written to.

0x4

High level. Match (for this bit slice) occurs when there is a high level on the input

specified for this bit slice in the PMSRC register.

0x5

0x6

Low level. Match occurs when there is a low level on the specified input.

Constant 0. This bit slice never contributes to a match (should be used to disable

any unused bit slices)

0x7

Event. Match occurs on an event - i.e. when either a rising or falling edge is first

detected on the specified input (this is a non-sticky version of option 3)

16:14 CFG2

Specifies the match-contribution condition for bit slice 2.

0b000

0x0

0x1

Constant 1. This bit slice always contributes to a product term match.

Rising edge. Match occurs if a rising edge on the specified input has occurred since

the last time the edge detection for this bit slice was cleared. This bit is only

cleared when the PMCFG or the PMSRC registers are written to.

0x2

0x3

Falling edge. Match occurs if a falling edge on the specified input has occurred since

the last time the edge detection for this bit slice was cleared. This bit is only

cleared when the PMCFG or the PMSRC registers are written to.

Rising or falling edge. Match occurs if either a rising or falling edge on the specified

input has occurred since the last time the edge detection for this bit slice was

cleared. This bit is only cleared when the PMCFG or the PMSRC registers

are written to.

0x4

High level. Match (for this bit slice) occurs when there is a high level on the input

specified for this bit slice in the PMSRC register.

0x5

0x6

Low level. Match occurs when there is a low level on the specified input.

Constant 0. This bit slice never contributes to a match (should be used to disable

any unused bit slices)

0x7

Event. Match occurs on an event - i.e. when either a rising or falling edge is first

detected on the specified input (this is a non-sticky version of option 3)

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Chapter 8: LPC800 Pin interrupts/pattern match engine

Table 92. Pattern match bit slice configuration register (PMCFG, address 0x4004 C030) bit description …continued

Bit

Symbol

Value Description

Reset

value

19:17 CFG3

Specifies the match-contribution condition for bit slice 3.

0b000

0x0

0x1

Constant 1. This bit slice always contributes to a product term match.

Rising edge. Match occurs if a rising edge on the specified input has occurred since

the last time the edge detection for this bit slice was cleared. This bit is only

cleared when the PMCFG or the PMSRC registers are written to.

0x2

0x3

Falling edge. Match occurs if a falling edge on the specified input has occurred since

the last time the edge detection for this bit slice was cleared. This bit is only

cleared when the PMCFG or the PMSRC registers are written to.

Rising or falling edge. Match occurs if either a rising or falling edge on the specified

input has occurred since the last time the edge detection for this bit slice was

cleared. This bit is only cleared when the PMCFG or the PMSRC registers

are written to.

0x4

High level. Match (for this bit slice) occurs when there is a high level on the input

specified for this bit slice in the PMSRC register.

0x5

0x6

Low level. Match occurs when there is a low level on the specified input.

Constant 0. This bit slice never contributes to a match (should be used to disable

any unused bit slices)

0x7

Event. Match occurs on an event - i.e. when either a rising or falling edge is first

detected on the specified input (this is a non-sticky version of option 3)

22:20 CFG4

Specifies the match-contribution condition for bit slice 4.

0b000

0x0

0x1

Constant 1. This bit slice always contributes to a product term match.

Rising edge. Match occurs if a rising edge on the specified input has occurred since

the last time the edge detection for this bit slice was cleared. This bit is only

cleared when the PMCFG or the PMSRC registers are written to.

0x2

0x3

Falling edge. Match occurs if a falling edge on the specified input has occurred since

the last time the edge detection for this bit slice was cleared. This bit is only

cleared when the PMCFG or the PMSRC registers are written to.

Rising or falling edge. Match occurs if either a rising or falling edge on the specified

input has occurred since the last time the edge detection for this bit slice was

cleared. This bit is only cleared when the PMCFG or the PMSRC registers

are written to.

0x4

High level. Match (for this bit slice) occurs when there is a high level on the input

specified for this bit slice in the PMSRC register.

0x5

0x6

Low level. Match occurs when there is a low level on the specified input.

Constant 0. This bit slice never contributes to a match (should be used to disable

any unused bit slices)

0x7

Event. Match occurs on an event - i.e. when either a rising or falling edge is first

detected on the specified input (this is a non-sticky version of option 3)

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Chapter 8: LPC800 Pin interrupts/pattern match engine

Table 92. Pattern match bit slice configuration register (PMCFG, address 0x4004 C030) bit description …continued

Bit

Symbol

Value Description

Reset

value

25:23 CFG5

Specifies the match-contribution condition for bit slice 5.

0b000

0x0

0x1

Constant 1. This bit slice always contributes to a product term match.

Rising edge. Match occurs if a rising edge on the specified input has occurred since

the last time the edge detection for this bit slice was cleared. This bit is only

cleared when the PMCFG or the PMSRC registers are written to.

0x2

0x3

Falling edge. Match occurs if a falling edge on the specified input has occurred since

the last time the edge detection for this bit slice was cleared. This bit is only

cleared when the PMCFG or the PMSRC registers are written to.

Rising or falling edge. Match occurs if either a rising or falling edge on the specified

input has occurred since the last time the edge detection for this bit slice was

cleared. This bit is only cleared when the PMCFG or the PMSRC registers

are written to.

0x4

High level. Match (for this bit slice) occurs when there is a high level on the input

specified for this bit slice in the PMSRC register.

0x5

0x6

Low level. Match occurs when there is a low level on the specified input.

Constant 0. This bit slice never contributes to a match (should be used to disable

any unused bit slices)

0x7

Event. Match occurs on an event - i.e. when either a rising or falling edge is first

detected on the specified input (this is a non-sticky version of option 3)

28:26 CFG6

Specifies the match-contribution condition for bit slice 6.

0b000

0x0

0x1

Constant 1. This bit slice always contributes to a product term match.

Rising edge. Match occurs if a rising edge on the specified input has occurred since

the last time the edge detection for this bit slice was cleared. This bit is only

cleared when the PMCFG or the PMSRC registers are written to.

0x2

0x3

Falling edge. Match occurs if a falling edge on the specified input has occurred since

the last time the edge detection for this bit slice was cleared. This bit is only

cleared when the PMCFG or the PMSRC registers are written to.

Rising or falling edge. Match occurs if either a rising or falling edge on the specified

input has occurred since the last time the edge detection for this bit slice was

cleared. This bit is only cleared when the PMCFG or the PMSRC registers

are written to.

0x4

High level. Match (for this bit slice) occurs when there is a high level on the input

specified for this bit slice in the PMSRC register.

0x5

0x6

Low level. Match occurs when there is a low level on the specified input.

Constant 0. This bit slice never contributes to a match (should be used to disable

any unused bit slices)

0x7

Event. Match occurs on an event - i.e. when either a rising or falling edge is first

detected on the specified input (this is a non-sticky version of option 3)

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Chapter 8: LPC800 Pin interrupts/pattern match engine

Table 92. Pattern match bit slice configuration register (PMCFG, address 0x4004 C030) bit description …continued

Bit

Symbol

Value Description

Reset

value

31:29 CFG7

Specifies the match-contribution condition for bit slice 7.

0b000

0x0

0x1

Constant 1. This bit slice always contributes to a product term match.

Rising edge. Match occurs if a rising edge on the specified input has occurred since

the last time the edge detection for this bit slice was cleared. This bit is only

cleared when the PMCFG or the PMSRC registers are written to.

0x2

0x3

Falling edge. Match occurs if a falling edge on the specified input has occurred since

the last time the edge detection for this bit slice was cleared. This bit is only

cleared when the PMCFG or the PMSRC registers are written to.

Rising or falling edge. Match occurs if either a rising or falling edge on the specified

input has occurred since the last time the edge detection for this bit slice was

cleared. This bit is only cleared when the PMCFG or the PMSRC registers

are written to.

0x4

High level. Match (for this bit slice) occurs when there is a high level on the input

specified for this bit slice in the PMSRC register.

0x5

0x6

Low level. Match occurs when there is a low level on the specified input.

Constant 0. This bit slice never contributes to a match (should be used to disable

any unused bit slices)

0x7

Event. Match occurs on an event - i.e. when either a rising or falling edge is first

detected on the specified input (this is a non-sticky version of option 3)

8.7 Functional description

8.7.1 Pin interrupts

In this interrupt facility, up to 8 pins are identified as interrupt sources by the Pin Interrupt

Select registers (PINTSEL0-7). All registers in the pin interrupt block contain 8 bits,

corresponding to the pins called out by the PINTSEL0-7 registers. The ISEL register

defines whether each interrupt pin is edge- or level-sensitive. The RISE and FALL

registers detect edges on each interrupt pin, and can be written to clear (and set) edge

detection. The IST register indicates whether each interrupt pin is currently requesting an

interrupt, and this register can also be written to clear interrupts.

The other pin interrupt registers play different roles for edge-sensitive and level-sensitive

pins, as described in Table 93.

Table 93. Pin interrupt registers for edge- and level-sensitive pins

Name

IENR

Edge-sensitive function

Level-sensitive function

Enables level interrupts.

Write to enable level interrupts.

Write to disable level interrupts.

Selects active level.

Enables rising-edge interrupts.

SIENR

CIENR

IENF

Write to enable rising-edge interrupts.

Write to disable rising-edge interrupts.

Enables falling-edge interrupts.

Write to enable falling-edge interrupts.

Write to disable falling-edge interrupts.

SIENF

CIENF

Write to select high-active.

Write to select low-active.

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Chapter 8: LPC800 Pin interrupts/pattern match engine

8.7.2 Pattern Match engine example

Suppose the desired boolean pattern to be matched is:

(IN1) + (IN1 * IN2) + (~IN2 * ~IN3 * IN6fe) + (IN5 * IN7ev)

with:

IN6fe = (sticky) falling-edge on input 6

IN7ev = (non-sticky) event (rising or falling edge) on input 7

Each individual term in the expression shown above is controlled by one bit-slice. To

specify this expression, program the pattern match bit slice source and configuration

register fields as follows:

• PMSRC register (Table 91):

– CLR_EDGEDET: A 1 may be written to bit 5 to clear any pre-existing edge detects

on bit-slice 5, if that is what is desired.

– SRC0: 001 - select input 1 for bit slice 0

– SRC1: 001 - select input 1 for bit slice 1

– SRC2: 010 - select input 2 for bit slice 2

– SRC3: 010 - select input 2 for bit slice 3

– SRC4: 011 - select input 3 for bit slice 4

– SRC5: 110 - select input 6 for bit slice 5

– SRC6: 101 - select input 5 for bit slice 6

– SRC7: 111 - select input 7 for bit slice 7

• PMCTRL register (Table 90):

– Bit[0]: Setting this bit will select pattern matches to generate the pin interrupts in

place of the normal pin interrupt mechanism.

For this example, pin interrupt 0 will be asserted when a match is detected on the

first product term (which, in this case, is just a high level on input 1).

Pin interrupt 2 will be asserted in response to a match on the second product term.

Pin interrupt 5 will be asserted when there is a match on the third product term.

Pin interrupt 7 will be asserted on a match on the last term.

– Bit[1]: Setting this bit will cause the RxEv signal to the ARM CPU to be asserted

whenever a match occurs on ANY of the product terms in the expression.

Otherwise, the RXEV line will not be used.

– Bit[31:24]: At any given time, bits 0, 2, 5 and/or 7 may be high if the corresponding

product terms are currently matching.

– The remaining bits will always be low.

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Chapter 9: LPC800 Switch matrix

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Preliminary user manual

9.1 How to read this chapter

The switch matrix is identical for all LPC800 parts. The USART2 and SPI1 functions are

only available on parts LPC812M101FDH20 and LPC812M101FDH16 and the corresponding

switch matrix select bits are reserved for all other parts.

9.2 Features

• Flexible assignment of digital peripheral functions to pins

• Enable/disable of analog functions

9.3 Basic configuration

Once configured, no clocks are needed for the switch matrix to function. The system clock

is needed only to write to or read from the pin assignment registers. After the switch matrix

is configured, disable the clock to the switch matrix block in the SYSAHBCLKCTRL

register.

Before activating a peripheral or enabling its interrupt, use the switch matrix to connect the

peripheral to external pins.

The boot loader assigns the SWD functions to pins PIO0_2 and PIO0_3. If the user code

disables the SWD functions through the switch matrix to use the pins for other functions,

the SWD port is disabled.

Remark: For the purpose of programming the pin functions through the switch matrix,

every pin except the power and ground pins is identified in a package-independent way by

its GPIO port pin number.

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Chapter 9: LPC800 Switch matrix

9.3.1 Connect an internal signal to a package pin

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A pin is identified for the purpose of programming the switch matrix by its default GPIO port pin.

Fig 7. Example: Connect function U0_RXD and U0_TXD to pins 8 and 14 on the SO20 package

The switch matrix connects all internal signals listed in the table of movable functions

through the pin assignment registers to external pins on the package. External pins are

identified by their default GPIO pin number PIO0_n. Follow these steps to connect an

internal signal FUNC to an external pin. An example of a movable function is the UART

transmit signal TXD:

1. Find the function FUNC in the list of movable function in Table 94 or in the data sheet.

2. Use the LPC800 data sheet to decide which pin x on the LPC800 package to connect

FUNC to.

3. Use the pin description table to find the default GPIO function PIO0_n assigned to

package pin x. m is the pin number.

4. Locate the pin assignment register for the function FUNC in the switch matrix register

description.

5. Disable any special functions on pin PIO0_n in the PINENABLE0 register.

6. Program the pin number n into the bits assigned to FUNC.

FUNC is now connected to pin x on the package.

9.3.2 Enable an analog input or other special function

The switch matrix enables functions that can only be assigned to one pin. Examples are

analog inputs, all GPIO pins, and the debug SWD pins.

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Chapter 9: LPC800 Switch matrix

• If you want to assign a GPIO pin to a pin on any LPC800 package, disable any special

function available on this pin in the PINENABLE0 register and do not assign any

movable function to it.

By default, all pins except pins PIO0_2, PIO0_3, and PIO0_5 are assigned to GPIO.

• For all other functions that are not in the table of movable functions, do the following:

a. Locate the function in the pin description table in the data sheet. This shows the

package pin for this function.

b. Enable the function in the PINENABLE0 register. All other possible functions on

this pins are now disabled.

9.4 General description

The switch matrix connects internal signals (functions) to external pins. Functions are

signals coming from or going to a single pin on the package and coming from or going to

an on-chip peripheral block. Examples of functions are the GPIOs, the UART transmit

output (TXD), or the clock output CLKOUT. Many peripherals have several functions that

must be connected to external pins.

On the LPC800, most functions can be assigned through the switch matrix to any external

pin that is not a power or ground pin. These functions are called movable functions.

A few functions like the crystal oscillator pins (XTALIN/XTALOUT) or the analog

comparator inputs can only be assigned to one particular external pin with the appropriate

electrical characteristics. These functions are called fixed-pin functions. If a fixed-pin

function is not used, it can be replaced by any other movable function.

GPIOs are fixed-pin functions. Each GPIO is assigned to one and only one external pin.

By default, all external pins have the GPIO function assigned. External pins are therefore

identified by their fixed-pin GPIO function.

9.4.1 Movable functions

Table 94. Movable functions (assign to pins PIO0_0 to PIO_17 through switch matrix)

Function name

Type

Description

SWM Pin assign

register

Reference

U0_TXD

U0_RXD

U0_RTS

U0_CTS

U0_SCLK

O

I

Transmitter output for USART0.

Receiver input for USART0.

PINASSIGN0

PINASSIGN1

Table 96

Table 97

O

I

Request To Send output for USART0.

Clear To Send input for USART0.

I/O

Serial clock input/output for USART0 in synchronous

mode.

U1_TXD

U1_RXD

U1_RTS

U1_CTS

U1_SCLK

O

I

Transmitter output for USART1.

Receiver input for USART1.

PINASSIGN1

PINASSIGN2

Table 97

Table 98

O

I

Request To Send output for USART1.

Clear To Send input for USART1.

I/O

Serial clock input/output for USART1 in synchronous

mode.

U2_TXD

O

Transmitter output for USART2.

PINASSIGN2

Table 98

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Table 94. Movable functions (assign to pins PIO0_0 to PIO_17 through switch matrix)

Function name

Type

Description

SWM Pin assign

register

Reference

U2_RXD

U2_RTS

U2_CTS

U2_SCLK

I

Receiver input for USART2.

PINASSIGN2

PINASSIGN3

Table 98

Table 99

O

I

Request To Send output for USART1.

Clear To Send input for USART1.

I/O

Serial clock input/output for USART1 in synchronous

mode.

SPI0_SCK

SPI0_MOSI

SPI0_MISO

SPI0_SSEL

SPI1_SCK

SPI1_MOSI

SPI1_MISO

SPI1_SSEL

CTIN_0

I/O

I

Serial clock for SPI0.

Master Out Slave In for SPI0.

Master In Slave Out for SPI0.

Slave select for SPI0.

Serial clock for SPI1.

Master Out Slave In for SPI1.

Master In Slave Out for SPI1.

Slave select for SPI1.

SCT input 0.

PINASSIGN3

PINASSIGN4

PINASSIGN5

PINASSIGN6

PINASSIGN7

Table 99

Table 100

Table 101

Table 102

Table 103

CTIN_1

I

SCT input 1.

CTIN_2

I

SCT input 2.

CTIN_3

I

SCT input 3.

CTOUT_0

CTOUT_1

CTOUT_2

CTOUT_3

I2C0_SDA

O

SCT output 0.

O

SCT output 1.

O

SCT output 2.

O

SCT output 3.

I/O

I²C-bus data input/output (open-drain if assigned to pin

PIO0_11). High-current sink only if assigned to pin

PIO0_11 and if I²C Fast-mode Plus is selected in the I/O

configuration register.

I2C0_SCL

I/O

I²C-bus clock input/output (open-drain if assigned to pin

PIO0_10). High-current sink only if assigned to PIO0_10

and if I²C Fast-mode Plus is selected in the I/O

configuration register.

PINASSIGN8

Table 104

ACMP_O

CLKOUT

O

Analog comparator output.

Clock output.

PINASSIGN8

Table 104

GPIO_INT_BMAT O

Output of the pattern match engine.

9.4.2 Switch matrix register interface

The switch matrix consists of two blocks of pin-assignment registers PINASSIGN and

PINENABLE. Every function has an assigned field (1-bit or 8-bit wide) within this bank of

registers where you can program the external pin - identified by its GPIO function - you

want the function to connect to.

GPIOs range from PIO0_0 to PIO0_17 and, for assignment through the pin-assignment

registers, are numbered 0 to 17.

There are two types of functions which must be assigned to port pins in different ways:

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1. Movable functions (PINASSIGN0 to 8):

All movable functions are digital functions. Assign movable functions to pin numbers

through the 8 bits of the PINASSIGN register associated with this function. Once the

function is assigned a pin PIO0_n, it is connected through this pin to a physical pin on

the package.

Remark: You can assign only one digital output function to an external pin at any

given time.

Remark: You can assign more than one digital input function to one external pin.

2. Fixed-pin functions (PINENABLE0):

Some functions require pins with special characteristics and cannot be moved to

other physical pins. Hence these functions are mapped to a fixed port pin. Examples

of fixed-pin functions are the oscillator pins or comparator inputs.

Each fixed-pin function is associated with one bit in the PINENABLE0 register which

selects or deselects the function.

– If a fixed-pin function is deselected, any movable function can be assigned to its

port and pin.

– If a fixed-pin function is deselected and no movable function is assigned to this pin,

the pin is GPIO.

– On reset, all fixed-pin functions are deselected.

– If a fixed-pin function is selected, its assigned pin can not be used for any other

function.

9.5 Register description

Table 95. Register overview: Switch matrix (base address 0x4000 C000)

Name

Access Offset

Description

Reset value

Reference

PINASSIGN0

R/W

0x000

Pin assign register 0. Assign movable

functions U0_TXD, U0_RXD, U0_RTS,

U0_CTS

0xFFFF FFFF Table 96

PINASSIGN1

PINASSIGN2

PINASSIGN3

PINASSIGN4

R/W

0x004

0x008

0x00C

0x010

Pin assign register 1. Assign movable

functions U0_SCLC, U1_TXD, U1_RXD

0xFFFF FFFF Table 97

0xFFFF FFFF Table 98

0xFFFF FFFF Table 99

0xFFFF FFFF Table 100

Pin assign register 2. Assign movable

functions U2_TXD, U2_RXD

Pin assignregister 3. Assign movable

function SPI0_SCK

Pin assign register 4. Assign movable

functions SPI0_MOSI, SPI0_MISO,

SPI0_SSEL, SPI1_SCK

PINASSIGN5

PINASSIGN6

R/W

0x014

0x018

Pin assign register 5. Assign movable

functions SPI1_MOSI, SPI1_MISO,

SPI1_SSEL, CTIN_0

0xFFFF FFFF Table 101

0xFFFF FFFF Table 102

Pin assign register 6. Assign movable

functions CTIN_1, CTIN_2, CTIN_3,

CTOUT_0

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Table 95. Register overview: Switch matrix (base address 0x4000 C000) …continued

Name

Access Offset

Description

Reset value

Reference

PINASSIGN7

R/W

0x01C

Pin assign egister 7. Assign movable

functions CTOUT_1, CTOUT_2, CTOUT_3,

I2C_SDA

0xFFFF FFFF Table 103

PINASSIGN8

R/W

0x020

Pin assign register 8. Assign movable

functions I2C_SCL, ACMP_O, CLKOUT,

GPIO_INT_BMAT

0xFFFF FFFF Table 104

-

0x024

0x1C0

Reserved

-

PINENABLE0

R/W

Pin enable register 0. Enables fixed-pin

functions ACMP_I0, ACMP_I1, SWCLK,

SWDIO, XTALIN, XTALOUT, RESET, CLKIN,

VDDCMP

0x1B3

Table 105

9.5.1 Pin assign register 0

Table 96. Pin assign register 0 (PINASSIGN0, address 0x4000 C000) bit description

Bit

Symbol

Description

Reset

value

7:0

U0_TXD_O U0_TXD function assignment. The value is the pin number to be 0xFF

assigned to this function. The following pins are available: PIO0_0

(= 0) to PIO0_17 (= 0x11).

15:8 U0_RXD_I

U0_RXD function assignment. The value is the pin number to be 0xFF

assigned to this function. The following pins are available: PIO0_0

(= 0) to PIO0_17 (= 0x11).

23:16 U0_RTS_O U0_RTS function assignment. The value is the pin number to be 0xFF

assigned to this function. The following pins are available: PIO0_0

(= 0) to PIO0_17 (= 0x11).

31:24 U0_CTS_I

U0_CTS function assignment. The value is the pin number to be 0xFF

assigned to this function. The following pins are available: PIO0_0

(= 0) to PIO0_17 (= 0x11).

9.5.2 Pin assign register 1

Table 97. Pin assign register 1 (PINASSIGN1, address 0x4000 C004) bit description

Bit

Symbol

Description

Reset

value

7:0

U0_SCLK_IO U0_SCLK function assignment. The value is the pin number to be 0xFF

assigned to this function. The following pins are available: PIO0_0

(= 0) to PIO0_17 (= 0x11).

15:8 U1_TXD_O

23:16 U1_RXD_I

31:24 U1_RTS_O

U1_TXD function assignment. The value is the pin number to be 0xFF

assigned to this function. The following pins are available: PIO0_0

(= 0) to PIO0_17 (= 0x11).

U1_RXD function assignment. The value is the pin number to be 0xFF

assigned to this function. The following pins are available: PIO0_0

(= 0) to PIO0_17 (= 0x11).

U1_RTS function assignment. The value is the pin number to be 0xFF

assigned to this function. The following pins are available: PIO0_0

(= 0) to PIO0_17 (= 0x11).

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9.5.3 Pin assign register 2

Table 98. Pin assign register 2 (PINASSIGN2, address 0x4000 C008) bit description

Bit

Symbol

Description

Reset

value

7:0

U1_CTS_I

U1_CTS function assignment. The value is the pin number to be 0xFF

assigned to this function. The following pins are available: PIO0_0

(= 0) to PIO0_17 (= 0x11).

15:8 U1_SCLK_IO U1_SCLK function assignment. The value is the pin number to be 0xFF

assigned to this function. The following pins are available: PIO0_0

(= 0) to PIO0_17 (= 0x11).

23:16 U2_TXD_O

U2_TXD function assignment. The value is the pin number to be 0xFF

assigned to this function. The following pins are available: PIO0_0

(= 0) to PIO0_17 (= 0x11).

31:24 U2_RXD_I

U2_RXD function assignment. The value is the pin number to be 0xFF

assigned to this function. The following pins are available: PIO0_0

(= 0) to PIO0_17 (= 0x11).

9.5.4 Pin assign register 3

Table 99. Pin assign register 3 (PINASSIGN3, address 0x4000 C00C) bit description

Bit

Symbol

Description

Reset

value

7:0

U2_RTS_O

U2_RTS function assignment. The value is the pin number to be 0xFF

assigned to this function. The following pins are available: PIO0_0

(= 0) to PIO0_17 (= 0x11).

15:8 U2_CTS_I

U2_CTS function assignment. The value is the pin number to be 0xFF

assigned to this function. The following pins are available: PIO0_0

(= 0) to PIO0_17 (= 0x11).

23:16 U2_SCLK_IO U2_SCLK function assignment. The value is the pin number to be 0xFF

assigned to this function. The following pins are available: PIO0_0

(= 0) to PIO0_17 (= 0x11).

31:24 SPI0_SCK_IO SPI0_SCK function assignment. The value is the pin number to

be assigned to this function. The following pins are available:

PIO0_0 (= 0) to PIO0_17 (= 0x11).

0xFF

9.5.5 Pin assign register 4

Table 100. Pin assign register 4 (PINASSIGN4, address 0x4000 C010) bit description

Bit

Symbol

Description

Reset

value

7:0

SPI0_MOSI_IO SPI0_MOSI function assignment. The value is the pin number to 0xFF

be assigned to this function. The following pins are available:

PIO0_0 (= 0) to PIO0_17 (= 0x11).

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Table 100. Pin assign register 4 (PINASSIGN4, address 0x4000 C010) bit description

Bit Symbol Description

Reset

value

15:8 SPI0_MISO_IO SPI0_MISIO function assignment. The value is the pin number 0xFF

to be assigned to this function. The following pins are available:

PIO0_0 (= 0) to PIO0_17 (= 0x11).

23:16 SPI0_SSEL_IO SPI0_SSEL function assignment. The value is the pin number to 0xFF

be assigned to this function. The following pins are available:

PIO0_0 (= 0) to PIO0_17 (= 0x11).

31:24 SPI1_SCK_IO SPI1_SCK function assignment. The value is the pin number to 0xFF

be assigned to this function. The following pins are available:

PIO0_0 (= 0) to PIO0_17 (= 0x11).

9.5.6 Pin assign register 5

Table 101. Pin assign register 5 (PINASSIGN5, address 0x4000 C014) bit description

Bit

Symbol

Description

Reset

value

7:0

SPI1_MOSI_IO SPI1_MOSI function assignment. The value is the pin number to 0xFF

be assigned to this function. The following pins are available:

PIO0_0 (= 0) to PIO0_17 (= 0x11).

15:8 SPI1_MISO_IO SPI1_MISIO function assignment. The value is the pin number 0xFF

to be assigned to this function. The following pins are available:

PIO0_0 (= 0) to PIO0_17 (= 0x11).

23:16 SPI1_SSEL_IO SPI1_SSEL function assignment. The value is the pin number to 0xFF

be assigned to this function. The following pins are available:

PIO0_0 (= 0) to PIO0_17 (= 0x11).

31:24 CTIN_0_I

CTIN_0 function assignment. The value is the pin number to be 0xFF

assigned to this function. The following pins are available:

PIO0_0 (= 0) to PIO0_17 (= 0x11).

9.5.7 Pin assign register 6

Table 102. Pin assign register 6 (PINASSIGN6, address 0x4000 C018) bit description

Bit

Symbol

Description

Reset

value

7:0

CTIN_1_I

CTIN_1 function assignment. The value is the pin number to be 0xFF

assigned to this function. The following pins are available:

PIO0_0 (= 0) to PIO0_17 (= 0x11).

15:8 CTIN_2_I

23:16 CTIN_3_I

31:24 CTOUT_0_O

CTIN_2function assignment. The value is the pin number to be 0xFF

assigned to this function. The following pins are available:

PIO0_0 (= 0) to PIO0_17 (= 0x11).

CTIN_3 function assignment. The value is the pin number to be 0xFF

assigned to this function. The following pins are available:

PIO0_0 (= 0) to PIO0_17 (= 0x11).

CTOUT_0 function assignment. The value is the pin number to 0xFF

be assigned to this function. The following pins are available:

PIO0_0 (= 0) to PIO0_17 (= 0x11).

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9.5.8 Pin assign register 7

Table 103. Pin assign register 7 (PINASSIGN7, address 0x4000 C01C) bit description

Bit

Symbol

Description

Reset

value

7:0

CTOUT_1_O

CTOUT_1 function assignment. The value is the pin number to 0xFF

be assigned to this function. The following pins are available:

PIO0_0 (= 0) to PIO0_17 (= 0x11).

15:8 CTOUT_2_O

23:16 CTOUT_3_O

31:24 I2C_SDA_IO

CTOUT_2 function assignment. The value is the pin number to 0xFF

be assigned to this function. The following pins are available:

PIO0_0 (= 0) to PIO0_17 (= 0x11).

CTOUT_3 function assignment. The value is the pin number to 0xFF

be assigned to this function. The following pins are available:

PIO0_0 (= 0) to PIO0_17 (= 0x11).

I2C_SDA function assignment. The value is the pin number to

be assigned to this function. The following pins are available:

PIO0_0 (= 0) to PIO0_17 (= 0x11).

0xFF

9.5.9 Pin assign register 8

Table 104. Pin assign register 8 (PINASSIGN8, address 0x4000 C020) bit description

Bit

Symbol

Description

Reset

value

7:0

I2C_SCL_IO

I2C_SCL function assignment. The value is the pin

number to be assigned to this function. The following pins

are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).

0xFF

15:8 ACMP_O_O

23:16 CLKOUT_O

ACMP_O_O function assignment. The value is the pin

number to be assigned to this function. The following pins

are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).

CLKOUT function assignment. The value is the pin

number to be assigned to this function. The following pins

are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).

31:24 GPIO_INT_BMAT_O GPIO_INT_BMAT function assignment. The value is the 0xFF

pin number to be assigned to this function. The following

pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).

9.5.10 Pin enable register 0

Table 105. Pin enable register 0 (PINENABLE0, address 0x4000 C1C0) bit description

Bit

Symbol

Value Description

Reset

value

0

ACMP_I1_EN

Enables fixed-pin function. Writing a 1 deselects the function and any movable

1

function can be assigned to this pin. By default the fixed--pin function is deselected

and GPIO is assigned to this pin.

0

1

Enable ACMP_I1. This function is enabled on pin PIO0_0.

Disable ACMP_I1. GPIO function PIO0_0 (default) or any other movable function

can be assigned to pin PIO0_0.

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Table 105. Pin enable register 0 (PINENABLE0, address 0x4000 C1C0) bit description

Bit

Symbol

Value Description

Reset

value

1

ACMP_I2_EN

Enables fixed-pin function. Writing a 1 deselects the function and any movable

1

function can be assigned to this pin. By default the fixed-pin function is deselected

and GPIO is assigned to this pin. Functions CLKIN and ACMP_I2 are connected to

the same pin PIO0_1. To use ACMP_I2, disable the CLKIN function in bit 7 of this

register and enable ACMP_I2.

0

1

Enable ACMP_I2. This function is enabled on pin PIO0_1.

Disable ACMP_I2. GPIO function PIO0_1 (default) or any other movable function

can be assigned to pin PIO0_1.

2

3

4

SWCLK_EN

SWDIO_EN

XTALIN_EN

Enables fixed-pin function. Writing a 1 deselects the function and any movable

function can be assigned to this pin. This function is selected by default.

0

1

0

1

Enable SWCLK. This function is enabled on pin PIO0_3.

Disable SWCLK. GPIO function PIO0_3 is selected on this pin. Any other movable

function can be assigned to pin PIO0_3.

Enables fixed-pin function. Writing a 1 deselects the function and any movable

function can be assigned to this pin. This function is selected by default.

0

1

Enable SWDIO. This function is enabled on pin PIO0_2.

Disable SWDIO. GPIO function PIO0_2 is selected on this pin. Any other movable

function can be assigned to pin PIO0_2.

Enables fixed-pin function. Writing a 1 deselects the function and any movable

function can be assigned to this pin. By default the fixed--pin function is deselected

and GPIO is assigned to this pin.

0

1

Enable XTALIN. This function is enabled on pin PIO0_8.

Disable XTALIN. GPIO function PIO0_8 (default) or any other movable function

can be assigned to pin PIO0_8.

5

XTALOUT_EN

Enables fixed-pin function. Writing a 1 deselects the function and any movable

function can be assigned to this pin. By default the fixed--pin function is deselected

and GPIO is assigned to this pin.

1

0

1

Enable XTALOUT. This function is enabled on pin PIO0_9.

Disable XTALOUT. GPIO function PIO0_9 (default) or any other movable function

can be assigned to pin PIO0_9.

6

7

RESET_EN

CLKIN

Enables fixed-pin function. Writing a 1 deselects the function and any movable

function can be assigned to this pin. This function is selected by default.

0

1

0

1

Enable RESET. This function is enabled on pin PIO0_5.

Disable RESET. GPIO function PIO0_5 is selected on this pin. Any other movable

function can be assigned to pin PIO0_5.

Enables fixed-pin function. Writing a 1 deselects the function and any movable

function can be assigned to this pin. By default the fixed-pin function is deselected

and GPIO is assigned to this pin. Functions CLKIN and ACMP_I2 are connected to

the same pin PIO0_1. To use CLKIN, disable ACMP_I2 in bit 1 of this register and

enable CLKIN.

0

1

Enable CLKIN. This function is enabled on pin PIO0_1.

Disable CLKIN. GPIO function PIO0_1 (default) or any other movable function can

be assigned to pin CLKIN.

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Table 105. Pin enable register 0 (PINENABLE0, address 0x4000 C1C0) bit description

Bit

Symbol

Value Description

Reset

value

8

VDDCMP

Enables fixed-pin function. Writing a 1 deselects the function and any movable

1

function can be assigned to this pin. By default the fixed--pin function is deselected

and GPIO is assigned to this pin.

0

1

Enable VDDCMP. This function is enabled on pin PIO0_6.

Disable VDDCMP. GPIO function PIO0_6 (default) or any other movable function

can be assigned to pin PIO0_6.

31:9

-

Reserved.

<tbd>

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Chapter 10: LPC800 State Configurable Timer (SCT)

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Preliminary user manual

10.1 How to read this chapter

The SCT is available on all LPC800 parts.

10.2 Features

• Two 16-bit counters or one 32-bit counter.

• Counters clocked by bus clock or selected input.

• Up counters or up-down counters.

• State variable allows sequencing across multiple counter cycles.

• The following conditions define an event: a counter match condition, an input (or

output) condition, a combination of a match and/or and input/output condition in a

specified state, and the count direction.

• Events control outputs, interrupts, and the SCT states.

– Match register 0 can be used as an automatic limit.

– In bi-directional mode, events can be enabled based on the count direction.

– Match events can be held until another qualifying event occurs.

• Selected events can limit, halt, start, or stop a counter.

• Supports:

– 4 inputs

– 4 outputs

– 5 match/capture registers

– 6 events

– 2 states

10.3 Basic configuration

Configure the SCT as follows:

• Use the SYSAHBCLKCTRL register (Table 18) to enable the clock to the SCT register

interface and peripheral clock. The LPC800 system clock is the input clock to the SCT

clock processing and is the source of the SCT clock.

• Clear the SCT peripheral reset using the PRESETCTRL register (Table 7).

• The SCT combined interrupt is connected to slot #8 in the NVIC.

• Use the switch matrix to connect the SCT inputs and outputs to pins (see

Section 10.4).

10.3.1 Use the SCT as a simple timer

To configure the SCT as a simple timer with match or capture functionality, follow these

steps:

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Chapter 10: LPC800 State Configurable Timer (SCT)

1. Set up the SCT as one 32-bit timer or one or two 16-bit timers. See Table 108.

2. Preload the 32-bit timer or the 16-bit timers with a count value. See Table 114.

3. If you want to create a match event when the timer reaches a match value:

a. Configure the register map for match registers. See Table 117.

b. Configure one or more match registers with a match value. See Table 125.

c. For each match value, create a match event. See Table 130.

d. If you want to create an interrupt on a match event, enable the event for interrupt.

See Table 122.

e. If you want to create a match output on a pin, connect the CTOUTn function to a

pin (see Section 10.4) and select an output for the match event in the EVn_CTRL

register. See Table 130. The EVn_CTRL registers also control what type of output

signal is created.

4. If you want to capture a timer value on a capture signal:

a. Configure the register map for capture registers. See Table 117.

b. Create one or more capture events. See Table 130.

c. Connect the CTIN functions to pins (see Section 10.4) and configure the signal to

create an event. See Table 130.

5. Start the timer by writing to the CRTL register. See Table 109.

6. Read the capture registers to read the timer value at the time of the capture events.

10.4 Pin description

The SCT inputs and outputs are movable functions and are assigned to external pins

through the switch matrix.

See Section 9.3.1 “Connect an internal signal to a package pin” to assign the SCT

functions to pins on the LPC800 package.

Table 106. SCT pin description

Function

CTIN_0

Direction Pin

Description

SCT input 0

SCT input 1

SCT input 2

SCT input 3

SCT output 0

SCT output 1

SCT output 2

SCT output 3

SWM register

PINASSIGN5

PINASSIGN6

PINASSIGN7

Reference

Table 101

Table 102

Table 103

I

any

CTIN_1

I

CTIN_2

I

CTIN_3

I

CTOUT_0

CTOUT_1

CTOUT_2

CTOUT_3

O

10.5 General description

The State Configurable Timer (SCT) allows a wide variety of timing, counting, output

modulation, and input capture operations.

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Chapter 10: LPC800 State Configurable Timer (SCT)

The most basic user-programmable option is whether a SCT operates as two 16-bit

counters or a unified 32-bit counter. In the two-counter case, in addition to the counter

value the following operational elements are independent for each half:

• State variable

• Limit, halt, stop, and start conditions

• Values of Match/Capture registers, plus reload or capture control values

In the two-counter case, the following operational elements are global to the SCT:

• Clock selection

• Inputs

• Events

• Outputs

• Interrupts

Events, outputs, and interrupts can use match conditions from either counter.

Remark: In this chapter, the term bus error indicates an SCT response that makes the

processor take an exception.

$D$(+<ꢈ!"#!ꢉ

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5)+$!%"+)A$B

Fig 8. SCT block diagram

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Chapter 10: LPC800 State Configurable Timer (SCT)

ꢀꢓꢋꢈ!"#!ꢉ

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5)+$!%"+)

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!#;&(+)

5)+$!%"+)

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Fig 9. SCT counter and select logic

10.6 Register description

The register addresses of the State Configurable Timer are shown in Table 107. For most

of the SCT registers, the register function depends on the setting of certain other register

bits:

1. The UNIFY bit in the CONFIG register determines whether the SCT is used as one

32-bit register (for operation as one 32-bit counter/timer) or as two 16-bit

counter/timers named L and H. The setting of the UNIFY bit is reflected in the register

map:

– UNIFY = 1: Only one register is used (for operation as one 32-bit counter/timer).

– UNIFY = 0: Access the L and H registers by a 32-bit read or write operation or can

be read or written to individually (for operation as two 16-bit counter/timers).

Typically, the UNIFY bit is configured by writing to the CONFIG register before any

other registers are accessed.

2. The REGMODEn bits in the REGMODE register determine whether each set of

Match/Capture registers uses the match or capture functionality:

– REGMODEn = 1: Registers operate as match and reload registers.

– REGMODEn = 0: Registers operate as capture and capture control registers.

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Table 107. Register overview: State Configurable Timer (base address 0x5000 4000)

Name

Access Address Description

offset

Reset value Reference

CONFIG

CTRL

R/W

-

0x000

0x004

0x006

0x008

0x00A

0x00C

0x00E

0x010

0x012

0x014

0x016

SCT configuration register

0x0000 7E00 Table 108

0x0004 0004 Table 109

SCT control register

CTRL_L

CTRL_H

LIMIT

SCT control register low counter 16-bit

SCT control register high counter 16-bit

SCT limit register

-

Table 109

0x0000 0000 Table 110

LIMIT_L

LIMIT_H

HALT

SCT limit register low counter 16-bit

SCT limit register high counter 16-bit

SCT halt condition register

-

Table 110

0x0000 0000 Table 111

HALT_L

HALT_H

STOP

SCT halt condition register low counter 16-bit

SCT halt condition register high counter 16-bit

SCT stop condition register

-

Table 111

0x0000 0000 Table 112

STOP_L

STOP_H

START

START_L

START_H

-

SCT stop condition register low counter 16-bit

SCT stop condition register high counter 16-bit

SCT start condition register

-

Table 112

0x0000 0000 Table 113

SCT start condition register low counter 16-bit

SCT start condition register high counter 16-bit

-

Table 113

-

0x018 - Reserved

0x03C

COUNT

R/W

RO

0x040

0x042

0x044

0x046

0x048

0x04C

SCT counter register

0x0000 0000 Table 114

COUNT_L

COUNT_H

STATE

SCT counter register low counter 16-bit

SCT counter register high counter 16-bit

SCT state register

-

Table 114

0x0000 0000 Table 115

STATE_L

STATE_H

INPUT

SCT state register low counter 16-bit

SCT state register high counter 16-bit

SCT input register

-

Table 115

0x0000 0000 Table 116

0x0000 0000 Table 117

REGMODE

REGMODE_L

R/W

SCT match/capture registers mode register

SCT match/capture registers mode register low

counter 16-bit

-

Table 117

REGMODE_H

R/W

0x04E

SCT match/capture registers mode register high

counter 16-bit

-

Table 117

OUTPUT

R/W

0x050

0x054

0x058

0x05C

0x060

SCT output register

0x0000 0000 Table 118

0x0000 0000 Table 119

0x0000 0000 Table 120

OUTPUTDIRCTRL

R/W

SCT output counter direction control register

RES

R/W

SCT conflict resolution register

-

0x064 - Reserved

0x0EC

EVEN

R/W

0x0F0

0x0F4

0x0F8

0x0FC

SCT event enable register

0x0000 0000 Table 121

0x0000 0000 Table 122

0x0000 0000 Table 123

0x0000 0000 Table 124

EVFLAG

CONEN

CONFLAG

SCT event flag register

SCT conflict enable register

SCT conflict flag register

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Table 107. Register overview: State Configurable Timer (base address 0x5000 4000) …continued

Name

Access Address Description

offset

Reset value Reference

MATCH0 to MATCH4 R/W

0x100 to SCT match value register of match channels 0 to 0x0000 0000 Table 124

0x110

4; REGMOD0 to REGMODE4 = 0

MATCH_L0 to

MATCH_L4

R/W

0x100 to SCT match value register of match channels 0 to

-

Table 124

0x110

4; low counter 16-bit; REGMOD0_L to

REGMODE4_L = 0

MATCH_H0 to

MATCH_H4

0x102 to SCT match value register of match channels 0 to

0x112

4; high counter 16-bit; REGMOD0_H to

REGMODE4_H = 0

CAP0 to CAP4

0x100 to SCT capture register of capture channel 0 to 4;

0x110 REGMOD0 to REGMODE4 = 1

0x0000 0000 Table 126

CAP_L0 to CAP_L4

0x100 to SCT capture register of capture channel 0 to 4;

-

Table 126

0x110

low counter 16-bit; REGMOD0_L to

REGMODE4_L = 1

CAP_H0 to CAP_H4

0x102 to SCT capture register of capture channel 0 to 4;

0x13E

high counter 16-bit; REGMOD0_H to

REGMODE4_H = 1

MATCHREL0 to

MATCHREL4

R/W

0x200 to SCT match reload value register 0 to 4

0x210 REGMOD0 = 0 to REGMODE4 = 0

0x0000 0000 Table 127

MATCHREL_L0 to

MATCHREL_L4

0x200 to SCT match reload value register 0 to 4; low

-

Table 127

0x210

counter 16-bit; REGMOD0_L = 0 to

REGMODE4_L = 0

MATCHREL_H0 to

MATCHREL_H4

R/W

0x202 to SCT match reload value register 0 to 4; high

0x212

counter 16-bit; REGMOD0_H = 0 to

REGMODE4_H = 0

CAPCTRL0 to

CAPCTRL4

0x200 to SCT capture control register 0 to 4; REGMOD0 = 0x0000 0000 Table 128

0x210 1 to REGMODE4 = 1

CAPCTRL_L0 to

CAPCTRL_L4

0x200 to SCT capture control register 0 to 4; low counter

0x210 16-bit; REGMOD0_L = 1 to REGMODE4_L = 1

-

Table 128

CAPCTRL_H0 to

CAPCTRL_H4

0x202 to SCT capture control register 0 to 4; high counter

-

Table 128

0x212

0x300

0x304

0x308

0x30C

0x310

0x314

0x318

0x31C

0x320

0x324

0x328

0x32C

0x500

0x504

0x508

16-bit; REGMOD0 = 1 to REGMODE4 = 1

SCT event 0 state register

SCT event 0 control register

SCT event 1 state register

SCT event 1 control register

SCT event 2 state register

SCT event 2 control register

SCT event 3 state register

SCT event 3 control register

SCT event 4 state register

SCT event 4 control register

SCT event 5 state register

SCT event 5 control register

SCT output 0 set register

EV0_STATE

EV0_CTRL

EV1_STATE

EV1_CTRL

EV2_STATE

EV2_CTRL

EV3_STATE

EV3_CTRL

EV4_STATE

EV4_CTRL

EV5_STATE

EV5_CTRL

OUT0_SET

OUT0_CLR

OUT1_SET

R/W

0x0000 0000 Table 129

0x0000 0000 Table 130

0x0000 0000 Table 129

0x0000 0000 Table 130

0x0000 0000 Table 129

0x0000 0000 Table 130

0x0000 0000 Table 129

0x0000 0000 Table 130

0x0000 0000 Table 129

0x0000 0000 Table 130

0x0000 0000 Table 129

0x0000 0000 Table 130

0x0000 0000 Table 131

0x0000 0000 Table 132

0x0000 0000 Table 131

SCT output 0 clear register

SCT output 1 set register

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Table 107. Register overview: State Configurable Timer (base address 0x5000 4000) …continued

Name

Access Address Description

offset

Reset value Reference

OUT1_CLR

OUT2_SET

OUT2_CLR

OUT3_SET

OUT3_CLR

R/W

0x50C

0x510

0x514

0x518

0x51C

SCT output 1 clear register

SCT output 2 set register

SCT output 2 clear register

SCT output 3 set register

SCT output 3 clear register

0x0000 0000 Table 132

0x0000 0000 Table 131

0x0000 0000 Table 132

0x0000 0000 Table 131

0x0000 0000 Table 132

10.6.1 SCT configuration register

This register configures the overall operation of the SCT. Write to this register before any

other registers.

Table 108. SCT configuration register (CONFIG, address 0x5000 4000) bit description

Bit

Symbol

Value Description

Reset

value

0

UNIFY

SCT operation

0

1

The SCT operates as two 16-bit counters named L and H.

The SCT operates as a unified 32-bit counter.

SCT clock mode

2:1

CLKMODE

0

0x0

0x1

The bus clock clocks the SCT and prescalers.

The SCT clock is the bus clock, but the prescalers are enabled to count only

when sampling of the input selected by the CKSEL field finds the selected

edge. The minimum pulse width on the clock input is 1 bus clock period. This

mode is the high-performance sampled-clock mode.

0x2

0x3

The input selected by CKSEL clocks the SCT and prescalers. The input is

synchronized to the bus clock and possibly inverted. The minimum pulse width

on the clock input is 1 bus clock period. This mode is the low-power

sampled-clock mode.

Reserved.

6:3

CKSEL

SCT clock select. All other values are reserved.

Rising edges on input 0.

Falling edges on input 0.

Rising edges on input 1.

Falling edges on input 1.

Rising edges on input 2.

Falling edges on input 2.

Rising edges on input 3.

Falling edges on input 3.

0

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

-

7

8

NORELAOD_L

NORELOAD_H

A 1 in this bit prevents the lower match registers from being reloaded from their

respective reload registers. Software can write to set or clear this bit at any

time. This bit applies to both the higher and lower registers when the UNIFY bit

is set.

0

-

A 1 in this bit prevents the higher match registers from being reloaded from their

respective reload registers. Software can write to set or clear this bit at any

time. This bit is not used when the UNIFY bit is set.

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Table 108. SCT configuration register (CONFIG, address 0x5000 4000) bit description …continued

Bit

Symbol

Value Description

Reset

value

16:9

INSYNC

-

Synchronization for input N (bit 9 = input 0, bit 10 = input 1,..., bit 16 = input 7). 1

A 1 in one of these bits subjects the corresponding input to synchronization to

the SCT clock, before it is used to create an event. If an input is synchronous to

the SCT clock, keep its bit 0 for faster response.

When the CKMODE field is 1x, the bit in this field, corresponding to the input

selected by the CKSEL field, is not used.

17

AUTOLIMIT_L

-

A one in this bit causes a match on match register 0 to be treated as a de-facto

LIMIT condition without the need to define an associated event.

As with any LIMIT event, this automatic limit causes the counter to be cleared to

zero in uni-directional mode or to change the direction of count in bi-directional

mode.

Software can write to set or clear this bit at any time. This bit applies to both the

higher and lower registers when the UNIFY bit is set.

18

AUTOLIMIT_H

-

A one in this bit will cause a match on match register 0 to be treated as a

de-facto LIMIT condition without the need to define an associated event.

As with any LIMIT event, this automatic limit causes the counter to be cleared to

zero in uni-directional mode or to change the direction of count in bi-directional

mode.

Software can write to set or clear this bit at any time. This bit is not used when

the UNIFY bit is set.

31:19

-

Reserved

-

10.6.2 SCT control register

If UNIFY = 1 in the CONFIG register, only the _L bits are used.

If UNIFY = 0 in the CONFIG register, this register can be written to as two registers

CTRL_L and CTRL_H. Both the L and H registers can be read or written individually or in

a single 32-bit read or write operation.

All bits in this register can be written to when the counter is stopped or halted. When the

counter is running, the only bits that can be written are STOP or HALT. (Other bits can be

written in a subsequent write after HALT is set to 1.)

Table 109. SCT control register (CTRL, address 0x5000 4004) bit description

Bit

Symbol

Value Description

Reset

value

0

DOWN_L

-

This bit is 1 when the L or unified counter is counting down. Hardware sets this bit

when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the

counter is counting down and a limit condition occurs or when the counter reaches 0.

0

1

2

STOP_L

HALT_L

When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events

related to the counter can occur. If such an event matches the mask in the Start

register, this bit is cleared and counting resumes.

When this bit is 1, the L or unified counter does not run and no events can occur. A

reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. If you

want to remove the halt condition and keep the SCT in the stop condition (not

running), then you can change the halt and stop condition with one single write to

this register.

Remark: Once set, only software can clear this bit to restore counter operation.

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Table 109. SCT control register (CTRL, address 0x5000 4004) bit description

Bit

Symbol

Value Description

Reset

value

3

4

CLRCTR_L

BIDIR_L

-

Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0.

0

L or unified counter direction select

0

1

-

The counter counts up to its limit condition, then is cleared to zero.

The counter counts up to its limit, then counts down to a limit condition or to 0.

12:5

PRE_L

Specifies the factor by which the SCT clock is prescaled to produce the L or unified

counter clock. The counter clock is clocked at the rate of the SCT clock divided by

PRE_L+1.

0

Remark: Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing

the PRE value.

15:13

16

-

Reserved

DOWN_H

-

This bit is 1 when the H counter is counting down. Hardware sets this bit when the

counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter is

counting down and a limit condition occurs or when the counter reaches 0.

0

1

17

18

STOP_H

HALT_H

When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related

to the counter can occur. If such an event matches the mask in the Start register, this

bit is cleared and counting resumes.

When this bit is 1, the H counter does not run and no events can occur. A reset sets

this bit. When the HALT_H bit is one, the STOP_H bit is cleared. If you want to

remove the halt condition and keep the SCT in the stop condition (not running), then

you can change the halt and stop condition with one single write to this register.

Remark: Once set, this bit can only be cleared by software to restore counter

operation.

19

20

CLRCTR_H -

BIDIR_H

Writing a 1 to this bit clears the H counter. This bit always reads as 0.

Direction select

0

The H counter counts up to its limit condition, then is cleared to zero.

The H counter counts up to its limit, then counts down to a limit condition or to 0.

1

-

28:21 PRE_H

Specifies the factor by which the SCT clock is prescaled to produce the H counter

clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1.

0

Remark: Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing

the PRE value.

31:29

-

Reserved

10.6.3 SCT limit register

If UNIFY = 1 in the CONFIG register, only the _L bits are used.

If UNIFY = 0 in the CONFIG register, this register can be written to as two registers

LIMIT_L and LIMIT_H. Both the L and H registers can be read or written individually or in

a single 32-bit read or write operation.

The bits in this register set which events act as counter limits. When a limit event occurs,

the counter is cleared to zero in unidirectional mode or changes the direction of count in

bidirectional mode. When the counter reaches all ones, this state is always treated as a

limit event, and the counter is cleared in unidirectional mode or, in bidirectional mode,

begins counting down on the next clock edge - even if no limit event as defined by the

SCT limit register has occurred.

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Note that in addition to using this register to specify events that serve as limits, it is also

possible to automatically cause a limit condition whenever a match register 0 match

occurs. This eliminates the need to define an event for the sole purpose of creating a limit.

The AUTOLIMITL and AUTOLIMITH bits in the configuration register enable/disable this

feature (see Table 108).

Table 110. SCT limit register (LIMIT, address 0x5000 4008) bit description

Bit

Symbol

Description

Reset

value

5:0

LIMMSK_L

If bit n is one, event n is used as a counter limit for the L or

0

unified counter (event 0 = bit 0, event 1 = bit 1, event 5 = bit

5).

15:6

-

Reserved.

-

20:16 LIMMSK_H

If bit n is one, event n is used as a counter limit for the H

counter (event 0 = bit 16, event 1 = bit 17, event 5 = bit 20).

0

31:21

-

Reserved.

-

10.6.4 SCT halt condition register

If UNIFY = 1 in the CONFIG register, only the _L bits are used.

If UNIFY = 0 in the CONFIG register, this register can be written to as two registers

HALT_L and HALT_H. Both the L and H registers can be read or written individually or in a

single 32-bit read or write operation.

Remark: Any event halting the counter disables its operation until software clears the

HALT bit (or bits) in the CTRL register (Table 109).

Table 111. SCT halt condition register (HALT, address 0x5004 400C) bit description

Bit

Symbol

Description

Reset

value

5:0

HALTMSK_L

-

If bit n is one, event n sets the HALT_L bit in the CTRL register

(event 0 = bit 0, event 1 = bit 1, event 5 = bit 5).

0

15:6

Reserved.

-

20:16 HALTMSK_H

If bit n is one, event n sets the HALT_H bit in the CTRL register

(event 0 = bit 16, event 1 = bit 17, event 5 = bit 20).

0

31:21

-

Reserved.

-

10.6.5 SCT stop condition register

If UNIFY = 1 in the CONFIG register, only the _L bits are used.

If UNIFY = 0 in the CONFIG register, this register can be written to as two registers

STOPT_L and STOP_H. Both the L and H registers can be read or written individually or

in a single 32-bit read or write operation.

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Table 112. SCT stop condition register (STOP, address 0x5000 4010) bit description

Bit

Symbol

Description

Reset

value

5:0

STOPMSK_L

If bit n is one, event n sets the STOP_L bit in the CTRL register

(event 0 = bit 0, event 1 = bit 1, event 5 = bit 5).

0

15:6

-

Reserved.

-

20:16 STOPMSK_H

If bit n is one, event n sets the STOP_H bit in the CTRL register

(event 0 = bit 16, event 1 = bit 17, event 5 = bit 20).

0

31:21 -

Reserved.

-

10.6.6 SCT start condition register

If UNIFY = 1 in the CONFIG register, only the _L bits are used.

If UNIFY = 0 in the CONFIG register, this register can be written to as two registers

START_L and START_H. Both the L and H registers can be read or written individually or

in a single 32-bit read or write operation.

The bits in this register select which events, if any, clear the STOP bit in the Control

register. (Since no events can occur when HALT is 1, only software can clear the HALT bit

by writing the Control register.)

Table 113. SCT start condition register (START, address 0x5000 4014) bit description

Bit

Symbol

Description

Reset

value

5:0

STARTMSK_L

If bit n is one, event n clears the STOP_L bit in the CTRL

register (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5).

0

15:6

-

Reserved.

-

20:16 STARTMSK_H

If bit n is one, event n clears the STOP_H bit in the CTRL

register (event 0 = bit 16, event 1 = bit 17, event 5 = bit 20).

0

31:21 -

Reserved.

-

10.6.7 SCT counter register

If UNIFY = 1 in the CONFIG register, the counter is a unified 32-bit register and both the

_L and _H bits are used.

If UNIFY = 0 in the CONFIG register, this register can be written to as two registers

COUNT_L and COUNT_H. Both the L and H registers can be read or written individually

or in a single 32-bit read or write operation. In this case, the L and H registers count

independently under the control of the other registers.

Attempting to write a counter while it is running does not affect the counter but produces a

bus error. Software can read the counter registers at any time.

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Table 114. SCT counter register (COUNT, address 0x5000 4040) bit description

Bit

Symbol

Description

Reset

value

15:0

CTR_L

When UNIFY = 0, read or write the 16-bit L counter value. When

UNIFY = 1, read or write the lower 16 bits of the 32-bit unified

counter.

0

31:16 CTR_H

When UNIFY = 0, read or write the 16-bit H counter value. When

UNIFY = 1, read or write the upper 16 bits of the 32-bit unified

counter.

0

10.6.8 SCT state register

If UNIFY = 1 in the CONFIG register, only the _L bits are used.

If UNIFY = 0 in the CONFIG register, this register can be written to as two registers

STATE_L and STATE_H. Both the L and H registers can be read or written individually or

in a single 32-bit read or write operation.

Software can read the state associated with a counter at any time. Writing the state is only

allowed when the counter HALT bit is 1; when HALT is 0, a write attempt does not change

the state and results in a bus error.

The state variable is the main feature that distinguishes the SCT from other counter/timer/

PWM blocks. Events can be made to occur only in certain states. Events, in turn, can

perform the following actions:

• set and clear outputs

• limit, stop, and start the counter

• cause interrupts

• modify the state variable

The value of a state variable is completely under the control of the application. If an

application does not use states, the value of the state variable remains zero, which is the

default value.

A state variable can be used to track and control multiple cycles of the associated counter

in any desired operational sequence. The state variable is logically associated with a state

machine diagram which represents the SCT configuration. See Section 10.6.22 and

10.6.23 for more about the relationship between states and events.

The STATELD/STADEV fields in the event control registers of all defined events set all

possible values for the state variable. The change of the state variable during multiple

counter cycles reflects how the associated state machine moves from one state to the

next.

Table 115. SCT state register (STATE, address 0x5000 4044) bit description

Bit

Symbol

Description

Reset

value

4:0

STATE_L

-

State variable.

Reserved.

0

-

15:5

20:16 STATE_H

31:21

State variable.

Reserved.

0

-

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10.6.9 SCT input register

Software can read the state of the SCT inputs in this read-only register in two slightly

different forms. The only situation in which these values are different is if CLKMODE = 2 in

the CONFIG register.

Table 116. SCT input register (INPUT, address 0x5000 4048) bit description

Bit

Symbol

Description

Reset

value

0

AIN0

AIN1

AIN2

AIN3

-

Real-time status of input 0.

1

Real-time status of input 1.

2

Real-time status of input 2.

3

Real-time status of input 3.

15:4

16

17

18

19

31:20

Reserved.

-

SIN0

SIN1

SIN2

SIN3

-

Input 0 state synchronized to the SCT clock.

Input 1 state synchronized to the SCT clock.

Input 2 state synchronized to the SCT clock.

Input 3 state synchronized to the SCT clock.

Reserved

10.6.10 SCT match/capture registers mode register

If UNIFY = 1 in the CONFIG register, only the _L bits of this register are used. The L bits

control whether each set of match/capture registers operates as unified 32-bit

capture/match registers.

If UNIFY = 0 in the CONFIG register, this register can be written to as two registers

REGMODE_L and REGMODE_H. Both the L and H registers can be read or written

individually or in a single 32-bit read or write operation.The _L bits/registers control the L

match/capture registers, and the _H bits/registers control the H match/capture registers.

The SCT contains 5 Match/Capture register pairs. The Register Mode register selects

whether each register pair acts as a Match register (see Section 10.6.18) or as a Capture

register (see Section 10.6.19). Each Match/Capture register has an accompanying

register which serves as a Reload register when the register is used as a Match register

(Section 10.6.20) or as a Capture-Control register when the register is used as a capture

register (Section 10.6.21). REGMODE_H is used only when the UNIFY bit is 0.

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Table 117. SCT match/capture registers mode register (REGMODE, address 0x5000 404C)

bit description

Bit

Symbol

Description

Reset

value

4:0

REGMOD_L

Each bit controls one pair of match/capture registers (register 0 =

bit 0, register 1 = bit 1,..., register 4 = bit 4).

0

0 = registers operate as match registers.

1 = registers operate as capture registers.

Reserved.

15:5

-

19:16 REGMOD_H Each bit controls one pair of match/capture registers (register 0 =

bit 16, register 1 = bit 17,..., register 4 = bit 19).

0

0 = registers operate as match registers.

1 = registers operate as capture registers.

31:20 -

Reserved.

-

10.6.11 SCT output register

The SCT supports 4 outputs, each of which has a corresponding bit in this register.

Software can write to any of the output registers when both counters are halted to control

the outputs directly. Writing to this register when either counter is stopped or running does

not affect the outputs and results in an bus error.

Software can read this register at any time to sense the state of the outputs.

Table 118. SCT output register (OUTPUT, address 0x5000 4050) bit description

Bit

Symbol

Description

Reset

value

3:0

OUT

Writing a 1 to bit n makes the corresponding output HIGH. 0 makes

the corresponding output LOW (output 0 = bit 0, output 1 = bit 1,...,

output 3 = bit 3).

0

31:4

-

Reserved

10.6.12 SCT bidirectional output control register

This register specifies (for each output) the impact of the counting direction on the

meaning of set and clear operations on the output (see Section 10.6.24 and

Section 10.6.25).

Table 119. SCT bidirectional output control register (OUTPUTDIRCTRL, address 0x5000 4054) bit description

Bit Symbol

Value Description

Reset

value

1:0 SETCLR0

Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.

0

0x0

0x1

0x2

Set and clear do not depend on any counter.

Set and clear are reversed when counter L or the unified counter is counting down.

Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.

Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value.

Set and clear do not depend on any counter.

3:2 SETCLR1

0

0x0

0x1

0x2

Set and clear are reversed when counter L or the unified counter is counting down.

Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.

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Table 119. SCT bidirectional output control register (OUTPUTDIRCTRL, address 0x5000 4054) bit description

Bit Symbol

Value Description

Reset

value

5:4 SETCLR2

Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.

0

-

0x0

0x1

0x2

Set and clear do not depend on any counter.

Set and clear are reversed when counter L or the unified counter is counting down.

Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.

Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value.

Set and clear do not depend on any counter.

7:6 SETCLR3

0x0

0x1

0x2

Set and clear are reversed when counter L or the unified counter is counting down.

Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.

Reserved

31:8 -

10.6.13 SCT conflict resolution register

The registers OUTn_SETn (Section 10.6.24) and OUTnCLRn (Section 10.6.25) allow

both setting and clearing to be indicated for an output in the same clock cycle, even for the

same event. This SCT conflict resolution register resolves this conflict.

To enable an event to toggle an output, set the OnRES value to 0x3 in this register, and

set the event bits in both the Set and Clear registers.

Table 120. SCT conflict resolution register (RES, address 0x5000 4058) bit description

Bit

Symbol

Value Description

Reset

value

1:0

O0RES

Effect of simultaneous set and clear on output 0.

No change.

0

-

0x0

0x1

0x2

0x3

Set output (or clear based on the SETCLR0 field).

Clear output (or set based on the SETCLR0 field).

Toggle output.

3:2

O1RES

O2RES

O3RES

-

Effect of simultaneous set and clear on output 1.

No change.

0x0

0x1

0x2

0x3

Set output (or clear based on the SETCLR1 field).

Clear output (or set based on the SETCLR1 field).

Toggle output.

5:4

Effect of simultaneous set and clear on output 2.

No change.

0x0

0x1

0x2

0x3

Set output (or clear based on the SETCLR2 field).

Clear output n (or set based on the SETCLR2 field).

Toggle output.

7:6

Effect of simultaneous set and clear on output 3.

No change.

0x0

0x1

0x2

0x3

-

Set output (or clear based on the SETCLR3 field).

Clear output (or set based on the SETCLR3 field).

Toggle output.

31:8

Reserved

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10.6.14 SCT flag enable register

This register enables flags to request an interrupt if the FLAGn bit in the SCT event flag

register (Section 10.6.15) is also set.

Table 121. SCT flag enable register (EVEN, address 0x5000 40F0) bit description

Bit

Symbol

Description

Reset

value

5:0

IEN

The SCT requests an interrupt when bit n of this register and the

event flag register are both one (event 0 = bit 0, event 1 = bit 1,...,

event 5 = bit 5).

0

31:6

-

Reserved

10.6.15 SCT event flag register

This register records events. Writing ones to this register clears the corresponding flags

and negates the SCT interrupt request if all enabled Flag bits are zero.

Table 122. SCT event flag register (EVFLAG, address 0x5000 40F4) bit description

Bit

Symbol Description

Reset

value

5:0

FLAG

-

Bit n is one if event n has occurred since reset or a 1 was last written to

this bit (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5).

0

31:6

Reserved

-

10.6.16 SCT conflict enable register

This register enables the “no change conflict” events specified in the SCT conflict

resolution register to request an IRQ.

Table 123. SCT conflict enable register (CONEN, address 0x5000 40F8) bit description

Bit

Symbol Description

Reset

value

3:0

NCEN

-

The SCT requests interrupt when bit n of this register and the SCT

conflict flag register are both one (output 0 = bit 0, output 1 = bit

1,..., output 3 = bit 3).

0

31:4

Reserved

10.6.17 SCT conflict flag register

This register records interrupt-enabled no-change conflict events and provides details of a

bus error. Writing ones to the NCFLAG bits clears the corresponding read bits and

negates the SCT interrupt request if all enabled Flag bits are zero.

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Table 124. SCT conflict flag register (CONFLAG, address 0x5000 40FC) bit description

Bit

Symbol

Description

Reset

value

3:0

NCFLAG

Bit n is one if a no-change conflict event occurred on output n

since reset or a 1 was last written to this bit (output 0 = bit 0,

output 1 = bit 1,..., output 3 = bit 3).

0

29:4

30

-

Reserved.

-

BUSERRL The most recent bus error from this SCT involved writing CTR

L/Unified, STATE L/Unified, MATCH L/Unified, or the Output

register when the L/U counter was not halted. A word write to

certain L and H registers can be half successful and half

unsuccessful.

0

31

BUSERRH The most recent bus error from this SCT involved writing CTR

H, STATE H, MATCH H, or the Output register when the H

counter was not halted.

0

10.6.18 SCT match registers 0 to 4 (REGMODEn bit = 0)

Match registers are compared to the counters to help create events. When the UNIFY bit

is 0, the L and H registers are independently compared to the L and H counters. When

UNIFY is 1, the L and H registers hold a 32-bit value that is compared to the unified

counter. A Match can only occur in a clock in which the counter is running (STOP and

HALT are both 0).

Match registers can be read at any time. Writing to a Match register while the associated

counter is running does not affect the Match register and results in a bus error. Match

events occur in the SCT clock in which the counter is (or would be) incremented to the

next value. When a Match event limits its counter as described in Section 10.6.3, the

value in the Match register is the last value of the counter before it is cleared to zero (or

decremented if BIDIR is 1).

There is no “write-through” from Reload registers to Match registers. Before starting a

counter, software can write one value to the Match register used in the first cycle of the

counter and a different value to the corresponding Match Reload register used in the

second cycle.

Table 125. SCT match registers 0 to 4 (MATCH[0:4], address 0x5000 4100 (MATCH0) to

0x5000 4110 (MATCH4)) bit description (REGMODEn bit = 0)

Bit

Symbol

Description

Reset

value

15:0

VALMATCH_L When UNIFY = 0, read or write the 16-bit value to be compared

to the L counter. When UNIFY = 1, read or write the lower 16

0

bits of the 32-bit value to be compared to the unified counter.

31:16 VALMATCH_H When UNIFY = 0, read or write the 16-bit value to be compared

to the H counter. When UNIFY = 1, read or write the upper 16

0

bits of the 32-bit value to be compared to the unified counter.

10.6.19 SCT capture registers 0 to 4 (REGMODEn bit = 1)

These registers allow software to read the counter values at which the event selected by

the corresponding Capture Control registers occurred.

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Table 126. SCT capture registers 0 to 4 (CAP[0:4], address 0x5000 4100 (CAP0) to 0x5000

4110 (CAP4)) bit description (REGMODEn bit = 1)

Bit

Symbol

Description

Reset

value

15:0

VALCAP_L When UNIFY = 0, read the 16-bit counter value at which this

register was last captured. When UNIFY = 1, read the lower 16 bits

of the 32-bit value at which this register was last captured.

0

31:16 VALCAP_H When UNIFY = 0, read the 16-bit counter value at which this

register was last captured. When UNIFY = 1, read the upper 16 bits

of the 32-bit value at which this register was last captured.

0

10.6.20 SCT match reload registers 0 to 4 (REGMODEn bit = 0)

A Match register (L, H, or unified 32-bit) is loaded from the corresponding Reload register

when BIDIR is 0 and the counter reaches its limit condition, or when BIDIR is 1 and the

counter reaches 0.

Table 127. SCT match reload registers 0 to 4 (MATCHREL[0:4], address 0x5000 4200

(MATCHREL0) to 0x5000 4210 (MATCHREL4) bit description (REGMODEn bit = 0)

Bit

Symbol

Description

Reset

value

15:0 RELOAD_L When UNIFY = 0, read or write the 16-bit value to be loaded into

the SCTMATCHn_L register. When UNIFY = 1, read or write the

lower 16 bits of the 32-bit value to be loaded into the MATCHn

register.

0

31:16 RELOAD_H When UNIFY = 0, read or write the 16-bit to be loaded into the

MATCHn_H register. When UNIFY = 1, read or write the upper 16

bits of the 32-bit value to be loaded into the MATCHn register.

0

10.6.21 SCT capture control registers 0 to 4 (REGMODEn bit = 1)

If UNIFY = 1 in the CONFIG register, only the _L bits are used.

If UNIFY = 0 in the CONFIG register, this register can be written to as two registers

CAPCTRLn_L and CAPCTRLn_H. Both the L and H registers can be read or written

individually or in a single 32-bit read or write operation.

Each Capture Control register (L, H, or unified 32-bit) controls which events load the

corresponding Capture register from the counter.

Table 128. SCT capture control registers 0 to 4 (CAPCTRL[0:4], address 0x5000 4200

(CAPCTRL0) to 0x5000 4210 (CAPCTRL4)) bit description (REGMODEn bit = 1)

Bit

Symbol

Description

Reset

value

5:0

CAPCONm_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the

CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1

= bit 1,..., event 5 = bit 5).

0

15:6

-

Reserved.

-

20:16 CAPCONm_H If bit m is one, event m causes the CAPn_H (UNIFY = 0)

register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event

5 = bit 20).

0

31:17

-

Reserved.

-

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10.6.22 SCT event state mask registers 0 to 5

Each event has one associated SCT event state mask register that allow this event to

happen in one or more states of the counter selected by the HEVENT bit in the

corresponding EVn_CTRL register.

An event n is disabled when its EVn_STATE register contains all zeros, since it is masked

regardless of the current state.

In simple applications that do not use states, write 0x01 to this register to enable an event.

Since the state always remains at its reset value of 0, writing 0x01 permanently

state-enables this event.

Table 129. SCT event state mask registers 0 to 5 (EV[0:5]_STATE, addresses 0x5000 4300

(EV0_STATE) to 0x5000 4328 (EV5_STATE)) bit description

Bit

Symbol

Description

Reset

value

1:0

STATEMSKm If bit m is one, event n (n= 0 to 5) happens in state m of the

counter selected by the HEVENT bit (m = state number; state 0 =

bit 0, state 1= bit 1).

0

31:2

-

Reserved.

-

10.6.23 SCT event control registers 0 to 5

This register defines the conditions for event n to occur, other than the state variable

which is defined by the state mask register. Most events are associated with a particular

counter (high, low, or unified), in which case the event can depend on a match to that

register. The other possible ingredient of an event is a selected input or output signal.

When the UNIFY bit is 0, each event is associated with a particular counter by the

HEVENT bit in its event control register. An event cannot occur when its related counter is

halted nor when the current state is not enabled to cause the event as specified in its

event mask register. An event is permanently disabled when its event state mask register

contains all 0s.

An enabled event can be programmed to occur based on a selected input or output edge

or level and/or based on its counter value matching a selected match register (STOP bit =

0). An event can be enabled by the event counter’s HALT bit and STATE register. In

bi-directional mode, events can also be enabled based on the direction of count.

Each event can modify its counter STATE value. If more than one event associated with

the same counter occurs in a given clock cycle, only the state change specified for the

highest-numbered event among them takes place. Other actions dictated by any

simultaneously occurring events all take place.

Table 130. SCT event control register 0 to 5 (EV[0:5]_CTRL, address 0x5000 4304 (EV0_CTRL) to 0x5000 432C

(EV5_CTRL)) bit description

Bit

Symbol

Value Description

Reset

value

3:0

MATCHSEL

-

Selects the Match register associated with this event (if any). A match can occur only

0

when the counter selected by the HEVENT bit is running.

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Table 130. SCT event control register 0 to 5 (EV[0:5]_CTRL, address 0x5000 4304 (EV0_CTRL) to 0x5000 432C

(EV5_CTRL)) bit description

Bit

Symbol

Value Description

Reset

value

4

HEVENT

Select L/H counter. Do not set this bit if UNIFY = 1.

0

1

Selects the L state and the L match register selected by MATCHSEL.

Selects the H state and the H match register selected by MATCHSEL.

Input/output select

5

OUTSEL

IOSEL

0

1

-

Selects the inputs elected by IOSEL.

Selects the outputs selected by IOSEL.

9:6

Selects the input or output signal associated with this event (if any). Do not select an

input in this register, if CKMODE is 1x. In this case the clock input is an implicit

ingredient of every event.

Bit 6 = 1: CTIN1/CTOUT0 selected.

Bit 7 = 1: CTIN1/CTOU1 selected.

Bit 8 = 1: CTIN2/CTOUT2 selected.

BIt 9 = 1: CTIN3/CTOUT3 selected.

11:10 IOCOND

Selects the I/O condition for event n. (The detection of edges on outputs lag the

conditions that switch the outputs by one SCT clock). In order to guarantee proper

edge/state detection, an input must have a minimum pulse width of at least one SCT

clock period .

0

0x0

0x1

0x2

0x3

LOW

Rise

Fall

HIGH

13:12 COMBMODE

Selects how the specified match and I/O condition are used and combined.

OR. The event occurs when either the specified match or I/O condition occurs.

MATCH. Uses the specified match only.

0x0

0x1

0x2

0x3

IO. Uses the specified I/O condition only.

AND. The event occurs when the specified match and I/O condition occur

simultaneously.

14

STATELD

This bit controls how the STATEV value modifies the state selected by HEVENT when

this event is the highest-numbered event occurring for that state.

0

1

STATEV value is added into STATE (the carry-out is ignored).

STATEV value is loaded into STATE.

19:15 STATEV

This value is loaded into or added to the state selected by HEVENT, depending on

STATELD, when this event is the highest-numbered event occurring for that state. If

STATELD and STATEV are both zero, there is no change to the STATE value.

20

MATCHMEM

If this bit is one and the COMBMODE field specifies a match component to the

triggering of this event, then a match is considered to be active whenever the counter

value is GREATER THAN OR EQUAL TO the value specified in the match register

when counting up, LESS THEN OR EQUAL TO the match value when counting down.

If this bit is zero, a match is only be active during the cycle when the counter is equal

to the match value.

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Table 130. SCT event control register 0 to 5 (EV[0:5]_CTRL, address 0x5000 4304 (EV0_CTRL) to 0x5000 432C

(EV5_CTRL)) bit description

Bit

Symbol

Value Description

Reset

value

22:21 DIRECTION

Direction qualifier for event generation. This field only applies when the counters are

operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is

reserved.

0x0

0x1

0x2

Direction independent. This event is triggered regardless of the count direction.

Counting up. This event is triggered only during up-counting when BIDIR = 1.

Counting down. This event is triggered only during down-counting when BIDIR = 1.

Reserved

31:23 -

10.6.24 SCT output set registers 0 to 3

Each output n has one set register that controls how events affect each output. Whether

outputs are set or cleared depends on the setting of the SETCLRn field in the

SCTOUTPUTDIRCTRL register.

Table 131. SCT output set register (OUT[0:3]_SET, address 0x5000 4500 (OUT0_SET) to

0x5000 4518 (OUT3_SET)) bit description

Bit

Symbol

Description

Reset

value

5:0

SET

-

A 1 in bit m selects event m to set output n (or clear it if SETCLRn =

0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5.

0

31:6

Reserved

10.6.25 SCT output clear registers 0 to 3

Each output n has one clear register that controls how events affect each output. Whether

outputs are set or cleared depends on the setting of the SETCLRn field in the

OUTPUTDIRCTRL register.

Table 132. SCT output clear register (OUT[0:3]_CLR, address 0x5000 0504 (OUT0_CLR) to

0x5000 051C (OUT3_CLR)) bit description

Bit

Symbol

Description

Reset

value

5:0

CLR

-

A 1 in bit m selects event m to clear output n (or set it if SETCLRn =

0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5.

0

31:6

Reserved

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10.7 Functional description

10.7.1 Match logic

ꢓ#;&(+)ꢈꢕ

ꢃ%(!7

ꢁ+"#%'ꢈ

6ꢈꢕ

ꢃ%(!7

ꢃ%(!7ꢈ6ꢈꢕ

ꢃ%(!7ꢈ6ꢈꢔ

I

ꢁ+=ꢈ6ꢈꢕ

ꢎꢑꢐꢒ

ꢃ%(!7

ꢁ+"#%'ꢈ

6ꢈꢔ

ꢃ%(!7

ꢁ+=ꢈ6ꢈꢔ

ꢓ#;&(+)ꢈꢔ

Fig 10. Match logic

10.7.2 Capture logic

ꢀꢓꢋꢈ!"#!ꢉ

ꢈ

Fig 11. Capture logic

10.7.3 Event selection

State variables allow control of the SCT across more than one cycle of the counter.

Counter matches, input/output edges, and state values are combined into a set of

general-purpose events that can switch outputs, request interrupts, and change state

values.

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ꢕꢈ<%(!7+$

ꢔꢈ<%(!7+$

$+"+!(

ꢃꢂꢋꢓꢕꢀꢌꢔ6

6&5;($

#;(5;($

+*+&(ꢈO6P

$+"+!(

ꢐꢚꢀꢌꢔ6

ꢚꢎꢋꢀꢌꢔ6

ꢐꢚꢓꢚꢑꢍ6

ꢓꢚꢃꢊꢃꢚꢍꢌ6

ꢀꢋꢂꢋꢌꢃꢂꢀꢛ6

$+"+!(

ꢕꢈꢀꢋꢂꢋꢌ

ꢔꢈꢀꢋꢂꢋꢌ

ꢕꢌ4ꢌꢑꢋ6

Fig 12. Event selection

10.7.4 Output generation

Figure 13 shows one output slice of the SCT.

ꢌ*+&($

ꢑ#ꢓ7%&=+ꢓ#&9"6!(ꢈO6P

ꢀ+(ꢈ

)+=6$(+)ꢈO6P

ꢀꢌꢋꢓꢔꢁ6

ꢀ+"+!(

ꢚꢎꢋꢈ

ꢚ;(5;(ꢈO6P

)+=

ꢚ6ꢁꢌꢀ

ꢓ"+%)ꢈ

)+=6$(+)ꢈO6P

ꢀꢓꢋꢈ!"#!ꢉ

Fig 13. Output slice i

10.7.5 Interrupt generation

The SCT generates one interrupt to the NVIC.

ꢌ*+&($

ꢌ&%C"+

)+=6$(+)

ꢒ"%=$

)+=6$(+)

ꢀꢓꢋꢈ6&(+));5(

ꢓ#&9"6!(

ꢑ#ꢈꢓ7%&=+ꢈ

ꢓ#&9"6!(ꢈ

ꢌ&%C"+

)+=6$(+)

ꢓ#&9"6!(ꢈ+*+&($

ꢒ"%=$

)+=6$(+)

Fig 14. SCT interrupt generation

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Chapter 10: LPC800 State Configurable Timer (SCT)

10.7.6 Clearing the prescaler

When enabled by a non-zero PRE field in the Control register, the prescaler acts as a

clock divider for the counter, like a fractional part of the counter value. The prescaler is

cleared whenever the counter is cleared or loaded for any of the following reasons:

• Hardware reset

• Software writing to the counter register

• Software writing a 1 to the CLRCTR bit in the control register

• an event selected by a 1 in the counter limit register when BIDIR = 0

When BIDIR is 0, a limit event caused by an I/O signal can clear a non-zero prescaler.

However, a limit event caused by a Match only clears a non-zero prescaler in one special

case as described Section 10.7.7.

A limit event when BIDIR is 1 does not clear the prescaler. Rather it clears the DOWN bit

in the Control register, and decrements the counter on the same clock if the counter is

enabled in that clock.

10.7.7 Match vs. I/O events

Counter operation is complicated by the prescaler and by clock mode 01 in which the SCT

clock is the bus clock. However, the prescaler and counter are enabled to count only when

a selected edge is detected on a clock input.

• The prescaler is enabled when the clock mode is not 01, or when the input edge

selected by the CLKSEL field is detected.

• The counter is enabled when the prescaler is enabled, and (PRELIM=0 or the

prescaler is equal to the value in PRELIM).

An I/O component of an event can occur in any SCT clock when its counter HALT bit is 0.

In general, a Match component of an event can only occur in a UT clock when its counter

HALT and STOP bits are both 0 and the counter is enabled.

Table 133 shows when the various kinds of events can occur.

Table 133. Event conditions

COMBMODE IOMODE

Event can occur on clock:

IO

Any

Event can occur whenever HALT = 0 (type A).

MATCH

Event can occur when HALT = 0 and STOP = 0 and the counter is

enabled (type C).

OR

Any

From the IO component: Event can occur whenever HALT = 0 (A).

From the match component: Event can occur when HALT = 0 and

STOP = 0 and the counter is enabled (C).

AND

LOW or HIGH Event can occur when HALT = 0 and STOP = 0 and the counter is

enabled (C).

RISE or FALL Event can occur whenever HALT = 0 (A).

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Chapter 10: LPC800 State Configurable Timer (SCT)

10.7.8 SCT operation

In its simplest, single-state configuration, the SCT operates as an event controlled one- or

bidirectional counter. Events can be configured to be counter match events, an input or

output level, transitions on an input or output pin, or a combination of match and

input/output behavior. In response to an event, the SCT output or outputs can transition,

or the SCT can perform other actions such as creating an interrupt or starting, stopping, or

resetting the counter. Multiple simultaneous actions are allowed for each event.

Furthermore, any number of events can trigger one specific action of the SCT.

An action or multiple actions of the SCT uniquely define an event. A state is defined by

which events are enabled to trigger an SCT action or actions in any stage of the counter.

Events not selected for this state are ignored.

In a multi-state configuration, states change in response to events. A state change is an

additional action that the SCT can perform when the event occurs. When an event is

configured to change the state, the new state defines a new set of events resulting in

different actions of the SCT. Through multiple cycles of the counter, events can change

the state multiple times and thus create a large variety of event controlled transitions on

the SCT outputs and/or interrupts.

Once configured, the SCT can run continuously without software intervention and can

generate multiple output patterns entirely under the control of events.

• To configure the SCT, see Section 10.7.9.

• To start, run, and stop the SCT, see Section 10.7.10.

• To configure the SCT as simple event controlled counter/timer, see Section 10.7.11.

10.7.9 Configure the SCT

To set up the SCT for multiple events and states, perform the following configuration

steps:

10.7.9.1 Configure the counter

1. Configure the L and H counters in the CONFIG register by selecting two independent

16-bit counters (L counter and H counter) or one combined 32-bit counter in the

UNIFY field.

2. Select the SCT clock source in the CONFIG register (fields CLKMODE and CLKSEL)

from any of the inputs or an internal clock.

10.7.9.2 Configure the match and capture registers

1. Select how many match and capture registers the application uses (total of up to 5):

– In the REGMODE register, select for each of the 5 match/capture register pairs

whether the register is used as a match register or capture register.

2. Define match conditions for each match register selected:

– Each match register MATCH sets one match value, if a 32-bit counter is used, or

two match values, if the L and H 16-bit counters are used.

– Each match reload register MATCHRELOAD sets a reload value that is loaded into

the match register when the counter reaches a limit condition or the value 0.

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10.7.9.3 Configure events and event responses

1. Define when each event can occur in the following way in the EVn_CTRL registers

(up to 6, one register per event):

– Select whether the event occurs on an input or output changing, on an input or

output level, a match condition of the counter, or a combination of match and

input/output conditions in field COMBMODE.

– For a match condition:

Select the match register that contains the match condition for the event to occur.

Enter the number of the selected match register in field MATCHSEL.

If using L and H counters, define whether the event occurs on matching the L or

the H counter in field HEVENT.

– For an SCT input or output level or transition:

Select the input number or the output number that is associated with this event in

fields IOSEL and OUTSEL.

Define how the selected input or output triggers the event (edge or level sensitive)

in field IOCOND.

2. Define what the effect of each event is on the SCT outputs in the OUTn_SET or

OUTn_CLR registers (up to 4 outputs, one register per output):

– For each SCT output, select which events set or clear this output. More than one

event can change the output, and each event can change multiple outputs.

3. Define how each event affects the counter:

– Set the corresponding event bit in the LIMIT register for the event to set an upper

limit for the counter.

When a limit event occurs in unidirectional mode, the counter is cleared to zero

and begins counting up on the next clock edge.

When a limit event occurs in bidirectional mode, the counter begins to count down

from the current value on the next clock edge.

– Set the corresponding event bit in the HALT register for the event to halt the

counter. If the counter is halted, it stops counting and no new events can occur.

The counter operation can only be restored by clearing the HALT_L and/or the

HALT_H bits in the CTRL register.

– Set the corresponding event bit in the STOP register for the event to stop the

counter. If the counter is stopped, it stops counting. However, an event that is

configured as a transition on an input/output can restart the counter.

– Set the corresponding event bit in the START register for the event to restart the

counting. Only events that are defined by an input changing can be used to restart

the counter.

4. Define which events contribute to the SCT interrupt:

– Set the corresponding event bit in the EVEN and the EVFLAG registers to enable

the event to contribute to the SCT interrupt.

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Chapter 10: LPC800 State Configurable Timer (SCT)

10.7.9.4 Configure multiple states

1. In the EVn_STATE register for each event (up to 6 events, one register per event),

select the state or states (up to 2) in which this event is allowed to occur. Each state

can be selected for more than one event.

2. Determine how the event affects the system state:

In the EVn_CTRL registers (up to 6 events, one register per event), set the new state

value in the STATEV field for this event. If the event is the highest numbered in the

current state, this value is either added to the existing state value or replaces the

existing state value, depending on the field STATELD.

Remark: If there are higher numbered events in the current state, this event cannot

change the state.

If the STATEV and STATELD values are set to zero, the state does not change.

10.7.9.5 Miscellaneous options

• There are a certain (selectable) number of capture registers. Each capture register

can be programmed to capture the counter contents when one or more events occur.

• If the counter is in bidirectional mode, the effect of set and clear of an output can be

made to depend on whether the counter is counting up or down by writing to the

OUTPUTDIRCTRL register.

10.7.10 Run the SCT

1. Configure the SCT (see Section 10.7.9 “Configure the SCT”).

2. Write to the STATE register to define the initial state. By default the initial state is state

0.

3. To start the SCT, write to the CTRL register:

– Clear the counters.

– Clear or set the STOP_L and/or STOP_H bits.

Remark: The counter starts counting once the STOP bit is cleared as well. If the

STOP bit is set, the SCT waits instead for an event to occur that is configured to

start the counter.

– For each counter, select unidirectional or bidirectional counting mode (field

BIDIR_L and/or BIDIR_H).

– Select the prescale factor for the counter clock (CTRL register).

– Clear the HALT_L and/or HALT_H bit. By default, the counters are halted and no

events can occur.

4. To stop the counters by software at any time, stop or halt the counter (write to

STOP_L and/or STOP_H bits or HALT_L and/or HALT_H bits in the CTRL register).

– When the counters are stopped, both an event configured to clear the STOP bit or

software writing a zero to the STOP bit can start the counter again.

– When the counter are halted, only a software write to clear the HALT bit can start

the counter again. No events can occur.

– When the counters are halted, software can set any SCT output HIGH or LOW

directly by writing to the OUT register.

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Chapter 10: LPC800 State Configurable Timer (SCT)

The current state can be read at any time by reading the STATE register.

To change the current state by software (that is independently of any event occurring), set

the HALT bit and write to the STATE register to change the state value. Writing to the

STATE register is only allowed when the counter is halted (the HALT_L and/or HALT_H

bits are set) and no events can occur.

10.7.11 Configure the SCT without using states

The SCT can be used as standard counter/timer with external capture inputs and match

outputs without using the state logic. To operate the SCT without states, configure the

SCT as follows:

• Write zero to the STATE register (zero is the default).

• Write zero to the STATELD and STATEV fields in the EVCTRL registers for each

event.

• Write 0x1 to the EVn_STATE register of each event. Writing 0x1 enables the event.

In effect, the event is allowed to occur in a single state which never changes while the

counter is running.

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Chapter 11: LPC800 Multi-Rate Timer (MRT)

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11.1 How to read this chapter

The MRT is available on all LPC800 parts.

11.2 Features

• 24-bit interrupt timer

• Four channels independently counting down from individually set values

• Repeat and one-shot interrupt modes

11.3 Basic configuration

Configure the MRT using the following registers:

• In the SYSAHBCLKCTRL register, set bit 10 (Table 18) to enable the clock to the

register interface.

• Clear the MRT reset using the PRESETCTRL register (Table 7).

• The global MRT interrupt is connected to interrupt #10 in the NVIC.

11.4 Pin description

The MRT has no configurable pins.

11.5 General description

The Multi-Rate Timer (MRT) provides a repetitive interrupt timer with four channels. Each

channel can be programmed with an independent time interval.

Each channel operates independently from the other channels in one of the following

modes:

• Repeat interrupt mode. See Section 11.5.1.

• One-shot interrupt mode. See Section 11.5.2.

The modes for each timer are set in the timer’s control register. See Table 137.

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Chapter 11: LPC800 Multi-Rate Timer (MRT)

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Fig 15. MRT block diagram

11.5.1 Repeat interrupt mode

The repeat interrupt mode generates repeated interrupts after a selected time interval.

This mode can be used for software-based PWM or PPM applications.

When the timer n is in idle state, writing a non-zero value IVALUE to the INTVALn register

immediately loads the time interval value IVALUE - 1, and the timer begins to count down

from this value. When the timer reaches zero, an interrupt is generated, the value in the

INTVALn register IVALUE - 1 is reloaded automatically, and the timer starts to count down

again.

While the timer is running in repeat interrupt mode, you can perform the following actions:

• Change the interval value on the next timer cycle by writing a new value (>0) to the

INTVALn register and setting the LOAD bit to 0. An interrupt is generated when the

timer reaches zero. On the next cycle, the timer counts down from the new value.

• Change the interval value on-the-fly immediately by writing a new value (>0) to the

INTVALn register and setting the LOAD bit to 1. The timer immediately starts to count

down from the new timer interval value. An interrupt is generated when the timer

reaches 0.

• Stop the timer at the end of time interval by writing a 0 to the INTVALn register and

setting the LOAD bit to 0. An interrupt is generated when the timer reaches zero.

• Stop the timer immediately by writing a 0 to the INTVALn register and setting the

LOAD bit to 1. No interrupt is generated when the INTVALn register is written.

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Chapter 11: LPC800 Multi-Rate Timer (MRT)

11.5.2 One-shot interrupt mode

The one-shot interrupt generates one interrupt after a one-time count. With this mode, you

can generate a single interrupt at any point. This mode can be used to introduce a specific

delay in a software task.

When the timer is in the idle state, writing a non-zero value IVALUE to the INTVALn

register immediately loads the time interval value IVALUE - 1, and the timer starts to count

down. When the timer reaches 0, an interrupt is generated and the timer stops and enters

the idle state.

While the timer is running in the one-shot interrupt mode, you can perform the following

actions:

• Update the INTVALn register with a new time interval value (>0) and set the LOAD bit

to 1. The timer immediately reloads the new time interval, and starts counting down

from the new value. No interrupt is generated when the TIME_INTVALn register is

updated.

• Write a 0 to the INTVALn register and set the LOAD bit to 1. The timer immediately

stops counting and moves to the idle state. No interrupt is generated when the

INTVALn register is updated.

11.6 Register description

The reset values shown in Table 134 are POR reset values.

Table 134. Register overview: MRT (base address 0x4000 4000)

Name

Access Address Description

offset

Reset value Reference

0 Table 135

INTVAL0

TIMER0

CTRL0

R/W

0x0

0x4

0x8

MRT0 Time interval value register. This value is

loaded into the TIMER0 register.

R

MRT0 Timer register. This register reads the value 0x00FF FFFF Table 136

of the down-counter.

R/W

MRT0 Control register. This register controls the

MRT0 modes.

0

Table 137

STAT0

R/W

0xC

MRT0 Status register.

0

Table 138

Table 135

INTVAL1

0x10

MRT1 Time interval value register. This value is

loaded into the TIMER1 register.

TIMER1

CTRL1

R/W

0x14

0x18

MRT1 Timer register. This register reads the value 0x00FF FFFF Table 136

of the down-counter.

MRT1 Control register. This register controls the

MRT1 modes.

0

Table 137

STAT1

R/W

0x1C

0x20

MRT1 Status register.

0

Table 138

Table 135

INTVAL2

MRT2 Time interval value register. This value is

loaded into the TIMER2 register.

TIMER2

CTRL2

STAT2

R/W

0x24

0x28

0x2C

MRT2 Timer register. This register reads the value 0x00FF FFFF Table 136

of the down-counter.

MRT2 Control register. This register controls the

MRT2 modes.

0

Table 137

MRT2 Status register.

0

Table 138

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Chapter 11: LPC800 Multi-Rate Timer (MRT)

Table 134. Register overview: MRT (base address 0x4000 4000)

Name

Access Address Description

offset

Reset value Reference

INTVAL3

TIMER3

CTRL3

R/W

0x30

0x34

0x38

MRT3 Time interval value register. This value is

loaded into the TIMER3 register.

0

Table 135

MRT3 Timer register. This register reads the value 0x00FF FFFF Table 136

of the down-counter.

MRT3 Control register. This register controls the

MRT modes.

0

Table 137

STAT3

R/W

R

0x3C

0xF4

MRT3 Status register.

0

Table 138

Table 139

IDLE_CH

Idle channel register. This register returns the

number of the first idle channel.

IRQ_FLAG

R/W

0xF8

Global interrupt flag register

0

Table 140

11.6.1 Time interval register

This register contains the MRT load value and controls how the timer is reloaded. The

load value is IVALUE -1.

Table 135. Time interval register (INTVAL[0:3], address 0x4000 4000 (INTVAL0) to 0x4000

4030 (INTVAL3)) bit description

Bit

Symbol Value Description

Reset

value

23:0

IVALUE

Time interval load value. This value is loaded into the

0

TIMERn register and the MRTn starts counting down from

IVALUE -1.

If the timer is idle, writing a non-zero value to this bit field

starts the timer immediately.

If the timer is running, writing a zero to this bit field does the

following:

• If LOAD = 1, the timer stops immediately.

• If LOAD = 0, the timer stops at the end of the time

interval.

30:24

31

-

Reserved.

0

LOAD

Determines how the timer interval value IVALUE -1 is

loaded into the TIMERn register. This bit is write-only.

Reading this bit always returns 0.

0

1

No force load. The load from the INTVALn register to the

TIMERn register is processed at the end of the time interval

if the repeat mode is selected.

Force load. The INTVALn interval value IVALUE -1 is

immediately loaded into the TIMERn register while TIMERn

is running.

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Chapter 11: LPC800 Multi-Rate Timer (MRT)

11.6.2 Timer register

The timer register holds the current timer value. This register is read-only.

Table 136. Timer register (TIMER[0:3], address 0x4000 4004 (TIMER0) to 0x4000 4034

(TIMER3)) bit description

Bit

Symbol Description

Reset

value

23:0

VALUE Holds the current timer value of the down-counter. The initial value 0x00FF

of the TIMERn register is loaded as IVALUE - 1 from the INTVALn

register either at the end of the time interval or immediately in the

following cases:

FFFF

INTVALn register is updated in the idle state.

INTVALn register is updated with LOAD = 1.

When the timer is in idle state, reading this bit fields returns -1

(0x00FF FFFF).

31:24

-

Reserved.

0

11.6.3 Control register

The control register configures the the mode for each MRT and enables the interrupt.

Table 137. Control register (CTRL[0:3], address 0x4000 4008 (CTRL0) to 0x4000 4038

(CTRL3)) bit description

Bit

Symbol

Value

Description

Reset

value

0

INTEN

Enable the TIMERn interrupt.

Disable.

0

1

Enable.

2:1

MODE

Selects timer mode.

Repeat interrupt mode.

One-shot interrupt mode.

Reserved.

0x0

0x1

0x2

0x3

Reserved.

31:3

-

Reserved.

0

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Chapter 11: LPC800 Multi-Rate Timer (MRT)

11.6.4 Status register

This register indicates the status of each MRT.

Table 138. Status register (STAT[0:3], address 0x4000 400C (STAT0) to 0x4000 403C (STAT3))

bit description

Bit

Symbol

Value

Description

Reset

value

0

INTFLAG

Monitors the interrupt flag.

0

1

No pending interrupt. Writing a zero is equivalent to no

operation.

Pending interrupt. The interrupt is pending because

TIMERn has reached the end of the time interval. If the

INTEN bit in the CONTROLn is also set to 1, the

interrupt for timer channel n and the global interrupt are

raised.

Writing a 1 to this bit clears the interrupt request.

Indicates the state of TIMERn. This bit is read-only.

Idle state. TIMERn is stopped.

1

RUN

-

0

1

Running. TIMERn is running.

31:2

Reserved.

11.6.5 Idle channel register

The idle channel register returns the lowest idle channel number. The channel is

considered idle when both flags is the STATUS register (RUN and INTFLAG) are zero.

In an application with multiple timers running independently, you can calculate the register

offset of the next idle timer by reading the idle channel number in this register. The idle

channel register allows you set up the next idle timer without checking the idle state of

each timer.

Table 139. Idle channel register (IDLE_CH, address 0x4000 40F4) bit description

Bit

Symbol

Description

Reset

value

3:0

7:4

-

Reserved.

0

CHAN

Idle channel. Reading the CHAN bits, returns the lowest idle timer

channel. If all timer channels are running, CHAN = 0xF.

31:8

-

Reserved.

0

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11.6.6 Global interrupt flag register

The global interrupt register combines the interrupt flags from the individual timer

channels in one register. Setting and clearing each flag behaves in the same way as

setting and clearing the INTFLAG bit in each of the STATUSn registers.

Table 140. Global interrupt flag register (IRQ_FLAG, address 0x4000 40F8) bit description

Bit

Symbol Value Description

Reset

value

0

GFLAG0

GFLAG1

GFLAG2

GFLAG3

-

Monitors the interrupt flag of TIMER0.

0

1

No pending interrupt. Writing a zero is equivalent to no

operation.

Pending interrupt. The interrupt is pending because TIMER0

has reached the end of the time interval. If the INTEN bit in the

CONTROL0 register is also set to 1, the interrupt for timer

channel 0 and the global interrupt are raised.

Writing a 1 to this bit clears the interrupt request.

Monitors the interrupt flag of TIMER1.

1

0

1

No pending interrupt. Writing a zero is equivalent to no

operation.

Pending interrupt. The interrupt is pending because TIMER1

has reached the end of the time interval. If the INTEN bit in the

CONTROL1 register is also set to 1, the interrupt for timer

channel 1 and the global interrupt are raised.

Writing a 1 to this bit clears the interrupt request.

Monitors the interrupt flag of TIMER2.

2

0

1

No pending interrupt. Writing a zero is equivalent to no

operation.

Pending interrupt. The interrupt is pending because TIMER2

has reached the end of the time interval. If the INTEN bit in the

CONTROL2 register is also set to 1, the interrupt for timer

channel 2 and the global interrupt are raised.

Writing a 1 to this bit clears the interrupt request.

Monitors the interrupt flag of TIMER3.

3

0

1

No pending interrupt. Writing a zero is equivalent to no

operation.

Pending interrupt. The interrupt is pending because TIMER3

has reached the end of the time interval. If the INTEN bit in the

CONTROL3 register is also set to 1, the interrupt for timer

channel 3 and the global interrupt are raised.

Writing a 1 to this bit clears the interrupt request.

Reserved.

31:4

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Chapter 12: LPC800 Windowed Watchdog Timer (WWDT)

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12.1 How to read this chapter

The watchdog timer is identical on all LPC800 parts.

12.2 Features

• Internally resets chip if not reloaded during the programmable time-out period.

• Optional windowed operation requires reload to occur between a minimum and

maximum time-out period, both programmable.

• Optional warning interrupt can be generated at a programmable time prior to

watchdog time-out.

• Programmable 24-bit timer with internal fixed pre-scaler.

• Selectable time period from 1,024 watchdog clocks (T_WDCLK 256  4) to over 67

million watchdog clocks (T_WDCLK 2²⁴ 4) in increments of 4 watchdog clocks.

• “Safe” watchdog operation. Once enabled, requires a hardware reset or a Watchdog

reset to be disabled.

• Incorrect feed sequence causes immediate watchdog event if enabled.

• The watchdog reload value can optionally be protected such that it can only be

changed after the “warning interrupt” time is reached.

• Flag to indicate Watchdog reset.

• The Watchdog clock (WDCLK) source is the WatchDog oscillator.

• The Watchdog timer can be configured to run in Deep-sleep or Power-down mode.

• Debug mode.

12.3 Basic configuration

The WWDT is configured through the following registers:

• Power to the register interface (WWDT PCLK clock): In the SYSAHBCLKCTRL

register, set bit 17 in Table 18.

• Enable the WWDT clock source (the watchdog oscillator) in the PDRUNCFG register

(Table 37). This is the clock source for the timer base.

• For waking up from a WWDT interrupt, enable the watchdog interrupt for wake-up in

the STARTERP1 register (Table 34).

12.4 Pin description

The WWDT has no external pins.

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Chapter 12: LPC800 Windowed Watchdog Timer (WWDT)

12.5 General description

The purpose of the Watchdog Timer is to reset or interrupt the microcontroller within a

programmable time if it enters an erroneous state. When enabled, a watchdog reset is

generated if the user program fails to feed (reload) the Watchdog within a predetermined

amount of time.

When a watchdog window is programmed, an early watchdog feed is also treated as a

watchdog event. This allows preventing situations where a system failure may still feed

the watchdog. For example, application code could be stuck in an interrupt service that

contains a watchdog feed. Setting the window such that this would result in an early feed

will generate a watchdog event, allowing for system recovery.

The Watchdog consists of a fixed (divide by 4) pre-scaler and a 24-bit counter which

decrements when clocked. The minimum value from which the counter decrements is

0xFF. Setting a value lower than 0xFF causes 0xFF to be loaded in the counter. Hence the

minimum Watchdog interval is (T_WDCLK 256  4) and the maximum Watchdog interval is

(T_WDCLK 2²⁴ 4) in multiples of (T_WDCLK 4). The Watchdog should be used in the

following manner:

• Set the Watchdog timer constant reload value in the TC register.

• Set the Watchdog timer operating mode in the MOD register.

• Set a value for the watchdog window time in the WINDOW register if windowed

operation is desired.

• Set a value for the watchdog warning interrupt in the WARNINT register if a warning

interrupt is desired.

• Enable the Watchdog by writing 0xAA followed by 0x55 to the FEED register.

• The Watchdog must be fed again before the Watchdog counter reaches zero in order

to prevent a watchdog event. If a window value is programmed, the feed must also

occur after the watchdog counter passes that value.

When the Watchdog Timer is configured so that a watchdog event will cause a reset and

the counter reaches zero, the CPU will be reset, loading the stack pointer and program

counter from the vector table as for an external reset. The Watchdog time-out flag

(WDTOF) can be examined to determine if the Watchdog has caused the reset condition.

The WDTOF flag must be cleared by software.

When the Watchdog Timer is configured to generate a warning interrupt, the interrupt will

occur when the counter matches the value defined by the WARNINT register.

12.5.1 Block diagram

The block diagram of the Watchdog is shown below in the Figure 16. The synchronization

logic (PCLK - WDCLK) is not shown in the block diagram.

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Chapter 12: LPC800 Windowed Watchdog Timer (WWDT)

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Fig 16. Windowed Watchdog timer block diagram

12.5.2 Clocking and power control

The watchdog timer block uses two clocks: PCLK and WDCLK. PCLK is used for the APB

accesses to the watchdog registers and is derived from the system clock (see Figure 3).

The WDCLK is used for the watchdog timer counting and is derived from the watchdog

oscillator.

The synchronization logic between the two clock domains works as follows: When the

MOD and TC registers are updated by APB operations, the new value will take effect in 3

WDCLK cycles on the logic in the WDCLK clock domain.

When the watchdog timer is counting on WDCLK, the synchronization logic will first lock

the value of the counter on WDCLK and then synchronize it with PCLK, so that the CPU

can read the WDTV register.

Remark: Because of the synchronization step, software must add a delay of three

WDCLK clock cycles between the feed sequence and the time the WDPROTECT bit is

enabled in the MOD register. The length of the delay depends on the selected watchdog

clock WDCLK.

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Chapter 12: LPC800 Windowed Watchdog Timer (WWDT)

12.5.3 Using the WWDT lock features

The WWDT supports several lock features which can be enabled to ensure that the

WWDT is running at all times:

• Disabling the WWDT clock source

• Changing the WWDT reload value

12.5.3.1 Disabling the WWDT clock source

If bit 5 in the WWDT MOD register is set, the WWDT clock source is locked and can not

be disbled either by software or by hardware when Sleep, Deep-sleep or Power-down

modes are entered. Therefore, the user must ensure that the watchdog oscillator for each

power mode is enabled before setting bit 5 in the MOD register.

In Deep power-down mode, no clock locking mechanism is in effect because no clocks

are running. However, an additional lock bit in the PMU can be set to prevent the part from

even entering Deep power-down mode (see Table 42).

12.5.3.2 Changing the WWDT reload value

If bit 4 is set in the WWDT MOD register, the watchdog time-out value (TC) can be

changed only after the counter is below the value of WDWARNINT and WDWINDOW.

The reload overwrite lock mechanism can only be disabled by a reset of any type.

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12.6 Register description

The Watchdog Timer contains the registers shown in Table 141.

The reset value reflects the data stored in used bits only. It does not include the content of

reserved bits.

Table 141. Register overview: Watchdog timer (base address 0x4000 4000)

Name

Access Address Description

offset

Reset

value

Reference

MOD

R/W

WO

0x000

0x004

0x008

Watchdog mode register. This

register contains the basic mode and

status of the Watchdog Timer.

0

Table 142

TC

Watchdog timer constant register.

This 24-bit register determines the

time-out value.

0xFF

NA

Table 144

Table 145

FEED

Watchdog feed sequence register.

Writing 0xAA followed by 0x55 to this

register reloads the Watchdog timer

with the value contained in WDTC.

TV

-

RO

-

0x00C

Watchdog timer value register. This

24-bit register reads out the current

value of the Watchdog timer.

0xFF

Table 146

0x010

0x014

Reserved

-

WARNINT R/W

Watchdog Warning Interrupt compare

value.

0

Table 147

WINDOW R/W

0x018

Watchdog Window compare value.

0xFF FFFF Table 148

12.6.1 Watchdog mode register

The WDMOD register controls the operation of the Watchdog. Note that a watchdog feed

must be performed before any changes to the WDMOD register take effect.

Table 142. Watchdog mode register (MOD - 0x4000 4000) bit description

Bit Symbol

Value Description

Reset

value

0

WDEN

Watchdog enable bit. Once this bit has been written with

0

a 1, it cannot be re-written with a 0. Once this bit is set

to one, the watchdog timer starts running after a

watchdog feed.

0

1

The watchdog timer is stopped.

The watchdog timer is running.

1

2

WDRESET

WDTOF

Watchdog reset enable bit. Once this bit has been

written with a 1 it cannot be re-written with a 0.

0

1

A watchdog time-out will not cause a chip reset.

A watchdog time-out will cause a chip reset.

Watchdog time-out flag. Set when the watchdog timer

0 (only

times out, by a feed error, or by events associated with after

WDPROTECT. Cleared by software. Causes a chip

reset if WDRESET = 1.

external

reset)

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Table 142. Watchdog mode register (MOD - 0x4000 4000) bit description

Bit Symbol Value Description

Reset

value

3

4

WDINT

Warning interrupt flag. Set when the timer reaches the

value in WDWARNINT. Cleared by software.

0

WDPROTECT

Watchdog update mode. This bit can be set once by

software and is only cleared by a reset.

0

1

The watchdog time-out value (TC) can be changed at

any time.

The watchdog time-out value (TC) can be changed only

after the counter is below the value of WDWARNINT

and WDWINDOW.

5

LOCK

A 1 in this bit prevents disabling or powering down the

watchdog oscillator. This bit can be set once by

software and is only cleared by any reset.

0

31:6 -

Reserved, user software should not write ones to

reserved bits. The value read from a reserved bit is not

defined.

NA

Once the WDEN, WDPROTECT, or WDRESET bits are set they can not be cleared by

software. Both flags are cleared by an external reset or a Watchdog timer reset.

WDTOF The Watchdog time-out flag is set when the Watchdog times out, when a feed

error occurs, or when PROTECT =1 and an attempt is made to write to the TC register.

This flag is cleared by software writing a 0 to this bit.

WDINT The Watchdog interrupt flag is set when the Watchdog counter reaches the value

specified by WARNINT. This flag is cleared when any reset occurs, and is cleared by

software by writing a 0 to this bit.

In all power modes except Deep power-down mode, a Watchdog reset or interrupt can

occur when the watchdog is running and has an operating clock source. The watchdog

oscillator can be configured to keep running in Sleep, Deep-sleep modes, and

Power-down modes.

If a watchdog interrupt occurs in Sleep, Deep-sleep mode, or Power-down mode, and the

WWDT interrupt is enabled in the NVIC, the device will wake up. Note that in Deep-sleep

and Power-down modes, the WWDT interrupt must be enabled in the STARTERP1

register in addition to the NVIC.

See the following registers:

Table 34 “Start logic 1 interrupt wake-up enable register (STARTERP1, address 0x4004

8214) bit description”

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Chapter 12: LPC800 Windowed Watchdog Timer (WWDT)

Table 143. Watchdog operating modes selection

WDEN WDRESET Mode of Operation

0

1

X (0 or 1)

0

Debug/Operate without the Watchdog running.

Watchdog interrupt mode: the watchdog warning interrupt will be generated

but watchdog reset will not.

When this mode is selected, the watchdog counter reaching the value

specified by WDWARNINT will set the WDINT flag and the Watchdog

interrupt request will be generated.

1

Watchdog reset mode: both the watchdog interrupt and watchdog reset are

enabled.

When this mode is selected, the watchdog counter reaching the value

specified by WDWARNINT will set the WDINT flag and the Watchdog

interrupt request will be generated, and the watchdog counter reaching zero

will reset the microcontroller. A watchdog feed prior to reaching the value of

WDWINDOW will also cause a watchdog reset.

12.6.2 Watchdog Timer Constant register

The TC register determines the time-out value. Every time a feed sequence occurs the

value in the TC is loaded into the Watchdog timer. The TC resets to 0x00 00FF. Writing a

value below 0xFF will cause 0x00 00FF to be loaded into the TC. Thus the minimum

time-out interval is T_WDCLK 256  4.

If the WDPROTECT bit in WDMOD = 1, an attempt to change the value of TC before the

watchdog counter is below the values of WDWARNINT and WDWINDOW will cause a

watchdog reset and set the WDTOF flag.

Table 144. Watchdog Timer Constant register (TC - 0x4000 4004) bit description

Bit

Symbol Description

Reset

Value

23:0 COUNT Watchdog time-out value.

31:24 -

0x00 00FF

Reserved, user software should not write ones to reserved bits. The NA

value read from a reserved bit is not defined.

12.6.3 Watchdog Feed register

Writing 0xAA followed by 0x55 to this register will reload the Watchdog timer with the

WDTC value. This operation will also start the Watchdog if it is enabled via the WDMOD

register. Setting the WDEN bit in the WDMOD register is not sufficient to enable the

Watchdog. A valid feed sequence must be completed after setting WDEN before the

Watchdog is capable of generating a reset. Until then, the Watchdog will ignore feed

errors.

After writing 0xAA to WDFEED, access to any Watchdog register other than writing 0x55

to WDFEED causes an immediate reset/interrupt when the Watchdog is enabled, and

sets the WDTOF flag. The reset will be generated during the second PCLK following an

incorrect access to a Watchdog register during a feed sequence.

It is good practice to disable interrupts around a feed sequence, if the application is such

that an interrupt might result in rescheduling processor control away from the current task

in the middle of the feed, and then lead to some other access to the WDT before control is

returned to the interrupted task.

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Table 145. Watchdog Feed register (FEED - 0x4000 4008) bit description

Bit

Symbol

Description

Reset

Value

7:0

FEED

-

Feed value should be 0xAA followed by 0x55.

NA

31:8

Reserved, user software should not write ones to reserved

bits. The value read from a reserved bit is not defined.

12.6.4 Watchdog Timer Value register

The WDTV register is used to read the current value of Watchdog timer counter.

When reading the value of the 24-bit counter, the lock and synchronization procedure

takes up to 6 WDCLK cycles plus 6 PCLK cycles, so the value of WDTV is older than the

actual value of the timer when it's being read by the CPU.

Table 146. Watchdog Timer Value register (TV - 0x4000 400C) bit description

Bit

Symbol Description

Reset

Value

23:0 COUNT Counter timer value.

31:24 -

0x00 00FF

Reserved, user software should not write ones to reserved bits. The NA

value read from a reserved bit is not defined.

12.6.5 Watchdog Timer Warning Interrupt register

The WDWARNINT register determines the watchdog timer counter value that will

generate a watchdog interrupt. When the watchdog timer counter matches the value

defined by WARNINT, an interrupt will be generated after the subsequent WDCLK.

A match of the watchdog timer counter to WARNINT occurs when the bottom 10 bits of

the counter have the same value as the 10 bits of WARNINT, and the remaining upper bits

of the counter are all 0. This gives a maximum time of 1,023 watchdog timer counts (4,096

watchdog clocks) for the interrupt to occur prior to a watchdog event. If WARNINT is 0, the

interrupt will occur at the same time as the watchdog event.

Table 147. Watchdog Timer Warning Interrupt register (WARNINT - 0x4000 4014) bit

description

Bit

Symbol

Description

Reset

Value

9:0

WARNINT Watchdog warning interrupt compare value.

0

31:10 -

Reserved, user software should not write ones to reserved bits. The

value read from a reserved bit is not defined.

NA

12.6.6 Watchdog Timer Window register

The WINDOW register determines the highest WDTV value allowed when a watchdog

feed is performed. If a feed sequence occurs when WDTV is greater than the value in

WINDOW, a watchdog event will occur.

WINDOW resets to the maximum possible WDTV value, so windowing is not in effect.

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Table 148. Watchdog Timer Window register (WINDOW - 0x4000 4018) bit description

Bit

Symbol

Description

Reset

Value

23:0 WINDOW Watchdog window value.

0xFF FFFF

NA

31:24 -

Reserved, user software should not write ones to reserved bits.

The value read from a reserved bit is not defined.

12.7 Functional description

The following figures illustrate several aspects of Watchdog Timer operation.

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Fig 19. Watchdog warning interrupt

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Chapter 13: LPC800 Analog comparator

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13.1 How to read this chapter

The analog comparator is available on all LPC800 parts.

13.2 Features

• Selectable external inputs can be used as either the positive or negative input of the

comparator.

• The Internal voltage reference (0.9 V bandgap reference) can be used as either the

positive or negative input of the comparator.

• 32-stage voltage ladder can be used as either the positive or negative input of the

comparator.

• Voltage ladder source selectable between the supply pin V_DDor VDDCMP pin.

• Voltage ladder can be separately powered down when not required.

• Interrupt capability

13.3 Basic configuration

Configure the analog comparator using the following registers:

• In the SYSAHBCLKCTRL register, set bit 19 (Table 18) to enable the clock to the

register interface.

• You can enable or disable the power to the analog comparator through the

PDRUNCFG register (Table 37).

• Clear the analog comparator peripheral reset using the PRESETCTRL register

(Table 7).

• The analog comparator interrupt is connected to interrupt #11 in the NVIC.

• Configure the analog comparator pin functions through the switch matrix. See

Section 13.4.

13.3.1 Connect the comparator output to the SCT

You can use the comparator output function (ACMP_O) to start or stop the SCT or, more

generally, create an SCT event. To create an SCT event, connect AMP_O as follows:

1. Using the switch matrix, connect ACMP_O to a pin. See Table 149.

2. Using the switch matrix, connect any of the SCT input functions to the same pin. See

Table 106.

The selected SCT input can now monitor the ACMP_O function.

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Chapter 13: LPC800 Analog comparator

13.4 Pin description

The analog comparator reference voltage, the inputs, and the output are assigned to

external pins through the switch matrix. You can assign the analog comparator output to

any pin on the package that is not a supply or ground pin. The comparator inputs and the

reference voltage are fixed-pin functions that must be enabled through the switch matrix

and can only be assigned to special pins on the package.

See Section 9.3.1 “Connect an internal signal to a package pin” to assign the analog

comparator output to any pin on the LPC800 package.

See Section 9.3.2 to enable the analog comparator inputs and the reference voltage input.

Table 149. Analog comparator pin description

Function Type Pin

Description

SWM register

Reference

ACMP_I1

ACMP_I2

I

PIO0_0/ACMP_I1

Comparator input 1

PINENABLE0

Section 9.5.10

PIO0_0/ACMP_I2/CLKIN Comparator input 2. Disable the CLKIN PINENABLE0

function in the PINSASSIGN1BIT0

register.

ACMP_O

VDDCMP

O

I

any

Comparator output

PINASSIGN8

PINENABLE0

Section 9.5.9

Section 9.5.10

PIO0_6/VDDCMP

External reference voltage source for

32-stage Voltage Ladder.

13.5 General description

The analog comparator can compare voltage levels on external pins and internal voltages.

The comparator has 8 inputs multiplexed separately to its positive and negative inputs.

The multiplexers are controlled by the comparator register CTL (see Figure 20 and

Table 151).

Input 0 of the multiplexers is the programmable voltage ladder output.

Bits 2:1 control the external inputs ACMP_I[2:1].

Bits 6 of the multiplexers controls internal reference voltage input.

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Fig 20. Comparator block diagram

13.5.1 Reference voltages

The voltage ladder can use two reference voltages, from the VDDCMP or the V_DDpin.

The voltage ladder selects one of 32 steps between the pin voltage and V_SSinclusive. The

voltage on VDDCMP should not exceed that on V_DD

.

13.5.2 Settling times

After the voltage ladder is powered on, it requires stabilization time until comparisons

using it are accurate. Much shorter settling times apply after the LADSEL value is

changed and when either or both voltage sources are changed. Software can deal with

these factors by repeatedly reading the comparator output until a number of readings yield

the same result.

13.5.3 Interrupts

The interrupt output comes from edge detection circuitry in this module. Rising edges,

falling edges, or both edges can set the COMPEDGE bit and thus request an interrupt.

COMPEDGE and the interrupt request are cleared when software writes a 1 to

EDGECLR.

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13.5.4 Comparator outputs

The comparator output (conditioned by COMPSA bit) can be routed to an external pin.

When COMPSA is 0 and the comparator interrupt is disabled, the comparator can be

used with the bus clock disabled (Table 18 “System clock control register

(SYSAHBCLKCTRL, address 0x4004 8080) bit description”) to save power if the control

registers don’t need to be written.

The status of the comparator output can be observed through the comparator status

register bit.

The comparator output can be routed to the SCT via the switch matrix allowing to capture

the time of a voltage crossing or to count crossings in either or both directions. See

Section 13.3.1 “Connect the comparator output to the SCT”.

13.6 Register description

Table 150. Register overview: Analog comparator (base address 0x4002 4000)

Name

Access Address Description

offset

Reset value

CTRL

LAD

R/W

0x000

0x004

Comparator control register

Voltage ladder register

0

13.6.1 Comparator control register

This register enables the comparator, configures the interrupts, and controls the input

multiplexers on both sides of the comparator. All bits not shown in Table 151 are reserved

and should be written as 0.

Table 151. Comparator control register (CTRL, address 0x4002 4000) bit description

Bit

Symbol

Value Description

Reset

value

2:0

4:3

-

Reserved. Write as 0.

0

EDGESEL

This field controls which edges on the comparator

output set the COMPEDGE bit (bit 23 below):

0x0

0x1

0x2

0x3

Falling edges

Rising edges

Both edges

5

6

-

Reserved. Write as 0.

Comparator output control

Comparator output is used directly.

0

COMPSA

0

1

Comparator output is synchronized to the bus clock for

output to other modules.

7

-

Reserved. Write as 0.

0

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Chapter 13: LPC800 Analog comparator

Table 151. Comparator control register (CTRL, address 0x4002 4000) bit description

Bit Symbol Value Description

Reset

value

10:8 COMP_VP_SEL

13:11 COMP_VM_SEL

19:14 -

Selects positive voltage input

0

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

Voltage ladder output

ACMP_I1

ACMP_I2

Reserved

Internal reference voltage

Reserved

Selects negative voltage input

Voltage ladder output

ACMP_I1

0

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

ACMP_I2

Reserved

Internal reference voltage

Reserved

Reserved. Write as 0.

0

20

EDGECLR

Interrupt clear bit. To clear the COMPEDGE bit and

thus negate the interrupt request, toggle the

EDGECLR bit by first writing a 1 and then a 0.

21

COMPSTAT

Comparator status. This bit reflects the state of the

comparator output.

0

22

23

24

-

Reserved. Write as 0.

0

COMPEDGE

-

Comparator edge-detect status.

Reserved. Write as 0.

26:25 HYS

Controls the hysteresis of the comparator. When the

comparator is outputting a certain state, this is the

difference between the selected signals, in the

opposite direction from the state being output, that will

switch the output.

0x0

0x1

0x2

0x3

None (the output will switch as the voltages cross)

5 mV

10 mV

20 mV

Reserved

31:27 -

-

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Chapter 13: LPC800 Analog comparator

13.6.2 Voltage ladder register

This register enables and controls the voltage ladder. The fraction of the reference voltage

produced by the ladder is programmable in steps of 1/31.

Table 152. Voltage ladder register (LAD, address 0x4002 4004) bit description

Bit

Symbol

Value Description

Reset

value

0

LADEN

Voltage ladder enable

0

5:1

LADSEL

Voltage ladder value. The reference voltage Vref depends

on the LADREF bit below.

00000 = V_SS

00001 = 1 Vref/31

00010 = 2 Vref/31

...

11111 = Vref

6

LADREF

Selects the reference voltage Vref for the voltage ladder:

0

1

Supply pin V_DD

VDDCMP pin

Reserved.

31:7

-

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Chapter 14: LPC800 Self wake-up timer (WKT)

Rev. 1.0 — 7 November 2012

Preliminary user manual

14.1 How to read this chapter

The self wake-up timer is available on all LPC800 parts.

14.2 Features

• 32-bit loadable down-counter. Counter starts automatically when a count value is

loaded. Time-out generates an interrupt/wake up request.

• The WKT resides in a separate, always-on power domain.

• The WKT supports two clock sources. One clock source originates from the

always-on power domain.

• The WKT can be used for waking up the part from any low power mode, including

Deep power-down mode, or for general-purpose timing.

14.3 Basic configuration

• In the SYSAHBCLKCTRL register, set bit 9 (Table 18) to enable the clock to the

register interface.

• Clear the WKT reset using the PRESETCTRL register (Table 7).

• The WKT interrupt is connected to interrupt #15 in the NVIC.

• Enable the low power oscillator in the PMU (Table 45).

• Enable the IRC and IRC output in the PDRUNCFG register (Table 37).

• See Section 5.7.1 to enable the various power down modes.

14.4 Pin description

The WKT has no configurable pins.

14.5 General description

The self wake-up timer is a 32-bit, loadable down-counter. Writing any non-zero value to

this timer automatically enables the counter and launches a count-down sequence. When

the counter is being used as a wake up timer, this write can occur just prior to entering a

reduced power mode.

When a starting count value is loaded, the self wake-up timer automatically turns on,

counts from the pre-loaded value down to zero, generates an interrupt and/or a wake up

request, and then turns itself off until re-launched by a subsequent software write.

14.5.1 WKT clock sources

The self wake-up timer can be clocked from two alternative clock sources:

• A 750 kHz clock derived from the IRC oscillator. This is the default clock,

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Chapter 14: LPC800 Self wake-up timer (WKT)

• A 10 kHz, low-power clock with a dedicated on-chip oscillator as clock source.

The IRC-derived clock is much more accurate than the alternative, low-power clock.

However, the IRC is not available in most low-power modes. This clock must not be

selected when the timer is being used to wake up from a power mode where the IRC is

disabled.

The alternative clock source is a (nominally) 10 kHz, low-power clock, sourced from a

dedicated oscillator. This oscillator resides in the always-on voltage domain, so it can be

programmed to continue operating in Deep power-down mode when power is removed

from the rest of the part. This clock is also be available during other low-power modes

when the IRC clock is shut-down.

The Low-Power oscillator is not accurate (approximately +/- 45% over process and

temperature). The frequency measurement feature (if available<tbd>) can be used to

determine what the actual frequency is before selecting a time-out value to write into the

self wake-up timer. The frequency may still drift, however, while counting is in progress -

particularly due to reduced chip temperature after a low-power mode is entered.

14.6 Register description

Table 153. Register overview: WKT (base address 0x4000 8000)

Name

Access Address Description

offset

Reset Reference

value

CTRL

R/W

0x0

Self wake-up timer control register.

Counter register.

0

Table 154

COUNT

0xC

14.6.1 Control register

The WKT interrupt must be enabled in the NVIC to wake up the part using the self

wake-up counter.

Table 154. Control register (CTRL, address 0x4000 8000) bit description

Bit

Symbol

Value Description

Reset

value

0

CLKSEL

Select the self wake-up timer clock source.

0

1

Divided IRC clock. This clock runs at 750 kHz and provides time-out periods of up

to approximately 95 minutes in 1.33 μs increments.

Remark: This clock is not available in not available in Deep-sleep, power-down,

deep power-down modes. Do not select this option if the timer is to be used to

wake up from one of these modes.

Low power clock. This is the (nominally) 10 kHz clock and provides time-out

periods of up to approximately 119 hours in 100 μs increments. The accuracy of

this clock is limited to +/- 45 % over temperature and processing.

Remark: This clock is available in all power modes. Prior to use, the low-power

oscillator must be enabled. The oscillator must also be set to remain active in

Deep power-down if needed.

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Chapter 14: LPC800 Self wake-up timer (WKT)

Table 154. Control register (CTRL, address 0x4000 8000) bit description

Bit

Symbol

Value Description

Reset

value

1

ALARMFLAG

Wake-up or alarm timer flag.

-

0

1

No time-out. The self wake-up timer has not timed out. Writing a 0 to has no effect.

Time-out. The self wake-up timer has timed out. This flag generates an interrupt

request which can wake up the part from any reduced power mode including Deep

power-down if the clock source is the low power oscillator. Writing a 1 clears this

status bit.

2

CLEARCTR

Clears the self wake-up timer.

0

-

0

1

No effect. Reading this bit always returns 0.

Clear the counter. Counting is halted until a new count value is loaded.

Reserved.

31:3

-

14.6.2 Count register

Do not write to this register while the counting is in progress.

Remark: In general, reading the timer state is not recommended. There is no mechanism

to ensure that some bits of this register don't change while a read is in progress if the read

happens to coincide with an self wake-up timer clock edge. If you must read this value, it

is recommended to read it twice in succession.

Table 155. Counter register (COUNT, address 0x4000 800C) bit description

Bit

Symbol

Description

Reset

value

31:0 VALUE

A write to this register pre-loads start count value into the timer

and starts the count-down sequence.

-

A read reflects the current value of the timer.

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Chapter 15: LPC800 USART0/1/2

Rev. 1.0 — 7 November 2012

Preliminary user manual

15.1 How to read this chapter

USART0 and USART1 are available on all parts. USART2 is available on parts

LPC812M101FDH16 and LPC812M101FDH20 only.

Read this chapter for a description of the USART peripheral and the software interface.

The LPC800 also provides an on-chip ROM-based USART API to configure and operate

the USART. See Table 271.

15.2 Features

• 7, 8, or 9 data bits and 1 or 2 stop bits

• Synchronous mode with master or slave operation. Includes data phase selection and

continuous clock option.

• Multiprocessor/multidrop (9-bit) mode with software address compare. (RS-485

possible with software address detection and transceiver direction control.)

• Parity generation and checking: odd, even, or none.

• One transmit and one receive data buffer.

• RTS/CTS for hardware signaling for automatic flow control. Software flow control can

be performed using Delta CTS detect, Transmit Disable control, and any GPIO as an

RTS output.

• Received data and status can optionally be read from a single register

• Break generation and detection.

• Receive data is 2 of 3 sample "voting". Status flag set when one sample differs.

• Built-in Baud Rate Generator.

• A fractional rate divider is shared among all UARTs.

• Interrupts available for Receiver Ready, Transmitter Ready, Receiver Idle, change in

receiver break detect, Framing error, Parity error, Overrun, Underrun, Delta CTS

detect, and receiver sample noise detected.

• Separate data and flow control loopback modes for testing.

• Baud rate clock can also be output in asynchronous mode.

15.3 Basic configuration

Remark: The on-chip USART API provides software routines to configure and use the

USART. See Table 271.

Configure USART0/1/2 for receiving and transmitting data:

• In the SYSAHBCLKCTRL register, set bit 14 to 16 (Table 18) to enable the clock to

the register interface.

• Clear the USART0/1/2 peripheral resets using the PRESETCTRL register (Table 7).

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Chapter 15: LPC800 USART0/1/2

• Enable or disable the USART0/1/2 interrupts in slots #3 to 5 in the NVIC.

• Configure the USART0/1/2 pin functions through the switch matrix. See Section 15.4.

• Configure the USART clock and baud rate. See Section 15.3.1.

Configure the USART0/1/2 to wake up the part from low power modes:

• Configure the USART to receive and transmit data in synchronous slave mode. See

Section 15.3.2.

15.3.1 Configure the USART clock and baud rate

All three USARTs use a common peripheral clock (U_PCLK) and, if needed, a fractional

baud rate generator.The peripheral clock and the fractional divider for the baud rate

calculation are set up in the SYSCON block as follows (see Figure 21):

1. Configure the UART clock by writing a value UARTCLKDIV > 0 in the USART

peripheral clock divider register. This is the divided main clock common to all

USARTs.

Section 4.6.14 “USART clock divider register”

2. If a fractional value is needed to obtain a particular baud rate, program the fractional

divider. The fractional divider value is the fraction of MULT/DIV. The MULT value is

programmed in the UARTFRGMULT register and the DIV value is programmed in the

UARTFRGDIV register in the SYSCON block.

U_PCLK = UARTCLKDIV/(1+MULT/DIV)

The following rules apply for MULT and DIV:

– Always set DIV to 256 by programming the UARTFRGDIV register with the value

of 0xFF.

– Program any value between 0 and 255 in the UARTFRGMULT register.

– The fraction of MULT/DIV must be smaller than 1.

Section 4.6.19 “USART fractional generator multiplier value register”

Section 4.6.18 “USART fractional generator divider value register”

3. In asynchronous mode: Configure the baud rate divider BRGVAL in the USARTn BRG

register. The baud rate divider divides the common USART peripheral clock by a

factor of 16 multiplied by the baud rate value to provide the

baud rate = U_PCLK/16 x BRGVAL.

Section 15.6.9 “USART Baud Rate Generator register”

4. In synchronous mode: The serial clock is Un_SCLK = U_PCLK/BRGVAL

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Chapter 15: LPC800 USART0/1/2

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Fig 21. USART clocking

For details on the clock configuration see:

Section 15.7.1 “Clocking and Baud rates”

15.3.2 Configure the USART for wake-up

The USART can wake up the system from sleep mode in asynchronous or synchronous

mode on any enabled USART interrupt.

If the USART is configured for synchronous slave mode, the USART block can create an

interrupt on a received signal even when the USART block receives no clocks from the

ARM Cortex-M0+ core - that is in Deep-sleep or Power-down mode.

As long as the USART receives a clock signal from the master, it can receive up to one

byte in the RXDATA register while in Deep-sleep or Power-down mode. Any interrupt

raised as part of the receive data process can then wake up the part.

15.3.2.1 Wake-up from Sleep mode

• Configure the USART in either asynchronous mode or synchronous mode. See

Table 158.

• Enable the USART interrupt in the NVIC.

• Any USART interrupt wakes up the part from sleep mode. Enable the USART

interrupt in the INTENSET register (Table 161).

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Chapter 15: LPC800 USART0/1/2

15.3.2.2 Wake-up from Deep-sleep or Power-down mode

• Configure the USART in synchronous slave mode. See Table 158. You must connect

the SCLK function to a pin and connect the pin to the master.

• Enable the USART interrupt in the STARTERP1 register. See Table 34 “Start logic 1

interrupt wake-up enable register (STARTERP1, address 0x4004 8214) bit

description”.

• Enable the USART interrupt in the NVIC.

• The USART wakes up the part from Deep-sleep or Power-down mode on all events

that cause an interrupt and also are enabled in the INTENSET register. Typical

wake-up events are:

– A received start bit has been detected.

– An address bit has been sent.

– The RXDATA buffer has received one byte and is full.

– Data are ready to be transmitted in the TXDATA buffer and a serial clock from the

master has been received.

– A change in the state of the CTS pin if the CTS function is connected. <tbd>

– Remark: By enabling or disabling the interrupt in the INTENSET register

(Table 161), you can customize when the wake-up occurs in the USART

receive/transmit protocol.

15.4 Pin description

The USART receive, transmit, and control signals are movable functions and are

assigned to external pins through the switch matrix.

See Section 9.3.1 “Connect an internal signal to a package pin” to assign the USART

functions to pins on the LPC800 package.

Table 156. USART pin description

Function Direction Pin

Description

SWM register Reference

U0_TXD

U0_RXD

U0_RTS

O

I

any

Transmitter output for USART0. Serial transmit data.

Receiver input for USART0. Serial receive data.

PINASSIGN0

Table 96

O

Request To Send output for USART0. Active low signal for PINASSIGN0

supports inter-processor communication through the use of

hardware flow control. This feature is active when the

USART RTS signal is configured to appear on a device pin.

U0_CTS

I

any

Clear To Send input for USART0. Active low signal indicates PINASSIGN0

if the external device that is in communication with the

USART is ready to accept data. This feature is active when

enabled by the CTSEn bit in CFG register and when

configured to appear on a device pin. When deasserted

(high) by the external device, the USART will complete

transmitting any character already in progress, then stop

until CTS is again asserted (low).

Table 96

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Chapter 15: LPC800 USART0/1/2

Table 156. USART pin description

Function Direction Pin

Description

SWM register Reference

U0_SCLK I/O

any

Serial clock input/output for USART0 in synchronous mode. PINASSIGN1

Table 97

Clock input or output in synchronous mode. If connected to

a pin in asynchronous mode, will output the baud rate clock

if the SYNCMST bit in CFG register is set to 1.

U1_TXD

U1_RXD

U1_RTS

U1_CTS

O

I

any

Transmitter output for USART1. Serial transmit data.

Receiver input for USART1.

PINASSIGN1

PINASSIGN2

Table 97

Table 98

Table 99

O

I

Request To Send output for USART1.

Clear To Send input for USART1.

U1_SCLK I/O

Serial clock input/output for USART1 in synchronous mode. PINASSIGN2

U2_TXD

U2_RXD

U2_RTS

U2_CTS

O

I

Transmitter output for USART2. Serial transmit data.

Receiver input for USART2.

PINASSIGN2

PINASSIGN3

O

I

Request To Send output for USART2.

Clear To Send input for USART2.

U0_SCLK I/O

Serial clock input/output for USART2 in synchronous mode. PINASSIGN3

15.5 General description

The USART receiver block monitors the serial input line, Un_RXD, for valid input. The

receiver shift register assembles characters as they are received, after which they are

passed to the receiver buffer register to await access by the CPU.

The USART transmitter block accepts data written by the CPU and buffers the data in the

transmit holding register. When the transmitter is available, the transmit shift register takes

that data, formats it, and serializes it to the serial output, Un_TXD.

The Baud Rate Generator block divides the incoming clock to create a 16x baud rate

clock in the standard asynchronous operating mode. The BRG clock input source is the

shared Fractional Rate Generator that runs from the common USART peripheral clock

U_PCLK).

In synchronous slave mode, data is transmitted and received using the serial clock

directly. In synchronous master mode, data is transmitted and received using the baud

rate clock without division.

Status information from the transmitter and receiver is saved and provided via the Stat

register. Many of the status flags are able to generate interrupts, as selected by software.

Remark: The fractional value and the USART peripheral clock are shared between all

USARTs.

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UM10601

NXP Semiconductors

Chapter 15: LPC800 USART0/1/2

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U_PCLK = UARTCLKDIV/(1+MULT/DIV)

Fig 22. USART block diagram

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Chapter 15: LPC800 USART0/1/2

15.6 Register description

The reset value reflects the data stored in used bits only. It does not include the content of

reserved bits.

Table 157: Register overview: USART (base address 0x4006 4000 (USART0), 0x4006 8000 (USART1), 0x4006 C000

(USART2))

Name

Access Offset

Description

Reset

value

Reference

Table 158

Table 159

CFG

R/W

0x000

0x004

0x008

USART Configuration register. Basic USART configuration

settings that typically are not changed during operation.

0

CTRL

STAT

USART Control register. USART control settings that are more

likely to change during operation.

0

USART Status register. The complete status value can be read 0x000E Table 160

here. Writing 1s clears some bits in the register. Some bits can

be cleared by writing a 1 to them.

INTENSET

INTENCLR

R/W

W

0x00C

0x010

Interrupt Enable read and Set register. Contains an individual

interrupt enable bit for each potential USART interrupt. A

complete value may be read from this register. Writing a 1 to any

implemented bit position causes that bit to be set.

0

Table 161

Interrupt Enable Clear register. Allows clearing any combination

of bits in the INTENSET register. Writing a 1 to any implemented

bit position causes the corresponding bit to be cleared.

-

Table 162

RXDATA

R

0x014

0x018

Receiver Data register. Contains the last character received.

-

Table 163

Table 164

RXDATASTAT

Receiver Data with Status register. Combines the last character

received with the current USART receive status. Allows software

to recover incoming data and status together.

TXDATA

BRG

R/W

0x01C

0x020

Transmit Data register. Data to be transmitted is written here.

0

Table 165

Table 166

Baud Rate Generator register. 16-bit integer baud rate divisor

value.

INTSTAT

R

0x024

Interrupt status register. Reflects interrupts that are currently

enabled.

0x0005 Table 167

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Chapter 15: LPC800 USART0/1/2

15.6.1 USART Configuration register

The CFG register contains communication and mode settings for aspects of the USART

that would normally be configured once in an application.

Remark: If software needs to change configuration values, the following sequence should

be used: 1) Make sure the USART is not currently sending or receiving data. 2) Disable

the USART by writing a 0 to the Enable bit (0 may be written to the entire register). 3)

Write the new configuration value, with the ENABLE bit set to 1.

Table 158. USART Configuration register (CFG, address 0x4006 4000 (USART0), 0x4006 8000

(USART1), 0x4006 C000 (USART2)) bit description

Bit

Symbol

Value Description

Reset

Value

0

ENABLE

USART Enable.

0

1

Disabled. The USART is disabled and the internal state

machine and counters are reset. While Enable = 0, all

USART interrupts are disabled. When Enable is set again,

CFG and most other control bits remain unchanged. For

instance, when re-enabled, the USART will immediately

generate a TxRdy interrupt if enabled because the

transmitter has been reset and is therefore available.

Enabled. The USART is enabled for operation.

1

-

Reserved. Read value is undefined, only zero should be

written.

NA

00

3:2

DATALEN

Selects the data size for the USART.

7 bit Data length.

0x0

0x1

0x2

8 bit Data length.

9 bit data length. The 9th bit is commonly used for

addressing in multidrop mode. See the ADDRDET bit in the

CTRL register.

0x3

Reserved.

5:4

PARITYSEL

Selects what type of parity is used by the USART.

00

0x0

0x1

0x2

No parity.

Reserved.

Even parity. Adds a bit to each character such that the

number of 1s in a transmitted character is even, and the

number of 1s in a received character is expected to be even.

0x3

Odd parity. Adds a bit to each character such that the

number of 1s in a transmitted character is odd, and the

number of 1s in a received character is expected to be odd.

6

STOPLEN

Number of stop bits appended to transmitted data. Only a

single stop bit is required for received data.

0

1

1 stop bit.

2 stop bits. This setting should only be used for

asynchronous communication.

7

8

-

Reserved. Only write 0 to this bit.

Reserved. Read value is undefined, only zero should be

written.

NA

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Table 158. USART Configuration register (CFG, address 0x4006 4000 (USART0), 0x4006 8000

(USART1), 0x4006 C000 (USART2)) bit description …continued

Bit

Symbol

Value Description

Reset

Value

9

CTSEN

CTS Enable. Determines whether CTS is used for flow

0

control. CTS can be from the input pin, or from the USART’s

own RTS if loopback mode is enabled. See Section 15.7.3

for more information.

0

1

No flow control. The transmitter does not receive any

automatic flow control signal.

Flow control enabled. The transmitter uses external or

internal CTS for flow control purposes.

10

11

-

Reserved. Read value is undefined, only zero should be

written.

NA

0

SYNCEN

Selects synchronous or asynchronous operation.

Asynchronous mode is selected.

0

1

Synchronous mode is selected.

12

CLKPOL

Selects the clock polarity and sampling edge of received

data in synchronous mode.

0

1

Falling edge. Un_RXD is sampled on the falling edge of

SCLK.

Rising edge. Un_RXD is sampled on the rising edge of

SCLK.

13

14

-

Reserved. Read value is undefined, only zero should be

written.

NA

0

SYNCMST

Synchronous mode Master select.

0

1

Slave. When synchronous mode is enabled, the USART is a

slave.

Master. When synchronous mode is enabled, the USART is

a master. In asynchronous mode, the baud rate clock will be

output on SCLK if it is connected to a pin.

15

LOOP

Selects data loopback mode.

Normal operation.

0

1

Loopback mode. This provides a mechanism to perform

diagnostic loopback testing for USART data. Serial data

from the transmitter (Un_TXD) is connected internally to

serial input of the receive (Un_RXD). Un_TXD and Un_RTS

activity will also appear on external pins if these functions

are configured to appear on device pins. The receiver RTS

signal is also looped back to CTS and performs flow control

if enabled by CTSEN.

31:16 -

Reserved. Read value is undefined, only zero should be

written.

NA

15.6.2 USART Control register

The CTRL register controls aspects of USART operation that are more likely to change

during operation.

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Table 159. USART Control register (CTRL, address 0x4006 4004 (USART0), 0x4006 8004

(USART1), 0x4006 C004 (USART2)) bit description

Bit

Symbol

Value Description

Reset

Value

0

-

Reserved. Read value is undefined, only zero should be

NA

written.

1

TXBRKEN

Break Enable.

Normal operation.

0

1

Continuous break is sent immediately when this bit is set,

and remains until this bit is cleared.

A break may be sent without danger of corrupting any

currently transmitting character if the transmitter is first

disabled (TXDIS in CTRL is set) and then waiting for the

transmitter to be disabled (TXDISINT in STAT = 1) before

writing 1 to TXBRKEN.

2

ADDRDET

Enable address detect mode.

0

1

Enabled. The USART receiver is enabled for all incoming

data.

Disabled. The USART receiver ignores incoming data that

does not have the most significant bit of the data (typically

the 9th bit) = 1. When the data MSB bit = 1, the receiver

treats the incoming data normally, generating a received data

interrupt. Software can then check the data to see if this is an

address that should be handled. If it is, the ADDRDET bit is

cleared by software and further incoming data is handled

normally.

5:3

6

-

Reserved. Read value is undefined, only zero should be

written.

NA

0

TXDIS

Transmit Disable.

0

1

Not disabled. USART transmitter is not disabled.

Disabled. USART transmitter is disabled after any character

currently being transmitted is complete. This feature can be

used to facilitate software flow control.

7

8

-

Reserved. Read value is undefined, only zero should be

written.

NA

0

CC

Continuous Clock generation. By default, SCLK is only

output while data is being transmitted in synchronous mode.

0

1

Clock on character. In synchronous mode, SCLK cycles only

when characters are being sent on Un_TXD or to complete a

character that is being received.

Continuous clock. SCLK runs continuously in synchronous

mode, allowing characters to be received on Un_RxD

independently from transmission on Un_TXD).

9

CLRCC

Clear Continuous Clock.

No affect on the CC bit.

0

1

Auto-clear. The CC bit is automatically cleared when a

complete character has been received. This bit is cleared at

the same time.

31:10 -

Reserved. Read value is undefined, only zero should be

written.

NA

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15.6.3 USART Status register

The STAT register primarily provides a complete set of USART status flags for software to

read. Flags other than read-only flags may be cleared by writing ones to corresponding

bits of STAT.

The error flags (for received noise, parity error, framing error, and overrun) are set

immediately upon detection and remain set until cleared by software action in STAT.

Table 160. USART Status register (STAT, address 0x4006 4008 (USART0), 0x4006 8008 (USART1), 0x4006

C008(USART2)) bit description

Bit

Symbol

RXRDY

RXIDLE

Description

Reset Acces

value

s^[1]

0

Receiver Ready flag. When 1, indicates that data is available to be read from the

receiver buffer. Cleared after a read of the RXDATA or RXDATASTAT registers.

0

RO

1

Receiver Idle. When 0, indicates that the receiver is currently in the process of

receiving data. When 1, indicates that the receiver is not currently in the process

of receiving data.

1

RO

2

TXRDY

Transmitter Ready flag. When 1, this bit indicates that data may be written to the

transmit buffer. Previous data may still be in the process of being transmitted.

Cleared when data is written to TXDATA until the data is moved to the transmit

shift register.

3

4

TXIDLE

CTS

Transmitter Idle. When 0, indicates that the transmitter is currently in the process

of sending data.When 1, indicate that the transmitter is not currently in the

process of sending data.

1

RO

This bit reflects the current state of the CTS signal, regardless of the setting of

the CTSEN bit in the CFG register. This will be the value of the CTS input pin

unless loopback mode is enabled.

NA

5

6

DELTACTS

TXDISINT

This bit is set when a change in the state is detected for the CTS flag above. This

bit is cleared by software.

0

W1

RO

Transmitter Disabled Interrupt flag. When 1, this bit indicates that the USART

transmitter is fully idle after being disabled via the TXDIS in the CFG register

(TXDIS = 1).

7

8

-

Reserved. Read value is undefined, only zero should be written.

NA

0

NA

W1

OVERRUNINT

Overrun Error interrupt flag. This flag is set when a new character is received

while the receiver buffer is still in use. If this occurs, the newly received character

in the shift register is lost.

9

-

Reserved. Read value is undefined, only zero should be written.

NA

0

NA

RO

10

RXBRK

Received Break. This bit reflects the current state of the receiver break detection

logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that

FRAMERRINT will also be set when this condition occurs because the stop bit(s)

for the character would be missing. RXBRK is cleared when the Un_RXD pin

goes high.

11

12

DELTARXBRK

START

This bit is set when a change in the state of receiver break detection occurs.

Cleared by software.

0

W1

This bit is set when a start is detected on the receiver input and subsequently

confirmed by a mid-bit sample. Its purpose is primarily to allow wakeup from

Power-down mode immediately when a start is detected. Cleared by software.

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Table 160. USART Status register (STAT, address 0x4006 4008 (USART0), 0x4006 8008 (USART1), 0x4006

C008(USART2)) bit description

Bit

Symbol

Description

Reset Acces

value

s^[1]

13

FRAMERRINT

Framing Error interrupt flag. This flag is set when a character is received with a

missing stop bit at the expected location. This could be an indication of a baud

rate or configuration mismatch with the transmitting source.

0

W1

14

15

PARITYERRINT Parity Error interrupt flag. This flag is set when a parity error is detected in a

received character, if parity is enabled via the Parity field in the CFG register.

0

W1

RXNOISEINT

Received Noise interrupt flag. This bit is valid when there is a character to be

read in the RXDATA register and reflects the status of that character. Three

samples of received data are taken in order to determine the value of each

received data bit, except in synchronous mode. This acts as a noise filter if one

sample disagrees. The Noise bit is set when a received data bit contains one

disagreeing sample. This could indicate line noise, a baud rate or character

format mismatch, or loss of synchronization during data reception. RXNOISEINT

is not updated during a received break.

31:16 -

Reserved. Read value is undefined, only zero should be written.

NA

[1] RO = Read-only, W1 = write 1 to clear.

15.6.4 USART Interrupt Enable read and set register

The INTENSET register is used to enable various USART interrupt sources. Enable bits in

INTENSET are mapped in locations that correspond to the flags in the STAT register. The

complete set of interrupt enables may be read from this register. Writing ones to

implemented bits in this register causes those bits to be set. The INTENCLR register is

used to clear bits in this register.

Table 161. USART Interrupt Enable read and set register (INTENSET, address 0x4006

400C(USART0), 0x4006 800C (USART1), 0x4006 C00C(USART2)) bit description

Bit

Symbol

RXRDYEN

-

Description

Reset

Value

0

When 1, enables an interrupt when there is a received

character available to be read from the RXDATA register.

0

NA

0

1

Reserved. Read value is undefined, only zero should be

written.

2

TXRDYEN

-

When 1, enables an interrupt when the TXDATA register is

available to take another character to transmit.

4:3

5

Reserved. Read value is undefined, only zero should be

written.

NA

0

DELTACTSEN

TXDISINTEN

When 1, enables an interrupt when there is a change in the

state of the CTS input.

6

When 1, enables an interrupt when the transmitter is fully

disabled as indicated by the TXDISINT flag in STAT. See

description of the TXDISINT bit for details.

0

7

8

-

Reserved. Read value is undefined, only zero should be

written.

NA

0

OVERRUNEN

When 1, enables an interrupt when an overrun error

occurred.

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Table 161. USART Interrupt Enable read and set register (INTENSET, address 0x4006

400C(USART0), 0x4006 800C (USART1), 0x4006 C00C(USART2)) bit description

Bit

10:9

11

Symbol

Description

Reset

Value

-

Reserved. Read value is undefined, only zero should be

written.

NA

DELTARXBRKEN

When 1, enables an interrupt when a change of state has

occurred in the detection of a received break condition

(break condition asserted or deasserted).

0

12

13

14

15

STARTEN

When 1, enables an interrupt when a received start bit has

been detected.

0

FRAMERREN

PARITYERREN

RXNOISEEN

When 1, enables an interrupt when a framing error has been

detected.

When 1, enables an interrupt when a parity error has been

detected.

0

When 1, enables an interrupt when noise is detected. See

description of the RXNOISEINT bit in Table 160.

0

31:16 -

Reserved. Read value is undefined, only zero should be

written.

NA

15.6.5 USART Interrupt Enable Clear register

The INTENCLR register is used to clear bits in the INTENSET register.

Table 162. USART Interrupt Enable clear register (INTENCLR, address 0x4006

4010(USART0), 0x4006 8010 (USART1), 0x4006 C010(USART2)) bit description

Bit

0

Symbol

Description

Reset

Value

RXRDYCLR

Writing 1 clears the corresponding bit in the INTENSET

register.

0

1

-

Reserved. Read value is undefined, only zero should be

written.

NA

0

2

TXRDYCLR

Writing 1 clears the corresponding bit in the INTENSET

register.

4:3

5

-

Reserved. Read value is undefined, only zero should be

written.

NA

0

DELTACTSCLR

Writing 1 clears the corresponding bit in the INTENSET

register.

6

TXDISINTCLR

Writing 1 clears the corresponding bit in the INTENSET

register.

0

7

-

Reserved. Read value is undefined, only zero should be

written.

NA

0

8

OVERRUNCLR

-

Writing 1 clears the corresponding bit in the INTENSET

register.

10:9

11

Reserved. Read value is undefined, only zero should be

written.

NA

0

DELTARXBRKCLR Writing 1 clears the corresponding bit in the INTENSET

register.

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Table 162. USART Interrupt Enable clear register (INTENCLR, address 0x4006

4010(USART0), 0x4006 8010 (USART1), 0x4006 C010(USART2)) bit description

Bit

12

13

14

15

Symbol

Description

Reset

Value

STARTCLR

Writing 1 clears the corresponding bit in the INTENSET

register.

0

FRAMERRCLR

PARITYERRCLR

RXNOISECLR

Writing 1 clears the corresponding bit in the INTENSET

register.

0

Writing 1 clears the corresponding bit in the INTENSET

register.

Writing 1 clears the corresponding bit in the INTENSET

register.

0

31:16 -

Reserved. Read value is undefined, only zero should be

written.

NA

15.6.6 USART Receiver Data register

The RXDATA register contains the last character received before any overrun.

Remark: Reading this register changes the status flags in the RXDATASTAT register.

Table 163. USART Receiver Data register (RXDATA, address 0x4006 4014 (USART0), 0x4006

8014 (USART1), 0x4006 C014 (USART2)) bit description

Bit

Symbol Description

Reset Value

8:0

RXDAT The USART Receiver Data register contains the next received

character. The number of bits that are relevant depends on the

USART configuration settings.

0

31:9

-

Reserved, the value read from a reserved bit is not defined.

NA

15.6.7 USART Receiver Data with Status register

The RXDATASTAT register contains the next complete character to be read and its

relevant status flags. This allows getting all information related to a received character

with one 16-bit read.

Remark: Reading this register changes the status flags.

Table 164. USART Receiver Data with Status register (RXDATASTAT, address 0x4006 4018

(USART0), 0x4006 8018 (USART1), 0x4006 C018 (USART2)) bit description

Bit

Symbol

Description

Reset

Value

8:0

RXDAT

The USART Receiver Data register contains the next received

character. The number of bits that are relevant depends on the

USART configuration settings.

0

12:9

13

-

Reserved, the value read from a reserved bit is not defined.

NA

0

FRAMERR

Framing Error status flag. This bit is valid when there is a character

to be read in the RXDATA register and reflects the status of that

character. This bit will set when the character in RXDAT was

received with a missing stop bit at the expected location. This

could be an indication of a baud rate or configuration mismatch

with the transmitting source.

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Table 164. USART Receiver Data with Status register (RXDATASTAT, address 0x4006 4018

(USART0), 0x4006 8018 (USART1), 0x4006 C018 (USART2)) bit description

Bit

Symbol

Description

Reset

Value

14

PARITYERR Parity Error status flag. This bit is valid when there is a character to

be read in the RXDATA register and reflects the status of that

character. This bit will be set when a parity error is detected in a

received character.

0

15

RXNOISE

Received Noise flag. See description of the RxNoiseInt bit in

Table 160.

0

31:16 -

Reserved, the value read from a reserved bit is not defined.

NA

15.6.8 USART Transmitter Data Register

The TXDATA register is written in order to send data via the USART transmitter. That data

will be transferred to the transmit shift register when it is available, and another character

may then be written to TXDATA.

Table 165. USART Transmitter Data Register (TXDATA, address 0x4006 401C (USART0),

0x4006 801C (USART1), 0x4006 C01C (USART2)) bit description

Bit

Symbol

TXDAT

-

Description

Reset

Value

8:0

Writing to the USART Transmit Data Register causes the data to be

transmitted as soon as the transmit shift register is available.

0

31:9

Reserved. Only zero should be written.

NA

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15.6.9 USART Baud Rate Generator register

The Baud Rate Generator is a simple 16-bit integer divider controlled by the BRG register.

The BRG register contains the value used to divide the base clock in order to produce the

clock used for USART internal operations.

A 16-bit value allows producing standard baud rates from 300 baud and lower at the

highest frequency of the device, up to 921,600 baud from a base clock as low as 14.7456

MHz.

Typically, the baud rate clock is 16 times the actual baud rate. This overclocking allows for

centering the data sampling time within a bit cell, and for noise reduction and detection by

taking three samples of incoming data.

Details on how to select the right values for BRG can be found later in this chapter, see

Section 15.7.1.

Remark: If software needs to change the baud rate, the following sequence should be

used: 1) Make sure the USART is not currently sending or receiving data. 2) Disable the

USART by writing a 0 to the Enable bit (0 may be written to the entire registers). 3) Write

the new BRGVAL. 4) Write to the CFG register to set the Enable bit to 1.

Table 166. USART Baud Rate Generator register (BRG, address 0x4006 4020 (USART0),

0x4006 8020 (USART1), 0x4006 C020 (USART2)) bit description

Bit

Symbol

Description

Reset

Value

15:0 BRGVAL This value is used to divide the USART input clock to determine the

baud rate, based on the input clock from the FRG.

0

0 = The FRG clock is used directly by the USART function.

1 = The FRG clock is divided by 2 before use by the USART function.

2 = The FRG clock is divided by 3 before use by the USART function.

...

0xFFFF = The FRG clock is divided by 65,536 before use by the

USART function.

31:16 -

Reserved. Read value is undefined, only zero should be written.

NA

15.6.10 USART Interrupt Status register

The read-only INTSTAT register provides a view of those interrupt flags that are currently

enabled. This can simplify software handling of interrupts. See Table 160 for detailed

descriptions of the interrupt flags.

Table 167. USART Interrupt Status register (INTSTAT, address 0x4006 4024 (USART0),

0x4006 8024 (USART1), 0x4006 C024(USART2)) bit description

Bit

Symbol

Description

Reset

Value

0

1

RXRDY

-

Receiver Ready flag.

0

Reserved. Read value is undefined, only zero should be

written.

NA

2

TXRDY

Transmitter Ready flag.

1

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Table 167. USART Interrupt Status register (INTSTAT, address 0x4006 4024 (USART0),

0x4006 8024 (USART1), 0x4006 C024(USART2)) bit description

Bit

4:3

5

Symbol

Description

Reset

Value

-

Reserved. Read value is undefined, only zero should be

written.

NA

DELTACTS

This bit is set when a change in the state of the CTS input is

detected.

0

6

7

TXDISINT

-

Transmitter Disabled Interrupt flag.

0

Reserved. Read value is undefined, only zero should be

written.

NA

8

OVERRUNINT

-

Overrun Error interrupt flag.

0

10:9

Reserved. Read value is undefined, only zero should be

written.

NA

11

DELTARXBRK

This bit is set when a change in the state of receiver break

detection occurs.

0

12

13

14

15

START

This bit is set when a start is detected on the receiver input.

Framing Error interrupt flag.

0

FRAMERRINT

PARITYERRINT Parity Error interrupt flag.

0

RXNOISEINT

Received Noise interrupt flag.

0

31:16 -

Reserved. Read value is undefined, only zero should be

written.

NA

15.7 Functional description

15.7.1 Clocking and Baud rates

In order to use the USART, clocking details must be defined such as setting up the BRG,

and typically also setting up the FRG. See Figure 21.

15.7.1.1 Fractional Rate Generator (FRG)

The Fractional Rate Generator can be used to obtain more precise baud rates when the

peripheral clock is not a good multiple of standard (or otherwise desirable) baud rates.

The FRG is typically set up to produce an integer multiple of the highest required baud

rate, or a very close approximation. The BRG is then used to obtain the actual baud rate

needed.

The FRG register controls the USART Fractional Rate Generator, which provides the

base clock for the USART. The Fractional Rate Generator creates a lower rate output

clock by suppressing selected input clocks. When not needed, the value of 0 can be set

for the FRG, which will then not divide the input clock.

The FRG output clock is defined as the inputs clock divided by 1 + (MULT / 256), where

MUTL is in the range of 1 to 255. This allows producing an output clock that ranges from

the input clock divided by 1+1/256 to 1+255/256 (just more than 1 to just less than 2). Any

further division can be done specific to each USART block by the integer BRG divider

contained in each USART.

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The base clock produced by the FRG cannot be perfectly symmetrical, so the FRG

distributes the output clocks as evenly as is practical. Since the USART normally uses 16x

overclocking, the jitter in the fractional rate clock in these cases tends to disappear in the

ultimate USART output.

For setting up the fractional divider use the following registers:

Table 23 “USART fractional generator divider value register (UARTFRGDIV, address

0x4004 80F0) bit description”

Table 24 “USART fractional generator multiplier value register (UARTFRGMULT, address

0x4004 80F4) bit description”

For details see Section 15.3.1 “Configure the USART clock and baud rate”.

15.7.1.2 Baud Rate Generator (BRG)

The Baud Rate Generator (see Section 15.6.9) is used to divide the base clock to produce

a rate 16 times the desired baud rate. Typically, standard baud rates can be generated by

integer divides of higher baud rates.

15.7.1.3 Baud rate calculations

Base clock rates are 16x for asynchronous mode and 1x for synchronous mode.

15.7.2 Synchronous mode

Remark: Sync mode transmit and receive operate at the incoming clock rate in slave

mode and the BRG selected rate (not divided by 16) in master mode.

15.7.3 Flow control

The USART supports both hardware and software flow control.

15.7.3.1 Hardware flow control

The USART supports hardware flow control using RTS and/or CTS signalling. If RTS is

configured to appear on a device pin so that it can be sent to an external device, it

indicates to an external device the ability of the receiver to receive more data. It can also

be used internally to throttle the transmitter from the receiver, which can be especially

useful if loopback mode is enabled.

If connected to a pin, and if enabled to do so, the CTS input can allow an external device

to throttle the USART transmitter. Both internal and external CTS can be used separately

or together.

Figure 23 shows an overview of RTS and CTS within the USART.

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Chapter 15: LPC800 USART0/1/2

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15.7.3.2 Software flow control

Software flow control could include XON / XOFF flow control, or other mechanisms. these

are supported by the ability to check the current state of the CTS input, and/or have an

interrupt when CTS changes state (via the CTS and DELTACTS bits, respectively, in the

STAT register), and by the ability of software to gracefully turn off the transmitter (via the

TXDIS bit in the CTRL register).

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Chapter 16: LPC800 I2C-bus interface

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16.1 How to read this chapter

The I2C-bus interface is available on all parts.

Read this chapter if you want to understand the I2C operation and the software interface

and want to learn how to use the I2C for wake-up from reduced power modes.

The LPC800 provides an on-chip ROM-based I2C API to configure and operate the I2C.

See Table 250 “I2C API calls”.

16.2 Features

• Independent Master, Slave, and Monitor functions.

• Supports both Multi-master and Multi-master with Slave functions.

• Multiple I²C slave addresses supported in hardware.

• One slave address can be selectively qualified with a bit mask or an address range in

order to respond to multiple I²C bus addresses.

• 10-bit addressing supported with software assist.

• Supports SMBus.

16.3 Basic configuration

Configure I2C using the following registers:

• In the SYSAHBCLKCTRL register, set bit 5 (Table 18) to enable the clock to the

register interface.

• Clear the I2C peripheral reset using the PRESETCTRL register (Table 7).

• Enable/disable the I2C interrupt in interrupt slots #8 in the NVIC.

• Configure the I2C pin functions through the switch matrix. See Section 16.4.

• The peripheral clock for the I2C is the system clock (see Figure 24).

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Fig 24. I2C clocking

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Chapter 16: LPC800 I2C-bus interface

16.4 Pin description

The I2C pins are movable pin functions and are assigned to pins on the LPC800

packages through the switch matrix. You have two choices to connect the I2C pins:

1. Connect to special I2C open-drain pins (PIO0_10 and PIO0_11).

2. Connect to any other pin that can host a movable function..

When the I²C function is connected to specialized I²C pins, it completely supports the

I²C-bus specification up to Fast Mode Plus (up to 1 MHz I²C).

When the I²C function is connected to standard pins that are set to open-drain mode, a

functional I²C-bus can be used in this way, but some aspects of the I²C-bus specification

may not be met. This can have an impact on the bus speed, noise filtering, and the

capability of powering down the device without affecting the bus.

See Section 9.3.1 “Connect an internal signal to a package pin” to assign the I2C pins to

any pin on the LPC800 package.

Table 168. I2C-bus pin description

Function

Type Pin

Description

SWM register

Reference

I2C0_SCL

I/O any; use pin PIO0_10 or PIO0_11 for

I2C0 serial clock.

PINASSIGN8

Table 104

compatibility with the full I2C-bus specification.

I2C0_SDA I/O

any; use pin PIO0_10 or PIO0_11 for

I2C0 serial data.

PINASSIGN7

Table 103

compatibility with the full I2C-bus specification.

16.5 General description

The architecture of the I2C-bus interface is shown in Figure 25.

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Chapter 16: LPC800 I2C-bus interface

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Fig 25. I2C block diagram

16.6 Register description

The register functionalities can be grouped as follows:

• Common registers:

– Table 170 “I2C Configuration register (CFG, address 0x4005 0000) bit description”

– Table 171 “I²C Status register (STAT, address 0x4005 0004) bit description”

– Table 178 “I²C Interrupt Status register (INTSTAT, address 0x4005 0018) bit

description”

– Table 174 “Interrupt Enable Set and read register (INTENSET, address 0x4005

0008) bit description”

– Table 175 “Interrupt Enable Clear register (INTENCLR, address 0x4005 000C) bit

description”

– Table 176 “time-out register (TIMEOUT, address 0x4005 0010) bit description”

– Table 177 “I²C Clock Divider register (DIV, address 0x4005 0014) bit description”

• Master function registers:

– Table 179 “Master Control register (MSTCTL, address 0x4005 0020) bit

description”

– Table 180 “Master Time register (MSTTIME, address 0x4005 0024) bit description”

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– Table 181 “Master Data register (MSTDAT, address 0x4005 0028) bit description”

• Slave function registers:

– Table 182 “Slave Control register (SLVCTL, address 0x4005 0040) bit description”

– Table 184 “Slave Address registers (SLVADR[0:3]- address 0x4005 0048

(SLVADR0) to 0x4005 0054 (SLVADR3)) bit description”

– Table 185 “Slave address Qualifier 0 register (SLVQUAL0, address 0x4005 0058)

bit description”

• Monitor function register: Table 186 “Monitor data register (MONRXDAT, address

0x4005 0080) bit description”

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Table 169: Register overview: I2C (base address 0x4005 0000)

Name

Access Offset

Description

Reset

value

Reference

CFG

R/W

0x00

0x04

Configuration for shared functions.

0

Table 170

STAT

Status register for Master, Slave, and Monitor functions.

0x00080 Table 171

1

INTENSET

INTENCLR

TIMEOUT

DIV

R/W

W

0x08

0x0C

0x10

0x14

Interrupt Enable Set and read register.

Interrupt Enable Clear register.

Time-out value register.

Clock pre-divider for the entire I²C block. This determines what

time increments are used for the MSTTIME and SLVTIME

registers.

0

Table 174

Table 175

NA

R/W

0xFFFF Table 176

0

Table 177

INTSTAT

R

0x18

Interrupt Status register for Master, Slave, and Monitor

functions.

0

Table 178

MSTCTL

MSTTIME

MSTDAT

SLVCTL

R/W

0x20

0x24

0x28

0x40

0x44

0x48

0x4C

0x50

0x54

0x58

0x80

Master control register.

0

Table 179

Table 180

Table 181

Table 182

Table 183

Table 184

Table 185

Table 186

Master timing configuration.

Combined Master receiver and transmitter data register.

Slave control register.

0x77

NA

0

SLVDAT

Combined Slave receiver and transmitter data register.

Slave address 0.

NA

0x01

0

SLVADR0

SLVADR1

SLVADR2

SLVADR3

SLVQUAL0

Slave address 1.

Slave address 2.

Slave address 3.

Slave Qualification for address 0.

Monitor receiver data register.

MONRXDAT RO

0

16.6.1 I2C Configuration register

The CFG register contains mode settings that apply to Master, Slave, and Monitor

functions.

Table 170. I2C Configuration register (CFG, address 0x4005 0000) bit description

Bit Symbol

Value Description

Reset

Value

0

1

MSTEN

SLVEN

Master Enable. When disabled, configurations settings for

the Master function are not changed, but the Master

function is internally reset.

Disabled. The I²C Master function is disabled.

Enabled. The I²C Master function is enabled.

0

1

Slave Enable. When disabled, configurations settings for

the Slave function are not changed, but the Slave function

is internally reset.

0

1

Disabled. The I²C slave function is disabled.

Enabled. The I²C slave function is enabled.

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Table 170. I2C Configuration register (CFG, address 0x4005 0000) bit description

Bit Symbol Value Description

Reset

Value

2

MONEN

Monitor Enable. When disabled, configurations settings for

0

the Monitor function are not changed, but the Monitor

function is internally reset.

0

1

Disabled. The I²C monitor function is disabled.

Enabled. The I²C monitor function is enabled.

3

TIMEOUTEN

I²C bus Time-out Enable. When disabled, time-out flags

will be automatically cleared.

0

1

Disabled. Time-out function is disabled.

Enabled. Time-out function is enabled. Both types of

time-out flags will be generated and will cause interrupts if

they are enabled. Typically, only one time-out will be used

in a system.

4

MONCLKSTR

Monitor function Clock Stretching.

0

1

Disabled. The monitor function will not perform clock

stretching. Software may not always be able to read data

provided by the monitor function before it is overwritten.

This mode may be used when non-invasive monitoring is

critical.

Enabled. The monitor function will perform clock stretching

in order to ensure that software can read all incoming data

supplied by the monitor function.

31:5 -

Reserved. Read value is undefined, only zero should be

written.

NA

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16.6.2 I2C Status register

The STAT register provides status flags and state information about all of the functions of

the I²C block. Some information in this register is read-only, some flags can be cleared by

writing a 1 to them.

Access to bits in this register varies. RO = Read-only, W1 = write 1 to clear.

Details on the master and slave states described in the MSTSTATE and SLVSTATE bits in

this register are listed in Table 172 and Table 173.

Table 171. I²C Status register (STAT, address 0x4005 0004) bit description

Bit

Symbol

Value Description

Reset Acce

value

ss

0

MSTPENDING

Master Pending. Indicates whether the Master function needs software

1

RO

service. This flag will cause an interrupt when set if enabled via the

INTENSET register. The MSTPENDING flag is automatically cleared

when a 1 is written to the MSTCONTINUE bit in the MSTCTL register.

0

1

No service needed. The Master function does not currently need service.

Service needed. The Master function needs service. Information on what

is needed can be found in the adjacent MSTSTATE field.

3:1

MSTSTATE

Master State code. Each value of this field indicates a specific required

service for the Master function. All other values are reserved.

0

RO

0x0

0x1

Idle. The Master function is available to be used for a new transaction.

Receive ready. Received data available (Master Receiver mode).

Address plus Read was previously sent and Acknowledged by slave.

0x2

Transmit ready. Data can be transmitted (Master Transmitter mode).

Address plus Write was previously sent and Acknowledged by slave.

0x3

0x4

Address. Slave Nacked address.

Data. Slave Nacked transmitted data.

4

MSTARBLOSS

Master Arbitration Loss flag. This flag can be cleared by software writing

a 1 to this bit. It is also cleared automatically a 1 is written to

MSTCONTINUE.

0

W1

0

1

No loss. No Arbitration Loss has occurred.

Arbitration loss. The Master function has experienced an Arbitration

Loss.

At this point, the Master function has already stopped driving the bus and

gone to an idle state. Software can respond by doing nothing, or by

sending a Start in order to attempt to gain control of the bus when it next

becomes idle.

5

6

-

Reserved. Read value is undefined, only zero should be written.

NA

0

NA

W1

MSTSTSTPERR

Master Start/Stop Error flag. This flag can be cleared by software writing

a 1 to this bit. It is also cleared automatically a 1 is written to

MstContinue.

0

1

No Start/Stop Error has occurred.

Start/stop error has occurred. The Master function has experienced a

Start/Stop Error.

A Start or Stop was detected at a time when it is not allowed by the I²C

specification. The Master interface has stopped driving the bus and gone

to an idle state, no action is required. A request for a Start could be

made, or software could attempt to insure that the bus has not stalled.

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Table 171. I²C Status register (STAT, address 0x4005 0004) bit description …continued

Bit

Symbol

Value Description

Reset Acce

value

ss

NA

RO

7

8

-

Reserved. Read value is undefined, only zero should be written.

NA

SLVPENDING

Slave Pending. Indicates whether the Slave function needs software

service. This flag will cause an interrupt when set if enabled via

INTENSET. The SLVPENDING flag is read-only and is automatically

cleared when a 1 is written to the SLVCONTINUE bit in the MSTCTL

register.

0

1

No service needed. The Slave function does not currently need service.

Service needed. The Slave function needs service. Information on what

is needed can be found in the adjacent SLVSTATE field.

10:9 SLVSTATE

Slave State code. Each value of this field indicates a specific required

service for the Slave function. All other values are reserved.

0

RO

0x0

Received. Address plus R/W received. At least one of the four slave

addresses has been matched by hardware.

0x1

0x2

Data available. Received data is available (Slave Receiver mode).

Data ready for transmit. Data can be transmitted (Slave Transmitter

mode).

0x3

Reserved.

11

SLVNOTSTR

Slave Not Stretching. Indicates when the slave function is stretching the

I²C clock. This is needed in order to gracefully invoke Deep Sleep or

Power-down modes during slave operation. This read-only flag reflects

the slave function status in real time.

1

RO

0

1

Stretching. The slave function is currently stretching the I²C bus clock.

Deep-Sleep or Power-down mode cannot be entered at this time.

Not stretching. The slave function is not currently stretching the I²C bus

clock. Deep-sleep or Power-down mode could be entered at this time.

13:12 SLVIDX

Slave address match Index. This field is valid when the I²C slave function

has been selected by receiving an address that matches one of the slave

addresses defined by any enabled slave address registers, and provides

an identification of the address that was matched. It is possible that more

than one address could be matched, but only one match can be reported

here.

0

RO

0x0

0x1

0x2

0x3

Slave address 0 was matched.

Slave address 1 was matched.

Slave address 2 was matched.

Slave address 3 was matched.

14

SLVSEL

Slave selected flag. SLVSEL is set after an address match when

software tells the Slave function to acknowledge the address. It is cleared

when another address cycle presents an address that does not match an

enabled address on the Slave function, when slave software decides to

Nack a matched address, or when there is a Stop detected on the bus.

SLVSEL is not cleared if software Nacks data.

0

RO

0

1

Not selected. The Slave function is not currently selected.

Selected. The Slave function is currently selected.

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Table 171. I²C Status register (STAT, address 0x4005 0004) bit description …continued

Bit

Symbol

Value Description

Reset Acce

value

ss

15

SLVDESEL

Slave Deselected flag. This flag will cause an interrupt when set if

0

W1

enabled via INTENSET. This flag can be cleared by writing a 1 to this bit.

0

1

Not deselected. The Slave function has not become deselected. This

does not mean that it is currently selected. That information can be found

in the SLVSEL flag.

Deselected. The Slave function has become deselected. This is

specifically caused by the SLVSEL flag changing from 1 to 0. See the

description of SLVSEL for details on when that event occurs.

16

17

MONRDY

MONOV

Monitor Ready. This flag is cleared when the MONRXDAT register is

read.

0

RO

W1

0

1

No data. The Monitor function does not currently have data available.

Data waiting. The Monitor function has data waiting to be read.

Monitor Overflow flag.

0

1

No overrun. Monitor data has not overrun.

Overrun. A Monitor data overrun has occurred. This can only happen

when Monitor clock stretching not enabled via the MONCLKSTR bit in

the CFG register. Writing 1 to this bit clears the flag.

18

19

MONACTIVE

MONIDLE

Monitor Active flag. This flag indicates when the Monitor function

considers the I²C bus to be active. Active is defined here as when some

Master is on the bus: a bus Start has occurred more recently than a bus

Stop.

Inactive. The Monitor function considers the I²C bus to be inactive.

Active. The Monitor function considers the I²C bus to be active.

Monitor Idle flag. This flag is set when the Monitor function sees the I²C

bus change from active to inactive. This can be used by software to

decide when to process data accumulated by the Monitor function. This

flag will cause an interrupt when set if enabled via the INTENSET

register . The flag can be cleared by writing a 1 to this bit.

0

RO

W1

0

1

0

1

Not idle. The I²C bus is not idle, or this flag has been cleared by software.

Idle. The I²C bus has gone idle at least once since the last time this flag

was cleared by software.

23:20 -

24 EVENTTIMEOUT

Reserved. Read value is undefined, only zero should be written.

NA

0

NA

W1

Event Time-out Interrupt flag. Indicates when the time between events

has been longer than the time specified by the TIMEOUT register. Events

include Start, Stop, and clock edges. The case of SCL remaining low

longer than TIMEOUT is not reported by this flag, it is reported in by the

SCL Time-out flag. The flag is cleared by writing a 1 to this bit.

0

1

No time-out. I²C bus events have not caused a time-out.

Event time-out. The time between I²C bus events has been longer than

the time specified by the I2C TIMEOUT register.

25

SCLTIMEOUT

SCL Time-out Interrupt flag. Indicates when SCL has remained low

longer than the time specific by the TIMEOUT register. The flag is

cleared by writing a 1 to this bit.

0

W1

NA

0

1

No time-out. SCL low time has not caused a time-out.

Time-out. SCL low time has caused a time-out.

31:26 -

Reserved. Read value is undefined, only zero should be written.

NA

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Table 172: Master function state codes (MSTSTATE)

MstState Description

Actions

0

1

2

Idle. The Master function is available to be used for a new

transaction.

Send a Start or disable MstPending interrupt if

the Master function is not needed currently.

Received data is available (Master Receiver mode). Address Read data and either continue, send a Stop, or

plus Read was previously sent and Acknowledged by slave.

send a Repeated Start.

Data can be transmitted (Master Transmitter mode).

Send data and continue, or send a Stop or

Address plus Write was previously sent and Acknowledged by Repeated Start.

slave.

3

4

Slave Nacked address.

Send a Stop or Repeated Start.

Slave Nacked transmitted data.

Table 173: Slave function state codes (SLVSTATE)

SlvState Description

Actions

0

Address plus R/W received. At least one of the 4

slave addresses has been matched by hardware.

Software can further check the address if needed, for

instance if a subset of addresses qualified by SLVQUAL0

is to be used. Software can Ack or Nack the address by

writing 1 to either SLVCONTINUE or SLVNACK. Also see

Section 16.7.3 regarding 10-bit addressing.

1

2

3

Received data is available (Slave Receiver mode). Read data reply with an Ack or a Nack.

Data can be transmitted (Slave Transmitter mode). Send data.

Reserved.

-

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16.6.3 Interrupt Enable Set and read register

The INTENSET register controls which I²C status flags generate interrupts. Writing a 1 to

a bit position in this register enables an interrupt in the corresponding position in the STAT

register, if an interrupt is supported there. Reading INTENSET indicates which interrupts

are currently enabled.

Table 174. Interrupt Enable Set and read register (INTENSET, address 0x4005 0008) bit

description

Bit

Symbol

Value Description

Reset

value

0

MSTPENDINGEN

Master Pending interrupt Enable.

0

1

The MstPending interrupt is disabled.

The MstPending interrupt is enabled.

3:1

4

-

Reserved. Read value is undefined, only zero

should be written.

NA

0

MSTARBLOSSEN

Master Arbitration Loss interrupt Enable.

The MstArbLoss interrupt is disabled.

The MstArbLoss interrupt is enabled.

0

1

5

6

-

Reserved. Read value is undefined, only zero

should be written.

NA

0

MSTSTSTPERREN

Master Start/Stop Error interrupt Enable.

The MstStStpErr interrupt is disabled.

The MstStStpErr interrupt is enabled.

0

1

7

8

-

Reserved. Read value is undefined, only zero

should be written.

NA

0

SLVPENDINGEN

Slave Pending interrupt Enable.

0

1

The SlvPending interrupt is disabled.

The SlvPending interrupt is enabled.

10:9

11

-

Reserved. Read value is undefined, only zero

should be written.

NA

0

SLVNOTSTREN

Slave Not Stretching interrupt Enable.

The SlvNotStr interrupt is disabled.

The SlvNotStr interrupt is enabled.

0

1

14:12 -

Reserved. Read value is undefined, only zero

should be written.

NA

0

15

16

17

18

SLVDESELEN

Slave Deselect interrupt Enable.

The SlvDeSel interrupt is disabled.

The SlvDeSel interrupt is enabled.

Monitor data Ready interrupt Enable.

The MonRdy interrupt is disabled.

The MonRdy interrupt is enabled.

Monitor Overrun interrupt Enable.

The MonOv interrupt is disabled.

The MonOv interrupt is enabled.

0

1

MONRDYEN

MONOVEN

-

0

1

0

1

Reserved. Read value is undefined, only zero

should be written.

NA

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Table 174. Interrupt Enable Set and read register (INTENSET, address 0x4005 0008) bit

description

Bit

Symbol

Value Description

Reset

value

19

MONIDLEEN

Monitor Idle interrupt Enable.

0

1

The MonIdle interrupt is disabled.

The MonIdle interrupt is enabled.

23:20 -

Reserved. Read value is undefined, only zero

should be written.

NA

0

24

EVENTTIMEOUTEN

Event time-out interrupt Enable.

0

1

The Event time-out interrupt is disabled.

The Event time-out interrupt is enabled.

SCL time-out interrupt Enable.

25

SCLTIMEOUTEN

0

1

The SCL time-out interrupt is disabled.

The SCL time-out interrupt is enabled.

31:26 -

Reserved. Read value is undefined, only zero

should be written.

NA

16.6.4 Interrupt Enable Clear register

Writing a 1 to a bit position in INTENCLR clears the corresponding position in the

INTENSET register, disabling that interrupt. INTENCLR is a write-only register.

Bits that do not correspond to defined bits in INTENSET are reserved and only zeroes

should be written to them.

Table 175. Interrupt Enable Clear register (INTENCLR, address 0x4005 000C) bit

description

Bit

Symbol

Description

Reset

value

0

MSTPENDINGCLR

Master Pending interrupt clear. Writing 1 to this bit clears

the corresponding bit in the INTENSET register if

implemented.

0

3:1

-

Reserved. Read value is undefined, only zero should be NA

written.

4

5

MSTARBLOSSCLR

-

Master Arbitration Loss interrupt clear.

0

Reserved. Read value is undefined, only zero should be NA

written.

6

7

MSTSTSTPERRCLR Master Start/Stop Error interrupt clear.

0

-

Reserved. Read value is undefined, only zero should be NA

written.

8

SLVPENDINGCLR

-

Slave Pending interrupt clear.

0

10:9

Reserved. Read value is undefined, only zero should be NA

written.

11

SLVNOTSTRCLR

Slave Not Stretching interrupt clear.

0

14:12 -

Reserved. Read value is undefined, only zero should be NA

written.

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Table 175. Interrupt Enable Clear register (INTENCLR, address 0x4005 000C) bit

description …continued

Bit

Symbol

Description

Reset

value

15

16

17

18

SLVDESELCLR

MONRDYCLR

MONOVCLR

-

Slave Deselect interrupt clear.

Monitor data Ready interrupt clear.

Monitor Overrun interrupt clear.

0

Reserved. Read value is undefined, only zero should be NA

written.

19

MONIDLECLR

Monitor Idle interrupt clear.

0

23:20 -

Reserved. Read value is undefined, only zero should be NA

written.

24

25

EVENTTIMEOUTCLR Event time-out interrupt clear.

SCLTIMEOUTCLR SCL time-out interrupt clear.

0

31:26 -

Reserved. Read value is undefined, only zero should be NA

written.

16.6.5 Time-out value register

The TIMEOUT register allows setting an upper limit to certain I²C bus times, informing by

status flag and/or interrupt when those times are exceeded.

Two time-outs are generated, software can elect to use either of them. EVENTTIMEOUT

checks the time between bus events while the bus is not idle: Start, SCL rising, SCL

falling, and Stop. The EVENTTIMEOUT status flag in the STAT register is set if the time

between any two events becomes longer than the time configured in the TIMEOUT

register. The EVENTTIMEOUT status flag can cause an interrupt if enabled to do so by

the EVENTTIMEOUTEN bit in the INTENSET register.

SCLTIMEOUT checks only the time that the SCL signal remains low, while the bus is not

idle. The SCLTIMEOUT status flag in the STAT register is set if SCL remains low longer

than the time configured in the TIMEOUT register. The SCLTIMEOUT status flag can

cause an interrupt if enabled to do so by the SCLTIMEOUTEN bit in the INTENSET

register.

Also see Section 16.7.2 “Time-out”.

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Table 176. time-out register (TIMEOUT, address 0x4005 0010) bit description

Bit

Symbol Description

Reset

value

3:0

TOMIN

Time-out time value, bottom four bits. These are hard-wired to 0xF.

This gives a minimum time-out of 16 I²C function clocks and also a

time-out resolution of 16 I²C function clocks.

0xF

15:4 TO

Time-out time value. Specifies the time-out interval value in increments 0xFFF

of 16 I²C function clocks, as defined by the CLKDIV register. To change

this value while I²C is in operation, disable all time-outs, write a new

value to TIMEOUT, then re-enable time-outs.

0x000 = A time-out will occur after 16 counts of the I²C function clock.

0x001 = A time-out will occur after 32 counts of the I²C function clock.

...

0xFFF = A time-out will occur after 65,536 counts of the I²C function

clock.

31:16 -

Reserved. Read value is undefined, only zero should be written.

NA

16.6.6 I2C Clock Divider register

The CLKDIV register divides down the Peripheral Clock (PCLK) to produce the I²C

function clock that is used to time various aspects of the I²C interface. The I²C function

clock is used for some internal operations in the I²C block and to generate the timing

required by the I²C bus specification, some of which are user configured in the MSTTIME

register for Master operation and the SLVTIME register for Slave operation.

See Section 16.7.1.1 “Rate calculations” for details on bus rate setup.

Table 177. I²C Clock Divider register (DIV, address 0x4005 0014) bit description

Bit

Symbol Description

Reset

value

15:0 DIVVAL This field controls how the clock (PCLK) is used by the I²C functions

that need an internal clock in order to operate.

0

0x0000 = PCLK is used directly by the I²C function.

0x0001 = PCLK is divided by 2 before use by the I²C function.

0x0002 = PCLK is divided by 3 before use by the I²C function.

...

0xFFFF = PCLK is divided by 65,536 before use by the I²C function.

31:16 -

Reserved. Read value is undefined, only zero should be written.

NA

16.6.7 I2C Interrupt Status register

The INTSTAT register provides register provides a view of those interrupt flags that are

currently enabled. This can simplify software handling of interrupts. See Table 171 for

detailed descriptions of the interrupt flags.

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Table 178. I²C Interrupt Status register (INTSTAT, address 0x4005 0018) bit description

Bit

Symbol

Description

Reset

value

0

MSTPENDING

Master Pending.

1

3:1

4

-

Reserved.

MSTARBLOSS

-

Master Arbitration Loss flag.

0

5

Reserved. Read value is undefined, only zero should be

written.

NA

6

7

MSTSTSTPERR

-

Master Start/Stop Error flag.

0

Reserved. Read value is undefined, only zero should be

written.

NA

8

SLVPENDING

-

Slave Pending.

0

10:9

Reserved. Read value is undefined, only zero should be

written.

NA

11

SLVNOTSTR

Slave Not Stretching status.

1

14:12 -

Reserved. Read value is undefined, only zero should be

written.

NA

15

16

17

18

SLVDESEL

Slave Deselected flag.

Monitor Ready.

0

MONRDY

MONOV

-

0

Monitor Overflow flag.

0

Reserved. Read value is undefined, only zero should be

written.

NA

19

MONIDLE

Monitor Idle flag.

0

23:20 -

Reserved. Read value is undefined, only zero should be

written.

NA

24

25

EVENTTIMEOUT Event time-out Interrupt flag.

0

SCLTIMEOUT

SCL time-out Interrupt flag.

0

31:26 -

Reserved. Read value is undefined, only zero should be

written.

NA

16.6.8 Master Control register

The MSTCTL register contains bits that control various functions of the I²C Master

interface.

Table 179. Master Control register (MSTCTL, address 0x4005 0020) bit description

Bit Symbol

Value Description

Reset

value

0

1

MSTCONTINUE

Master Continue. This bit is write-only.

No effect.

0

1

Continue. Informs the Master function to continue to the

next operation. This must done after writing transmit data,

reading received data, or any other housekeeping related

to the next bus operation.

MSTSTART

Master Start control. This bit is write-only.

0

1

No effect.

Start. A Start will be generated on the I²C bus at the next

allowed time.

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Table 179. Master Control register (MSTCTL, address 0x4005 0020) bit description

Bit Symbol Value Description

Reset

value

2

MSTSTOP

Master Stop control. This bit is write-only.

No effect.

Stop. A Stop will be generated on the I²C bus at the next

allowed time, preceded by a Nack to the slave if the

master is receiving data from the slave (Master Receiver

mode).

0

1

31: -

2

Reserved. Read value is undefined, only zero should be NA

written.

16.6.9 Master Time

The MSTTIME register allows programming of certain times that may be controlled by the

Master function. These include the clock (SCL) high and low times, repeated Start setup

time, and transmitted data setup time.

The I2C clock pre-divider is described in Table 177.

Table 180. Master Time register (MSTTIME, address 0x4005 0024) bit description

Bit

Symbol

Value Description

Reset

value

2:0

MSTSCLLOW

Master SCL Low time. Specifies the minimum low time

0

that will be asserted by this master on SCL. Other devices

on the bus (masters or slaves) could lengthen this time.

This corresponds to the parameter t_LOWin the I²C bus

specification. I²C bus specification parameters t_BUFand

t_SU;STAhave the same values and are also controlled by

MSTSCLLOW.

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

2 clocks. Minimum SCL low time is 2 clocks of the I²C

clock pre-divider.

3 clocks. Minimum SCL low time is 3 clocks of the I²C

clock pre-divider.

4 clocks. Minimum SCL low time is 4 clocks of the I²C

clock pre-divider.

5 clocks. Minimum SCL low time is 5 clocks of the I²C

clock pre-divider.

6 clocks. Minimum SCL low time is 6 clocks of the I²C

clock pre-divider.

7 clocks. Minimum SCL low time is 7 clocks of the I²C

clock pre-divider.

8 clocks. Minimum SCL low time is 8 clocks of the I²C

clock pre-divider.

9 clocks. Minimum SCL low time is 9 clocks of the I²C

clock pre-divider.

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Table 180. Master Time register (MSTTIME, address 0x4005 0024) bit description …continued

Bit

Symbol

Value Description

Reset

value

6:4

MSTSCLHIGH

Master SCL High time. Specifies the minimum high time

0

that will be asserted by this master on SCL. Other

masters in a multi-master system could shorten this time.

This corresponds to the parameter t_HIGHin the I²C bus

specification. I²C bus specification parameters t_SU;STO

and t_HD;STAhave the same values and are also controlled

by MSTSCLHIGH.

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

2 clocks. Minimum SCL high time is 2 clock of the I²C

clock pre-divider.

3 clocks. Minimum SCL high time is 3 clocks of the I²C

clock pre-divider .

4 clocks. Minimum SCL high time is 4 clock of the I²C

clock pre-divider.

5 clocks. Minimum SCL high time is 5 clock of the I²C

clock pre-divider.

6 clocks. Minimum SCL high time is 6 clock of the I²C

clock pre-divider.

7 clocks. Minimum SCL high time is 7 clock of the I²C

clock pre-divider.

8 clocks. Minimum SCL high time is 8 clock of the I²C

clock pre-divider.

9 clocks. Minimum SCL high time is 9 clocks of the I²C

clock pre-divider.

31:7

-

Reserved. Read value is undefined, only zero should be NA

written.

16.6.10 Master Data register

The MSTDAT register provides the means to read the most recently received data for the

Master function, and to transmit data using the Master function.

Table 181. Master Data register (MSTDAT, address 0x4005 0028) bit description

Bit

Symbol

Description

Reset

value

7:0

DATA

Master function data register.

0

Read: read the most recently received data for the Master function.

Write: transmit data using the Master function.

Reserved. Read value is undefined, only zero should be written.

31:8

-

NA

16.6.11 Slave Control register

The SLVCTL register contains bits that control various functions of the I²C Slave interface.

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Table 182. Slave Control register (SLVCTL, address 0x4005 0040) bit description

Bit

Symbol

Value Description

Reset

Value

0

SlvContinue

Slave Continue.

0

1

No effect.

Continue. Informs the Slave function to continue to the next

operation. This must done after writing transmit data, reading

received data, or any other housekeeping related to the next

bus operation.

1

SlvNack

Slave Nack.

No effect.

0

1

Nack. Causes the Slave function to Nack the master when

the slave is receiving data from the master (Slave Receiver

mode).

31:2

-

Reserved. Read value is undefined, only zero should be

written.

NA

16.6.12 Slave Data register

The SLVDAT register provides the means to read the most recently received data for the

Slave function and to transmit data using the Slave function.

Table 183. Slave Data register (SLVDAT, address 0x4005 0044) bit description

Bit

Symbol

Description

Reset

Value

7:0

DATA

Slave function data register.

0

Read: read the most recently received data for the Slave function.

Write: transmit data using the Slave function.

Reserved. Read value is undefined, only zero should be written.

31:8

-

NA

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16.6.13 Slave Address registers

The SLVADR[0:3] registers allow enabling and defining one of the addresses that can be

automatically recognized by the I²C slave hardware. The value in the SLVADR0 register is

qualified by the setting of the SLVQUAL0 register.

When the slave address is compared to the receive address, the compare can be affected by the

setting of the SLVQUAL0 register (see Section 16.6.14).

The I²C slave function has 4 address comparators. The additional 3 address comparators

do not include the address qualifier feature. For handling of the general call address, one

of the 4 address registers can be programmed to respond to address 0.

Table 184. Slave Address registers (SLVADR[0:3]- address 0x4005 0048 (SLVADR0) to

0x4005 0054 (SLVADR3)) bit description

Bit

Symbol

Value Description

Reset

value

0

SADISABLE

Slave Address n Disable.

1

0

1

Enabled. Slave Address n is enabled and will be

recognized with any changes specified by the SLVQUAL0

register.

Ignored Slave Address n is ignored.

7:1

SLVADR

-

Seven bit slave address that is compared to received

addresses if enabled.

0

31:8

Reserved. Read value is undefined, only zero should be

written.

NA

16.6.14 Slave address Qualifier 0 register

The SLVQUAL0 register can alter how Slave Address 0 is interpreted.

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Table 185. Slave address Qualifier 0 register (SLVQUAL0, address 0x4005 0058) bit

description

Bit

Symbol

Value Description

Reset

Value

0

QUALMODE0

Reserved. Read value is undefined, only zero should be

0

written.

0

1

The SLVQUAL0 field is used as a logical mask for

matching address 0.

The SLVQUAL0 field is used to extend address 0

matching in a range of addresses.

7:1

SLVQUAL0

Slave address Qualifier for address 0. A value of 0 causes

the address in SLVADR0 to be used as-is, assuming that

it is enabled.

0

If QUALMODE0 = 0, any bit in this field which is set to 1

will cause an automatic match of the corresponding bit of

the received address when it is compared to the

SLVADR0 register.

If QUALMODE0 = 1, an address range is matched for

address 0. This range extends from the value defined by

SLVADR0 to the address defined by SLVQUAL0 (address

matches when SLVADR0[7:1] <= received address <=

SLVQUAL0[7:1]).

31:8

-

Reserved. Read value is undefined, only zero should be NA

written.

16.6.15 Monitor data register

The read-only MONRXDAT register provides information about events on the I²C bus,

primarily to facilitate debugging of the I²C during application development. All data

addresses and data passing on the bus and whether these were acknowledged, as well

as Start and Stop events, are reported.

The Monitor function must be enabled by the MONEN bit in the CFG register. Monitor

mode can be configured to stretch the I²C clock if data is not read from the MONRXDAT

register in time to prevent it, via the MONCLKSTR bit in the CFG register. This can help

ensure that nothing is missed but can cause the monitor function to be somewhat intrusive

(by potentially adding clock delays, depending on software response time). In order to

improve the chance of collecting all Monitor information if clock stretching is not enabled,

Monitor data is buffered such that it is available until the end of the next piece of

information from the I²C bus.

Table 186. Monitor data register (MONRXDAT, address 0x4005 0080) bit description

Bit

Symbol

Value Description

Reset

value

7:0

MONRXDAT

Monitor function Receiver Data. This reflects every data

byte that passes on the I²C pins, and adds indication of

Start, Repeated Start, and data Nack.

0

8

MONSTART

Monitor Received Start.

0

1

No detect. The monitor function has not detected a Start

event on the I²C bus.

Start detect. The monitor function has detected a Start

event on the I²C bus.

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Table 186. Monitor data register (MONRXDAT, address 0x4005 0080) bit description

Bit

Symbol

Value Description

Reset

value

9

MONRESTART

Monitor Received Repeated Start.

0

1

No start detect. The monitor function has not detected a

Repeated Start event on the I²C bus.

Repeated start detect. The monitor function has

detected a Repeated Start event on the I²C bus.

10

MONNACK

Monitor Received Nack.

0

1

Acknowledged. The data currently being provided by the

monitor function was acknowledged by at least one

master or slave receiver.

Not acknowledged. The data currently being provided by

the monitor function was not acknowledged by any

receiver.

31:11 -

Reserved. Read value is undefined, only zero should be NA

written.

16.7 Functional description

16.7.1 Bus rates and timing considerations

Due to the nature of the I²C bus, it is generally not possible to guarantee a specific clock

rate on the SCL pin. The clock can be stretched by any slave device, extended by

software overhead time, etc. In a multi-master system, the master that provides the

shortest SCL high time will cause that time to appear on SCL as long as that master is

participating in I2C traffic (i.e. when it is the only master on the bus, or during arbitration

between masters).

Rate calculations give a base frequency that represents the fastest that the I²C bus could

operate if nothing slows it down.

16.7.1.1 Rate calculations

SCL high time (in I²C function clocks) = (CLKDIV + 1) * (MSTSCLHIGH + 2)

SCL low time (in I²C function clocks) = (CLKDIV + 1) * (MSTSCLLOW + 2)

Nominal SCL rate = I²C function clock rate / (SCL high time + SCL low time)

16.7.2 Time-out

A time-out feature on an I²C interface can be used to detect a “stuck” bus and potentially

do something to alleviate the condition. Two different types of time-out are supported.

Both types apply whenever the I²C block and the time-out function are both enabled,

Master, Slave, or Monitor functions do not need to be enabled.

In the first type of time-out, reflected by the EVENTTIMEOUT flag in the STAT register, the

time between bus events governs the time-out check. These events include Start, Stop,

and all changes on the I²C clock (SCL). This time-out is asserted when the time between

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Chapter 16: LPC800 I2C-bus interface

any of these events is longer than the time configured in the TIMEOUT register. This

time-out could be useful in monitoring an I²C bus within a system as part of a method to

keep the bus running of problems occur.

The second type of I²C time-out is reflected by the SCLTIMEOUT flag in the STAT

register. This time-out is asserted when the SCL signal remains low longer than the time

configured in the TIMEOUT register. This corresponds to SMBus time-out parameter

T

_TIMEOUT. In this situation, a slave could reset its own I²C interface in case it is the

offending device. If all listening slaves (including masters that can be addressed as

slaves) do this, then the bus will be released unless it is a current master causing the

problem. Refer to the SMBus specification for more details.

Both types of time-out are generated when the I²C bus is considered busy.

16.7.3 Ten-bit addressing

Ten-bit addressing is accomplished by the I²C master sending a second address byte to

extend a particular range of standard 7-bit addresses. In the case of the master writing to

the slave, the I²C frame simply continues with data after the 2 address bytes. For the

master to read from a slave, it needs to reverse the data direction after the second

address byte. This is done by sending a Repeated Start, followed by a repeat of the same

standard 7-bit address, with a Read bit. The slave must remember that it had been

addressed by the previous write operation and stay selected for the subsequent read with

the correct partial I²C address.

For the Master function, the I2C is simply instructed to perform the 2-byte addressing as a

normal write operation, followed either by more write data, or by a Repeated Start with a

repeat of the first part of the 10-bit slave address and then reading in the normal fashion.

For the Slave function, the first part of the address is automatically matched in the same

fashion as 7-bit addressing. The Slave address qualifier feature (see Section 16.6.14) can

be used to intercept all potential 10-bit addresses (first address byte values F0 through

F6), or just one. In the case of Slave Receiver mode, data is received in the normal

fashion after software matches the first data byte to the remaining portion of the 10-bit

address. The Slave function should record the fact that it has been addressed, in case

there is a follow-up read operation.

For Slave Transmitter mode, the slave function responds to the initial address in the same

fashion as for Slave Receiver mode, and checks that it has previously been addressed

with a full 10-bit address. If the address matched is address 0, and address qualification is

enabled, software must check that the first part of the 10-bit address is a complete match

to the previous address before acknowledging the address.

16.7.4 Clocking and power considerations

The Master function of the I²C always requires a peripheral clock to be running in order to

operate. The Slave function can operate without any internal clocking when the slave is

not currently addressed. This means that reduced power modes up to Power-down mode

can be entered, and the device will wake up when the I²C Slave function recognizes an

address. Monitor mode can similarly wake up the device from a reduced power mode

when information becomes available.

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16.7.5 lnterrupts

The I2C provides a single interrupt output that handles all interrupts for Master, Slave, and

Monitor functions.

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Chapter 17: LPC800 SPI0/1

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17.1 How to read this chapter

SPI0 is available on all parts. SPI1 is available on parts LPC812M101FDH16 and

LPC812M101FDH20 only.

17.2 Features

• Data frames of 1 to 16 bits supported directly. Larger frames supported by software.

• Master and slave operation.

• Data can be transmitted to a slave without the need to read incoming data. This can

be useful while setting up an SPI memory, for instance.

• Control information can optionally be written along with data. This allows very

versatile operation, including “any length” frames.

• One Slave Select input/output with selectable polarity and flexible usage.

Remark: Texas Instruments SSI and National Microwire modes are not supported.

17.3 Basic configuration

Configure SPI0/1 using the following registers:

• In the SYSAHBCLKCTRL register, set bit 11 and 12 (Table 18) to enable the clock to

the register interface.

• Clear the SPI0/1 peripheral resets using the PRESETCTRL register (Table 7).

• Enable/disable the SPI0/1 interrupts in interrupt slots #0 and 1 in the NVIC.

• Configure the SPI0/1 pin functions through the switch matrix. See Section 17.4.

• The peripheral clock for both SPIs is the system clock (see Figure 3 “LPC800 clock

generation”).

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Fig 26. SPI clocking

17.3.1 Configure the SPIs for wake-up

The SPI can wake up the system from sleep mode in master or slave mode.

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If the SPI is configured for slave mode, the SPI block can create an interrupt on a received

signal even when the SPI receives no clocks from the ARM Cortex-M0+ core, which is the

case when the system is in deep-sleep or power-down mode.

17.3.1.1 Wake-up from Sleep mode

• Configure the SPI in either master or slave mode. See Table 189.

• Enable the SPI interrupt in the NVIC.

• Any SPI interrupt wakes up the part from sleep mode. Enable the SPI interrupt in the

INTENSET register (Table 192).

17.3.1.2 Wake-up from Deep-sleep or Power-down mode

• Configure the SPI in slave mode. See Table 189. You must connect the SCK function

to a pin and connect the pin to the master.

• Enable the SPI interrupt in the STARTERP1 register. See Table 34 “Start logic 1

interrupt wake-up enable register (STARTERP1, address 0x4004 8214) bit

description”.

• Enable the SPI interrupt in the NVIC.

• The SPI wakes up the part from Deep-sleep or Power-down mode on the following

events that cause an interrupt:

– A change in the state of the SSEL pin.

– <tbd>.

Remark: Enable the interrupt for each wake-up event in the INTENSET register

(Table 192).

17.4 Pin description

The SPI signals are movable functions and are assigned to external pins through the

switch matrix.

See Section 9.3.1 “Connect an internal signal to a package pin” to assign the SPI

functions to pins on the LPC800 package.

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Table 187: SPI Pin Description

Function

Direct Pin Description

SWM register

Reference

ion

SPI0_SCK

I/O

any Serial Clock. SCK is a clock signal used to synchronize the PINASSIGN3

transfer of data. It is driven by the master and received by the

slave. When the SPI interface is used, the clock is

programmable to be active-high or active-low. SCK only

switches during a data transfer. It is driven whenever the

Master bit in CFG equals 1, regardless of the state of the

Enable bit.

Table 99

SPI0_MOSI

SPI0_MISO

SPI0_SSEL

I/O

any Master Out Slave In. The MOSI signal transfers serial data PINASSIGN4

from the master to the slave. When the SPI is a master, it

outputs serial data on this signal. When the SPI is a slave, it

clocks in serial data from this signal. MOSI is driven

whenever the Master bit in SPInCfg equals 1, regardless of

the state of the Enable bit.

Table 100

any Master In Slave Out. The MISO signal transfers serial data PINASSIGN4

from the slave to the master. When the SPI is a master, serial

data is input from this signal. When the SPI is a slave, serial

data is output to this signal. MISO is driven when the SPI

block is enabled, the Master bit in CFG equals 0, and when

the slave is selected by one or more SSEL signals.

any Slave Select . When the SPI interface is a master, it will drive PINASSIGN4

the SSEL signals to an active state before the start of serial

data and then release them to an inactive state after the serial

data has been sent. By default, this signal is active low but

can be selected to operate as active high. When the SPI is a

slave, any SSEL in an active state indicates that this slave is

being addressed. The SSEL pin is driven whenever the

Master bit in the CFG register equals 1, regardless of the

state of the Enable bit.

SPI1_SCK

SPI1_MOSI

SPI1_MISO

SPI1_SSEL

I/O

any Serial Clock.

PINASSIGN4

PINASSIGN5

Table 100

Table 101

any Master Out Slave In.

any Master In Slave Out.

any Slave Select.

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17.5 General description

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(1) Includes CPOL, CPHA, LSBF, FLEN, master, enable, transfer_delay, frame_delay, pre_delay, post_delay, SOT, EOT, EOF,

RXIgnore, individual interrupt enables.

Fig 27. SPI block diagram

17.6 Register description

The Reset Value reflects the data stored in used bits only. It does not include reserved bits

content.

Table 188. Register overview: SPI (base address 0x4005 8000 (SPI0) and 0x4008 C000

(SPI1))

Name

Access

Offset

Description

Reset

value

Reference

CFG

DLY

R/W

0x000

0x004

0x008

SPI Configuration register

SPI Delay register

0

Table 189

Table 190

STAT

SPI Status. Some status flags can be 0x0102 Table 191

cleared by writing a 1 to that bit

position

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Table 188. Register overview: SPI (base address 0x4005 8000 (SPI0) and 0x4008 C000 (SPI1))

…continued

Name

Access

Offset

Description

Reset

value

Reference

INTENSET R/W

0x00C

SPI Interrupt Enable read and Set. A

complete value may be read from this

register. Writing a 1 to any

0

Table 192

implemented bit position causes that

bit to be set.

INTENCLR

RXDAT

W

R

0x010

SPI Interrupt Enable Clear. Writing a 1 NA

to any implemented bit position causes

the corresponding bit in INTENSET to

be cleared.

Table 193

0x014

0x018

0x01C

0x020

0x024

0x028

SPI Receive Data

NA

0

Table 194

Table 195

Table 196

Table 197

Table 198

Table 199

TXDATCTL R/W

SPI Transmit Data with Control

SPI Transmit Data

TXDAT

TXCTL

DIV

R/W

R

0

SPI Transmit Control

SPI clock Divider

0

INTSTAT

SPI Interrupt Status

0x02

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17.6.1 SPI Configuration register

The CFG register contains information for the general configuration of the SPI. Typically,

this information is not changed during operation. Some configurations, such as CPOL,

CPHA, and LSBF should not be made while the SPI is not fully idle. See the description of

the Idle status (in Table 191) for more information.

Remark: If the interface is re-configured from Master mode to Slave mode or the reverse

(an unusual case), the SPI should be disabled and re-enabled with the new configuration.

Table 189. SPI Configuration register (CFG, addresses 0x4005 8000 (SPI0) , 0x4005 C000 (SPI1)) bit

description

Bit

Symbol

Value Description

Reset

value

0

Enable

SPI enable.

0

1

Disabled. The SPI is disabled and the internal state machine and counters are reset.

Enabled. The SPI is enabled for operation.

Reserved. Read value is undefined, only zero should be written.

Master mode select.

1

2

-

NA

0

Master

0

1

Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are

inputs, MISO is an output.

Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals

are outputs, MISO is an input.

3

4

LSBF

LSB First mode enable.

0

1

Standard. Data is transmitted and received in standard MSB first order.

Reverse. Data is transmitted and received in reverse order (LSB first).

Clock Phase select.

CPHA

0

1

Change. The SPI captures serial data on the first clock transition of the frame (when the

clock changes away from the rest state). Data is changed on the following edge.

Capture. The SPI changes serial data on the first clock transition of the frame (when the

clock changes away from the rest state). Data is captured on the following edge.

5

CPOL

Clock Polarity select.

0

1

Low. The rest state of the clock (between frames) is low.

High. The rest state of the clock (between frames) is high.

Reserved. Read value is undefined, only zero should be written.

6

7

-

NA

0

LOOP

Loopback mode enable. Loopback mode applies only to Master mode, and connects

transmit and receive data connected together to allow simple software testing.

0

1

Disabled.

Enabled.

8

SPOL

SSEL Polarity select.

0

1

Low. The SSEL pin is active low. The value in the SSEL fields of the RXDAT, TXDATCTL,

and TXCTL registers related to SSEL is not inverted relative to the pins.

High. The SSEL pin is active high. The value in the SSEL fields of the RXDAT,

TXDATCTL, and TXCTL registers related to SSEL is inverted relative to the pins.

31:9

-

Reserved. Read value is undefined, only zero should be written.

NA

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17.6.2 SPI Delay register

The DLY register controls several programmable delays related to SPI signalling. These

delays apply only to master mode, and are all stated in SPI clocks.

Timing details are shown in:

Section 17.7.2.1 “Pre_delay and Post_delay”

Section 17.7.2.2 “Frame_delay”

Section 17.7.2.3 “Transfer_delay”

Table 190. SPI Delay register (DLY, addresses 0x4005 8004 (SPI0) , 0x4005 C004 (SPI1)) bit description

Bit

Symbol

Description

Reset

value

3:0

PRE_DELAY

Controls the amount of time between SSEL assertion and the beginning of a data

frame.

0

There is always one SPI clock time between SSEL assertion and the first clock edge.

This is not considered part of the pre-delay.

0x0 = No additional time is inserted.

0x1 = 1 SPI clock time is inserted.

0x2 = 2 SPI clock times are inserted.

...

0xF = 15 SPI clock times are inserted.

Controls the amount of time between the end of a data frame and SSEL deassertion.

0x0 = No additional time is inserted.

0x1 = 1 SPI clock time is inserted.

0x2 = 2 SPI clock times are inserted.

...

7:4

POST_DELAY

0

0xF = 15 SPI clock times are inserted.

Controls the minimum amount of time between adjacent data frames.

0x0 = No additional time is inserted.

0x1 = 1 SPI clock time is inserted.

0x2 = 2 SPI clock times are inserted.

...

11:8 FRAME_DELAY

0xF = 15 SPI clock times are inserted.

15:12 TRANSFER_DELAY Controls the minimum amount of time that the SSEL is deasserted between transfers.

0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added

time.)

0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times.

0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times.

...

0xF = The minimum time that SSEL is deasserted is 16 SPI clock times.

31:16 -

Reserved. Read value is undefined, only zero should be written.

NA

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17.6.3 SPI Status register

The STAT register provides SPI status flags for software to read, and a control bit for

forcing an end of transfer. Flags other than read-only flags may be cleared by writing ones

to corresponding bits of STAT.

STAT contains 2 error flags. RXOV and TXUR. These are receiver overrun and transmit

underrun, respectively. If either of these errors occur during operation, the SPI should be

disabled, then re-enabled in order to make sure all internal states are cleared before

attempting to resume operation.

In this register, the following notation is used: RO = Read-only, W1 = write 1 to clear..

Table 191. SPI Status register (STAT, addresses 0x4005 8008 (SPI0) , 0x4005 C008 (SPI1)) bit description

Bit

Symbol

RXRDY

TXRDY

Description

Reset Access

value

[1]

0

Receiver Ready flag. When 1, indicates that data is available to be read from

the receiver buffer. Cleared after a read of the RXDAT register.

0

RO

1

Transmitter Ready flag. When 1, this bit indicates that data may be written to

the transmit buffer. Previous data may still be in the process of being

transmitted. Cleared when data is written to TXDAT or TXDATCTL until the data

is moved to the transmit shift register.

1

2

3

RXOV

TXUR

Receiver Overrun interrupt flag. This flag is set when the beginning of a

received character is detected while the receiver buffer is still in use. If this

occurs, the receiver buffer contents are preserved, and the incoming data is

lost. Data received by the SPI should be considered undefined if RxOv is set.

0

W1

Transmitter Underrun interrupt flag. This flag applies only to slave mode

(Master = 0). In this case, the transmitter must begin sending new data on the

next input clock if the transmitter is idle. If that data is not available in the

transmitter holding register at that point, there is no data to transmit and the

TxUr flag is set. Data transmitted by the SPI should be considered undefined if

TxUr is set.

4

5

SSA

Slave Select Assert. This flag is set whenever any slave select transitions from

deasserted to asserted, in both master and slave modes. This allows

determining when the SPI transmit/receive functions become busy, and allows

waking up the device from reduced power modes when a slave mode access

begins. This flag is cleared by software.

0

W1

SSD

Slave Select Deassert. This flag is set whenever any asserted slave selects

transition to deasserted, in both master and slave modes. This allows

determining when the SPI transmit/receive functions become idle. This flag is

cleared by software.

6

7

STALLED

Stalled status flag. This indicates whether the SPI is currently in a stall

condition.

0

RO

ENDTRANSFER End Transfer control bit. Software can set this bit to force an end to the current

transfer when the transmitter finishes any activity already in progress, as if the

EOT flag had been set prior to the last transmission. This capability is included

to support cases where it is not known when transmit data is written that it will

be the end of a transfer. The bit is cleared when the transmitter becomes Idle as

the transfer comes to an end. Forcing an end of transfer in this manner causes

any specified FrameDelay and TransferDelay to be inserted.

RO/W1

8

IDLE

Idle status flag. This bit is 1 whenever the SPI master function is fully idle. This

means that the transmit holding register is empty and the transmitter is not in

the process of sending data.

1

RO

NA

31:9

-

Reserved. Read value is undefined, only zero should be written.

NA

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[1] RO = Read-only, W1 = write 1 to clear.

17.6.4 SPI Interrupt Enable read and Set register

The INTENSET register is used to enable various SPI interrupt sources. Enable bits in

INTENSET are mapped in locations that correspond to the flags in the STAT register. The

complete set of interrupt enables may be read from this register. Writing ones to

implemented bits in this register causes those bits to be set. The INTENCLR register is

used to clear bits in this register. See Table 191 for details of the interrupts.

Table 192. SPI Interrupt Enable read and Set register (INTENSET, addresses 0x4005 800C (SPI0) , 0x4005 C00C

(SPI1)) bit description

Bit

Symbol

Value Description

Reset

value

0

RXRDYEN

Determines whether an interrupt occurs when receiver data is available.

0

1

No interrupt will be generated when receiver data is available.

An interrupt will be generated when receiver data is available in the RXDAT register.

1

2

TXRDYEN

RXOVEN

Determines whether an interrupt occurs when the transmitter holding register is

available.

0

1

No interrupt will be generated when the transmitter holding register is available.

An interrupt will be generated when data may be written to TXDAT.

Determines whether an interrupt occurs when a receiver overrun occurs. This happens

in slave mode when there is a need for the receiver to move newly received data to the

RXDAT register when it is already in use.

0

The interface prevents receiver overrun in Master mode by not allowing a new

transmission to begin when a receiver overrun would otherwise occur.

0

1

No interrupt will be generated when a receiver overrun occurs.

An interrupt will be generated if a receiver overrun occurs.

3

4

TXUREN

SSAEN

Determines whether an interrupt occurs when a transmitter underrun occurs. This

happens in slave mode when there is a need to transmit data when none is available.

0

1

No interrupt will be generated when the transmitter underruns.

An interrupt will be generated if the transmitter underruns.

Determines whether an interrupt occurs when the Slave Select is asserted.

0

1

No interrupt will be generated when any Slave Select transitions from deasserted to

asserted.

An interrupt will be generated when any Slave Select transitions from deasserted to

asserted.

5

SSDEN

-

Determines whether an interrupt occurs when the Slave Select is deasserted.

No interrupt will be generated when all asserted Slave Selects transition to deasserted.

An interrupt will be generated when all asserted Slave Selects transition to deasserted.

Reserved. Read value is undefined, only zero should be written.

0

1

31:6

NA

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17.6.5 SPI Interrupt Enable Clear register

The INTENCLR register is used to clear interrupt enable bits in the INTENSET register.

Table 193. SPI Interrupt Enable clear register (INTENCLR, addresses 0x4005 8010 (SPI0) ,

0x4005 C010 (SPI1)) bit description

Bit

Symbol

Description

Reset

value

0

RXRDYEN Writing 1 clears the corresponding bits in the INTENSET register.

TXRDYEN Writing 1 clears the corresponding bits in the INTENSET register.

0

1

0

2

RXOVEN

TXUREN

SSAEN

SSDEN

-

Writing 1 clears the corresponding bits in the INTENSET register.

Reserved. Read value is undefined, only zero should be written.

0

3

0

4

0

5

0

31:6

NA

17.6.6 SPI Receiver Data register

The read-only RXDAT register provides the means to read the most recently received

data. The value of SSEL can be read along with the data.

For details on the slave select process, see Section 17.7.4.

Table 194. SPI Receiver Data register (RXDAT, addresses 0x4005 8014 (SPI0) , 0x4005 C014

(SPI1)) bit description

Bit

Symbol

Description

Reset

value

15:0 RXDAT

Receiver Data. This contains the next piece of received data.

The number of bits that are used depends on the FLen setting in

TXCTL / TXDATCTL.

undefined

16

RXSSELN

Slave Select for receive. This field allows the state of the SSEL undefined

pin to be saved along with received data. The value will reflect

the SSEL pin for both master and slave operation. A zero

indicates that a slave select is active. The actual polarity of each

slave select pin is configured by the related SPOL bit in CFG.

19:17 -

Reserved.

-

20

SOT

Start of Transfer flag. This flag will be 1 if this is the first frame

after SSEL went from deasserted to asserted (i.e., any

previous transfer has ended). This information can be used to

identify the first piece of data in cases where the frame length is

greater than 16 bit.

31:21 -

Reserved, the value read from a reserved bit is not defined.

NA

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17.6.7 SPI Transmitter Data and Control register

The TXDATCTL register provides a location where both transmit data and control

information can be written simultaneously. This allows detailed control of the SPI without a

separate write of control information for each piece of data.

When control information remains static during transmit, the TXDAT register should be

used (see Section 17.6.8) instead of the TXDATCTL register. Control information can then

be written separately via the TXCTL register (see Section 17.6.9). The upper part of

TXDATCTL (bits 27 to 16) are the same bits contained in the TXCTL register. The two

registers simply provide two ways to access them.

For details on the slave select process, see Section 17.7.4.

For details on using multiple consecutive frames for frame lengths larger than 16 bit, see

Section 17.7.5 “Data lengths greater than 16 bits”.

Table 195. SPI Transmitter Data and Control register (TXDATCTL, addresses 0x4005 8018 (SPI0) , 0x4005 C018

(SPI1)) bit description

Bit

Symbol

Value Description

Reset

value

15:0 TXDAT

Transmit Data. This field provides from 1 to 16 bits of data to be transmitted.

0

16

TXSSELN

Transmit Slave Select . This field controls what is output for SSEL in master mode.

Remark: The active state of the SSEL function is configured by bits in the CFG

register.

0

1

SSEL asserted.

SSEL not asserted.

Reserved.

19:17 -

20

21

22

EOT

End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and

remain so for at least the time specified by the Transfer_delay value in the DLY

register.

0

1

SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL

will not be deasserted at the end of this data.

SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be

deasserted at the end of this piece of data.

EOF

End of Frame. Between frames, a delay may be inserted, as defined by the

Frame_delay value in the DLY register. The end of a frame may not be particularly

meaningful if the FRAME_DELAY value = 0. This control can be used as part of the

support for frame lengths greater than 16 bits.

0

1

Data not EOF. This piece of data transmitted is not treated as the end of a frame.

Data EOF. This piece of data is treated as the end of a frame, causing the

FRAME_DELAY time to be inserted before subsequent data is transmitted.

RXIGNORE

Receive Ignore. This allows data to be transmitted using the SPI without the need to

read unneeded data from the receiver to simplify the transmit process.

0

1

Read received data. Received data must be read in order to allow transmission to

progress. In slave mode, an overrun error will occur if received data is not read before

new data is received.

Ignore received data. Received data is ignored, allowing transmission without reading

unneeded received data. No receiver flags are generated.

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Table 195. SPI Transmitter Data and Control register (TXDATCTL, addresses 0x4005 8018 (SPI0) , 0x4005 C018

(SPI1)) bit description …continued

Bit

Symbol

Value Description

Reset

value

23

-

Reserved. Read value is undefined, only zero should be written.

NA

27:24 FLEN

Frame Length. Specifies the frame length from 1 to 16 bits. Note that frame lengths

greater than 16 bits are supported by implementing multiple sequential frames.

0x0

Note that if a 1-bit frame is selected, the master function will always insert a delay with

a length of one SCK time following the single clock seen on the SCK pin.

0x0 = Data frame is 1 bit in length.

0x1 = Data frame is 2 bits in length.

0x2 = Data frame is 3 bits in length.

...

0xF = Data frame is 16 bits in length.

Reserved. Read value is undefined, only zero should be written.

31:28 -

NA

17.6.8 SPI Transmitter Data Register

The TXDAT register is written in order to send data via the SPI transmitter when control

information is not changing during the transfer (see Section 17.6.7). That data will be sent

to the transmit shift register when it is available, and another character may then be

written to TXDAT.

Table 196. SPI Transmitter Data Register (TXDAT, addresses 0x4005 801ST (SPI0) , 0x4005

C00C (SPI1)) bit description

Bit

Symbol

Description

Reset

value

15:0 DATA

31:16 -

Transmit Data. This field provides from 4 to 16 bits of data to be

transmitted.

0

Reserved. Only zero should be written.

NA

17.6.9 SPI Transmitter Control register

The TXCTL register provides a way to separately access control information for the SPI.

These bits are another view of the same-named bits in the TXDATCTL register (see

Section 17.6.7). Changing bits in TXCTL has no effect unless data is later written to the

TXDAT register. Data written to TXDATCTL overwrites the TXCTL register.

When control information needs to be changed during transmission, the TXDATCTL

register should be used (see Section 17.6.7) instead of TXDAT. Control information can

then be written along with data.

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Table 197. SPI Transmitter Control register (TXCTL, addresses 0x4005 8020 (SPI0) , 0x4005

C020 (SPI1)) bit description

Bit

Symbol

Description

Reset

value

15:0

16

-

Reserved. Read value is undefined, only zero should be written. NA

TX SSEL

Transmit Slave Select.

Reserved.

0x0

0

19:17 -

20

21

22

23

EOT

EOF

End of Transfer.

End of Frame.

0

RXIGNORE Receive Ignore.

0

-

Reserved. Read value is undefined, only zero should be written. NA

Frame Length. 0x0

Reserved. Read value is undefined, only zero should be written. NA

27:24 FLEN

31:28 -

17.6.10 SPI Divider register

The DIV register determines the clock used by the SPI in master mode.

For details on clocking, see Section 17.7.3 “Clocking and data rates”.

Table 198. SPI Divider register (DIV, addresses 0x4005 8024 (SPI0) , 0x4005 C024(SPI1)) bit

description

Bit

Symbol

Description

Reset

Value

15:0 DIVVAL

Rate divider value,1. Specifies how the PCLK for the SPI is divided

to produce the SPI clock rate in master mode.

0

DIVVAL is -1 encoded such that the value 0 results in PCLK/1, the

value 1 results in PCLK/2, up to the maximum possible divide value

of 0xFFFF, which results in PCLK/65536.

31:16 -

Reserved. Read value is undefined, only zero should be written.

NA

17.6.11 SPI Interrupt Status register

The read-only INTSTAT register provides a view of those interrupt flags that are currently

enabled. This can simplify software handling of interrupts. See Table 191 for detailed

descriptions of the interrupt flags.

Table 199. SPI Interrupt Status register (INTSTAT, addresses 0x4005 8028 (SPI0) , 0x4005

C028 (SPI1)) bit description

Bit

Symbol

Description

Reset

value

0

1

2

3

RXRDY

TXRDY

RXOV

TXUR

Receiver Ready flag.

0

1

0

Transmitter Ready flag.

Receiver Overrun interrupt flag.

Transmitter Underrun interrupt flag.

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Table 199. SPI Interrupt Status register (INTSTAT, addresses 0x4005 8028 (SPI0) , 0x4005

C028 (SPI1)) bit description

Bit

Symbol

Description

Reset

value

4

SSA

SSD

-

Slave Select Assert.

0

5

Slave Select Deassert.

0

31:6

Reserved. Read value is undefined, only zero should be written.

NA

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Chapter 17: LPC800 SPI0/1

17.7 Functional description

17.7.1 Operating modes: clock and phase selection

SPI interfaces typically allow configuration of clock phase and polarity. These are

sometimes referred to as numbered SPI modes, as described in Table 200 and shown in

Figure 28. CPOL and CPHA are configured by bits in the CFG register (Section 17.6.1).

Table 200: SPI mode summary

SPI

Mode

SCKrest

state

SCK data

change edge sample edge

SCK data

CPOL CPHA

Description

The SPI captures serial data on the first clock transition of

the frame (when the clock changes away from the rest

state). Data is changed on the following edge.

0

1

0

1

low

falling

rising

falling

The SPI changes serial data on the first clock transition of

the frame (when the clock changes away from the rest

state). Data is captured on the following edge.

1

0

1

2

3

Same as mode 0 with SCK inverted.

Same as mode 1 with SCK inverted.

high

rising

falling

rising

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Fig 28. Basic SPI operating modes

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Chapter 17: LPC800 SPI0/1

17.7.2 Frame delays

Several delays can be specified for SPI frames. These include:

• Pre_delay: delay after SSEL is asserted before data clocking begins

• Post_delay: delay at the end of a data frame before SSEL is deasserted

• Frame_delay: delay between data frames when SSEL is not deasserted

• Transfer_delay: minimum duration of SSEL in the deasserted state between transfers

17.7.2.1 Pre_delay and Post_delay

Pre_delay and Post_delay are illustrated by the examples in Figure 29. The Pre_delay

value controls the amount of time between SSEL being asserted and the beginning of the

subsequent data frame. The Post_delay value controls the amount of time between the

end of a data frame and the deassertion of SSEL.

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Fig 29. Pre_delay and Post_delay

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Chapter 17: LPC800 SPI0/1

17.7.2.2 Frame_delay

The Frame_delay value controls the amount of time at the end of each frame. This delay

is inserted when the EOF bit = 1. Frame_delay is illustrated by the examples in Figure 30.

Note that frame boundaries occur only where specified. This is because frame lengths

can be any size, involving multiple data writes. See Section 17.7.5 for more information.

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Fig 30. Frame_delay

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Chapter 17: LPC800 SPI0/1

17.7.2.3 Transfer_delay

The Transfer_delay value controls the minimum amount of time that SSEL is deasserted

between transfers, because the EOT bit = 1. When Transfer_delay = 0, SSEL may be

deasserted for a minimum of one SPI clock time. Transfer_delay is illustrated by the

examples in Figure 31.

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Fig 31. Transfer_delay

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Chapter 17: LPC800 SPI0/1

17.7.3 Clocking and data rates

In order to use the SPI, clocking details must be defined. This includes configuring the

system clock and selection of the clock divider value in DIV. See Figure 26.

17.7.3.1 Data rate calculations

The SPI interface is designed to operate asynchronously from any on-chip clocks, and

without the need for overclocking.

In slave mode, this means that the SCK from the external master is used directly to run

the transmit and receive shift registers and other logic. The upper rate limit depends on

the speed of the logic and pin electronics, and signalling quality in the external

connections.

In master mode, the SPI rate clock produced by the SPI clock divider is used directly as

the outgoing SCK. Again, the upper rate limit depends on the speed of the logic and pin

electronics, and signalling quality in the external connections.

The SPI clock divider is an integer divider. The SPI in master mode can be set to run at

the same speed as the selected PCLK, or at lower integer divide rates. The SPI rate will

be = PCLK_SPIn / DIVVAL.

In slave mode, the clock is taken from the SCK input and the SPI clock divider is not used.

17.7.4 Slave select

The SPI block provides for one Slave Select input in slave mode or output in master

mode. The SSEL can be set for normal polarity (active low), or can be inverted (active

high). Representation of the SSEL in a register is always active low. If the SSEL is

inverted, this is done as the signal leaves/enters the SPI block.

In slave mode, the asserted SSEL that is connected to a pin will activate the SPI. In

master mode, the SSEL that is connected to a pin will be output as defined in the SPI

registers.

In master mode, the Slave Select is configured by the TXSSE LN field, which appears in

both the CCD and DETECT registers. In slave mode, the state of the SSEL is saved along

with received data in the RXSSELN field of the RXDAT register.

17.7.5 Data lengths greater than 16 bits

The SPI interface handles data frame sizes from 1 to 16 bits directly. Larger sizes can be

handled by splitting data up into groups of 16 bits or less. For example, 24 bits can be

supported as 2 groups of 16 bits and 8 bits or 2 groups of 12 bits, among others. Frames

of any size, including greater than 32 bits, can supported in the same way.

Details of how to handle larger data widths depend somewhat on other SPI configuration

options. For instance, if it is intended for Slave Selects to be deasserted between frames,

then this must be suppressed when a larger frame is split into more than one part.

Sending 2 groups of 12 bits with SSEL deasserted between 24-bit increments, for

instance, would require changing the value of the EOF bit on alternate 12-bit frames.

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Chapter 17: LPC800 SPI0/1

17.7.6 Data stalls

A stall for Master transmit data can happen in modes 0 and 2 when SCK cannot be

returned to the rest state until the MSB of the next data frame can be driven on MOSI. In

this case, the stall happens just before the final clock edge of data if the next piece of data

is not yet available.

A stall for Master receive can happen when a receiver overrun would otherwise occur if

the transmitter was not stalled. In modes 0 and 2, this occurs if the previously received

data is not read before the end of the next piece of is received. This stall happens one

clock edge earlier than the transmitter stall.

In modes 1 and 3, the same kind of receiver stall can occur, but just before the final clock

edge of the received data. Also, a transmitter stall will not happen in modes 1 and 3

because the transmitted data is complete at the point where a stall would otherwise occur,

so it is not needed.

Stalls are reflected in the STAT register by the Stalled status flag, which indicates the

current SPI status.

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Chapter 17: LPC800 SPI0/1

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Fig 32. Examples of data stalls

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Chapter 18: LPC800 Cyclic Redundancy Check (CRC) engine

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Preliminary user manual

18.1 How to read this chapter

The CRC engine is available on all LPC800 parts.

18.2 Features

• Supports three common polynomials CRC-CCITT, CRC-16, and CRC-32.

– CRC-CCITT: x¹⁶+ x¹²+ x⁵+ 1

– CRC-16: x¹⁶+ x¹⁵+ x²+ 1

– CRC-32: x³²+ x²⁶+ x²³+ x²²+ x¹⁶+ x¹²+ x¹¹+ x¹⁰+ x⁸+ x⁷+ x⁵+ x⁴+ x²+ x + 1

• Bit order reverse and 1’s complement programmable setting for input data and CRC

sum.

• Programmable seed number setting.

• Supports CPU PIO back-to-back transfer.

• Accept any size of data width per write: 8, 16 or 32-bit.

– 8-bit write: 1-cycle operation

– 16-bit write: 2-cycle operation (8-bit x 2-cycle)

– 32-bit write: 4-cycle operation (8-bit x 4-cycle)

18.3 Basic configuration

Enable the clock to the CRC engine in the SYSAHBCLKCTRL register (Table 18, bit 13).

18.4 Pin description

The CRC engine has no configurable pins.

18.5 General description

The Cyclic Redundancy Check (CRC) generator with programmable polynomial settings

supports several CRC standards commonly used.

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Chapter 18: LPC800 Cyclic Redundancy Check (CRC) engine

18.6 Description

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Fig 33. CRC block diagram

18.7 Register description

Table 201. Register overview: CRC engine (base address 0x5000 0000)

Name

Access Address Description

offset

Reset value

MODE

SEED

R/W

RO

0x00

0x04

0x08

CRC mode register

CRC seed register

CRC checksum register

CRC data register

0x0000 0000

0x0000 FFFF

-

SUM

WR_DATA

WO

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Chapter 18: LPC800 Cyclic Redundancy Check (CRC) engine

18.7.1 CRC mode register

Table 202. CRC mode register (MODE, address 0x5000 0000) bit description

Bit Symbol

Description

Reset value

1:0 CRC_POLY

CRC polynom:

00

1X= CRC-32 polynomial

01= CRC-16 polynomial

00= CRC-CCITT polynomial

Data bit order:

2

3

4

5

BIT_RVS_WR

CMPL_WR

0

1= Bit order reverse for CRC_WR_DATA (per byte)

0= No bit order reverse for CRC_WR_DATA (per byte)

Data complement:

0

1= 1’s complement for CRC_WR_DATA

0= No 1’s complement for CRC_WR_DATA

CRC sum bit order:

BIT_RVS_SUM

CMPL_SUM

0

1= Bit order reverse for CRC_SUM

0= No bit order reverse for CRC_SUM

CRC sum complement:

0

1= 1’s complement for CRC_SUM

0=No 1’s complement for CRC_SUM

Always 0 when read

31:6 Reserved

0x0000000

18.7.2 CRC seed register

Table 203. CRC seed register (SEED, address 0x5000 0004) bit description

Bit Symbol Description

Reset value

31:0 CRC_SEED A write access to this register will load CRC seed value to 0x0000 FFFF

CRC_SUM register with selected bit order and 1’s

complement pre-processes.

Remark: A write access to this register will overrule the

CRC calculation in progresses.

18.7.3 CRC checksum register

This register is a Read-only register containing the most recent checksum. The read

request to this register is automatically delayed by a finite number of wait states until the

results are valid and the checksum computation is complete.

Table 204. CRC checksum register (SUM, address 0x5000 0008) bit description

Bit

Symbol

Description

Reset value

31:0 CRC_SUM

The most recent CRC sum can be read through this

register with selected bit order and 1’s complement

post-processes.

0x0000 FFFF

18.7.4 CRC data register

This register is a Write-only register containing the data block for which the CRC sum will

be calculated.

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Chapter 18: LPC800 Cyclic Redundancy Check (CRC) engine

Table 205. CRC data register (WR_DATA, address 0x5000 0008) bit description

Bit

Symbol

Description

Reset

value

31:0 CRC_WR_DATA

Data written to this register will be taken to perform CRC

calculation with selected bit order and 1’s complement

pre-process. Any write size 8, 16 or 32-bit are allowed and

accept back-to-back transactions.

-

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Chapter 18: LPC800 Cyclic Redundancy Check (CRC) engine

18.8 Functional description

The following sections describe the register settings for each supported CRC standard:

18.8.1 CRC-CCITT set-up

Polynomial = x¹⁶+ x¹²+ x⁵+ 1

Seed Value = 0xFFFF

Bit order reverse for data input: NO

1's complement for data input: NO

Bit order reverse for CRC sum: NO

1's complement for CRC sum: NO

CRC_MODE = 0x0000 0000

CRC_SEED = 0x0000 FFFF

18.8.2 CRC-16 set-up

Polynomial = x¹⁶+ x¹⁵+ x²+ 1

Seed Value = 0x0000

Bit order reverse for data input: YES

1's complement for data input: NO

Bit order reverse for CRC sum: YES

1's complement for CRC sum: NO

CRC_MODE = 0x0000 0015

CRC_SEED = 0x0000 0000

18.8.3 CRC-32 set-up

Polynomial = x³²+ x²⁶+ x²³+ x²²+ x¹⁶+ x¹²+ x¹¹+ x¹⁰+ x⁸+ x⁷+ x⁵+ x⁴+ x²+ x + 1

Seed Value = 0xFFFF FFFF

Bit order reverse for data input: YES

1's complement for data input: NO

Bit order reverse for CRC sum: YES

1's complement for CRC sum: YES

CRC_MODE = 0x0000 0036

CRC_SEED = 0xFFFF FFFF

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Chapter 19: LPC800 Flash controller

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19.1 How to read this chapter

The flash controller is identical on all LPC800 parts.

19.2 Features

• Controls flash access time.

• Provides registers for flash signature generation.

19.3 General description

The flash controller is accessible for programming flash wait states and for generating the

the flash signature.

19.4 Register description

Table 206. Register overview: FMC (base address 0x4004 0000)

Name

Access Address Description

offset

Reset Reference

value

FLASHCFG R/W

FMSSTART R/W

0x010

0x020

0x024

0x02C

Flash configuration register

Signature start address register

Signature stop-address register

Signature word

<tbd> Table 207

0

-

Table 208

Table 209

Table 210

FMSSTOP

FMSW0

R/W

R

19.4.1 Flash configuration register

Depending on the system clock frequency, access to the flash memory can be configured

with various access times by writing to the FLASHCFG register at address 0x4003 C010.

Remark: Improper setting of this register may result in incorrect operation of the flash

memory.

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Chapter 19: LPC800 Flash controller

Table 207. Flash configuration register (FLASHCFG, address 0x4003 C010) bit description

Bit Symbol

Value

Description

Reset

value

1:0 FLASHTIM

Flash memory access time. FLASHTIM +1 is equal to the 10

number of system clocks used for flash access.

0x0

0x1

1 system clock flash access time (for system clock

frequencies of up to 20 MHz).

2 system clocks flash access time (for system clock

frequencies of up to 30 MHz).

0x2

0x3

-

Reserved.

31:2 -

Reserved. User software must not change the value of

these bits. Bits 31:2 must be written back exactly as

read.

-

19.4.2 Flash signature start address register

Table 208. Flash Module Signature Start register (FMSSTART - 0x4003 C020) bit description

Bit

Symbol

START

-

Description

Reset

value

16:0

31:17

Signature generation start address (corresponds to AHB byte

address bits[20:4]).

0

Reserved, user software should not write ones to reserved bits.

The value read from a reserved bit is not defined.

NA

19.4.3 Flash signature stop address register

Table 209. Flash Module Signature Stop register (FMSSTOP - 0x4003 C024) bit description

Bit

Symbol

Value Description

Reset

value

16:0

STOPA

Stop address for signature generation (the word

specified by STOPA is included in the address range).

The address is in units of memory words, not bytes.

0

30:17

31

-

Reserved, user software should not write ones to

reserved bits. The value read from a reserved bit is not

defined.

STRTBIST

When this bit is written to 1, signature generation starts.

At the end of signature generation, this bit is

automatically cleared.

19.4.4 Flash signature generation result register

The signature generation result register returns the flash signature produced by the

embedded signature generator.

The generated flash signature can be used to verify the flash memory contents. The

generated signature can be compared with an expected signature and thus makes saves

time and code space. The method for generating the signature is described in

Section 19.5.1.

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Chapter 19: LPC800 Flash controller

Table 210. FMSW0 register bit description (FMSW0, address: 0x4003 C02C)

Bit

Symbol

Description

Reset value

31:0

SIG

32-bit signature.

-

19.5 Functional description

19.5.1 Flash signature generation

The flash module contains a built-in signature generator. This generator can produce a

32-bit signature from a range of flash memory. A typical usage is to verify the flashed

contents against a calculated signature (e.g. during programming).

The address range for generating a signature must be aligned on flash-word boundaries,

i.e. 32-bit boundaries. Once started, signature generation completes independently. While

signature generation is in progress, the flash memory cannot be accessed for other

purposes, and an attempted read will cause a wait state to be asserted until signature

generation is complete. Code outside of the flash (e.g. internal RAM) can be executed

during signature generation. This can include interrupt services, if the interrupt vector

table is re-mapped to memory other than the flash memory. The code that initiates

signature generation should also be placed outside of the flash memory.

19.5.1.1 Signature generation address and control registers

These registers control automatic signature generation. A signature can be generated for

any part of the flash memory contents. The address range to be used for generation is

defined by writing the start address to the signature start address register (FMSSTART)

and the stop address to the signature stop address register (FMSSTOP. The start and

stop addresses must be aligned to 32-bit boundaries.

Signature generation is started by setting the STRTBIST bit in the FMSSTOP register.

Setting the STRTBIST bit is typically combined with the signature stop address in a single

write.

Table 208 and Table 209 show the bit assignments in the FMSSTART and FMSSTOP

registers respectively.

19.5.1.2 Signature generation

A signature can be generated for any part of the flash contents. The address range to be

used for signature generation is defined by writing the start address to the FMSSTART

register, and the stop address to the FMSSTOP register.

The signature generation is started by writing a 1 to the SIG_START bit in the FMSSTOP

register. Starting the signature generation is typically combined with defining the stop

address, which is done in the STOP bits of the same register.

The time that the signature generation takes is proportional to the address range for which

the signature is generated. Reading of the flash memory for signature generation uses a

self-timed read mechanism and does not depend on any configurable timing settings for

the flash. A safe estimation for the duration of the signature generation is:

Duration = int((60 / tcy) + 3) x (FMSSTOP - FMSSTART + 1)

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When signature generation is triggered via software, the duration is in AHB clock cycles,

and tcy is the time in ns for one AHB clock. The SIG_DONE bit in FMSTAT can be polled

by software to determine when signature generation is complete.

After signature generation, a 32-bit signature can be read from the FMSW0 register. The

32-bit signature reflects the corrected data read from the flash and the flash parity bits and

check bit values.

19.5.1.3 Content verification

The signature as it is read from the FMSW0 register must be equal to the reference

signature. The following pseudo-code shows the algorithm to derive the reference

signature:

sign = 0

FOR address = FMSSTART.START to FMSSTOP.STOPA

{

FOR i = 0 TO 30{

nextSign[i] = f_Q[addredd[i] XOR sign[i + 1]

nextSign[31] = f_q[address[31] XOR sign[0] XOR sign[10] XOR sign[30] XOR sign[31]

sign = nextSign

}

signature32 = sign

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Chapter 20: LPC800 Boot ROM

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Preliminary user manual

20.1 How to read this chapter

The Boot ROM is identical for all LPC800 parts.

20.2 Features

• 8 kB on-chip boot ROM

• Contains the boot loader with In-System Programming (ISP) facility and the following

APIs:

– In Application Programming (IAP) of flash memory

– Power profiles for optimizing power consumption and system performance

– USART drivers

– I2C drivers

20.3 General description

20.3.1 Boot loader

The boot loader controls initial operation after reset and also provides the means to

accomplish programming of the flash memory via USART. This could be initial

programming of a blank device, erasure and re-programming of a previously programmed

device, or programming of the flash memory by the application program in a running

system.

The boot loader code is executed every time the part is powered on or reset. The boot

loader can execute the ISP command handler or the user application code. A LOW level

after reset at the PIO0_1 pin is considered as an external hardware request to start the

ISP command handler via USART.

For details on the boot process, see Section 20.4.3 “Boot process”.

Remark: SRAM location 0x1000 0000 to 0x1000 0050 is not used by the bootloader and

the memory content in this area is retained during reset. SRAM memory is not retained

when the part powers down or enters Deep power-down mode.

Assuming that power supply pins are on their nominal levels when the rising edge on

RESET pin is generated, it may take up to <tbd>3 ms before PIO0_1 is sampled and the

decision whether to continue with user code or ISP handler is made. If PIO0_1 is sampled

low and the watchdog overflow flag is set, the external hardware request to start the ISP

command handler is ignored. If there is no request for the ISP command handler

execution (PIO0_1 is sampled HIGH after reset), a search is made for a valid user

program. If a valid user program is found then the execution control is transferred to it. If a

valid user program is not found, the auto-baud routine is invoked.

Remark: The sampling of pin PIO0_1 can be disabled through programming flash

location 0x0000 02FC (see Section 21.3.3 “Code Read Protection (CRP)”).

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Chapter 20: LPC800 Boot ROM

20.3.2 ROM-based APIs

Once the part has booted, the user can access several APIs located in the boot ROM to

access the flash memory, optimize power consumption, and operate the USART and I2C

peripherals.

The structure of the boot ROM APIs is shown in

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Fig 34. Boot ROM structure

Table 211. API calls

API

Description

Reference

Table 234

Table 247

Flash IAP

Flash In-Application programming

Power profiles API

Configure system clock and power

consumption

I2C driver

I2C ROM Driver

Table 250

Table 271

UART driver

UART get memory size

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Chapter 20: LPC800 Boot ROM

20.4 Functional description

20.4.1 Boot pins

When pin PIO0_1 is pulled LOW on reset, the part enters ISP mode and the ISP

command handler starts up. In ISP mode, pins PIO0_0 is connected to function U0_RXD

and pin PIO0_4 is connected to function U0_TXD on the USART0 block.

20.4.2 Memory map after any reset

The boot block is 8 kB in size. The boot block is located in the memory region starting

from the address 0x1FFF 0000. The bootloader is designed to run from this memory area,

but both the ISP and IAP software use parts of the on-chip RAM. The RAM usage is

described later in this chapter. The interrupt vectors residing in the boot block of the

on-chip flash memory also become active after reset, i.e., the bottom 512 bytes of the

boot block are also visible in the memory region starting from the address 0x0000 0000.

20.4.3 Boot process

During the boot process, the boot loader checks if there is valid user code in flash. The

criterion for valid user code is as follows:

The reserved Cortex-M0+ exception vector location 7 (offset 0x0000 001C in the vector

table) should contain the 2’s complement of the check-sum of table entries 0 through 6.

This causes the checksum of the first 8 table entries to be 0. The bootloader code

checksums the first 8 locations in sector 0 of the flash. If the result is 0, then execution

control is transferred to the user code.

If the signature is not valid, the auto-baud routine synchronizes with the host via serial port

USART0. The host should send a ’?’ (0x3F) as a synchronization character and wait for a

response. The host side serial port settings should be 8 data bits, 1 stop bit and no parity.

The auto-baud routine measures the bit time of the received synchronization character in

terms of its own frequency (the 12 MHz IRC frequency) and programs the baud rate

generator of the serial port. It also sends an ASCII string ("Synchronized<CR><LF>") to

the host. In response, the host should send the same string ("Synchronized<CR><LF>").

The boot loader auto-baud routine looks at the received characters to verify

synchronization. If synchronization is verified then "OK<CR><LF>" string is sent to the

host. The host should respond by sending the crystal frequency (in kHz) at which the part

is running. The response is required for backward compatibility of the boot loader code

and, on the LPC800, is ignored. The boot loader configures the part to run at the 12 MHz

IRC frequency.

Once the crystal frequency response is received, the part is initialized and the ISP

command handler is invoked. For safety reasons an "Unlock" command is required before

executing the commands resulting in flash erase/write operations and the "Go" command.

The rest of the commands can be executed without the unlock command. The Unlock

command is required to be executed once per ISP session. The Unlock command is

explained in Table 218 “UART ISP Unlock command”.

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Chapter 20: LPC800 Boot ROM

20.4.4 Boot process flowchart

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(1) This step is included for backward compatibility and the response is ignored by the boot loader.

Fig 35. Boot process flowchart

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Chapter 21: LPC800 Flash ISP and IAP programming

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Preliminary user manual

21.1 How to read this chapter

See Table 212 for different flash configurations.

Table 212. LPC800 flash configurations

Type number

Flash

4 kB

LPC810M021FN8

LPC811M001FDH16

LPC812M101FDH16

LPC812M101FD20

8 kB

16 kB

LPC812M101FDH20

21.2 Features

• In-System Programming: In-System programming (ISP) is programming or

reprogramming the on-chip flash memory, using the bootloader software and UART

serial port.

• In-Application Programming: In-Application (IAP) programming is performing erase

and write operation on the on-chip flash memory, as directed by the end-user

application code.

• You can use ISP and IAP when the part resides in the end-user board.

• Flash page write and erase supported.

21.3 General description

21.3.1 Flash configuration

Most IAP and ISP commands operate on sectors and specify sector numbers. In addition

a page erase command is supported. The following table shows the correspondence

between page numbers, sector numbers, and memory addresses.

The size of a sector is 1 kB and the size of a page is 64 Byte. One sector contains 16

pages.

Table 213. LPC800 flash configuration

Sector

Sector Page

Address range

4 kB

8 kB

16 kB

number size

[kB]

number

0

1

2

3

4

5

1

0 -15

0x0000 0000 - 0x0000 03FF

0x0000 0400 - 0x0000 07FF

0x0000 0800 - 0x0000 0BFF

0x0000 0C00 - 0x0000 0FFF

0x0000 1000 - 0x0000 13FF

0x0000 1400 - 0x0000 17FF

yes

16 - 31

32 - 47

48 - 63

64 - 79

80 - 95

yes

-

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Chapter 21: LPC800 Flash ISP and IAP programming

Table 213. LPC800 flash configuration

Sector

Sector Page

Address range

4 kB

8 kB

16 kB

number size

[kB]

number

6

1

96 - 111

0x0000 1800 - 0x0000 1BFF

0x0000 1C00 - 0x0000 1FFF

0x0000 2000 - 0x0000 23FF

0x0000 2400 - 0x0000 27FF

0x0000 2800 - 0x0000 2BFF

0x0000 2C00 - 0x0000 2FFF

0x0000 3000 - 0x0000 33FF

0x0000 3400 - 0x0000 37FF

0x0000 3800 - 0x0000 3BFF

0x0000 3C00 - 0x0000 3FFF

-

yes

7

112 - 127

128 - 143

144 - 159

160 - 175

176 - 191

192 - 207

208 - 223

224 - 239

240 - 255

-

8

-

9

yes

10

11

12

13

14

15

21.3.2 Flash content protection mechanism

The part is equipped with the Error Correction Code (ECC) capable Flash memory. The

purpose of an error correction module is twofold:

The ECC first decodes data words read from the memory into output data words. Then,

the ECC encodes data words to be written to the memory. The error correction capability

consists of single bit error correction with Hamming code.

The operation of the ECC is transparent to the running application. The ECC content itself

is stored in a flash memory not accessible by the user’s code to either read from it or write

into it on its own. 6 bit of ECC corresponds to every consecutive 32 bit of the user

accessible Flash. Consequently, Flash bytes from 0x0000 0000 to 0x0000 0003 are

protected by the first 6 bit ECC, Flash bytes from 0x0000 0004 to 0x0000 0007 are

protected by the second 6-bit ECC byte, etc.

Whenever the CPU requests a read from the user accessible Flash, both 32 bits of raw

data containing the specified memory location and the matching ECC byte are evaluated.

If the ECC mechanism detects a single error in the fetched data, a correction will be

applied before data are provided to the CPU. When a write request into the user

accessible Flash is made, writing the user specified content is accompanied by a

matching ECC value calculated and stored in the ECC memory.

When a sector of Flash memory is erased, the corresponding ECC bits are also erased.

Once a 6-bit ECC is written, it can not be updated unless it is erased first. Therefore, for

the implemented ECC mechanism to perform properly, data must be written into the flash

memory in groups of 4 bytes (or multiples of 4), aligned as described above.

21.3.3 Code Read Protection (CRP)

Code Read Protection is a mechanism that allows the user to enable different levels of

security in the system so that access to the on-chip flash and use of the ISP can be

restricted. When needed, CRP is invoked by programming a specific pattern in flash

location at 0x0000 02FC. IAP commands are not affected by the code read protection.

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Chapter 21: LPC800 Flash ISP and IAP programming

Important: any CRP change becomes effective only after the device has gone

through a power cycle.

Table 214. Code Read Protection options

Name

Pattern

Description

programmed in

0x0000 02FC

NO_ISP 0x4E69 7370

Prevents sampling of pin PIO0_1 for entering ISP mode. PIO0_1 is available for other uses.

CRP1

0x12345678

Access to chip via the SWD pins is disabled. This mode allows partial flash update using the

following ISP commands and restrictions:

• Write to RAM command should not access RAM below 0x1000 0300. Access to

addresses below 0x1000 0200 is disabled.

• Copy RAM to flash command can not write to Sector 0.

• Erase command can erase Sector 0 only when all sectors are selected for erase.

• Compare command is disabled.

• Read Memory command is disabled.

This mode is useful when CRP is required and flash field updates are needed but all sectors

can not be erased. Since compare command is disabled in case of partial updates the

secondary loader should implement checksum mechanism to verify the integrity of the flash.

CRP2

0x87654321

Access to chip via the SWD pins is disabled. The following ISP commands are disabled:

• Read Memory

• Write to RAM

• Go

• Copy RAM to flash

• Compare

When CRP2 is enabled the ISP erase command only allows erasure of all user sectors.

CRP3

0x43218765

Access to chip via the SWD pins is disabled. ISP entry by pulling PIO0_1 LOW is disabled if a

valid user code is present in flash sector 0.

This mode effectively disables ISP override using PIO0_1 pin. It is up to the user’s application

to provide a flash update mechanism using IAP calls or call reinvoke ISP command to enable

flash update via UART.

Caution: If CRP3 is selected, no future factory testing can be performed on the device.

Table 215. Code Read Protection hardware/software interaction

CRP option

User Code

Valid

PIO0_1 pin at SWD enabled Part enters

partial flash

update in ISP

mode

reset

ISP mode

None

CRP1

CRP2

CRP3

CRP1

CRP2

CRP3

No

x

Yes

No

Yes

No

Yes

NA

Yes

NA

Yes

NA

No

Yes

No

High

Low

High

Low

High

Low

x

Yes

No

Yes

No

Yes

No

NA

Yes

No

x

Yes

No

x

No

x

No

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Chapter 21: LPC800 Flash ISP and IAP programming

Table 216. ISP commands allowed for different CRP levels

ISP command

CRP1

CRP2

CRP3 (no entry in ISP

mode allowed)

Unlock

yes

no

n/a

Set Baud Rate

Echo

Write to RAM

yes; above 0x1000 0300

only

Read Memory

no

n/a

Prepare sector(s) for

write operation

yes

Copy RAM to flash

Go

yes; not to sector 0

no

n/a

Erase sector(s)

yes; sector 0 can only be

yes; all sectors n/a

erased when all sectors are only

erased.

Blank check sector(s)

Read Part ID

no

n/a

yes

no

Read Boot code version yes

Compare

ReadUID

no

yes

In case a CRP mode is enabled and access to the chip is allowed via the ISP, an

unsupported or restricted ISP command will be terminated with return code

CODE_READ_PROTECTION_ENABLED.

21.3.3.1 ISP entry protection

In addition to the three CRP modes, the user can prevent the sampling of pin PIO0_1 for

entering ISP mode and thereby release pin PIO0_1 for other uses. This is called the

NO_ISP mode. The NO_ISP mode can be entered by programming the pattern

0x4E69 7370 at location 0x0000 02FC.

21.4 API description

21.4.1 UART ISP commands

The following commands are accepted by the ISP command handler. Detailed status

codes are supported for each command. The command handler sends the return code

INVALID_COMMAND when an undefined command is received. Commands and return

codes are in ASCII format.

CMD_SUCCESS is sent by ISP command handler only when received ISP command has

been completely executed and the new ISP command can be given by the host.

Exceptions from this rule are "Set Baud Rate", "Write to RAM", "Read Memory", and "Go"

commands.

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Table 217. UART ISP command summary

ISP Command

Usage

Described in

Table 218

Table 219

Table 220

Table 221

Table 222

Table 223

Unlock

U <Unlock Code>

Set Baud Rate

Echo

B <Baud Rate> <stop bit>

A <setting>

Write to RAM

Read Memory

W <start address> <number of bytes>

R <address> <number of bytes>

P <start sector number> <end sector number>

Prepare sector(s) for

write operation

Copy RAM to flash

Go

C <Flash address> <RAM address> <number of bytes> Table 224

G <address> <Mode>

Table 225

Table 226

Table 227

Table 228

Table 230

Table 231

Table 232

Erase sector(s)

Blank check sector(s)

Read Part ID

Read Boot code version

Compare

E <start sector number> <end sector number>

I <start sector number> <end sector number>

J

K

M <address1> <address2> <number of bytes>

N

ReadUID

21.4.1.1 Unlock <Unlock code>

Table 218. UART ISP Unlock command

Command

Input

U

Unlock code: 23130₁₀

Return Code

CMD_SUCCESS |

INVALID_CODE |

PARAM_ERROR

Description

Example

This command is used to unlock Flash Write, Erase, and Go commands.

"U 23130<CR><LF>" unlocks the Flash Write/Erase & Go commands.

21.4.1.2 Set Baud Rate <Baud Rate> <stop bit>

Table 219. UART ISP Set Baud Rate command

Command

B

Input

Baud Rate: 9600 | 19200 | 38400 | 57600 | 115200

Stop bit: 1 | 2

Return Code

CMD_SUCCESS |

INVALID_BAUD_RATE |

INVALID_STOP_BIT |

PARAM_ERROR

Description

Example

This command is used to change the baud rate. The new baud rate is effective

after the command handler sends the CMD_SUCCESS return code.

"B 57600 1<CR><LF>" sets the serial port to baud rate 57600 bps and 1 stop bit.

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21.4.1.3 Echo <setting>

Table 220. UART ISP Echo command

Command

A

Input

Setting: ON = 1 | OFF = 0

Return Code

CMD_SUCCESS |

PARAM_ERROR

Description

Example

The default setting for echo command is ON. When ON the ISP command handler

sends the received serial data back to the host.

"A 0<CR><LF>" turns echo off.

21.4.1.4 Write to RAM <start address> <number of bytes>

The host should send the plain binary code after receiving the CMD_SUCCESS return

code. This ISP command handler responds with “OK<CR><LF>” when the transfer has

finished.

Table 221. UART ISP Write to RAM command

Command

W

Input

Start Address: RAM address where data bytes are to be written. This address

should be a word boundary.

Number of Bytes: Number of bytes to be written. Count should be a multiple of 4

CMD_SUCCESS |

Return Code

ADDR_ERROR (Address not on word boundary) |

ADDR_NOT_MAPPED |

COUNT_ERROR (Byte count is not multiple of 4) |

PARAM_ERROR |

CODE_READ_PROTECTION_ENABLED

Description

Example

This command is used to download data to RAM. This command is blocked when

code read protection levels 2 or 3 are enabled. Writing to addresses below

0x1000 0300 is disabled for CRP1.

"W 268436224 4<CR><LF>" writes 4 bytes of data to address 0x1000 0300.

21.4.1.5 Read Memory <address> <number of bytes>

Reads the the plain binary code of the data stream, followed by the CMD_SUCCESS

return code.

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Table 222. UART ISP Read Memory command

Command

R

Input

Start Address: Address from where data bytes are to be read. This address

should be a word boundary.

Number of Bytes: Number of bytes to be read. Count should be a multiple of 4.

CMD_SUCCESS followed by <actual data (plain binary)> |

ADDR_ERROR (Address not on word boundary) |

ADDR_NOT_MAPPED |

Return Code

COUNT_ERROR (Byte count is not a multiple of 4) |

PARAM_ERROR |

CODE_READ_PROTECTION_ENABLED

Description

Example

This command is used to read data from RAM or flash memory. This command is

blocked when code read protection is enabled.

"R 268435456 4<CR><LF>" reads 4 bytes of data from address 0x1000 0000.

21.4.1.6 Prepare sector(s) for write operation <start sector number> <end sector

number>

This command makes flash write/erase operation a two step process.

Table 223. UART ISP Prepare sector(s) for write operation command

Command

P

Input

Start Sector Number

End Sector Number: Should be greater than or equal to start sector number.

Return Code

Description

CMD_SUCCESS |

BUSY |

INVALID_SECTOR |

PARAM_ERROR

This command must be executed before executing "Copy RAM to flash" or "Erase

Sector(s)" command. Successful execution of the "Copy RAM to flash" or "Erase

Sector(s)" command causes relevant sectors to be protected again. The boot

block can not be prepared by this command. To prepare a single sector use the

same "Start" and "End" sector numbers.

Example

"P 0 0<CR><LF>" prepares the flash sector 0.

21.4.1.7 Copy RAM to flash <Flash address> <RAM address> <no of bytes>

When writing to the flash, the following limitations apply:

1. The smallest amount of data that can be written to flash by the copy RAM to flash

command is 64 byte (equal to one page).

2. One page consists of 16 flash words (lines), and the smallest amount that can be

modified per flash write is one flash word (one line). This limitation follows from the

application of ECC to the flash write operation, see Section 21.3.2.

3. To avoid write disturbance (a mechanism intrinsic to flash memories), an erase should

be performed after following 16 consecutive writes inside the same page. Note that

the erase operation then erases the entire sector.

Remark: Once a page has been written to 16 times, it is still possible to write to other

pages within the same sector without performing a sector erase (assuming that those

pages have been erased previously).

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Table 224. UART ISP Copy RAM to flash command

Command

Input

C

Flash Address (DST): Destination flash address where data bytes are to be

written. The destination address should be a 64 byte boundary.

RAM Address (SRC): Source RAM address from where data bytes are to be read.

Number of Bytes: Number of bytes to be written. Should be 64 | 128 | 256 | 512 |

1024.

Return Code CMD_SUCCESS |

SRC_ADDR_ERROR (Address not on word boundary) |

DST_ADDR_ERROR (Address not on correct boundary) |

SRC_ADDR_NOT_MAPPED |

DST_ADDR_NOT_MAPPED |

COUNT_ERROR (Byte count is not 64 | 128 | 256 | 512 | 1024) |

SECTOR_NOT_PREPARED_FOR WRITE_OPERATION |

BUSY |

CMD_LOCKED |

PARAM_ERROR |

CODE_READ_PROTECTION_ENABLED

Description

Example

This command is used to program the flash memory. The "Prepare Sector(s) for

Write Operation" command should precede this command. The affected sectors are

automatically protected again once the copy command is successfully executed.

The boot block cannot be written by this command. This command is blocked when

code read protection is enabled.

"C 0 268467504 512<CR><LF>" copies 512 bytes from the RAM address

0x1000 0800 to the flash address 0.

21.4.1.8 Go <address> <mode>

Table 225. UART ISP Go command

Command

G

Input

Address: Flash or RAM address from which the code execution is to be started.

This address should be on a word boundary.

Mode: T (Execute program in Thumb Mode).

Return Code CMD_SUCCESS |

ADDR_ERROR |

ADDR_NOT_MAPPED |

CMD_LOCKED |

PARAM_ERROR |

CODE_READ_PROTECTION_ENABLED

Description

Example

This command is used to execute a program residing in RAM or flash memory. It

may not be possible to return to the ISP command handler once this command is

successfully executed. This command is blocked when code read protection is

enabled. The command must be used with an address of 0x0000 0200 or greater.

"G 512 T<CR><LF>" branches to address 0x0000 0200 in Thumb mode.

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21.4.1.9 Erase sector(s) <start sector number> <end sector number>

Table 226. UART ISP Erase sector command

Command

E

Input

Start Sector Number

End Sector Number: Should be greater than or equal to start sector number.

Return Code CMD_SUCCESS |

BUSY |

INVALID_SECTOR |

SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION |

CMD_LOCKED |

PARAM_ERROR |

CODE_READ_PROTECTION_ENABLED

Description

Example

This command is used to erase one or more sector(s) of on-chip flash memory. The

boot block can not be erased using this command. This command only allows

erasure of all user sectors when the code read protection is enabled.

"E 2 3<CR><LF>" erases the flash sectors 2 and 3.

21.4.1.10 Blank check sector(s) <sector number> <end sector number>

Table 227. UART ISP Blank check sector command

Command

I

Input

Start Sector Number:

End Sector Number: Should be greater than or equal to start sector number.

Return Code CMD_SUCCESS |

SECTOR_NOT_BLANK (followed by <Offset of the first non blank word location>

<Contents of non blank word location>) |

INVALID_SECTOR |

PARAM_ERROR

Description

Example

This command is used to blank check one or more sectors of on-chip flash memory.

Blank check on sector 0 always fails as first 64 bytes are re-mapped to flash

boot block.

When CRP is enabled, the blank check command returns 0 for the offset and value

of sectors which are not blank. Blank sectors are correctly reported irrespective of

the CRP setting.

"I 2 3<CR><LF>" blank checks the flash sectors 2 and 3.

21.4.1.11 Read Part Identification number

Table 228. UART ISP Read Part Identification command

Command

J

Input

None.

Return Code CMD_SUCCESS followed by part identification number in ASCII (see Table 229).

Description

This command is used to read the part identification number.

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Table 229. Part identification numbers

Device

Hex coding

0x0000 8100

0x0000 8110

0x0000 8120

0x0000 8121

0x0000 8122

LPC810M021FN8

LPC811M001FDH16

LPC812M101FDH16

LPC812M101FD20

LPC812M101FDH20

21.4.1.12 Read Boot code version number

Table 230. UART ISP Read Boot Code version number command

Command

K

Input

None

Return Code CMD_SUCCESS followed by 2 bytes of boot code version number in ASCII format.

It is to be interpreted as <byte1(Major)>.<byte0(Minor)>.

Description

This command is used to read the boot code version number.

21.4.1.13 Compare <address1> <address2> <no of bytes>

Table 231. UART ISP Compare command

Command

M

Input

Address1 (DST): Starting flash or RAM address of data bytes to be compared.

This address should be a word boundary.

Address2 (SRC): Starting flash or RAM address of data bytes to be compared.

This address should be a word boundary.

Number of Bytes: Number of bytes to be compared; should be a multiple of 4.

Return Code CMD_SUCCESS | (Source and destination data are equal)

COMPARE_ERROR | (Followed by the offset of first mismatch)

COUNT_ERROR (Byte count is not a multiple of 4) |

ADDR_ERROR |

ADDR_NOT_MAPPED |

PARAM_ERROR

Description

Example

This command is used to compare the memory contents at two locations.

"M 8192 268468224 4<CR><LF>" compares 4 bytes from the RAM address

0x1000 8000 to the 4 bytes from the flash address 0x2000.

21.4.1.14 ReadUID

Table 232. UART ISP ReadUID command

Command

N

Input

None

Return Code CMD_SUCCESS followed by four 32-bit words of E-sort test information in ASCII

format. The word sent at the lowest address is sent first.

Description

This command is used to read the unique ID.

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21.4.1.15 UART ISP Return Codes

Table 233. UART ISP Return Codes Summary

Return Mnemonic

Code

Description

0

CMD_SUCCESS

Command is executed successfully. Sent by ISP

handler only when command given by the host has

been completely and successfully executed.

1

2

3

4

INVALID_COMMAND

SRC_ADDR_ERROR

DST_ADDR_ERROR

SRC_ADDR_NOT_MAPPED

Invalid command.

Source address is not on word boundary.

Destination address is not on a correct boundary.

Source address is not mapped in the memory map.

Count value is taken in to consideration where

applicable.

5

DST_ADDR_NOT_MAPPED

Destination address is not mapped in the memory

map. Count value is taken in to consideration

where applicable.

6

7

COUNT_ERROR

Byte count is not multiple of 4 or is not a permitted

value.

INVALID_SECTOR

SECTOR_NOT_BLANK

Sector number is invalid or end sector number is

greater than start sector number.

8

9

Sector is not blank.

SECTOR_NOT_PREPARED_FOR_ Command to prepare sector for write operation

WRITE_OPERATION

COMPARE_ERROR

BUSY

was not executed.

10

11

12

Source and destination data not equal.

Flash programming hardware interface is busy.

PARAM_ERROR

Insufficient number of parameters or invalid

parameter.

13

14

ADDR_ERROR

Address is not on word boundary.

ADDR_NOT_MAPPED

Address is not mapped in the memory map. Count

value is taken in to consideration where applicable.

15

16

17

18

19

CMD_LOCKED

Command is locked.

INVALID_CODE

Unlock code is invalid.

Invalid baud rate setting.

Invalid stop bit setting.

Code read protection enabled.

INVALID_BAUD_RATE

INVALID_STOP_BIT

CODE_READ_PROTECTION_

ENABLED

21.4.2 IAP commands

For in application programming the IAP routine should be called with a word pointer in

register r0 pointing to memory (RAM) containing command code and parameters. Result

of the IAP command is returned in the result table pointed to by register r1. The user can

reuse the command table for result by passing the same pointer in registers r0 and r1. The

parameter table should be big enough to hold all the results in case the number of results

are more than number of parameters. Parameter passing is illustrated in the Figure 36.

The number of parameters and results vary according to the IAP command. The

maximum number of parameters is 5, passed to the "Copy RAM to FLASH" command.

The maximum number of results is 4, returned by the "ReadUID" command. The

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command handler sends the status code INVALID_COMMAND when an undefined

command is received. The IAP routine resides at 0x1FFF 1FF0 location and it is thumb

code.

The IAP function could be called in the following way using C.

Define the IAP location entry point. Since the 0th bit of the IAP location is set there will be

a change to Thumb instruction set when the program counter branches to this address.

#define IAP_LOCATION 0x1fff1ff1

Define data structure or pointers to pass IAP command table and result table to the IAP

function:

unsigned long command[5];

unsigned long result[4];

or

unsigned long * command;

unsigned long * result;

command=(unsigned long *) 0x...

result= (unsigned long *) 0x...

Define pointer to function type, which takes two parameters and returns void. Note the IAP

returns the result with the base address of the table residing in R1.

typedef void (*IAP)(unsigned int [],unsigned int[]);

IAP iap_entry;

Setting function pointer:

iap_entry=(IAP) IAP_LOCATION;

Whenever you wish to call IAP you could use the following statement.

iap_entry (command, result);

As per the ARM specification (The ARM Thumb Procedure Call Standard SWS ESPC

0002 A-05) up to 4 parameters can be passed in the r0, r1, r2 and r3 registers

respectively. Additional parameters are passed on the stack. Up to 4 parameters can be

returned in the r0, r1, r2 and r3 registers respectively. Additional parameters are returned

indirectly via memory. Some of the IAP calls require more than 4 parameters. If the ARM

suggested scheme is used for the parameter passing/returning then it might create

problems due to difference in the C compiler implementation from different vendors. The

suggested parameter passing scheme reduces such risk.

The flash memory is not accessible during a write or erase operation. IAP commands,

which results in a flash write/erase operation, use 32 bytes of space in the top portion of

the on-chip RAM for execution. The user program should not be use this space if IAP flash

programming is permitted in the application.

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Table 234. IAP Command Summary

IAP Command

Command Code

50 (decimal)

51 (decimal)

52 (decimal)

53 (decimal)

54 (decimal)

55 (decimal)

56 (decimal)

57 (decimal)

58 (decimal)

59 (decimal)

Described in

Table 235

Table 236

Table 237

Table 238

Table 239

Table 240

Table 241

Table 242

Table 243

Table 244

Prepare sector(s) for write operation

Copy RAM to flash

Erase sector(s)

Blank check sector(s)

Read Part ID

Read Boot code version

Compare

Reinvoke ISP

Read UID

Erase page

ꢓꢚꢃꢃꢂꢑꢍꢈꢓꢚꢍꢌ

ꢙꢂꢁꢂꢃꢌꢋꢌꢁꢈꢄ

ꢙꢂꢁꢂꢃꢌꢋꢌꢁꢈꢆ

!#<<%&'

5%)%<+(+)ꢈ(%C"+

ꢂꢁꢃꢈꢁꢌꢏꢐꢀꢋꢌꢁꢈ),

ꢂꢁꢃꢈꢁꢌꢏꢐꢀꢋꢌꢁꢈ)ꢄ

ꢙꢂꢁꢂꢃꢌꢋꢌꢁꢈ&

ꢀꢋꢂꢋꢎꢀꢈꢓꢚꢍꢌ

ꢁꢌꢀꢎꢔꢋꢈꢄ

!#<<%&'

)+$;"(ꢈ(%C"+

ꢁꢌꢀꢎꢔꢋꢈꢆ

ꢁꢌꢀꢎꢔꢋꢈ&

Fig 36. IAP parameter passing

21.4.2.1 Prepare sector(s) for write operation (IAP)

This command makes flash write/erase operation a two step process.

Table 235. IAP Prepare sector(s) for write operation command

Command

Prepare sector(s) for write operation

Command code: 50 (decimal)

Param0: Start Sector Number

Input

Param1: End Sector Number (should be greater than or equal to start sector

number).

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Table 235. IAP Prepare sector(s) for write operation command

Command Prepare sector(s) for write operation

Return Code

CMD_SUCCESS |

BUSY |

INVALID_SECTOR

None

Result

Description

This command must be executed before executing "Copy RAM to flash" or "Erase

Sector(s)" command. Successful execution of the "Copy RAM to flash" or "Erase

Sector(s)" command causes relevant sectors to be protected again. The boot

sector can not be prepared by this command. To prepare a single sector use the

same "Start" and "End" sector numbers.

21.4.2.2 Copy RAM to flash (IAP)

See Section 21.4.1.4 for limitations on the write-to-flash process.

Table 236. IAP Copy RAM to flash command

Command

Copy RAM to flash

Input

Command code: 51 (decimal)

Param0(DST): Destination flash address where data bytes are to be written. This

address should be a 64 byte boundary.

Param1(SRC): Source RAM address from which data bytes are to be read. This

address should be a word boundary.

Param2: Number of bytes to be written. Should be 64 | 128 | 256 | 512 | 1024.

Param3: System Clock Frequency (CCLK) in kHz.

CMD_SUCCESS |

Return Code

SRC_ADDR_ERROR (Address not a word boundary) |

DST_ADDR_ERROR (Address not on correct boundary) |

SRC_ADDR_NOT_MAPPED |

DST_ADDR_NOT_MAPPED |

COUNT_ERROR (Byte count is not 256 | 512 | 1024 | 4096) |

SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION |

BUSY

Result

None

Description

This command is used to program the flash memory. The affected sectors should

be prepared first by calling "Prepare Sector for Write Operation" command. The

affected sectors are automatically protected again once the copy command is

successfully executed. The boot sector can not be written by this command.

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21.4.2.3 Erase Sector(s) (IAP)

Table 237. IAP Erase Sector(s) command

Command

Erase Sector(s)

Input

Command code: 52 (decimal)

Param0: Start Sector Number

Param1: End Sector Number (should be greater than or equal to start sector

number).

Param2: System Clock Frequency (CCLK) in kHz.

Return Code

CMD_SUCCESS |

BUSY |

SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION |

INVALID_SECTOR

None

Result

Description

This command is used to erase a sector or multiple sectors of on-chip flash

memory. The boot sector can not be erased by this command. To erase a single

sector use the same "Start" and "End" sector numbers.

21.4.2.4 Blank check sector(s) (IAP)

Table 238. IAP Blank check sector(s) command

Command Blank check sector(s)

Input Command code: 53 (decimal)

Param0: Start Sector Number

Param1: End Sector Number (should be greater than or equal to start sector

number).

Return Code

CMD_SUCCESS |

BUSY |

SECTOR_NOT_BLANK |

INVALID_SECTOR

Result

Result0: Offset of the first non blank word location if the Status Code is

SECTOR_NOT_BLANK.

Result1: Contents of non blank word location.

Description

This command is used to blank check a sector or multiple sectors of on-chip flash

memory. To blank check a single sector use the same "Start" and "End" sector

numbers.

21.4.2.5 Read Part Identification number (IAP)

Table 239. IAP Read Part Identification command

Command

Read part identification number

Command code: 54 (decimal)

Parameters: None

Input

Return Code

Result

CMD_SUCCESS

Result0: Part Identification Number.

This command is used to read the part identification number.

Description

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21.4.2.6 Read Boot code version number (IAP)

Table 240. IAP Read Boot Code version number command

Command

Read boot code version number

Command code: 55 (decimal)

Parameters: None

Input

Return Code

Result

CMD_SUCCESS

Result0: 2 bytes of boot code version number. Read as

<byte1(Major)>.<byte0(Minor)>

Description

This command is used to read the boot code version number.

21.4.2.7 Compare <address1> <address2> <no of bytes> (IAP)

Table 241. IAP Compare command

Command

Compare

Input

Command code: 56 (decimal)

Param0(DST): Starting flash or RAM address of data bytes to be compared. This

address should be a word boundary.

Param1(SRC): Starting flash or RAM address of data bytes to be compared. This

address should be a word boundary.

Param2: Number of bytes to be compared; should be a multiple of 4.

CMD_SUCCESS |

Return Code

COMPARE_ERROR |

COUNT_ERROR (Byte count is not a multiple of 4) |

ADDR_ERROR |

ADDR_NOT_MAPPED

Result

Result0: Offset of the first mismatch if the Status Code is COMPARE_ERROR.

This command is used to compare the memory contents at two locations.

Description

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21.4.2.8 Reinvoke ISP (IAP)

Table 242. IAP Reinvoke ISP

Command

Input

Compare

Command code: 57 (decimal)

Return Code

Result

None

None.

Description

This command is used to invoke the bootloader in ISP mode. It maps boot

vectors, sets PCLK = CCLK, and configures USART0 pins U0_RXD and

U0_TXD. This command may be used when a valid user program is present in the

internal flash memory and the PIO0_1 pin is not accessible to force the ISP mode.

21.4.2.9 ReadUID (IAP)

Table 243. IAP ReadUID command

Command

Input

Compare

Command code: 58 (decimal)

CMD_SUCCESS

Return Code

Result

Result0: The first 32-bit word (at the lowest address).

Result1: The second 32-bit word.

Result2: The third 32-bit word.

Result3: The fourth 32-bit word.

Description

This command is used to read the unique ID.

21.4.2.10 Erase page

Table 244. IAP Erase page command

Command

Erase page

Input

Command code: 59 (decimal)

Param0: Start page number.

Param1: End page number (should be greater than or equal to start page)

Param2: System Clock Frequency (CCLK) in kHz.

Return Code

CMD_SUCCESS |

BUSY |

SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION |

INVALID_SECTOR

None

Result

Description

This command is used to erase a page or multiple pages of on-chip flash memory.

To erase a single page use the same "start" and "end" page numbers.

21.4.2.11 IAP Status Codes

Table 245. IAP Status Codes Summary

Status Mnemonic

Code

Description

0

1

2

3

CMD_SUCCESS

Command is executed successfully.

Invalid command.

INVALID_COMMAND

SRC_ADDR_ERROR

DST_ADDR_ERROR

Source address is not on a word boundary.

Destination address is not on a correct boundary.

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Table 245. IAP Status Codes Summary

Status Mnemonic

Description

Code

4

SRC_ADDR_NOT_MAPPED

DST_ADDR_NOT_MAPPED

COUNT_ERROR

Source address is not mapped in the memory map.

Count value is taken in to consideration where

applicable.

5

6

Destination address is not mapped in the memory

map. Count value is taken in to consideration where

applicable.

Byte count is not multiple of 4 or is not a permitted

value.

7

8

9

INVALID_SECTOR

Sector number is invalid.

Sector is not blank.

SECTOR_NOT_BLANK

SECTOR_NOT_PREPARED_

FOR_WRITE_OPERATION

Command to prepare sector for write operation was

not executed.

10

11

COMPARE_ERROR

BUSY

Source and destination data is not same.

Flash programming hardware interface is busy.

21.5 Functional description

21.5.1 UART Communication protocol

All UART ISP commands should be sent as single ASCII strings. Strings should be

terminated with Carriage Return (CR) and/or Line Feed (LF) control characters. Extra

<CR> and <LF> characters are ignored. All ISP responses are sent as <CR><LF>

terminated ASCII strings. Data is sent and received in plain binary format.

21.5.1.1 UART ISP command format

"Command Parameter_0 Parameter_1 ... Parameter_n<CR><LF>" "Data" (Data only for

Write commands).

21.5.1.2 UART ISP response format

"Return_Code<CR><LF>Response_0<CR><LF>Response_1<CR><LF> ...

Response_n<CR><LF>" "Data" (Data only for Read commands).

21.5.1.3 UART ISP data format

The data stream is in plain binary format.

21.5.2 Memory and interrupt use for ISP and IAP

21.5.2.1 Interrupts during UART ISP

The boot block interrupt vectors located in the boot block of the flash are active after any

reset.

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21.5.2.2 Interrupts during IAP

The on-chip flash memory is not accessible during erase/write operations. When the user

application code starts executing the interrupt vectors from the user flash area are active.

Before making any IAP call, either disable the interrupts or ensure that the user interrupt

vectors are active in RAM and that the interrupt handlers reside in RAM. The IAP code

does not use or disable interrupts.

21.5.2.3 RAM used by ISP command handler

The stack of ISP commands is located at 0x1000 0270. The maximum stack usage is

540 byte and grows downwards.

21.5.2.4 RAM used by IAP command handler

The maximum stack usage in the user allocated stack space is 148 bytes and grows

downwards.

21.5.3 Debugging

21.5.3.1 Comparing flash images

Depending on the debugger used and the IDE debug settings, the memory that is visible

when the debugger connects might be the boot ROM, the internal SRAM, or the flash. To

help determine which memory is present in the current debug environment, check the

value contained at flash address 0x0000 0004. This address contains the entry point to

the code in the ARM Cortex-M0+ vector table, which is the bottom of the boot ROM, the

internal SRAM, or the flash memory respectively.

Table 246. Memory mapping in debug mode

Memory mapping mode

Bootloader mode

Memory start address visible at 0x0000 0004

0x1FFF 0000

0x0000 0000

0x1000 0000

User flash mode

User SRAM mode

21.5.3.2 Serial Wire Debug (SWD) flash programming interface

Debug tools can write parts of the flash image to RAM and then execute the IAP call

"Copy RAM to flash" repeatedly with proper offset.

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Chapter 22: LPC800 Power profile API ROM driver

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22.1 How to read this chapter

The power profiles are available for all LPC800 parts.

22.2 Features

• Includes ROM-based application services

• Power Management services

• Clocking services

22.3 General description

The power consumption in Active and Sleep modes can be optimized for the application

through simple calls to the power profile. The power configuration routine configures the

LPC800 for one of the following power modes:

• Default mode corresponding to power configuration after reset.

• CPU performance mode corresponding to optimized processing capability.

• Efficiency mode corresponding to optimized balance of current consumption and CPU

performance.

• Low-current mode corresponding to lowest power consumption.

In addition, the power profile includes routines to select the optimal PLL settings for a

given system clock and PLL input clock.

Remark: Disable all interrupts before making calls to the power profile API. You can

re-enable the interrupts after the power profile API calls have completed.

The API calls to the ROM are performed by executing functions which are pointed by a

pointer within the ROM Driver Table. Figure 37 shows the pointer structure used to call the

Power Profiles API.

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Chapter 22: LPC800 Power profile API ROM driver

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Fig 38. LPC800 clock configuration for power API use

22.4 API description

The power profile API provides functions to configure the system clock and optimize the

system setting for lowest power consumption.

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Table 247. Power profile API calls

API call

Description

Reference

Table 248

Table 249

set_pll(command, result)

set_power(command, result)

Power API set pll routine

Power API set power routine

The following elements have to be defined in an application that uses the power profiles:

typedef struct _PWRD {

void (*set_pll)(unsigned int cmd[], unsigned int resp[]);

void (*set_power)(unsigned int cmd[], unsigned int resp[]);

} PWRD;

typedef struct _ROM {

const PWRD * pWRD;

} ROM;

ROM ** rom = (ROM **) (0x1FFF1FF8 + 3 * sizeof(ROM**));

unsigned int command[4], result[2];

22.4.1 set_pll

This routine sets up the system PLL according to the calling arguments. If the expected

clock can be obtained by simply dividing the system PLL input, set_pll bypasses the PLL

to lower system power consumption.

Remark: Before this routine is invoked, the PLL clock source (IRC/system oscillator) must

be selected (Table 13), the main clock source must be set to the input clock to the system

PLL (Table 8) and the system/AHB clock divider must be set to 1 (Table 15).

set_pll attempts to find a PLL setup that matches the calling parameters. Once a

combination of a feedback divider value (SYSPLLCTRL, M), a post divider ratio

(SYSPLLCTRL, P) and the system/AHB clock divider (SYSAHBCLKDIV) is found, set_pll

applies the selected values and switches the main clock source selection to the system

PLL clock out (if necessary).

The routine returns a result code that indicates if the system PLL was successfully set

(PLL_CMD_SUCCESS) or not (in which case the result code identifies what went wrong).

The current system frequency value is also returned. The application should use this

information to adjust other clocks in the device (the SSP, UART, and WDT clocks, and/or

clockout).

Table 248. set_pll routine

Routine

set_pll

Input

Param0: system PLL input frequency (in kHz)

Param1: expected system clock (in kHz)

Param2: mode (CPU_FREQ_EQU, CPU_FREQ_LTE, CPU_FREQ_GTE,

CPU_FREQ_APPROX)

Param3: system PLL lock time-out

Result

Result0: PLL_CMD_SUCCESS | PLL_INVALID_FREQ | PLL_INVALID_MODE |

PLL_FREQ_NOT_FOUND | PLL_NOT_LOCKED

Result1: system clock (in kHz)

The following definitions are needed when making set_pll power routine calls:

/* set_pll mode options */

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#define

CPU_FREQ_EQU

CPU_FREQ_LTE

CPU_FREQ_GTE

CPU_FREQ_APPROX

0

1

2

3

/* set_pll result0 options */

#define

PLL_CMD_SUCCESS

PLL_INVALID_FREQ

PLL_INVALID_MODE

PLL_FREQ_NOT_FOUND

PLL_NOT_LOCKED

0

1

2

3

4

For a simplified clock configuration scheme see Figure 38. For more details see Figure 3.

22.4.1.1 Param0: system PLL input frequency and Param1: expected system clock

set_pll looks for a setup in which the system PLL clock does not exceed 50 MHz. It easily

finds a solution when the ratio between the expected system clock and the system PLL

input frequency is an integer value, but it can also find solutions in other cases.

The system PLL input frequency (Param0) must be between 10000 to 25000 kHz (10

MHz to 25 MHz) inclusive. The expected system clock (Param1) must be between 1 and

50000 kHz inclusive. If either of these requirements is not met, set_pll returns

PLL_INVALID_FREQ and returns Param0 as Result1 since the PLL setting is unchanged.

22.4.1.2 Param2: mode

The first priority of set_pll is to find a setup that generates the system clock at exactly the

rate specified in Param1. If it is unlikely that an exact match can be found, input parameter

mode (Param2) should be used to specify if the actual system clock can be less than or

equal, greater than or equal or approximately the value specified as the expected system

clock (Param1).

A call specifying CPU_FREQ_EQU will only succeed if the PLL can output exactly the

frequency requested in Param1.

CPU_FREQ_LTE can be used if the requested frequency should not be exceeded (such

as overall current consumption and/or power budget reasons).

CPU_FREQ_GTE helps applications that need a minimum level of CPU processing

capabilities.

CPU_FREQ_APPROX results in a system clock that is as close as possible to the

requested value (it may be greater than or less than the requested value).

If an illegal mode is specified, set_pll returns PLL_INVALID_MODE. If the expected

system clock is out of the range supported by this routine, set_pll returns

PLL_FREQ_NOT_FOUND. In these cases the current PLL setting is not changed and

Param0 is returned as Result1.

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22.4.1.3 Param3: system PLL lock time-out

It should take no more than 100 s for the system PLL to lock if a valid configuration is

selected. If Param3 is zero, set_pll will wait indefinitely for the PLL to lock. A non-zero

value indicates how many times the code will check for a successful PLL lock event

before it returns PLL_NOT_LOCKED. In this case the PLL settings are unchanged and

Param0 is returned as Result1.

Remark: The time it takes the PLL to lock depends on the selected PLL input clock

source (IRC/system oscillator) and its characteristics. The selected source can

experience more or less jitter depending on the operating conditions such as power

supply and/or ambient temperature. This is why it is suggested that when a good known

clock source is used and a PLL_NOT_LOCKED response is received, the set_pll routine

should be invoked several times before declaring the selected PLL clock source invalid.

Hint: setting Param3 equal to the system PLL frequency [Hz] divided by 10000 will

provide more than enough PLL lock-polling cycles.

22.4.2 set_power

This routine configures the device’s internal power control settings according to the calling

arguments. The goal is to reduce active power consumption while maintaining the feature

of interest to the application close to its optimum.

Remark: The set_power routine was designed for systems employing the configuration of

SYSAHBCLKDIV = 1 (System clock divider register, see Table 17 and Figure 38). Using

this routine in an application with the system clock divider not equal to 1 might not improve

microcontroller’s performance as much as in setups when the main clock and the system

clock are running at the same rate.

set_power returns a result code that reports whether the power setting was successfully

changed or not.

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Fig 39. Power profiles usage

Table 249. set_power routine

Routine

set_power

Input

Param0: main clock (in MHz)

Param1: mode (PWR_DEFAULT, PWR_CPU_PERFORMANCE, PWR_

EFFICIENCY, PWR_LOW_CURRENT)

Param2: system clock (in MHz)

Result

Result0: PWR_CMD_SUCCESS | PWR_INVALID_FREQ |

PWR_INVALID_MODE

The following definitions are needed for set_power routine calls:

/* set_power mode options */

#define

PWR_DEFAULT

PWR_CPU_PERFORMANCE

PWR_EFFICIENCY

0

1

2

3

PWR_LOW_CURRENT

/* set_power result0 options */

#define

PWR_CMD_SUCCESS

PWR_INVALID_FREQ

PWR_INVALID_MODE

0

1

2

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For a simplified clock configuration scheme see Figure 38. For more details see Figure 3.

22.4.2.1 Param0: main clock

The main clock is the clock rate the microcontroller uses to source the system’s and the

peripherals’ clock. It is configured by either a successful execution of the clocking routine

call or a similar code provided by the user. This operand must be an integer between 1 to

50 MHz inclusive. If a value out of this range is supplied, set_power returns

PWR_INVALID_FREQ and does not change the power control system.

22.4.2.2 Param1: mode

The input parameter mode (Param1) specifies one of four available power settings. If an

illegal selection is provided, set_power returns PWR_INVALID_MODE and does not

change the power control system.

PWR_DEFAULT keeps the device in a baseline power setting similar to its reset state.

PWR_CPU_PERFORMANCE configures the microcontroller so that it can provide more

processing capability to the application. CPU performance is 30% better than the default

option.

PWR_EFFICIENCY setting was designed to find a balance between active current and

the CPU’s ability to execute code and process data. In this mode the device outperforms

the default mode both in terms of providing higher CPU performance and lowering active

current.

PWR_LOW_CURRENT is intended for those solutions that focus on lowering power

consumption rather than CPU performance.

22.4.2.3 Param2: system clock

The system clock is the clock rate at which the microcontroller core is running when

set_power is called. This parameter is an integer between from 1 and 50 MHz inclusive.

22.5 Functional description

22.5.1 Clock control

See Section 22.5.1.1 to Section 22.5.1.6 for examples of the clock control API.

22.5.1.1 Invalid frequency (device maximum clock rate exceeded)

command[0] = 12000;

command[1] = 60000;

command[2] = CPU_FREQ_EQU;

command[3] = 0;

(*rom)->pWRD->set_pll(command, result);

The above code specifies a 12 MHz PLL input clock and a system clock of exactly

60 MHz. The application was ready to infinitely wait for the PLL to lock. But the expected

system clock of 60 MHz exceeds the maximum of 50 MHz. Therefore set_pll returns

PLL_INVALID_FREQ in result[0] and 12000 in result[1] without changing the PLL

settings.

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22.5.1.2 Invalid frequency selection (system clock divider restrictions)

command[0] = 12000;

command[1] = 40;

command[2] = CPU_FREQ_LTE;

command[3] = 0;

(*rom)->pWRD->set_pll(command, result);

The above code specifies a 12 MHz PLL input clock, a system clock of no more than

40 kHz and no time-out while waiting for the PLL to lock. Since the maximum divider value

for the system clock is 255 and running at 40 kHz would need a divide by value of 300,

set_pll returns PLL_INVALID_FREQ in result[0] and 12000 in result[1] without changing

the PLL settings.

22.5.1.3 Exact solution cannot be found (PLL)

command[0] = 12000;

command[1] = 25000;

command[2] = CPU_FREQ_EQU;

command[3] = 0;

(*rom)->pWRD->set_pll(command, result);

The above code specifies a 12 MHz PLL input clock and a system clock of exactly

25 MHz. The application was ready to infinitely wait for the PLL to lock. Since there is no

valid PLL setup within earlier mentioned restrictions, set_pll returns

PLL_FREQ_NOT_FOUND in result[0] and 12000 in result[1] without changing the PLL

settings.

22.5.1.4 System clock less than or equal to the expected value

command[0] = 12000;

command[1] = 25000;

command[2] = CPU_FREQ_LTE;

command[3] = 0;

(*rom)->pWRD->set_pll(command, result);

The above code specifies a 12 MHz PLL input clock, a system clock of no more than

25 MHz and no locking time-out. set_pll returns PLL_CMD_SUCCESS in result[0] and

24000 in result[1]. The new system clock is 24 MHz.

22.5.1.5 System clock greater than or equal to the expected value

command[0] = 12000;

command[1] = 25000;

command[2] = CPU_FREQ_GTE;

command[3] = 0;

(*rom)->pWRD->set_pll(command, result);

The above code specifies a 12 MHz PLL input clock, a system clock of at least 25 MHz

and no locking time-out. set_pll returns PLL_CMD_SUCCESS in result[0] and 36000 in

result[1]. The new system clock is 36 MHz.

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22.5.1.6 System clock approximately equal to the expected value

command[0] = 12000;

command[1] = 16500;

command[2] = CPU_FREQ_APPROX;

command[3] = 0;

(*rom)->pWRD->set_pll(command, result);

The above code specifies a 12 MHz PLL input clock, a system clock of approximately

16.5 MHz and no locking time-out. set_pll returns PLL_CMD_SUCCESS in result[0] and

16000 in result[1]. The new system clock is 16 MHz.

22.5.2 Power control

See Section 22.5.1.1 and Section 22.5.2.2 for examples of the power control API.

22.5.2.1 Invalid frequency (device maximum clock rate exceeded)

command[0] = 30;

command[1] = PWR_CPU_PERFORMANCE;

command[2] = 40;

(*rom)->pWRD->set_power(command, result);

The above setup would be used in a system running at the main and system clock of

30 MHz, with a need for maximum CPU processing power. Since the specified 40 MHz

clock is above the 30 MHz maximum, set_power returns PWR_INVALID_FREQ in

result[0] without changing anything in the existing power setup.

22.5.2.2 An applicable power setup

command[0] = 24;

command[1] = PWR_CPU_EFFICIENCY;

command[2] = 24;

(*rom)->pWRD->set_power(command, result);

The above code specifies that an application is running at the main and system clock of

24 MHz with emphasis on efficiency. set_power returns PWR_CMD_SUCCESS in

result[0] after configuring the microcontroller’s internal power control features.

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Chapter 23: LPC800 I2C-bus ROM API

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23.1 How to read this chapter

The I2C-bus ROM API is available on all LPC800 parts.

23.2 Features

• Simple I2C drivers to send and receive data on the I2C-bus.

• Polled and interrupt-driven receive and transmit functions for master and slave

modes.

23.3 General description

The drivers are callable for use by any application program to send or receive data on the

I2C bus. With the I2C drivers it is easy to produce working projects using the I2C

interface.

The ROM routines allow the user to operate the I2C interface as a Master or a Slave. The

software routines do not implement arbitration to make a Master switch to a Slave mode in

the midst of a transmission.

Although multi-master arbitration is not implemented in these I2C drivers, it is possible to

use them in a system design with more than one master. If the flag returned from the

driver indicates that the message was not successful due to loss of arbitration, the

application just resends the message.

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Chapter 23: LPC800 I2C-bus ROM API

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Fig 40. I2C-bus driver routines pointer structure

23.4 API description

The I2C API contains functions to configure the I2C and send and receive data in master

and slave modes.

Table 250. I2C API calls

API call

Description

Reference

void i2c_isr_handler(I2C_HANDLE_T*)

I2C ROM Driver interrupt service

routine.

Table 251

ErrorCode_t i2c_master_transmit_poll(I2C_HANDLE_T*, I2C_PARAM*, I2C Master Transmit Polling

I2C_RESULT* )

Table 252

Table 253

Table 254

Table 255

Table 256

Table 257

ErrorCode_t i2c_master_receive_poll(I2C_HANDLE_T* , I2C_PARAM* , I2C Master Receive Polling

I2C_RESULT*)

ErrorCode_t i2c_master_tx_rx_poll(I2C_HANDLE_T* , I2C_PARAM* ,

I2C_RESULT*)

I2C Master Transmit and Receive

Polling

ErrorCode_t i2c_master_transmit_intr(I2C_HANDLE_T* , I2C_PARAM* , I2C Master Transmit Interrupt

I2C_RESULT*)

ErrorCode_t i2c_master_receive_intr(I2C_HANDLE_T* , I2C_PARAM* , I2C Master Receive Interrupt

I2C_RESULT*)

ErrorCode_t i2c_master_tx_rx_intr(I2C_HANDLE_T* , I2C_PARAM* ,

I2C_RESULT*)

I2C Master Transmit Receive

Interrupt

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Table 250. I2C API calls

API call

Description

I2C Slave Receive Polling

Reference

ErrorCode_t i2c_slave_receive_poll(I2C_HANDLE_T* , I2C_PARAM* ,

I2C_RESULT*)

Table 258

ErrorCode_t i2c_slave_transmit_poll(I2C_HANDLE_T* , I2C_PARAM* , I2C Slave Transmit Polling

I2C_RESULT*)

Table 259

Table 260

Table 261

Table 262

ErrorCode_t i2c_slave_receive_intr(I2C_HANDLE_T* , I2C_PARAM* ,

I2C_RESULT*)

I2C Slave Receive Interrupt

ErrorCode_t i2c_slave_transmit_intr(I2C_HANDLE_T* , I2C_PARAM* , I2C Slave Transmit Interrupt

I2C_RESULT*)

ErrorCode_t i2c_set_slave_addr(I2C_HANDLE_T*, slave_addr_0_3,

slave_mask_0_3)

I2C Set Slave Address

uint32_t i2c_get_mem_size(void)

I2C Get Memory Size

I2C Setup

Table 263

Table 264

Table 265

I2C_HANDLE_T* i2c_setup(i2c_base_addr, *start_of_ram)

ErrorCode_t i2c_set_bitrate(I2C_HANDLE_T*, P_clk_in_hz,

bitrate_in_bps)

I2C Set Bit Rate

uint32_t i2c_get_firmware_version(void )

I2C Get Firmware Version

I2C Get Status

Table 266

Table 267

Table 268

I2C_MODE_T i2c_get_status(I2C_HANDLE_T* )

ErrorCode_t i2c_set_timeout(I2C_HANDLE_T* h_i2c, uint32_t timeout) I2C time-out value

The following structure has to be defined to use the I2C API:

typedef struct I2CD_API

{

// index of all the i2c driver functions

void (*i2c_isr_handler) (I2C_HANDLE_T* h_i2c)

// MASTER functions ***

; // ISR interrupt service request

ErrorCode_t (*i2c_master_transmit_poll)(I2C_HANDLE_T* h_i2c, I2C_PARAM* ptp,

I2C_RESULT* ptr );

ErrorCode_t (*i2c_master_receive_poll)(I2C_HANDLE_T* h_i2c, I2C_PARAM* ptp,

I2C_RESULT* ptr );

ErrorCode_t (*i2c_master_tx_rx_poll)(I2C_HANDLE_T* h_i2c,I2C_PARAM* ptp,

I2C_RESULT* ptr

ErrorCode_t (*i2c_master_transmit_intr)(I2C_HANDLE_T* h_i2c, I2C_PARAM* ptp,

I2C_RESULT* ptr

ErrorCode_t (*i2c_master_receive_intr)(I2C_HANDLE_T* h_i2c, I2C_PARAM* ptp,

I2C_RESULT* ptr

ErrorCode_t (*i2c_master_tx_rx_intr)(I2C_HANDLE_T* h_i2c, I2C_PARAM* ptp, I2C_RESULT*

ptr

) ;

)

;

)

;

)

;

// SLAVE functions ***

ErrorCode_t (*i2c_slave_receive_poll)(I2C_HANDLE_T* h_i2c, I2C_PARAM* ptp, I2C_RESULT*

ptr

ErrorCode_t (*i2c_slave_transmit_poll)(I2C_HANDLE_T* h_i2c, I2C_PARAM* ptp,

I2C_RESULT* ptr

ErrorCode_t (*i2c_slave_receive_intr)(I2C_HANDLE_T* h_i2c, I2C_PARAM* ptp, I2C_RESULT*

ptr

ErrorCode_t (*i2c_slave_transmit_intr)(I2C_HANDLE_T* h_i2c, I2C_PARAM* ptp,

I2C_RESULT* ptr

ErrorCode_t (*i2c_set_slave_addr)(I2C_HANDLE_T* h_i2c,

uint32_t slave_addr_0_3, uint32_t slave_mask_0_3);

) ;

)

;

)

;

)

;

// OTHER functions

uint32_t (*i2c_get_mem_size)(void)

; //ramsize_in_bytes memory needed by I2C drivers

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I2C_HANDLE_T*

ErrorCode_t

(*i2c_setup)(uint32_t i2c_base_addr, uint32_t *start_of_ram

(*i2c_set_bitrate)(I2C_HANDLE_T* h_i2c, uint32_t P_clk_in_hz,

) ;

uint32_t bitrate_in_bps)

uint32_t (*i2c_get_firmware_version)()

I2C_MODE_T (*i2c_get_status)(I2C_HANDLE_T* h_i2c

I2CD_API_T

;

)

;

}

;

23.4.1 ISR handler

Table 251. ISR handler

Routine

ISR handler

void i2c_isr_handler(I2C_HANDLE_T*)

Prototype

Input parameter

Return

I2C_HANDLE_T - Handle to the allocated SRAM area.

None.

Description

I2C ROM Driver interrupt service routine. This function must be called from

the I2C ISR when using I2C Rom Driver interrupt mode.

23.4.2 I2C Master Transmit Polling

Table 252. I2C Master Transmit Polling

Routine

I2C Master Transmit Polling

Prototype

ErrorCode_t i2c_master_transmit_poll(I2C_HANDLE_T*, I2C_PARAM*,

I2C_RESULT* )

Input parameter

I2C_HANDLE_T - Handle to the allocated SRAM area.

I2C_PARAM - Pointer to the I2C PARAM struct.

I2C_RESULT - Pointer to the I2C RESULT struct.

ErrorCode.

Return

Description

Transmits bytes in the send buffer to a slave. The slave address with the R/W

bit =0 is expected in the first byte of the send buffer. STOP condition is sent at

end unless stop_flag =0. When the task is completed, the function returns to

the line after the call.

23.4.3 I2C Master Receive Polling

Table 253. I2C Master Receive Polling

Routine

I2C Master Receive Polling

Prototype

ErrorCode_t i2c_master_receive_poll(I2C_HANDLE_T* , I2C_PARAM* ,

I2C_RESULT*)

Input parameter

I2C_HANDLE_T - Handle to the allocated SRAM area.

I2C_PARAM - Pointer to the I2C PARAM struct.

I2C_RESULT - Pointer to the I2C RESULT struct.

ErrorCode.

Return

Description

Receives bytes from slave and put into receive buffer. The slave address with

the R/W bit =0 is expected in the first byte of the send buffer. After the task is

finished, the slave address with the R/W bit =1 is in the first byte of the receive

buffer. STOP condition is sent at end unless stop_flag =0. When the task is

completed, the function returns to the line after the call.

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23.4.4 I2C Master Transmit and Receive Polling

Table 254. I2C Master Transmit and Receive Polling

Routine

I2C Master Transmit and Receive Polling

Prototype

ErrorCode_t i2c_master_tx_rx_poll(I2C_HANDLE_T* , I2C_PARAM* ,

I2C_RESULT*)

Input parameter

I2C_HANDLE_T - Handle to the allocated SRAM area.

I2C_PARAM - Pointer to the I2C PARAM struct.

I2C_RESULT - Pointer to the I2C RESULT struct.

ErrorCode.

Return

Description

First, transmit bytes in the send buffer to a slave and secondly, receives bytes

from slave and store it in the receive buffer. The slave address with the R/W

bit =0 is expected in the first byte of the send buffer. After the task is finished,

the slave address with the R/W bit =1 is in the first byte of the receive buffer.

STOP condition is sent at end unless stop_flag =0. When the task is

completed, the function returns to the line after the call.

23.4.5 I2C Master Transmit Interrupt

Table 255. I2C Master Transmit Interrupt

Routine

I2C Master Transmit Interrupt

Prototype

ErrorCode_t i2c_master_transmit_intr(I2C_HANDLE_T* , I2C_PARAM* ,

I2C_RESULT*)

Input parameter

I2C_HANDLE_T - Handle to the allocated SRAM area.

I2C_PARAM - Pointer to the I2C PARAM struct.

I2C_RESULT - Pointer to the I2C RESULT struct.

ErrorCode.

Return

Description

Transmits bytes in the send buffer to a slave. The slave address with the R/W

bit =0 is expected in the first byte of the send buffer. STOP condition is sent at

end unless stop_flag =0. Program control will be returned immediately and

task will be completed on an interrupt-driven basis. When task is completed,

the callback function is called.

23.4.6 I2C Master Receive Interrupt

Table 256. I2C Master Receive Interrupt

Routine

I2C Master Receive Interrupt

Prototype

ErrorCode_t i2c_master_receive_intr(I2C_HANDLE_T* , I2C_PARAM* ,

I2C_RESULT*)

Input parameter

I2C_HANDLE_T - Handle to the allocated SRAM area.

I2C_PARAM - Pointer to the I2C PARAM struct.

I2C_RESULT - Pointer to the I2C RESULT struct.

ErrorCode.

Return

Description

Receives bytes from slave and put into receive buffer. After the task is

finished, the slave address with the R/W bit =1 is in the first byte of the receive

buffer. STOP condition is sent at end unless stop_flag =0. Program control will

be returned immediately and task will be completed on an interrupt-driven

basis. When task is completed, the callback function is called.

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23.4.7 I2C Master Transmit Receive Interrupt

Table 257. I2C Master Transmit Receive Interrupt

Routine

I2C Master Transmit Receive Interrupt

Prototype

ErrorCode_t i2c_master_tx_rx_intr(I2C_HANDLE_T* , I2C_PARAM* ,

I2C_RESULT*)

Input parameter

I2C_HANDLE_T - Handle to the allocated SRAM area.

I2C_PARAM - Pointer to the I2C PARAM struct.

I2C_RESULT - Pointer to the I2C RESULT struct.

ErrorCode.

Return

Description

First, transmits bytes in the send buffer to a slave and secondly, receives

bytes from slave and store it in the receive buffer. The slave address with the

R/W bit =0 is expected in the first byte of the send buffer. After the task is

finished, the slave address with the R/W bit =1 is in the first byte of the receive

buffer. STOP condition is sent at end unless stop_flag =0. Program control will

be returned immediately and task will be completed on an interrupt-driven

basis. When task is completed, the callback function is called.

23.4.8 I2C Slave Receive Polling

Table 258. I2C Slave Receive Polling

Routine

I2C Slave Receive Polling

Prototype

ErrorCode_t i2c_slave_receive_poll(I2C_HANDLE_T* , I2C_PARAM* ,

I2C_RESULT*)

Input parameter

I2C_HANDLE_T - Handle to the allocated SRAM area.

I2C_PARAM - Pointer to the I2C PARAM struct.

I2C_RESULT - Pointer to the I2C RESULT struct.

ErrorCode.

Return

Description

Receives data from master. When the task is completed, the function returns

to the line after the call.

23.4.9 I2C Slave Transmit Polling

Table 259. I2C Slave Transmit Polling

Routine

I2C Slave Transmit Polling

Prototype

ErrorCode_t i2c_slave_transmit_poll(I2C_HANDLE_T* , I2C_PARAM* ,

I2C_RESULT*)

Input parameter

I2C_HANDLE_T - Handle to the allocated SRAM area.

I2C_PARAM - Pointer to the I2C PARAM struct.

I2C_RESULT - Pointer to the I2C RESULT struct.

ErrorCode.

Return

Description

Sends data bytes back to master. When the task is completed, the function

returns to the line after the call.

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23.4.10 I2C Slave Receive Interrupt

Table 260. I2C Slave Receive Interrupt

Routine

I2C Slave Receive Interrupt

Prototype

ErrorCode_t i2c_slave_receive_intr(I2C_HANDLE_T* , I2C_PARAM* ,

I2C_RESULT*)

Input parameter

I2C_HANDLE_T - Handle to the allocated SRAM area.

I2C_PARAM - Pointer to the I2C PARAM struct.

I2C_RESULT - Pointer to the I2C RESULT struct.

ErrorCode.

Return

Description

Receives data from master. Program control will be returned immediately and

task will be completed on an interrupt-driven basis. When task is completed,

the callback function is called.

23.4.11 I2C Slave Transmit Interrupt

Table 261. I2C Slave Transmit Interrupt

Routine

I2C Slave Transmit Interrupt

Prototype

ErrorCode_t i2c_slave_transmit_intr(I2C_HANDLE_T* , I2C_PARAM* ,

I2C_RESULT*)

Input parameter

I2C_HANDLE_T - Handle to the allocated SRAM area.

I2C_PARAM - Pointer to the I2C PARAM struct.

I2C_RESULT - Pointer to the I2C RESULT struct.

ErrorCode.

Return

Description

Sends data to the Master. Program control will be returned immediately and

task will be completed on an interrupt-driven basis. When task is completed,

the callback function is called.

23.4.12 I2C Set Slave Address

Table 262. I2C Set Slave Address

Routine

I2C Set Slave Address

Prototype

ErrorCode_t i2c_set_slave_addr(I2C_HANDLE_T*, slave_addr_0_3,

slave_mask_0_3)

Input parameter

I2C_HANDLE_T - Handle to the allocated SRAM area.

Slave_addr_0_3 - unint32 variable. 7-bit slave address .

Slave_mask_0_3 - unint32 variable. Slave address mask.

ErrorCode.

Return

Description

Sets the slave address and associated mask. The set_slave_addr() function

supports four 7-bit slave addresses and masks.

23.4.13 I2C Get Memory Size

Table 263. I2C Get Memory Size

Routine

I2C Get Memory Size

Prototype

uint32_t i2c_get_mem_size(void)

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Table 263. I2C Get Memory Size

Routine

I2C Get Memory Size

None.

Input parameter

Return

uint32.

Description

Returns the number of bytes in SRAM needed by the I2C driver.

23.4.14 I2C Setup

Table 264. I2C Setup

Routine

I2C Setup

Prototype

I2C_HANDLE_T* i2c_setup(i2c_base_addr, *start_of_ram)

I2C_base addr - unint32 variable. Base address for I2C peripherals.

Start_of_ram - unint32 pointer. Pointer to allocated SRAM.

I2C_Handle.

Input parameter

Return

Description

Returns a handle to the allocated SRAM area.

23.4.15 I2C Set Bit Rate

Table 265. I2C Set Bit Rate

Routine

I2C Set Bit Rate

Prototype

ErrorCode_t i2c_set_bitrate(I2C_HANDLE_T*, P_clk_in_hz, bitrate_in_bps)

I2C_HANDLE_T - Handle to the allocated SRAM area.

P_clk_in_hz - unint32 variable. The Peripheral Clock in Hz.

Bitrate_in_bps - unint32 variable. Requested I2C operating frequency in Hz.

ErrorCode.

Input parameter

Return

Description

Configures the I2C duty-cycle registers (SCLH and SCLL).

23.4.16 I2C Get Firmware Version

Table 266. I2C Get Firmware Version

Routine

I2C Get Firmware Version

Prototype

Input parameter

Return

uint32_t i2c_get_firmware_version(void )

None.

I2C ROM Driver version number.

Description

Returns the version number. The firmware version is an unsigned 32-bit

number.

23.4.17 I2C Get Status

Table 267. I2C Get Status

Routine

I2C Get Status

Prototype

Input parameter

Return

I2C_MODE_T i2c_get_status(I2C_HANDLE_T* )

I2C_HANDLE_T - Handle to the allocated SRAM area.

Status code.

Description

Returns status code. The status code indicates the state of the I2C bus.

Refer to I2C Status Code Table.

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23.4.18 I2C time-out value

Table 268. I2C time-out value

Routine

I2C time-out value

Prototype

ErrorCode_t i2c_set_timeout(I2C_HANDLE_T* h_i2c, uint32_t timeout)

I2C_HANDLE_T - Handle to the allocated SRAM area.

Input parameter

uint32_t timeout - time value is timeout*16 i2c function clock. If timeout = 0,

timeout feature is disabled.

Return

Status code.

Description

Returns status code. The status code indicates the state of the I2C bus.

Refer to I2C Status Code Table.

23.4.19 Error codes

Table 269. Error codes

Error Code

0

Description

Comment

Successful completion

General error

Function was completed successfully.

1

-

0x0006 0001

0x0006 0002

0x0006 0003

0x0006 0004

0x0006 0005

0x0006 0006

0x0006 0007

0x0006 0008

ERR_I2C_NAK

ERR_I2C_BUFFER_OVERFLOW

ERR_I2C_BYTE_COUNT_ERR

-

ERR_I2C_LOSS_OF_ARBRITRATION

ERR_I2C_SLAVE_NOT_ADDRESSED

ERR_I2C_LOSS_OF_ARBRITRATION_NAK_BIT -

ERR_I2C_GENERAL_FAILURE

Failure detected on I2C bus.

ERR_I2C_REGS_SET_TO_DEFAULT

I2C clock frequency could not be set. Default value

of 0x04 is loaded into SCLH and SCLL.

23.4.20 I2C Status code

Table 270. I2C Status code

Status code

Description

0

1

2

3

4

IDLE

MASTER_SEND

MASTER_RECEIVE

SLAVE_SEND

SLAVE_RECEIVE

23.4.21 I2C ROM driver variables

The I2C ROM driver requires specific variables to be declared and initialized for proper

usage. Depending on the operating mode, some variables can be omitted.

23.4.21.1 I2C Handle

The I2C handle is a pointer allocated for the I2C ROM driver. The handle needs to be

defined as an I2C handle TYPE:

typedef void* I2C_HANDLE_T

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After the definition of the handle, the handle must be initialized with I2C base address and

RAM reserved for the I2C ROM driver by making a call to the i2c_setup() function.

The callback function type must be defined if interrupts for the I2C ROM driver are used:

typedef void (*I2C_CALLBK_T) (uint32_t err_code, uint32_t n)

The callback function will be called by the I2C ROM driver upon completion of a task when

interrupts are used.

23.4.22 PARAM and RESULT structure

The I2C ROM driver input parameters consist of two structures, a PARAM structure and a

RESULT structure. The PARAM structure contains the parameters passed to the I2C

ROM driver and the RESULT structure contains the results after the I2C ROM driver is

called.

The PARAM structure is as follows:

typedef struct i2c_A

{ //parameters passed to ROM function

uint32_t num_bytes_send

uint32_t num_bytes_rec

;

uint8_t *buffer_ptr_send

uint8_t *buffer_ptr_rec

;

I2C_CALLBK_T func_pt; // callback function pointer

uint8_t stop_flag;

uint8_t dummy[3]

I2C_PARAM

;

// required for word alignment

}

;

The RESULT structure is as follows:

typedef struct i2c_R

{

// RESULTs struct--results are here when returned

uint32_t n_bytes_sent

uint32_t n_bytes_recd

;

}

I2C_RESULT ;

23.4.23 Error structure

The error code returned by the I2C ROM driver is an enum structure. The Error structure

is as follows:

typedef enum

{

LPC_OK=0, /**< enum value returned on Success */

ERROR,

ERR_I2C_BASE

= 0x00060000,

/*0x00060001*/ ERR_I2C_NAK=ERR_I2C_BASE+1,

/*0x00060002*/ ERR_I2C_BUFFER_OVERFLOW,

/*0x00060003*/ ERR_I2C_BYTE_COUNT_ERR,

/*0x00060004*/ ERR_I2C_LOSS_OF_ARBRITRATION,

/*0x00060005*/ ERR_I2C_SLAVE_NOT_ADDRESSED,

/*0x00060006*/ ERR_I2C_LOSS_OF_ARBRITRATION_NAK_BIT,

/*0x00060007*/ ERR_I2C_GENERAL_FAILURE,

/*0x00060008*/ ERR_I2C_REGS_SET_TO_DEFAULT

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}

ErrorCode_t;

23.4.24 I2C Mode

The i2c_get_status() function returns the current status of the I2C engine. The return

codes can be defined as an enum structure:

typedef enum I2C_mode

IDLE,

{

MASTER_SEND,

MASTER_RECEIVE,

SLAVE_SEND,

SLAVE_RECEIVE

}

I2C_MODE_T ;

23.4.25 I2C ROM driver pointer

The I2C ROM driver resides in the address 0x1FFF1FF8. The address must be declared

to allow access to the ROM driver:

#define ROM_DRIVERS_PTR ((ROM *)(*((unsigned int *)0x1FFF1FF8)))

23.5 Functional description

23.5.1 I2C Set-up

Before calling any setup functions in the I2C ROM, the application program is responsible

for doing the following:

1. Enable the clock to the I2C peripheral.

2. Enable the two pins required for the SCL and SDA outputs of the I2C peripheral.

3. Allocate a RAM area for dedicated use of the I2C ROM Driver.

After the I2C block is configured, the I2C ROM driver variables have to be set up:

1. Initialize pointer to the I2C API function table.

2. Declare the PARAM and RESULT struct.

3. Declare Error Code struct.

4. Declare the transmit and receive buffer.

If interrupts are used, then additional driver variables have to be set up:

1. Declare the I2C_CALLBK_ T type.

2. Declare callback functions.

3. Declare I2C ROM Driver ISR within the I2C ISR.

4. Enable I2C interrupt.

23.5.2 I2C Master mode set-up

The I2C ROM Driver support polling and interrupts. In the master mode, 7-bit and 10-bit

addressing are supported. The setup is as follows:

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1. Allocate SRAM for the I2C ROM Driver by making a call to the i2c_get_mem_size()

function.

2. Create the I2C handle by making a call to the i2c_setup() function.

3. Set the I2C operating frequency by making a call to the i2c_set_bitrate() function.

pI2cApi

size_in_bytes

=

ROM_DRIVERS_PTR->pI2CD; //setup I2C function table pointer

pI2cApi->i2c_get_mem_size();

=

i2c_handle

error_code

=

pI2cApi->i2c_setup(LPC_I2C_BASE, (uint32_t *)&I2C_Handle[0] );

pI2cApi->i2c_set_bitrate((I2C_HANDLE_T*)i2c_handle, PCLK_in_Hz,

bps_in_hz);

23.5.3 I2C Slave mode set-up

The I2C ROM Driver support polling and interrupts in the slave mode. In the slave mode,

only 7-bit addressing is supported. The set-up is as follows:

1. Allocate SRAM for the I2C ROM Driver by making a call to the i2c_get_mem_size()

function.

2. Create the I2C handle by making a call to the i2c_setup() function.

3. Set the I2C operating frequency by making a call to the i2c_set_bitrate() function.

4. Set the slave address by making a call to the i2c_set_slave_addr() function.

The I2C ROM driver allows setting up to 4 slave addresses and 4 address masks as well

as possibly enabling the General Call address.

The four slave address bytes are packed into the 4 byte variable. Slave address byte 0 is

the least significant byte and Slave address byte 3 is the most significant byte. The Slave

address mask bytes are ordered the same way in the other 32 bit variable. When in slave

receive mode, all of these addresses (or groups if masks are used) will be monitored for a

match. If the General Call bit (least significant bit of any of the four slave address bytes) is

set, then the General Call address of 0x00 is monitored as well.

ꢂ

ꢀꢁꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂ

ꢊ

ꢋC:0VꢂꢌRR`Vꢍꢍꢂꢀꢂ ꢎꢏꢂ ꢋC:0VꢂꢌRR`Vꢍꢍꢂꢃꢂ ꢎꢏꢂ ꢋC:0VꢂꢌRR`Vꢍꢍꢂꢁꢂ ꢎꢏꢂ ꢋC:0VꢂꢌRR`Vꢍꢍꢂꢊꢂ ꢎꢏꢂ

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Fig 41. I2C slave mode set-up address packing

pI2cApi

size_in_bytes

=

ROM_DRIVERS_PTR->pI2CD; //setup I2C function table pointer

pI2cApi->i2c_get_mem_size();

=

i2c_handle

error_code

=

pI2cApi->i2c_setup(LPC_I2C_BASE, (uint32_t *)&I2C_Handle[0] );

pI2cApi->i2c_set_bitrate((I2C_HANDLE_T*)i2c_handle, PCLK_in_Hz,

bps_in_hz);

error_code

=

pI2cApi->i2c_set_slave_addr((I2C_HANDLE_T*)i2c_handle, slave_addr,

slave_addr_mask)

;

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Chapter 23: LPC800 I2C-bus ROM API

23.5.4 I2C Master Transmit/Receive

The Master mode drivers give the user the choice of either polled (wait for the message to

finish) or interrupt driven routines (non-blocking). Polled routines are recommended for

testing purposes or very simple I2C applications. These routines allow the Master to send

to Slaves with 7-bit or 10-bit addresses.

The following routines are polled routines :

err_code i2c_master_transmit_poll(I2C_HANDLE_T*, I2C_PARAM*, I2C_RESULT*)

err_code i2c_master_receive_poll(I2C_HANDLE_T*, I2C_PARAM*, I2C_RESULT*)

err_code i2c_master_tx_rx_poll (I2C_HANDLE_T*, I2C_PARAM*, I2C_RESULT*)

The following routines are interrupt driven routines:

err_code i2c_master_transmit_intr(I2C_HANDLE_T*, I2C_PARAM*, I2C_RESULT*)

err_code i2c_master_receive_intr(I2C_HANDLE_T*, I2C_PARAM*, I2C_RESULT*)

err_code i2c_master_tx_rx_intr(I2C_HANDLE_T*, I2C_PARAM*, I2C_RESULT*)

Where:

• err_code is the return state of the function. An “0” indicates success. All non-zero

indicates an error. Refer to Error Table.

• I2C_PARM* is a structure with parameters passed to the function. Refer to

Section 23.4.22.

• I2C_RESULT* is a containing the results after the function executes.

To initiate a master mode write/read the I2C_PARAM has to be setup. The I2C_PARAM is

a structure with various variables needed by the I2C ROM Driver to operate correctly. The

structure contains the following:

• Number of bytes to be transmitted.

• Number of bytes to be receive.

• Pointer to the transmit buffer.

• Pointer to the receive buffer.

• Pointer to callback function.

• Stop flag.

The RESULT structure contains the results after the function executes. The structure

contains the following:

• Number of bytes transmitted.

• Number of bytes received.

Remark: The number of bytes transmitted will be updated for i2c_master_transmit_intr()

and i2c_master_transmit_poll(). The number of bytes received will only be update on

i2c_master_receive_poll(), i2c_master_receive_intr(), i2c_master_tx_rx_poll(), and

i2c_master_tx_rx_intr().

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In all the master mode routines, the transmit buffer’s first byte must be the slave address

with the R/W bit set to “0”. To enable a master read, the receive buffer’s first byte must be

the slave address with the R/W bit set to “1”.

The following conditions must be fulfilled to use the I2C driver routines in master mode:

• For 7-bit addressing, the first byte of the send buffer must have the slave address in

the most significant 7 bits and the least significant (R/W) bit = 0. Example: Slave

address 0x53, first byte is 0xA6.

• For 7-bit addressing, the first byte of the receive buffer must have the slave address in

the most significant 7 bits and the least significant (R/W) bit = 1. Example: Slave Addr

0x53, first byte 0xA7.

• For 10-bit address, the first byte of the transmit buffer must have the slave address

most significant 2 bits with the (R/W) bit =0. The second byte must contain the

remaining 8-bit of the slave address.

• For 10-bit address, the first byte of the receive buffer must have the slave address

most significant 2 bits with the (R/W) bit =1. The second byte must contain the

remaining 8-bit of the slave address.

• The number of bytes to be transmitted should include the first byte of the buffer which

is the slave address byte. Example: 2 data bytes + 7-bit slave addr = 3.

• The application program must enable I2C interrupts. When I2C interrupt occurs, the

i2c_isr_handler function must be called from the application program.

When using the interrupt function calls, the callback functions must be define. Upon the

completion of a read/write as specified by the PARAM structure, the callback functions will

be invoked.

23.5.5 I2C Slave Mode Transmit/Receive

In slave mode, polled routines are intended for testing purposes. It is up to the user to

decide whether to use the polled or interrupt driven mode. While operating the Slave

driver in polled mode can be useful for program development and debugging, most

applications will need the interrupt-driven versions of Slave Receive and Transmit in the

final software.

The following routines are polled routines:

err_code i2c_slave_receive_poll(I2C_HANDLE_T*, I2C_PARAM*, I2C_RESULT*)

err_code i2c_slave_transmit_poll(I2C_HANDLE_T*, I2C_PARAM*, I2C_RESULT*)

The following routines are interrupt driven routines:

err_code i2c_slave_receive_intr(I2C_HANDLE_T*, I2C_PARAM*, I2C_RESULT*)

err_code i2c_slave_transmit_intr(I2C_HANDLE_T*, I2C_PARAM*, I2C_RESULT*)

Where:

• err_code is the return state of the function. An 0 indicates success. All non-zero

indicates an error. Refer to the Error Code Table.

• I2C_PARM is a structure with parameters passed to the function. Section 23.4.22.

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• I2C_RESULT is a containing the results after the function executes. Section 23.4.22.

To initiate a master-mode write/read the I2C_PARAM has to be setup. The I2C_PARAM is

a structure with various variables needed by the I2C ROM Driver to operate correctly. The

structure contains the following:

• Number of bytes to be transmitted.

• Number of bytes to be received.

• Pointer to the transmit buffer.

• Pointer to the receive buffer.

• Pointer to callback function.

• Stop flag.

The RESULT structure contains the results after the function executes. The structure

contains the following:

• Number of bytes transmitted.

• Number of bytes received.

Remark: The number of bytes transmitted is updated only for i2c_slave_send_poll() and

i2c_slave_send_intr(). The number of bytes received is updated only for

i2c_slave_receive_poll() and i2c_slave_receive_intr().

To initiate a slave mode communication, the receive function is called. This can be either

the polling or interrupt driven function, i2c_slave_receive_poll() or

i2c_slave_receive_intr(), respectively. The receive buffer should be as large or larger than

any data or command that will be received. If the amount of data exceed the receive buffer

size, an error code will be returned.

In slave-receive mode, the driver receives data until one of the following are true:

• Address matching set in the set_slave_addr() function with the R/W bit set to 1

• STOP or repeated START is received

• An error condition is detected

When using the interrupt function calls, the callback functions must be define. Upon the

completion of a read/write as specified by the PARAM structure, the callback functions will

be invoked.

23.5.6 I2C time-out feature

//timeout: Timeout time value. Specifies the timeout interval value in increments of

// 16 I2C function clocks (Min value is 16).

//

if timeout

= 0, timeout feature is disabled

if timeout != 0, time value is timeout*16 i2c function clock.

ErrorCode_t i2c_set_timeout(I2C_HANDLE_T* h_i2c, uint32_t timeout)

{

I2C_DRIVER_TypeDef *h

(I2C_DRIVER_TypeDef*) h_i2c

if (timeout != 0){

h->i2c_base->TimeOut

;

// declare pointer to i2c structure [handle]

h

=

;

//assign handle pointer address

=

(timeout - 1)<<4;

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// Enable timeout feature

h->i2c_base->CFG |= BI2C_TIMEOUT_EN;

}

else

// disable timeout feature

h->i2c_base->CFG &= ~BI2C_TIMEOUT_EN;

return(LPC_OK)

}//i2c_set_timeout

;

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Chapter 24: LPC800 USART API ROM driver routines

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Preliminary user manual

24.1 How to read this chapter

The USART ROM driver routines are available on all LPC800 parts.

24.2 Features

• Send and receive characters in asynchronus UART mode

• Send and receive multiple characters (line) in asynchronous UART mode

24.3 General description

The UART API handles sending and receiving characters using any of the USART blocks

in asynchronous mode.

Remark: Because all USARTS share a common fractional divider, the uart_init routine

returns the value for the common divider.

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Fig 42. USART driver routines pointer structure

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Chapter 24: LPC800 USART API ROM driver routines

24.4 API description

The UART API contains functions to send and receive characters via any of the USART

blocks.

Table 271. UART API calls

API call

Description

Reference

Table 272

Table 273

Table 274

Table 275

Table 276

Table 277

uint32_t ramsize_in_bytes uart_get_mem_size( void) ;

UART_HANDLE_T* uart_setup(uint32_t base_addr, uint8_t *ram) ;

uint32_t uart_init(UART_HANDLE_T* handle, UART_CONFIG set);

uint8_t uart_get_char(UART_HANDLE_T* handle);

void uart_put_char(UART_HANDLE_T* handle, uint8_t data);

UART get memory size

UART set-up

UART init

UART get character

UART put character

UART get line

uint32_t uart_get_line(UART_HANDLE_T* handle, UART_PARAM_T

param);

uint32_t uart_put_line(UART_HANDLE_T* handle, UART_PARAM_T

param);

UART put line

Table 278

void uart_isr(UART_HANDLE_T* handle);

UART interrupt service routine Table 279

The following structure has to be defined to use the UART API:

typedef struct UARTD_API {

// index of all the uart driver functions

uint32_t (*uart_get_mem_size)(void);

UART_HANDLE_T (*uart_setup)(uint32_t base_addr, uint8_t *ram);

uint32_t (*uart_init)(UART_HANDLE_T handle, UART_CONFIG_T *set);

//--polling functions--//

uint8_t (*uart_get_char)(UART_HANDLE_T handle);

void (*uart_put_char)(UART_HANDLE_T handle, uint8_t data);

uint32_t (*uart_get_line)(UART_HANDLE_T handle, UART_PARAM_T * param);

uint32_t (*uart_put_line)(UART_HANDLE_T handle, UART_PARAM_T * param);

//--interrupt functions--//

void (*uart_isr)(UART_HANDLE_T handle);

} UARTD_API_T

;

// end of structure

24.4.1 UART get memory size

Table 272. uart_get_mem_size

Routine

uart_get_mem_size

Prototype

Input parameter

Return

uint32_t ramsize_in_bytes uart_get_mem_size( void) ;

None.

Memory size in bytes.

Description

Get the memory size needed by one Min UART instance.

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Chapter 24: LPC800 USART API ROM driver routines

24.4.2 UART setup

Table 273. uart_setup

Routine

uart_setup

Prototype

UART_HANDLE_T* uart_setup(uint32_t base_addr, uint8_t *ram) ;

base_addr: Base address of register for this uart block.

Input parameter

ram: Pointer to the memory space for uart instance. The size of the memory

space can be obtained by the uart_get_mem_size function.

Return

The handle to corresponding uart instance.

Description

Setup Min UART instance with provided memory and return the handle to this

instance.

24.4.3 UART init

Table 274. uart_init

Routine

uart_init

Prototype

uint32_t uart_init(UART_HANDLE_T* handle, UART_CONFIG set);

handle: The handle to the uart instance.

Input parameter

set: configuration for uart operation.

Return

Fractional divider value if System clock is not integer multiples of baud rate.

Setup baud rate and operation mode for uart, then enable uart.

Description

24.4.4 UART get character

Table 275. uart_get_char

Routine

uart_get_char

Prototype

Input parameter

Return

uint8_t uart_get_char(UART_HANDLE_T* handle);

handle: The handle to the uart instance.

Received data

Description

Receive one Char from uart. This functions is only returned after Char is

received. In case Echo is enabled, the received data is sent out immediately.

24.4.5 UART put character

Table 276. uart_put_char

Routine

uart_put_char

Prototype

void uart_put_char(UART_HANDLE_T* handle, uint8_t data);

handle: The handle to the uart instance.

data: data to be sent out.

Input parameter

Return

None.

Description

Send one Char through uart. This function is only returned after data is sent.

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Chapter 24: LPC800 USART API ROM driver routines

24.4.6 UART get line

Table 277. uart_get_line

Routine

uart_get_line

Prototype

uint32_t uart_get_line(UART_HANDLE_T* handle, UART_PARAM_T

param);

Input parameter

Return

handle: The handle to the uart instance.

param: Refer to UART_PARAM_T definition.

Error code:

ERR_UART_RECEIVE_ON - UART receive is ongoing.

Receive multiple bytes from UART.

Description

24.4.7 UART put line

Table 278. uart_put_line

Routine

uart_put_line

Prototype

uint32_t uart_put_line(UART_HANDLE_T* handle, UART_PARAM_T

param);

Input parameter

Return

handle: The handle to the uart instance.

param: Refer to UART_PARAM_T definition.

Error code:

ERR_UART_SEND_ON - UART sending is ongoing.

Send string (end with \0) or raw data through UART.

Description

24.4.8 UART interrupt service routine

Table 279. uart_isr

Routine

uart_isr

Prototype

Input parameter

Return

void uart_isr(UART_HANDLE_T* handle);

handle: The handle to the uart instance.

None.

Description

UART interrupt service routine. To use this routine, the corresponding USART

interrupt must be enabled. This function is invoked by the user ISR.

24.4.9 Error codes

Table 280. Error codes

Return code

Error Code

Description

0x0008 0001

ERR_UART_RXD_BUSY =

ERR_UART_BASE+1,

UART receive is busy

0x0008 0002

0x0008 0003

ERR_UART_TXD_BUSY

UART transmit is busy

ERR_UART_OVERRUN_FRA Overrun error, Frame error,

ME_PARITY_NOISE

ERR_UART_UNDERRUN

ERR_UART_PARAM

parity error, RxNoise error

0x0008 0004

0x0008 0005

Underrun error

Parameter error

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Chapter 24: LPC800 USART API ROM driver routines

24.4.10 UART ROM driver variables

24.4.10.1 UART_CONFIG structure

Typdef struct UART_CONFIG {

uint32_t sys_clk_in_hz; // Sytem clock in hz.

uint32_t baudrate_in_hz; // Baudrate in hz

uint8_t config; //bit1:0

// 00: 7 bits length, 01: 8 bits lenght, others: reserved

//bit3:2

// 00: No Parity, 01: reserved, 10: Even, 11: Odd

//bit4

// 0: 1 Stop bit, 1: 2 Stop bits

uint8_t sync_mod; //bit0: 0(Async mode), 1(Sync mode)

//bit1: 0(Un_RXD is sampled on the falling edge of SCLK)

1(Un_RXD is sampled on the rising edge of SCLK)

//

//bit2: 0(Start and stop bits are transmitted as in asynchronous // mode)

// 1(Start and stop bits are not transmitted)

//bit3: 0(the UART is a slave on Sync mode)

// 1(the UART is a master on Sync mode)

uint16_t error_en; //Bit0: OverrunEn, bit1: UnderrunEn, bit2: FrameErrEn,

// bit3: ParityErrEn, bit4: RxNoiseEn

}

24.4.10.2 UART_HANDLE_T

The handle to the instance of the UART driver. Each UART has one handle, so there can

be several handles for up to three UART blocks. This handle is created by Init API and

used by the transfer functions for the corresponding UART block.

typedef void

UART_HANDLE_T

;

// define TYPE for uart handle pointer

24.4.10.3 UART_PARAM_T

typedef struct uart_A { // parms passed to uart driver function

uint8_t buffer ; // The pointer of buffer.

// For uart_get_line function, buffer for receiving data.

// For uart_put_line function, buffer for transmitting data.

// [IN] The size of buffer.

*

uint32_t size;

//[OUT] The number of bytes transmitted/received.

uint16_t transfer_mode ;

// 0x00: For uart_get_line function, transfer without

// termination.

// For uart_put_line function, transfer without termination.

// 0x01: For uart_get_line function, stop transfer when

// <CR><LF> are received.

// For uart_put_line function, transfer is stopped after

// reaching \0. <CR><LF> characters are sent out after that.

// 0x02: For uart_get_line function, stop transfer when <LF>

// is received.

// For uart_put_line function, transfer is stopped after

// reaching \0. A <LF> character is sent out after that.

//0x03: For uart_get_line function, RESERVED.

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// For uart_put_line function, transfer is stopped after

// reaching \0.

uint16_t driver_mode;

//0x00: Polling mode, function is blocked until transfer is

// finished.

// 0x01: Intr mode, function exit immediately, callback function

// is invoked when transfer is finished.

//0x02: RESERVED

UART_CALLBK_T

UART_PARAM_T

callback_func_pt; // callback function

}

;

24.5 Functional description

<tbd>

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Chapter 25: LPC800 Debugging

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Preliminary user manual

25.1 How to read this chapter

The debug functionality is identical for all LPC800 parts.

25.2 Features

• Supports ARM Serial Wire Debug mode.

• Direct debug access to all memories, registers, and peripherals.

• No target resources are required for the debugging session.

• Four breakpoints.

• Two data watchpoints that can also be used as triggers.

• Supports JTAG boundary scan.

• Micro Trace Buffer (MTB) supported.

25.3 General description

Debug functions are integrated into the ARM Cortex-M0+. Serial wire debug functions are

supported. The ARM Cortex-M0+ is configured to support up to four breakpoints and two

watchpoints.

Support for boundary scan and Micro Trace Buffer is available.

25.4 Pin description

The SWD functions are assigned to pins through the switch matrix. The SWD functions

are fixed-pin functions that are enabled through the switch matrix and can only be

assigned to special pins on the package. The SWD functions are enabled by default.

See Section 9.3.2 to enable the analog comparator inputs and the reference voltage input.

Table 281. SWD pin description

Function Type Pin

Description

SWCLK/PIO0_3/ Serial Wire Clock. This pin is the clock for SWD

SWM register Reference

SWCLK

I/O

PINENABLE0 Table 105

TCLK

debug logic when in the Serial Wire Debug mode

(SWD). This pin is pulled up internally.

SWDIO

I/O

SWDIO/PIO0_2/ Serial wire debug data input/output. The SWDIO PINENABLE0 Table 105

TMS

pin is used by an external debug tool to

communicate with and control the LPC800. This pin

is pulled up internally.

The boundary scan mode and the pins needed are selected by hardware (see

Section 25.5.3). There is no access to the boundary scan pins through the switch matrix.

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Table 282. JTAG boundary scan pin description

Function Pin name

Type

Description

TCK

SWCLK/PIO0_3/

I

JTAG Test Clock. This pin is the clock for JTAG boundary scan when the RESET

TCK

pin is LOW.

TMS

SWDIO/PIO0_2/

TMS

I

JTAG Test Mode Select. The TMS pin selects the next state in the TAP state

machine. This pin includes an internal pull-up and is used for JTAG boundary scan

when the RESET pin is LOW.

TDI

PIO0_1/ACMP_I2/ I

CLKIN/TDI

JTAG Test Data In. This is the serial data input for the shift register. This pin

includes an internal pull-up and is used for JTAG boundary scan when the RESET

pin is LOW.

TDO

TRST

PIO0_0/ACMP_I1/ O

TDO

JTAG Test Data Output. This is the serial data output from the shift register. Data

is shifted out of the device on the negative edge of the TCK signal. This pin is used

for JTAG boundary scan when the RESET pin is LOW.

PIO0_4/

I

JTAG Test Reset. The TRST pin can be used to reset the test logic within the

debug logic. This pin includes an internal pull-up and is used for JTAG boundary

scan when the RESET pin is LOW.

WAKEUP/TRST

25.5 Functional description

25.5.1 Debug limitations

It is recommended not to use the debug mode during Deep-sleep or Power-down mode

mode.

During a debugging session, the System Tick Timer is automatically stopped whenever

the CPU is stopped. Other peripherals are not affected.

25.5.2 Debug connections for SWD

For debugging purposes, it is useful to provide access to the ISP entry pin PIO0_1. This

pin can be used to recover the part from configurations which would disable the SWD port

such as improper PLL configuration, reconfiguration of SWD pins, entry into Deep

power-down mode out of reset, etc. This pin can be used for other functions such as

GPIO, but it should not be held LOW on power-up or reset.

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Chapter 25: LPC800 Debugging

4ꢍꢍ

ꢋꢌꢃꢍꢉꢉ

4ꢋꢁꢌꢒ

ꢀꢝꢍꢐꢚ

ꢀꢝꢓꢔꢛ

ꢀꢝꢍꢐꢚ

ꢀꢝꢓꢔꢛ

ꢁꢌꢀꢌꢋ

&ꢀꢁꢀꢋ

ꢏꢑꢍ

ꢙꢐꢚ,-ꢄ

ꢏ&'

ꢐꢀꢙꢈ+&()D

The VTREF pin on the SWD connector enables the debug connector to match the target voltage.

Fig 43. Connecting the SWD pins to a standard SWD connector

25.5.3 Boundary scan

The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM

SWD debug (RESET = HIGH). The ARM SWD debug port is disabled while the

LPC11Uxx is in reset.

To perform boundary scan testing, follow these steps:

1. Erase any user code residing in flash.

2. Power up the part with the RESET pin pulled HIGH externally.

3. Wait for at least 250 s.

4. Pull the RESET pin LOW externally.

5. Perform boundary scan operations.

6. Once the boundary scan operations are completed, assert the TRST pin to enable the

SWD debug mode and release the RESET pin (pull HIGH).

Remark: The JTAG interface cannot be used for debug purposes.

Remark: POR, BOD reset, or a LOW on the TRST pin puts the test TAP controller in the

Test-Logic Reset state. The first TCK clock while RESET = HIGH places the test TAP in

Run-Test Idle mode.

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26.1 Packages

ꢄ

ꢆ

/

ꢇ

ꢖ

>

ꢗ

8

ꢁꢌꢀꢌꢋꢅꢙꢐꢚ,-8

ꢙꢐꢚ,-ꢇꢅꢝꢂꢛꢌꢎꢙꢅꢋꢁꢀꢋ

ꢀꢝꢓꢔꢛꢅꢙꢐꢚ,-/ꢅꢋꢓꢛ

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4

ꢀꢀ

ꢍꢍ

ꢐꢜꢌꢍ

ꢙꢐꢚ,-ꢄꢅꢂꢓꢃꢙ-ꢐꢆꢅꢓꢔꢛꢐꢑꢅꢋꢍꢐ

ꢀꢀꢀꢁꢂꢂꢃꢄꢅꢄ

Fig 44. Pin configuration DIP8 package (LPC810M021FN8)

ꢄ

ꢆ

/

ꢇ

8

ꢗ

>

ꢖ

ꢄꢗ

ꢄ8

ꢄꢇ

ꢄ/

ꢄꢆ

ꢄꢄ

ꢄ,

?

ꢙꢐꢚ,-ꢄ/

ꢙꢐꢚ,-ꢄꢆ

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ꢙꢐꢚ,-ꢗꢅ4ꢍꢍꢓꢃꢙ

ꢙꢐꢚ,->

ꢁꢌꢀꢌꢋꢅꢙꢐꢚ,-8

ꢙꢐꢚ,-ꢇꢅꢝꢂꢛꢌꢎꢙꢅꢋꢁꢀꢋ

ꢀꢝꢓꢔꢛꢅꢙꢐꢚ,-/ꢅꢋꢓꢛ

ꢀꢝꢍꢐꢚꢅꢙꢐꢚ,-ꢆꢅꢋꢃꢀ

ꢙꢐꢚ,-ꢄꢄ

ꢋꢌꢃꢍꢛꢛꢂꢉꢉꢛ ꢐ!ꢛ"

ꢋꢌꢃꢍꢛꢏꢂꢛꢉꢛ ꢐ!ꢛ"

ꢅꢎꢎꢄꢌꢛ"

4

ꢀꢀ

ꢍꢍ

ꢙꢐꢚ,-ꢖꢅ3ꢋꢂꢔꢐꢑ

ꢙꢐꢚ,-?ꢅ3ꢋꢂꢔꢚꢎꢋ

ꢙꢐꢚ,-ꢄ,

ꢙꢐꢚ,-ꢄꢅꢂꢓꢃꢙ-ꢐꢆꢅꢓꢔꢛꢐꢑꢅꢋꢍꢐ

ꢀꢀꢀꢁꢂꢂꢉꢄꢂꢄ

Fig 45. Pin configuration TSSOP16 package

ꢄ

ꢆ,

ꢙꢐꢚ,-ꢄꢇ

ꢙꢐꢚ,-ꢄ>

ꢙꢐꢚ,-ꢄ/

ꢆ

/

ꢄ?

ꢄꢖ

ꢄ>

ꢄꢗ

ꢄ8

ꢄꢇ

ꢄ/

ꢄꢆ

ꢄꢄ

ꢙꢐꢚ,-,ꢅꢂꢓꢃꢙ-ꢐꢄꢅꢋꢍꢚ

ꢙꢐꢚ,-ꢗꢅ4ꢍꢍꢓꢃꢙ

ꢙꢐꢚ,->

ꢙꢐꢚ,-ꢄꢆ

ꢇ

ꢁꢌꢀꢌꢋꢅꢙꢐꢚ,-8

ꢙꢐꢚ,-ꢇꢅꢝꢂꢛꢌꢎꢙꢅꢋꢁꢀꢋ

ꢀꢝꢓꢔꢛꢅꢙꢐꢚ,-/ꢅꢋꢓꢛ

ꢀꢝꢍꢐꢚꢅꢙꢐꢚ,-ꢆꢅꢋꢃꢀ

ꢙꢐꢚ,-ꢄꢄ

8

4

ꢀꢀ

ꢍꢍ

ꢎꢄꢏꢉ

ꢗ

>

ꢙꢐꢚ,-ꢖꢅ3ꢋꢂꢔꢐꢑ

ꢖ

ꢙꢐꢚ,-?ꢅ3ꢋꢂꢔꢚꢎꢋ

ꢙꢐꢚ,-ꢄꢅꢂꢓꢃꢙ-ꢆꢅꢓꢔꢛꢐꢑꢅꢋꢍꢐ

ꢙꢐꢚ,-ꢄ8

?

ꢙꢐꢚ,-ꢄ,

ꢄ,

ꢙꢐꢚ,-ꢄꢗ

ꢀꢀꢀꢁꢂꢂꢉꢄꢃꢆ

Fig 46. Pin configuration SO20 package (LPC812M101FD20)

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Chapter 26: LPC800 Packages and pin description

ꢄ

ꢆ

ꢆ,

ꢄ?

ꢄꢖ

ꢄ>

ꢄꢗ

ꢄ8

ꢄꢇ

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ꢄꢄ

ꢙꢐꢚ,-ꢄ>

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ꢙꢐꢚ,-ꢄꢇ

ꢙꢐꢚ,-,ꢅꢂꢓꢃꢙ-ꢐꢄꢅꢋꢍꢚ

ꢙꢐꢚ,-ꢗꢅ4ꢍꢍꢓꢃꢙ

ꢙꢐꢚ,->

/

ꢙꢐꢚ,-ꢄꢆ

ꢇ

ꢁꢌꢀꢌꢋꢅꢙꢐꢚ,-8

ꢋꢌꢃꢍꢛꢏꢂꢛꢉꢛ ꢐ!ꢏꢉ

ꢅꢎꢎꢄꢌꢏꢉ

8

ꢙꢐꢚ,-ꢇꢅꢝꢂꢛꢌꢎꢙꢅꢋꢁꢀꢋ

ꢀꢝꢓꢔꢛꢅꢙꢐꢚ,-/ꢅꢋꢓꢛ

ꢀꢝꢍꢐꢚꢅꢙꢐꢚ,-ꢆꢅꢋꢃꢀ

ꢙꢐꢚ,-ꢄꢄ

4

ꢀꢀ

ꢍꢍ

ꢗ

>

ꢙꢐꢚ,-ꢖꢅ3ꢋꢂꢔꢐꢑ

ꢖ

ꢙꢐꢚ,-?ꢅ3ꢋꢂꢔꢚꢎꢋ

ꢙꢐꢚ,-ꢄꢅꢂꢓꢃꢙ-ꢐꢆꢅꢓꢔꢛꢐꢑꢅꢋꢍꢐ

ꢙꢐꢚ,-ꢄ8

?

ꢙꢐꢚ,-ꢄ,

ꢄ,

ꢙꢐꢚ,-ꢄꢗ

ꢀꢀꢀꢁꢂꢂꢉꢄꢄꢃ

Fig 47. Pin configuration TSSOP20 package

26.2 Pin description

The pin description table Table 283 shows the pin functions that are fixed to specific pins

on each package. These fixed-pin functions are selectable between the GPIO,

comparator, SWD, and the XTAL pins. By default, the GPIO function is selected except on

pins PIO0_2, PIO0_3, and PIO0_5. JTAG functions are available in boundary scan mode

only.

Movable function for the I2C, USART, SPI, and SCT pin functions can be assigned

through the switch matrix to any pin that is not power or ground in place of the pin’s fixed

functions.

The following exceptions apply:

For full I2C-bus compatibility, assign the I2C functions to the open-drain pins PIO0_11 and

PIO0_10.

Do not assign more than one output to any pin. However, more than one input can be

assigned to a pin.

Pin PIO0_4 triggers a wake-up from Deep power-down mode. If you need to wake up

from Deep power-down mode via an external pin, do not assign any movable function to

this pin.

The JTAG functions TDO, TDI, TCK, TMS, and TRST are selected on pins PIO0_0 to

PIO0_4 by hardware when the part is in boundary scan mode.

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Chapter 26: LPC800 Packages and pin description

Table 283. Pin description table (fixed pins)

Symbol

Type Reset Description

state

[1]

[5]

PIO0_0/ACMP_I1/

TDO

19

12

16

9

8

5

I/O

I; PU PIO0_0 — General purpose digital input/output port 0 pin 0.

In ISP mode, this is the USART0 receive pin U0_RXD.

In boundary scan mode: TDO (Test Data Out).

AI

-

ACMP_I1 — Analog comparator input 1.

PIO0_1/ACMP_I2/

CLKIN/TDI

I/O

I; PU PIO0_1 — General purpose digital input/output pin. ISP entry

pin. A LOW level on this pin during reset starts the ISP command

handler.

In boundary scan mode: TDI (Test Data In).

AI

I

-

ACMP_I2 — Analog comparator input 2.

CLKIN — External clock input.

[2]

[6]

SWDIO/PIO0_2/TMS 7

6

5

4

3

2

I/O

I; PU SWDIO — Serial Wire Debug I/O. SWDIO is enabled by default

on this pin.

In boundary scan mode: TMS (Test Mode Select).

I/O

-

PIO0_2 — General purpose digital input/output pin.

SWCLK/PIO0_3/

TCK

6

5

I; PU SWCLK — Serial Wire Clock. SWCLK is enabled by default on

this pin.

In boundary scan mode: TCK (Test Clock).

I/O

-

PIO0_3 — General purpose digital input/output pin.

PIO0_4/WAKEUP/

TRST

I; PU PIO0_4 — General purpose digital input/output pin.

In ISP mode, this is the USART0 transmit pin U0_TXD.

In boundary scan mode: TRST (Test Reset).

This pin triggers a wake-up from Deep power-down mode. If you

need to wake up from Deep power-down mode via an external

pin, do not assign any movable function to this pin. Pull this pin

HIGH externally to enter Deep power-down mode. Pull this pin

LOW to exit Deep power-down mode. A LOW-going pulse as

short as 50 ns wakes up the part.

[4]

[9]

RESET/PIO0_5

4

3

1

-

I/O

I; PU RESET — External reset input: A LOW-going pulse as short as

50 ns on this pin resets the device, causing I/O ports and

peripherals to take on their default states, and processor

execution to begin at address 0.

I

-

PIO0_5 — General purpose digital input/output pin.

PIO0_6/VDDCMP

18

15

I/O

AI

I; PU PIO0_6 — General purpose digital input/output pin.

-

VDDCMP — Alternate reference voltage for the analog

comparator.

[2]

[8]

PIO0_7

17

14

11

-

I/O

I

I; PU PIO0_7 — General purpose digital input/output pin.

I; PU PIO0_8 — General purpose digital input/output pin.

PIO0_8/XTALIN

-

XTALIN — Input to the oscillator circuit and internal clock

generator circuits. Input voltage must not exceed 1.95 V.

[8]

[3]

PIO0_9/XTALOUT

PIO0_10

13

9

10

8

-

I/O

O

I

I; PU PIO0_9 — General purpose digital input/output pin.

-

XTALOUT — Output from the oscillator circuit.

IA

PIO0_10 — General purpose digital input/output pin. Assign I2C

functions to this pin when true open-drain pins are needed for a

signal compliant with the full I2C specification.

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Chapter 26: LPC800 Packages and pin description

Table 283. Pin description table (fixed pins)

Symbol

Type Reset Description

state

[1]

[3]

PIO0_11

8

7

-

I

IA

PIO0_11 — General purpose digital input/output pin. Assign I2C

functions to this pin when true open-drain pins are needed for a

signal compliant with the full I2C specification.

[2]

[7]

PIO0_12

PIO0_13

PIO0_14

PIO0_15

PIO0_16

PIO0_17

V_DD

3

2

1

-

I/O

-

I; PU PIO0_12 — General purpose digital input/output pin.

I; PU PIO0_13 — General purpose digital input/output pin.

I; PU PIO0_14 — General purpose digital input/output pin.

I; PU PIO0_15 — General purpose digital input/output pin.

I; PU PIO0_16 — General purpose digital input/output pin.

I; PU PIO0_17 — General purpose digital input/output pin.

2

-

20

11

10

1

-

15

16

12

13

6

7

-

3.3 V supply voltage.

Ground.

V_SS

[1] Pin state at reset for default function: I = Input; AI = Analog Input; O = Output; PU = internal pull-up enabled (pins pulled up to full V_DD

level ); IA = inactive, no pull-up/down enabled.

[2] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis; includes

high-current output driver.

[3] True open-drain pin. I²C-bus pins compliant with the I²C-bus specification for I²C standard mode, I²C Fast-mode, and I²C Fast-mode

Plus. Do not use this pad for high-speed applications like the SPI clock.

[4] RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep

power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode.

[5] 5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog input. When

configured as an analog input, the digital section of the pin is disabled, and the pin is not 5 V tolerant.

[6] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis. In Deep

power-down mode, pulling this pin LOW wakes up the chip.

[7] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.

[8] 5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog I/O for the system

oscillator. When configured as an analog I/O, the digital section of the pin is disabled, and the pin is not 5 V tolerant.

[9] Not a 5 V tolerant pin due to special analog functionality. Pin provides standard digital I/O functions with configurable modes,

configurable hysteresis, and analog I/O. When configured as an analog I/O, the digital section of the pin is disabled

Table 284. Movable functions (assign to pins PIO0_0 to PIO_17 through switch matrix)

Function name

U0_TXD

Type

Description

O

I

Transmitter output for USART0.

U0_RXD

U0_RTS

Receiver input for USART0.

O

I

Request To Send output for USART0.

Clear To Send input for USART0.

Serial clock input/output for USART0 in synchronous mode.

Transmitter output for USART1.

U0_CTS

U0_SCLK

U1_TXD

I/O

O

I

U1_RXD

U1_RTS

Receiver input for USART1.

O

I

Request To Send output for USART1.

Clear To Send input for USART1.

Serial clock input/output for USART1 in synchronous mode.

Transmitter output for USART2.

U1_CTS

U1_SCLK

U2_TXD

I/O

O

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Chapter 26: LPC800 Packages and pin description

Table 284. Movable functions (assign to pins PIO0_0 to PIO_17 through switch matrix)

Function name

U2_RXD

Type

I

Description

Receiver input for USART2.

Request To Send output for USART2.

Clear To Send input for USART2.

Serial clock input/output for USART2 in synchronous mode.

Serial clock for SPI0.

Master Out Slave In for SPI0.

Master In Slave Out for SPI0.

Slave select for SPI0.

Serial clock for SPI1.

Master Out Slave In for SPI1.

Master In Slave Out for SPI1.

Slave select for SPI1.

SCT input 0.

U2_RTS

O

U2_CTS

I

U2_SCLK

SPI0_SCK

SPI0_MOSI

SPI0_MISO

SPI0_SSEL

SPI1_SCK

SPI1_MOSI

SPI1_MISO

SPI1_SSEL

CTIN_0

I/O

I

CTIN_1

I

SCT input 1.

CTIN_2

I

SCT input 2.

CTIN_3

I

SCT input 3.

CTOUT_0

CTOUT_1

CTOUT_2

CTOUT_3

I2C0_SCL

O

SCT output 0.

O

SCT output 1.

O

SCT output 2.

O

SCT output 3.

I/O

I²C-bus clock input/output (open-drain if assigned to pin PIO0_10).

High-current sink only if assigned to PIO0_10 and if I²C Fast-mode

Plus is selected in the I/O configuration register.

I2C0_SDA

I/O

I²C-bus data input/output (open-drain if assigned to pin PIO0_11).

High-current sink only if assigned to pin PIO0_11 and if I²C

Fast-mode Plus is selected in the I/O configuration register.

ACMP_O

CLKOUT

O

Analog comparator output.

Clock output.

GPIO_INT_BMAT O

Output of the pattern match engine.

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27.1 Abbreviations

Table 285. Abbreviations

Acronym

AHB

Description

Advanced High-performance Bus

Advanced Peripheral Bus

BrownOut Detection

APB

BOD

GPIO

PLL

General-Purpose Input/Output

Phase-Locked Loop

RC

Resistor-Capacitor

SPI

Serial Peripheral Interface

System Management Bus

Transverse ElectroMagnetic

Universal Asynchronous Receiver/Transmitter

SMBus

TEM

UART

27.2 References

[1] DDI0484B_cortex_m0p_r0p0_trm — ARM Cortex-M0+ Technical Reference

Manual

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Chapter 27: Supplementary information

27.3 Legal information

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

27.3.1Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

27.3.2Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

27.3.3Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

I²C-bus — logo is a trademark of NXP B.V.

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Chapter 27: Supplementary information

27.4 Tables

Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .5

Table 2. Ordering options. . . . . . . . . . . . . . . . . . . . . . . . .5

Table 3. Connection of interrupt sources to the NVIC . .10

Table 4. SYSCON pin description . . . . . . . . . . . . . . . . .15

Table 5. Register overview: System configuration (base

address 0x4004 8000) . . . . . . . . . . . . . . . . . .17

Table 6. System memory remap register

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 26. POR captured PIO status register 0

(PIOPORCAP0, address 0x4004 8100) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 27. IOCON glitch filter clock divider registers 6 to 0

(IOCONCLKDIV[6:0], address 0x4004 8134

(IOCONCLKDIV6) to 0x004 814C

(SYSMEMREMAP, address 0x4004 8000) bit

(IOCONFILTCLKDIV0)) bit description . . . . . . 30

Table 28. BOD control register (BODCTRL, address 0x4004

8150) bit description. . . . . . . . . . . . . . . . . . . . . 30

Table 29. System tick timer calibration register

(SYSTCKCAL, address 0x4004 8154) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 30. IRQ latency register (IRQLATENCY, address

0x4004 8170) bit description . . . . . . . . . . . . . . 32

Table 31. NMI source selection register (NMISRC, address

0x4004 8174) bit description . . . . . . . . . . . . . . 32

Table 32. Pin interrupt select registers (PINTSEL[0:7],

address 0x4004 8178 (PINTSEL0) to 0x4004

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Table 7. Peripheral reset control register (PRESETCTRL,

address 0x4004 8004) bit description. . . . . . . .19

Table 8. System PLL control register (SYSPLLCTRL,

address 0x4004 8008) bit description . . . . . . .21

Table 9. System PLL status register (SYSPLLSTAT,

address 0x4004 800C) bit description . . . . . . .21

Table 10. System oscillator control register (SYSOSCCTRL,

address 0x4004 8020) bit description. . . . . . . .21

Table 11. Watchdog oscillator control register

(WDTOSCCTRL, address 0x4004 8024) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Table 12. System reset status register (SYSRSTSTAT,

address 0x4004 8030) bit description. . . . . . . .23

Table 13. System PLL clock source select register

(SYSPLLCLKSEL, address 0x4004 8040) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Table 14. System PLL clock source update enable register

(SYSPLLCLKUEN, address 0x4004 8044) bit

8194 (PINTSEL7)) bit description . . . . . . . . . . 33

Table 33. Start logic 0 pin wake-up enable register 0

(STARTERP0, address 0x4004 8204) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 34. Start logic 1 interrupt wake-up enable register

(STARTERP1, address 0x4004 8214) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 35. Deep-sleep configuration register

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Table 15. Main clock source select register (MAINCLKSEL,

address 0x4004 8070) bit description. . . . . . . .24

Table 16. Main clock source update enable register

(MAINCLKUEN, address 0x4004 8074) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Table 17. System clock divider register (SYSAHBCLKDIV,

address 0x4004 8078) bit description. . . . . . . .25

Table 18. System clock control register

(SYSAHBCLKCTRL, address 0x4004 8080) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 19. USART clock divider register (UARTCLKDIV,

address 0x4004 8094) bit description. . . . . . . .27

Table 20. CLKOUT clock source select register

(CLKOUTSEL, address 0x4004 80E0) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 21. CLKOUT clock source update enable register

(CLKOUTUEN, address 0x4004 80E4) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 22. CLKOUT clock divider registers (CLKOUTDIV,

address 0x4004 80E8) bit description . . . . . . .28

Table 23. USART fractional generator divider value register

(UARTFRGDIV, address 0x4004 80F0) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Table 24. USART fractional generator multiplier value

register (UARTFRGMULT, address 0x4004 80F4)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . .29

Table 25. External trace buffer command register

(EXTTRACECMD, address 0x4004 80FC) bit

(PDSLEEPCFG, address 0x4004 8230) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 36. Wake-up configuration register (PDAWAKECFG,

address 0x4004 8234) bit description . . . . . . 36

Table 37. Power configuration register (PDRUNCFG,

address 0x4004 8238) bit description . . . . . . 37

Table 38. Device ID register (DEVICE_ID, address 0x4004

83F4) bit description . . . . . . . . . . . . . . . . . . . . 38

Table 39. PLL frequency parameters. . . . . . . . . . . . . . . . 39

Table 40. PLL configuration examples. . . . . . . . . . . . . . . 40

Table 41. Wake-up sources for reduced power modes . . 43

Table 42. Register overview: PMU (base address 0x4002

0000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 43. Power control register (PCON, address 0x4002

0000) bit description . . . . . . . . . . . . . . . . . . . . 44

Table 44. General purpose registers 0 to 3 (GPREG[0:3],

address 0x4002 0004 (GPREG0) to 0x4002 0010

(GPREG3)) bit description . . . . . . . . . . . . . . . 44

Table 45. Deep power down control register (DPDCTRL,

address 0x4002 0014) bit description . . . . . . 45

Table 46. Peripheral configuration in reduced power modes

46

Table 47. Pinout summary. . . . . . . . . . . . . . . . . . . . . . . . 53

Table 48. Register overview: I/O configuration (base

address 0x4004 4000) . . . . . . . . . . . . . . . . . . . 57

Table 49. PIO0_17 register (PIO0_17, address 0x4004

4000) bit description. . . . . . . . . . . . . . . . . . . . . 57

Table 50. PIO0_13 register (PIO0_13, address 0x4004

4004) bit description . . . . . . . . . . . . . . . . . . . . 59

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Chapter 27: Supplementary information

Table 51. PIO0_12 register (PIO0_12, address 0x4004

4008) bit description . . . . . . . . . . . . . . . . . . . .60

Table 52. PIO0_5 register (PIO0_5, address 0x4004 400C)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .61

Table 53. PIO0_4 register (PIO0_4, address 0x4004 4010)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .62

Table 54. PIO0_3 register (PIO0_3, address 0x4004 4014)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .63

Table 55. PIO0_2 register (PIO0_2, address 0x4004 4018)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .64

Table 56. PIO0_11 register (PIO0_11, address 0x4004

401C) bit description. . . . . . . . . . . . . . . . . . . . .65

Table 57. PIO0_10 register (PIO0_10, address 0x4004

4020) bit description . . . . . . . . . . . . . . . . . . . .66

Table 58. PIO0_16 register (PIO0_16, address 0x4004

4024) bit description . . . . . . . . . . . . . . . . . . . .67

Table 59. PIO0_15 register (PIO0_15, address 0x4004

4028) bit description . . . . . . . . . . . . . . . . . . . .68

Table 60. PIO0_1 register (PIO0_1, address 0x4004 402C)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .69

Table 61. PIO0_9 register (PIO0_9, address 0x4004 4034)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .70

Table 62. PIO0_8 register (PIO0_8, address 0x4004 4038)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .71

Table 63. PIO0_7 register (PIO0_7, address 0x4004 403C)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .72

Table 64. PIO0_6 register (PIO0_6, address 0x4004 4040)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .73

Table 65. PIO0_0 register (PIO0_0, address 0x4004 4044)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .74

Table 66. PIO0_14 register (PIO0_14, address 0x4004

4048) bit description . . . . . . . . . . . . . . . . . . . .75

Table 67. GPIO pins available . . . . . . . . . . . . . . . . . . . . .76

Table 68. Register overview: GPIO port (base address

0xA000 0000) . . . . . . . . . . . . . . . . . . . . . . . . . .77

Table 69. GPIO port 0 byte pin registers (B[0:17], addresses

0xA000 0000 (B0) to 0xA000 0012 (B17)) bit

Table 80. Pin interrupt mode register (ISEL, address

0xA000 4000) bit description . . . . . . . . . . . . . 86

Table 81. Pin interrupt level or rising edge interrupt enable

register (IENR, address 0xA000 4004) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 82. Pin interrupt level or rising edge interrupt set

register (SIENR, address 0xA000 4008) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 83. Pin interrupt level or rising edge interrupt clear

register (CIENR, address 0xA000 400C) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 84. Pin interrupt active level or falling edge interrupt

enable register (IENF, address 0xA000 4010) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 85. Pin interrupt active level or falling edge interrupt

set register (SIENF, address 0xA000 4014) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 86. Pin interrupt active level or falling edge interrupt

clear register (CIENF, address 0xA000 4018) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 87. Pin interrupt rising edge register (RISE, address

0xA000 401C) bit description . . . . . . . . . . . . . 89

Table 88. Pin interrupt falling edge register (FALL, address

0xA000 4020) bit description . . . . . . . . . . . . . 90

Table 89. Pin interrupt status register (IST, address 0xA000

4024) bit description . . . . . . . . . . . . . . . . . . . . 90

Table 90. Pattern match interrupt control register (PMCTRL,

address 0x4004 C028)

bit description. . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 91. Pattern match bit-slice source register (PMSRC,

address 0x4004 C02C)

bit description. . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 92. Pattern match bit slice configuration register

(PMCFG, address 0x4004 C030) bit description

94

Table 93. Pin interrupt registers for edge- and

level-sensitive pins . . . . . . . . . . . . . . . . . . . . . 98

Table 94. Movable functions (assign to pins PIO0_0 to

PIO_17 through switch matrix). . . . . . . . . . . . 102

Table 95. Register overview: Switch matrix (base address

0x4000 C000) . . . . . . . . . . . . . . . . . . . . . . . 104

Table 96. Pin assign register 0 (PINASSIGN0, address

0x4000 C000) bit description . . . . . . . . . . . . . 105

Table 97. Pin assign register 1 (PINASSIGN1, address

0x4000 C004) bit description . . . . . . . . . . . . . 105

Table 98. Pin assign register 2 (PINASSIGN2, address

0x4000 C008) bit description . . . . . . . . . . . . . 106

Table 99. Pin assign register 3 (PINASSIGN3, address

0x4000 C00C) bit description. . . . . . . . . . . . . 106

Table 100. Pin assign register 4 (PINASSIGN4, address

0x4000 C010) bit description . . . . . . . . . . . . . 106

Table 101. Pin assign register 5 (PINASSIGN5, address

0x4000 C014) bit description . . . . . . . . . . . . . 107

Table 102. Pin assign register 6 (PINASSIGN6, address

0x4000 C018) bit description . . . . . . . . . . . . . 107

Table 103. Pin assign register 7 (PINASSIGN7, address

0x4000 C01C) bit description. . . . . . . . . . . . . 108

Table 104. Pin assign register 8 (PINASSIGN8, address

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Table 70. GPIO port 0 word pin registers (W[0:17],

addresses 0xA000 1000 (W0) to 0x5000 1048

(W17)) bit description . . . . . . . . . . . . . . . . . . . .78

Table 71. GPIO direction port 0 register (DIR0, address

0xA000 2000) bit description . . . . . . . . . . . . . .78

Table 72. GPIO mask port 0 register (MASK0, address

0xA000 2080) bit description . . . . . . . . . . . . . .78

Table 73. GPIO port 0 pin register (PIN0, address 0xA000

2100) bit description . . . . . . . . . . . . . . . . . . . . .79

Table 74. GPIO masked port 0 pin register (MPIN0, address

0xA000 2180) bit description . . . . . . . . . . . . . .79

Table 75. GPIO set port 0 register (SET0, address 0xA000

2200) bit description . . . . . . . . . . . . . . . . . . . . .79

Table 76. GPIO clear port 0 register (CLR0, address 0xA000

2280) bit description . . . . . . . . . . . . . . . . . . . . .80

Table 77. GPIO toggle port 0 register (NOT0, address

0xA000 2300) bit description . . . . . . . . . . . . . .80

Table 78. SCT pin description . . . . . . . . . . . . . . . . . . . . .83

Table 79. Register overview: Pin interrupts/pattern match

engine (base address: 0xA000 4000). . . . . . . .86

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UM10601

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Chapter 27: Supplementary information

0x4000 C020) bit description . . . . . . . . . . . . .108

(EV[0:5]_STATE, addresses 0x5000 4300

(EV0_STATE) to 0x5000 4328 (EV5_STATE)) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 130. SCT event control register 0 to 5 (EV[0:5]_CTRL,

address 0x5000 4304 (EV0_CTRL) to 0x5000

432C (EV5_CTRL)) bit description . . . . . . . . 129

Table 131. SCT output set register (OUT[0:3]_SET, address

0x5000 4500 (OUT0_SET) to 0x5000 4518

(OUT3_SET)) bit description . . . . . . . . . . . . . 131

Table 132. SCT output clear register (OUT[0:3]_CLR,

address 0x5000 0504 (OUT0_CLR) to 0x5000

051C (OUT3_CLR)) bit description . . . . . . . . 131

Table 133. Event conditions . . . . . . . . . . . . . . . . . . . . . . 134

Table 134. Register overview: MRT (base address 0x4000

4000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Table 135. Time interval register (INTVAL[0:3], address

0x4000 4000 (INTVAL0) to 0x4000 4030

(INTVAL3)) bit description . . . . . . . . . . . . . . . 142

Table 136. Timer register (TIMER[0:3], address 0x4000 4004

(TIMER0) to 0x4000 4034 (TIMER3)) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Table 137. Control register (CTRL[0:3], address 0x4000

4008 (CTRL0) to 0x4000 4038 (CTRL3)) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Table 138. Status register (STAT[0:3], address 0x4000 400C

(STAT0) to 0x4000 403C (STAT3)) bit description

144

Table 105. Pin enable register 0 (PINENABLE0, address

0x4000 C1C0) bit description . . . . . . . . . . . . .108

Table 106. SCT pin description . . . . . . . . . . . . . . . . . . . .112

Table 107. Register overview: State Configurable Timer

(base address 0x5000 4000) . . . . . . . . . . . .115

Table 108. SCT configuration register (CONFIG, address

0x5000 4000) bit description . . . . . . . . . . . .117

Table 109. SCT control register (CTRL, address 0x5000

4004) bit description . . . . . . . . . . . . . . . . . . . .118

Table 110. SCT limit register (LIMIT, address 0x5000 4008)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .120

Table 111. SCT halt condition register (HALT, address

0x5004 400C) bit description . . . . . . . . . . . .120

Table 112. SCT stop condition register (STOP, address

0x5000 4010) bit description . . . . . . . . . . . .121

Table 113. SCT start condition register (START, address

0x5000 4014) bit description . . . . . . . . . . . .121

Table 114. SCT counter register (COUNT, address 0x5000

4040) bit description . . . . . . . . . . . . . . . . . . . .122

Table 115. SCT state register (STATE, address 0x5000

4044) bit description . . . . . . . . . . . . . . . . . . . .122

Table 116. SCT input register (INPUT, address 0x5000

4048) bit description . . . . . . . . . . . . . . . . . . . .123

Table 117. SCT match/capture registers mode register

(REGMODE, address 0x5000 404C) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . .124

Table 118. SCT output register (OUTPUT, address 0x5000

4050) bit description . . . . . . . . . . . . . . . . . . . .124

Table 119. SCT bidirectional output control register

(OUTPUTDIRCTRL, address 0x5000 4054) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . .124

Table 120. SCT conflict resolution register (RES, address

0x5000 4058) bit description . . . . . . . . . . . .125

Table 121. SCT flag enable register (EVEN, address 0x5000

40F0) bit description. . . . . . . . . . . . . . . . . . . .126

Table 122. SCT event flag register (EVFLAG, address

0x5000 40F4) bit description . . . . . . . . . . . . .126

Table 123. SCT conflict enable register (CONEN, address

0x5000 40F8) bit description . . . . . . . . . . . . .126

Table 124. SCT conflict flag register (CONFLAG, address

0x5000 40FC) bit description . . . . . . . . . . . . .127

Table 125. SCT match registers 0 to 4 (MATCH[0:4],

address 0x5000 4100 (MATCH0) to 0x5000 4110

(MATCH4)) bit description (REGMODEn bit = 0) .

127

Table 139. Idle channel register (IDLE_CH, address 0x4000

40F4) bit description . . . . . . . . . . . . . . . . . . . 144

Table 140. Global interrupt flag register (IRQ_FLAG, address

0x4000 40F8) bit description . . . . . . . . . . . . . 145

Table 141. Register overview: Watchdog timer (base

address 0x4000 4000) . . . . . . . . . . . . . . . . . . 150

Table 142. Watchdog mode register (MOD - 0x4000 4000)

bit description. . . . . . . . . . . . . . . . . . . . . . . . . 150

Table 143. Watchdog operating modes selection . . . . . . 152

Table 144. Watchdog Timer Constant register (TC - 0x4000

4004) bit description. . . . . . . . . . . . . . . . . . . . 152

Table 145. Watchdog Feed register (FEED - 0x4000 4008)

bit description. . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 146. Watchdog Timer Value register (TV - 0x4000

400C) bit description . . . . . . . . . . . . . . . . . . . 153

Table 147. Watchdog Timer Warning Interrupt register

(WARNINT - 0x4000 4014) bit description. . . 153

Table 148. Watchdog Timer Window register (WINDOW -

0x4000 4018) bit description . . . . . . . . . . . . . 154

Table 149. Analog comparator pin description . . . . . . . . 156

Table 150. Register overview: Analog comparator (base

address 0x4002 4000) . . . . . . . . . . . . . . . . . . 158

Table 151. Comparator control register (CTRL, address

0x4002 4000) bit description . . . . . . . . . . . . . 158

Table 152. Voltage ladder register (LAD, address 0x4002

4004) bit description. . . . . . . . . . . . . . . . . . . . 160

Table 153. Register overview: WKT (base address 0x4000

8000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Table 154. Control register (CTRL, address 0x4000 8000) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Table 155. Counter register (COUNT, address 0x4000 800C)

Table 126. SCT capture registers 0 to 4 (CAP[0:4], address

0x5000 4100 (CAP0) to 0x5000 4110 (CAP4)) bit

description (REGMODEn bit = 1) . . . . . . . . . .128

Table 127. SCT match reload registers 0 to 4

(MATCHREL[0:4], address 0x5000 4200

(MATCHREL0) to 0x5000 4210 (MATCHREL4) bit

description (REGMODEn bit = 0) . . . . . . . . . .128

Table 128. SCT capture control registers 0 to 4

(CAPCTRL[0:4], address 0x5000 4200

(CAPCTRL0) to 0x5000 4210 (CAPCTRL4)) bit

description (REGMODEn bit = 1) . . . . . . . . . .128

Table 129. SCT event state mask registers 0 to 5

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Rev. 1.0 — 7 November 2012

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UM10601

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Chapter 27: Supplementary information

bit description . . . . . . . . . . . . . . . . . . . . . . . . .163

0010) bit description. . . . . . . . . . . . . . . . . . . . 196

Table 177. I²C Clock Divider register (DIV, address 0x4005

0014) bit description. . . . . . . . . . . . . . . . . . . . 196

Table 178. I²C Interrupt Status register (INTSTAT, address

0x4005 0018) bit description . . . . . . . . . . . . . 197

Table 179. Master Control register (MSTCTL, address

0x4005 0020) bit description . . . . . . . . . . . . . 197

Table 180. Master Time register (MSTTIME, address 0x4005

0024) bit description . . . . . . . . . . . . . . . . . . . 198

Table 181. Master Data register (MSTDAT, address 0x4005

0028) bit description. . . . . . . . . . . . . . . . . . . . 199

Table 182. Slave Control register (SLVCTL, address 0x4005

0040) bit description. . . . . . . . . . . . . . . . . . . . 200

Table 183. Slave Data register (SLVDAT, address 0x4005

0044) bit description. . . . . . . . . . . . . . . . . . . . 200

Table 184. Slave Address registers (SLVADR[0:3]- address

0x4005 0048 (SLVADR0) to 0x4005 0054

Table 156. USART pin description. . . . . . . . . . . . . . . . . .167

Table 157: Register overview: USART (base address

0x4006 4000 (USART0), 0x4006 8000 (USART1),

0x4006 C000 (USART2)) . . . . . . . . . . . . . . . .170

Table 158. USART Configuration register (CFG, address

0x4006 4000 (USART0), 0x4006 8000 (USART1),

0x4006 C000 (USART2)) bit description . . .171

Table 159. USART Control register (CTRL, address 0x4006

4004 (USART0), 0x4006 8004 (USART1), 0x4006

C004 (USART2)) bit description . . . . . . . . . . .173

Table 160. USART Status register (STAT, address 0x4006

4008 (USART0), 0x4006 8008 (USART1), 0x4006

C008(USART2)) bit description . . . . . . . . . . .174

Table 161. USART Interrupt Enable read and set register

(INTENSET, address 0x4006 400C(USART0),

0x4006 800C (USART1), 0x4006

C00C(USART2)) bit description . . . . . . . . . .175

Table 162. USART Interrupt Enable clear register

(INTENCLR, address 0x4006 4010(USART0),

0x4006 8010 (USART1), 0x4006 C010(USART2))

bit description . . . . . . . . . . . . . . . . . . . . . . . .176

Table 163. USART Receiver Data register (RXDATA,

address 0x4006 4014 (USART0), 0x4006 8014

(USART1), 0x4006 C014 (USART2)) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . .177

Table 164. USART Receiver Data with Status register

(RXDATASTAT, address 0x4006 4018 (USART0),

0x4006 8018 (USART1), 0x4006 C018

(SLVADR3)) bit description . . . . . . . . . . . . . . 201

Table 185. Slave address Qualifier 0 register (SLVQUAL0,

address 0x4005 0058) bit description . . . . . . 202

Table 186. Monitor data register (MONRXDAT, address

0x4005 0080) bit description . . . . . . . . . . . . . 202

Table 187: SPI Pin Description . . . . . . . . . . . . . . . . . . . . 208

Table 188. Register overview: SPI (base address 0x4005

8000 (SPI0) and 0x4008 C000 (SPI1)) . . . . . 209

Table 189. SPI Configuration register (CFG, addresses

0x4005 8000 (SPI0) , 0x4005 C000 (SPI1)) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Table 190. SPI Delay register (DLY, addresses 0x4005 8004

(SPI0) , 0x4005 C004 (SPI1)) bit description. 212

Table 191. SPI Status register (STAT, addresses 0x4005

8008 (SPI0) , 0x4005 C008 (SPI1)) bit description

213

(USART2)) bit description. . . . . . . . . . . . . . . .177

Table 165. USART Transmitter Data Register (TXDATA,

address 0x4006 401C (USART0), 0x4006 801C

(USART1), 0x4006 C01C (USART2)) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . .178

Table 166. USART Baud Rate Generator register (BRG,

address 0x4006 4020 (USART0), 0x4006 8020

(USART1), 0x4006 C020 (USART2)) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . .179

Table 167. USART Interrupt Status register (INTSTAT,

address 0x4006 4024 (USART0), 0x4006 8024

(USART1), 0x4006 C024(USART2)) bit

Table 192. SPI Interrupt Enable read and Set register

(INTENSET, addresses 0x4005 800C (SPI0) ,

0x4005 C00C (SPI1)) bit description . . . . . . . 214

Table 193. SPI Interrupt Enable clear register (INTENCLR,

addresses 0x4005 8010 (SPI0) , 0x4005 C010

(SPI1)) bit description . . . . . . . . . . . . . . . . . . 215

Table 194. SPI Receiver Data register (RXDAT, addresses

0x4005 8014 (SPI0) , 0x4005 C014 (SPI1)) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . .179

Table 168. I2C-bus pin description . . . . . . . . . . . . . . . . .184

Table 169: Register overview: I2C (base address 0x4005

0000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187

Table 170. I2C Configuration register (CFG, address 0x4005

0000) bit description . . . . . . . . . . . . . . . . . . . .187

Table 171. I²C Status register (STAT, address 0x4005 0004)

bit description . . . . . . . . . . . . . . . . . . . . . . . .189

Table 172: Master function state codes (MSTSTATE). . .192

Table 173: Slave function state codes (SLVSTATE) . . . .192

Table 174. Interrupt Enable Set and read register

(INTENSET, address 0x4005 0008) bit description

193

description . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

Table 195. SPI Transmitter Data and Control register

(TXDATCTL, addresses 0x4005 8018 (SPI0) ,

0x4005 C018 (SPI1)) bit description . . . . . . . 216

Table 196. SPI Transmitter Data Register (TXDAT,

addresses 0x4005 801ST (SPI0) , 0x4005 C00C

(SPI1)) bit description . . . . . . . . . . . . . . . . . . 217

Table 197. SPI Transmitter Control register (TXCTL,

addresses 0x4005 8020 (SPI0) , 0x4005 C020

(SPI1)) bit description . . . . . . . . . . . . . . . . . . 218

Table 198. SPI Divider register (DIV, addresses 0x4005 8024

(SPI0) , 0x4005 C024(SPI1)) bit description . 218

Table 199. SPI Interrupt Status register (INTSTAT, addresses

0x4005 8028 (SPI0) , 0x4005 C028 (SPI1)) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Table 200: SPI mode summary. . . . . . . . . . . . . . . . . . . . 220

Table 201. Register overview: CRC engine (base address

Table 175. Interrupt Enable Clear register (INTENCLR,

address 0x4005 000C) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . .194

Table 176. time-out register (TIMEOUT, address 0x4005

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0x5000 0000) . . . . . . . . . . . . . . . . . . . . . . . . .228

Table 202. CRC mode register (MODE, address 0x5000

0000) bit description . . . . . . . . . . . . . . . . . . . .229

Table 203. CRC seed register (SEED, address 0x5000

0004) bit description . . . . . . . . . . . . . . . . . . . .229

Table 204. CRC checksum register (SUM, address 0x5000

0008) bit description . . . . . . . . . . . . . . . . . . . .229

Table 205. CRC data register (WR_DATA, address 0x5000

0008) bit description . . . . . . . . . . . . . . . . . . . .230

Table 206. Register overview: FMC (base address 0x4004

0000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232

Table 207. Flash configuration register (FLASHCFG,

address 0x4003 C010) bit description . . . . . .233

Table 208. Flash Module Signature Start register

(FMSSTART - 0x4003 C020) bit description .233

Table 209. Flash Module Signature Stop register (FMSSTOP

- 0x4003 C024) bit description . . . . . . . . . . . .233

Table 210. FMSW0 register bit description (FMSW0,

address: 0x4003 C02C) . . . . . . . . . . . . . . . . .234

Table 211. API calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237

Table 212. LPC800 flash configurations . . . . . . . . . . . . .240

Table 213. LPC800 flash configuration . . . . . . . . . . . . . .240

Table 214. Code Read Protection options. . . . . . . . . . . .242

Table 215. Code Read Protection hardware/software

interaction. . . . . . . . . . . . . . . . . . . . . . . . . . . .242

Table 244. IAP Erase page command . . . . . . . . . . . . . . 256

Table 245. IAP Status Codes Summary . . . . . . . . . . . . . 256

Table 246. Memory mapping in debug mode . . . . . . . . . 258

Table 247. Power profile API calls . . . . . . . . . . . . . . . . . 261

Table 248. set_pll routine . . . . . . . . . . . . . . . . . . . . . . . . 261

Table 249. set_power routine . . . . . . . . . . . . . . . . . . . . . 264

Table 250. I2C API calls . . . . . . . . . . . . . . . . . . . . . . . . . 269

Table 251. ISR handler . . . . . . . . . . . . . . . . . . . . . . . . . . 271

Table 252. I2C Master Transmit Polling . . . . . . . . . . . . . 271

Table 253. I2C Master Receive Polling . . . . . . . . . . . . . 271

Table 254. I2C Master Transmit and Receive Polling. . . 272

Table 255. I2C Master Transmit Interrupt . . . . . . . . . . . . 272

Table 256. I2C Master Receive Interrupt . . . . . . . . . . . . 272

Table 257. I2C Master Transmit Receive Interrupt . . . . . 273

Table 258. I2C Slave Receive Polling. . . . . . . . . . . . . . . 273

Table 259. I2C Slave Transmit Polling . . . . . . . . . . . . . . 273

Table 260. I2C Slave Receive Interrupt . . . . . . . . . . . . . 274

Table 261. I2C Slave Transmit Interrupt . . . . . . . . . . . . . 274

Table 262. I2C Set Slave Address . . . . . . . . . . . . . . . . . 274

Table 263. I2C Get Memory Size . . . . . . . . . . . . . . . . . . 274

Table 264. I2C Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

Table 265. I2C Set Bit Rate . . . . . . . . . . . . . . . . . . . . . . 275

Table 266. I2C Get Firmware Version. . . . . . . . . . . . . . . 275

Table 267. I2C Get Status . . . . . . . . . . . . . . . . . . . . . . . 275

Table 268. I2C time-out value. . . . . . . . . . . . . . . . . . . . . 276

Table 269. Error codes . . . . . . . . . . . . . . . . . . . . . . . . . . 276

Table 270. I2C Status code. . . . . . . . . . . . . . . . . . . . . . . 276

Table 271. UART API calls . . . . . . . . . . . . . . . . . . . . . . . 285

Table 272. uart_get_mem_size. . . . . . . . . . . . . . . . . . . . 285

Table 273. uart_setup . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

Table 274. uart_init . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

Table 275. uart_get_char . . . . . . . . . . . . . . . . . . . . . . . . 286

Table 276. uart_put_char . . . . . . . . . . . . . . . . . . . . . . . . 286

Table 277. uart_get_line . . . . . . . . . . . . . . . . . . . . . . . . . 287

Table 278. uart_put_line . . . . . . . . . . . . . . . . . . . . . . . . . 287

Table 279. uart_isr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

Table 280. Error codes . . . . . . . . . . . . . . . . . . . . . . . . . . 287

Table 281. SWD pin description . . . . . . . . . . . . . . . . . . . 290

Table 282. JTAG boundary scan pin description. . . . . . . 291

Table 283. Pin description table (fixed pins) . . . . . . . . . . 295

Table 284. Movable functions (assign to pins PIO0_0 to

PIO_17 through switch matrix). . . . . . . . . . . . 296

Table 216. ISP commands allowed for different CRP levels .

243

Table 217. UART ISP command summary . . . . . . . . . . .244

Table 218. UART ISP Unlock command . . . . . . . . . . . . .244

Table 219. UART ISP Set Baud Rate command . . . . . . .244

Table 220. UART ISP Echo command . . . . . . . . . . . . . .245

Table 221. UART ISP Write to RAM command . . . . . . . .245

Table 222. UART ISP Read Memory command . . . . . . .246

Table 223. UART ISP Prepare sector(s) for write operation

command . . . . . . . . . . . . . . . . . . . . . . . . . . . .246

Table 224. UART ISP Copy RAM to flash command. . . .247

Table 225. UART ISP Go command . . . . . . . . . . . . . . . .247

Table 226. UART ISP Erase sector command . . . . . . . .248

Table 227. UART ISP Blank check sector command . . .248

Table 228. UART ISP Read Part Identification command248

Table 229. Part identification numbers . . . . . . . . . . . . . .249

Table 230. UART ISP Read Boot Code version number

command . . . . . . . . . . . . . . . . . . . . . . . . . . . .249

Table 285. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . 298

Table 231. UART ISP Compare command . . . . . . . . . . .249

Table 232. UART ISP ReadUID command . . . . . . . . . . .249

Table 233. UART ISP Return Codes Summary. . . . . . . .250

Table 234. IAP Command Summary. . . . . . . . . . . . . . . .252

Table 235. IAP Prepare sector(s) for write operation

command . . . . . . . . . . . . . . . . . . . . . . . . . . . .252

Table 236. IAP Copy RAM to flash command . . . . . . . . .253

Table 237. IAP Erase Sector(s) command . . . . . . . . . . .254

Table 238. IAP Blank check sector(s) command. . . . . . .254

Table 239. IAP Read Part Identification command . . . . .254

Table 240. IAP Read Boot Code version number command.

255

Table 241. IAP Compare command. . . . . . . . . . . . . . . . .255

Table 242. IAP Reinvoke ISP . . . . . . . . . . . . . . . . . . . . .256

Table 243. IAP ReadUID command. . . . . . . . . . . . . . . . .256

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Chapter 27: Supplementary information

27.5 Figures

Fig 1. LPC800 block diagram . . . . . . . . . . . . . . . . . . . . .6

Fig 2. LPC800 Memory mapping. . . . . . . . . . . . . . . . . . .9

Fig 3. LPC800 clock generation. . . . . . . . . . . . . . . . . . .16

Fig 4. System PLL block diagram . . . . . . . . . . . . . . . . .38

Fig 5. Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . .54

Fig 6. Pattern match bit slice . . . . . . . . . . . . . . . . . . . . .85

Fig 7. Example: Connect function U0_RXD and U0_TXD

to pins 8 and 14 on the SO20 package . . . . . . .101

Fig 8. SCT block diagram . . . . . . . . . . . . . . . . . . . . . . 113

Fig 9. SCT counter and select logic. . . . . . . . . . . . . . .114

Fig 10. Match logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

Fig 11. Capture logic . . . . . . . . . . . . . . . . . . . . . . . . . . .132

Fig 12. Event selection . . . . . . . . . . . . . . . . . . . . . . . . .133

Fig 13. Output slice i . . . . . . . . . . . . . . . . . . . . . . . . . . .133

Fig 14. SCT interrupt generation . . . . . . . . . . . . . . . . . .133

Fig 15. MRT block diagram . . . . . . . . . . . . . . . . . . . . . .140

Fig 16. Windowed Watchdog timer block diagram. . . . .148

Fig 17. Early watchdog feed with windowed mode enabled

154

Fig 18. Correct watchdog feed with windowed mode

enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154

Fig 19. Watchdog warning interrupt. . . . . . . . . . . . . . . .154

Fig 20. Comparator block diagram. . . . . . . . . . . . . . . . .157

Fig 21. USART clocking. . . . . . . . . . . . . . . . . . . . . . . . .166

Fig 22. USART block diagram . . . . . . . . . . . . . . . . . . . .169

Fig 23. Hardware flow control using RTS and CTS . . . .182

Fig 24. I2C clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . .183

Fig 25. I2C block diagram . . . . . . . . . . . . . . . . . . . . . . .185

Fig 26. SPI clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . .206

Fig 27. SPI block diagram . . . . . . . . . . . . . . . . . . . . . . .209

Fig 28. Basic SPI operating modes . . . . . . . . . . . . . . . .220

Fig 29. Pre_delay and Post_delay. . . . . . . . . . . . . . . . .221

Fig 30. Frame_delay . . . . . . . . . . . . . . . . . . . . . . . . . . .222

Fig 31. Transfer_delay. . . . . . . . . . . . . . . . . . . . . . . . . .223

Fig 32. Examples of data stalls . . . . . . . . . . . . . . . . . . .226

Fig 33. CRC block diagram . . . . . . . . . . . . . . . . . . . . . .228

Fig 34. Boot ROM structure. . . . . . . . . . . . . . . . . . . . . .237

Fig 35. Boot process flowchart . . . . . . . . . . . . . . . . . . .239

Fig 36. IAP parameter passing . . . . . . . . . . . . . . . . . . .252

Fig 37. Power profiles pointer structure . . . . . . . . . . . . .260

Fig 38. LPC800 clock configuration for power API use .260

Fig 39. Power profiles usage . . . . . . . . . . . . . . . . . . . . .264

Fig 40. I2C-bus driver routines pointer structure . . . . . .269

Fig 41. I2C slave mode set-up address packing . . . . . .279

Fig 42. USART driver routines pointer structure . . . . . .284

Fig 43. Connecting the SWD pins to a standard SWD

connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292

Fig 44. Pin configuration DIP8 package (LPC810M021FN8)

293

Fig 45. Pin configuration TSSOP16 package . . . . . . . .293

Fig 46. Pin configuration SO20 package

(LPC812M101FD20) . . . . . . . . . . . . . . . . . . . . .293

Fig 47. Pin configuration TSSOP20 package . . . . . . . .294

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Chapter 27: Supplementary information

27.6 Contents

Chapter 1: LPC800 Introductory information

1.1

1.2

1.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Ordering information. . . . . . . . . . . . . . . . . . . . . 5

1.4

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 6

General description . . . . . . . . . . . . . . . . . . . . . 7

ARM Cortex-M0+ core configuration . . . . . . . . 7

1.5

1.5.1

Chapter 2: LPC800 Memory mapping

2.1

2.2

How to read this chapter. . . . . . . . . . . . . . . . . . 8

General description. . . . . . . . . . . . . . . . . . . . . . 8

2.2.1

2.2.2

Memory mapping . . . . . . . . . . . . . . . . . . . . . . . 9

Micro Trace Buffer (MTB). . . . . . . . . . . . . . . . . 9

Chapter 3: LPC800 Nested Vectored Interrupt Controller (NVIC)

3.1

3.2

How to read this chapter. . . . . . . . . . . . . . . . . 10

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.3

3.3.1

General description . . . . . . . . . . . . . . . . . . . . 10

Interrupt sources . . . . . . . . . . . . . . . . . . . . . . 10

Chapter 4: LPC800 System configuration (SYSCON)

4.1

4.2

How to read this chapter. . . . . . . . . . . . . . . . . 13

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.6.17

4.6.18

CLKOUT clock divider register. . . . . . . . . . . . 28

USART fractional generator divider value register

28

USART fractional generator multiplier value

register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

External trace buffer command register . . . . 29

POR captured PIO status register 0 . . . . . . . 30

IOCON glitch filter clock divider registers 6 to 0 .

30

BOD control register . . . . . . . . . . . . . . . . . . . 30

System tick counter calibration register . . . . . 31

IRQ latency register . . . . . . . . . . . . . . . . . . . . 31

NMI source selection register . . . . . . . . . . . . 32

Pin interrupt select registers . . . . . . . . . . . . . 32

Start logic 0 pin wake-up enable register . . . 33

Start logic 1 interrupt wake-up enable register 34

Deep-sleep mode configuration register . . . . 35

Wake-up configuration register . . . . . . . . . . . 35

Power configuration register . . . . . . . . . . . . . 36

Device ID register . . . . . . . . . . . . . . . . . . . . . 37

4.3

Basic configuration . . . . . . . . . . . . . . . . . . . . . 13

Set up the PLL . . . . . . . . . . . . . . . . . . . . . . . . 13

Configure the main clock and system clock . . 14

Set up the system oscillator using XTALIN and

XTALOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.6.19

4.3.1

4.3.2

4.3.3

4.6.20

4.6.21

4.6.22

4.4

Pin description. . . . . . . . . . . . . . . . . . . . . . . . . 15

4.5

General description. . . . . . . . . . . . . . . . . . . . . 15

Clock generation. . . . . . . . . . . . . . . . . . . . . . . 15

Power control of analog components . . . . . . . 16

Configuration of reduced power-modes . . . . . 17

Reset and interrupt control . . . . . . . . . . . . . . . 17

4.6.23

4.6.24

4.6.25

4.6.26

4.6.27

4.6.28

4.6.29

4.6.30

4.6.31

4.6.32

4.6.33

4.5.1

4.5.2

4.5.3

4.5.4

4.6

Register description . . . . . . . . . . . . . . . . . . . . 17

System memory remap register . . . . . . . . . . . 19

Peripheral reset control register . . . . . . . . . . . 19

System PLL control register . . . . . . . . . . . . . . 20

System PLL status register. . . . . . . . . . . . . . . 21

System oscillator control register . . . . . . . . . . 21

Watchdog oscillator control register . . . . . . . . 22

System reset status register . . . . . . . . . . . . . . 23

System PLL clock source select register . . . . 23

System PLL clock source update register . . . 24

Main clock source select register . . . . . . . . . . 24

Main clock source update enable register . . . 24

System clock divider register . . . . . . . . . . . . . 25

System clock control register . . . . . . . . . . . . . 25

USART clock divider register . . . . . . . . . . . . . 27

CLKOUT clock source select register. . . . . . . 27

CLKOUT clock source update enable register 27

4.6.1

4.6.2

4.6.3

4.6.4

4.6.5

4.6.6

4.6.7

4.6.8

4.6.9

4.6.10

4.6.11

4.6.12

4.6.13

4.6.14

4.6.15

4.6.16

4.7

4.7.1

4.7.1.1

4.7.1.2

4.7.1.3

Functional description . . . . . . . . . . . . . . . . . . 38

System PLL functional description. . . . . . . . . 38

Lock detector . . . . . . . . . . . . . . . . . . . . . . . . . 39

Power-down control . . . . . . . . . . . . . . . . . . . . 39

Divider ratio programming . . . . . . . . . . . . . . . 39

4.7.1.3.1 Post divider . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.7.1.3.2 Feedback divider . . . . . . . . . . . . . . . . . . . . . . 39

4.7.1.3.3 Changing the divider values. . . . . . . . . . . . . . 39

4.7.1.4

Frequency selection. . . . . . . . . . . . . . . . . . . . 39

4.7.1.4.1 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.7.1.4.2 Power-down mode. . . . . . . . . . . . . . . . . . . . . 40

Chapter 5: LPC800 Reduced power modes and Power Management Unit (PMU)

5.1

How to read this chapter. . . . . . . . . . . . . . . . . 41

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Basic configuration . . . . . . . . . . . . . . . . . . . . . 41

Pin description. . . . . . . . . . . . . . . . . . . . . . . . . 41

5.5

5.5.1

5.6

General description . . . . . . . . . . . . . . . . . . . . 41

Wake-up process . . . . . . . . . . . . . . . . . . . . . . 42

Register description . . . . . . . . . . . . . . . . . . . . 43

Power control register . . . . . . . . . . . . . . . . . . 44

5.2

5.3

5.6.1

5.4

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Rev. 1.0 — 7 November 2012

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Chapter 27: Supplementary information

5.6.2

5.6.3

General purpose registers 0 to 3 . . . . . . . . . . 44

Deep power-down control register . . . . . . . . . 45

5.7.5.1

5.7.5.2

5.7.5.3

5.7.6

5.7.6.1

5.7.6.2

5.7.6.3

5.7.7

Power configuration in Deep-sleep mode . . . 48

Programming Deep-sleep mode . . . . . . . . . . 49

Wake-up from Deep-sleep mode . . . . . . . . . . 49

Power-down mode. . . . . . . . . . . . . . . . . . . . . 49

Power configuration in Power-down mode . . 50

Programming Power-down mode . . . . . . . . . 50

Wake-up from Power-down mode . . . . . . . . . 50

Deep power-down mode . . . . . . . . . . . . . . . . 51

Power configuration in Deep power-down mode .

51

5.7

5.7.1

5.7.2

Functional description . . . . . . . . . . . . . . . . . . 46

Power management . . . . . . . . . . . . . . . . . . . . 46

Reduced power modes and WWDT lock features

47

Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Power configuration in Active mode . . . . . . . . 47

Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Power configuration in Sleep mode . . . . . . . . 48

Programming Sleep mode . . . . . . . . . . . . . . . 48

Wake-up from Sleep mode. . . . . . . . . . . . . . . 48

Deep-sleep mode . . . . . . . . . . . . . . . . . . . . . . 48

5.7.3

5.7.3.1

5.7.4

5.7.4.1

5.7.4.2

5.7.4.3

5.7.5

5.7.7.1

5.7.7.2

5.7.7.3

Programming Deep power-down mode . . . . . 51

Wake-up from Deep power-down mode . . . . 51

Chapter 6: LPC800 I/O configuration (IOCON)

6.1

6.2

6.3

How to read this chapter. . . . . . . . . . . . . . . . . 53

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Basic configuration . . . . . . . . . . . . . . . . . . . . . 53

6.5.4

6.5.5

6.5.6

6.5.7

6.5.8

6.5.9

6.5.10

6.5.11

6.5.12

6.5.13

6.5.14

6.5.15

6.5.16

6.5.17

6.5.18

PIO0_5 register . . . . . . . . . . . . . . . . . . . . . . . 61

PIO0_4 register . . . . . . . . . . . . . . . . . . . . . . . 62

PIO0_3 register . . . . . . . . . . . . . . . . . . . . . . . 63

PIO0_2 register . . . . . . . . . . . . . . . . . . . . . . . 64

PIO0_11 register . . . . . . . . . . . . . . . . . . . . . . 65

PIO0_10 register . . . . . . . . . . . . . . . . . . . . . . 66

PIO0_16 register . . . . . . . . . . . . . . . . . . . . . . 67

PIO0_15 register . . . . . . . . . . . . . . . . . . . . . . 68

PIO0_1 register . . . . . . . . . . . . . . . . . . . . . . . 69

PIO0_9 register . . . . . . . . . . . . . . . . . . . . . . . 70

PIO0_8 register . . . . . . . . . . . . . . . . . . . . . . . 71

PIO0_7 register . . . . . . . . . . . . . . . . . . . . . . . 72

PIO0_6 register . . . . . . . . . . . . . . . . . . . . . . . 73

PIO0_0 register . . . . . . . . . . . . . . . . . . . . . . . 74

PIO0_14 register . . . . . . . . . . . . . . . . . . . . . . 75

6.4

General description. . . . . . . . . . . . . . . . . . . . . 54

Pin configuration. . . . . . . . . . . . . . . . . . . . . . . 54

Pin function. . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Pin mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Open-drain mode . . . . . . . . . . . . . . . . . . . . . . 55

Analog mode . . . . . . . . . . . . . . . . . . . . . . . . . 55

I²C-bus mode . . . . . . . . . . . . . . . . . . . . . . . . . 55

Programmable glitch filter. . . . . . . . . . . . . . . . 55

6.4.1

6.4.2

6.4.3

6.4.4

6.4.5

6.4.6

6.4.7

6.5

Register description . . . . . . . . . . . . . . . . . . . . 57

PIO0_17 register . . . . . . . . . . . . . . . . . . . . . . 57

PIO0_13 register . . . . . . . . . . . . . . . . . . . . . . 59

PIO0_12 register . . . . . . . . . . . . . . . . . . . . . . 60

6.5.1

6.5.2

6.5.3

Chapter 7: LPC800 GPIO port

7.1

7.2

7.3

7.4

7.5

How to read this chapter. . . . . . . . . . . . . . . . . 76

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Basic configuration . . . . . . . . . . . . . . . . . . . . . 76

Pin description. . . . . . . . . . . . . . . . . . . . . . . . . 76

General description. . . . . . . . . . . . . . . . . . . . . 76

7.6.5

7.6.6

7.6.7

7.6.8

7.6.9

GPIO port pin registers . . . . . . . . . . . . . . . . . 78

GPIO masked port pin registers. . . . . . . . . . . 79

GPIO port set registers . . . . . . . . . . . . . . . . . 79

GPIO port clear registers . . . . . . . . . . . . . . . . 79

GPIO port toggle registers . . . . . . . . . . . . . . . 80

7.7

Functional description . . . . . . . . . . . . . . . . . . 80

Reading pin state. . . . . . . . . . . . . . . . . . . . . . 80

GPIO output. . . . . . . . . . . . . . . . . . . . . . . . . . 80

Masked I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Recommended practices . . . . . . . . . . . . . . . . 81

7.6

Register description . . . . . . . . . . . . . . . . . . . . 77

GPIO port byte pin registers. . . . . . . . . . . . . . 77

GPIO port word pin registers . . . . . . . . . . . . . 77

GPIO port direction registers . . . . . . . . . . . . . 78

GPIO port mask registers. . . . . . . . . . . . . . . . 78

7.7.1

7.7.2

7.7.3

7.7.4

7.6.1

7.6.2

7.6.3

7.6.4

Chapter 8: LPC800 Pin interrupts/pattern match engine

8.1

How to read this chapter. . . . . . . . . . . . . . . . . 82

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

8.5.2.1

Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

8.2

8.6

8.6.1

8.6.2

Register description . . . . . . . . . . . . . . . . . . . . 86

Pin interrupt mode register. . . . . . . . . . . . . . . 86

Pin interrupt level or rising edge interrupt enable

register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Pin interrupt level or rising edge interrupt set

register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Pin interrupt level or rising edge interrupt clear

register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

8.3

8.3.1

Basic configuration . . . . . . . . . . . . . . . . . . . . . 82

Configure pins as pin interrupts or as inputs to the

pattern match engine . . . . . . . . . . . . . . . . . . . 83

8.6.3

8.6.4

8.4

Pin description. . . . . . . . . . . . . . . . . . . . . . . . . 83

8.5

8.5.1

8.5.2

General description. . . . . . . . . . . . . . . . . . . . . 83

Pin interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . 84

Pattern match engine . . . . . . . . . . . . . . . . . . . 84

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Preliminary user manual

Rev. 1.0 — 7 November 2012

307 of 313

UM10601

NXP Semiconductors

Chapter 27: Supplementary information

8.6.5

8.6.6

8.6.7

Pin interrupt active level or falling edge interrupt

8.6.11

8.6.12

Pattern Match Interrupt Control Register . . . . 90

Pattern Match Interrupt Bit-Slice Source register.

91

Pattern Match Interrupt Bit-Slice Configuration

register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

enable register . . . . . . . . . . . . . . . . . . . . . . . . 88

Pin interrupt active level or falling edge interrupt

set register . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Pin interrupt active level or falling edge interrupt

clear register. . . . . . . . . . . . . . . . . . . . . . . . . . 89

Pin interrupt rising edge register. . . . . . . . . . . 89

Pin interrupt falling edge register . . . . . . . . . . 90

Pin interrupt status register. . . . . . . . . . . . . . . 90

8.6.13

8.7

8.7.1

8.7.2

Functional description . . . . . . . . . . . . . . . . . . 98

Pin interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 98

Pattern Match engine example . . . . . . . . . . . 99

8.6.8

8.6.9

8.6.10

Chapter 9: LPC800 Switch matrix

9.1

9.2

How to read this chapter. . . . . . . . . . . . . . . . 100

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

9.5.1

9.5.2

9.5.3

9.5.4

9.5.5

9.5.6

9.5.7

9.5.8

9.5.9

9.5.10

Pin assign register 0 . . . . . . . . . . . . . . . . . . 105

Pin assign register 1 . . . . . . . . . . . . . . . . . . 105

Pin assign register 2 . . . . . . . . . . . . . . . . . . 106

Pin assign register 3 . . . . . . . . . . . . . . . . . . 106

Pin assign register 4 . . . . . . . . . . . . . . . . . . 106

Pin assign register 5 . . . . . . . . . . . . . . . . . . 107

Pin assign register 6 . . . . . . . . . . . . . . . . . . 107

Pin assign register 7 . . . . . . . . . . . . . . . . . . 108

Pin assign register 8 . . . . . . . . . . . . . . . . . . 108

Pin enable register 0 . . . . . . . . . . . . . . . . . . 108

9.3

9.3.1

9.3.2

Basic configuration . . . . . . . . . . . . . . . . . . . . 100

Connect an internal signal to a package pin. 101

Enable an analog input or other special function .

101

9.4

9.4.1

9.4.2

General description. . . . . . . . . . . . . . . . . . . . 102

Movable functions. . . . . . . . . . . . . . . . . . . . . 102

Switch matrix register interface. . . . . . . . . . . 103

9.5

Register description . . . . . . . . . . . . . . . . . . . 104

Chapter 10: LPC800 State Configurable Timer (SCT)

10.1

10.2

10.3

10.3.1

10.4

10.5

How to read this chapter. . . . . . . . . . . . . . . . 111

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Basic configuration . . . . . . . . . . . . . . . . . . . . 111

Use the SCT as a simple timer. . . . . . . . . . . 111

Pin description. . . . . . . . . . . . . . . . . . . . . . . . 112

General description. . . . . . . . . . . . . . . . . . . . 112

10.6.19 SCT capture registers 0 to 4 (REGMODEn bit = 1)

127

10.6.20 SCT match reload registers 0 to 4 (REGMODEn

bit = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

10.6.21 SCT capture control registers 0 to 4 (REGMODEn

bit = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

10.6.22 SCT event state mask registers 0 to 5. . . . . 129

10.6.23 SCT event control registers 0 to 5 . . . . . . . . 129

10.6.24 SCT output set registers 0 to 3 . . . . . . . . . . 131

10.6.25 SCT output clear registers 0 to 3 . . . . . . . . . 131

10.6

Register description . . . . . . . . . . . . . . . . . . . 114

SCT configuration register . . . . . . . . . . . . . . 117

SCT control register . . . . . . . . . . . . . . . . . . . 118

SCT limit register . . . . . . . . . . . . . . . . . . . . . 119

SCT halt condition register . . . . . . . . . . . . . . 120

SCT stop condition register . . . . . . . . . . . . . 120

SCT start condition register . . . . . . . . . . . . . 121

SCT counter register . . . . . . . . . . . . . . . . . . 121

SCT state register. . . . . . . . . . . . . . . . . . . . . 122

SCT input register. . . . . . . . . . . . . . . . . . . . . 123

10.6.1

10.6.2

10.6.3

10.6.4

10.6.5

10.6.6

10.6.7

10.6.8

10.6.9

10.7

Functional description . . . . . . . . . . . . . . . . . 132

Match logic. . . . . . . . . . . . . . . . . . . . . . . . . . 132

Capture logic . . . . . . . . . . . . . . . . . . . . . . . . 132

Event selection. . . . . . . . . . . . . . . . . . . . . . . 132

Output generation . . . . . . . . . . . . . . . . . . . . 133

Interrupt generation . . . . . . . . . . . . . . . . . . . 133

Clearing the prescaler . . . . . . . . . . . . . . . . . 134

Match vs. I/O events . . . . . . . . . . . . . . . . . . 134

SCT operation . . . . . . . . . . . . . . . . . . . . . . . 135

Configure the SCT . . . . . . . . . . . . . . . . . . . 135

10.7.1

10.7.2

10.7.3

10.7.4

10.7.5

10.7.6

10.7.7

10.7.8

10.7.9

10.6.10 SCT match/capture registers mode register. 123

10.6.11 SCT output register . . . . . . . . . . . . . . . . . . . 124

10.6.12 SCT bidirectional output control register. . . . 124

10.6.13 SCT conflict resolution register. . . . . . . . . . . 125

10.6.14 SCT flag enable register. . . . . . . . . . . . . . . . 126

10.6.15 SCT event flag register. . . . . . . . . . . . . . . . . 126

10.6.16 SCT conflict enable register . . . . . . . . . . . . . 126

10.6.17 SCT conflict flag register . . . . . . . . . . . . . . . 126

10.6.18 SCT match registers 0 to 4 (REGMODEn bit = 0)

127

10.7.9.1 Configure the counter . . . . . . . . . . . . . . . . . 135

10.7.9.2 Configure the match and capture registers . 135

10.7.9.3 Configure events and event responses . . . . 136

10.7.9.4 Configure multiple states . . . . . . . . . . . . . . . 137

10.7.9.5 Miscellaneous options . . . . . . . . . . . . . . . . . 137

10.7.10 Run the SCT . . . . . . . . . . . . . . . . . . . . . . . . 137

10.7.11 Configure the SCT without using states. . . . 138

Chapter 11: LPC800 Multi-Rate Timer (MRT)

11.1

11.2

11.3

How to read this chapter. . . . . . . . . . . . . . . . 139

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Basic configuration . . . . . . . . . . . . . . . . . . . . 139

11.4

Pin description . . . . . . . . . . . . . . . . . . . . . . . 139

General description . . . . . . . . . . . . . . . . . . . 139

Repeat interrupt mode . . . . . . . . . . . . . . . . . 140

11.5

11.5.1

UM10601

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Preliminary user manual

Rev. 1.0 — 7 November 2012

308 of 313

UM10601

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Chapter 27: Supplementary information

11.5.2

One-shot interrupt mode. . . . . . . . . . . . . . . . 141

11.6.3

11.6.4

11.6.5

11.6.6

Control register . . . . . . . . . . . . . . . . . . . . . . 143

Status register . . . . . . . . . . . . . . . . . . . . . . . 144

Idle channel register. . . . . . . . . . . . . . . . . . . 144

Global interrupt flag register. . . . . . . . . . . . . 145

11.6

11.6.1

11.6.2

Register description . . . . . . . . . . . . . . . . . . . 141

Time interval register . . . . . . . . . . . . . . . . . . 142

Timer register . . . . . . . . . . . . . . . . . . . . . . . . 143

Chapter 12: LPC800 Windowed Watchdog Timer (WWDT)

12.1

12.2

12.3

12.4

How to read this chapter. . . . . . . . . . . . . . . . 146

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Basic configuration . . . . . . . . . . . . . . . . . . . . 146

Pin description. . . . . . . . . . . . . . . . . . . . . . . . 146

12.5.3.2 Changing the WWDT reload value . . . . . . . 149

12.6

Register description . . . . . . . . . . . . . . . . . . . 150

Watchdog mode register . . . . . . . . . . . . . . . 150

Watchdog Timer Constant register. . . . . . . . 152

Watchdog Feed register. . . . . . . . . . . . . . . . 152

Watchdog Timer Value register . . . . . . . . . . 153

Watchdog Timer Warning Interrupt register . 153

Watchdog Timer Window register . . . . . . . . 153

12.6.1

12.6.2

12.6.3

12.6.4

12.6.5

12.6.6

12.5

General description. . . . . . . . . . . . . . . . . . . . 147

Block diagram. . . . . . . . . . . . . . . . . . . . . . . . 147

Clocking and power control . . . . . . . . . . . . . 148

Using the WWDT lock features. . . . . . . . . . . 149

12.5.1

12.5.2

12.5.3

12.7

Functional description . . . . . . . . . . . . . . . . . 154

12.5.3.1 Disabling the WWDT clock source . . . . . . . . 149

Chapter 13: LPC800 Analog comparator

13.1

13.2

13.3

13.3.1

13.4

13.5

How to read this chapter. . . . . . . . . . . . . . . . 155

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Basic configuration . . . . . . . . . . . . . . . . . . . . 155

Connect the comparator output to the SCT . 155

Pin description. . . . . . . . . . . . . . . . . . . . . . . . 156

General description. . . . . . . . . . . . . . . . . . . . 156

13.5.1

13.5.2

13.5.3

13.5.4

Reference voltages . . . . . . . . . . . . . . . . . . . 157

Settling times . . . . . . . . . . . . . . . . . . . . . . . . 157

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Comparator outputs . . . . . . . . . . . . . . . . . . . 158

13.6

13.6.1

13.6.2

Register description . . . . . . . . . . . . . . . . . . . 158

Comparator control register . . . . . . . . . . . . . 158

Voltage ladder register. . . . . . . . . . . . . . . . . 160

Chapter 14: LPC800 Self wake-up timer (WKT)

14.1

14.2

14.3

14.4

How to read this chapter. . . . . . . . . . . . . . . . 161

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Basic configuration . . . . . . . . . . . . . . . . . . . . 161

Pin description. . . . . . . . . . . . . . . . . . . . . . . . 161

14.5

14.5.1

General description . . . . . . . . . . . . . . . . . . . 161

WKT clock sources . . . . . . . . . . . . . . . . . . . 161

14.6

14.6.1

14.6.2

Register description . . . . . . . . . . . . . . . . . . . 162

Control register . . . . . . . . . . . . . . . . . . . . . . 162

Count register . . . . . . . . . . . . . . . . . . . . . . . 163

Chapter 15: LPC800 USART0/1/2

15.1

15.2

How to read this chapter. . . . . . . . . . . . . . . . 164

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

15.6.5

15.6.6

15.6.7

15.6.8

15.6.9

USART Interrupt Enable Clear register . . . . 176

USART Receiver Data register . . . . . . . . . . 177

USART Receiver Data with Status register . 177

USART Transmitter Data Register . . . . . . . 178

USART Baud Rate Generator register. . . . . 179

15.3

15.3.1

15.3.2

Basic configuration . . . . . . . . . . . . . . . . . . . . 164

Configure the USART clock and baud rate. . 165

Configure the USART for wake-up . . . . . . . 166

15.6.10 USART Interrupt Status register. . . . . . . . . . 179

15.3.2.1 Wake-up from Sleep mode. . . . . . . . . . . . . . 166

15.3.2.2 Wake-up from Deep-sleep or Power-down mode.

167

15.7

15.7.1

Functional description . . . . . . . . . . . . . . . . . 180

Clocking and Baud rates . . . . . . . . . . . . . . . 180

15.7.1.1 Fractional Rate Generator (FRG) . . . . . . . . 180

15.7.1.2 Baud Rate Generator (BRG) . . . . . . . . . . . . 181

15.7.1.3 Baud rate calculations . . . . . . . . . . . . . . . . . 181

15.4

15.5

Pin description. . . . . . . . . . . . . . . . . . . . . . . . 167

General description. . . . . . . . . . . . . . . . . . . . 168

15.6

Register description . . . . . . . . . . . . . . . . . . . 170

USART Configuration register . . . . . . . . . . . 171

USART Control register . . . . . . . . . . . . . . . . 172

USART Status register . . . . . . . . . . . . . . . . . 174

USART Interrupt Enable read and set register . .

175

15.7.2

15.7.3

Synchronous mode . . . . . . . . . . . . . . . . . . . 181

Flow control . . . . . . . . . . . . . . . . . . . . . . . . . 181

15.6.1

15.6.2

15.6.3

15.6.4

15.7.3.1 Hardware flow control . . . . . . . . . . . . . . . . . 181

15.7.3.2 Software flow control . . . . . . . . . . . . . . . . . . 182

Chapter 16: LPC800 I2C-bus interface

16.1

How to read this chapter. . . . . . . . . . . . . . . . 183

16.2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

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309 of 313

UM10601

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Chapter 27: Supplementary information

16.3

16.4

16.5

Basic configuration . . . . . . . . . . . . . . . . . . . . 183

16.6.10 Master Data register . . . . . . . . . . . . . . . . . . 199

16.6.11 Slave Control register . . . . . . . . . . . . . . . . . 199

16.6.12 Slave Data register . . . . . . . . . . . . . . . . . . . 200

16.6.13 Slave Address registers. . . . . . . . . . . . . . . . 201

16.6.14 Slave address Qualifier 0 register . . . . . . . . 201

16.6.15 Monitor data register . . . . . . . . . . . . . . . . . . 202

Pin description. . . . . . . . . . . . . . . . . . . . . . . . 184

General description. . . . . . . . . . . . . . . . . . . . 184

16.6

Register description . . . . . . . . . . . . . . . . . . . 185

I2C Configuration register . . . . . . . . . . . . . . 187

I2C Status register . . . . . . . . . . . . . . . . . . . . 189

Interrupt Enable Set and read register . . . . . 193

Interrupt Enable Clear register . . . . . . . . . . . 194

Time-out value register. . . . . . . . . . . . . . . . . 195

I2C Clock Divider register. . . . . . . . . . . . . . . 196

I2C Interrupt Status register . . . . . . . . . . . . . 196

Master Control register. . . . . . . . . . . . . . . . . 197

Master Time . . . . . . . . . . . . . . . . . . . . . . . . . 198

16.6.1

16.6.2

16.6.3

16.6.4

16.6.5

16.6.6

16.6.7

16.6.8

16.6.9

16.7

Functional description . . . . . . . . . . . . . . . . . 203

16.7.1

Bus rates and timing considerations . . . . . . 203

16.7.1.1 Rate calculations . . . . . . . . . . . . . . . . . . . . . 203

16.7.2

16.7.3

16.7.4

16.7.5

Time-out. . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Ten-bit addressing . . . . . . . . . . . . . . . . . . . . 204

Clocking and power considerations . . . . . . . 204

lnterrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Chapter 17: LPC800 SPI0/1

17.1

How to read this chapter. . . . . . . . . . . . . . . . 206

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Basic configuration . . . . . . . . . . . . . . . . . . . . 206

Configure the SPIs for wake-up . . . . . . . . . . 206

17.6.7

17.6.8

17.6.9

SPI Transmitter Data and Control register. . 216

SPI Transmitter Data Register . . . . . . . . . . 217

SPI Transmitter Control register. . . . . . . . . . 217

17.2

17.3

17.3.1

17.6.10 SPI Divider register . . . . . . . . . . . . . . . . . . . 218

17.6.11 SPI Interrupt Status register. . . . . . . . . . . . . 218

17.3.1.1 Wake-up from Sleep mode. . . . . . . . . . . . . . 207

17.3.1.2 Wake-up from Deep-sleep or Power-down mode.

207

17.7

17.7.1

17.7.2

Functional description . . . . . . . . . . . . . . . . . 220

Operating modes: clock and phase selection 220

Frame delays . . . . . . . . . . . . . . . . . . . . . . . . 221

17.4

17.5

Pin description. . . . . . . . . . . . . . . . . . . . . . . . 207

General description. . . . . . . . . . . . . . . . . . . . 209

17.7.2.1 Pre_delay and Post_delay. . . . . . . . . . . . . . 221

17.7.2.2 Frame_delay . . . . . . . . . . . . . . . . . . . . . . . . 222

17.7.2.3 Transfer_delay . . . . . . . . . . . . . . . . . . . . . . . 223

17.6

Register description . . . . . . . . . . . . . . . . . . . 209

SPI Configuration register . . . . . . . . . . . . . . 211

SPI Delay register. . . . . . . . . . . . . . . . . . . . . 212

SPI Status register . . . . . . . . . . . . . . . . . . . . 213

SPI Interrupt Enable read and Set register . 214

SPI Interrupt Enable Clear register. . . . . . . . 215

SPI Receiver Data register . . . . . . . . . . . . . . 215

17.6.1

17.6.2

17.6.3

17.6.4

17.6.5

17.6.6

17.7.3

Clocking and data rates . . . . . . . . . . . . . . . . 224

17.7.3.1 Data rate calculations . . . . . . . . . . . . . . . . . 224

17.7.4

17.7.5

17.7.6

Slave select . . . . . . . . . . . . . . . . . . . . . . . . . 224

Data lengths greater than 16 bits. . . . . . . . . 224

Data stalls . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Chapter 18: LPC800 Cyclic Redundancy Check (CRC) engine

18.1

18.2

18.3

18.4

18.5

18.6

18.7

How to read this chapter. . . . . . . . . . . . . . . . 227

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Basic configuration . . . . . . . . . . . . . . . . . . . . 227

Pin description. . . . . . . . . . . . . . . . . . . . . . . . 227

General description. . . . . . . . . . . . . . . . . . . . 227

Description. . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Register description . . . . . . . . . . . . . . . . . . . 228

18.7.1

18.7.2

18.7.3

18.7.4

CRC mode register . . . . . . . . . . . . . . . . . . . 229

CRC seed register . . . . . . . . . . . . . . . . . . . . 229

CRC checksum register. . . . . . . . . . . . . . . . 229

CRC data register . . . . . . . . . . . . . . . . . . . . 229

18.8

Functional description . . . . . . . . . . . . . . . . . 231

CRC-CCITT set-up . . . . . . . . . . . . . . . . . . . 231

CRC-16 set-up. . . . . . . . . . . . . . . . . . . . . . . 231

CRC-32 set-up. . . . . . . . . . . . . . . . . . . . . . . 231

18.8.1

18.8.2

18.8.3

Chapter 19: LPC800 Flash controller

19.1

19.2

19.3

How to read this chapter. . . . . . . . . . . . . . . . 232

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

General description. . . . . . . . . . . . . . . . . . . . 232

19.4.4

19.5

19.5.1

Flash signature generation result register . . 233

Functional description . . . . . . . . . . . . . . . . . 234

Flash signature generation . . . . . . . . . . . . . 234

19.5.1.1 Signature generation address and control

registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

19.5.1.2 Signature generation . . . . . . . . . . . . . . . . . . 234

19.5.1.3 Content verification . . . . . . . . . . . . . . . . . . . 235

19.4

Register description . . . . . . . . . . . . . . . . . . . 232

Flash configuration register . . . . . . . . . . . . . 232

Flash signature start address register . . . . . 233

Flash signature stop address register. . . . . . 233

19.4.1

19.4.2

19.4.3

Chapter 20: LPC800 Boot ROM

20.1

How to read this chapter. . . . . . . . . . . . . . . . 236

20.2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

UM10601

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Preliminary user manual

Rev. 1.0 — 7 November 2012

310 of 313

UM10601

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Chapter 27: Supplementary information

20.3

20.3.1

20.3.2

General description. . . . . . . . . . . . . . . . . . . . 236

Boot loader . . . . . . . . . . . . . . . . . . . . . . . . . . 236

ROM-based APIs . . . . . . . . . . . . . . . . . . . . . 237

20.4.1

20.4.2

20.4.3

20.4.4

Boot pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

Memory map after any reset . . . . . . . . . . . . 238

Boot process . . . . . . . . . . . . . . . . . . . . . . . . 238

Boot process flowchart. . . . . . . . . . . . . . . . . 239

20.4

Functional description . . . . . . . . . . . . . . . . . 238

Chapter 21: LPC800 Flash ISP and IAP programming

21.1

21.2

How to read this chapter. . . . . . . . . . . . . . . . 240

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

21.4.1.14 ReadUID . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

21.4.1.15 UART ISP Return Codes . . . . . . . . . . . . . . . 250

21.4.2

IAP commands. . . . . . . . . . . . . . . . . . . . . . . 250

21.3

General description. . . . . . . . . . . . . . . . . . . . 240

Flash configuration . . . . . . . . . . . . . . . . . . . . 240

Flash content protection mechanism . . . . . . 241

Code Read Protection (CRP) . . . . . . . . . . . . 241

21.4.2.1 Prepare sector(s) for write operation (IAP) . 252

21.4.2.2 Copy RAM to flash (IAP) . . . . . . . . . . . . . . . 253

21.4.2.3 Erase Sector(s) (IAP). . . . . . . . . . . . . . . . . . 254

21.4.2.4 Blank check sector(s) (IAP) . . . . . . . . . . . . . 254

21.4.2.5 Read Part Identification number (IAP) . . . . . 254

21.4.2.6 Read Boot code version number (IAP) . . . . 255

21.4.2.7 Compare <address1> <address2> <no of bytes>

(IAP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

21.4.2.8 Reinvoke ISP (IAP) . . . . . . . . . . . . . . . . . . . 256

21.4.2.9 ReadUID (IAP). . . . . . . . . . . . . . . . . . . . . . . 256

21.4.2.10 Erase page. . . . . . . . . . . . . . . . . . . . . . . . . . 256

21.4.2.11 IAP Status Codes. . . . . . . . . . . . . . . . . . . . . 256

21.3.1

21.3.2

21.3.3

21.3.3.1 ISP entry protection . . . . . . . . . . . . . . . . . . . 243

21.4

21.4.1

API description . . . . . . . . . . . . . . . . . . . . . . . 243

UART ISP commands. . . . . . . . . . . . . . . . . . 243

21.4.1.1 Unlock <Unlock code> . . . . . . . . . . . . . . . . . 244

21.4.1.2 Set Baud Rate <Baud Rate> <stop bit> . . . 244

21.4.1.3 Echo <setting> . . . . . . . . . . . . . . . . . . . . . . . 245

21.4.1.4 Write to RAM <start address> <number of bytes>

245

21.4.1.5 Read Memory <address> <number of bytes> . . .

245

21.5

Functional description . . . . . . . . . . . . . . . . . 257

21.5.1

UART Communication protocol . . . . . . . . . . 257

21.4.1.6 Prepare sector(s) for write operation <start sector

number> <end sector number> . . . . . . . . . . 246

21.4.1.7 Copy RAM to flash <Flash address> <RAM

address> <no of bytes> . . . . . . . . . . . . . . . . 246

21.4.1.8 Go <address> <mode> . . . . . . . . . . . . . . . . 247

21.4.1.9 Erase sector(s) <start sector number> <end

sector number> . . . . . . . . . . . . . . . . . . . . . . 248

21.4.1.10 Blank check sector(s) <sector number> <end

sector number> . . . . . . . . . . . . . . . . . . . . . . 248

21.4.1.11 Read Part Identification number . . . . . . . . . 248

21.4.1.12 Read Boot code version number . . . . . . . . . 249

21.4.1.13 Compare <address1> <address2> <no of bytes>

249

21.5.1.1 UART ISP command format. . . . . . . . . . . . . 257

21.5.1.2 UART ISP response format . . . . . . . . . . . . . 257

21.5.1.3 UART ISP data format . . . . . . . . . . . . . . . . . 257

21.5.2

Memory and interrupt use for ISP and IAP . 257

21.5.2.1 Interrupts during UART ISP . . . . . . . . . . . . . 257

21.5.2.2 Interrupts during IAP . . . . . . . . . . . . . . . . . . 258

21.5.2.3 RAM used by ISP command handler. . . . . . 258

21.5.2.4 RAM used by IAP command handler. . . . . . 258

21.5.3

Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . 258

21.5.3.1 Comparing flash images . . . . . . . . . . . . . . . 258

21.5.3.2 Serial Wire Debug (SWD) flash programming

interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

Chapter 22: LPC800 Power profile API ROM driver

22.1

22.2

22.3

22.4

22.4.1

How to read this chapter. . . . . . . . . . . . . . . . 259

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

General description. . . . . . . . . . . . . . . . . . . . 259

API description . . . . . . . . . . . . . . . . . . . . . . . 260

set_pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

22.5.1.1 Invalid frequency (device maximum clock rate

exceeded) . . . . . . . . . . . . . . . . . . . . . . . . . . 265

22.5.1.2 Invalid frequency selection (system clock divider

restrictions) . . . . . . . . . . . . . . . . . . . . . . . . . 266

22.5.1.3 Exact solution cannot be found (PLL) . . . . . 266

22.5.1.4 System clock less than or equal to the expected

value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

22.5.1.5 System clock greater than or equal to the

expected value. . . . . . . . . . . . . . . . . . . . . . . 266

22.5.1.6 System clock approximately equal to the expected

value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

22.4.1.1 Param0: system PLL input frequency and

Param1: expected system clock. . . . . . . . . . 262

22.4.1.2 Param2: mode . . . . . . . . . . . . . . . . . . . . . . . 262

22.4.1.3 Param3: system PLL lock time-out. . . . . . . . 263

22.4.2

set_power. . . . . . . . . . . . . . . . . . . . . . . . . . . 263

22.4.2.1 Param0: main clock . . . . . . . . . . . . . . . . . . . 265

22.4.2.2 Param1: mode . . . . . . . . . . . . . . . . . . . . . . . 265

22.4.2.3 Param2: system clock . . . . . . . . . . . . . . . . . 265

22.5.2

Power control. . . . . . . . . . . . . . . . . . . . . . . . 267

22.5.2.1 Invalid frequency (device maximum clock rate

exceeded) . . . . . . . . . . . . . . . . . . . . . . . . . . 267

22.5.2.2 An applicable power setup. . . . . . . . . . . . . . 267

22.5

Functional description . . . . . . . . . . . . . . . . . 265

22.5.1

Clock control. . . . . . . . . . . . . . . . . . . . . . . . . 265

Chapter 23: LPC800 I2C-bus ROM API

23.1

How to read this chapter. . . . . . . . . . . . . . . . 268

23.2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

UM10601

All information provided in this document is subject to legal disclaimers.

Preliminary user manual

Rev. 1.0 — 7 November 2012

311 of 313

UM10601

NXP Semiconductors

Chapter 27: Supplementary information

23.3

General description. . . . . . . . . . . . . . . . . . . . 268

23.4.17 I2C Get Status . . . . . . . . . . . . . . . . . . . . . . . 275

23.4.18 I2C time-out value . . . . . . . . . . . . . . . . . . . . 276

23.4.19 Error codes . . . . . . . . . . . . . . . . . . . . . . . . . 276

23.4.20 I2C Status code . . . . . . . . . . . . . . . . . . . . . . 276

23.4.21 I2C ROM driver variables. . . . . . . . . . . . . . . 276

23.4.21.1 I2C Handle. . . . . . . . . . . . . . . . . . . . . . . . . . 276

23.4.22 PARAM and RESULT structure . . . . . . . . . . 277

23.4.23 Error structure . . . . . . . . . . . . . . . . . . . . . . . 277

23.4.24 I2C Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

23.4.25 I2C ROM driver pointer . . . . . . . . . . . . . . . . 278

23.4

API description . . . . . . . . . . . . . . . . . . . . . . . 269

ISR handler. . . . . . . . . . . . . . . . . . . . . . . . . . 271

I2C Master Transmit Polling . . . . . . . . . . . . . 271

I2C Master Receive Polling . . . . . . . . . . . . . 271

I2C Master Transmit and Receive Polling . . 272

I2C Master Transmit Interrupt. . . . . . . . . . . . 272

I2C Master Receive Interrupt . . . . . . . . . . . . 272

I2C Master Transmit Receive Interrupt. . . . . 273

I2C Slave Receive Polling . . . . . . . . . . . . . . 273

I2C Slave Transmit Polling . . . . . . . . . . . . . . 273

23.4.1

23.4.2

23.4.3

23.4.4

23.4.5

23.4.6

23.4.7

23.4.8

23.4.9

23.5

Functional description . . . . . . . . . . . . . . . . . 278

I2C Set-up . . . . . . . . . . . . . . . . . . . . . . . . . . 278

I2C Master mode set-up . . . . . . . . . . . . . . . 278

I2C Slave mode set-up . . . . . . . . . . . . . . . . 279

I2C Master Transmit/Receive. . . . . . . . . . . . 280

I2C Slave Mode Transmit/Receive. . . . . . . . 281

I2C time-out feature . . . . . . . . . . . . . . . . . . . 282

23.4.10 I2C Slave Receive Interrupt . . . . . . . . . . . . . 274

23.4.11 I2C Slave Transmit Interrupt. . . . . . . . . . . . . 274

23.4.12 I2C Set Slave Address . . . . . . . . . . . . . . . . . 274

23.4.13 I2C Get Memory Size . . . . . . . . . . . . . . . . . . 274

23.4.14 I2C Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

23.4.15 I2C Set Bit Rate . . . . . . . . . . . . . . . . . . . . . . 275

23.4.16 I2C Get Firmware Version . . . . . . . . . . . . . . 275

23.5.1

23.5.2

23.5.3

23.5.4

23.5.5

23.5.6

Chapter 24: LPC800 USART API ROM driver routines

24.1

24.2

24.3

How to read this chapter. . . . . . . . . . . . . . . . 284

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

General description. . . . . . . . . . . . . . . . . . . . 284

24.4.6

24.4.7

24.4.8

24.4.9

UART get line. . . . . . . . . . . . . . . . . . . . . . . . 287

UART put line. . . . . . . . . . . . . . . . . . . . . . . . 287

UART interrupt service routine. . . . . . . . . . . 287

Error codes . . . . . . . . . . . . . . . . . . . . . . . . . 287

24.4

API description . . . . . . . . . . . . . . . . . . . . . . . 285

UART get memory size. . . . . . . . . . . . . . . . . 285

UART setup . . . . . . . . . . . . . . . . . . . . . . . . . 286

UART init . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

UART get character . . . . . . . . . . . . . . . . . . . 286

UART put character . . . . . . . . . . . . . . . . . . . 286

24.4.10 UART ROM driver variables. . . . . . . . . . . . . 288

24.4.10.1 UART_CONFIG structure . . . . . . . . . . . . . . 288

24.4.10.2 UART_HANDLE_T. . . . . . . . . . . . . . . . . . . . 288

24.4.10.3 UART_PARAM_T. . . . . . . . . . . . . . . . . . . . . 288

24.4.1

24.4.2

24.4.3

24.4.4

24.4.5

24.5

Functional description . . . . . . . . . . . . . . . . . 289

Chapter 25: LPC800 Debugging

25.1

25.2

25.3

25.4

How to read this chapter. . . . . . . . . . . . . . . . 290

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

General description. . . . . . . . . . . . . . . . . . . . 290

Pin description. . . . . . . . . . . . . . . . . . . . . . . . 290

25.5

Functional description . . . . . . . . . . . . . . . . . 291

Debug limitations . . . . . . . . . . . . . . . . . . . . . 291

Debug connections for SWD . . . . . . . . . . . . 291

Boundary scan. . . . . . . . . . . . . . . . . . . . . . . 292

25.5.1

25.5.2

25.5.3

Chapter 26: LPC800 Packages and pin description

26.1

Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

26.2

Pin description . . . . . . . . . . . . . . . . . . . . . . . 294

Chapter 27: Supplementary information

27.1

27.2

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . 298

References . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

27.3.3

27.4

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . 299

Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

27.3

27.3.1

27.3.2

Legal information. . . . . . . . . . . . . . . . . . . . . . 299

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . 299

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . 299

27.5

27.6

UM10601

All information provided in this document is subject to legal disclaimers.

Preliminary user manual

Rev. 1.0 — 7 November 2012

312 of 313

UM10601

NXP Semiconductors

Chapter 27: Supplementary information

313

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 7 November 2012

Document identifier: UM10601


型号：	UM10601
厂家：	NXP
描述：	LPC800 User manual LPC800说明书 PC
文件：	总313页 (文件大小：1864K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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