VCH16245ADGG_技术文档

INTEGRATED CIRCUITS

DATA SHEET

74LVC16245A; 74LVCH16245A

16-bit bus transceiver with direction

pin; 5 V tolerant; 3-state

Product speciﬁcation

2003 Nov 25

Supersedes data of 2003 Jan 30

Philips Semiconductors

Product speciﬁcation

74LVC16245A;

74LVCH16245A

16-bit bus transceiver with direction pin; 5 V tolerant;

3-state

FEATURES

DESCRIPTION

• 5 V tolerant inputs/outputs for interfacing with 5 V logic

• Wide supply voltage range from 1.2 to 3.6 V

• CMOS low power consumption

• MULTIBYTE^TMflow-through standard pin-out

architecture

The 74LVC(H)16245A is a high-performance, low-power,

low-voltage, Si-gate CMOS device, superior to most

advanced CMOS compatible TTL families. Inputs can be

driven from either 3.3 or 5 V devices. In 3-state operation,

outputs can handle 5 Volt. These features allow the use of

these devices as a mixed 3.3 and 5 V environment.

• Low inductance multiple power and ground pins for

minimum noise and ground bounce

The 74LVC(H)16245A is a 16-bit transceiver featuring

non-inverting 3-state bus compatible outputs in both send

and receive directions. The device features two output

enable (nOE) inputs for easy cascading and two

send/receive (nDIR) inputs for direction control. nOE

controls the outputs so that the buses are effectively

isolated. This device can be used as two 8-bit transceivers

or one 16-bit transceiver.

• Direct interface with TTL levels

• High-impedance when V_CC= 0 V

• All data inputs have bushold (74LVCH16245A only)

• Complies with JEDEC standard no. 8-1A

• ESD protection:

HBM EIA/JESD22-A114-A exceeds 2000 V

MM EIA/JESD22-A115-A exceeds 200 V.

The 74LVCH16245A bushold data inputs eliminates the

need for external pull-up resistors to hold unused inputs.

QUICK REFERENCE DATA

GND = 0 V; T_amb= 25 °C; t_r= t_f≤ 2.5 ns.

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

2.2

UNIT

t

_PHL/t_PLH

propagation delay nAn to nBn; nBn to nAn C_L= 50 pF; V_CC= 3.3 V

input capacitance

ns

pF

C_I

5.0

10

30

C_I/O

C_PD

input/output capacitance

power dissipation capacitance per gate

V_CC= 3.3 V; notes 1 and 2

Notes

1. C_PDis used to determine the dynamic power dissipation (P_Din µW).

P_D= C_PD× V_CC²× f_i× N + Σ(C_L× V_CC²× f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in Volts;

N = total load switching outputs;

Σ(C_L× V_CC²× f_o) = sum of the outputs.

2. The condition is V_I= GND to V_CC

.

2003 Nov 25

2

Philips Semiconductors

Product speciﬁcation

16-bit bus transceiver with direction pin; 5 V tolerant;

3-state

74LVC16245A;

74LVCH16245A

ORDERING INFORMATION

PACKAGE

TYPE NUMBER

TEMPERATURE RANGE

PINS

PACKAGE

MATERIAL

CODE

74LVC16245ADL

74LVCH16245ADL

74LVC16245ADGG

74LVCH16245ADGG

74LVC16245AEV

74LVCH16245AEV

−40 to +125 °C

48

56

SSOP48

plastic

SOT370-1

SOT362-1

SOT702-1

TSSOP48

VFBGA56

FUNCTION TABLE

See note 1.

INPUT

OUTPUT

nOE

nDIR

nAn

nBn

L

H

X

A = B

inputs

Z

inputs

B = A

Z

H

Note

1. H = HIGH voltage level;

L = LOW voltage level;

X = don’t care;

Z = high-impedance OFF-state.

2003 Nov 25

3

Philips Semiconductors

Product speciﬁcation

16-bit bus transceiver with direction pin; 5 V tolerant;

3-state

74LVC16245A;

74LVCH16245A

PINNING

SYMBOL

1DIR

BALL

DESCRIPTION

1

2

3

A1

B2

B1

direction control input

1B0

1B1

GND

1B2

1B3

V_CC

1B4

1B5

1B6

1B7

2B0

2B1

2B2

2B3

2B4

2B5

2B6

2B7

2DIR

2OE

2A7

2A6

2A5

2A4

2A3

2A2

2A1

2A0

1A7

1A6

1A5

1A4

1A3

1A2

1A1

1A0

1OE

n.c.

data input/output

4, 10, 15, 21, 28, 34, 39, 45

B3, B4, D3, D4, G3, G4, J3, J4 ground (0 V)

5

C2

data input/output

6

C1

data input/output

supply voltage

7, 18, 31, 42

C3, C4, H3, H4

8

D2

D1

E2

E1

F1

F2

G1

G2

H1

H2

J1

data input/output

direction control input

output enable input (active LOW)

data input/output

output enable input (active LOW)

9

11

12

13

14

16

17

19

20

22

23

24

25

26

27

29

30

32

33

35

36

37

38

40

41

43

44

46

47

48

−

J2

K1

K6

J5

J6

H5

H6

G5

G6

F5

F6

E6

E5

D6

D5

C6

C5

B6

B5

A6

A2, A3, A4, A5, K2, K3, K4, K5 not connected

2003 Nov 25

4

Philips Semiconductors

Product speciﬁcation

16-bit bus transceiver with direction pin; 5 V tolerant;

3-state

74LVC16245A;

74LVCH16245A

1OE

1A0

1A1

GND

1A2

1A3

1DIR

1B0

1B1

GND

1B2

1B3

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

3

A

B

C

D

E

F

1DIR

1B1

1B3

1B5

1B7

2B0

2B2

2B4

2B6

n.c.

1B0

1B2

1B4

1B6

2B1

2B3

2B5

2B7

n.c.

1A0

1A2

1A4

1A6

2A1

2A3

2A5

2A7

1OE

1A1

1A3

1A5

1A7

2A0

2A2

2A4

2A6

2OE

4

5

GND GND

6

V

CC

7

CC

V

CC

V

CC

1A4

1A5

GND

1A6

1A7

2A0

2A1

GND

2A2

2A3

1B4

1B5

GND

1B6

1B7

2B0

2B1

GND

2B2

2B3

8

9

GND GND

10

11

12

13

14

15

16

17

18

19

16245

G

H

J

GND GND

V

CC

V

CC

V

CC

2B4

2A4

2B5 20

GND 21

2B6 22

2B7 23

2DIR 24

29 2A5

28 GND

27 2A6

26 2A7

25 2OE

GND GND

n.c.

2

n.c.

3

n.c.

4

n.c.

5

K

2DIR

1

6

mna707

mna710

Fig.1 Pin configuration SSOP48 and TSSOP48.

Fig.2 Pin configuration VFBGA56.

2003 Nov 25

5

Philips Semiconductors

Product speciﬁcation

16-bit bus transceiver with direction pin; 5 V tolerant;

3-state

74LVC16245A;

74LVCH16245A

handbook, full pagewidth

1

24

1DIR

2DIR

48

2

25

1OE

1B0

2OE

47

46

44

43

41

40

38

37

36

35

33

32

30

29

27

26

1A0

1A1

1A2

1A3

1A4

1A5

1A6

1A7

2A0

2A1

2A2

2A3

2A4

2A5

2A6

2A7

13

2B0

3

14

1B1

1B2

1B3

1B4

1B5

1B6

1B7

2B1

5

16

2B2

6

17

2B3

8

19

2B4

9

20

2B5

11

12

22

2B6

23

2B7

MNA708

Fig.3 Logic symbol.

2003 Nov 25

6

Philips Semiconductors

Product speciﬁcation

16-bit bus transceiver with direction pin; 5 V tolerant;

3-state

74LVC16245A;

74LVCH16245A

48

1

handbook, halfpage

1OE

G3

3EN1 BA

[

]

1DIR

[

]

3EN2 AB

25

24

G6

2OE

2DIR

[

]

6EN4 BA

[

6EN5 AB

47

2

1

1A0

1B0

2

3

5

46

44

43

41

40

V

1A1

1A2

1A3

1A4

1A5

1A6

1A7

2A0

1B1

1B2

1B3

1B4

1B5

1B6

1B7

2B0

handbook, halfpage

CC

6

8

9

data input

to internal circuit

11

12

13

38

37

36

MNA705

4

5

35

33

32

30

29

27

26

14

16

17

19

20

22

23

2A1

2A2

2A3

2A4

2A5

2A6

2A7

2B1

2B2

2B3

2B4

2B5

2B6

2B7

MNA709

Fig.4 Logic symbol (IEEE/IEC).

Fig.5 Bushold circuit.

2003 Nov 25

7

Philips Semiconductors

Product speciﬁcation

16-bit bus transceiver with direction pin; 5 V tolerant;

3-state

74LVC16245A;

74LVCH16245A

RECOMMENDED OPERATING CONDITIONS

SYMBOL

PARAMETER

supply voltage

CONDITIONS

for maximum speed

MIN.

2.7

MAX.

3.6

UNIT

V_CC

V

performance

for low voltage applications

1.2

0

3.6

5.5

V_CC

5.5

+125

20

V

V_I

input voltage

V

V_O

output voltage

output HIGH or LOW state

output 3-state

0

V

0

V

T_amb

t_r, t_f

operating ambient temperature

input rise and fall times

in free air

−40

0

°C

V_CC= 1.2 to 2.7 V

V_CC= 2.7 to 3.6 V

ns/V

0

10

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).

SYMBOL

PARAMETER

supply voltage

CONDITIONS

MIN.

−0.5

MAX.

+6.5

UNIT

V_CC

I_IK

V

input diode current

input voltage

V_I< 0

note 1

−

−50

mA

V

V_I

−0.5

−

+6.5

I_OK

V_O

output diode current

output voltage

V_O> V_CCor V_O< 0

±50

mA

V

output HIGH or LOW state;

note 1

−0.5

V_CC+ 0.5

output 3-state; note 1

V_O= 0 to V_CC

−0.5

−

+6.5

±50

V

I_O

output source or sink current

V_CCor GND current

storage temperature

power dissipation

mA

°C

I_CC, I_GND

−

±100

+150

T_stg

P_tot

−65

SSOP and TSSOP package

VFBGA package

T_amb= −40 to +125 °C; note 2

−

500

mW

T_amb= −40 to +125 °C; note 3

1000

Notes

1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. Above 60 °C the value of P_Dderates linearly with 5.5 mW/K.

3. Above 70 °C the value of P_Dderates linearly with 1.8 mW/K.

2003 Nov 25

8

Philips Semiconductors

Product speciﬁcation

16-bit bus transceiver with direction pin; 5 V tolerant;

3-state

74LVC16245A;

74LVCH16245A

DC CHARACTERISTICS

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

TEST CONDITIONS

SYMBOL

PARAMETER

MIN.

TYP. ⁽¹⁾

MAX.

UNIT

OTHER

V_CC(V)

T_amb= −40 to +85 °C

V_IH

V_IL

HIGH-level input voltage

1.2

V_CC

−

0

V

2.7 to 3.6 2.0

−

LOW-level input voltage

1.2

−

2.7 to 3.6

0.8

V_OH

HIGH-level output

voltage

V_I= V_IHor V_IL

I_O= −100 µA

I_O= −12 mA

I_O= −18 mA

I_O= −24 mA

2.7 to 3.6

2.7

V_CC− 0.2

V_CC− 0.5

V_CC− 0.6

V_CC− 0.8

V_CC

−

V

3.0

−

3.0

−

V_OL

LOW-level output voltage V_I= V_IHor V_IL

I_O= 100 µA

I_O= 12 mA

I_O= 24 mA

2.7 to 3.6

2.7

−

0

0.20

0.40

0.55

±5

V

−

3.0

−

I_LI

input leakage current

V_I= 5.5 V or GND 3.6

; notes 2 and 3

3-state output OFF-state V_I= V_IHor V_IL;

±0.1

µA

I_OZ

3.6

−

0.1

±5

µA

current

V_O= 5.5 V or GN

D

I_off

power off leakage supply V_Ior V_O= 5.5 V

0.0

−

0.1

±10

µA

I_CC

quiescent supply current V_I= V_CCor GND; 3.6

I_O= 0

10

∆I_CC

I_BHL

additional quiescent

supply current per pin

V_I=V_CC− 0.6 V;

I_O= 0

2.7 to 3.6

−

5

−

500

−

µA

bushold LOW sustaining V_I= 0.8 V;

current

3.0

75

notes 4, 5 and 6

I_BHH

bushold HIGH sustaining V_I= 2.0 V;

current

3.0

−75

500

−500

−

notes 4, 5 and 6

I_BHLO

I_BHHO

bushold LOW overdrive

current

notes 4, 5 and 7

3.6

−

bushold HIGH overdrive notes 4, 5 and 7

current

3.6

−

2003 Nov 25

9

Philips Semiconductors

Product speciﬁcation

16-bit bus transceiver with direction pin; 5 V tolerant;

3-state

74LVC16245A;

74LVCH16245A

TEST CONDITIONS

SYMBOL

PARAMETER

MIN.

TYP. ⁽¹⁾

MAX.

UNIT

OTHER

V_CC(V)

T_amb= −40 to +125 °C

V_IH

V_IL

HIGH-level input voltage

1.2

V_CC

−

V

2.7 to 3.6 2.0

−

LOW-level input voltage

1.2

−

GND

0.8

2.7 to 3.6

V_OH

HIGH-level output

voltage

V_I= V_IHor V_IL

I_O= −100 µA

I_O= −12 mA

I_O= −18 mA

I_O= −24 mA

2.7 to 3.6

2.7

V_CC− 0.3

V_CC− 0.65

V_CC− 0.75

V_CC− 1

−

V

3.0

V_OL

LOW-level output voltage V_I= V_IHor V_IL

I_O= 100 µA

I_O= 12 mA

I_O= 24 mA

2.7 to 3.6

2.7

−

0

−

0.3

0.6

0.8

±20

V

3.0

I_LI

input leakage current

V_I= 5.5 V or GND 3.6

; note 2

3-state output OFF-state V_I= V_IHor V_IL;

µA

I_OZ

3.6

−

±20

µA

current

V_O= 5.5 V or GN

D; notes 2 and 3

I_off

power off leakage supply V_Ior V_O= 5.5 V

0.0

−

±20

µA

I_CC

quiescent supply current V_I= V_CCor GND; 3.6

I_O= 0

40

∆I_CC

I_BHL

additional quiescent

supply current per pin

V_I=V_CC− 0.6 V;

I_O= 0

2.7 to 3.6

−

5000

µA

bushold LOW sustaining V_I= 0.8 V;

current

3.0

60

−

notes 4, 5 and 6

I_BHH

bushold HIGH sustaining V_I= 2.0 V;

current

3.0

−60

500

−500

notes 4, 5 and 6

I_BHLO

I_BHHO

bushold LOW overdrive

current

notes 4, 5 and 7

3.6

bushold HIGH overdrive notes 4, 5 and 7

current

3.6

Notes

1. All typical values are measured at V_CC= 3.3 V and T_amb= 25 °C.

2. For bushold parts, the bushold circuit is switched off when V_I> V_CCallowing 5.5 V on the input terminal.

3. For I/O ports the parameter I_OZincludes the input leakage current.

4. Valid for data inputs of bushold parts (74LVCH16245A) only.

5. For data inputs only, control inputs do not have a bushold circuit.

6. The specified sustaining current at the data input holds the input below the specified V_Ilevel.

7. The specified overdrive current at the data input forces the data input to the opposite input state.

2003 Nov 25

10

Philips Semiconductors

Product speciﬁcation

16-bit bus transceiver with direction pin; 5 V tolerant;

3-state

74LVC16245A;

74LVCH16245A

AC CHARACTERISTICS

GND = 0 V; t_r= t_f≤ 2.5 ns.

TEST CONDITIONS

SYMBOL

PARAMETER

MIN.

TYP.⁽¹⁾MAX.

UNIT

WAVEFORMS

V_CC(V)

T_amb= −40 to +85 °C

t_PHL/t_PLH

propagation delay nAn to nBn;

nBn to nAn

see Figs 6 and 8

1.2

2.7

3.0 to 3.6 1.0

−

13.0

2.7

2.2⁽²⁾

15.0

3.6

2.8⁽²⁾

11.0

3.4

−

ns

1.0

4.7

4.5

−

ns

t_PZH/t_PZL

3-state output enable time nOE see Figs 7 and 8

to nAn; nOE to nBn

1.2

2.7

−

1.5

6.7

5.5

−

3.0 to 3.6 1.0

t_PHZ/t_PLZ

3-state output disable time nOE see Figs 7 and 8

to nAn; nOE to nBn

1.2

2.7

−

1.5

6.6

5.6

3.0 to 3.6 1.5

3.2⁽²⁾

T_amb= −40 to +125 °C

t_PHL/t_PLHpropagation delay nAn to nBn;

nBn to nAn

see Figs 6 and 8

1.2

2.7

−

ns

1.0

6.0

−

3.0 to 3.6 1.0

t_PZH/t_PZL

3-state output enable time nOE see Figs 7 and 8

to nAn; nOE to nBn

1.2

2.7

−

1.5

8.5

7.0

−

3.0 to 3.6 1.0

t_PHZ/t_PLZ

3-state output disable time nOE see Figs 7 and 8

to nAn; nOE to nBn

1.2

2.7

−

1.5

8.5

7.0

3.0 to 3.6 1.5

Notes

1. All typical values are measured at T_amb= 25 °C.

2. Typical values are measured at V_CC= 3.3 V and T_amb= 25 °C.

2003 Nov 25

11

Philips Semiconductors

Product speciﬁcation

16-bit bus transceiver with direction pin; 5 V tolerant;

3-state

74LVC16245A;

74LVCH16245A

AC WAVEFORMS

V

handbook, halfpage

I

nAn, nBn

input

V

M

GND

t

PHL

PLH

V

OH

nBn, nAn

output

V

M

MNA477

V

OL

INPUT

V_CC

V_M

0.5 × V_CCV_CC

V_I

t_r= t_f

1.2 V

2.7 V

≤ 2.5 ns

1.5 V

2.7 V

3.0 to 3.6 V

V_OLand V_OHare typical output voltage drop that occur with the output load.

Fig.6 The input (nAn, nBn) to output (nBn, nAn) propagation delays.

2003 Nov 25

12

Philips Semiconductors

Product speciﬁcation

16-bit bus transceiver with direction pin; 5 V tolerant;

3-state

74LVC16245A;

74LVCH16245A

V

handbook, full pagewidth

I

nOE input

V

M

GND

t

PZL

PLZ

V

CC

output

LOW-to-OFF

OFF-to-LOW

V

M

V

X

V

OL

t

PHZ

PZH

V

OH

V

Y

output

HIGH-to-OFF

OFF-to-HIGH

V

M

GND

outputs

enabled

outputs

enabled

outputs

disabled

MNA362

INPUT

V_CC

V_M

0.5 × V_CCV_CC

V_I

t_r= t_f

V_X= V_OL+ 0.3 V at V_CC≥ 2.7 V;

V_X= V_OL+ 0.1 V at V_CC< 2.7 V.

V_Y= V_OH− 0.3 V at V_CC≥ 2.7 V;

V_Y= V_OH− 0.1 V at V_CC< 2.7 V.

1.2 V

≤ 2.5 ns

2.7 V

1.5 V

2.7 V

3.0 to 3.6 V

V_OLand V_OHare typical output voltage drop that occur with the output load.

Fig.7 3-state enable and disable times.

2003 Nov 25

13

Philips Semiconductors

Product speciﬁcation

16-bit bus transceiver with direction pin; 5 V tolerant;

3-state

74LVC16245A;

74LVCH16245A

V

handbook, full pagewidth

EXT

V

CC

R

L

V

O

I

PULSE

GENERATOR

D.U.T.

C

R

L

T

MNA616

V_EXT

t_PLH/t_PHLt_PZH/t_PHZt_PZL/t_PLZ

(1)

V_CC

V_I

V_CC

C_L

R_L

1.2 V

50 pF

500 Ω

open

GND

2 × V_CC

2.7 V

3.0 to 3.6 V

Note

1. The circuit performs better when R_L= 1000 Ω.

Definitions for test circuit:

R_L= Load resistor.

C_L= Load capacitance including jig and probe capacitance.

R_T= Termination resistance should be equal to the output impedance Z_oof the pulse generator.

Fig.8 Load circuitry for switching times.

2003 Nov 25

14

Philips Semiconductors

Product speciﬁcation

16-bit bus transceiver with direction pin; 5 V tolerant;

3-state

74LVC16245A;

74LVCH16245A

PACKAGE OUTLINES

SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm

SOT370-1

D

E

A

X

c

y

H

v

M

A

E

Z

25

48

Q

A

2

A

(A )

3

1

θ

pin 1 index

L

p

L

24

1

detail X

w

M

b

p

e

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

E

L

Q

v

w

y

Z

θ

p

1

2

3

max.

8^o

0^o

0.4

0.2

2.35

2.20

0.3

0.2

0.22 16.00

0.13 15.75

7.6

7.4

10.4

10.1

1.0

0.6

1.2

1.0

0.85

0.40

mm

2.8

0.25

0.635

1.4

0.25

0.18

0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT370-1

MO-118

2003 Nov 25

15

Philips Semiconductors

Product speciﬁcation

16-bit bus transceiver with direction pin; 5 V tolerant;

3-state

74LVC16245A;

74LVCH16245A

TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm

SOT362-1

E

D

A

X

c

H

v

M

A

y

E

Z

48

25

Q

A

2

(A )

3

A

1

pin 1 index

θ

L

p

L

detail X

1

24

w

M

b

e

p

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions).

A

(1)

(2)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

8^o

0^o

0.15

0.05

1.05

0.85

0.28

0.17

0.2

0.1

12.6

12.4

6.2

6.0

8.3

7.9

0.8

0.4

0.50

0.35

0.8

0.4

mm

1.2

0.25

0.5

1

0.25

0.08

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT362-1

MO-153

2003 Nov 25

16

Philips Semiconductors

Product speciﬁcation

16-bit bus transceiver with direction pin; 5 V tolerant;

3-state

74LVC16245A;

74LVCH16245A

VFBGA56: plastic very thin fine-pitch ball grid array package; 56 balls; body 4.5 x 7 x 0.65 mm

SOT702-1

B

A

D

ball A1

index area

A

2

A

E

A

1

detail X

e

1

C

v

M

C

A B

b

e

w

M

y

C

1

1/2

e

K

J

H

G

F

e

2

E

D

C

B

A

1/2

e

X

ball A1

index area

1

2

3

4

5

6

DIMENSIONS (mm are the original dimensions)

A

b

e

y

UNIT

D

E

e

v

w

y

1

2

0

2.5

5 mm

1

2

max.

0.3

0.2

0.7

0.6

0.45

0.35

4.6

4.4

7.1

6.9

scale

mm

1

3.25 5.85

0.08

0.1

0.65

0.15 0.08

REFERENCES

JEDEC JEITA

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

02-08-08

03-07-01

SOT702-1

MO-225

2003 Nov 25

17

Philips Semiconductors

Product speciﬁcation

16-bit bus transceiver with direction pin; 5 V tolerant;

3-state

74LVC16245A;

74LVCH16245A

DATA SHEET STATUS

DATA SHEET

STATUS⁽¹⁾

PRODUCT

STATUS⁽²⁾⁽³⁾

LEVEL

DEFINITION

I

Objective data

Development This data sheet contains data from the objective speciﬁcation for product

development. Philips Semiconductors reserves the right to change the

speciﬁcation in any manner without notice.

II

Preliminary data Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation.

Supplementary data will be published at a later date. Philips

Semiconductors reserves the right to change the speciﬁcation without

notice, in order to improve the design and supply the best possible

product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips

Semiconductors reserves the right to make changes at any time in order

to improve the design, manufacturing and supply. Relevant changes will

be communicated via a Customer Product/Process Change Notiﬁcation

(CPCN).

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was

published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

DEFINITIONS

DISCLAIMERS

Short-form specification

The data in a short-form

Life support applications

These products are not

specification is extracted from a full data sheet with the

same type number and title. For detailed information see

the relevant data sheet or data handbook.

designed for use in life support appliances, devices, or

systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips

Semiconductors customers using or selling these products

for use in such applications do so at their own risk and

agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Limiting values definition Limiting values given are in

accordance with the Absolute Maximum Rating System

(IEC 60134). Stress above one or more of the limiting

values may cause permanent damage to the device.

These are stress ratings only and operation of the device

at these or at any other conditions above those given in the

Characteristics sections of the specification is not implied.

Exposure to limiting values for extended periods may

affect device reliability.

Right to make changes

Philips Semiconductors

reserves the right to make changes in the products -

including circuits, standard cells, and/or software -

described or contained herein in order to improve design

and/or performance. When the product is in full production

(status ‘Production’), relevant changes will be

Application information

Applications that are

communicated via a Customer Product/Process Change

Notification (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these

products, conveys no licence or title under any patent,

copyright, or mask work right to these products, and

makes no representations or warranties that these

products are free from patent, copyright, or mask work

right infringement, unless otherwise specified.

described herein for any of these products are for

illustrative purposes only. Philips Semiconductors make

no representation or warranty that such applications will be

suitable for the specified use without further testing or

modification.

2003 Nov 25

18

Philips Semiconductors – a worldwide company

Contact information

For additional information please visit http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

For sales ofﬁces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.

SCA75

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

Printed in The Netherlands

R20/07/pp19

Date of release: 2003 Nov 25

Document order number: 9397 750 12155


型号：	VCH16245ADGG
厂家：	NXP
描述：	16-bit bus transceiver with direction pin; 5V tolerant 3-State 16位总线收发器的方向针; 5V容限三态总线驱动器总线收发器逻辑集成电路光电二极管
文件：	总19页 (文件大小：108K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

VCH16245ADGG [NXP]

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