VCH16374DGG-T_技术文档

INTEGRATED CIRCUITS

74LVC16374A/74LVCH16374A

16-bit edge triggered D-type flip-flop with

5 Volt tolerant inputs/outputs (3-State)

Product specification

1998 Mar 17

Supersedes data of 1997 Aug 22

IC24 Data Handbook

Philips

Semiconductors

Philips Semiconductors

Product specification

16-bit edge triggered D-type flip-flop with 5 Volt

tolerant inputs/outputs (3-State)

74LVC16374A/

74LVCH16374A

FEATURES

PIN CONFIGURATION

• 5 volt tolerant inputs/outputs for interfacing with 5V logic

48 1CP

1OE

1Q0

1Q1

1

2

3

• Wide supply voltage range of 1.2 V to 3.6 V

• Complies with JEDEC standard no. 8-1A

• CMOS low power consumption

47

46

45

1D0

1D1

GND

1Q2

4

5

TM

• MULTIBYTE flow-through standard pin-out architecture

44 1D2

43 1D3

• Low inductance multiple power and ground pins for minimum

1Q3

6

7

8

9

noise and ground bounce

42

41

40

V

CC

• Direct interface with TTL levels

1Q4

1Q5

1D4

1D5

• All data inputs have bus hold (74LVCH16374A only)

• High impedance when V = 0

CC

39 GND

38 1D6

37 1D7

GND 10

1Q6 11

1Q7 12

2Q0 13

2Q1 14

GND 15

2Q2 16

2Q3 17

DESCRIPTION

The 74LVC(H)16374A is a 16-bit edge-triggered flip-flop featuring

separate D-type inputs for each flip-flop and 3-State outputs for bus

oriented applications. The 74LVC16374A consists of 2 sections of

eight positive edge-triggered flip-flops. A clock (CP) input and an

output enable (OE) are provided for each octal. Inputs can be driven

from either 3.3V or 5V devices. In 3-State operation, outputs can

handle 5V. These features allow the use of these devices in a mixed

3.3V/5V environment.

36

2D0

35 2D1

34 GND

33 2D2

32 2D3

31

30

V

18

V

CC

The flip-flops will store the state of their individual D-inputs that meet

the set-up and hold time requirements on the LOW-to-HIGH CP

transition.

2D4

2Q4 19

2Q5 20

GND 21

2Q6 22

2Q7 23

2OE 24

29 2D5

28 GND

27 2D6

When OE is LOW, the contents of the flip-flops are available at the

outputs. When OE is HIGH, the outputs go to the high impedance

OFF-state. Operation of the OE input does not affect the state of the

flip-flops.

26

25

2D7

2CP

The 74LVCH16374A bus hold data inputs eliminates the need for

external pull up resistors to hold unused inputs.

SW00074

QUICK REFERENCE DATA

GND = 0V; T

= 25°C; t = t ≤ 2.5 ns

amb

r f

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

Propagation delay

Cp to Qn

C = 50pF

L

t

f

/t

3.8

ns

PHL PLH

V

CC

= 3.3V

Maximum clock frequency

Input capacitance

150

5.0

30

MHz

pF

MAX

C

I

1

Power dissipation capacitance per flip-flop

V

CC

= 3.3V

pF

PD

NOTES:

1. C is used to determine the dynamic power dissipation (P in mW):

PD

D

2

P

= C × V

× f + S (C × V

× f ) where:

D

PD

CC

i

L

CC o

f = input frequency in MHz; C = output load capacity in pF;

i

L

f = output frequency in MHz; V = supply voltage in V;

o

CC

2

S (C × V

× f ) = sum of outputs.

L

CC

o

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE OUTSIDE NORTH AMERICA

NORTH AMERICA

VC16374A DL

DWG NUMBER

SOT370-1

48-Pin Plastic SSOP Type III

48-Pin Plastic TSSOP Type II

48-Pin Plastic SSOP Type III

48-Pin Plastic TSSOP Type II

–40°C to +85°C

74LVC16374A DL

74LVC16374A DGG

74LVCH16374A DL

74LVCH16374A DGG

VC16374A DGG

VCH16374A DL

VCH16374A DGG

SOT362-1

SOT370-1

SOT362-1

2

1998 Mar 17

853-2028 19111

Philips Semiconductors

Product specification

74LVC16374A/

74LVCH16374A

16-bit edge triggered D-type flip-flop with 5 Volt

tolerant inputs/outputs (3-State)

PIN DESCRIPTION

LOGIC SYMBOL

PIN NUMBER

SYMBOL

NAME AND FUNCTION

1

24

Output enable input

(active LOW)

1

1OE

1Q0 to 1Q7

GND

1OE

2OE

47

2

1D0

1Q0

2, 3, 5, 6, 8, 9,

11, 12

3-State flip-flop outputs

46

44

1D1

1D2

1Q1

1Q2

3

5

4, 10, 15, 21,

28, 34, 39, 45

Ground (0V)

43

41

1D3

1D4

1Q3

1Q4

6

8

7, 18, 31, 42

V

CC

Positive supply voltage

3-State flip-flop outputs

40

38

37

1D5

1D6

1D7

1Q5

1Q6

1Q7

9

13, 14, 16, 17,

19, 20, 22, 23

11

12

2Q0 to 2Q7

Output enable input

(active LOW)

36

35

2D0

2D1

2Q0

2Q1

13

14

24

25

2OE

2CP

Clock input

Data inputs

33

32

2D2

2D3

2Q2

2Q3

16

17

36, 35, 33, 32,

30, 29, 27, 26

2D0 to 2D7

30

29

2D4

2D5

2Q4

2Q5

19

20

47, 46, 44, 43,

41, 40, 38, 37

1D0 to 1D7

1CP

Data inputs

Clock input

27

26

2D6

2D7

2Q6

2Q7

22

23

48

1CP

48

2CP

25

SW00075

LOGIC DIAGRAM

1D0

D

Q

1Q0

2D0

D

Q

2Q0

CP

FF1

FF9

1CP

1OE

2CP

2OE

TO 7 OTHER CHANNELS

SW00076

FUNCTION TABLE

INPUTS

OUTPUTS

INTERNAL

FLIP-FLOPS

OPERATING MODES

nOE

nCP

nDx

Q0 to Q7

L

°

l

h

L

H

L

H

Load and read register

H

°

l

h

L

H

Z

Load register and disable outputs

H = HIGH voltage level

h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition

L = LOW voltage level

l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition

Z = high impedance OFF-state

° = LOW-to-HIGH CP transition

3

1998 Mar 17

Philips Semiconductors

Product specification

74LVC16374A/

74LVCH16374A

16-bit edge triggered D-type flip-flop with 5 Volt

tolerant inputs/outputs (3-State)

LOGIC SYMBOL (IEEE/IEC)

BUS HOLD CIRCUIT

V

CC

1

1OE

1EN

C1

2EN

C2

48

24

25

1CLK

2OE

2CLK

47

46

44

43

2

3

5

1D0

1D1

1D2

1D3

1D4

1D5

1D6

1D7

2D0

1Q0

1Q1

1Q2

1Q3

1Q4

1Q5

1Q6

1Q7

2Q0

1D

1

Data Input

To internal circuit

6

8

9

41

40

38

37

11

12

SW00044

36

13

2D

2

35

33

14

16

2D1

2D2

2D3

2D4

2D5

2D6

2D7

2Q1

2Q2

2Q3

2Q4

2Q5

2Q6

2Q7

32

30

29

17

19

20

22

23

27

26

SW00077

RECOMMENDED OPERATING CONDITIONS

LIMITS

UNIT

SYMBOL

PARAMETER

CONDITIONS

MIN

2.7

1.2

0

MAX

DC supply voltage (for max. speed performance)

DC supply voltage (for low-voltage applications)

DC input voltage range

3.6

V

CC

V

3.6

V

I

5.5

V

DC input voltage range; output HIGH or LOW state

DC output voltage range; output 3-State

Operating free-air temperature range

0

V

CC

V

O

0

5.5

T

amb

–40

+85

°C

V

CC

V

CC

= 1.2 to 2.7V

= 2.7 to 3.6V

0

20

10

t , t

r

Input rise and fall times

ns/V

f

4

1998 Mar 17

Philips Semiconductors

Product specification

74LVC16374A/

74LVCH16374A

16-bit edge triggered D-type flip-flop with 5 Volt

tolerant inputs/outputs (3-State)

1

ABSOLUTE MAXIMUM RATINGS

In accordance with the Absolute Maximum Rating System (IEC 134).

Voltages are referenced to GND (ground = 0 V).

SYMBOL

PARAMETER

DC supply voltage

CONDITIONS

RATING

–0.5 to +6.5

–50

UNIT

V

CC

I

IK

DC input diode current

V t 0

mA

V

I

V

I

DC input voltage

Note 2

–0.5 to +6.5

"50

I

DC output diode current

V

O

uV or V t 0

mA

OK

CC

O

DC output voltage; output HIGH or LOW state

DC output voltage; output 3-State

DC output source or sink current

Note 2

–0.5 to V +0.5

CC

V

O

–0.5 to 6.5

"50

I

O

V

O

= 0 to V

CC

mA

°C

I

, I

DC V or GND current

"100

GND CC

CC

T

stg

Storage temperature range

–65 to +150

Power dissipation per package

– plastic mini-pack (SO)

– plastic shrink mini-pack (SSOP and TSSOP)

P

TOT

above +70°C derate linearly with 8 mW/K

above +60°C derate linearly with 5.5 mW/K

500

mW

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the

device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to

absolute-maximum-rated conditions for extended periods may affect device reliability.

2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

DC ELECTRICAL CHARACTERISTICS

Over recommended operating conditions voltages are referenced to GND (ground = 0V)

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

Temp = -40°C to +85°C

UNIT

1

MIN

TYP

MAX

V

= 1.2V

V

CC

V

HIGH level Input voltage

LOW level Input voltage

V

IH

= 2.7 to 3.6V

= 1.2V

2.0

GND

0.8

V

IL

= 2.7 to 3.6V

= 2.7V; V = V or V ; I = –12mA

V

*0.5

I

IH

IL

O

CC

= 3.0V; V = V or V ; I = –100µA

*0.2

*0.6

*0.8

V

CC

I

IH

IL

O

V

OH

HIGH level output voltage

LOW level output voltage

V

= 3.0V; V = V or V I

= –18mA

I = –24mA

I

IH

IL; O

= 3.0V; V = V or V

IL; O

I

IH

= 2.7V; V = V or V ; I = 12mA

0.40

0.20

0.55

"5

I

IH

IL

O

= 3.0V; V = V or V ; I = 100µA

V

OL

V

I

IH

IL

O

= 3.0V; V = V or V

I

= 24mA

I

IH

IL;

6

I

Input leakage current

= 3.6V; V = 5.5V or GND

"0.1

µA

I

3-State output OFF-state current

Power off leakage supply

Quiescent supply current

= 3.6V; V = V or V ; V = 5.5V or GND

0.1

"5

OZ

I

IH

IL

O

I

off

= 0.0V; V or V = 5.5V

"10

20

I

O

I

= 3.6V; V = V or GND; I = 0

0.1

5

CC

I

CC

O

Additional quiescent supply

current per input pin

∆I

CC

V

CC

= 2.7V to 3.6V; V = V –0.6V; I = 0

500

µA

I

CC

O

5

1998 Mar 17

Philips Semiconductors

Product specification

74LVC16374A/

74LVCH16374A

16-bit edge triggered D-type flip-flop with 5 Volt

tolerant inputs/outputs (3-State)

DC ELECTRICAL CHARACTERISTICS (Continued)

Over recommended operating conditions voltages are referenced to GND (ground = 0V)

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

Temp = -40°C to +85°C

UNIT

1

MIN

75

TYP

MAX

2, 3, 4

I

Bus hold LOW sustaining current

Bus hold HIGH sustaining current

Bus hold LOW overdrive current

Bus hold HIGH overdrive current

V

CC

V

CC

V

CC

V

CC

= 3.0V; V = 0.8V

µA

BHL

I

2, 3, 4

I

= 3.0V; V = 2.0V

–75

500

–500

BHH

I

2, 3, 5

I

= 3.6V

BHLO

BHHO

2, 3, 5

I

= 3.6V

NOTES:

1. All typical values are at V = 3.3V and T

= 25°C.

amb

CC

2. Valid for data inputs of bus hold parts (LVCH16-A) only.

3. For data inputs only, control inputs do not have a bus hold circuit.

4. The specified sustaining current at the data input holds the input below the specified V level.

I

5. The specified overdrive current at the data input forces the data input to the opposite logic input state.

6. For bus hold parts, the bus hold circuit is switched off when V exceeds V allowing 5.5V on the input terminal.

i

CC

AC CHARACTERISTICS

GND = 0V; t = t = 2.5ns; C = 50pF; R = 500Ω; T

= –40°C to +85°C.

R

F

L

amb

LIMITS

SYMBOL

PARAMETER

WAVEFORM

V

CC

= 3.3V ±0.3V

V

CC

= 2.7V

V = 1.2V

CC

UNIT

1

MIN

TYP

MAX

MIN

MAX

t

Propagation delay

CP to Qn

PHL

PLH

1, 4

2, 4

1

1.5

3.0

3.8

5.4

5.6

5.5

–

1.5

6.4

6.6

6.5

–

17

20

12

–

ns

t

3-State output enable time

OE to Qn

PZH

3.6

3.9

1.5

3.0

t

PZL

t

3-State output disable time

OE to Qn

PHZ

t

PLZ

CP pulse width

HIGH or LOW

t

W

t

Set-up time Dn to CP

Hold time Dn to CP

3

2.0

1.5

0.3

–

1.9

1.1

–

ns

su

t

–0.3

h

Maximum clock pulse

frequency

f

1

100

–

80

–

MHz

max

NOTE:

1. All typical values are at V = 3.3V and T

= 25°C.

amb

CC

6

1998 Mar 17

Philips Semiconductors

Product specification

74LVC16374A/

74LVCH16374A

16-bit edge triggered D-type flip-flop with 5 Volt

tolerant inputs/outputs (3-State)

AC WAVEFORMS

V

= 1.5V at V w 2.7V; V = 0.5 V at V t 2.7V.

M

CC M CC CC

and V are the typical output voltage drop that occur with the

OL

OH

output load.

V

X

V

Y

= V + 0.3V at V w 2.7V; V = V + 0.1 V at V t2.7V

OL CC X OL CC CC

= V –0.3V at V w2.7V; V = V – 0.1 V at V t2.7V

OH

CC

Y

OH

CC

V

I

1/f

MAX

CP

INPUT

V

M

V

I

GND

CP INPUT

GND

V

M

t

su

t

su

t

h

t

h

w

t

PLH

PHL

V

I

V

OH

Dn

V

M

Qn OUTPUT

INPUT

V

M

GND

V

OL

SW00078

V

OH

Qn

OUTPUT

Waveform 1. Clock (CP) to output (Qn) propagation delays, the

clock pulse width and the maximum clock pulse frequency

V

M

V

OL

NOTE: The shaded areas indicate when the input is permitted to change

V

I

for predictable output performance.

SW00079

V

OE INPUT

GND

V

M

Waveform 3. Data set-up and hold times for the Dn input to the

CP input

TEST CIRCUIT

t

PZL

PLZ

V

CC

S

1

V

OUTPUT

LOW-to-OFF

OFF-to-LOW

2<V

CC

V

Open

M

GND

V

X

V

OL

R =500 Ω

L

V

OUT

IN

PULSE

GENERATOR

t

D.U.T.

PHZ

PZH

V

OH

R =500 Ω

L

R

C

T

V

L

Y

OUTPUT

HIGH-to-OFF

OFF-to-HIGH

V

M

GND

Test Circuit for 3-State Outputs

SWITCH POSITION

outputs

enabled

outputs

disabled

outputs

enabled

V

IN

SW00072

TEST

SWITCH

Open

CC

Waveform 2. 3-State enable and disable times

t 2.7V

2.7 – 3.6V 2.7V

V

CC

t

/t

PLH PHL

t

/t

2<V

CC

PLZ PZL

t

/t

GND

PHZ PZH

DEFINITIONS

R = Load resistor

L

C = Load capacitance includes jig and probe capacitance

L

R = Termination resistance should be equal to Z

T

OUT

of pulse generators.

SW00047

Waveform 4. Load circuitry for switching times

7

1998 Mar 17

Philips Semiconductors

Product specification

16-bit edge triggered D-type flip-flop with 5 Volt

tolerant inputs/outputs (3-State)

74LVC16374A/

74LVCH16374A

SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm

SOT370-1

8

1998 Mar 17

Philips Semiconductors

Product specification

16-bit edge triggered D-type flip-flop with 5 Volt

tolerant inputs/outputs (3-State)

74LVC16374A/

74LVCH16374A

TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1mm

SOT362-1

9

1998 Mar 17

Philips Semiconductors

Product specification

16-bit edge triggered D-type flip-flop with 5 Volt

tolerant inputs/outputs (3-State)

74LVC16374A/

74LVCH16374A

DEFINITIONS

Data Sheet Identification

Product Status

Definition

This data sheet contains the design target or goal specifications for product development. Specifications

may change in any manner without notice.

Objective Specification

Formative or in Design

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips

Semiconductors reserves the right to make changes at any time without notice in order to improve design

and supply the best possible product.

Preliminary Specification

Product Specification

Preproduction Product

Full Production

This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes

at any time without notice, in order to improve design and supply the best possible product.

Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,

including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips

Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,

or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask

work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes

only. PhilipsSemiconductorsmakesnorepresentationorwarrantythatsuchapplicationswillbesuitableforthespecifiedusewithoutfurthertesting

or modification.

LIFE SUPPORT APPLICATIONS

Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,

orsystemswheremalfunctionofaPhilipsSemiconductorsandPhilipsElectronicsNorthAmericaCorporationProductcanreasonablybeexpected

to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips

Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully

indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.

Philips Semiconductors

811 East Arques Avenue

P.O. Box 3409

Copyright Philips Electronics North America Corporation 1998

Sunnyvale, California 94088–3409

Telephone 800-234-7381

print code

Date of release: 05-96

9397-750-04534

Document order number:

Philips

Semiconductors

10

yyyy mmm dd


型号：	VCH16374DGG-T
厂家：	NXP
描述：	暂无描述触发器
文件：	总10页 (文件大小：85K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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