WCT1013A [NXP]
Compliant with the latest version Wireless Power Consortium (WPC) power class 0 specification power transmitter design;
| 型号： | WCT1013A |
| 厂家： | 
NXP |
| 描述： | Compliant with the latest version Wireless Power Consortium (WPC) power class 0 specification power transmitter design PC 无线 |
| 文件： | 总43页 (文件大小：1260K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: WCT101XADS
Rev. 1.1, 01/2021
NXP Semiconductors
Data Sheet
Overview Description
WCT101XADS
Features
The WCT101xA is a wireless power transmitter controller
that integrates all required functions for WPC “Qi”
compliant wireless power transmitter design. It is an
intelligent device that works with the NXP touch sensing
technology or uses periodically analog PING to detect a
mobile device for charging while gaining super low standby
power. Once the mobile device is detected, the WCT101xA
controls the power transfer by adjusting the rail voltage, the
phase difference, or the duty cycle of the power stage
according to message packets sent by the mobile device.
•
Compliant with the latest version Wireless Power
Consortium (WPC) power class 0 specification power
transmitter design
Supports wide transmitter DC input voltage range of 6V
(limited duration at Start/Stop operation) to 16V
Integrated digital demodulation
Supports two-way communication, transmitter to
receiver by FSK and receiver to transmitter by ASK
Supports Q factor detection and calibrated power loss
based Foreign Object Detection (FOD) framework
Supports low standby power
Uses rail voltage control, phase difference control or
duty cycle control with the fixed operation frequency to
alleviate EMI in automotive system
Supports key FOB avoidance function
Supports operation frequency dithering technology to
eliminate AM band interference
Supports CAN/LIN/IIC/SCI/SPI interfaces
LED for system status indication
Over-voltage/current/temperature protection
Software based solution to provide maximum design
freedom and product differentiation
•
•
•
•
To maximize the design freedom and product differentiation,
the WCT101xA supports the extended power profile
consumer power transmitter design (WPC MP-Ax types,
MP-Bx types or customization) using the fixed operation
frequency control methods such as rail voltage control,
phase difference control or duty cycle control etc. by
software based solution, which can support wireless
charging with both extended power profile power receiver
and baseline power profile power receiver. In addition, the
easy-to-use FreeMASTER GUI tool has configuration,
calibration and debugging functions to provide the
•
•
•
•
•
•
•
•
user-friendly design experience and reduce time-to-market.
The WCT101xA includes a digital demodulation module to
reduce the external components, an FSK modulation module
to support two-way communication, a protection module to
handle the over-voltage/current/temperature protection, an
FOD module to protect from overheating by misplaced
metallic foreign objects, and general CAN/IIC/SCI/SPI
interfaces for external communications. It also handles any
abnormal condition and operational status and provides
comprehensive indicator outputs for robust system design.
•
Qualified to AEC100 Test Group A&B
Applications
•
Automotive Extended Power Profile Power Transmitter
WPC compliant or customer properties
o
Wireless Charging System Functional Diagram
© 2021 NXP B.V.
Contents
1
Absolute Maximum Ratings ....................................................................................................................4
Electrical operating ratings......................................................................................................................................4
Thermal handling ratings ........................................................................................................................................5
ESD handling ratings ...............................................................................................................................................5
Moisture handling ratings .......................................................................................................................................5
1.1
1.2
1.3
1.4
2
Electrical Characteristics .........................................................................................................................6
General characteristics............................................................................................................................................6
Device characteristics..............................................................................................................................................8
Thermal operating characteristics.........................................................................................................................22
2.1
2.2
2.3
3
Typical Performance Characteristics ............................................................................................... 23
System efficiency ..................................................................................................................................................23
Standby power......................................................................................................................................................23
Digital demodulation ............................................................................................................................................23
Two-way communication......................................................................................................................................23
Foreign object detection .......................................................................................................................................23
3.1
3.2
3.3
3.4
3.5
4
Device Information ................................................................................................................................. 24
Functional block diagram ......................................................................................................................................24
Product features overview....................................................................................................................................24
Pinout diagram .....................................................................................................................................................26
Pin function description ........................................................................................................................................26
4.1
4.2
4.3
4.4
WCT101XADS, Rev. 1.1, 01/2021
2
NXP Semiconductors
4.5
4.6
Ordering information............................................................................................................................................37
Package outline drawing .......................................................................................................................................37
5
Software Library ...................................................................................................................................... 38
Memory map ........................................................................................................................................................38
Software library and API description.....................................................................................................................38
5.1
5.2
6
Design Considerations ........................................................................................................................... 39
Electrical design considerations ............................................................................................................................39
PCB layout considerations.....................................................................................................................................40
Thermal design considerations..............................................................................................................................40
6.1
6.2
6.3
7
8
Links............................................................................................................................................................. 42
Revision History....................................................................................................................................... 42
9
Addendum for MWCT1011A3VLH ..................................................................................................... 42
Ordering information............................................................................................................................................42
Package outline drawing .......................................................................................................................................42
9.1
9.2
WCT101XADS, Rev. 1.1, 01/2021
NXP Semiconductors
3
1 Absolute Maximum Ratings
1.1 Electrical operating ratings
Table 1. Absolute maximum electrical ratings (VSS = 0 V, VSSA = 0 V)
Characteristic
Supply Voltage Range
Symbol
VDD
Notes1
Min.
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.4
–0.3
–
Max.
4.0
Unit
V
Analog Supply Voltage Range
ADC High Voltage Reference
Voltage difference VDD to VDDA
Voltage difference VSS to VSSA
Digital Input Voltage Range
VDDA
VREFHx
ΔVDD
ΔVss
4.0
V
V
4.0
V
V
V
V
V
V
0.3
0.3
VIN
Pin Group 1
Pin Group 2
Pin Group 4
Pin Group 3
5.5
RESET Input Voltage Range
VIN_RESET
VOSC
VINA
4.0
Oscillator Input Voltage Range
Analog Input Voltage Range
4.0
4.0
Input clamp current, per pin (VIN < VSS – 0.3 V)2, 3
Output clamp current, per pin4
VIC
–5.0
±20.0
mA
mA
VOC
–
Contiguous pin DC injection current—regional limit
IIcont
–25
25
mA
sum of 16 contiguous pins
–0.3
–0.3
–0.3
–0.3
4.0
5.5
4.0
4.0
Output Voltage Range (normal push-pull mode)
Output Voltage Range (open drain mode)
RESET Output Voltage Range
VOUT
VOUTOD
VOUTOD_RESET
VOUT_DAC
TA
Pin Group 1,2
Pin Group 1
Pin Group 2
Pin Group 5
V
V
V
DAC Output Voltage Range
V
Ambient Temperature
–40
–55
105
150
°C
°C
Storage Temperature Range
TSTG
1. Default Mode:
•
•
•
•
•
Pin Group 1: GPIO, TDI, TDO, TMS, TCK
Pin Group 2: RESET
Pin Group 3: ADC and Comparator Analog Inputs
Pin Group 4: XTAL, EXTAL
Pin Group 5: DAC analog output
2. Continuous clamp current.
3. All 5 volt tolerant digital I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode connection to VDD
If VIN greater than VDIO_MIN (=VSS –0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If this
limit cannot be observed, then a current limiting resistor is required.
.
4. I/O is configured as push-pull mode.
WCT101XADS, Rev. 1.1, 01/2021
4
NXP Semiconductors
1.2 Thermal handling ratings
Table 2. Thermal handling ratings
Symbol
TSTG
Description
Storage temperature
Solder temperature, lead-free
Min.
–55
–
Max.
150
Unit
°C
Notes
1
2
TSDR
260
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State
Surface Mount Devices.
1.3 ESD handling ratings
Table 3. ESD handling ratings
Characteristic1
Min.
-2000
-200
-500
-100
Max.
+2000
+200
+500
+100
Unit
V
ESD for Human Body Model (HBM)
ESD for Machine Model (MM)
ESD for Charge Device Model (CDM)
V
V
Latch-up current at TA= 85°C (ILAT
)
mA
1. Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless
otherwise noted.
1.4 Moisture handling ratings
Table 4. Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
–
3
–
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State
Surface Mount Devices.
WCT101XADS, Rev. 1.1, 01/2021
NXP Semiconductors
5
2 Electrical Characteristics
2.1 General characteristics
Table 5. General electrical characteristics
Recommended operating conditions (VREFLx = 0 V, VSSA = 0 V, VSS = 0 V)
Test
Characteristic
Supply Voltage2
Symbol
Notes
Min.
Typ.
Max.
Unit
conditions
-
VDD ,VDDA
-
2.7
3.3
3.6
V
VREFHA
VREFHB
ADC (Cyclic) Reference
Voltage High
-
-
3.0
2.0
-
-
VDDA
V
V
ADC (SAR) Reference
Voltage High
-
VREFHC
3
VDDA
V
V
-
-
Voltage difference VDD to VDDA
Voltage difference VSS to VSSA
ΔVDD
ΔVss
-
-
-0.1
-0.1
0
0
0.1
0.1
Input Voltage High (digital
inputs)
V
V
V
-
-
-
VIH
VIH_RESET
VIL
1 (Pin Group 1)
1 (Pin Group 2)
1 (Pin Group 1,2)
0.7×VDD
0.7×VDD
-
-
-
-
5.5
VDD
RESET Voltage High
Input Voltage Low (digital
inputs)
0.35×VDD
Oscillator Input Voltage High
V
V
-
-
VIHOSC
1 (Pin Group 4)
1 (Pin Group 4)
2.0
-
-
VDD + 0.3
0.8
XTAL driven by an external
clock source
Oscillator Input Voltage Low
VILOSC
-0.3
Output Source Current High
(at VOH min.) 4,5
• Programmed for low
-
IOH
1 (Pin Group 1)
1 (Pin Group 1)
-
-
-
-2
-9
drive strength
mA
• Programmed for high
drive strength
WCT101XADS, Rev. 1.1, 01/2021
6
NXP Semiconductors
Output Source Current Low
(at VOL max.) 4,5
• Programmed for low
IOL
1 (Pin Group 1,2)
1 (Pin Group 1,2)
-
-
2
9
drive strength
mA
• Programmed for high
drive strength
Output Voltage High
Output Voltage Low
VOH
VOL
1 (Pin Group 1)
VDD - 0.5
-
-
-
-
V
V
IOH = IOHmax
IOL = IOLmax
1 (Pin Group 1,2)
0.5
VIN = 2.4 V
to 5.5 V
1 (Pin Group 1)
1 (Pin Group 2)
Digital Input Current High
pull-up enabled or disabled
IIH
-
-
0
0
+/-2.5
+/-2
µA
VIN = 2.4 V
to VDD
Comparator Input Current
High
VIN = VDDA
IIHC
1 (Pin Group 3)
µA
µA
Oscillator Input Current High
VIN = VDDA
IIHOSC
RPull-Up
1 (Pin Group 4)
-
0
-
+/-2
50
-
-
Internal Pull-Up Resistance
Internal Pull-Down Resistance
-
-
20
20
kΩ
kΩ
RPull-Down
-
50
Comparator Input Current
Low
VIN = 0V
VIN = 0V
IILC
1 (Pin Group 3)
1 (Pin Group 4)
-
-
0
0
+/-2
+/-2
µA
µA
Oscillator Input Current Low
IILOSC
RLD = 3 kΩ,
CLD = 400
pF
VSSA
+
VDDA -
DAC Output Voltage Range
V
VDAC
1 (Pin Group 5)
-
0.04
0.04
Output Current1 High
Impedance State
IOZ
1 (Pin Group 1,2)
1 (Pin Group 1,2)
-
0
-
+/-1
µA
V
-
-
Schmitt Trigger Input
Hysteresis
VHYS
0.06×VDD
-
Input capacitance
Output capacitance
CIN
-
-
-
-
10
10
-
-
pF
pF
-
-
COUT
GPIO pin interrupt pulse
width6
Bus
TINT_Pulse
7
1.5
-
-
-
clock
Port rise and fall time (high
drive strength). Slew
disabled.
2.7 ≤ VDD ≤
TPort_H_DIS
8
8
5.5
1.5
-
-
15.1
6.8
ns
ns
3.6 V
Port rise and fall time (high
drive strength). Slew enabled.
2.7 ≤ VDD ≤
TPort_H_EN
3.6 V
WCT101XADS, Rev. 1.1, 01/2021
NXP Semiconductors
7
Port rise and fall time (low
drive strength). Slew
disabled.
2.7 ≤ VDD ≤
TPort_L_DIS
9
9
8.2
3.2
-
-
17.8
9.2
ns
ns
3.6 V
Port rise and fall time (low
drive strength). Slew enabled.
2.7 ≤ VDD ≤
TPort_L_EN
fSYSCLK
fBUS
3.6 V
Device (system and core)
clock frequency
-
0
-
-
-
100
MHz
MHz
-
-
Bus clock
10
50/100
1. Default Mode
o
Pin Group 1: GPIO, TDI, TDO, TMS, TCK
o
o
o
o
Pin Group 2: RESET
Pin Group 3: ADC and Comparator Analog Inputs
Pin Group 4: XTAL, EXTAL
Pin Group 5: DAC analog output
2. ADC (Cyclic) specifications are not guaranteed when VDDA is below 3.0 V.
3. ADC (SAR) is only on WCT1013A device.
4. Total chip source or sink current cannot exceed 75 mA.
5. Contiguous pin DC injection current of regional limit—including sum of negative injection currents or sum of positive injection
currents of 16 contiguous pins—is 25 mA.
6. Applies to a pin only when it is configured as GPIO and configured to cause an interrupt by appropriately programming GPIOn_IPOLR
and GPIOn_IENR.
7. The greater synchronous and asynchronous timing must be met.
8. 75 pF load
9. 15 pF load
10. WCT1011A only supports the maximum bus clock of 50 MHz, and WCT1013A supports 100 MHz maximum bus clock.
2.2 Device characteristics
Table 6. General device characteristics
Power mode transition Behavior
Symbol
Description
Min.
Max.
Unit
Notes
After a POR event, the amount of delay
from when VDD reaches 2.7 V to when the
first instruction executes (over the
operating temperature range).
TPOR
199
225
µs
-
TS2R
STOP mode to RUN mode
6.79
240.9
1424
0.57
7.27
551
µs
µs
µs
µs
µs
µs
1
2
4
3
2
4
TLPS2LPR
TVLPS2VLPR
TW2R
LPS mode to LPRUN mode
VLPS mode to VLPRUN mode
WAIT mode to RUN mode
1459
0.62
554
TLPW2LPR
TVLPW2VLPR
LPWAIT mode to LPRUN mode
VLPWAIT mode to VLPRUN mode
237.2
1413
1500
Power consumption operating behaviors
WCT101XADS, Rev. 1.1, 01/2021
8
NXP Semiconductors
Typical at 3.3 V, 25 °C
Mode
Conditions
Max. frequency
Notes
IDD
IDDA
100 MHz core clock, 50 MHz peripheral
clock, regulators are in full regulation,
relaxation oscillator on, PLL powered on,
continuous MAC instructions with fetches
from program Flash, all peripheral modules
enabled, TMRs and SCIs using 1×
peripheral clock, NanoEdge within
eFlexPWM using 2× peripheral clock,
ADC/DAC (only one 12-bit DAC and all
6-bit DACs) powered on and clocked,
comparator powered on, all ports
configured as inputs with input low and no
DC loads
RUN1
100 MHz
38.1 mA/-
9.9 mA/-
5
50 MHz/100 MHz5 core and peripheral
clock, regulators are in full regulation,
relaxation oscillator on, PLL powered on,
continuous MAC instructions with fetches
from program Flash, all peripheral modules
enabled, TMRs and SCIs using 1×
peripheral clock, NanoEdge within
eFlexPWM using 2× peripheral clock,
ADC/DAC (only one 12-bit DAC and all
6-bit DACs) powered on and clocked,
comparator powered on, all ports
configured as inputs with input low and no
DC loads
9.9
mA/16.7
mA
50 MHz/100
MHz5
27.6 mA/63.7
mA
RUN2
5
50 MHz/100 MHz5 core and peripheral
clock, regulators are in full regulation,
relaxation oscillator on, PLL powered on,
core in WAIT state, all peripheral modules
enabled, TMRs and SCIs using 1× clock,
NanoEdge within eFlexPWM using 2×
clock, ADC/DAC (one 12-bit DAC, all 6-bit
DACs)/comparator powered off, all ports
configured as inputs with input low and no
DC loads
50 MHz/100
MHz5
24.0 mA/43.5
mA
-/-
WAIT
5
4 MHz core and peripheral clock,
regulators are in full regulation, relaxation
oscillator on, PLL powered off, core in
STOP state, all peripheral module and
core clocks are off, ADC/DAC/Comparator
powered off, all ports configured as inputs
with input low and no DC loads
-/-
STOP
4 MHz
6.3 mA/10.1 mA
5
WCT101XADS, Rev. 1.1, 01/2021
NXP Semiconductors
9
200 kHz core and peripheral clock from
relaxation oscillator's low speed clock,
relaxation oscillator in standby mode,
regulators are in standby, PLL disabled,
repeat NOP instructions, all peripheral
modules enabled, except NanoEdge within
eFlexPWM and cyclic ADCs, one 12-bit
DAC and all 6-bit DACs enabled, simple
loop with running from platform instruction
buffer, all ports configured as inputs with
input low and no DC loads
3.1
mA/2.73
mA
LPRUN
2 MHz
2.8 mA/2.3 mA
5
200 kHz core and peripheral clock from
relaxation oscillator's low speed clock,
relaxation oscillator in standby mode,
regulators are in standby, PLL disabled, all
peripheral modules enabled, except
NanoEdge within eFlexPWM and cyclic
ADCs, one 12-bit DAC and all 6-bit DACs
enabled, core in WAIT mode, all ports
configured as inputs with input low and no
DC loads
3.1
mA/2.73
mA
LPWAIT
2 MHz
2.7 mA/2.29 mA
5
200 kHz core and peripheral clock from
relaxation oscillator's low speed clock,
relaxation oscillator in standby mode,
regulators are in standby, PLL disabled,
only PITs and COP enabled, other
peripheral modules disabled and clocks
gated off, core in STOP mode, all ports
configured as inputs with input low and no
DC loads
-
LPSTOP
2 MHz
1.2 mA/1.55 mA
5
32 kHz core and peripheral clock from a 64
kHz external clock source, oscillator in
power down, all relaxation oscillators
disabled, large regulator is in standby,
small regulator is disabled, PLL disabled,
repeat NOP instructions, all peripheral
modules, except COP and EWM, disabled
and clocks gated off, simple loop running
from platform instruction buffer, all ports
configured as inputs with input low and no
DC loads
-/-
VLPRUN
200 kHz
0.7 mA/1.18 mA
5
32 kHz core and peripheral clock from a 64
kHz external clock source, oscillator in
power down, all relaxation oscillators
disabled, large regulator is in standby,
small regulator is disabled, PLL disabled,
all peripheral modules, except COP,
disabled and clocks gated off, core in
WAIT mode, all ports configured as inputs
with input low and no DC loads
-/-
VLPWAIT
200 kHz
0.7 mA/1.1 mA
5
WCT101XADS, Rev. 1.1, 01/2021
10
NXP Semiconductors
32 kHz core and peripheral clock from a 64
kHz external clock source, oscillator in
power down, all relaxation oscillators
disabled, large regulator is in standby,
small regulator is disabled, PLL disabled,
all peripheral modules, except COP,
disabled and clocks gated off, core in
STOP mode, all ports configured as inputs
with input low and no DC loads
-/-
VLPSTOP
200 kHz
0.7 mA/1.03 mA
5
Reset and interrupt timing
Symbol
Characteristic
Min.
Max.
Unit
Notes
tRA
Minimum RESET Assertion Duration
16
-
ns
6
865 × TOSC + 8 ×
TSYSCLK
tRDA
RESET desertion to First Address Fetch
-
ns
ns
7
-
Delay from Interrupt Assertion to Fetch of
first instruction (exiting STOP mode)
tIF
361.3
570.9
PMC Low-Voltage Detection (LVD) and Power-On Reset (POR) parameters
Symbol
VPOR_A
Characteristic
POR Assert Voltage8
Min.
Typ.
2.0
Max.
Unit
V
-
-
-
-
-
-
-
-
VPOR_R
POR Release Voltage9
2.7
V
VLVI_2p7
LVI_2p7 Threshold Voltage
LVI_2p2 Threshold Voltage
2.73
2.23
V
VLVI_2p2
V
JTAG timing
Symbol
Description
Min.
Max.
Unit
MHz
ns
Notes
fOP
TCK frequency of operation
DC
fSYSCLK/8 (16)
10
-
tPW
tDS
tDH
tDV
tTS
TCK clock pulse width
50
5
5
-
-
-
TMS, TDI data set-up time
TMS, TDI data hold time
TCK low to TDO data valid
TCK low to TDO tri-state
ns
-
-
ns
-
30
30
ns
-
-
ns
-
Regulator 1.2 V parameters
Symbol
Characteristic
Min.
Typ.
1.22
600
Max.
Unit
V
VCAP
ISS
Output Voltage11
Short Circuit Current12
-
-
-
-
mA
Short Circuit Tolerance (VCAP shorted to
ground)
TRSC
-
-
30
Mins
WCT101XADS, Rev. 1.1, 01/2021
NXP Semiconductors
11
VREF
Reference Voltage (after trim)
-
1.21
-
V
External clock timing
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Frequency of operation (external clock
driver)
fOSC
-
-
50
MHz
tPW
trise
tfall
Clock pulse width13
8
-
ns
ns
ns
External clock input rise time14
External clock input fall time15
-
-
1
1
-
Input high voltage overdrive by an external
clock
Vih
Vil
0.85×VDD
-
-
-
-
V
V
Input low voltage overdrive by an external
clock
0.3×VDD
Phase-Locked Loop (PLL) timing
Symbol
fRef_PLL
fOP_PLL
tLock_PLL
tDC_PLL
Characteristic
Min.
8
Typ.
Max.
16
Unit
MHz
MHz
µs
PLL input reference frequency16
PLL output frequency17
8
-
200/240
35.5
40
400
73.2
60
PLL lock time18
-
Allowed Duty Cycle of input reference
50
%
External crystal or resonator specifications
Symbol
Characteristic
Frequency of operation
Min.
Typ.
Max.
Unit
fXOSC
4
8
16
MHz
Relaxation oscillator electrical specifications
Symbol
Characteristic
Min.
Typ.
Max.
Unit
8 MHz Output Frequency20
RUN Mode
7.84
7.76
8
8
8.16
8.24
MHz
MHz
• 0 °C to 105 °C
fROSC_8M
• -40 °C to 105 °C
Standby Mode (IRC trimmed @ 8 MHz)
• -40 °C to 105 °C
-
405
-
kHz
8 MHz Frequency Variation over 25 °C
RUN Mode
fROSC_8M_Delta
Due to temperature
• 0 °C to 105 °C
-
-
+/-1.5
+/-1.5
+/-2
+/-3
%
%
• -40 °C to 105 °C
200 kHz/32 kHz Output Frequency19,21
RUN Mode
19,
fROSC_200k/32k
20
194/30.1
200/32
206/33.9
kHz
• -40 °C to 105 °C
WCT101XADS, Rev. 1.1, 01/2021
12
NXP Semiconductors
200 kHz/32 kHz Output Frequency
Variation over 25 °C 19,21
RUN Mode
fROSC_200k/32k_D
19,20
elta
Due to temperature
• 0 °C to 85 °C
• -40 °C to 105 °C 22
-
-
+/-1.5
+/-2
%
%
+/-1.5 (2.5)
+/-3 (4)
Stabilization Time
tStab
• 8 MHz output23
• 200 kHz/32 kHz output19,24
0.12
µs
µs
-
-
-
-
10/14.4
tDC_ROSC
Output Duty Cycle
48
50
52
%
Flash specifications
Symbol
Description
Min.
Typ.
7.5
13
Max.
18
Unit
µs
thvpgm4
thversscr
thversall
Longword Program high-voltage time
Sector Erase high-voltage time25
Erase All high-voltage time25,26
-
-
-
113
452
ms
ms
52
Erase Block high-voltage time for 32
KB25,27
thversblk32k
thversblk256k
trd1sec1k/2k
-
-
-
52
104
-
452
904
60
ms
ms
µs
Erase Block high-voltage time for 256
KB25,27
Read 1s Section execution time (flash
sector)28
Read 1s Block execution time27
• 32 KB FlexNVM
trd1blk32k
-
-
-
-
0.5
1.7
ms
ms
trd1blk256k
• 256 KB program Flash
tpgmchk
trdrsrc
tpgm4
Program Check execution time28
Read Resource execution time28
Program Longword execution time
Erase Flash Sector execution time29
-
-
-
-
-
45
30
µs
µs
µs
ms
-
65
14
145
114
tersscr
Erase Flash Block execution time27,29
• 32 KB FlexNVM
tersblk32k
-
-
55
465
985
ms
ms
tersblk256k
• 256 KB program Flash
122
Program Section execution time27
• 512 B program Flash
• 512 B FlexNVM
tpgmsec512p
tpgmsec512n
tpgmsec1kp
tpgmsec1kn
-
-
-
-
2.4
4.7
4.7
9.3
-
-
-
-
ms
ms
ms
ms
• 1 KB program Flash
• 1 KB FlexNVM
trd1all
trdonce
tpgmonce
tersall
Read 1s All Blocks execution time
Read Once execution time28
-
-
-
-
-
0.9/1.830
ms
µs
-
25
Program Once execution time
Erase All Blocks execution time29
65
-
µs
70/17530
575/150030
ms
WCT101XADS, Rev. 1.1, 01/2021
NXP Semiconductors
13
Verify Backdoor Access Key execution
time28
tvfykey
-
-
-
30
-
µs
Program Partition for EEPROM execution
time for 32 KB FlexNVM27
tpgmpart32k
70
ms
Set FlexRAM Function execution time27
• Control Code 0xFF
tsetramff
tsetram8k
tsetram32k
-
-
-
50
0.3
0.7
-
µs
ms
ms
• 8 KB EEPROM backup
0.5
1.0
• 32 KB EEPROM backup
Byte-write to erased FlexRAM location
execution time27,31
teewr8bers
-
175
260
µs
Byte-write to FlexRAM execution time27
• 8 KB EEPROM backup
teewr8b8k
teewr8b16k
teewr8b32k
-
-
-
340
385
475
1700
1800
2000
µs
µs
µs
• 16 KB EEPROM backup
• 32 KB EEPROM backup
Word-write to erased FlexRAM location
execution time27
teewr16bers
-
175
260
µs
Word-write to FlexRAM execution time27
• 8 KB EEPROM backup
teewr16b8k
teewr16b16k
teewr16b32k
-
-
-
340
385
475
1700
1800
2000
µs
µs
µs
• 16 KB EEPROM backup
• 32 KB EEPROM backup
Longword-write to erased FlexRAM
location execution time27
teewr32bers
-
360
540
µs
Longword-write to FlexRAM execution
time27
teewr32b8k
teewr32b16k
teewr32b32k
-
-
-
545
630
810
1950
2050
2250
µs
µs
µs
• 8 KB EEPROM backup
• 16 KB EEPROM backup
• 32 KB EEPROM backup
tflashret10k
tflashret1k
nflashcyc
Data retention after up to 10 K cycles
Data retention after up to 1 K cycles
Cycling endurance33
5
5032
10032
50 K32
-
-
-
years
years
cycles
20
10 K
Data retention up to 100% of write
endurance27
teeret100
teeret10
5
5032
-
-
years
years
Data retention up to 10% of write
endurance27
20
10032
Write endurance27,34
neewr16
neewr128
neewr512
neewr4k
neewr8k
• EEPROM backup to FlexRAM ratio =
35 K
315 K
1.27 M
10 M
175 K
1.6 M
6.4 M
50 M
-
-
-
-
-
writes
writes
writes
writes
writes
16
• EEPROM backup to FlexRAM ratio =
128
• EEPROM backup to FlexRAM ratio =
512
• EEPROM backup to FlexRAM ratio =
4096
• EEPROM backup to FlexRAM ratio =
8192
20 M
100 M
WCT101XADS, Rev. 1.1, 01/2021
14
NXP Semiconductors
12-bit cyclic ADC electrical specifications
Symbol
VDDA
Characteristic
Supply voltage35
Min.
3.0
Typ.
Max.
3.6
Unit
V
3.3
VREFHX
fADCCLK
VREFH supply voltage36
ADC conversion clock37
VDDA - 0.6
0.1/0.6
VDDA
10/20
V
-
MHz
Conversion range38
• Fully differential26
• Single-ended/unipolar
VREFH
VREFL
-
RADC
-( VREFH - VREFL
VREFL
)
-
-
V
V
VREFH
Input voltage range (per input)39
• External Reference
VADCIN
VREFL
VSSA
-
-
VREFH
VDDA
V
V
• Internal Reference
tADC
Conversion time40
-
-
8/6
13
-
-
tADCCLK
tADCCLK
tADCPU
ADC power-up time (from adc_pdn)
ADC RUN current (per ADC block)26
ADC RUN current (per ADC block)27
• at 600 kHz ADC clock, LP mode
• ≤ 8.33 MHz ADC clock, 00 mode
• ≤ 12.5 MHz ADC clock, 01 mode
-
1.8
-
mA
-
-
-
-
-
1
5
-
-
-
-
-
mA
mA
mA
mA
mA
IADCRUN
9
15
19
• ≤ 16.67 MHz ADC clock, 10 mode
• ≤ 20 MHz ADC clock, 11 mode
ADC power down current (adc_pdn
enabled)41
IADPWRDWN
-
0.1/0.02
-
µA
IVREFH
INLADC
DNLADC
VREFH current (in external mode)42
Integral non-linearity43
-
-
-
190/0.001
+/-1.5 (3)
-
µA
+/-2.2 (5)
+/-0.8 (1)
LSB44
LSB44
Differential non-linearity43
+/-0.5 (0.6)
Offset45
VOFFSET
• Fully differential26
• Single ended/Unipolar46
-
-
+/-8
-
-
mV
mV
+/-12 (13.7)
0.99 to
1.10126
-
-
-
-
0.996 to 1.00426
0.801 to 0.80927
EGAIN
Gain Error
0.798 to
0.81427
ENOB
IINJ
Effective number of bits47
Input injection current48
-
-
10.6/9.5
-
-
bits
mA
+/-3
CADCI
-
4.8
-
pF
Input sampling capacitance
16-bit SAR ADC electrical specifications27
Symbol
VDDA
Characteristic
Supply voltage
Supply voltage delta to VDD
Min.
2.7
Typ.49
Max.
3.6
Unit
V
-
∆ VDDA
- 0.1
0
+ 0.1
V
WCT101XADS, Rev. 1.1, 01/2021
NXP Semiconductors
15
∆ VSSA
VREFH
VREFL
VADIN
Supply voltage delta to VSS
ADC reference voltage high
ADC reference voltage low
Input voltage range
- 0.1
VDDA
VSSA
VSSA
0
VDDA
VSSA
-
+ 0.1
VDDA
VSSA
VDDA
V
V
V
V
Input capacitance
• 16-bit mode
CADIN
RADIN
fADCK
-
-
8
4
10
5
pF
pF
• 8/10/12-bit mode
-
2
5
kΩ
Input resistance
ADC conversion clock frequency50
• 16-bit mode
2
1
-
-
12
18
MHz
MHz
• 8/10/12-bit mode
ADC conversion rate without ADC
hardware averaging
• 16-bit mode
Crate
37.037
20.000
-
-
461.467
818.330
ksps
ksps
• 8/10/12-bit mode
Supply current51
IDDA_ADC
-
-
1.7
mA
ADC asynchronous clock source
• ADLPC = 1, ADHSC = 0
• ADLPC = 1, ADHSC = 1
• ADLPC = 0, ADHSC = 0
• ADLPC = 0, ADHSC = 1
1.2
3.0
2.4
4.4
2.4
4.0
5.2
6.2
3.9
7.3
6.1
9.5
MHz
MHz
MHz
MHz
fADACK
Integral non-linearity53
• 16-bit mode
-
-
-
-
+/-7.0
+/-1.0
+/-0.5
LSB52
LSB52
LSB52
- 2.7 to +
1.9
INLAD
• 12-bit mode
- 0.7 to +
0.5
• < 12-bit modes
Differential non-linearity53
• 16-bit mode
-
-
-
-
-
- 1.0 to + 4.0
+/-0.7
LSB52
LSB52
LSB52
DNLAD
• 12-bit mode
- 0.3 to +
0.5
+/-0.2
• < 12-bit modes
53
Full-scale error (VADIN = VDDA
)
EFS
-
-
- 4
- 5.4
- 1.8
LSB52
LSB52
• 12-bit mode
- 1.4
• < 12-bit modes
Quantization error
• 16-bit mode
• 12-bit mode
EQ
-
-
- 1 to 0
-
-
LSB52
LSB52
+/-0.5
WCT101XADS, Rev. 1.1, 01/2021
16
NXP Semiconductors
Effective number of bits54
16-bit single-ended mode
• Avg = 32
12.2
11.4
13.9
13.1
-
-
bits
bits
ENOB
• Avg = 4
12-bit single-ended mode
• Avg = 32
-
-
10.8
10.2
-
-
bits
bits
• Avg = 4
STEMP
-
-
1.715
722
-
-
mV/°C
mV
Temp sensor slope under -40 °C to 105 °C
Temp sensor voltage55 at 25 °C
VTEMP25
12-bit DAC electrical specifications
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Settling time56 under RLD = 3 kΩ, CLD = 400
tSETTLE
-
1
-
µs
pF
DAC power-up time (from PWRDWN
release to valid DACOUT)
tDACPU
-
-
11
µs
INLDAC
Integral non-linearity58
-
-
+/-3
+/-4
LSB57
LSB57
DNLDAC
Differential non-linearity58
+/-0.8
+/-0.9
Monotonicity (> 6 sigma monotonicity, <
3.4 ppm non-monotonicity)
MONDAC
Guaranteed
-
VOFFSET
EGAIN
VOUT
Offset error58 (5% to 95% of full range)
Gain error58 (5% to 95% of full range)
Output voltage range
-
+ 25
+/-0.5
-
+ 35
mV
%
-
+/-1.5
VSSA + 0.04
VDDA - 0.04
V
SNR
Signal-to-noise ratio
-
-
85
-
-
dB
bits
ENOB
Effective number of bits
11
Comparator and 6-bit DAC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
2.7
-
3.6
V
Supply current, High-speed mode(EN=1,
PMODE=1)59
IDDHS
-
-
300/-
36/-
-/200
-/20
µA
µA
Supply current, Low-speed mode(EN=1,
PMODE=0)59
IDDLS
VAIN
VAIO
Analog input voltage
Vss
-
-
-
VDD
20
V
Analog input offset voltage
mV
WCT101XADS, Rev. 1.1, 01/2021
NXP Semiconductors
17
Analog comparator hysteresis60
• CR0[HYSTCTR]=00
• CR0[HYSTCTR]=01
• CR0[HYSTCTR]=10
• CR0[HYSTCTR]=11
-
-
-
-
5
13
48
mV
mV
mV
mV
25/10
55/20
80/30
VH
105
148
VCMPOh
VCMPOl
tDHS
Output high
Output low
VDD - 0.5
-
-
-
-
V
V
0.5
Propagation delay, high-speed
mode(EN=1, PMODE=1)61
-
-
-
-
50
ns
ns
Propagation delay, low-speed
mode(EN=1, PMODE=0) 61
tDLS
200
tDInit
Analog comparator initialization delay62
6-bit DAC current adder (enabled)
6-bit DAC reference inputs
-
40
7
-
-
µs
µA
IDAC6b
-
-
RDAC6b
VDDA
-0.5
-0.3
VDD
0.5
0.3
V
INLDAC6b
DNLDAC6b
6-bit DAC integral non-linearity
6-bit DAC differential non-linearity
-
LSB63
LSB63
-
PWM timing parameters
Symbol
Characteristic
Min.
Typ.
100
312
Max.
Unit
MHz
ps
fPWM
PWM clock frequency
-
-
-
-
SPWMNEP
NanoEdge Placement (NEP) step size64,65
Delay for fault input activating to PWM
output deactivated
tDFLT
1
-
-
-
-
ns
µs
tPWMPU
Power-up time66
25
Quad timer timing
Symbol
Characteristic
Min.
Max.
Unit
ns
Notes
67
PIN
PINHL
Timer input period
2Ttimer + 6
1Ttimer + 3
2Ttimer - 2
1Ttimer - 2
-
-
-
-
Timer input high/low period
Timer output period
ns
67
POUT
ns
67
POUTHL
Timer output high/low period
ns
67
QSPI timing68
Min.
Max.
Symbol
Characteristic
Unit
Master
Slave
60/35
Master
Slave
tC
Cycle time
60/35
-
-
-
-
-
-
-
-
ns
ns
ns
ns
tELD
tELG
tCH
Enable lead time
Enable lag time
Clock (SCLK) high time
-
20/17.5
20/17.5
28/16.6
-
28/16.6
WCT101XADS, Rev. 1.1, 01/2021
18
NXP Semiconductors
tCL
tDS
tDH
Clock (SCLK) low time
28/16.6
20/16.5
1
28/16.6
-
-
-
-
-
-
ns
ns
ns
Data set-up time required for inputs
Data hold time required for inputs
1
3
Access time (time to data active from
high-impedance state)
tA
tD
-
-
5
5
-
-
-
-
ns
ns
Disable time (hold time to high-impedance
state)
tDV
tDI
tR
Data valid for outputs
Data invalid
Rise time
-
0
-
-
0
-
-/5
-
-/15
ns
ns
ns
ns
-
1
1
1
tF
Fall time
-
-
1
QSCI timing
Symbol
BRSCI
Characteristic
Baud rate
Min.
-
Max.
Unit
Notes
(fMAX_SCI /16)
1.04/BRSCI
1.04/BRSCI
Mbit/s
µs
69
-
PWRXD
RXD pulse width
TXD pulse width
0.965/BRSCI
0.965/BRSCI
PWTXD
µs
-
LIN Slave Mode
Deviation of slave node clock from nominal
clock rate before synchronization
FTOL_UNSYNCH
- 14
- 2
14
2
%
%
-
-
Deviation of slave node clock relative to
the master node clock after
synchronization
FTOL_SYNCH
Mater node
bit periods
13
11
-
-
-
-
TBREAK
Minimum break character length
Slave node
bit periods
CAN timing
Symbol
BRCAN
Characteristic
Baud rate
Min.
Max.
Unit
Mbit/s
µs
Notes
-
-
1
1.5/2
-
-
70
-
TWAKEUP
TWAKEUP
CAN Wakeup dominant pulse filtered
CAN Wakeup dominant pulse pass
5
µs
IIC timing
Symbol
fSCL
Min.
Max.
Min. Max.
Characteristic
Unit
Notes
Min.
Max.
SCL clock frequency
-
0
100
0
400
kHz
µs
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
tHD_STA
4
-
-
0.6
1.3
-
-
-
-
tSCL_LOW
LOW period of the SCL clock
4.7
µs
WCT101XADS, Rev. 1.1, 01/2021
NXP Semiconductors
19
tSCL_HIGH
tSU_STA
HIGH period of the SCL clock
4
-
-
0.6
0.6
-
-
µs
µs
-
-
Set-up time for a repeated START
condition
4.7
tHD_DAT
Data hold time for IIC bus devices
Data set-up time
071
3.4572
-
073
0.971
-
µs
ns
ns
ns
-
tSU_DAT
25074
10075
72
76
75
tr
tf
Rise time of SDA and SCL signals
Fall time of SDA and SCL signals
-
-
1000
300
20 + 0.1Cb
20 + 0.1Cb
300
300
tSU_STOP
tBUS_Free
Set-up time for STOP condition
-
-
4
-
-
0.6
1.3
-
-
µs
µs
Bus free time between STOP and START
condition
4.7
Pulse width of spikes that must be
suppressed by the input filter
tSP
-
N/A
N/A
0
50
ns
1. CPU clock = 4 MHz and System running from 8 MHz IRC Applicable to all wakeup times: Wakeup times (in 1,2,3,4) are measured
from GPIO toggle for wakeup till GPIO toggle at the wakeup interrupt subroutine from respective stop/wait mode.
2. CPU clock = 200 kHz and 8 MHz IRC on standby. Exit via interrupt on Port C GPIO.
3. Clock configuration: CPU and system clocks= 100 MHz; Bus Clock = 50 MHz. Exit via an interrupt on PortC GPIO.
4. Using 64 KHz external clock; CPU Clock = 32 KHz. Exit via an interrupt on PortC GPIO.
5. WCT1011A supports maximum 100 MHz CPU clock and 50 MHz peripheral bus clock, maximum 100 MHz CPU and peripheral bus
clock for WCT1013A. In total, WCT1013A has higher power consumption than WCT1011A in the same operating mode. For the
current consumption data, the former is for WCT1011A, and the latter for WCT1013A.
6. If the RESET pin filter is enabled by setting the RST_FLT bit in the SIM_CTRL register to 1, the minimum pulse assertion must be
greater than 21 ns.
7. TOSC means oscillator clock cycle; TSYSCLK means system clock cycle.
8. During 3.3 V VDD power supply ramp down.
9. During 3.3 V VDD power supply ramp up (gated by LVI_2p7).
10. The maximum TCK operation frequency is fSYSCLK/8 for WCT1011A, fSYSCLK/16 for WCT1013A.
11. Value is after trim.
12. Guaranteed by design.
13. The chip may not function if the high or low pulse width is smaller than 6.25 ns.
14. External clock input rise time is measured from 10% to 90%.
15. External clock input fall time is measured from 90% to 10%.
16. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The PLL is
optimized for 8 MHz input.
17. The frequency of the core system clock cannot exceed 100 MHz. If the NanoEdge PWM is available, the PLL output must be set to
400 MHz. And the minimum PLL output frequency is 200 MHz for WCT1011A, 240 MHz for WCT1013A.
18. This is the time required after the PLL is enabled to ensure reliable operation.
19. 200 kHz internal RC oscillator is on WCT1011A, 32 kHz internal RC oscillator on WCT1013A.
20. Frequency after application of 8 MHz trimmed.
21. Frequency after application of 200 kHz/32 kHz trimmed.
22. Typical +/-1.5%, maximum +/-3% frequency variation for 200 kHz internal RC oscillator, and typical +/-2.5%, maximum +/-4%
frequency variation for 32 kHz internal RC oscillator.
23. Standby to run mode transition.
24. Power down to run mode transition. Typical 10 µs stabilization time for 200 kHz internal RC oscillator, and 14.4 µs stabilization time
for 32 kHz internal RC oscillator.
25. Maximum time based on expectations at cycling end-of-life.
26. The specification is only for WCT1011A.
27. The specification is only for WCT1013A.
28. Assumes 25 MHz flash clock frequency.
29. Maximum times for erase parameters based on expectations at cycling end-of-life.
30. All blocks size is 64 KB on WCT1011A, 256 KB on WCT1013A. Longer all blocks command operation time for WCT1013A.
31. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.
32. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25°C use
WCT101XADS, Rev. 1.1, 01/2021
20
NXP Semiconductors
profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619.
33. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C.
34. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤ Tj ≤ 125°C influenced by the cycling
endurance of the FlexNVM and the allocated EEPROM backup. Minimum and typical values assume all byte-writes to FlexRAM.
35. The ADC functions up to VDDA = 2.7 V. When VDDA is below 3.0 V, ADC specifications are not guaranteed.
36. When the input is at the VREFL level, the resulting output will be all zeros (hex 000), plus any error contribution due to offset and gain
error. When the input is at the VREFH level, the output will be all ones (hex FFF), minus any error contribution due to offset and gain
error.
37. ADC clock duty cycle is 45% ~ 55%. WCT1011A only supports the maximum ADC clock of 10 MHz and minimum ADC clock of 0.1 MHz,
and WCT1013A supports 20 MHz maximum ADC clock and 0.6 MHz minimum ADC clock.
38. Conversion range is defined for x1 gain setting. For x2 and x4 the range is 1/2 and 1/4, respectively.
39. In unipolar mode, positive input must be ensured to be always greater than negative input.
40. For WCT1011A, the first conversion takes 10 clock cycles, 8 clock cycles for the subsequent conversion; On WCT1013A, 8.5 clock
cycles for the first conversion, 6 clock cycles for the subsequent conversion.
41. For WCT1011A, the power down current of ADC is 0.1 µA, and 0.02 µA for WCT1013A.
42. For WCT1011A, the VREFH current of ADC is 190 µA, and 0.001 µA for WCT1013A.
43. INLADC/DNLADC is measured from VADCIN = VREFL to VADCIN = VREFH using Histogram method at x1 gain setting. On WCT1011A,
typical value is +/-1.5 LSB, and maximum value +/-2.2 LSB for INLADC; typical value is +/-0.5 LSB, and maximum value +/-0.8 LSB for
DNLADC. On WCT1013A, typical value is +/-3 LSB, and maximum value +/-5 LSB for INLADC; typical value is +/-0.6 LSB, and maximum
value +/-1 LSB for DNLADC
.
44. Least Significant Bit = 0.806 mV at 3.3 V VDDA, x1 gain setting.
45. Any off-channel with 50 kHz full-scale input to the channel being sampled with DC input (isolation crosstalk).
46. Typical +/-12 mV offset for WCT1011A, +/-13.7 mV offset for WCT1013A.
47. Typical ENOB is 10.6 bits for WCT1011A, 9.5 bits for WCT1013A.
48. The current that can be injected into or sourced from an unselected ADC input without affecting the performance of the ADC.
49. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and
are not tested in production.
50. To use the maximum ADC conversion clock frequency, the ADHSC bit must be set and the ADLPC bit must be clear.
51. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power). For lowest
power operation the ADLPC bit should be set, the HSC bit should be clear with 1MHz ADC conversion clock speed.
52. 1 LSB = (VREFH - VREFL)/2N.
53. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11).
54. Input data is 100 Hz sine wave; ADC conversion clock < 12 MHz.
55. System clock = 4 MHz, ADC clock = 2 MHz, AVG = Max, Long Sampling = Max.
56. Settling time is swing range from VSSA to VDDA.
57. LSB = 0.806 mV.
58. No guaranteed specification within 5% of VDDA or VSSA.
59. Typical supply current with high-speed mode is 300 µA, typical supply current with low-speed mode is 36 µA on WCT1011A.
Maximum supply current with high-speed mode is 200 µA, maximum supply current with low-speed mode is 20 µA on WCT1013A.
60. Typical hysteresis is measured with input voltage range limited to 0.7 to VDD-0.7 V. On WCT1011A, typical 25 mV for CR0[HYSTCTR]
= 01, typical 55 mV for CR0[HYSTCTR] = 10, typical 80 mV for CR0[HYSTCTR] = 11. On WCT1013A, typical 10 mV for CR0[HYSTCTR] =
01, typical 20 mV for CR0[HYSTCTR] = 10, typical 30 mV for CR0[HYSTCTR] = 11.
61. Signal swing is 100 mV.
62. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN, VRSEL,
PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
63. 1 LSB = Vreference/64.
64. Reference IPbus clock of 100 MHz in NanoEdge Placement mode.
65. Temperature and voltage variations do not affect NanoEdge Placement step size.
66. Powerdown to NanoEdge mode transition.
67. Ttimer = Timer input clock cycle. For 100 MHz operation, Ttimer = 10 ns.
68. For QSPI specifications, all data with xx/xx format, the former is for WCT1011A, the latter is for WCT1013A.
69. fMAX_SCI is the frequency of operation of the SCI clock in MHz, which can be selected as the bus clock or 2x bus clock for the device.
70. WCT1011A supports maximum 1.5 us pulse filtered, and WCT1013A supports maximum 2 us pulse filtered.
71. The master mode IIC deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves acknowledge this
address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL lines.
72. The maximum tHD_DAT must be met only if the device does not stretch the LOW period (tSCL_LOW) of the SCL signal.
WCT101XADS, Rev. 1.1, 01/2021
NXP Semiconductors
21
73. Input signal Slew = 10 ns and Output Load = 50 pF
74. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
75. A Fast mode IIC bus device can be used in a Standard mode IIC bus system, but the requirement tSU_DAT ≥ 250 ns must then be
met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU_DAT = 1000 + 250 = 1250 ns
(according to the Standard mode IIC bus specification) before the SCL line is released.
76. Cb = total capacitance of the one bus line in pF.
2.3 Thermal operating characteristics
Table 7. General thermal characteristics
Symbol
Description
Die junction temperature
Ambient temperature
Min
-40
-40
Max
125
105
Unit
°C
TJ
TA
°C
WCT101XADS, Rev. 1.1, 01/2021
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NXP Semiconductors
3 Typical Performance Characteristics
3.1 System efficiency
The typical system efficiency (receiver output power vs. transmitter input power) on NXP
WCT101xA-based transmitter solutions can usually reach more than 65%. The detailed number depends
on the specific solution type. For example, NXP WCT-15WTXAUTO reference solution has more than
70% system efficiency with the MP Qi Receiver Simulator.
Note: Power components are the main factor to determine the system efficiency, such as drivers and
MOSFETs.
3.2 Standby power
The purpose of the standby mode of operation is to reduce the power consumption of a wireless power
transfer system when power transfer is not required. There are two ways to enter standby mode. The first is
when the transmitter does not detect the presence of a valid receiver. The second is when the receiver
sends only an End Power Transfer Packet. In standby mode, the transmitter only monitors if a receiver is
placed on the active charging area of the transmitter or removed from there.
It is recommended that the power consumption of the transmitter in standby mode meets the relative
regional regulations especially for “No-load power consumption”.
3.3 Digital demodulation
To optimize system BOM cost, the WCT101xA solution employs digital demodulation algorithm to
communicate with the receiver. This method can achieve high performance, low cost, and very simple coil
signal sensing circuit with less components number.
3.4 Two-way communication
The WCT101xA solution supports two-way communication and uses FSK to send messages to receiver.
This method allows transmitter to negotiate with receiver to establish advanced power transfer contract,
and calibrate power loss for more precise FOD protection.
3.5 Foreign object detection
The WCT101xA solution supports power class 0 FOD framework, which is based on calibrated power
loss method and quality factor (Q factor) method. With NXP FreeMASTER GUI tool, the FOD algorithm
can be easily calibrated to get accurate power loss information especially for very sensitive foreign
objects.
WCT101XADS, Rev. 1.1, 01/2021
NXP Semiconductors
23
4 Device Information
4.1 Functional block diagram
This functional block diagram shows the common pin assignment information by all members of the
family. For the detailed pin multiplexing information, see Section 4.4 “Pin Function Description”.
Figure 1. WCT1011/3AVLH function block diagram
4.2 Product features overview
The following table lists the features that differ among members of the family. Features not listed are
shared in common by all members of the family.
Table 8. Feature comparison between WCT1011A and WCT1013A
Part
WCT1011A
WCT1013A
Maximum Core/Bus Clock (MHz)
Maximum Fully Run Current Consumption (mA)
Program Flash Memory
100/50
100/100
38.1 (VDD) + 9.9 (VDDA
)
63.7 (VDD) + 16.7 (VDDA)
64
0/0
64
256
32/2
288
32
On-Chip Flash
FlexNVM/FlexRAM
Memory Size (KB)
Total Flash Memory
On-Chip SRAM Memory Size (KB)
Memory Resource Protection
8
Yes
Yes
Yes
Yes
Inter-Peripheral Crossbar Switches with AOI
WCT101XADS, Rev. 1.1, 01/2021
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NXP Semiconductors
On-Chip Relaxation Oscillator
Computer Operating Properly (Watchdog)
External Watchdog Monitor
Cyclic Redundancy Check
Periodic Interrupt Timer
1 (8 MHz) + 1 (200 kHz)
1 (8 MHz) + 1 (32 kHz)
1 (windowed)
1
1
1
1
1
2
2
Quad Timer
1 x 4
2 x 4
Programmable Delay Block
12-bit Cyclic ADC Channels
16-bit SAR ADC Channels
0
2
2 x 8
2 x 8
0
1 x 8
High-Resolution
PWM Channels
8
8
Standard
4
1
12-bit DAC
2
1
Analog Comparator /w 6-bit REF DAC
DMA Channels
4
4
4
4
Queued Serial Communications Interface
Queued Serial Peripheral Interface
Inter-Integrated Circuit
Controller Area Network
GPIO
2
2
2
1
1
2
1 (MSCAN)
54
1 (FlexCAN)
54
Package
64 LQFP
64 LQFP
WCT101XADS, Rev. 1.1, 01/2021
NXP Semiconductors
25
4.3 Pinout diagram
Figure 2. WCT1011/3AVLH pinout diagram
4.4 Pin function description
By default, each pin is configured for its primary function (listed first). Any alternative functionality,
shown in parentheses, can be programmed through GPIO module peripheral enable registers and SIM
module GPIO peripheral select registers.
Table 9. Pin signal descriptions
Multiplexing
Signal name
Pin No.
Function description
signals
Test Clock Input — This input pin provides a gated clock to synchronize the
test logic and shift serial data to the JTAG/EOnCE port. The pin is connected
internally to a pull-up resistor. A Schmitt-trigger input is used for noise
immunity.
TCK
1
GPIOD2
Port D GPIO — This GPIO pin can be individually programmed as an input
or output pin.
After reset, the default state is TCK.
WCT101XADS, Rev. 1.1, 01/2021
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NXP Semiconductors
RESET — This input is a direct hardware reset on the processor. When
RESET is asserted low, the device is initialized and placed in the reset state.
A Schmitt-trigger input is used for noise immunity. The internal reset signal is
de-asserted synchronous with the internal clocks after a fixed number of
internal clocks.
2
GPIOD4
RESET
Port D GPIO — This GPIO pin can be individually programmed as an input
or output pin. If RESET functionality is disabled in this mode and the chip can
be reset only via POR, COP reset, or software reset.
After reset, the default state is RESET.
Port C GPIO — This GPIO pin can be individually programmed as an input
or output pin.
EXTAL — External Crystal Oscillator Input. This input connects the internal
GPIOC0
GPIOC1
3
4
EXTAL/CLKIN0
crystal oscillator input to an external crystal or ceramic resonator.
CLKIN0 — This pin serves as an external clock input 0.
After reset, the default state is GPIOC0.
Port C GPIO — This GPIO pin can be individually programmed as an input
or output pin.
XTAL
XTAL — External Crystal Oscillator Output. This output connects the internal
crystal oscillator output to an external crystal or ceramic resonator.
After reset, the default state is GPIOC1.
Port C GPIO — This GPIO pin can be individually programmed as an input
or output pin.
TXD0 — The SCI0 transmit data output or transmit/receive in single wire
operation.
XB_OUT11 — Crossbar module output 11 only on WCT1011A.
TB0 — Quad timer module B channel 0 input/output only on WCT1013A.
TXD0/XB_OUT
11(TB0)/XB_IN
2/CLKO0
GPIOC2
5
XB_IN2 — Crossbar module input 2.
CLKO0 — This is a buffered clock output 0; the clock source is selected by
clock out select (CLKOSEL) bits in the clock output select register
(CLKOUT) of the SIM.
After reset, the default state is GPIOC2.
Port F GPIO — This GPIO pin can be individually programmed as an input or
output pin.
RXD0 — The SCI0 receive data input.
XB_OUT10 — Crossbar module output 10 only on WCT1011A.
TB1 — Quad timer module B channel 1 input/output only on WCT1013A.
RXD0/XB_OUT
10(TB1)/CMPD
_O/PWM_2X
GPIOF8
GPIOC3
6
7
CMPD_O — Analog comparator D output.
PWM_2X — NanoEdge eFlexPWM sub-module 2 output X or input capture
X only on WCT1011A.
After reset, the default state is GPIOF8.
Port C GPIO — This GPIO pin can be individually programmed as an input
or output pin.
TA0/CMPA_O/
RXD0/CLKIN1
WCT101XADS, Rev. 1.1, 01/2021
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27
TA0 — Quad timer module A channel 0 input/output.
CMPA_O — Analog comparator A output.
RXD0 — The SCI0 receive data input.
CLKIN1 — This pin serves as an external clock input 1.
After reset, the default state is GPIOC3.
Port C GPIO — This GPIO pin can be individually programmed as an input
or output pin.
TA1 — Quad timer module A channel 1 input/output.
TA1/CMPB_O/X CMPB_O — Analog comparator B output.
B_IN6(XB_IN8)/
GPIOC4
8
XB_IN6 — Crossbar module input 6 only on WCT1011A.
XB_IN8 — Crossbar module input 8 only on WCT1013A.
EWM_OUT
EWM_OUT — External watchdog monitor output.
After reset, the default state is GPIOC4.
Port A GPIO — This GPIO pin can be individually programmed as an input
or output pin.
ANA7&CMPD_IN3 — Analog input to channel 7 of ADCA and input 3 of
analog comparator D only on WCT1011A. When used as an analog input,
the signal goes to the ANA7 and CMPD_IN3.
ANA7&ANC11 — Analog input to channel 7 of ADCA and analog input 11 of
ADCC only on WCT1013A. When used as an analog input, the signal goes
to the ANA7 and ANC11.
ANA7&CMPD_I
N3(ANC11)
GPIOA7
9
After reset, the default state is GPIOA7.
Port A GPIO — This GPIO pin can be individually programmed as an input
or output pin.
ANA6&CMPD_IN2 — Analog input to channel 6 of ADCA and input 2 of
analog comparator D only on WCT1011A. When used as an analog input,
the signal goes to the ANA6 and CMPD_IN2.
ANA6&ANC10 — Analog input to channel 6 of ADCA and analog input 10 of
ADCC only on WCT1013A. When used as an analog input, the signal goes
to the ANA6 and ANC10.
ANA6&CMPD_I
N2(ANC10)
GPIOA6
10
After reset, the default state is GPIOA6.
Port A GPIO — This GPIO pin can be individually programmed as an input
or output pin.
ANA5&CMPD_IN1 — Analog input to channel 5 of ADCA and input 1 of
analog comparator D only on WCT1011A. When used as an analog input,
the signal goes to the ANA5 and CMPD_IN1.
ANA5&ANC9 — Analog input to channel 5 of ADCA and analog input 9 of
ADCC only on WCT1013A. When used as an analog input, the signal goes
to the ANA5 and ANC9.
ANA5&CMPD_I
N1(ANC9)
GPIOA5
GPIOA4
11
12
After reset, the default state is GPIOA5.
Port A GPIO — This GPIO pin can be individually programmed as an input
or output pin.
ANA4&CMPD_I
N0&ANC8
ANA4&CMPD_IN0 — Analog input to channel 4 of ADCA and input 0 of
analog comparator D only on WCT1011A. When used as an analog input,
WCT101XADS, Rev. 1.1, 01/2021
28
NXP Semiconductors
the signal goes to the ANA4 and CMPD_IN0.
ANA4&CMPD_IN0&ANC8 — Analog input to channel 4 of ADCA and input 0
of analog comparator D and analog input to channel 8 of ADCC only on
WCT1013A. When used as an analog input, the signal goes to the ANA4
and CMPD_IN0 and ANC8.
After reset, the default state is GPIOA4.
Port A GPIO — This GPIO pin can be individually programmed as an input
or output pin.
ANA0&CMPA_IN3 — Analog input to channel 0 of ADCA and input 3 of
ANA0&CMPA_I analog comparator A. When used as an analog input, the signal goes to the
GPIOA0
13
N3/CMPC_O
ANA0 and CMPA_IN3.
CMPC_O — Analog comparator C output.
After reset, the default state is GPIOA0.
Port A GPIO — This GPIO pin can be individually programmed as an input
or output pin.
ANA1&CMPA_I ANA1 and CMPA_IN0 — Analog input to channel 1 of ADCA and input 0 of
GPIOA1
GPIOA2
14
15
N0
analog comparator A. When used as an analog input, the signal goes to the
ANA1 and CMPA_IN0.
After reset, the default state is GPIOA1.
Port A GPIO — This GPIO pin can be individually programmed as an input
or output pin.
ANA2&VREFHA&CMPA_IN1 — Analog input to channel 2 of ADCA and
analog references high of ADCA and input 1 of analog comparator A. When
used as an analog input, the signal goes to ANA2 and VREFHA and
CMPA_IN1. ADC control register configures this input as ANA2 or VREFHA.
ANA2&VREFH
A&CMPA_IN1
After reset, the default state is GPIOA2.
Port A GPIO — This GPIO pin can be individually programmed as an input
or output pin.
ANA3&VREFLA&CMPA_IN2 — Analog input to channel 3 of ADCA and
analog references low of ADCA and input 2 of analog comparator A. When
used as an analog input, the signal goes to ANA3 and VREFLA and
CMPA_IN2. ADC control register configures this input as ANA3 or VREFLA.
ANA3&VREFLA
&CMPA_IN2
GPIOA3
16
After reset, the default state is GPIOA3.
Port B GPIO — This GPIO pin can be individually programmed as an input
or output pin.
ANB7&CMPB_IN2 — Analog input to channel 7 of ADCB and input 2 of
analog comparator B only on WCT1011A. When used as an analog input,
ANB7&CMPB_I the signal goes to the ANB7 and CMPB_IN2.
GPIOB7
17
N2&ANC15
ANB7&CMPB_IN2&ANC15 — Analog input to channel 7 of ADCB and input
2 of analog comparator B and analog input to channel 15 of ADCC only on
WCT1013A. When used as an analog input, the signal goes to the ANB7
and CMPB_IN2 and ANC15.
After reset, the default state is GPIOB7.
Port C GPIO — This GPIO pin can be individually programmed as an input
or output pin.
GPIOC5
18
DAC_O/XB_IN7
DAC_O — 12-bit Digital-to-Analog Converter output. For WCT1011A, it’s
DACA output.
WCT101XADS, Rev. 1.1, 01/2021
NXP Semiconductors
29
XB_IN7 — Crossbar module input 7.
After reset, the default state is GPIOC5.
Port B GPIO — This GPIO pin can be individually programmed as an input
or output pin.
ANB6&CMPB_IN1 — Analog input to channel 6 of ADCB and input 1 of
analog comparator B only on WCT1011A. When used as an analog input,
ANB6&CMPB_I the signal goes to the ANB6 and CMPB_IN1.
GPIOB6
GPIOB5
GPIOB4
19
20
21
N1&ANC14
ANB6&CMPB_IN1&ANC14 — Analog input to channel 6 of ADCB and input
1 of analog comparator B and analog input to channel 14 of ADCC only on
WCT1013A. When used as an analog input, the signal goes to the ANB6
and CMPB_IN1 and ANC14.
After reset, the default state is GPIOB6.
Port B GPIO — This GPIO pin can be individually programmed as an input
or output pin.
ANB5&CMPC_IN2 — Analog input to channel 5 of ADCB and input 2 of
analog comparator C only on WCT1011A. When used as an analog input,
ANB5&CMPC_I the signal goes to the ANB5 and CMPC_IN2.
N2&ANC13 ANB5&CMPC_IN2&ANC13 — Analog input to channel 5 of ADCB and input
2 of analog comparator C and analog input to channel 13 of ADCC only on
WCT1013A. When used as an analog input, the signal goes to the ANB5
and CMPC_IN2 and ANC13.
After reset, the default state is GPIOB5.
Port B GPIO — This GPIO pin can be individually programmed as an input
or output pin.
ANB4&CMPC_IN1 — Analog input to channel 4 of ADCB and input 1 of
analog comparator C only on WCT1011A. When used as an analog input,
ANB4&CMPC_I the signal goes to the ANB4 and CMPC_IN1.
N1&ANC12
ANB4&CMPC_IN1&ANC12 — Analog input to channel 4 of ADCB and input
1 of analog comparator C and analog input to channel 12 of ADCC only on
WCT1013A. When used as an analog input, the signal goes to the ANB4
and CMPC_IN1 and ANC12.
After reset, the default state is GPIOB4.
Analog Power — This pin supplies 3.3 V power to the analog modules. It
must be connected to a clean analog power supply.
Analog Ground — This pin supplies an analog ground to the analog
modules. It must be connected to a clean power supply.
Port B GPIO — This GPIO pin can be individually programmed as an input
or output pin.
VDDA
VSSA
22
23
-
-
ANB0&CMPB_I ANB0&CMPB_IN3 — Analog input to channel 0 of ADCB and input 3 of
GPIOB0
GPIOB1
24
25
N3
analog comparator B. When used as an analog input, the signal goes to
ANB0 and CMPB_IN3.
After reset, the default state is GPIOB0.
Port B GPIO — This GPIO pin can be individually programmed as an input
or output pin.
ANB1&CMPB_IN0 — Analog input to channel 1 of ADCB and input 0 of
analog comparator B. When used as an analog input, the signal goes to
ANB1 and CMPB_IN0.
ANB1&CMPB_I
N0/DACB_O
DACB_O — 12-bit Digital-to-Analog Converter B output only on WCT1011A.
WCT101XADS, Rev. 1.1, 01/2021
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NXP Semiconductors
After reset, the default state is GPIOB1.
Connect a 2.2 μF or greater bypass capacitor between this pin and VSS to
stabilize the core voltage regulator output required for proper device
operation.
Port B GPIO — This GPIO pin can be individually programmed as an input
or output pin.
VCAP1
26
27
-
ANB2&VREFHB&CMPC_IN3 — Analog input to channel 2 of ADCB and
analog references high of ADCB and input 3 of analog comparator C. When
used as an analog input, the signal goes to ANB2 and VREFHB and
CMPC_IN3. ADC control register configures this input as ANB2 or VREFHB.
ANB2&VREFH
B&CMPC_IN3
GPIOB2
After reset, the default state is GPIOB2.
Port B GPIO — This GPIO pin can be individually programmed as an input
or output pin.
ANB3&VREFLB&CMPC_IN0 — Analog input to channel 3 of ADCB and
analog references low of ADCB and input 0 of analog comparator C. When
used as an analog input, the signal goes to ANB3 and VREFLB and
CMPC_IN0. ADC control register configures this input as ANB3 or VREFLB.
ANB3&VREFLB
&CMPC_IN0
GPIOB3
28
After reset, the default state is GPIOB3.
VDD1
VSS1
29
30
-
-
I/O Power — Supplies 3.3 V power to on-chip digital module.
I/O Ground — Provides ground on-chip digital module.
Port C GPIO — This GPIO pin can be individually programmed as an input
or output pin.
TA2 — Quad timer module A channel 2 input/output.
XB_IN3 — Crossbar module input 3.
TA2/XB_IN3/C
GPIOC6
31
MP_REF/SS0
CMP_REF — Input 5 of analog comparator A and B and C and D.
SS0 — SS0 is used in slave mode to indicate to the SPI0 module that the
current transfer is to be received. This signal is only on WCT1011A.
After reset, the default state is GPIOC6.
Port C GPIO — This GPIO pin can be individually programmed as an input
or output pin.
SS0 — SS0 is used in slave mode to indicate to the SPI0 module that the
current transfer is to be received.
SS0/TXD0/XB_I
N8
GPIOC7
32
TXD0 — SCI0 transmit data output or transmit/receive in single wire
operation.
XB_IN8 — Crossbar module input 8 only on WCT1011A.
After reset, the default state is GPIOC7.
Port C GPIO — This GPIO pin can be individually programmed as an input
or output pin.
MISO0 — Master in/slave out. In master mode, this pin serves as the data
input. In slave mode, this pin serves as the data output. The MISO0 line of a
slave device is placed in the high-impedance state if the slave device is not
selected.
MISO0
/RXD0/XB_IN9/
XB_OUT6
GPIOC8
33
RXD0 — SCI0 receive data input.
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31
XB_IN9 — Crossbar module input 9.
XB_OUT6 — Crossbar module output 6 only on WCT1011A.
After reset, the default state is GPIOC8.
Port C GPIO — This GPIO pin can be individually programmed as an input
or output pin.
SCLK0 — The SPI0 serial clock. In master mode, this pin serves as an
output, clocking slaved listeners. In slave mode, this pin serves as the data
clock input.
SCLK0/XB_IN4/
TXD0/XB_OUT
8
GPIOC9
34
XB_IN4 — Crossbar module input 4.
TXD0 — SCI0 transmit data output or transmit/receive in single wire
operation. This signal is only on WCT1011A.
XB_OUT8 — Crossbar module output 8 only on WCT1011A.
After reset, the default state is GPIOC9.
Port C GPIO — This GPIO pin can be individually programmed as an input
or output pin.
MOSI0 — Master out/slave in. In master mode, this pin serves as the data
output. In slave mode, this pin serves as the data input.
XB_IN5 — Crossbar module input 5.
MOSI0
GPIOC10
35
/XB_IN5/MISO0
/XB_OUT9
MISO0 — Master in/slave out. In master mode, this pin serves as the data
input. In slave mode, this pin serves as the data output. The MISO0 line of a
slave device is placed in the high-impedance state if the slave device is not
selected.
XB_OUT9 — Crossbar module output 9 only on WCT1011A.
After reset, the default state is GPIOC10.
Port F GPIO — This GPIO pin can be individually programmed as an input or
output pin.
XB_IN6 — Crossbar module input 6.
XB_IN6/TB2/SC TB2 — Quad timer module B channel 2 input/output only on WCT1013A.
LK1
GPIOF0
36
SCLK1 — The SPI1 serial clock. In master mode, this pin serves as an
output, clocking slaved listeners. In slave mode, this pin serves as the data
clock input.
After reset, the default state is GPIOF0.
Port C GPIO — This GPIO pin can be individually programmed as an input
or output pin.
CANTX — CAN transmit data output.
CAN_TX/SCL0( SCL0 — IIC0 serial clock only on WCT1011A.
GPIOC11
37
SCL1)/TXD1
SCL1 — IIC1 serial clock only on WCT1013A.
TXD1 — SCI1 transmit data output or transmit/receive in single wire
operation.
After reset, the default state is GPIOC11.
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NXP Semiconductors
Port C GPIO — This GPIO pin can be individually programmed as an input
or output pin.
CANRX — CAN receive data input.
CAN_RX/SDA0(
SDA1)/RXD1
GPIOC12
38
SDA0 — IIC0 serial data line only on WCT1011A.
SDA1 — IIC1 serial data line only on WCT1013A.
RXD1 — SCI1 receive data input.
After reset, the default state is GPIOC12.
Port F GPIO — This GPIO pin can be individually programmed as an input or
output pin.
SCL0 — IIC0 serial clock only on WCT1011A.
SCL1 — IIC1 serial clock only on WCT1013A.
SCL0(SCL1)/XB XB_OUT6 — Crossbar module output 6.
_OUT6/MISO1
GPIOF2
39
MISO1 — Master in/slave out. In master mode, this pin serves as the data
input. In slave mode, this pin serves as the data output. The MISO1 line of a
slave device is placed in the high-impedance state if the slave device is not
selected. This signal is only on WCT1011A.
After reset, the default state is GPIOF2.
Port F GPIO — This GPIO pin can be individually programmed as an input or
output pin.
SDA0 — IIC0 serial data line only on WCT1011A.
SDA1 — IIC1 serial data line only on WCT1013A.
SDA0(SDA1)/X
B_OUT7/
GPIOF3
40
XB_OUT7 — Crossbar module output 7.
MOSI1
MOSI1 — Master out/slave in. In master mode, this pin serves as the data
output. In slave mode, this pin serves as the data input. This signal is only on
WCT1011A.
After reset, the default state is GPIOF3.
Port F GPIO — This GPIO pin can be individually programmed as an input or
output pin.
TXD1 — The SCI1 transmit data output or transmit/receive in single wire
operation.
TXD1/XB_OUT
8/PWM_0X/PW
M_FAULT6
XB_OUT8 — Crossbar module output 8.
GPIOF4
41
PWM_0X — NanoEdge eFlexPWM sub-module 0 output X or input capture
X only on WCT1011A.
PWM_FAULT6 — NanoEdge eFlexPWM fault input 6 only on WCT1011A.
After reset, the default state is GPIOF4.
Port F GPIO — This GPIO pin can be individually programmed as an input or
output pin.
RXD1/XB_OUT
9/PWM_1X/PW
M_FAULT7
RXD1 — The SCI1 receive data input.
XB_OUT9 — Crossbar module output 9.
GPIOF5
42
PWM_1X — NanoEdge eFlexPWM sub-module 1 output X or input capture
X only on WCT1011A.
WCT101XADS, Rev. 1.1, 01/2021
NXP Semiconductors
33
PWM_FAULT7 — NanoEdge eFlexPWM fault input 7 only on WCT1011A.
After reset, the default state is GPIOF5.
VSS2
VDD2
43
44
-
-
I/O Ground — Provides ground to on-chip digital module.
I/O Power — Supplies 3.3 V power to on-chip digital module.
Port E GPIO — This GPIO pin can be individually programmed as an input
or output pin.
GPIOE0
GPIOE1
GPIOE2
GPIOE3
45
46
47
48
PWM_0B
PWM_0A
PWM_1B
PWM_1A
PWM_0B — NanoEdge eFlexPWM sub-module 0 output B or input capture
B.
After reset, the default state is GPIOE0.
Port E GPIO — This GPIO pin can be individually programmed as an input
or output pin.
PWM_0A — NanoEdge eFlexPWM sub-module 0 output A or input capture
A.
After reset, the default state is GPIOE1.
Port E GPIO — This GPIO pin can be individually programmed as an input
or output pin.
PWM_1B — NanoEdge eFlexPWM sub-module 1 output B or input capture
B.
After reset, the default state is GPIOE2.
Port E GPIO — This GPIO pin can be individually programmed as an input
or output pin.
PWM_1A — NanoEdge eFlexPWM sub-module 1 output A or input capture
A.
After reset, the default state is GPIOE3.
Port C GPIO — This GPIO pin can be individually programmed as an input
or output pin.
TA3 — Quad timer module A channel 3 input/output.
XB_IN6 — Crossbar module input 6.
TA3/XB_IN6/
EWM_OUT
GPIOC13
49
EWM_OUT — External watchdog monitor output.
After reset, the default state is GPIOC13.
Port F GPIO — This GPIO pin can be individually programmed as an input or
output pin.
CLKO1 — This is a buffered clock output 1; the clock source is selected by
clock out select (CLKOSEL) bits in the clock output select register
CLKO1/XB_IN7/ (CLKOUT) of the SIM.
CMPD_O
GPIOF1
GPIOE4
50
51
XB_IN7 — Crossbar module input 7.
CMPD_O — Analog comparator D output.
After reset, the default state is GPIOF1.
Port E GPIO — This GPIO pin can be individually programmed as an input
or output pin.
PWM_2B/XB_I
N2
PWM_2B — NanoEdge eFlexPWM sub-module 2 output B or input capture
WCT101XADS, Rev. 1.1, 01/2021
34
NXP Semiconductors
B.
XB_IN2 — Crossbar module input 2.
After reset, the default state is GPIOE4.
Port E GPIO — This GPIO pin can be individually programmed as an input
or output pin.
PWM_2A — NanoEdge eFlexPWM sub-module 2 output A or input capture
A.
PWM_2A/XB_I
N3
GPIOE5
GPIOE6
GPIOE7
52
53
54
XB_IN3 — Crossbar module input 3.
After reset, the default state is GPIOE5.
Port E GPIO — This GPIO pin can be individually programmed as an input
or output pin.
PWM_3B — NanoEdge eFlexPWM sub-module 3 output B or input capture
B.
PWM_3B/XB_I
N4
XB_IN4 — Crossbar module input 4.
After reset, the default state is GPIOE6.
Port E GPIO — This GPIO pin can be individually programmed as an input
or output pin.
PWM_3A — NanoEdge eFlexPWM sub-module 3 output A or input capture
A.
PWM_3A/XB_I
N5
XB_IN5 — Crossbar module input 5.
After reset, the default state is GPIOE7.
Port C GPIO — This GPIO pin can be individually programmed as an input
or output pin.
SDA0 — IIC0 serial data line.
SDA0/XB_OUT
4/PWM_FAULT
4
GPIOC14
55
XB_OUT4 — Crossbar module output 4.
PWM_FAULT4 — NanoEdge eFlexPWM fault input 4 only on WCT1011A.
After reset, the default state is GPIOC14.
Port C GPIO — This GPIO pin can be individually programmed as an input
or output pin.
SCL0 — IIC0 serial clock.
SCL0/XB_OUT
5/PWM_FAULT
5
GPIOC15
56
XB_OUT5 — Crossbar module output 5.
PWM_FAULT5 — NanoEdge eFlexPWM fault input 5 only on WCT1011A.
After reset, the default state is GPIOC15.
Connect a 2.2 μF or greater bypass capacitor between this pin and VSS to
stabilize the core voltage regulator output required for proper device
operation.
Port F GPIO — This GPIO pin can be individually programmed as an input or
output pin.
VCAP2
57
58
-
TB2/PWM_3X/X
B_IN2
GPIOF6
TB2 — Quad timer module B channel 2 input/output only on WCT1013A.
WCT101XADS, Rev. 1.1, 01/2021
NXP Semiconductors
35
PWM_3X — NanoEdge eFlexPWM sub-module 3 output X or input capture
X.
XB_IN2 — Crossbar module input 2.
After reset, the default state is GPIOF6.
Port F GPIO — This GPIO pin can be individually programmed as an input or
output pin.
TB3 — Quad timer module B channel 3 input/output only on WCT1013A.
CMPC_O— Analog comparator C output.
TB3/CMPC_O/
GPIOF7
59
SS1/XB_IN3
SS1 — SS1 is used in slave mode to indicate to the SPI1 module that the
current transfer is to be received.
XB_IN3 — Crossbar module input 3.
After reset, the default state is GPIOF7.
VDD3
VSS3
60
61
-
-
I/O Power — Supplies 3.3 V power to on-chip digital module.
I/O Ground — Provides ground to on-chip digital module.
Test Data Output — This tri-stateable output pin provides a serial output
data stream from the JTAG/EOnCE port. It is driven in the shift-IR and
shift-DR controller states, and changes on the falling edge of TCK.
TDO
TMS
TDI
62
63
64
GPIOD1
GPIOD3
GPIOD0
Port D GPIO — This GPIO pin can be individually programmed as an input
or output pin.
After reset, the default state is TDO.
Test Mode Select Input — This input pin is used to sequence the JTAG TAP
controller’s state machine. It is sampled on the rising edge of TCK and has
an on-chip pull-up resistor.
Port D GPIO — This GPIO pin can be individually programmed as an input
or output pin.
After reset, the default state is TMS.
NOTE: Always tie the TMS pin to VDD through a 2.2 kΩ resistor if need to
keep on-board debug capability. Otherwise, directly tie to VDD.
Test Data Input — This input pin provides a serial input data stream to the
JTAG/EOnCE port. It is sampled on the rising edge of TCK and has an
on-chip pull-up resistor.
Port D GPIO — This GPIO pin can be individually programmed as an input
or output pin.
After reset, the default state is TDI.
WCT101XADS, Rev. 1.1, 01/2021
36
NXP Semiconductors
4.5 Ordering information
Table 10 lists the pertinent information needed to place an order. Consult a NXP Semiconductors sales
office to determine availability and to order this device.
Table 10. MWCT101xAVLH ordering information
Device
Supply voltage
Package type
Pin count
Ambient temp.
-40 to +105℃
-40 to +105℃
Order number
MWCT1011AVLH
3.0 to 3.6 V
LQFP
64
MWCT1011AVLH
MWCT1013AVLH
3.0 to 3.6 V
LQFP
64
MWCT1013AVLH
4.6 Package outline drawing
To find a package drawing, go to nxp.com and perform a keyword search for the drawing’s document
number of 98ASS23234W.
WCT101XADS, Rev. 1.1, 01/2021
NXP Semiconductors
37
5 Software Library
The software for WCT101xA is matured and tested for production ready. NXP provides a Wireless
Charging Transmitter (WCT) software library for speeding user designs. In this library, low-level drivers
of HAL (Hardware Abstract Layer), callback functions for library access are open to user. For the
software API and library details, see the WCT101xA TX Library User’s Guide (WCT101XALIBUG).
5.1 Memory map
WCT101xA has large on-chip Flash memory and RAM for user design. Besides wireless charging
transmitter library code, the user can develop private functions and link it to library through predefined
APIs.
Table 11. WCT101xA memory footprint
Part
Memory
Flash
RAM
Total size
64 Kbytes
8 Kbytes
Library size
41.9 Kbytes
3.22 Kbytes
41.9 Kbytes
3.22 Kbytes
FreeMASTER size EEPROM size
Free size
17.6 Kbytes
4.65 Kbytes
241.6 Kbytes
28.65 Kbytes
3.5 Kbytes
0.13 Kbytes
3.5 Kbytes
0.13 Kbytes
1 Kbytes
0 Kbytes
1 Kbytes
0 Kbytes
WCT1011A
Flash
RAM
288 Kbytes
32 Kbytes
WCT1013A
5.2 Software library and API description
For more information about WCT software library and API definition, see the WCT101xA TX Library
User’s Guide (WCT101XALIBUG).
WCT101XADS, Rev. 1.1, 01/2021
38
NXP Semiconductors
6 Design Considerations
6.1 Electrical design considerations
To ensure correct operations on the device and system, pay attention to the following points:
• The minimum bypass requirement is to place 0.01 - 0.1μF capacitors positioned as near as
possible to the package supply pins. The recommended bypass configuration is to place one bypass
capacitor on each of the VDD/VSS pairs, including VDDA/VSSA. Ceramic and tantalum
capacitors tend to provide better tolerances.
• Bypass the VDD and VSS with approximately 10μF, plus the number of 0.1μF ceramic
capacitors.
• Consider all device loads as well as parasitic capacitance due to PCB traces when calculating
capacitance. This is especially critical in systems with higher capacitive loads that could create
higher transient currents in the VDD and VSS circuits.
• Take special care to minimize noise levels on the VDDA and VSSA pins.
• It is recommended to use separate power planes for VDD and VDDA and use separate ground
planes for VSS and VSSA. Connect the separate analog and digital power and ground planes as
near as possible to power supply outputs. If an analog circuit and digital circuit are powered by the
same power supply, connect a small inductor or ferrite bead in serial with VDDA trace.
• If desired, connect an external RC circuit to the RESET pin. The resistor value should be in the
range of 4.7 kΩ – 10 kΩ; and the capacitor value should be in the range of 0.1μF – 4.7μF.
• Add a 2.2 kΩ external pull-up on the TMS pin of the JTAG port to keep device in a restate during
normal operation if JTAG converter is not present.
• During reset and after reset but before I/O initialization, all I/O pins are at input mode with internal
weak pull-up.
• To eliminate PCB trace impedance effect, each ADC input should have a no less than 33 pF/10 Ω
RC filter.
• To assure chip reliable operation, reserve enough margin for chip electrical design. Figure 3 shows
the relationship between electrical ratings and electrical operating characteristics for correct chip
operation.
WCT101XADS, Rev. 1.1, 01/2021
NXP Semiconductors
39
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Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
Expected permanent failure
- No permanent failure
- Possible decreased life
- No permanent failure
- Correct operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- Possible incorrect operation
−
+
Operating (power on)
)
.
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.
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H
H
Fatal range
Handling range
Fatal range
Expected permanent failure
Expected permanent failure
No permanent failure
−
+
Handling (power off)
Figure 3. Relationship between ratings and operating characteristics
6.2 PCB layout considerations
• Provide a low-impedance path from the board power supply to each VDD pin on the device and
from the board ground to each VSS pin.
• Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and
VSS pins are as short as possible.
• PCB trace lengths should be minimal for high-frequency signals.
• Physically separate analog components from noisy digital components by ground planes. Do not
place an analog trace in parallel with digital traces. Place an analog ground trace around an analog
signal trace to isolate it from digital traces.
• The decoupling capacitors of 0.1μF must be placed on the VDD pins as close as possible, and
place those ceramic capacitors on the same PCB layer with WCT101xA device. VIA is not
recommend between the VDD pins and decoupling capacitors.
• As the wireless charging system functions as a switching-mode power supply, the power
components layout is very important for the whole system power transfer efficiency and EMI
performance. The power routing loop should be as small and short as possible. Especially for the
resonant network, the traces of this circuit should be short and wide, and the current loop should be
optimized smaller for the MOSFETs, resonant capacitor and primary coil. Another important thing
is that the control circuit and power circuit should be separated.
6.3 Thermal design considerations
WCT101xA power consumption is not so critical, so there is not additional part needed for power
dissipation. However, the power inverter needs the additional PCB Cu copper to dissipate the heat, so
WCT101XADS, Rev. 1.1, 01/2021
40
NXP Semiconductors
good thermal package MOSFET is recommended, such as DFN package, and for the resonant capacitor,
COG material, and 1206 or 1210 package are recommended to meet the thermal requirement. The worst
thermal case is on the inverter, so the user should make some special actions to dissipate the heat for good
transmitter system thermal performance.
WCT101XADS, Rev. 1.1, 01/2021
NXP Semiconductors
41
7 Links
•
•
•
nxp.com
nxp.com/products/power-management/wireless-charging-ics
www.wirelesspowerconsortium.com
8 Revision History
This table summarizes revisions to this document.
Table 12. Revision history
Revision number
Date
Substantive changes
Initial release.
0
09/2016
05/2020
01/2021
1
Added MWCT1011A3VLH.
1.1
Changed "AEC-Q100 grade 2 certification" to "Qualified to AEC100
Test Group A&B".
9 Addendum for MWCT1011A3VLH
This addendum provides update to all revisions of the MWCT1011AVLH Data Sheet (document
MWCT101XADS).
The purpose of the addendum is to outline the differences that need to be considered in designing the
MWCT1011A3VLH and MWCT1011AVLH.
MWCT1011A3VLH has exactly the same peripherals and electrical specifications and package as the
MWCT1011AVLH.
9.1 Ordering information
The following table lists the pertinent information needed to place an order. Consult a NXP
Semiconductors sales office to determine availability and order this device.
Table 13. MWCT1011A3VLH ordering information
Device
Supply voltage
Package type Pin count
LQFP 64
Ambient temp.
Order number
MWCT1011A3VLH
3.0 to 3.6 V
-40 to +105 ℃
MWCT1011A3VLH
9.2 Package outline drawing
To find a package drawing, go to www.nxp.com and perform a keyword search for the drawing’s
document number of 98ASS23234W.
WCT101XADS, Rev. 1.1, 01/2021
42
NXP Semiconductors
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Document Number: WCT101XADS
Rev. 1.1.1
01/2021
相关型号：
WCT101XADS
Compliant with the latest version Wireless Power Consortium (WPC) power class 0 specification power transmitter design
NXP
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