XA-SCC [NXP]
CMOS 16-bit communications microcontroller; CMOS 16位微控制器的通信
| 型号： | XA-SCC |
| 厂家： | 
NXP |
| 描述： | CMOS 16-bit communications microcontroller |
| 文件： | 总42页 (文件大小：232K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
XA-SCC
CMOS 16-bit communications
microcontroller
Preliminary specification
Supersedes data of 1999 Feb 23
IC25 Data Handbook
1999 Mar 29
Philips
Semiconductors
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
GENERAL DESCRIPTION
• Memory controller also generates 6 chip selects to support
SRAM, ROM, Flash, EPROM, peripheral chips, etc. without
external glue.
The XA-SCC device is a member of Philips’ XA (eXtended
Architecture) family of high performance 16-bit single-chip
microcontrollers.
• Supports off-chip addressing up to 32 MB (2 x 2**24 address
spaces) in Harvard architecture, or 16MB in unified memory
configuration.
The XA-SCC includes a complete onboard DRAM controller capable
of supporting up to 32MegaBytes of DRAM.
The XA-SCC device combines many powerful communications
oriented peripherals on one chip. 4 Full Function SCC’s, 8 DMA
channels (2 per SCC), hardware autobaud up to 921.6Kbps, IDL
TDM interface, two timers/counters, 1 watchdog timer, and multiple
general purpose I/O ports. It is suited for many high performance
embedded communications functions, including ISDN terminal
adaptors and Asynchronous Muxes.
• A clock output reference “ClkOut” is added to simplify external bus
interfacing.
• High performance 8-channel DMA Controller offloads the CPU for
moving data to/from SCC’s and memory.
• Two standard counter/timers with enhanced features (same as
XA-G3 T0, T1). Both timers have a toggle output capability.
• Watchdog timer.
SPECIFIC FEATURES OF THE XA-SCC
• Seven standard software interrupts, plus four High Priority
• 3.3V to 5.5V operation to 30MHz over the industrial temperature
Software Interrupts, plus 7 levels of Hardware Event Interrupts.
range, available in 100 pin LQFP package.
• Active low reset output pin indicates all internal reset occurrences
(watchdog reset and the RESET instruction). A reset source
register allows program determination of the cause of the most
recent reset.
• 4 onboard SCC’s for 2B+D plus Asynch port, or any combination
of 4 sync/async ports. Industry standard IDL and SCP interfaces
for glueless connection to U-Chip or S/T chip. Sync data rates to
4Mbps. Asynch data rates to 921.6Kbps with/without autobaud.
• 32 General Purpose I/O pins, each with 4 programmable output
• Complete onboard DRAM controller supports 5 banks of up to
8MBytes each. Interfaces without glue chips to most industry
standard DRAMs.
configurations.
• Power saving operating modes: Idle and Power-Down. Wake-Up
from power-down via an external interrupt is supported.
ORDERING INFORMATION
ROMless Only
TEMPERATURE RANGE °C AND PACKAGE
–40 to +85, 100-pin Low Profile Quad Flat Pkg. (LQFP)
FREQ (MHz)
PACKAGE DRAWING NUMBER
PXASCCKFBE
30
SOT407-1
NOTE:
1. K=30MHz, F = (–40 to +85 °C), BE = LQFP
2
1999 Mar 29
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
PIN CONFIGURATION
VSS 76
VDD 77
50 WE
49 CS0
48 CS1_RAS1
47 CS2_RAS2
46 CS3_RAS3
45 ClkOut
44 VSS
43 VDD
42 D15
41 D14
40 D13
39 D12
38 D11
37 D10
36 D9
CD1_Int2 78
MOLD MARK
Int0 79
P2.0_RxD3 80
P2.1_TxD3 81
P2.2_RTClk3 82
P2.3_ComClk_TRClk3 83
P2.4_CD3 84
P2.5_CTS3 85
P2.6_RTS3 86
P2.7_Sync3_BRG3 87
XA-SCC
PLASTIC LOW PROFILE QUAD FLAT PACKAGE (LQFP)
Top View
VSS 88
VDD 89
P0.0_Sync0_BRG0_SDS2 90
P0.1_RTS0_L1RQ 91
P0.2_CTS0_L1GR 92
P0.3_CD0_L1SY1 93
P0.4_TRClk0_SDS1 94
P0.5_RTClk0_L1Clk 95
TxD0_L1TxD 96
35 D8
34 D7
33 D6
32 D5
31 D4
30 D3
MOLD MARK
RxD0_L1RxD 97
29 VDD
28 VSS
27 D2
SCPClk 98
PIN INDEX
P0.6_SCPTx 99
P0.7_SCPRx 100
26 D1
NOTE:
Address lines output during various DRAM CAS cycles are shown in parentheses.
See DRAM controller for details.
SU01120
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1999 Mar 29
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
LOGIC SYMBOL
V
V
SS
DD
Int0
XTAL1
XTAL2
MISC.
Int2
SCC1
CD1
PORT3
CS4, RAS4
RTClk1
RTS1
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
CS5, RAS5
ResetOut, Timer0
Timer1
BRG1, Sync1
CTS1
CS3, RAS3
CS2, RAS2
RxD1
TxD1
CS1, RAS1
CS0
Int1
TRClk1
SCC3
PORT2
RxD3
TxD3
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
RTClk3
ComClk, TRClk3
CD3
A19 – A0 ( DRAM A22 – A0)
CTS3
RTS3
BRG3, Sync3
D15 – D0
SCC2
PORT1
RxD2
TxD2
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
RTClk2
TRClk2
CD2
ClkOut
CASH, BHE
CASL, BLE
CTS2
RTS2
BRG2, Sync2
OE
WE
IDL
SCC0
PORT0
Wait, Size16
ResetIn
L1TxD
TxD0
RxD0
L1RxD
BRG0, Sync0
RTS0
SDS2
L1RQ
L1GR
L1SY1
SDS1
L1Clk
0.0
0.1
0.2
0.3
0.4
0.5
CTS0
CD0
TRClk0
RTClk0
SCPTx
SCPRx
0.6
0.7
SCPClk
SU01121
4
1999 Mar 29
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
BLOCK DIAGRAM
RESET
CONTROL &
STATUS
TIMERS 0,1
WATCHDOG
TIMER
INTERRUPT
CONTROLLER
256 BYTES
RAM
XA CPU
SCP
INTERFACE
SCP PORT
GPIO
PORTS and
PIN
FUNCTION
AUTOBAUD
x4
MUX
IDL
INTERFACE
EXTERNAL
MEMORY
and I/O
MIF and
DRAM
CONTROLLER
DMA
CHANNELS
x8
IDL and
NMSI
PORTS
SCCs x4
BUS
v.54
2047
x2
NOTE:
Main Communications Data paths shown in bold.
SU01122
Figure 1. XA-SCC Block Diagram
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1999 Mar 29
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
PIN DESCRIPTIONS
LQFP
PIN NO.
MNEMONIC
TYPE
NAME AND FUNCTION
V
SS
1, 19,
28, 44,
59, 76,
88
I
Ground: 0V reference.
V
DD
2, 20,
29, 43,
62, 77,
89
I
Power Supply: This is the power supply voltage for normal, idle, and power down operation.
ResetIn
WAIT/Size16
XTALIn
55
52
60
I
I
I
Reset: A low on this pin resets the microcontroller, causing I/O ports and peripherals to take on their
default states, and the processor to begin execution at the address contained in the reset vector.
Wait/Size16: During Reset, this input determines bus size for boot device (1 = 16 bit boot device,
0 = 8 bit.) During normal operation this is the Wait input (1 = Wait, 0 = Proceed.)
Crystal 1: Input to the inverting amplifier used in the oscillator circuit and input to the internal clock
generator circuits.
XTALOut
CS0
61
49
I
Crystal 2: Output from the oscillator amplifier.
O
Chip Select 0: This output provides the active low chip select to the boot device (usually ROM or
Flash.) It cannot be connected to DRAM. From reset, it is enabled and mapped to an address range
based at 000000h. It can be remapped to a higher base in the address map (see the Memory Interface
chapter in the XA-SCC User Manual.)
CS1_RAS1
48
O
Chip Select 1 , RAS 1: Chip selects 1 through 5 come out of reset disabled. They can be programmed
to function as normal chip selects, or as RAS strobes to DRAM. CS1 can be “swapped” with CS0
(see the SWAP operation and control bit in the Memory Controller chapter of the XA-SCC
User Manual.) CS1 is usually mapped to be based at 000000h eventually, but is capable of being based
anywhere in the 16MB space.
CS2_RAS2
CS3_RAS3
47
46
O
O
CS2 , RAS 2: Active low chip selects CS1 through CS5 come out of reset disabled. They can be
programmed to function as normal chip selects, or as RAS strobes to DRAM. CS2 through CS5 are
not used with the “SWAP” operation (see Memory Controller chapter in the XA-SCC User Manual.)
They are mappable to any region of the 16MB address space.
CS3, RAS 3: See chip select 2 for description.
see pins 56,57 for 2 more chip
selects
WE
OE
50
51
54
O
O
O
Write Enable: Goes active low during all bus write cycles only.
Output Enable: Goes active low during all bus read cycles only.
BLE_CASL
Byte Low Enable or CAS_Low_Byte: Goes active low during all bus cycles that access D7–D0, read
or write, Generic or DRAM. Functions as CAS during DRAM cycles.
BHE_CASH
ClkOut
53
45
O
O
Byte High Enable or CAS_High_Byte: Goes active low during all bus cycles that access D15–D8,
read or write, Generic or DRAM. Functions as CAS during DRAM cycles.
Clock Output: This pin outputs a buffered version of the internal CPU clock. The clock output may be
used in conjunction with the external bus to synchronize WAIT state generators, etc. The clock output
may be disabled by software. WARNING: The capacitive loading on this output must not exceed 40pF.
A19–A0
24–21,
18–3
O
Address[19:0]: These address lines output a19–a0 during generic (SRAM etc) bus cycles. DRAMs are
connected only to pins 22,21, 18–10 (pins A17 to A7; see User Manual MIF Chapter for connecting
various DRAM sizes); the appropriate address values are multiplexed onto these 11 pins for RAS and
CAS during DRAM bus cycles.
D15–D0
42–30,
27–25
I/O
I/O
I/O
I/O
Data[15:0]: Bi-directional data bus, D15–D0.
1
P0.0
90
91
92
P0.0_Sync0_BRG0_SDS2: Port 0 Bit 0, or SCC0 Sync input or output, or SCC0 BRG output, or SCC0
TxClk output, or IDL SDS2 output.
1
P0.1
P0.1_RTS0_L1RQ: Port0 Bit1 , or SCC0 RTS (Request to send) output, or IDL L1RQ (D Channel
Request) output.
1
P0.2
P0.2_CTS0_L1GR: Port 0 Bit2, or SCC0 CTS (Clear to Send) input or IDL L1GR (D Channel Grant)
input
1
P0.3
93
94
I/O
I/O
P0.3_CD0_L1SY1: Port 0 Bit 3, or SCC0 Carrier Detect input, or IDL Sync input.
P0.4_TRClk0_SDS1: Port 0 Bit 4, or SCC0 TR clock input, or IDL SDS1 output.
1, 2
P0.4
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1999 Mar 29
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
LQFP
PIN NO.
MNEMONIC
TYPE
NAME AND FUNCTION
1, 2
P0.5
95
I/O
I/O
I/O
O
P0.5_RTClk0_L1Clk: Port 0 Bit 5, or SCC0 RT clock input, or IDL Clock input.
P0.6_SCPTx: Port 0 Bit 6, or SCP interface Transmit data output.
P0.7_SCPRx: Port 0 Bit 7, or SCP interface Receive data input.
TxD0_L1Txd: Transmit data for SCC0 in NMSI mode, or for IDL bus
RxD0_L1Rxd: Receive data for SCC0 in NMSI mode, or for IDL bus
SCPClk: This output provides the gated clock for the SCP bus.
P1.0_RxD2: Port 1 Bit 0, or SCC2 RxD input
1
P0.6
99
1
P0.7
100
96
TxD0_L1TxD
RxD0_L1RxD
SCPClk
97
I
98
O
P1.0
68
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P1.1
69
P1.1_TxD2: Port 1 Bit 1, or SCC2 TxD output
2
P1.2
70
P1.2_RTClk2: Port 1 Bit 2, or SCC2 RT Clock input
2
P1.3
71
P1.3_TRClk2: Port 1 Bit 3, or SCC2 TR Clock input
P1.4
P1.5
P1.6
P1.7
72
P1.4_CD2: Port 1 Bit 4, or SCC2 Carrier Detect input
73
P1.5_CTS2: Port 1 Bit 5, or SCC2 Clear To Send input
P1.6_RTS2: Port 1 Bit 6, or SCC2 Request To Send output
74
75
P1.7_BRG2_Sync2: Port 1 Bit 7, or SCC2 Sync input or output, or BRG output, or TxClk output (see
SCC clocks diagrams in User Manual Chp 5)
P2.0
P2.1
80
81
82
83
84
85
86
87
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P2.0_RxD3: Port 2 Bit 0, or SCC3 Rx Data input
P2.1_TxD3: Port 2 Bit 1, or SCC3 Tx Data output
P2.2_RTClk3: Port 2 Bit 2, or SCC3 RT Clock input
P2.3_ComClk_TRClk3: Port 2 Bit 3, or SCC3 TR Clock input
P2.4_CD3: Port 2 Bit 4, or SCC3 Carrier Detect input
P2.5_CTS3: Port 2 Bit 5, or SCC3 Clear To Send input
P2.6_RTS3: Port 2 Bit 6, or SCC3 Request To Send output
2
P2.2
2
P2.3
P2.4
P2.5
P2.6
P2.7
P2.7_Sync3_BRG3: Port 2 Bit 7, or SCC3 Sync input or output, or BRG output, or TxClk output (see
SCC clocks diagrams in User Manual Chp 5)
2
P3.0
56
57
58
I/O
I/O
I/O
P3.0_CS4_RAS4_RTClk1: Port 3 Bit 0, or CS4 or RAS4 output, or SCC1 RT Clock input
P3.1_CS5_RAS5_RTS1: Port 3 Bit 1, or CS5 or RAS5 output, or SCC1 Request To Send output
P3.2_Timer0_ResetOut: Port 3 Bit 2, or Timer0 input or output, or ResetOut output.
P3.1
P3.2
ResetOut: If the ResetOut function is selected, this pin outputs a low whenever the XA-SCC processor
is reset by an internal source (watchdog reset or the RESET instruction.) WARNING: Unlike the other
31 GPIO pins, during power up reset, this pin can output a strongly driven low pulse. The duration of this
low pulse ranges from 0ns to 258 system clocks, starting at the time that V is valid. The state of the
CC
ResetIn pin does not affect this pulse.
When used as GPIO, this pin can also be driven low by software without resetting the XA-SCC.
P3.3
63
I/O
P3.3_Timer1_BRG1_Sync1: Port 3 Bit 3, or Timer1 input or output, or SCC1 BRG output, or SCC1
Sync input or output
P3.4
P3.5
P3.6
64
65
66
67
78
79
I/O
I/O
I/O
I/O
I
P3.4_CTS1: Port 3 Bit 4, or SCC1 Clear To Send input
P3.5_RxD1: Port 3 Bit 5, or SCC1 Receive Data input
P3.6_TxD1: Port 3 Bit 6, or SCC1 Transmit Data output
P3.7_Int1_TRClk1: Port 3 Bit 7, or External Interrupt1 input, or SCC1 TR Clock input
CD1_Int2: SCC1 Carrier Detect, or External Interrupt 2
External Interrupt 0
2
P3.7
CD1_Int2
I
Int0
NOTES:
1. See XA-SCC User Guide “Pins Chapter” for how to program selection of pin functions.
2. RTClk input is usually used for Rx Clock if an external clock is needed, but can be used for either Rx or Tx or both. TRClk is usually used for
Tx Clock, but can be used for Rx or Tx or both.
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1999 Mar 29
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
SFRs are accessed by “direct addressing” only (see IC25 XA User
Manual for direct addressing.) The MMRs are specific to the
XA-SCC on board peripherals, and can be accessed by any
addressing mode that can be used for off chip data accesses. The
MMRs are implemented in a relocatable block. See the MIF chapter
in the XA-SCC User Manual for details on how to relocate the
MMRs by writing a new base address into the MRBL and MRBH
(MMR Base Low and High) registers.
CONTROL REGISTER OVERVIEW
There are two types of control registers in the XA-SCC, these are
SFRs (Special Function Registers), and MMRs (Memory Mapped
Registers.) The SFR registers, with the exception of MRBL, MRBH,
MICFG, BCR, BRTH, BRTL, and RSTSRC are the standard XA core
registers. See WARNINGs about BCR, BRTH, and BRTL in the
Table below.
1, 2, 3
Table 1. Special Function Registers (SFR)
BIT FUNCTIONS AND ADDRESSES
RESET
SFR
Address
MSB
LSB
VALUE
NAME
BCR
DESCRIPTION
Bus Configuration Reg
RESERVED—see warning
46Ah
WARNING—Never write to the BCR register in the XA-SCC part—it is initialized to
07h, the only legal value. This is not the same as for other XA derivatives.
07h
BTRH
BTRL
Bus Timing Reg High
Bus Timing Reg Low
469h
468h
WARNING—Immediately after reset, always write BTRH = 51h, followed by writing
BTRL = 40h in that order. Follow these two writes with five NOPS. This is not the
same as for other XA derivatives.
FFh
EFh
MRBL#
MRBH#
MICFG#
MMR Base Address Low
MMR Base Address High
496h
497h
499h
MA15
MA23
–
MA14
MA22
–
MA13
MA21
–
MA12
MA20
–
–
MA19
–
–
MA18
–
–
MA17
–
MRBE
MA16
x0h
xx
ClkOut Tri-St Enable
1 = Enabled
CLKOE
01h
CS
DS
ES
Code Segment
Data Segment
Extra Segment
443h
441h
442h
00h
00h
00h
33F
33E
33D
33C
33B
33A
339
338
IEH*
Interrupt Enable High
427h
EHSWR3 EHSWR2 EHSWR1 EHSWR0
ESCP
EAuto
ESC23
ESC01
00h
337
EA
–
336
335
EDMAL
PT0
334
333
ET1
–
332
331
ET0
330
IEL*
IPA0
IPA1
IPA2
IPA3
IPA4
IPA5
IPA6
IPA7
Interrupt Enable Low
Interrupt Priority A0
Interrupt Priority A1
Interrupt Priority A2
Interrupt Priority A3
Interrupt Priority A4
Interrupt Priority A5
Interrupt Priority A6
Interrupt Priority A7
426h
4A0h
4A1h
4A2h
4A3h
4A4h
4A5h
4A6h
4A7h
EDMAH
EX2
EX1
EX0
00h
00h
00h
00h
00h
00h
00h
00h
00h
PX0
–
PT1
–
PX1
–
PDMAL
–
PX2
Reserved
–
PDMAH
PSC01
PAutoB
PHSWR0
PHSWR2
–
–
–
–
PSC23
PSCP
–
–
PHSWR1
PHSWR3
–
–
387
38F
397
386
38E
396
385
38D
395
384
38C
394
383
38B
393
382
38A
392
381
389
391
380
388
390
P0*
P1*
P2*
Port 0
Port 1
Port 2
430h
431h
432h
FFh
FFh
FFh
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1999 Mar 29
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
BIT FUNCTIONS AND ADDRESSES
SFR
Address
RESET
VALUE
MSB
LSB
398
NAME
DESCRIPTION
39F
39E
39D
39C
39B
39A
399
P3*
Port 3
433h
FFh
P0CFGA
P1CFGA
P2CFGA
P3CFGA
P0CFGB
P1CFGB
P2CFGB
P3CFGB
Port 0 Configuration A
Port 1 Configuration A
Port 2 Configuration A
Port 3 Configuration A
Port 0 Configuration B
Port 1 Configuration B
Port 2 Configuration B
Port 3 Configuration B
470h
471h
472h
473h
4F0h
4F1h
4F2h
4F3h
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
227
–
226
–
225
–
224
–
223
–
222
–
221
PD
220
IDL
PCON*
Power Control Reg
404h
00h
20F
SM
207
C
20E
TM
206
AC
20D
RS1
205
–
20C
RS0
204
–
20B
IM3
203
–
20A
IM2
202
V
209
IM1
201
N
208
IM0
200
Z
PSWH*
PSWL*
Program Status Word High
Program Status Word Low
80C51 compatible PSW
Reset Source Reg
401h
400h
402h
463h
Note 5
Note 5
Note 6
Note 7
217
C
216
AC
215
F0
214
RS1
213
RS0
212
V
211
F1
210
P
PSW51*
RSTSRC
ROEN
–
–
–
–
R_WD
R_CMD
R_EXT
RTH0
RTH1
RTL0
RTL1
Timer 0 Reload High
Timer 1 Reload High
Timer 0 Reload Low
Timer 1 Reload Low
455h
457h
454h
456h
00h
00h
00h
00h
SCR
System Configuration Reg
Segment Selection Reg
440h
403h
–
–
–
–
PT1
PT0
CM
PZ
00h
00h
21F
21E
21D
21C
21B
21A
219
218
SSEL*
ESWEN
R6SEG
R5SEG
R4SEG
R3SEG
R2SEG
R1SEG
R0SEG
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1999 Mar 29
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
BIT FUNCTIONS AND ADDRESSES
SFR
RESET
Address
MSB
LSB
SWE1
VALUE
NAME
SWE
DESCRIPTION
Software Interrupt Enable
47Ah
–
SWE7
SWE6
SWE5
SWE4
SWE3
SWE2
00h
357
–
356
355
354
353
352
351
350
SWR*
Software Interrupt Request
42Ah
SWR7
SWR6
SWR5
SWR4
SWR3
SWR2
SWR1
00h
287
TF1
286
285
TF0
284
283
IE1
282
IT1
281
IE0
280
IT0
TCON*
TH0
Timer 0/1 Control
Timer 0 High
Timer 1 High
Timer 0 Low
410h
451h
453h
450h
452h
45Ch
TR1
TR0
00h
00h
00h
00h
00h
00h
TH1
TL0
TL1
Timer 1 Low
TMOD
Timer 0/1 Mode
GATE
C/T
M1
M0
GATE
C/T
M1
M0
28F
–
28E
–
28D
–
28C
–
28B
–
28A
289
–
288
TSTAT*
Timer 0/1 Extended Status
411h
T1OE
T0OE
00h
2FF
2FE
2FD
2FC
–
2FB
–
2FA
2F9
2F8
–
WDCON* Watchdog Control
41Fh
45Fh
45Dh
45Eh
PRE2
PRE1
PRE0
WDRUN
WDTOF
Note 8
00h
xx
WDL
Watchdog Timer Reload
WFEED1
Watchdog Feed 1
Watchdog Feed 2
WFEED2
xx
NOTES:
*
#
SFRs marked with an asterisk (*) are bit addressable.
SFRs marked with a pound sign (#) are additional SFR registers specific to the XA-SCC.
1. The XA-SCC implements an 8-bit SFR bus, as stated in Chapter 8 of the IC25 Data Handbook XA User Guide. All SFR accesses must be
8-bit operations. Attempts to write 16 bits to an SFR will actually write only the lower 8 bits. Sixteen bit SFR reads will return undefined data
in the upper byte.
2. Unimplemented bits in SFRs are X (unknown) at all times. Ones should not be written to these bits since they may be used for other
purposes in future XA derivatives. The reset value shown for these bits is 0.
3. The XA guards writes to certain bits (typically interrupt flags) that may be written by a peripheral function. This prevents loss of an interrupt
or other status if a bit was written directly by a peripheral action between the read and write of an instruction that performs a
read-modify-write operation. XA-SCC SFR bits that are guarded in this manner are: TF1, TF0, IE1, and IE0 (in TCON), and WDTOF (in
WDCON).
4. Port configurations default to quasi-bidirectional when the XA begins execution after reset. Thus all PnCFGA registers will contain FFh
and PnCFGB register will contain 00h. See warning in XA-SCC User Manual about P3.2_Timer0_ResetOut pin during first 258 clocks after
power up. Basically, during this period, this pin may output a strongly driven low pulse. If the pulse does occur, it will terminate in a
transition to high at a time no later than the 259th system clock after valid VCC power up.
5. SFR is loaded from the reset vector.
6. F1, F0, and P reset to 0. All other bits are loaded from the reset vector.
7. The RSTSRC register reflects the cause of the last XA reset. One bit will be set to 1, the others will be 0. RSTSRC[7] enables the ResetOut
function; 1 = Enabled, 0 = Disabled. See XA-SCC User Manual for details; RSTSRC[7] differs in function from most other XA derivatives.
8. The WDCON reset value is E6 for a Watchdog reset, E4 for all other reset causes.
10
1999 Mar 29
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
Table 2. Memory Mapped Registers
Read/Write or
Read Only
Address
Offset
Reset
Value
MMR Name
Size
Description
SCCO Registers
SCC0 Write Register 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
8
8
8
8
8
8
8
800h
802h
804h
806h
808h
80Ah
80Ch
Command register
00h
xx
SCC0 Write Register 1
SCC0 Write Register 2
SCC0 Write Register 3
SCC0 Write Register 4
SCC0 Write Register 5
SCC0 Write Register 6
Tx/Rx Interrupt & data transfer mode
Extended Features Control
xx
Receive Parameter and Control
Tx/Rx misc. parameters & mode
Tx. parameter and control
00h
00h
00h
Sync character or SDLC address field or Match
Character 0
00h
SCC0 Write Register 7
SCC0 Write Register 8
SCC0 Write Register 9
SCC0 Write Register 10
SCC0 Write Register 11
SCC0 Write Register 12
SCC0 Write Register 13
SCC0 Write Register 14
SCC0 Write Register 15
SCC0 Write Register 16
SCC0 Write Register 17
SCC0 Read Register 0
SCC0 Read Register 1
Reserved—do not write
SCC0 Read Register 3
see WR16 and 17
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
8
8
8
8
8
8
8
8
8
8
8
8
8
80Eh
810h
812h
814h
816h
818h
81Ah
81Ch
81Eh
828h
82Ah
820h
822h
824h
826h
Sync character or SDLC flag or Match Character 1
Transmit Data Buffer
xx
xx
Master Interrupt control
xx
Misc. Tx/Rx control register
Clock Mode Control
00h
xx
Lower Byte of Baud rate time constant
Upper Byte of Baud rate time constant
Misc. Control bits
00h
00h
xx
External/Status interrupt control
Match Character 2 (WR16)
f8h
00h
00h
—
Match Character 3 (WR17)
Tx/Rx buffer and external status
Receive condition status/residue code
RO
—
—
RO
8
Interrupt Pending Bits
—
828–82Ah see WR16 and WR17 above
—
SCC0 Read Register 6
SCC0 Read Register 7
SCC0 Read Register 8
Reserved
RO
RO
RO
8
8
8
82Ch
82Eh
SDLC byte count low register
SDLC byte count high & FIFO status
Receive Buffer
—
—
830h
—
832h
—
SCC0 Read Register 10
Reserved
RO
8
834h
Loop/clock status
—
836–83Eh
—
SCC1 Registers
SCC1 Write Register 0
SCC1 Write Register 1
SCC1 Write Register 2
SCC1 Write Register 3
SCC1 Write Register 4
SCC1 Write Register 5
SCC1 Write Register 6
R/W
R/W
R/W
R/W
R/W
R/W
R/W
8
8
8
8
8
8
8
840h
842h
844h
846h
848h
84Ah
84Ch
Command register
00h
xx
Tx/Rx Interrupt & data transfer mode
Extended Features Control
Receive Parameter and Control
Tx/Rx misc. parameters & mode
Tx. parameter and control
xx
00h
00h
00h
00h
Sync character or SDLC address field or Match
Character 0
SCC1 Write Register 7
SCC1 Write Register 8
SCC1 Write Register 9
SCC1 Write Register 10
SCC1 Write Register 11
SCC1 Write Register 12
R/W
R/W
R/W
R/W
R/W
R/W
8
8
8
8
8
8
84Eh
850h
852h
854h
856h
858h
Sync character or SDLC flag or Match Character 1
Transmit Data Buffer
xx
xx
Master Interrupt control
xx
Misc. Tx/Rx control register
Clock Mode Control
00h
xx
Lower Byte of Baud rate time constant
00h
11
1999 Mar 29
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
Read/Write or
Read Only
Address
Offset
Reset
Value
MMR Name
Size
Description
SCC1 Write Register 13
SCC1 Write Register 14
SCC1 Write Register 15
SCC1 Write Register 16
SCC1 Write Register 17
SCC1 Read Register 0
SCC1 Read Register 1
Reserved
R/W
R/W
R/W
R/W
R/W
RO
8
8
8
8
8
8
8
85Ah
85Ch
85Eh
868h
86Ah
860h
862h
864h
866h
Upper Byte of Baud rate time constant
Misc. Control bits
00h
xx
External/Status interrupt control
Match Character 2 (WR16)
f8h
00h
00h
—
Match Character 3 (WR17)
Tx/Rx buffer and external status
Receive condition status/residue code
RO
—
—
SCC1 Read Register 3
see WR16 and 17
RO
8
Interrupt Pending Bits
—
868–86Ah see WR16 and WR17 above
—
SCC1 Read Register 6
SCC1 Read Register 7
SCC1 Read Register 8
Reserved
RO
RO
RO
8
8
8
86Ch
86Eh
SDLC byte count low register
SDLC byte count high & FIFO status
Receive Buffer
—
—
870h
—
872h
—
SCC1 Read Register 10
Reserved
RO
8
874h
Loop/clock status
—
876–87Eh
—
SCC2 Registers
SCC2 Write Register 0
SCC2 Write Register 1
SCC2 Write Register 2
SCC2 Write Register 3
SCC2 Write Register 4
SCC2 Write Register 5
SCC2 Write Register 6
R/W
R/W
R/W
R/W
R/W
R/W
R/W
8
8
8
8
8
8
8
880h
882h
884h
886h
888h
88Ah
88Ch
Command register
00h
xx
Tx/Rx Interrupt & data transfer mode
Extended Features Control
Receive Parameter and Control
Tx/Rx misc. parameters & mode
Tx. parameter and control
xx
00h
00h
00h
Sync character or SDLC address field or Match
Character 0
00h
SCC2 Write Register 7
SCC2 Write Register 8
SCC2 Write Register 9
SCC2 Write Register 10
SCC2 Write Register 11
SCC2 Write Register 12
SCC2 Write Register 13
SCC2 Write Register 14
SCC2 Write Register 15
SCC2 Write Register 16
SCC2 Write Register 17
SCC2 Read Register 0
SCC2 Read Register 1
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
8
8
8
8
8
8
8
8
8
8
8
8
8
88Eh
890h
892h
894h
896h
898h
89Ah
89Ch
89Eh
8A8h
8AAh
8A0h
8A2h
8A4h
8A6h
Sync character or SDLC flag or Match Character 1
Transmit Data Buffer
xx
xx
Master Interrupt control
xx
Misc. Tx/Rx control register
Clock Mode Control
00h
xx
Lower Byte of Baud rate time constant
Upper Byte of Baud rate time constant
Misc. Control bits
00h
00h
xx
External/Status interrupt control
Match Character 2 (wr16)
f8h
00h
00h
—
Match Character 3 (wr17)
Tx/Rx buffer and external status
Receive condition status/residue code
RO
—
—
SCC2 Read Register 3
see WR16 and 17
RO
8
Interrupt Pending Bits
—
8A8–8AAh see WR16 and WR17 above
—
SCC2 Read Register 6
SCC2 Read Register 7
SCC2 Read Register 8
Reserved
RO
RO
RO
8
8
8
8ACh
8AEh
SDLC byte count low register
SDLC byte count high & FIFO status
Receive Buffer
—
—
8B0h
—
8B2h
—
SCC2 Read Register 10
Reserved
RO
8
8B4h
Loop/clock status
—
8B6–8BEh
—
12
1999 Mar 29
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
Read/Write or
Read Only
Address
Offset
Reset
Value
MMR Name
Size
Description
SCC3 Registers
SCC3 Write Register 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
8
8
8
8
8
8
8
8C0h
8C2h
8C4h
8C6h
8C8h
8CAh
8CCh
Command register
00h
xx
SCC3 Write Register 1
SCC3 Write Register 2
SCC3 Write Register 3
SCC3 Write Register 4
SCC3 Write Register 5
SCC3 Write Register 6
Tx/Rx Interrupt & data transfer mode
Extended Features Control
xx
Receive Parameter and Control
Tx/Rx misc. parameters & mode
Tx. parameter and control
00h
00h
00h
Sync character or SDLC address field or Match
Character 0
00h
SCC3 Write Register 7
SCC3 Write Register 8
SCC3 Write Register 9
SCC3 Write Register 10
SCC3 Write Register 11
SCC3 Write Register 12
SCC3 Write Register 13
SCC3 Write Register 14
SCC3 Write Register 15
SCC3 Write Register 16
SCC3 Write Register 17
SCC3 Read Register 0
SCC3 Read Register 1
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
8
8
8
8
8
8
8
8
8
8
8
8
8
8CEh
8D0h
8D2h
8D4h
8D6h
8D8h
8DAh
8DCh
8DEh
8E8h
8EAh
8E0h
8E2h
8E4h
8E6h
8ECh
8EEh
8F0h
Sync character or SDLC flag or Match Character 1
Transmit Data Buffer
xx
xx
Master Interrupt control
xx
Misc. Tx/Rx control register
Clock Mode Control
00h
xx
Lower Byte of Baud rate time constant
Upper Byte of Baud rate time constant
Misc. Control bits
00h
00h
xx
External/Status interrupt control
Match Character 2 (wr16)
f8h
00h
00h
—
Match Character 3 (wr17)
Tx/Rx buffer and external status
Receive condition status/residue code
RO
—
—
SCC3 Read Register 3
SCC3 Read Register 6
SCC3 Read Register 7
SCC3 Read Register 8
Reserved
RO
RO
RO
RO
8
8
8
8
Interrupt Pending Register
SDLC byte count low register
SDLC byte count high & FIFO status
Receive Buffer
—
—
—
—
8F2h
—
SCC3 Read Register 10
Reserved
RO
8
8F4h
Loop/clock status
—
8F6–8FEh
—
Rx DMA Registers
DMA Control Register Ch.0 Rx
FIFO Control & Status Reg Ch.0 Rx
Segment Register Ch.0 Rx
R/W
R/W
R/W
R/W
8
8
8
8
100h
101h
102h
104h
Control Register
00h
00h
00h
00h
Control & Status Register
Points to 64K data segment
Buffer Base Register Ch.0 Rx
Wrap Reload Value for A15 –A8, A7–A0 reloaded
to zero by hardware
Buffer Bound Register Ch.0 Rx
Address Pointer Reg Ch.0 Rx
Byte Count Register Ch.0 Rx
R/W
R/W
R/W
16
16
16
106h
108h
10Ah
Upper Bound (plus 1) on A15–A0
Current Address pointer A15–A0
0000h
0000h
0000h
Corresponds to A15–A0 Byte Count, generates
interrupt if enabled and byte count exceeded.
Data FIFO Register Ch.0 Lo Rx
Data FIFO Register Ch.0 Hi Rx
R/W
R/W
16
16
10Ch
10Eh
10Ch = Byte 0 = older,
10Dh = Byte 1 = younger
00h
00h
10Eh = Byte 2 = older,
10Fh = Byte 3 = younger
00h
00h
DMA Control Register Ch.1 Rx
FIFO Control & Status Register Ch.1 Rx
Segment Register Ch. 1 Rx
R/W
R/W
R/W
R/W
8
8
8
8
110h
111h
112h
114h
Control Register
00h
00h
00h
00h
Control & Status Register
Points to 64K data segment
Buffer Base Register Ch. 1 Rx
Wrap Reload Value for A15 –A8, A7–A0 reloaded
to zero by hardware
13
1999 Mar 29
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
Read/Write or
Read Only
Address
Offset
Reset
Value
MMR Name
Size
Description
Buffer Bound Register Ch.1 Rx
Address Pointer Reg Ch.1 Rx
Byte Count Register Ch.1 Rx
R/W
R/W
R/W
16
16
16
116h
118h
11Ah
Upper Bound (plus 1) on A15–A0
Current Address pointer A15–A0
0000h
0000h
Corresponds to A15–A0 Byte Count, generates
interrupt if enabled and byte count exceeded.
0000h
Data FIFO Register Ch.1 Lo Rx
Data FIFO Register Ch.1 Hi Rx
R/W
R/W
16
16
11Ch
11Eh
11Ch = Byte 0 = older,
11Dh = Byte 1 = younger
00h
00h
11Eh = Byte 2 = older,
11Fh = Byte 3 = younger
00h
00h
DMA Control Register Ch.2 Rx
FIFO Control & Status Register Ch.2 Rx
Segment Register Ch. 2 Rx
R/W
R/W
R/W
R/W
8
8
8
8
120h
121h
122h
124h
Control Register
00h
00h
00h
00h
Control & Status Register
Points to 64K data segment
Buffer Base Register Ch. 2 Rx
Wrap Reload Value for A15 –A8, A7–A0 reloaded
to zero by hardware
Buffer Bound Register Ch.2 Rx
Address Pointer Reg Ch.2 Rx
Byte Count Register Ch.2 Rx
R/W
R/W
R/W
16
16
16
126h
128h
12Ah
Upper Bound (plus 1) on A15–A0
Current Address pointer A15–A0
0000h
0000h
0000h
Corresponds to A15–A0 Byte Count, generates
interrupt if enabled and byte count exceeded.
Data FIFO Register Ch.2 Lo Rx
Data FIFO Register Ch.2 Hi Rx
R/W
R/W
16
16
12Ch
12Eh
12Ch = Byte 0 = older,
12Dh = Byte 1 = younger
00h
00h
12Eh = Byte 2 = older,
12Fh = Byte 3 = younger
00h
00h
DMA Control Register Ch.3 Rx
FIFO Control & Status Register Ch.3 Rx
Segment Register Ch. 3 Rx
R/W
R/W
R/W
R/W
8
8
8
8
130h
131h
132h
134h
Control Register
00h
00h
00h
00h
Control & Status Register
Points to 64K data segment
Buffer Base Register Ch. 3 Rx
Wrap Reload Value for A15 –A8, A7–A0 reloaded
to zero by hardware
Buffer Bound Register Ch.3 Rx
Address Pointer Reg Ch.3 Rx
Byte Count Register Ch.3 Rx
R/W
R/W
R/W
16
16
16
136h
138h
13Ah
Upper Bound (plus 1) on A15–A0
Current Address pointer A15–A0
0000h
0000h
0000h
Corresponds to A15–A0 Byte Count, generates
interrupt if enabled and byte count exceeded.
Data FIFO Register Ch.3 Lo Rx
Data FIFO Register Ch.3 Hi Rx
R/W
R/W
16
16
13Ch
13Eh
13Ch = Byte 0 = older,
13Dh = Byte 1 = younger
00h
00h
13Eh = Byte 2 = older,
13Fh = Byte 3 = younger
00h
00h
Tx DMA Registers
DMA Control Register Ch.0 Tx
FIFO Control & Status Register Ch.0 Tx
Segment Register Ch. 0 Tx
R/W
R/W
R/W
R/W
8
8
8
8
140h
141h
142h
144h
Control Register
00h
00h
00h
00h
Control & Status Register
Points to 64K data segment
Buffer Base Register Ch. 0 Tx
Wrap Reload Value for A15 –A8, A7–A0 reloaded
to zero by hardware
Buffer Bound Register Ch.0 Tx
Address Pointer Reg Ch.0 Tx
Byte Count Register Ch.0 Tx
R/W
R/W
R/W
16
16
16
146h
148h
14Ah
Upper Bound (plus 1) on A15–A0
Current Address pointer A15–A0
0000h
0000h
0000h
Corresponds to A15–A0 Byte Count, generates
interrupt if enabled and byte count exceeded.
Data FIFO Register Ch.0 Tx
Data FIFO Register Ch.0 Tx
R/W
R/W
16
16
14Ch
14Eh
14C = Byte0 = older
14D = Byte 1 = younger
0000h
0000h
14E = Byte2 = older
14F = Byte3 = younger
DMA Control Register Ch.1 Tx
FIFO Control & Status Register Ch.1 Tx
Segment Register Ch.1 Tx
R/W
R/W
R/W
8
8
8
150h
151h
152h
Control Register
00h
00h
00h
Control & Status Register
Points to 64K data segment
14
1999 Mar 29
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
Read/Write or
Read Only
Address
Offset
Reset
Value
MMR Name
Size
Description
Buffer Base Register Ch.1 Tx
R/W
8
154h
Wrap Reload Value for A15–A8, A7–A0 reloaded
to zero by hardware
00h
Buffer Bound Register Ch.1 Tx
Address Pointer Reg Ch.1 Tx
Byte Count Register Ch.1 Tx
R/W
R/W
R/W
16
16
16
156h
158h
15Ah
Upper Bound (plus 1) on A15–A0
Current Address pointer A15–A0
0000h
0000h
0000h
Corresponds to A15–A0 Byte Count, generates
interrupt if enabled and byte count exceeded.
Data FIFO Register Ch.1 Lo Tx
Data FIFO Register Ch.1 Hi Tx
DMA Control Register Ch.2 Tx
FIFO Control & Status Register Ch.2 Tx
Segment Register Ch.2 Tx
R/W
R/W
R/W
R/W
R/W
R/W
16
16
8
15Ch
15Eh
160h
161h
162h
164h
Byte0 & 1
0000h
0000h
00h
Byte2 & 3
Control Register
Control & Status Register
Points to 64K data segment
8
00h
8
00h
Buffer Base Register Ch.2 Tx
8
Wrap Reload Value for A15 –A8, A7–A0 reloaded
to zero by hardware
00h
Buffer Bound Register Ch.2 Tx
Address Pointer Reg Ch.2 Tx
Byte Count Register Ch.2 Tx
R/W
R/W
R/W
16
16
16
166h
168h
16Ah
Upper Bound (plus 1) on A15–A0
Current Address pointer A15–A0
0000h
0000h
0000h
Corresponds to A15–A0 Byte Count, generates
interrupt if enabled and byte count exceeded.
Data FIFO Register Ch.2 Lo Tx
Data FIFO Register Ch.2 Hi Tx
DMA Control Register Ch.3 Tx
FIFO Control & Status Register Ch.3 Tx
Segment Register Ch. 3 Tx
R/W
R/W
R/W
R/W
R/W
R/W
16
16
8
16Ch
16Eh
170h
171h
172h
174h
Byte0 & 1
0000h
0000h
00h
Byte2 & 3
Control Register
Control & Status Register
Points to 64K data segment
8
00h
8
00h
Buffer Base Register Ch. 3 Tx
8
Wrap Reload Value for A15 –A8
00h
A7–A0 reloaded to zero by hardware
Buffer Bound Register Ch.3 Tx
Address Pointer Reg Ch.3 Tx
Byte Count Register Ch.3 Tx
R/W
R/W
R/W
16
16
16
176h
178h
17Ah
Upper Bound (plus 1) on A15–A0
Current Address pointer A15–A0
0000h
0000h
0000h
Corresponds to A15–A0 Byte Count, generates
interrupt if enabled and byte count exceeded.
Data FIFO Register Ch.3Lo Tx
Data FIFO Register Ch.3 Hi Tx
R/W
R/W
R/W
16
16
17Ch
17Eh
Byte0 & 1
Byte2 & 3
0000h
0000h
—
180–1FEh RESERVED for future DMA
Miscellaneous DMA Registers
Rx Character Time Out Register Ch.0
Rx Character Time Out Register Ch.1
Rx Character Time Out Register Ch.2
Rx Character Time Out Register Ch.3
Global DMA Interrupt Register
R/W
R/W
R/W
R/W
R/W
8
8
200h
202h
204h
206h
210h
0 value disables counter interrupt.
Same as above, for Rx1
Same as above, for Rx2
Same as above, for Rx3
DMA Interrupt Flags
00h
00h
8
00h
8
00h
16
0000h
V.54/2047 Registers
VACS
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
8
8
8
8
8
8
8
8
8
8
240h
241h
242h
243h
244h
248h
249h
24Ah
24Bh
24Ch
V.54 2047 Unit A Control & Status
V.54 2047 Unit A Configuration
V.54 2047 Unit A Threshold Cntr Lo
V.54 2047 Unit A Threshold Cntr Hi
V.54 2047 Unit A Error Counter
V.54 2047 Unit B Control & Status
V.54 2047 Unit B Configuration
V.54 2047 Unit B Threshold Cntr Lo
V.54 2047 Unit B Threshold Cntr Hi
V.54 2047 Unit B Error Counter
00h
—
VACFG
VATCL
VATCH
VAEC
—
—
—
VBCS
00h
—
VBCFG
VBTCL
VBTCH
VBEC
—
—
—
15
1999 Mar 29
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
Read/Write or
Read Only
Address
Offset
Reset
Value
MMR Name
Size
Description
SCP Interface Registers
SCPCFG
SCPD
R/W
R/W
R/W
8
8
8
260h
262h
263h
SCP Configuration
SCP Data Byte
8xh
xx
SCPCS
SCP Control & Status
00h
Autobaud Registers
BDAEE
BDCS
R/W
R/W
8
8
270h
272h
Autobaud Echo Enable
00h ..
00h ..
Autobaud Control & Status
Memory Interface (MIF) Registers
B0CFG
B0AM
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
280h
281h
282h
284h
285h
286h
288h
289h
28Ah
28Ch
28Dh
28Eh
290h
291h
292h
294h
295h
296h
2BEh
2BFh
MIF Bank 0 Config
—
00h..
—
MIF Bank 0 Base Address
MIF Bank 0 Timing Params
MIF Bank 1 Config
B0TMG
B1CFG
B1AM
0xh
xxh
xxh
0xh
xx
MIF Bank 1 Base Address
MIF Bank 1 Timing Params
MIF Bank 2 Config
B1TMG
B2CFG
B2AM
MIF Bank 2 Base Address
MIF Bank 2 Timing Params
MIF Bank 3 Config
B2TMG
B3CFG
B3AM
xx
0xh
xx
MIF Bank 3 Base Address
MIF Bank 3 Timing Params
MIF Bank 4 Config
B3TMG
B4CFG
B4AM
xx
0xh
xx
MIF Bank 4 Base Address
MIF Bank 4 Timing Params
MIF Bank 5 Config
B4TMG
B5CFG
B5AM
xx
0xh
xx
MIF Bank 5 Base Address
MIF Bank 5 Timing Params
B5TMG
MBCL
xx
MIF Memory Bank Configuration Lock Register
MIF Refresh Control
3Fh
00h
RFSH
IDL Interface Registers
MSI Control Register
DataMask Register
R/W
R/W
16
16
2C0h
2C2h
IDL Mode Control Register
IDL Mask Register
0000h
0000h
Miscellaneous Registers
Hi-Pri Soft Ints & Pin Mux Control Reg.
XInt2
R/W
R/W
16
8
2D0h
2D2h
Control bits for Hi-Priority Soft Ints, and Pin Mux
External Interrupt 2 Control
0000h
00h
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1999 Mar 29
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
FUNCTIONAL DESCRIPTION
ResetOut
The XA-SCC functions are described in the following sections.
Because all blocks are thoroughly documented in either the IC25 XA
Data Handbook, or the XA-SCC User Manual, only brief descriptions
are given in this datasheet, in conjunction with references to the
appropriate document.
The P3.2_Timer0_ResetOut pin provides an external indication (if
the ResetOut function is enabled in the RSRSRC register) via an
active low output when an internal reset occurs (internal reset is
Reset instruction or Watchdog time out.) If the ResetOut function is
enabled, the ResetOut pin will be driven low when a Watchdog reset
occurs or the Reset instruction is executed. This signal may be used
to inform other devices in the system that the XA-SCC has been
internally reset. The ResetIn signal does NOT get passed on to
ResetOut. When activated, the duration of the ResetOut pulse is
256 system clocks.
XA CPU
The CPU is a 30MHz implementation of the standard XA CPU core.
See the XA Data Handbook (IC25) for details. The CPU core is
identical to the G3 core. See caveat in next paragraph about the Bus
Interface Unit.
WARNING: At power on time, from the time that power coming up is
valid, the P3.2_Timer0_ResetOut pin may be driven low for any
period from zero nanoseconds up to 258 system clocks. This is true
independently of whether ResetIn is active or not.
Bus Interface Unit (BIU)
This is the internal Bus, not the bus at the pins. This internal bus
connects the CPU to the MIF (Memory and DRAM Controller.)
WARNING: Immediately after reset, always write BTRH = 51h,
followed by BTRL = 40h, in that order. Once written, do not change
the values in these registers. Follow these two writes with five
NOPS. Never write to the BCR register, it comes out of reset
initialized to 07h, which is the only value that will work.
Reset Source Register
The reset source identification register (RSTSRC) indicates the
cause of the most recent XA reset. The cause may have been an
externally applied reset signal, execution of the RESET instruction,
or a Watchdog reset. Figure 2 shows the fields in the RSTSRC
register. If the ResetOut function is tied back into the ResetIn pin,
then all resets will be external resets, and will thus appear as
external resets in the reset source register. RSTSRC[7] enables the
ResetOut function; 1 = Enabled, 0 = Disabled. See XA-SCC User
Manual for details; RSTSRC[7] differs in function from most other
XA derivatives.
Timers 0 and 1
Timers 0 and 1 are the standard XA-G3 timer 0 and 1. Each has an
associated I/O pin and interrupt. See the XA-G3 data sheet in the
IC25 XA Data Handbook for details. Many XA derivatives include a
standard XA Timer 2, and standard UARTs. These blocks have been
removed in order to provide other functions on the XA-SCC. There
is no Timer 2, and the UARTs have been replaced with full function
SCCs.
Watchdog Timer
This timer is a standard XA-G3 Watchdog Timer. See the G3
datasheet in IC25. Also, if you intend to use the Watchdog Timer to
assert the ResetOut pin, see ResetOut in the XA-SCC User Manual.
The Watchdog Timer is enabled at reset, and must be periodically
fed to prevent timeout. If the watchdog times out, it will generate an
internal reset; and if ResetOut is enabled the internal reset will
generate a ResetOut pulse (active low pulse on ResetOut pin.)
XA CPU
BIU
INTERNAL CPU BUS
Reset
MIF and
DRAM
CONTROLLER
EXTERNAL
MEMORY
and I/O BUS
DMA
CHANNELS
x8
On the XA-SCC there are two pins associated with reset. The
ResetIn pin provides an external reset into the XA-SCC. The port
pin P3.2_Timer0_ResetOut output can be configured as ResetOut.
Because ResetOut does not reflect ResetIn, the ResetOut pin can
be tied directly back into the ResetIn pin without other PC board
logic. This configuration will make all resets (internal or external)
appear to the XA as external resets. See the XA-SCC User Manual
for a full discussion of the reset functions.
SU01123
Figure 2. XA CPU Core BIU (Bus Interface Unit)
ResetIn
The ResetIn function is the standard XA-G3 ResetIn function. The
ResetIn signal does NOT get passed on to ResetOut. See the
XA-SCC User Manual for details on reset.
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1999 Mar 29
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
RSTRC
Reg Type and Address = SFR 463h
Not Bit Addressable
Reset Value = see below
MSB
LSB
ROEN
—
6
—
5
—
4
—
3
R_WD
R_CMD
R_EXT
Bit:
7
2
1
0
Bit
Symbol
Function
RSTSRC.7 ROEN
ResetOut function enable bit – see XA–SCC User Manual for details
Reserved for future use. Should not be set to 1 by user programs.
Reserved for future use. Should not be set to 1 by user programs.
Reserved for future use. Should not be set to 1 by user programs.
Reserved for future use. Should not be set to 1 by user programs.
RSTSRC.6
RSTSRC.5
RSTSRC.4
RSTSRC.3
–
–
–
–
RSTSRC.2 R_WD
Indicates that the last reset was caused by a watchdog timer overflow (see WARNING.)
Indicates that the last reset was caused by execution of the RESET instruction (see WARNING.)
Indicates that the last reset was caused by the external ResetIn input.
RSTSRC.1 R_CMD
RSTSRC.0 R_EXT
WARNING:
If ResetOut function is tied back into ResetIn pin, RSTSRC will always show external reset ONLY, because external reset always takes precedence over internal reset.
SU01124
Figure 3. RSTSRC Reset Source Register
memory bank or peripheral can be programmed to accommodate
slow or fast devices.
DRAM Controller and Memory/IO Bus Interface
(MIF)
In the memory or system bus interface terminology, generic bus
cycles are synonymous with SRAM bus cycles, because these
cycles are designed to service SRAMs, Flash, EEPROM, peripheral
chips, etc. Chip select output pins function as either CS or RAS
depending on whether the memory bank has been programmed as
generic or DRAM.
Each memory bank and it’s associated RAS (chip select pin in
DRAM mode) output, can be programmed to access up to an
8MByte mappable address space in either EDO or FPM DRAM
modes (up to a total of 16MB of DRAM, or 32MB if 16MB of data
space and 16MB code space is elected. WARNING: Future
XA-SCC derivatives may not support separate code and data
spaces.)
The XA-SCC has a highly programmable memory bus interface with
a complete onboard DRAM controller. Most DRAMs (up to 8MBytes
per RAS pin), SRAMs, Flash, ROMs, and peripheral chips can be
connected to this interface with zero glue chips. The bus interface
provides 6 mappable chip select outputs, five of which can be
programmed to function as RAS strobes to DRAM. CAS generation,
proper address multiplexing for a wide range of DRAM sizes, and
refresh are all generated onboard. The bus timing for each individual
Each memory bank and associated chip select programmed for
“generic” (SRAM, Flash, ROM, peripheral chips, etc) is capable of
supporting a 1Mbyte address space (six chip selects can thus
support 6MB of SRAM and other generic devices.)
The Memory Interface can be programmed to support both Intel
style and 68000 bus style SRAMs and peripherals.
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1999 Mar 29
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
Bus Interface Pins
For this discussion, see Figure 4.
XA–SCC
CS5, RAS5, (or P3.1, RTS1)
CS4, RAS4, (or P3.0, RTClk1)
CS3, RAS3
CS2, RAS2
CS1, RAS1
CS0
A19–A0 (IF DRAM CYCLE, A22–A0 ARE TIME-MULTIPLEXED FOR RAS/CAS)
D15–D0
MIF
(MEMORY CONTROLLER)
ClkOut
CASH, BHE
CASL, BLE
OE
WE
WAIT, SIZE16
SU01125
Figure 4. Memory Bus Interface Signal Pins
detailed bus strobe sequence, DRAM cycle or generic bus cycle,
DRAM size if DRAM, and bus width. Pin CS0 is always generic in
order to service the boot device, thus CS0 cannot be connected to
DRAM.
Chip Selects and RAS pins
There are six chip select pins (CS5–CS0) mapped to six sets of
bank control registers. The following attributes are individually
programmable for each bank and associated chip select (or RAS if
DRAM): bank on/off, address range, external device access time,
WARNING: On the external bus, ALL XA-SCC reads are 16 bit Reads. If the CPU instruction only specifies 8 bits, then the CPU uses
the appropriate byte, and discards the extra byte. Thus “8 Bit Reads” appear to be identical on the bus. On an 8 bit bus, this will
appear as two consecutive 8 bit reads even though the CPU instruction specified a byte read
Some 8 bit I/O devices (especially FIFOs) cannot operate correctly with 2 bytes being Read for a 1 Byte Read. The most common (and
least expensive) solution is to operate these 8 bit devices on a 16 bit bus, and access them in software on all odd byte (or all even byte)
boundaries. An added benefit of this technique is that byte reads are faster than on an 8 bit bus, because only 1 word is fetched (a single
read) instead of 2 consecutive bytes.
CLKOUT to be output enabled at reset, but it may be turned off
Clock Output
(tri-state disabled) by software via the MICFG MMR.
WARNING: The capacitive loading on this output must not
exceed 40pf.
The CLKOUT pin allows easier external bus interfacing in some
situations. This output reflects the XTALIn clock input to the XA
(referred to internally as CClk or System Clock), but is delayed to
match the external bus outputs and strobes. The default is for
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1999 Mar 29
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
CS0
CS
OE
128K x 8 ROM
A16–A0
D7–D0
XA–SCC
CS1
RAS
CASL
CASH
256K x 16 DRAM
(HM514260DI)
OE
WE
A17–A9
D15–D0
A8–A0
D15–D0
CS2
RAS
CASL
CASH
1M x 16 DRAM
(MT4C1M16C3)
OE
OE
WE
A17–A8
A9–A0
A19–A0
D15–D0
D15–D0
CS3
RAS
BLE
BHE
CASL
CASH
32K x 16 SRAM
WE
WE
A15–A1
D15–D0
NOTE:
During DRAM cycles only, the appropriate CAS Address will be multiplexed onto pins A17–A7 after the assertion or RAS and prior to the assertion of BHE (CASH) and
BLE (CASL). See AC timing diagrams and the XA–SCC User Manual for complete details.
SU01126
Figure 5. Typical System Bus Configuration
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1999 Mar 29
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
Table 3. Memory Interface Control Registers
Reg
Type
Register Name
Description
MRBH
“MMR Base Address”
High
SFR
8 bits
This SFR is used to relocate the MMRs. It contains address bits a23–a16 of the
base address for the 4 KByte Memory Mapped Register space. See XA-SCC User
Manual for using this SFR to relocate the MMRs.
MRBL
MICFG
MBCL
BiCFG
“MMR Base Address” Low
MIF Configuration
SFR
Contains address bits a15–a12 of the base address for the 4 KByte Memory
Mapped Register space.
8 bits
MMR
8 bits
Contains the CLKOUT Enable bit.
Memory Bank
Configuration Lock
MMR
8 bits
Contains the bits for locking and unlocking the BiCFG Registers.
Contains the size, type, bus width, and enable bits for Memory Bank i.
Bank i Configuration
MMR
8 bits
Bank i Base
Address/DRAM Address
Multiplexer Control
MMR
8 bits
Contains the base address bits and DRAM address multiplex control bits for
Memory Bank i.
BiAM
Bank i Timing
MMR
8 bits
Contains the timing control bits for Memory Bank i.
BiTMG
RFSH
Refresh Timing
MMR
8 bits
Contains the refresh time constant and DRAM Refresh Timer enable bit.
Eight Channel DMA Controller
The XA-SCC has eight DMA channels; one Rx DMA channel
Transmit DMA Channel Modes
The four Tx channels have four DMA modes specifically designed
dedicated to each SCC Receive (Rx) channel, and one Tx DMA
channel dedicated to each SCC Transmit (Tx) channel. All DMA
channels are optimized to support memory efficient circular data
buffers in external memory. All DMA channels can also support
traditional linear data buffers.
for various applications of the attached SCCs. These modes are
summarized in the following table. Full details for all DMA functions
can be found in the DMA chapter of the XA-SCC User Manual.
Table 4. Tx DMA Modes Summary
Mode
Byte Count Source
Header in memory
Maskable Interrupt
Description
Non-SDLC/HDLC
Tx Chaining
On stop
DMA channel picks up header from memory at
end of transmission. If byte count in header is
greater than zero, then DMA transmits the
number of bytes specified in the byte count. If
byte count equals 0, then a maskable interrupt is
generated. This process repeats until byte count
in data header is zero. See XA-SCC User
manual for details.
SDLC/HDLC
Tx Chaining
Header in memory
End of packet (not
end of fragment)
Same as above, except DMA header
distinguishes between fragment of packet and
full pack. See XA-SCC User manual for details.
Stop on TC
Processor loads Byte Count
Register (for each fragment)
Byte count completed
(Tx DMA stops)
Processor loads byte count into DMA. DMA
sends that number of bytes, generates maskable
interrupt, and stops.
Periodic Interrupt
Processor loads Byte Count
Register (only once)
Each time byte count
completed (Tx DMA
continues)
DMA runs until commanded to stop by
processor. Everytime byte counter rolls over, a
new maskable interrupt is generated.
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1999 Mar 29
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
Receive DMA Channel Modes
The Rx DMA channels have four DMA modes specifically designed
for various applications of the attached SCCs. These modes are
summarized in the following table. For full details on implementation
and use, see the XA-SCC User Manual.
Table 5. Rx DMA Modes Summary
Mode
Byte Count Source
Maskable Interrupt
Description
SDLC/HDLC Rx
Chaining
DMA stores byte count in header in
memory with data packet.
At end of received
packet
When a complete or aborted SDLC/HDLC
packet has been received, the packet byte count
and status information are stored in memory with
the packet. A maskable interrupt is generated.
Periodic Interrupt
Loaded by processor into DMA,
used only to determine the number
of bytes between interrupts.
Processor can infer the byte count
from the DMA address pointer.
When Byte Counter
reaches zero and is
reloaded by DMA
hardware from the byte
count register.
The DMA channel runs until commanded to stop
by the processor. It generates a maskable
interrupt once per n bytes, where n is the
number written once into the byte count register
by the processor, thus an interrupt is generated
once every n received bytes.
Asynchronous
Character Time Out
Byte Count can be calculated by
software from the DMA address
pointer.
If no character is
received within a
specified time out
period, then interrupt.
Processor specifies time out period between
incoming characters. If no character is received
within that time, interrupt is generated.
Asynchronous
Character Match
Byte Count can be calculated by
software from the DMA address
pointer.
When matched
character is stored in
memory.
There are four match registers, each incoming
character is compared to all four registers. When
a matched character is stored in memory by
DMA, a maskable interrupt is generated.
DATA FIFO 3
DATA FIFO 1
DATA FIFO 2
DATA FIFO 0
DMA CONTROL
SEGMENT
BUFFER BASE
Rx CHANNEL
BUFFER BOUND
ADDRESS POINTER
BYTE COUNT
FIFO CONTROL
Rx TIME OUT
DATA FIFO 3
DATA FIFO 1
DATA FIFO 2
DATA FIFO 0
DMA CONTROL
SEGMENT
Tx CHANNEL
BUFFER BASE
BUFFER BOUND
ADDRESS POINTER
BYTE COUNT
FIFO CONTROL
SU01127
Figure 6. Rx and Tx DMA Registers
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1999 Mar 29
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
– Automatic CRC generation and checking (can be disabled for
“pass-thru.”)
DMA Registers
In addition to the 16-bit Global DMA Interrupt Register (which is
shared by all eight DMA channels), each DMA channel has seven
control registers and a four-byte Data FIFO. The four Rx DMA
channels have one additional register, the Rx Character Time Out
Register. All DMA registers can be read and written in Memory
Mapped Register (MMR) space. These registers are summarized
below.
– Automatic zero-bit insertion and stripping.
– Automatic partial byte residue code generation.
– 14-bit Packet byte count stored in memory with received packet
by DMA.
• Synchronous character oriented protocol features:
– Automatic CRC generation and checking.
– One (Monosync) or two (Bisync) sync characters option.
– External Sync option.
• Global DMA Interrupt Register (not shown in figure): All DMA
interrupt flags are in this register .
• DMA Control Register: Contains the master mode select and
interrupt enable bits for the channel.
• Transparent mode for bit-streaming applications.
• Segment Register: Holds A23–A16 (the current segment) of the
• Data encoding/decoding options:
– FM0 (Biphase Space)
– FM1 (Biphase Mark)
– NRZ
24-bit data buffer address.
• Buffer Base Register: Holds a pointer (A15–A8) to the lowest byte
in the memory buffer.
– NRZI
• Buffer Bound Register: Points to the first out-of-bounds address
above a circular buffer.
• Programmable Baud Rate Generator, and 7/8 Clock Prescaler
option.
• Address Pointer Register: Points to a single byte or word in the
data buffer in memory. The 24-bit DMA address is formed by
concatenating the contents of the Segment Register [A23–A16]
with the contents of the Address Pointer Register [A15–A0].
• Auto Echo and Local Loopback modes.
• Supports hardware V.54/2047 generation and checking.
• Byte Count Register: Holds the initial number of bytes to be
transferred. In Tx Chaining mode, this register is not used
because the byte count is brought into the byte counter from
buffer headers in memory.
• IDL (2B + D) supported on three SCC channels. Supports both “8
bit” and “10 bit” IDL.
IDL Time Division Multiplexor
SCC0, SCC1, and SCC2 can be internally connected to the on-chip
IDL Interface, a glueless industry standard interface to Layer One
devices such as U-Chips or S/T chips. Thus connected, the three
SCCs can efficiently support the ISDN B1, B2, and D channels,
while the IDL Interface time-multiplexes and demultiplexes the
outgoing and incoming serial data streams.
• FIFO Control & Status Register: Holds the queuing order and
full/empty status for the Data FIFO Registers.
• Data FIFO Registers: A four-byte data FIFO buffer internal to the
DMA channel.
• Rx Char Time Out Register (RxCTOR, Rx DMA channels only):
Holds the initial value for an 8-bit character timeout countdown
timer which can generate an interrupt.
If software enables the IDL interface, then SCC0 is connected to
IDL. Optionally, the software can also connect SCC1 and SCC2 to
the IDL interface. SCC3 cannot be connected to the IDL interface.
See the IDL chapter in the XA-SCC User Manual.
Quad Serial Communications Controllers with
Autobaud
• Asynchronous features:
In Figure 7, SCC0 is connected to IDL because IDL has been
enabled by software. Software, in this example has also connected
SCC1 to IDL, and has bypassed IDL for SCC2. SCC3 cannot be
connected to IDL. If there are pins not being used by any of the
SCCs, software can assign alternate functions to those pins; see the
pin steering logic in the “Pins” appendix of the XA-SCC User
Manual. For complete documentation on the IDL interface, see the
IDL chapter in the XA-SCC User Manual.
– Asynchronous transfers up to 921.6Kbps
– Can monitor input stream for up to four match characters per
receiver
– 5, 6, 7, or 8 data bits per character.
– 1, 1.5, or 2 Stop bits per character.
– Even or Odd parity generate and check.
– Parity, Rx Overrun, and Framing Error detection.
– Break detection.
SCP Serial Interface Controller
The SCP Interface provides a full duplex, industry standard
synchronous serial communication bus, similar to SPI and
Microwire. SCP can be used to transfer control and status
information to other chips, and for accessing serial flash devices.
See the IDL interface chapter in the XA-SCC User Manual.
– Supports hardware Autobaud detection and response up to
921.6Kbps.
• SDLC/HDLC features:
– Automatic Flag and Abort Character generation and
recognition.
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Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
PIN
FUNCTION
MUX
IDL
IDL On
IDL On
IF IDL ON
IDL PINS,
ELSE
SCC 0
SCC0 PINS
SCC 1
SCC 2
SCC1 PINS
OR GPIO
SCC2 PINS
OR GPIO
SCC 3
SCC3 PINS
OR GPIO
The Pin Function Mux is used to enable
alternate functions on unused pins.
SU01128
Figure 7. IDL Connection Options
The power down mode stops the oscillator in order to absolutely
minimize power. The processor can be made to exit power down
mode via a reset or one of the external interrupt inputs (INT0 or
INT1). This will occur if the interrupt is enabled and its priority is
higher than that defined by IM3 through IM0. In power down mode,
the power supply voltage may be reduced to the RAM keep-alive
Dual v.54 and 2047 Generators/Checkers
One of the two hardware generator/checkers which support the
V.54/2047 line testing standards can be attached to each SCC.
During V.54/2047 line testing sequences, the V.54/2047 units can be
programmed to generate an interrupt when certain error criteria
have been detected on the transmissions lines. The CPU can
determine the quality of the transmission line by reading the
V.54/2047 units’ status registers.
voltage V
. This retains the RAM, register, and SFR contents at
RAM
the point where power down mode was entered. WARNING: V
DD
must be raised to within the operating range before power down
mode is exited.
Autobaud Detectors
Each SCC has it’s own Autobaud detector, capable of baud rate
detection up to 921.6Kbaud. The detectors can be programmed to
automatically echo the industry standard autobaud sequences. They
can be programmed to update the necessary control registers in the
SCCs, and turn on the receiver; which in turn will automatically
initiate DMA into memory of received data. Thus, once the baud rate
is determined, reception begins without intervention from the
processor. When the baud rate is detected, a maskable interrupt is
sent to the processor. See the Autobaud chapter in the XA-SCC
User Manual for details.
INTERRUPTS
In the XA architecture, all exceptions, including Reset, are handled
in the same general exception structure. The highest priority
exception is of course Reset, and it is non-maskable. All exceptions
are vectored through the Exception Vector Table in low memory.
Coming out of Reset, these vectors must be stored in non-volatile
memory based at location 000000. Later in the boot sequence,
DRAM or SRAM can be mapped into this address space if desired.
There is a feature in the XA-SCC Memory Controller called “Bank
Swap” that supports replacing the ROM vector table and other low
memory with RAM. See the XA-SCC User Manual for details.
I/O PORT OUTPUT CONFIGURATION
Port input/output configurations are the same as standard XA ports:
open drain, quasi-bidirectional, push-pull, and off (off means tri-state
Hi-Z, and allows the pin to be used as an input. WARNING: At
power on time, from the time that power coming up is valid, the
P3.2_Timer0_ResetOut pin may be driven low for any period from
zero nanoseconds up to 258 system clocks. This is true
independently of whether ResetIn is active or not.
The XA-SCC has a standard XA CPU Interrupt Controller,
implemented with 15 Maskable Event Interrupts. Event Interrupts
are defined as maskable interrupts usually generated by hardware
events. However, in the XA-SCC, 4 of the 15 Event Interrupts are
generated by software writing directly to the interrupt flag bit. These
4 interrupts are referred to as High Priority Software Interrupts.
See the IC25 XA Data Handbook for a full explanation of the
exception structure, including event interrupts, of the XA CPU.
Because the High Priority Software Interrupts are specific to the
XA-SCC, they are explained in the XA-SCC User Manual.
POWER REDUCTION MODES
The XA-SCC supports Idle and Power Down modes of power
reduction. The idle mode leaves most peripherals running in order to
allow them to activate the processor when an interrupt is generated.
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1999 Mar 29
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
XA CORE
INTERRUPT CONTROLLER
DMAH
DMAL
DMA
INTERRUPTS
INTERRUPT
ENABLE/
DISABLE BITS
CTS0
CD0
CTS1
SCC0/
SCC1
CD1_INT2
INT2
CTS2
CD2
INTERRUPT
TO XA CPU
MASTER
ENABLE
“EA”
SCC2/
SCC3
CTS3
CD3
INT0
INT1
AUTOBAUD 3–0
v.54_2047 1–0
OR
SCP INTERFACE
TIMER 0
TIMER 1
4
HIGH PRIORITY
SOFTWARE INTS
HSWR 3–0
SU01129
Figure 8. XA-SCC Interrupt Structure Overview
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1999 Mar 29
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
Table 6. SCC0 Interrupts (Interrupt structure is the same except for bit locations for all 4 SCCs)
Source Bit
MMR Hex
Offset
Individual Enable Bit
MMR Hex Offset
Group Enable Bit(s)
MMR Hex Offset
Group Flag Bit MMR Master Enable Bit
Hex Offset
MMR Hex Offset
Potential SCC0 Interrupt
Rx Character Available
–
RR0[0]
SCC0/1 Master
Interrupt Enable
WR9[3]
Even Channel Rx IP
RR3[5]
WR1[4:3]
SDLC EOF
–
RR1[7]
RR1[6]
RR1[5]
RR1[4]
RR0[2]
CRC/Framing Error
Rx Overrun
–
–
Parity Error
WR1[2]
See WR1[1]
Tx Buffer Empty
Tx Interrupt Enable
WR1[1]
Even Channel Tx IP
RR3[4]
Break/Abort
Tx Underrun/EOM
CTS
Break/Abort IE
WR15[7]
RR0[7]
Tx Underrun/EOM IE RR0[6]
WR15[6]
CTS IE
WR15[5]
RR0[5]
RR0[4]
RR0[3]
RR0[1]
Master External/ Status
Interrupt Enable
WR1[0]
Even Channel
External/Status IP
RR3[3]
SYNC/HUNT
DCD
SYNC/HUNT IE
WR15[4]
DCD IE
WR15[3]
Zero Count
Zero Count IE
WR15[1]
EXCEPTION/TRAPS PRECEDENCE
DESCRIPTION
VECTOR ADDRESS
ARBITRATION RANKING
Reset (h/w, watchdog, s/w)
Breakpoint
0000–0003
0004–0007
0008–000B
000C–000F
0010–0013
0014–0017
0040–007F
0 (High)
1
1
1
1
1
1
Trace
Stack Overflow
Divide by 0
User RETI
TRAP 0–15 (software)
26
1999 Mar 29
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
EVENT INTERRUPTS
Description
Event Interrupt Source
Interrupt Vector
Address
Enable Bit
(SFR)
Priority Register Bit
Field (SFR)
Flag Bit
Arb. Rank
High Priority Software
Interrupt 3
HSWR3
00BF–00BC
00BB–00B8
00B7–00B4
00B3–00B0
00AF–00AC
EHSWR3
PHSWR3
PHSWR2
PHSWR1
PHSWR0
PSCP
17
MMR
High Priority Software
Interrupt 2
HSWR2
MMR
EHSWR2
EHSWR1
EHSWR0
ESCP
16
15
14
13
High Priority Software
Interrupt 1
HSWR1
MMR
High Priority Software
Interrupt 0
HSWR0
MMR
SCP Port
SPFG
SCPCS[3]
MMR
Autobaud and V.54/2047 multiple OR from
Autobauds 3–0 &
00AB–00A8
EAuto
PAutoB
12
V.54/2047 A and B
SCC “SCC2/3” Interrupt multiple OR from
SCC2 & SCC3
00A7–00A4
00A3–00A0
ESC23
ESC01
PSC23
PSC01
11
10
SCC “SCC0/1” Interrupt multiple OR from
SCC0 & SCC1
DMA “DMAH” Interrupt
DMA “DMAL” Interrupt
multiple OR from DMA
multiple OR from DMA
009B– 0098
0097–0094
0093–0090
EDMAH
EDMAL
EX2
PDMAH
PDMAL
PX2
8
7
6
External Interrupt 2
(INT2)
IE2
MMR
Timer 1
TF1
008F–008C
008B–0088
0087–0084
0083–0080
ET1
EX1
ET0
EX0
PT1
PX1
PT0
PX0
5
4
3
2
SFR
External Interrupt 1
(INT1)
IE1
SFR
Timer 0
TF0
SFR
External Interrupt 0
(INT0)
IE0
SFR
SOFTWARE INTERRUPTS
DESCRIPTION
FLAG BIT
VECTOR ADDRESS
ENABLE BIT
INTERRUPT PRIORITY
Software Interrupt 1
SWR1
SWR2
SWR3
SWR4
SWR5
SWR6
SWR7
0100–0103
SWE1
(fixed at 1)
(fixed at 2)
(fixed at 3)
(fixed at 4)
(fixed at 5)
(fixed at 6)
(fixed at 7)
Software Interrupt 2
Software Interrupt 3
Software Interrupt 4
Software Interrupt 5
Software Interrupt 6
Software Interrupt 7
0104–0107
0108–010B
010C–010F
0110–0113
0114–0117
0118–011B
SWE2
SWE3
SWE4
SWE5
SWE6
SWE7
27
1999 Mar 29
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
UNIT
°C
Operating temperature under bias
Storage temperature range
–55 to +125
–65 to +150
°C
Voltage on any other pin to V
Maximum IOL per I/O pin
–0.5 to V +0.5V
v
SS
DD
15
mA
W
Power dissipation (based on package heat transfer, not device power consumption)
1.5
PRELIMINARY DC ELECTRICAL CHARACTERISTICS
V
DD
= 5.0V "10% or 3.3V "10% unless otherwise specified;
Tamb = –40°C to +85°C for industrial, unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
5.0V, 30 MHz
3.3V, 30 MHz
75
63
120
80
mA
mA
I
Power supply current, operating
DD
5.0V, 30 MHz
3.3V, 30 MHz
5.0V, 3.0V
62
50
100
65
mA
mA
µA
V
I
Power supply current, Idle mode
ID
1
I
Power supply current, Power Down mode
RAM keep-alive voltage
500
PDI
V
1.5
–0.5
2.2
RAM
V
Input low voltage
0.22V
V
IL
DD
V
Input high voltage, except Xtal1, RST
Input high voltage to Xtal1, RST
V
IH
V
IH1
For both 3.0 & 5.0V
0.7 V
V
DD
8
V
OL
Output low voltage all ports
I
OL
I
OL
= 3.2mA, V = 4.5V
0.5
0.4
V
DD
= 1.0mA, V = 3.0V
V
DD
V
V
Output high voltage, all ports
Output high voltage, all ports
Input/Output pin capacitance
I
= –100µA, V = 4.5V
2.4
2.0
2.4
2.2
V
OH1
OH2
OH
DD
I
I
I
= –30µA, V = 3.0V
V
OH
OH
OH
DD
= 3.2mA, V = 4.5V
V
DD
= 1.0mA, V = 3.0V
V
DD
C
15
pF
µA
µA
µA
µA
IO
7
I
I
Logical 0 input current, all ports
V
IN
= 0.45V
–50
±10
IL
6
Input leakage current, all ports
V
IN
= V or V
IL IH
LI
5
I
Logical 1 to 0 transition current, all ports
At V = 5.5V
–650
–250
TL
DD
At V = 3.6V
DD
NOTES:
1. V must be raised to within the operating range before power down mode is exited.
DD
2. Ports in quasi-bidirectional mode with weak pullup .
3. Ports in PUSH-PULL mode, both pullup and pulldown assumed to be the same strength.
4. In all output modes.
5. Port pins source a transition current when used in quasi-bidirectional mode and externally driven from 1 to 0. This current is highest when
is approximately 2V.
V
IN
6. Measured with port in high impedance mode.
7. Measured with port in quasi-bidirectional mode.
8. Under steady state (non-transient) conditions, I must be externally limited as follows:
OL
Maximum I per port pin:
15mA (*NOTE: This is 85°C specification for V = 5V.)
OL
DD
Maximum I per 8-bit port:
26mA
71mA
OL
Maximum total I for all outputs:
OL
If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
OL
OL
test conditions.
28
1999 Mar 29
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
1
PRELIMINARY AC ELECTRICAL CHARACTERISTICS (5.0V "10%)
V
DD
= 5.0V "10%, T
= –40_C to +85_C (industrial)
amb
LIMITS
SYMBOL
All Cycles
FIGURE
PARAMETER
MIN
MAX
UNIT
F
System Clock Frequency
0
30
–
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
t
C
25
25
25
25
25
All
All
All
All
All
26
System Clock Period = 1/F
XTALIN High Time
XTALIN Low Time
33.33
C
t
t * 0.5
–
CHCX
C
t
t * 0.4
–
CLCX
CLCH
CHCL
C
t
t
XTALIN Rise Time
XTALIN Fall Time
–
–
5
5
t
Address Valid to Strobe low
t
– 21
1
–
AVSL
C
9
t
Address hold after CLKOUT rising edge
–
CHAH
t
Delay from CLKOUT rising edge to address valid
–
25
21
19
CHAV
9
t
Delay from CLKOUT rising edge to Strobe High
1
CHSH
9
t
Delay from CLKOUT rising edge to Strobe Low
1
CHSL
t
ClkOut Duty Cycle High (into 40pF max.)
t
–7
t
+3
CODH
CHCX
CHCX
(See Warning Note 5 on page 31.)
t
13, 14, 16, CAS Pulse Width High
20, 21, 22
t
– 12
–
ns
ns
CPWH
C
t
13, 21
CAS Pulse Width Low
t
C
– 10
–
–
CPWL
All DRAM cycles
8
t
24
RAS precharge time, thus minimum RAS high time
(n * t ) –16
note 8
ns
ns
ns
RP
C
Generic Data Read Only
9, 16
t
Address hold (A19–A1 only, not A0) after CS, BLE, BHE rise at end
of Generic Data Read Cycle (not code fetch)
t
–12
–
–
AHDR
C
Data Read and Instruction Fetch Cycles
t
9, 10,
Data In Valid setup to ClkOut rising edge
25
DIS
12–14, 16,
17, 20, 21
2
t
Data In Valid hold after ClkOut rising edge
0
–
–
ns
ns
DIH
t
10, 12, 13, OE high to XA Data Bus Driver Enable
16, 20, 21
t
C
– 14
OHDE
Write Cycles
t
Clock High to Data Valid
–
25
–
ns
ns
ns
ns
CHDV
t
Data Valid prior to Strobe Low
t
– 23
DVSL
SHAH
SHDH
C
t
11, 16
21
Minimum Address Hold Time after strobe goes inactive
Data hold after strobes (CS and BHE/BLE) high
–
tC – 25
t
t
– 25
–
C
C
Refresh
t
CAS low to RAS low
t
– 15
–
ns
CLRL
Wait Input
t
24
24
WAIT setup (stable high or low) to CLKOUT rising edge
WAIT hold (stable high or low) after CLKOUT rising edge
20
0
–
–
ns
ns
WS
t
WH
NOTE:
1. See notes after the 3.3V AC timing table.
29
1999 Mar 29
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
AC ELECTRICAL CHARACTERISTICS (3.3V "10%)
V
DD
= 3.3V "10%, T
= –40_C to +85_C (industrial)
amb
LIMITS
SYMBOL
All Cycles
FIGURE
PARAMETER
UNIT
MIN
MAX
F
25
25
25
25
25
25
All
All
All
All
All
26
System Clock (internally called CClk) Frequency
System Clock Period = 1/FC
XTALIN High Time
0
30
–
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
t
C
33.33
t
t * 0.5
–
CHCX
C
t
XTALIN Low Time
t * 0.4
–
CLCX
CLCH
CHCL
C
t
t
XTALIN Rise Time
–
–
5
XTALIN Fall Time
5
t
Address Valid to Strobe low
t
– 21
–
AVSL
C
9
t
Address hold after CLKOUT rising edge
1
–
1
1
–
CHAH
t
Delay from CLKOUT rising edge to address valid
30
28
25
CHAV
CHSH
9
t
Delay from CLKOUT rising edge to Strobe High
9
t
Delay from CLKOUT rising edge to Strobe Low
CHSL
t
ClkOut Duty Cycle High (into 40pF max.)
t
–7
t
+3
CODH
CHCX
CHCX
(See Warning Note 5 on page 31.)
t
13, 14, 16, CAS Pulse Width High
20, 21, 22
t
– 12
–
ns
ns
CPWH
C
t
13, 21
CAS Pulse Width Low
t
C
– 10
–
–
CPWL
All DRAM cycles
8
t
24
RAS precharge time, thus minimum RAS high time
(n * t ) –16
note 8
ns
ns
ns
RP
C
Generic Data Read Only
9, 16
t
Address hold (A19–A1 only, not A0) after CS, BLE, BHE rise at end
of Generic Data Read Cycle (not code fetch)
t
–12
–
–
AHDR
C
Data Read and Instruction Fetch Cycles
t
9, 10,
Data In Valid setup to ClkOut rising edge
32
DIS
12–14, 16,
17, 20, 21
2
t
Data In Valid hold after ClkOut rising edge
0
–
–
ns
ns
DIH
t
10, 12, 13, OE high to XA Data Bus Driver Enable
16, 20, 21
t
C
– 19
OHDE
Write Cycles
t
Clock High to Data Valid
–
30
–
ns
ns
ns
ns
CHDV
t
Data Valid prior to Strobe Low
t
t
t
– 23
– 25
– 25
DVSL
SHAH
SHDH
C
C
C
t
11, 16
21
Minimum Address Hold Time after strobe goes inactive
Data hold after strobes (CS and BHE/BLE) high
–
t
–
Refresh
t
CAS low to RAS low
t
C
– 15
–
ns
CLRL
Wait Input
t
24
24
WAIT setup (stable high or low) prior to CLKOUT rising edge
WAIT hold (stable high or low) after CLKOUT rising edge
25
0
–
–
ns
ns
WS
t
WH
NOTES:
1. On a 16 bit bus, if only one byte is being written, then only one of BLE_CASL or BHE_CASH will go active. On an 8 bit bus, BLE_CASL
goes active for all (odd or even address) accesses. BHE_CASH will not go active during any accesses on an 8 bit bus.
2. The bus timing is designed to make meeting hold time very straightforward without glue logic. On all generic reads and fetches, in order to
meet hold time, the slave device should hold data valid on the bus until the earliest of CS, BHE/BLE, OE, goes high (inactive), or until the
address changes. On all FPM DRAM reads and fetches, hold data valid on the bus until the earliest of RAS, CAS, or OE goes high
(inactive.) On all EDO DRAM reads and fetches, hold data valid on the bus until a new CAS is asserted, or until OE goes high (inactive.)
3. To avoid tri-state fights during read cycles and fetch cycles, do not drive data bus until OE goes active
30
1999 Mar 29
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
4. To meet hold time, EDO DRAM drives data onto the bus until OE rises, or until a new falling edge of CAS.
5. WARNING: ClkOut is specified at 40pF max. More than 40pf on ClkOut may significantly degrade the ClkOut waveform. Load capacitance
for all outputs (except ClkOut) = 80pF.
6. Not all combinations of bus timing configuration values result in valid bus cycles. Please refer to the XA-SCC User Manual for details.
7. When code is being fetched on the external bus, a burst mode fetch is used. This burst can be from 2 to 16 bytes long. On a 16 bit bus,
A3–A1 are incremented for each new word of the burst. On an 8 bit bus, A3–A0 are incremented for each new byte of the burst code fetch.
8. t is specified as the minimum high time (thus inactive) on each of the 5 individual CS_RAS[5:1] pins when such pin is programmed in the
RP
memory controller to service DRAM. The number of CClks (system clocks) in t is programmable, and is represented by n in the t
RP
RP
equation in the AC tables. Regardless of what value is programmed into the control register, n will never be less than 2 clocks. Thus at
30MHz system clock, the minimum value for RAS precharge is t = ((2 * t ) –16) = ((2 * 33.33) – 16) = 50.6ns. As the system clock
RP
C
frequency F , is slowed down, t (system clock period) of course becomes greater, and thus t becomes greater.
C
C
RP
9. The MIN value for this parameter is guaranteed by design and is not tested in production to the specified limit. In those cases where a
maximum value is specified in the table for this parameter, it is tested.
31
1999 Mar 29
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
CLKOUT
A0
t
t
CHAV
CHAH
A19–A1
t
t
(DOES NOT INCLUDE A0)
CHSL
AHDR
t
AVSL
CS
BHE/BLE
OE
t
CHSH
NOTE 3
t
(NOTE 2)
DIH
t
DIS
D15–D0
NOTE: On Generic Data Reads, A0 can terminate a full clock period before A19–A1,
and therefore should not be used on some peripheral devices.
SU01130
Figure 9. Generic (SRAM, ROM, Flash, IO Devices, etc.) Read on 16 Bit Bus
CLKOUT
A[19:0]
t
t
CHAV
CHAV
t
CHAV
ADDRESS + 4
ADDRESS
ADDRESS + 2
t
CHSL
t
t
CHSH
AVSL
CS
BHE/BLE
t
NOTE 3
OE
OHDE
t
(NOTE 2)
t
DIH
t
DIH
DIH
t
t
DIS
t
DIS
DIS
NOTE 2
NOTE 2
DRIVEN
BY XA
D[15:0]
DRIVEN BY XA
NOTE: The processor can prefetch from one to eight words.
NOTE 2: To meet the required Data In Hold time, data should be held on the bus at least until the earliest of CS, BHE, BLE, OE goes high, or until the address changes,
whichever comes first.
SU01131
Figure 10. Generic Memory (SRAM, ROM, Flash, etc.) Burst Code Fetch on 16 Bit Bus
32
1999 Mar 29
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
CLKOUT
t
CHAV
t
CHSH
A
t
CHSL
t
CS
AVSL
t
SHAH
NOTE 1
BHE/BLE
WE
t
SHDH
t
CHDV
D
SU01132
Figure 11. Generic (SRAM, IO Devices, etc.) Write
CLKOUT
t
CHAH
A
RAS ADDRESS
CAS ADDRESS
t
t
CHAV
CHAV
t
CHSL
t
CHSH
t
AVSL
RAS (CS)
t
CHSL
t
CAS (BHE/BLE)
AVSL
t
CHSH
OE
D
t
OHDE
t
DIH
NOTE 2
t
DIS
VALID DATA
SU01133
Figure 12. DRAM Single Read Cycle
33
1999 Mar 29
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
CLKOUT
t
CHAV
t
CHAH
t
t
CHAH
CHAH
A
RAS ADDRESS
CAS ADDRESS
CAS ADDRESS + 2
t
t
CHAV
CHAV
t
CHSL
t
t
CHSH
CHSH
tAVSL
RAS (CS)
t
CHSL
t
t
t
CPWL
CAS (BHE/BLE)
AVSL
CPWH
NOTE 3
OE
t
OHDE
t
NOTE 4
t
NOTE 4
DIS
DIS
WORD
(from CAS ADDR)
WORD
(from CAS ADDR + 2)
DRIVEN BY XA
DRIVEN BY SLAVE DEVICE
D[15:0]
4 Byte Fetch (1 word = 2 bytes) is shown on 16 bit bus, burst can be 2 to 16 bytes (1 to 8 words.)
Note 4: To meet hold time, EDO DRAM drives valid Data until OE rises, or until new falling edge of CAS.
SU01134
Figure 13. DRAM EDO Burst Code Fetch on 16 Bit Bus
CLKOUT
t
t
t
t
t
CHAV
CHAV
CHSL
CHAV
CHAV
A
RAS ADDRESS
CAS ADDRESS
CAS ADDRESS + 2
t
t
CHAH
CHAH
t
t
CHAH
CHSL
t
t
CHSH
AVSL
RAS
t
CHSH
t
AVSL
CASL/CASH
t
CPWH
t
CHSL
OE
NOTE 2
t
NOTE 2
t
DIS
DIS
D[15:0]
INSTRUCTION
INSTRUCTION
NOTE: The processor can prefetch from one to eight words (1 word = 2 bytes)
SU01135
Figure 14. DRAM FPM (Fast Page Mode) Burst Code Fetch
34
1999 Mar 29
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
CLKOUT
t
t
t
t
CHAH
CHAV
CHAH
CHSL
RAS ADDRESS
CAS ADDRESS
A
t
t
CHSH
CHSL
t
RAS (CS)
AVSL
t
NOTE 1
AVSL
CAS (BHE/BLE)
t
CHSH
WE
D
t
CHDV
VALID DATA
NOTE: If only one byte is being written, then only the corresponding CAS signal goes active. On 8 bit bus, CASH is inactive, and CASL goes active for
both even and odd addressed bytes.
:
OE is inactive during all writes.
SU01136
Figure 15. DRAM Write (on 16 Bit Bus, also 8 Bit Write on 8 Bit Bus)
CLKOUT
t
CHAV
EVEN BYTE ADDRESS
ODD BYTE ADDRESS
A19–A1
A0
t
CHAV
t
t
AHDR
t
CHSL
t
CHSH
AVSL
CS
BLE
OE
NOTE 3
t
OHDE
t
DIH
NOTE 2
t
t
DIS
DIS
DRIVEN
BY XA
D7–D0
NOTE 2
DRIVEN BY XA
On all cycles on 8 bit bus, BHE remains high (inactive).
WARNING: On the external bus, ALL XA–SCC reads are 16 bit Reads. If the CPU instruction only specifies 8 bits, then the CPU uses the appropriate byte, and discards the extra
byte. Thus “8 Bit Reads” and “16 bit Reads” appear to be identical on the bus. On an 8 bit bus, this will appear as two consecutive 8 bit reads even though the CPU will only use one
of the two bytes.
WARNING: Some 8 bit I/O devices (especially FIFOs) cannot operate correctly with 2 bytes being Read for a 1 Byte Read. The most common (and least expensive) solution is to
operate these 8 bit devices on a 16 bit bus, and access them in software on all odd byte (or all even byte) boundaries. An added benefit of this technique is that byte reads are faster
than on an 8 bit bus, because only 1 word is fetched (a single read) instead of 2 consecutive bytes.
SU01137
Figure 16. Generic (SRAM, Flash, I/O Device, etc.) Read (16 Bit or 8 Bit) on 8 Bit Bus
35
1999 Mar 29
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
ClkOut
t
CHAV
t
t
t
CHAV
CHAV
CHAV
EVEN ADDRESS
ADDRESS + 1
ADDRESS + 2
ADDRESS + 3
t
CHAV
t
NOTE 3
CHSH
OE, BLE, CS
D[7:0]
t
t
t
t
DIH
DIH
DIH
DIH
t
t
t
t
DIS
DIS
DIS
DIS
Note 2
Note 2
Note 2
Note 2
LS BYTE
MS BYTE
LS BYTE
MS BYTE
NOTES: BHE remains high (inactive) for all accesses on an 8 bit bus.
A burst code fetch can be from 1 to 8 words (1 word = 2 bytes), a 2 word fetch is shown here.
To meet the required Data In Hold time, data should be held on the bus at least until the earliest of CS, BLE, OE goes high, or until the address changes, whichever occurs
first.
SU01138
Figure 17. Burst Code Fetch on 8 bit bus, Generic Memory
ClkOut
t
CHSH
t
CHSL
t
CHAV
A19–A1
t
t
A0
SHAH
SHAH
t
CHSL
t
AVSL
CS
BLE, WE
D7–D0
t
AVSL
t
t
DVSL
SHDH
OE is inactive during all writes.
SU01139
Figure 18. Generic 16 Bit Write on 8 Bit Bus
36
1999 Mar 29
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
CLKOUT
t
t
CHAV
CHSL
t
t
t
CHAV
CHAV
CHAV
A
RAS ADDRESS
CAS ADDRESS EVEN
CAS ADDRESS ODD
t
t
CHAH
CHAH
t
CHAH
t
CHSL
t
t
CHSH
RAS
AVSL
t
CHSH
t
AVSL
CASL
(CASH STAYS HIGH)
t
CPWH
t
CHSL
OE
NOTE 2
t
t
(NOTE 2)
t
DIS
DIS
DIH
D[7:0]
LS BYTE
MS BYTE
SU01140
Figure 19. 16 Bit Read on 8 Bit Bus, DRAM (both FPM and EDO)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
ClkOut
t
CHAH
t
CHAV
CAS ADDR
(EVEN)
CAS ADDR
(ODD)
CAS ADDR
(EVEN)
CAS ADDR
(ODD)
A
RAS ADDR
t
CHSL
t
CHSH
t
AVSL
RAS
t
t
CHSL
CHSH
t
CPWH
t
CASL
AVSL
t
CHSH
OE
t
OHDE
t
t
(NOTE 2)
t
(NOTE 2)
DIS
DIH
DIH
D7–D0
LS BYTE
MS BYTE
LS BYTE
MS BYTE
4 Byte Fetch is shown on 8 bit bus, burst can be 2 to 16 bytes.
Data bus is sampled on the rising edge of clock 6, and every three clocks thereafter (clocks 6, 9, 12, and 15 in this example).
NOTE 2: If data is held valid on the bus until the earliest of CAS, RAS, or OE rises, then the hold time is met.
SU01141
Figure 20. DRAM FPM (Fast Page Mode) Burst Code Fetch on 8 Bit Bus
37
1999 Mar 29
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
1
2
3
4
5
6
7
8
9
10
11
12
ClkOut
t
CHAH
t
CHAV
CAS ADDR
(EVEN)
CAS ADDR
(ODD)
CAS ADDR
(EVEN)
CAS ADDR
(ODD)
RAS ADDRESS
A
t
CHSL
t
t
CHSH
CHSH
t
AVSL
RAS
t
CHSL
t
CPWL
t
CASL
AVSL
t
CPWH
t
CHSH
NOTE 3
OE
t
OHDE
t
NOTE 4
MS BYTE
NOTE 4
MS BYTE
DIS
DRIVEN
BY XA
DRIVEN BY SLAVE
LS BYTE
D7–D0
LS BYTE
4 Byte Fetch is shown on 8 bit bus, burst can be 2 to 16 bytes.
NOTE 4: To meet hold time, EDO DRAM drives Data until OE rises, or until a new falling edge of CAS.
Data Bus is sampled on rising edge of clock 6, and every 2 clocks thereafter (clocks 6, 8, 10, and 12 in this example).
SU01142
Figure 21. EDO DRAM Burst Code Fetch on 8 Bit Bus
CLKOUT
t
t
t
t
t
CHAV
CHAV
CHAV
CHSL
CHAV
A
RAS ADDRESS
CAS ADDRESS (EVEN)
CAS ADDRESS (ODD)
t
t
CHAH
CHAH
t
CHAH
t
CHSL
t
t
CHSH
AVSL
RAS (CS)
CASL
t
CHSH
t
AVSL
t
CPWH
t
CHSL
WE
t
t
DVSL
DVSL
D[7:0]
LS BYTE
MS BYTE
SU01143
Figure 22. DRAM 16 Bit Write on 8 Bit Bus (FPM or EDO DRAMs)
38
1999 Mar 29
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
CLKOUT
t
CHSL
t
CHSH
RAS
t
CLRL
CASH, CASL
RAS and CAS terminate together. The active low portion of RAS can be programmed to last from 3 to 6 clock cycles.
The high portion of RAS after Refresh can be programmed to last from 2 to 4 clock cycles. See Chapter 3 of XA–SCC User Manual.
SU01144
Figure 23. REFRESH
t
RP
RAS
NOTE: t min. is specified for each of the 5 individual RAS pins (CS_RAS[5:1]).
RP
It is the minimum high time (thus RAS inactive) between two DRAM bus cycles on the same RAS pin.
SU01145
Figure 24. RAS Precharge Time
V
– 0.5
DD
0.7 V
DD
XTALIN
0.2 V – 0.1
DD
0.45 V
t
CHCX
t
t
t
CLCH
CHCL
CLCX
t
C
SU01146
Figure 25. External Clock Input Drive
t
CODH
ClkOut
WARNING: ClkOut is specified into 40 pF max, do not overload.
SU01147
Figure 26. ClkOut Duty Cycle
39
1999 Mar 29
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
ClkOut
t
t
WH
WS
WAIT
t
t
– Setup time of WAIT to riasing edge of ClkOut.
– Hold time of WAIT after ClkOut High.
WS
WH
SU01148
Figure 27. External WAIT Pin Timing
40
1999 Mar 29
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm
SOT407-1
mold mark
mold mark
41
1999 Mar 29
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1999
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 03-99
Document order number:
9397 750 05491
Philips
Semiconductors
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