AT8563 [Narda-ATM]
AT8563是一款经典的工业级实时时钟芯片(RTC)，I2C总线接口，具有功耗低、精度高等特点，广泛应用于电表、水表、气表、电话等产品。;
| 型号： | AT8563 |
| 厂家： | 
Narda-ATM |
| 描述： | AT8563是一款经典的工业级实时时钟芯片(RTC)，I2C总线接口，具有功耗低、精度高等特点，广泛应用于电表、水表、气表、电话等产品。 电话 时钟 |
| 文件： | 总24页 (文件大小：729K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DataSheet
AT8563
——A low power RTC chip with I2C
深圳市宏达科技有限公司
深圳市宏达科技有限公司 Tel：0755-36917049 Moile：13530382140 曾先生 Fax：0755-29502958
CONTENTS
1
2
Chip Overview............................................................................................................................1
Functional Description................................................................................................................2
2.1 Summary ..........................................................................................................................2
2.2 Alarm function modes......................................................................................................4
2.3 Timer................................................................................................................................4
2.4 CLKOUT output ..............................................................................................................4
2.5 Reset.................................................................................................................................4
2.6 Voltage-low detector........................................................................................................4
2.7 Register organization .......................................................................................................5
2.7.1 Control/Status 1 register........................................................................................6
2.7.2 Control/Status 2 register........................................................................................6
2.7.3 Seconds, Minutes and Hours registers ..................................................................7
2.7.4 Days, Weekdays, Months/Century and Years registers ........................................7
2.7.5 Alarm registers......................................................................................................9
2.7.6 CLKOUT frequency register...............................................................................10
2.7.7 Countdown timer registers ..................................................................................10
2.8 EXT_CLK test mode......................................................................................................11
2.9 Power-On Reset override mode .....................................................................................12
Serial interface ..........................................................................................................................12
3.1 I2C Specification ............................................................................................................12
3.2 I2C of AT8563................................................................................................................14
Parameters.................................................................................................................................15
Application Reference...............................................................................................................19
5.1 Crystal frequency adjustment.........................................................................................19
Package outline .........................................................................................................................20
6.1 DIP-8..............................................................................................................................20
6.2 SO8 ................................................................................................................................21
6.3 TSSOP8..........................................................................................................................21
6.4 MSOP8...........................................................................................................................22
3
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AT8563
1 Chip Overview
AT8563 is a CMOS real-time clock/calendar chip optimized for low power consumption.
The timing counter consists of century, year, month, day, date, hour, minute and second bits.
External MPU can read or set the time as well as timer or alarmer when it is necessary. As
exchanging data by the advance serial bus I2C, lines number on PCB can be reduced
dramatically, which is very suitable in a complicated system.
The chip has the following features:
An external 32.768 kHz crystal is needed to generated time base
Wide operating supply voltage range: 1.0 to 5.5 V
Low back-up current; typical 0.25 µA at VDD = 3.0 V and Tamb = 25 °C
400 kHz two-wire I2C-bus interface (at VDD = 1.8 to 5.5 V)
Programmable clock output for peripheral devices: 32.768 kHz, 1024 Hz 32 Hz
and 1 Hz
Alarm and timer functions
Voltage-low detector
Integrated oscillator capacitor
Internal power-on reset
I2C-bus slave address: read A3H; write A2H
Typical Applications:
Mobile telephones
Portable instruments
OA equipments such as Fax machines
Battery powered products
Table 1 shows our ordering information for AT8563.
Table1 Ordering information
Type number
Package
Name
Name
DIP8
Description
quantity
100/tape
2500/reel
3000/reel
3000/reel
AT8563P
AT8563T
AT8563TS
AT8563S
plastic dual in-line package; 8 leads (300 mil)
plastic small outline package; 8 leads; body width 3.9 mm
plastic small outline package; 8 leads; body width 3.0 mm
plastic small outline package; 8 leads; body width 3.0 mm
SO8
SSO8
MSOP8
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Table 2 Quick reference data
Symol
Parameter
Conditions
Min
1.0
Max
5.5
Unit
I2C-bus inactive; Tamb = 25 °
I2C-bus active; fSCL = 400 kHz;
V
V
VDD
supply voltage operating mode
1.8
5.5
Tamb = −30 to +85°C
fSCL = 200 kHz
800
200
µA
µA
supply crrent; timer and CLKOUT
disabled
fSCL = 100 kHz
IDD
fSCL = 0 Hz; Tamb= 25 °C
VDD = 5 V
550
450
µA
µA
°C
°C
VDD = 2 V
Tamb
Tstg
operating ambient temperature
storage temperature
-
-
−30
−65
+85
+150
2 Functional Description
2.1 Summary
The device’s structure is shown in Fig 1.
Fig 1 Block diagram
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AT8563
AT8563’s pin layout and its protection network are shown in Fig 2 and Fig 3.
Fig 3 Device diode protection diagram
Fig 2 Pin Layout
Table 3 gives the pins’ description.
Table 3: Pin description
Description
Symbol
OSCI
OSCO
INT
Pin
1
oscillator input
oscillator output
2
3
interrupt output (open-drain; active LOW)
ground
VSS
4
SDA
5
serial Data I/O (open-drain)
serial Clock in
SCL
6
CLKOUT
VDD
7
clock output (open-drain)
positive power supply
8
AT8563 contains sixteen 8-bit registers with an auto-increasing address register, an
on-chip 32.768 kHz oscillator with an integrated capacitor, a frequency divider which provides
source clock for the Real-Time Clock (RTC), a programmable clock output, a timer, an alarm, a
voltage-low detector and a I2C-bus interface.
The 16 registers are mapped into a memory block, which is addressable, but not all bits
are implemented. The first two registers (memory address 00H and 01H) are used as control
and/or status registers. The memory addresses 02H through 08H are used as counters for the
clock function (seconds up to year counters). Address locations 09H through 0CH contain
alarm registers which define the conditions for an alarm. Address 0DH controls the frequency
of CLKOUT output. 0EH and 0FH are timer control, timer counter register, respectively.
The Seconds, Minutes, Hours, Days, Months, Years as well as the Minute alarm, Hour
alarm and Day alarm registers are all coded in BCD format. The Weekdays and Weekday
alarm register are not coded in BCD format.
When one of the RTC registers is read the contents of all counters are frozen. Therefore,
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faulty reading of the clock/calendar during a carry condition is prevented.
2.2 Alarm function modes
———
By clearing the MSB (bit AE= Alarm Enable) of one or more of the alarm registers, the
corresponding alarm condition(s) will be active. In this way an alarm can be generated from
once per minute up to once per week. The alarm condition sets the alarm flag, AF (bit 3 of
Control/Status 2 register). The asserted AF can be used to generate an interrupt (INT). Bit AF
can only be cleared by software.
2.3 Timer
The 8-bit countdown timer (address 0FH) is controlled by the Timer Control register
(address 0EH; see Table 25). The Timer Control register selects one of 4 source clock
frequencies for the timer (4096, 64, 1, or 1⁄60 Hz), and enables/disables the timer. The timer
counts down from a software-loaded 8-bit binary value. At the end of every countdown, the
timer sets the timer flag TF (see Table 7). The timer flag TF can only be cleared by software.
The asserted timer flag TF can be used to generate aninterrupt (INT). The interrupt may be
generated as a pulsed signal every countdownperiod or as a permanently active signal which
follows the condition of TF. TI/TP (seeTable 7) is used to control this mode selection. When
reading the timer, current countdown value is returned.
2.4 CLKOUT output
A programmable square wave is available at the CLKOUT pin. Operation is controlled by
the CLKOUT frequency register (address 0DH; see Table 23). Frequencies of 32.768 kHz
(default), 1024, 32 and 1 Hz can be generated for use as a system clock, microcontroller clock,
input to a charge pump, or for calibration of the oscillator. CLKOUT is an open-drain output
and enabled at power-on. If disabled it becomes high-impedance.
2.5 Reset
AT8563 includes an internal reset circuit which is active whenever the oscillator is
stopped. In the reset state the I2C-bus logic is initialized and all registers, including the address
———
pointer, are cleared with the exception of bits FE, VL, TD1, TD0, TESTC and AEwhich are set
to logic 1.
2.6 Voltage-low detector
AT8563 has an on-chip voltage-low detector. When VDD drops below Vlow the VL bit
(Voltage Low, bit 7 in the Seconds register) is set to indicate that reliable clock/calendar
information is no longer guaranteed. The VL flag can only be cleared by software.
The VL bit is intended to detect the situation when VDD is decreasing slowly for example
under battery operation. Should VDD reach Vlow before power is re-asserted then the VL bit will
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be set. This will indicate that the time may have been corrupted.
Fig 4 Voltage-low detection
2.7 Register organization
Table 4 Registers overview
Address
Register name
b7
b6
b5
b4
b3
b2
b1
b0
00H
01H
0DH
0EH
Control/Status 1
Control/Status 2
CLKOUT frequency
Timer control
TEST1
0
0
0
-
STOP
0
TESTC
0
TF
-
0
0
0
-
TI/TP
AF
AIE
TIE
FE
-
-
-
-
FD1 FD0
TD1 TD0
TE
-
-
-
0FH
Timer countdownvalue
<timer countdown value>
Note: Bit positions labeled as ‘− ’are not implemented; those labeled with ‘0’ should always be written with
logic 0.
Table 5 BCD formatted registers overview
Address
Register name
b7
b6
b5
b4
b3
b2
b1
b0
Seconds
minutes
hours
02H
03H
04H
05H
06H
VL
－
－
－
－
ten seconds（0-5）
ten minutes（0-5）
seconds（0-9）
minutes（0-9）
hours（0-9）
days（0-9）
－
－
－
ten hours（0-2）
ten days（0-3）
days
weekday
－
－
－
－
weekdays（0-6）
month（0-9）
ten month
07H
months/century
C
－
（0-1）
08H
09H
0AH
0BH
0CH
years
ten years（0-9）
years（0-9）
minutes（0-9）
hours（0-9）
———
minute alarm
hour alarm
day alarm
ten minutes（0-5）
AE
———
－
－
－
ten hours（0-2）
ten days（0-3）
AE
———
days（0-9）
AE
———
weekday alarm
－
－
－
weekdays（0-6）
AE
Note: Bit positions labelled as ‘− ’are not implemented.
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2.7.1 Control/Status 1 register
Table 6 Control/Status 1 register bits description
00H
b7
Symbol
TEST1
Description
TEST1 = 0; normal mode.
TEST1 = 1; EXT_CLK test mode; see Section 8.7.
STOP = 0; RTC source clock runs.
STOP = 1; all RTC divider chain flip-flops are asynchronously set to logic 0; the
RTC clock is stopped (CLKOUT at 32.768 kHz is still available).
b5
STOP
TESTC = 0; power-on reset override facility is disabled (set to logic 0 for normal
operation).
TESTC = 1; power-on reset override is enabled.
b3
TESTC
-
b6, b4,
b2..0
By default set to logic 0.
2.7.2 Control/Status 2 register
Table 7 Description of Control/Status 2 register bits description
01H
Symbol
0
Description
b7..5
By default set to logic 0
TI/TP = 0: INT is active when TF is active (subject to the status of TIE).
TI/TP = 1: INT pulses active according to Table 8 (subject to the status of TIE). Note
that if AF and AIE are active then INT will be permanently active.
When an alarm occurs, AF is set to logic 1. Similarly, at the end of a timer
countdown, TF is set to logic 1. These bits maintain their value until overwritten by
software. If both timer and alarm interrupts are required in the application, the source
of the interrupt can be determined by reading these bits. To prevent one flag being
overwritten while clearing another, a logic AND is performed during a write access.
See Table 9 for the value descriptions of bits AF and TF.
Bits AIE and TIE activate or deactivate the generation of an interrupt when AF or TF
is asserted, respectively. The interrupt is the logical OR of these two conditions
when both AIE and TIE are set.
AIE = 0: alarm interrupt disabled; AIE = 1: alarm interrupt enabled.
TIE = 0: timer interrupt disabled; TIE = 1: timer interrupt enabled.
b4
b3
TI/TP
AF
b2
b1
b0
TF
AIE
TIE
———
Table 8 INT operation (bit TI/TP = 1)
———
INT period(s)
Source clock (Hz)
n=1
n>1
4096
64
1/8192
1/128
1/64
1/4096
1/64
1
1/64
1/60
1/64
1/64
Note:
———
[1] TF and INT become active simultaneously.
[2] n = loaded countdown timer value. Timer stopped when n = 0.
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Table 9 Value descriptions for bits AF and TF
Bit: AF Bit: TF
Description Description
R/W
Value
Value
0
alarm flag inactive
0
1
0
1
timer flag inactive
timer flag active
Read
1
alarm flag active
0
alarm flag is cleared
alarm flag remains unchanged
timer flag is cleared
Write
1
timer flag remains unchanged
2.7.3 Seconds, Minutes and Hours registers
Table 10: Seconds/VL register bits description
02H
b7
Symbol
VL
Description
VL = 0: reliable clock/calendar information is guaranteed;
VL = 1: reliable clock/calendar information is no longer guaranteed.
These bits represent the current seconds value coded in BCD format; value
= 00 to 59.
b6..0 <seconds>
Example: <seconds> = 101 1001, represents the value 59 s.
Table 11 Minutes register bits description
Description
03H
b7
Symbol
-
not implemented
These bits represent the current minutes value coded in BCD
format; value = 00 to 59.
b6..0 <minutes>
Table 12 Hours register bits description
Description
04H
b7..6
b5..0
Symbol
-
not implemented
These bits represent the current hours value coded in BCD format; value = 00
to 23.
<hours>
2.7.4 Days, Weekdays, Months/Century and Years registers
Table 13 Days register bits description
05H Symbol
b7..6
Description
-
not implemented
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These bits represent the current day value coded in BCD format; value = 01 to
31.
AT8563 compensates for leap years by adding a 29th day to February if the year
counter contains a value which is exactly divisible by 4, including the year ‘00’.
b5..0 <days>
Table 14 Weekdays register bits description
Description
06H
Symbol
b7..3
-
not implemented
These bits represent the current weekday value 0 to 6, whose
meaning is customized by users. However, we recommend a way
to specify the weekday number, see Table 15.
These bits may be re-assigned by the user.
b2..0 <weekdays>
Table 15 Suggested Weekday assignments
Day
Bit 2 Bit 1 Bit 0
Sunday
Monday
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Tuesday
Wednesday
Thursday
Friday
Saturday
Table 16 Months/Century register bits description
07H
Symbol
Description
Century bit. C = 0; indicates the century is 20xx.
C = 1; indicates the century is 19xx. ‘xx’ indicates the value held in the
Years register; see Table 18.
This bit is toggled when the Years register overflows from 99 to 00.
These bits may be re-assigned by the user
b7
C
-
b6..5
not implemented
These bits represents the current month value coded in BCD format;
value = 01 to 12; see Table 17.
b4..0 <months>
Table 17 Month assignments
Month
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
January
February
March
April
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
1
0
1
0
May
June
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July
0
0
0
1
1
1
0
1
1
0
0
0
1
0
0
0
0
0
1
0
0
0
0
1
1
0
1
0
1
0
August
September
October
November
December
Table 18 Years register bits description
08H
Symbol
Description
This register represents the current year value coded in BCD format; value
= 00 to 99.
b7..0 <years>
2.7.5 Alarm registers
When one or more of the alarm registers are loaded with a valid minute, hour, day or
———
weekday and its corresponding AE(Alarm Enable) bit is a logic 0, then that information will be
compared with the current minute, hour, day and weekday. When all enabled comparisons first
match, the bit AF (Alarm Flag) is set.
AF will remain set until cleared by software. Once AF has been cleared it will only be set
again when the time increments to match the alarm condition once more. Alarm registers
———
which have their AE bit set at logic 1 will be ignored.
Table 19 Minute alarm register bits description
09H
b7
Symbol
Description
———
———
———
AE= 0; minute alarm is enabled. A E= 1; minute alarm is disabled.
AE
These bits represents the minute alarm information coded in BCD
format; value = 00 to 59.
b6..0 <minute alarm>
Table 20 Hour alarm register bits description
0AH
7
Symbol
Description
———
———
———
AE
AE= 0; hour alarm is enabled. A E= 1; hour alarm is disabled.
These bits represents the hour alarm information coded in BCD
format; value = 00 to 23.
6 to
0
<hour alarm>
Table 21: Day alarm register bits description
0BH
b7
Symbol
Description
———
———
———
AE
AE= 0; day alarm is enabled. A E= 1; day alarm is disabled.
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These bits represents the day alarm information coded in BCD
format; value = 01 to 31.
b6..0
<day alarm>
Table 22 Weekday alarm register bits description
Symbol Description
0CH
b7
———
———
AE= 0; weekday alarm is enabled.
———
AE
AE= 1; weekday alarm is disabled.
These bits represents the weekday alarm information
value 0 to 6.
b6..0 <Weekday alarm>
2.7.6 CLKOUT frequency register
Table 23 CLKOUT frequency register bits description
0DH
Symbol
Description
FE = 0; the CLKOUT output is inhibited and the CLKOUT output is set to
high-impedance. FE = 1; the CLKOUT output is activated.
b7
FE
-
b6..2
not implemented
b1
b0
FD1
FD0
These bits control the frequency output (fCLKOUT) on the CLKOUT pin; see
Table 24.
Table 24 CLKOUT frequency selection
FD1 FD0
fCLKOUT
32.768 kHz
1 024 Hz
32 Hz
0
0
1
1
0
1
0
1
1 Hz
2.7.7 Countdown timer registers
The Timer register is an 8-bit binary countdown timer. It is enabled and disabled via the
Timer control register bit TE. The source clock for the timer is also selected by the Timer
control register. Other timer properties, e.g. interrupt generation, are controlled via the
Control/status 2 register. For accurate read back of the countdown value, the I2C-bus clock
SCL must be operating at a frequency of at least twice the selected timer clock.
Table 25 Timer control register bits description
Symbol
Description
TE = 0; timer is disabled. TE = 1; timer is enabled.
not implemented
0EH
b7
TE
-
b6～b2
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Symbol
Description
0EH
b1
Timer source clock frequency selection bits. These bits
determine the source clock for the countdown timer, see
Table 26. When not in use, TD1 and TD0 should be set to
‘11’ (1⁄60 Hz) for power saving.
TD1
b0
TD0
Table 26 Timer source clock frequency selection
Timer source clock
TD[1:0]
frequency（Hz）
00
01
10
11
4096
64
1
1/60
Table 27 Timer countdown value register bits description
Description
0FH
Symbol
<timer countdown value>
b7～b0
countdown value n, the counter’s period is “”n/fCLK”
2.8 EXT_CLK test mode
A test mode is available which allows for on-board testing. In this mode it is possible to set
up test conditions and control the operation of the RTC.
The test mode is entered by setting bit TEST1 in the Control/Status1 register. The
CLKOUT pin then becomes an input. The test mode replaces the internal 64 Hz signal with the
signal that is applied to the CLKOUT pin. Every 64 positive edges applied to CLKOUT will then
generate an increment of one second.
The signal applied to the CLKOUT pin should have a minimum pulse width of 300 ns and
a minimum period of 1000 ns. The internal 64 Hz clock, now sourced from CLKOUT, is divided
down to 1 Hz by a 26 divide chain called a pre-scaler. The pre-scaler can be set into a known
state by using the STOP bit. When the STOP bit is set, the pre-scaler is reset to 0. STOP must
be cleared before the pre-scaler can operate again. From a STOP condition, the first 1 s
increment will take place after 32 positive edges on CLKOUT. Thereafter, every 64 positive
edges will cause a 1 s increment.
Remark: Entry into EXT_CLK test mode is not synchronized to the internal 64 Hz clock.
When entering the test mode, no assumption as to the state of the pre-scaler can be made.
You can operate in the following steps:
1. Enter the EXT_CLK test mode; set bit 7 of Control/Status 1 register (TEST = 1)
2. Set bit 5 of Control/Status 1 register (STOP = 1)
3. Clear bit 5 of Control/Status 1 register (STOP = 0)
4. Set time registers (Seconds, Minutes, Hours, Days, Weekdays, Months/Century and
Years) to desired value
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5. Apply 32 clock pulses to CLKOUT
6. Read time registers to see the first change
7. Apply 64 clock pulses to CLKOUT
8. Read time registers to see the second change.
Repeat steps 7 and 8 for additional increments if necessary.
2.9 Power-On Reset override mode
The POR duration is directly related to the crystal oscillator start-up time. Due to the long
start-up times experienced by these types of circuits, a mechanism has been built in to disable
the POR and hence speed up on-board test of the device. The setting of this mode requires
that the I2C-bus pins, SDA and SCL, be toggled in a specific order as shown in Fig 5. All timing
values are required minimum.
Once the override mode has been entered, the chip immediately stops being reset and
normal operation starts i.e. entry into the EXT_CLK test mode via I2C-bus access. The
override mode is cleared by writing a logic 0 to bit TESTC. Re-entry into the override mode is
only possible after TESTC is set to logic 1. Setting TESTC to logic 0 during normal operation
has no effect except to prevent entry into the POR override mode.
Fig 5 POR override sequence.
3 Serial interface
The serial interface of AT8563 is the I2C -bus, which requires minimum connections
between MPU and it peripherals ——.a serial Data I/O line and a serial CLK line driven by
MPU.
3.1 I2C Specification
The I2C -bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when
the bus is idle.
The I2C -bus system configuration is shown in Fig 6. A device generating a message is a
‘transmitter’, a device receiving a message is the ‘receiver’. The device that controls the
message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’.
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Fig 6 I2C-bus system configuration.
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH is defined as the start condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop
condition (P); see Fig 7.
Fig 7 START and STOP conditions on the I2C-bus
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time will be
interpreted as a control signal; see Fig 8.
Fig 8 Bit transfer on the I2C-bus
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit.
The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time
the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the
reception of each byte. Also a master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the slave transmitter.
The device that acknowledges must pull down the SDA line during the acknowledge clock
pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related
clock pulse (set-up and hold times must be taken into consideration).
A master receiver must signal an end of data to the transmitter by not generating an
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acknowledge on the last byte that has been clocked out of the slave. In this event the
transmitter must leave the data line HIGH to enable the master to generate a STOP condition.
Fig 9 Acknowledge on the I2C -bus
3.2 I2C of AT8563
Before any data is transmitted on the I2C -bus, the device which should respond is
addressed first. The addressing is always carried out with the first byte transmitted after the
start procedure.
AT8563 acts as a slave receiver or slave transmitter. Therefore the clock signal SCL is
only an input signal, but the data signal SDA is a bidirectional line.
AT8563 slave address is shown in Fig 10.
Fig 10 Slave address
The I2C -bus configuration for the different AT8563 read and write cycles are shown in Fig
11, 12 and 13. The word address is a four bit value that defines which register is to be
accessed next. The upper four bits of the word address are not used.
Fig 11 Master transmits to slave receiver (write mode)
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Fig 12 Master reads after setting word address (write word address; read data)
Fig 13 Master reads slave immediately after first byte (read mode)
4 Parameters
Table 28 Absolute Parameters
Symbol
Parameter
Min
Max
Unit
VDD
IDD
supply voltage
supply current
-0.5
-50
+6.5
+50
6.5
V
mA
V
input voltage on inputs SCL and SDA
input voltage on input OSCI
-0.5
VI
-0.5
-0.5
VDD + 0.5
6.5
V
V
VO
output voltage on outputs CLKOUT and INT
II
DC input current at any input
DC output current at any output
total power dissipation
-10
-10
-
+10
300
+85
mA
mA
mW
IO
Ptot
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AT8563
Tamb
Tstg
operating ambient temperature
storage temperature
-40
-65
+150
-0.5
°C
°C
Please refer Table 29 and Table 30 for DC or AC characteristics.
Table 29: Static characteristics
(Test condition: VDD = 1.8 to 5.5 V; VSS = 0 V; Tamb =− 40 to 85° C; fOSC = 32.768 kHz; quartz Rs = 40 kΩ;
CL = 8 pF; unless otherwise specified. )
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supplies
I2C bus
1.0[1]
1.8[1]
VLOW
−
−
5.5
5.5
5.5
V
V
V
inactive; Tamb
= 25 °C
supply voltage
I2C bus active;
VDD
f
SCL = 400 kHz
Tamb=25 °C
−
supply voltage for reliable
clock/calendar information
[2]
fSCL=200kHz
−
−
−
800
200
μA
μA
fSCL=100kHz
fSCL=0Hz
VDD=5V
−
[2]
supply current;
IDD1
CLKOUT disabled(FE=0)
−
−
−
700
650
600
−
900
750
650
800
200
nA
nA
nA
μA
μA
VDD=3V
VDD=2V
[2]
fSCL=200kHz
fSCL=100kHz
fSCL=0kHz
VDD=5V
−
−
[2]
−
supply current;
CLKOUT enabled
(fCLKOUT = 32 kHz; FE = 1)
IDD2
−
−
−
1000
810
1100
900
800
nA
nA
nA
VDD=3V
VDD=2V
720
Inputs
VIL
VSS
0.7VDD
-1
0.3VDD
VDD
+1
V
V
−
−
−
−
LOW-level input voltage
HIGH-level input voltage
input leakage current
input capacitance
VIH
ILI
VI= VDD or VSS
μA
pF
[3]
Ci
7
−
Outputs
VOL=0.4V;
VDD=5V
IOL(SDA)
-3
mA
−
−
LOW-level output current;pin SDA
LOW-level output current;pin INT
––––––––––
-1
-1
mA
mA
−
−
−
−
IOL(
)
I N T
LOW-level output current; pin
CLKOUT
IOL(CLKOUT)
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AT8563
Symbol
Parameter
Conditions
OH=4.6V;
VDD=5V
Min
1
Typ
Max
Unit
mA
V
HIGH-level output current; pin
CLKOUT
IOH(CLKOUT)
−
−
ILO
VO=VDD or VSS
-1
+1
−
μA
output leakage current
Voltage detector
voltage-low detection level
Tamb=25℃
VLOW
−
0.9
1.0
V
[1] For reliable oscillator start-up at power-up: VDD(min) power-up = VDD(min) + 0.3 V.
[2] Timer source clock = 1⁄60 Hz; SCL and SDA = VDD
.
[3] Tested on sample basis.
Tamb=25℃;Timer=1 minute.
IDD as a function of VDD; CLKOUT = 32 kHz
Tamb=25℃;Timer=1 minute.
Fig 15
Fig 14 IDD as a function of VDD; CLKOUT disabled
Tamb=25℃;normalized to VDD=3V.
Fig 17 Frequency deviation as function of VDD
VDD=3V;Timer=1 minute.
Fig 16
IDD as a function of Tamb; CLKOUT = 32 kHz
Table 30 AC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
pF
Oscillator
CL
integrated load capacitance
oscillator stability
15
25
35
ΔVDD=200mV
amb=25℃
ΔfOSC/fOSC
−
2×10-7
−
T
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Quartz crystal parameters(fOSC=32.768kHz)
serial resistance
RS
CL
−
−
2
8
−
10
−
40
−
kΩ
parallel load capacitance
pF
Version B
Version C
10
12
CT
pF
trimmer capacitance
−
CLKOUT output
[1]
CLKOUT duty factor
I2 C-bus timing characteristics[2]
50
δCLKOUT
−
−
−
%
[3]
SCL clock frequency
fSCL
400
kHz
−
−
START condition hold time
tHD;STA
0.6
0.6
−
μs
set-up time for a repeated
START condition
tSU:STA
−
−
μs
SCL LOW time
tLOW
tHIGH
tr
1.3
0.6
−
−
−
−
−
−
−
−
−
−
−
−
μs
μs
μs
μs
pF
ns
ns
μs
ns
SCL HIGH time
SCL and SDA rise time
SCL and SDA fall time
capacitive bus line load
data set-up time
0.3
0.3
400
−
tf
−
Cb
−
tSU;DAT
tH D;DAT
tSU:STO
tSW
100
0
data hold time
−
set-up time for STOP condition
tolerable spike width on bus
4.0
−
−
50
[1] Unspecified for fCLKOUT = 32.768 kHz.
[2] All timing values are valid within the operating supply voltage range at Tamb and referenced to VIL and
VIH with an input voltage swing of VSS to VDD
.
[3] I2C -bus access time between two STARTs or between a START and a STOP condition to this device
must be less than one second.
Fig 18 I2C -bus timing waveforms.
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5 Application Reference
Fig 19 Typical Application diagram
5.1 Crystal frequency adjustment
Method 1: Fixed OSCI capacitor — By evaluating the average capacitance
necessary for the application layout a fixed capacitor can be used. The frequency is
best measured via the 32.768 kHz signal available after power-on at the CLKOUT
pin. The frequency tolerance depends on the quartz crystal tolerance, the capacitor
tolerance and the device-to-device tolerance (on average ±5 × 10−6).
Average deviations of ±5 minutes per year can be easily achieved.
Method 2: OSCI trimmer — The oscillator is tuned to the required accuracy by
adjusting a trimmer capacitor on pin OSCI and measuring the 32.768 kHz signal
available after power-on at the CLKOUT pin.
Method 3: OSCO output — Direct output measurement on pin OSCO (accounting for
test probe capacitance).
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6 Package outline
6.1 DIP-8
Table 20 DIP-8
Table 31 Dimension noted in Fig 20
A
A1
A2
z
Unit
b
b1
b2
c
D
E
e
e1
L
ME
MH
w
max min max
max
1.73 0.53 1.07 0.36 9.8 6.48
1.14 0.38 0.89 0.23 9.2 6.20
0.068 0.021 0.042 0.014 0.39 0.26
0.045 0.016 0.035 0.009 0.36 0.24
3.60 8.26 10.0
3.05 7.80 8.3
0.14 0.32 0.39
0.12 0.31 0.33
mm 4.2 0.51 3.2
inch 0.17 0.020 0.13
2.54 7.62
0.10 0.30
0.254 1.15
0.01 0.045
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6.2 SO8
图21 SO-8
Table 32 Dimension noted in Fig 21
A
D(1) E(2)
e
HE
L
LP
Q
v
w
y
z
Unit
A1
A2 A3 bp
c
θ
max
0.25 1.45
0.49
0.36
0.25
0.19
5.0 4.0
4.8 3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm 1.75
0.25
0.01
1.27
0.050
1.05
0.041
0.25 0.25 0.1
0.01 0.01 0.004
0.10 1.25
8°
0°°
0.010 0.057
0.004 0.049
0.019 0.0100 0.20 0.16
0.014 0.0075 0.19 0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inch 0.069
6.3 TSSOP8
Fig 22 TSSOP-8
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AT8563
Table 33 Dimension noted in Fig 22
Unit
mm
A
A1
B
C
D
E
e
H
0.006 0.012 0.007 0.122 0.176
0.002 0.007 0.004 0.114 0.169
0.256
0.246
0.043
0.0256
0.15
0.05
0.30
0.18
0.18
0.09
3.10
2.90
4.48
4.30
6.50
6.25
inch
1.10
0.65
6.4 MSOP8
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