KGL4201 [OKI]
10-Gbps GaAs Family High-Speed Optical Communications System; 10 - Gbps的砷化镓系列高速光通信系统
| 型号： | KGL4201 |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | 10-Gbps GaAs Family High-Speed Optical Communications System |
| 文件： | 总24页 (文件大小：429K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
O
K
I
G
a
A
s
P
R
O
D
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T
S
10-Gbps GaAs Family
High-Speed Optical Communications System
April 1999
■ ■ ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
CONTENTS
10-GHz GaAs Family .........................................................................................................................1
KGL4201
10-GHz 8:1 Multiplexer ............................................................................................................................. 3
KGL4202
10-GHz 1:8 Demultiplexer ........................................................................................................................ 7
GHDD4411
EX-OR Circuit.......................................................................................................................................... 11
GHDD4414
Decision Circuit with Phase Detector...................................................................................................... 15
Oki Semiconductor
10-GHz GaAs Family
High-Speed Optical Communications Systems
INTRODUCTION
Oki’s 10-GHz logic devices are manufactured using a 0.2-µm, ion-implanted process, which is similar to
Oki’s familiar 0.5-µm telecommunications process. However, the 0.2-µm process uses a phase-shifting
edge line (PEL) masking method for gate fabrication. Gold-based, three-level metal interconnections are
used for high density and shorter wiring paths. Layers 1 and 2 are signal lines. Layer 3, which is formed
by electroplating, is used for ground or power supply lines because of its lower resistance. An optional
buried “p” channel structure is adopted for reducing short channel effects.
The following table shows the digital GaAs logic processes of the 10-GHz GaAs family.
GaAs Logic Processes
Basic Gate
Circuit
Gate Length
(µm)
Gate Delays
(ps)
Basic FET Process
MESFET
Photo Masking
I-line printing
PEL
fT (GHz)
30
Application
DCFL or SBFL
DCFL or SBFL
0.5
< 0.2
0.2
25
9
< 2.4 Gbps standard cell
>12-Gbps hand-routed logic
> 20-Gbps low-density logic
Analog amplifier
MESFET
60
Pseudomorphic-inverted HEMT DCFL or SBFL
Pseudomorphic BP--MESFET Analog
PEL
> 60
> 60
7
Deep UV
0.2
–
The key to operating reliably at 10 Gbps is logic circuitry that can easily manipulate data at over 13 Gbps.
The higher frequency overhead is required to meet the different clock skews encountered when design-
ing and routing 10-Gbps data management hardware.
The logic is either direct-coupled FET logic (DCFL) or source-coupled FET logic (SCFL). The low-drive
disadvantage of DCFL can be improved by using super-buffer FET logic (SBFL). The basic speed of SBFL
is slower than DCFL, but SBFL is faster with higher fanouts and longer metal runs. A designer selects the
best performing logic for each logic element application. SBFLs used for clock distribution, output buff-
ers, etc. Typical gate delays of 9 ps and power of 2 mW per gate are achieved. Register logic elements like
D-flip flops are assembled using memory cell flip flops (MCFF) as shown in Figure 1.The operation speed
of a MCFF, which is about twice that of a conventional 6 NOR-gate circuit, operates at very low power.
To simplify device interconnections, AC-coupled clock and data input lines are created using the circuit
shown in Figure 2.
FEATURES
• 10-Gbps operation: highest speed available
• ECL level logic swings: easy interface to other
logic
• Inputs internally terminated: reduces noise and
phase jitter
• 50-Ω I/Os: easy to interconnect hardware
Oki Semiconductor
1
■ 10-GHz GaAs Family ■ ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
Data
Q
Data
Q
Master
Slave
Clock
Clock
Master/Slave Flip-Flop
Data
Out
Clock
Clock
Flip-Flop
Figure 1. Memory Cell Flip-Flops
Data or Clock In
50Ω
Dummy Gate
Reference
Figure 2. AC-Coupled, Self-Biased Logic Input
Many 10-Gbps inputs are self-biased and 50-Ω terminated, for capacitance coupling. The outputs are DC-
coupled to drive 50-Ω ground terminated lines.
DATA SHEETS
This document contains data sheets for the KGL4201, KGL4202, GHDD4411, and GHDD4414 10-Gbps
GaAs High-Speed Optical Communication Systems.
Data sheets for other communication devices may be obtained from the Oki Semiconductor WEB site,
www.okisemi.com or from the local sales office.
2
Oki Semiconductor
KGL4201
10-GHz 8:1 Multiplexer
GENERAL DESCRIPTION
Oki’s KGL4201 is a 10-GHz 8:1 multiplexer designed to operate in 10-Gbps communication links. This
circuit synchronously merges eight 1.25-Gbps data streams, clocked at low frequency rates into a single
10-Gbps stream, clocked at the higher frequency. In the KGL4201 multiplexer, the 10-GHz master clock is
first divided by two, then by four. The lower frequency components are first multiplexed by four, then
the two groups are merged into a single data stream using the master 10-Gbps clock. Complementary
1/8 synchronous clock outputs are made available from the KGL4201 for use in synchronizing lower fre-
quency logic.
All signal interfaces are 50-Ω with direct DC coupling on the 1.25-Gbps data inputs and phase-locked
1.25-Gbps clock outputs. The 10-Gbps data output and 10-GHz clock input are AC-capacitively-coupled
for ease of interfacing at microwave speeds and reducing ground noise induced phase jitter. All package
clock and data pins are separated by either ground or supply voltage pins to control the I/O impedance,
maintain signal isolation and reduce phase noise.
The KGL4201 is shipped in a 40-pin ceramic flat-package with impedance-controlling ground plane and
flush mounting bottom heat sink.
FEATURES
• AC-coupled 10 Gbps I/O: eliminates DC
coupled phase jitter
• Isolated I/O pins: minimize noise and
impedance variation
• 1/8 clock generated on chip: easy to
synchronize downstream logic
• Packaged in 40-pin ceramic flat-package with
ground plane and heat sink.
• 2 V, 2.4 W
Oki Semiconductor
3
■ KGL4201 ■ –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
PIN CONFIGURATION
14.84 SQ
13.01 SQ
10.67 SQ
0.7 ±0.05
0.9 ±.005
1.7 ±0.15
40
31
1
30
2 ±0.3
21
10
20
11
0.4 ±0.05
1.27
0.125 ±0.05
Pin Configuration
Pin
1
Name
Pin
Pin Name
Pin
21
22
23
24
25
26
Pin Name
VDD
GND
GND
CK
Pin
31
32
33
34
35
36
37
38
39
40
Pin Name
GND
VDD
D7
GND
Q
11
12
13
14
15
16
17
18
19
20
GND
VDD
D0
2
3
GND
Q
4
GND
D2
GND
D5
5
GND
GND
1/8CK
GND
1/8CK
VB
GND
GND
RCK
6
D4
D3
7
GND
D6
27
28
29
GND
D1
8
GND
GND
GND
9
GND
GND
VB
10
30
VDD
BLOCK DIAGRAM
D0
D2
D4
D6
4:1 MUX
Q
Q
2:1
MUX
Output
Latch
D1
D3
D5
D7
4:1 MUX
1/8CK
1/8CK
1/2
Divider
1/4 Divider
CK
4
Oki Semiconductor
––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ KGL4201 ■
ELECTRICAL CHARACTERISTICS
RECOMMENDED OPERATING CONDITIONS
Rated Value
Parameter
Power supply voltage for internal logic
Power supply voltage for output buffer
Operating temperature range at package base
Symbol
Min
1.9
1.9
0
Typ
2.0
2.0
–
Max
2.1
2.1
70
Unit
V
VDD
VB
V
TS
°C
DC CHARACTERISTICS
VDD = 2V ±±0.Vꢀ VB=2V ±±0.V Ts = ± to ꢁ±7C
Rated Value
Parameter
Power dissipation
Symbol
Test Condition
Min0
–
Typ0
Max0
3.0
1.3
0.3
1.2
0.9
1.3
0.3
Unit
P
2.4
W
V
High-level 1/8 CK output voltage
Low-level 1/8 CK output voltage
Data output voltage swing
Clock input voltage swing
High-level data input voltage
Low-level data input voltage
VOH
VOL
VOD
VCK
VIDH
VIDL
0.85
0
V
50-Ω load
0.7
0.5
0.8
0
VP-P
VP-P
V
Capacitive coupling
V
AC CHARACTERISTICS
VDD = 2V ±±0.Vꢀ VB=2V ±±0.V Ts = ± to ꢁ±7C
Rated Value
Parameter
Minimum clock period
Setup time (Data to 1/8 CK ↓)
Hold time (1/8 CK ↓ to Data)
CK-D[7:0] phase margin
Rise time (Q, Q)
Symbol
Test Condition
Min0
–
Typ0
–
Max0
100
Unit
ps
∆tC
tPS
tDH
∆tM
tR
450
-400
550
20
500
-350
650
30
550
ps
-300
ps
Input clock period is 100 ps
ps
40
40
ps
Fall time (Q, Q)
tF
20
30
ps
Oki Semiconductor
5
■ KGL4201 ■ –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
INTERFACE TIMING
CK
D0
D1
A1
B1
C1
D1
E1
F1
A2
B2
C2
D2
E2
F2
A3
B3
C3
D3
E3
F3
A4
B4
C4
D4
E4
F4
D2
D3
D4
D5
D6
G1
H1
G2
H2
G3
H3
G4
H4
D7
Q
A1 B1 C1 D1 E1 F1 G1 H1 A2 B2 C2 D2 E2 F2 G2 H2 A3 B3 C3
A1 B1 C1 D1 E1 F1 G1 H1 A2 B2 C2 D2 E2 F2 G2 H2 A3 B3 C3
Q
1/8 CK
1/8 CK
6
Oki Semiconductor
KGL4202
10-GHz 1:8 Demultiplexer
GENERAL DESCRIPTION
Oki’s KGL4202 is a 10-GHz 1:8 demultiplexer designed to operate in 10-Gbps communication links. This
circuit synchronously separates a single 10-Gbps data stream, clocked at up to 10 GHz, into eight lower
frequency data streams, clocked at lower frequency rates. In the KGL4202 demultiplexer, the 10-GHz
master clock is first divided by two, then by four. The 10-Gbps data stream is first divided into two syn-
chronous serial paths, then these two data streams are separated into four each lower speed data streams
and brought out to data latched outputs. Complementary 1/8 synchronous clock outputs are made avail-
able from the KGL4202 for use in synchronizing lower frequency logic.
All signal interfaces are 50 Ω with all inputs internally terminated in 50 Ω. Direct DC coupling is used on
the 10-Gbps data input, the 1.25-Gbps data outputs and phase-locked 1.25-Gbps clock outputs. The 10-
GHz clock input is AC-capacitively-coupled for ease of interfacing at microwave speeds and reducing
ground noise induced phase jitter. The package 10-GHz clock and 10-Gbps data pins are separated by
ground pins to control the I/O impedance, maintain signal isolation and reduce phase noise. The eight
data outputs are distributed to opposite sides of the package to facilitate hardware layout and reduce
noise. Over one third of the chip power is due to the ten 50-Ω outputs.
The KGL4202 is shipped in a 40-pin ceramic flat-package with impedance-controlling ground plane and
flush-mounting bottom heat sink.
FEATURES
• AC-coupled 10 Gbps I/O: eliminates DC
coupled phase jitter
• Isolated I/O pins: minimizes noise and
impedance variation
• 1/8 clock generated on chip: easy to
synchronize downstream logic
• 2 V, 3.2 W
• Packaged in 40-pin ceramic flat-package with
ground plane and heat sink
Oki Semiconductor
7
■ KGL4202 ■ –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
PIN CONFIGURATION
14.84 SQ
13.01 SQ
10.67 SQ
0.7 ±0.05
0.9 ±.005
1.7 ±0.15
40
31
1
30
2 ±0.3
21
10
11
20
1.27
0.4 ±0.05
0.125 ±0.05
Pin Configuration
Pin
1
Name
GND
1/8CK
GND
1/8CK
RD
Pin
Pin Name
GND
VDD
Q1
Pin
21
22
23
24
25
26
27
28
29
30
Pin Name
Pin
31
32
33
34
35
36
37
38
39
40
Pin Name
GND
VDD
Q6
11
12
13
14
15
16
17
18
19
20
VDD
GND
GND
CKIN
GND
GND
RCK
GND
GND
VB
2
3
4
GND
Q3
GND
Q4
5
6
GND
N.C.
Q5
Q2
7
GND
Q7
GND
Q0
8
GND
GND
VB
9
VB
VB
10
GND
VDD
BLOCK DIAGRAM
Q0
Q2
Q4
Q6
1:4 DEMUX
1:2
DEMUX
D
Q1
Q3
Q5
Q7
1:4 DEMUX
1/8CK
1/8CK
1/8CK
1/8CK
CK
1/2 Divider
1/4 Divider
8
Oki Semiconductor
––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ KGL4202 ■
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Rated Value
Parameter
Supply voltage for internal logic
Symbol
Min0
-0.3
-0.3
-0.3
-0.3
-45
Max0
2.3
Unit
V
VDD
VB
CK
D
Supply voltage for output buffer
Clock input
2.3
V
1.5
V
Data inputs
1.5
V
Temperature at package base under bias
Storage temperature
TS
100
125
°C
°C
TST
-45
RECOMMENDED OPERATING CONDITIONS
Rated Value
Parameter
Power supply voltage for internal logic
Power supply voltage for output buffer
Operating temperature range at package base
Symbol
Min0
Typ0
2.0
2.0
–
Max0
Unit
V
VDD
VB
1.9
1.9
0
2.1
2.1
70
V
TS
°C
DC CHARACTERISTICS
VDD = 2 V ±±0. Vꢀ VB=2 V ±±0. V TS = ± to ꢁ±7C
Rated Value
Parameter
Symbol
Test Condition
Min0
Typ0
Max0
4.0
Unit
Power dissipation
P
3.2
W
V
High-level 1/8CK output voltage
Low-level 1/8CK output voltage
Data input voltage swing
Clock input voltage swing
VOH
VOL
VID
VICK
50-Ω load
0.85
0
1.3
50-Ω load
0.3
V
Capacitive coupling
Capacitive coupling
0.5
0.5
0.9
VP-P
VP-P
0.9
AC CHARACTERISTICS
VDD = 2V ±±0.Vꢀ VB=2V ±±0.V Ts = ± to ꢁ±7C
Rated Value
Typ0
Parameter
Minimum clock period
Setup time (D to CK ↓)
Hold time (CK ↓ to D)
CK-D phase margin
Symbol
Test Condition
Min0
Max0
100
-35
Unit
ps
∆tC
tDS
-55
70
-45
80
ps
tDH
90
ps
∆tM
tC8Q
Input clock period is 100 ps
50
65
ps
1/8CK ↑ to valid data delay
-40
-10
20
ps
Oki Semiconductor
9
■ KGL4202 ■ –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
INTERFACE TIMING
CK
D
Q0
A1 B1 C1 D1 E1 F1 G1 H1 A2 B2 C2 D2 E2 F2 G2 H2 A3 B3 C3 D3 E3 F3 G3 H3 A4 B4 C4 D4
A1
B1
C1
D1
E1
F1
A2
B2
C2
D2
E2
F2
A3
B3
C3
D3
E3
F3
Q1
Q2
Q3
Q4
Q5
Q6
G1
H1
G2
H2
G3
H3
Q7
1/8 CK
1/8 CK
TIMING
∆t
C
CK
∆t
M
t
t
DH
DS
D
1/8 CK
1/8 CK
Q[7:0]
t
C8Q
Valid
Valid
10
Oki Semiconductor
GHDD4411
EX-OR Circuit
GENERAL DESCRIPTION
Oki’s GHDD4411 is a 10-GHz exclusive-OR/NOR circuit designed to function in 10-Gbps high-speed
communication serial bit streams. The EX-OR must operate from both rising and falling edges at an
equivalent speed of 20-Gbps non-return-to-zero (NRZ) signal to extract a 10-Gbps clock from a 10-Gbps
signal. Using closely matched Gilbert cell circuitry, this device operates at over 10 Gbps using DCFL and
SBFL logic from inverted HEMT technology. Internal input 50-Ω terminations and a self-referencing bias
voltage allow capacitive coupling, simplifying interconnections.
The GHDD4411 EX-OR circuit is high-speed in a 28-pin ceramic flat package with impedance-controlling
ground plane and flush-mounting bottom heat sink.
FEATURES
• EX-OR and EX-NOR: outputs optimized for
performance
• Packaged in 28-pin ceramic flat package with
ground plane and heat sink
• 1.5 V, 0.6 W: lowest power with 50-Ω interfaces
Oki Semiconductor
11
■ GHDD4411 ■ ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
PIN CONFIGURATION
6 ±0.1
16 ±0.1
2
2.1 ±0.1
0.5
12
9.6
8
0.5
0.5
28
20
1
5
19
15
6
14
1.27
0.3
0.125
10.16
Dimensions in mm
15
Pin
1
Signal
IN1BS
Function
Pin
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Signal
Function
Power supply (buffer)
No Connect
Input 1 bias input
No Connect
VB
2
N.C.
N.C.
3
IN1RF
N.C.
Input 1 bias reference output
No Connect
IN2RF
N.C.
IN2BS
GND
IN2
Input 2 bias reference output
No Connect
4
5
VB
Power supply (buffer)
Ground
Input 2 bias input
Ground
6
GND
EXOR
GND
N.C.
7
EX-OR output
Ground
Data input 2
8
GND
VD
Ground
9
No Connect
Power supply (logic circuit)
No Connect
10
11
12
13
14
N.C.
No Connect
N.C.
VD
N.C.
No Connect
Power supply (logic circuit)
Ground
GND
EXNOR
GND
Ground
GND
IN1
EX-NOR output
Ground
Data input 1
GND
Ground
12
Oki Semiconductor
––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ GHDD4411 ■
BLOCK DIAGRAM
IN1
RF
IN1
EXNOR
EXOR
IN1
BS
IN2
IN2
BS
IN2
RF
Oki Semiconductor
13
■ GHDD4411 ■ ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Suuply voltage for internal logic
Symbol
Min
-0.3
-0.3
-0.3
-0.3
-45
Max
2.3
Unit
V
VDD
VB
CK
D
Supply voltage for outpu buffer
Clock input
2.3
V
1.0
V
Data input
1.0
V
Temperature at package base under bias
Storage temperature
TS
100
125
°C
°C
TST
-45
Recommended Operating Conditions
Parameter
Suuply voltage for internal logic
Symbol
Min0
Typ0
1.5
Max0
1.6
Unit
VDD
VB
1.4
1.4
0
V
V
Supply voltage for output buffer
1.5
1.6
Operating temperature range at package base
TS
70
°C
V
= 1.5 V ±0.1, V = 1.5 V ± 0.1, T = 0 to 70 °C
DD
B
S
Parameter
Symbol
Condition
Min0
Typ0
Max0
Unit
Power dissipation
Input bit rate
P
0.6
10
W
B
Gb/s
VP-P
VP-P
ps
Data input voltage amplitude
Data output voltage amplitude
Data output rise/fall time
VID
VOD
τ
Capacitive coupling
0.2
0.8
50-Ω load,
Capacitive coupling
0.7
20
OUTPUT WAVEFORM
I63A-7, DEC12,5-7, 25C, P
Horizontal - 20ps/Div, Vertical - 200 mV/div
14
Oki Semiconductor
GHDD4414
Decision Circuit with Phase Detectors
GENERAL DESCRIPTION
Oki’s GHDD4414 is a 10-GHz decision circuit designed to strip data from high-speed serial bit streams in
10-Gbps communication links. Using a clock input at up to 10 GHz and using D-flip-flops, EX-ORs, and
phase detectors, this circuit separates a 10-Gbps data stream into: clock output, data output, “phase”
variation output, and data density output.
A 10-GHz master clock drives two D-flip-flops in this circuit. Buffered input data is clocked through the
first flip-flop, then the second, “data out” is taken from the first flip-flop. The data input buffer is com-
posed of a series of inverters to delay the signal and obtain a small decision ambiguity. A phase compar-
ison is made of the buffered data and data from flip-flop one; a second phase comparison is made of the
output of flip-flops one and two. The phase detectors are modified EX-OR circuits with resistor summing
of the logic gates to permit analog measurement of their outputs. Any change in the timing relationships
between the clock and data is seen at the output of the first phase detector. The second flip-flop operates
as a 1-bit shift register with fixed 360-deg phase shift. The second phase detector output depends only
upon the transition density (speed of rise and fall transitions) of the input data signal.
All signal interfaces are 50-Ω with all inputs internally terminated in 50 Ω. The 10-GHz clock and data
inputs are AC capacitively-coupled for ease of interfacing at microwave speeds and reducing ground
noise induced phase jitter. Data and phase outputs are DC-coupled.
FEATURES
• Phase detectors on chip: verifies data integrity
• Isolated 10-Gbps input pins: minimizes noise
and impedance variation
• 28-pin ceramic flat package with impedance
controlling ground plane and flush mount heat
sink
• 1.5 V, 1 W: lowest power with 50-Ω interfaces
Oki Semiconductor
15
■ GHDD4414 ■ ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
PIN CONFIGURATION
6 ±0.1
16 ±0.1
2
2.1 ±0.1
0.5
12
9.6
8
0.5
0.5
28
20
1
5
19
15
6
14
1.27
0.3
0.125
10.16
Dimensions in mm
15
Pin
1
Signal
CBS
Function
Pin
Signal
Function
Clock bias input
15 VB
16 P1
17 P2
18 P3
19 VD
Power supply (buffer)
2
NC
Phase detector output
3
CMB
NC
Clock output duty monitor
Powr supply (buffer)
Data output
Phase detector ref. output 1
Phase detector ref. output 2
Power supply (logic circuit)
4
5
VB
6
GND
DOUT
GND
NC
20 GND
21 DIN
22 GND
23 DBS
24 DRF
25 VD
7
Data input
8
9
Data bias input
10 NC
Data bias reference output
Power supply (logic circuit)
11 NC
12 GND
13 COUT
14 GND
26 GND
27 CK
Clock output
Clock input
28 GND
16
Oki Semiconductor
––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ GHDD4414 ■
BLOCK DIAGRAM
D
OUT
Phase Detector
PD
PD
PD
P
P
P
1
2
3
D
D
Q
D
Q
D
BS
D
RF
LPF
C
C
MB
CK
OUT
C
BS
APPLICATION BLOCK DIAGRAM
Pin-PD &
PreAmp
Decision
Circuit
Fiber Input
AGC Amp
Out
Clock
Phase
Shifter
Limiting
Amp
Rectifier
Filter
Delay
Oki Semiconductor
17
■ GHDD4414 ■ ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
ELECTRICAL CHARACTERISTICS
V
= 1.5 V ±0.1 V, V = 1.5 V ±0.1 V, T = 0° to 70°C
B S
DD
Parameter
Symbol
P
Condition
Min0
Max0
1
Unit
W
Power dissipation
Decision ambiguity
VIDEC
∆ θ
10 Gbps
0.05
VP-P
PRBS: 215 -1
Phase margin
250
degree
VP-P
Data input voltage amplitude
Clock input voltage amplitude
Data output voltage amplitude
VID
Capacitive coupling
0.8
0.8
VIC
0.4
0.7
0.7
40
VP-P
VOD
VOC
DTYC
τCD
50Ω load
capacitive coupling
VP-P
Clock output voltage amplitude
Clock output duty cycle
Clock to data delay
VP-P
60
45
%
25
ps
Phase detection sensitivity
∆ V θ
10 Gbps
0.28
mV/degree
PRBS: 215 -1
Phase Detection Characteristics (D Amplitude = 0.7-V
)
IN
P-P
CIN Delay (ps)
P. (V)
0.350
0.383
0.424
P2 (V)
0.343
0.340
0.342
P3 (V)
0.443
0.443
0.443
Comments
Maximum delay for ER <10-10
+29
0
Center of phase margin
-29
Minimum delay for ER <10-10
PHASE DETECTOR CIRCUIT
Input 1
Output
Input 2
18
Oki Semiconductor
––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ GHDD4414 ■
PHASE DETECTION BETWEEN SIGNAL AND CLOCK AT 10 Gbps
400
P1[mV]
P2[mV]
P3[mV]
350
300
250
200
Error Free Range
0
-270
-180
-90
90
180
270
Phase Variation (degree)
TIMING
Data
Clock
200mV/div
25ps/div
Oki Semiconductor
19
■ GHDD4414 ■ ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
20
Oki Semiconductor
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相关型号：
KGL4201C
Multiplexer, 4000/14000/40000 Series, 1-Func, 8 Line Input, 1 Line Output, Complementary Output, PQFP40, QFP-40
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